1/* 2 Copyright (c) 2002, Thomas Kurschel 3 4 5 Part of Radeon driver 6 7 2D registers 8*/ 9 10 11#ifndef _2D_REGS_H 12#define _2D_REGS_H 13 14#define RADEON_DP_BRUSH_BKGD_CLR 0x1478 15#define RADEON_DP_BRUSH_FRGD_CLR 0x147c 16#define RADEON_DP_CNTL 0x16c0 17# define RADEON_DST_X_LEFT_TO_RIGHT (1 << 0) 18# define RADEON_DST_Y_TOP_TO_BOTTOM (1 << 1) 19#define RADEON_DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0 20# define RADEON_DST_Y_MAJOR (1 << 2) 21# define RADEON_DST_Y_DIR_TOP_TO_BOTTOM (1 << 15) 22# define RADEON_DST_X_DIR_LEFT_TO_RIGHT (1 << 31) 23#define RADEON_DP_DATATYPE 0x16c4 24# define RADEON_HOST_BIG_ENDIAN_EN (1 << 29) 25#define RADEON_DP_GUI_MASTER_CNTL 0x146c 26# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) 27# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) 28# define RADEON_GMC_SRC_CLIPPING (1 << 2) 29# define RADEON_GMC_DST_CLIPPING (1 << 3) 30# define RADEON_GMC_BRUSH_DATATYPE_MASK (0x0f << 4) 31# define RADEON_GMC_BRUSH_8X8_MONO_FG_BG (0 << 4) 32# define RADEON_GMC_BRUSH_8X8_MONO_FG_LA (1 << 4) 33# define RADEON_GMC_BRUSH_1X8_MONO_FG_BG (4 << 4) 34# define RADEON_GMC_BRUSH_1X8_MONO_FG_LA (5 << 4) 35# define RADEON_GMC_BRUSH_32x1_MONO_FG_BG (6 << 4) 36# define RADEON_GMC_BRUSH_32x1_MONO_FG_LA (7 << 4) 37# define RADEON_GMC_BRUSH_32x32_MONO_FG_BG (8 << 4) 38# define RADEON_GMC_BRUSH_32x32_MONO_FG_LA (9 << 4) 39# define RADEON_GMC_BRUSH_8x8_COLOR (10 << 4) 40# define RADEON_GMC_BRUSH_1X8_COLOR (12 << 4) 41# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) 42# define RADEON_GMC_BRUSH_NONE (15 << 4) 43# define RADEON_GMC_DST_8BPP_CI (2 << 8) 44# define RADEON_GMC_DST_15BPP (3 << 8) 45# define RADEON_GMC_DST_16BPP (4 << 8) 46# define RADEON_GMC_DST_24BPP (5 << 8) 47# define RADEON_GMC_DST_32BPP (6 << 8) 48# define RADEON_GMC_DST_8BPP_RGB (7 << 8) 49# define RADEON_GMC_DST_Y8 (8 << 8) 50# define RADEON_GMC_DST_RGB8 (9 << 8) 51# define RADEON_GMC_DST_VYUY (11 << 8) 52# define RADEON_GMC_DST_YVYU (12 << 8) 53# define RADEON_GMC_DST_AYUV444 (14 << 8) 54# define RADEON_GMC_DST_ARGB4444 (15 << 8) 55# define RADEON_GMC_DST_DATATYPE_MASK (0x0f << 8) 56# define RADEON_GMC_DST_DATATYPE_SHIFT 8 57# define RADEON_GMC_SRC_DATATYPE_MASK (3 << 12) 58# define RADEON_GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12) 59# define RADEON_GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12) 60# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) 61# define RADEON_GMC_BYTE_PIX_ORDER (1 << 14) 62# define RADEON_GMC_BYTE_MSB_TO_LSB (0 << 14) 63# define RADEON_GMC_BYTE_LSB_TO_MSB (1 << 14) 64# define RADEON_GMC_CONVERSION_TEMP (1 << 15) 65# define RADEON_GMC_CONVERSION_TEMP_6500 (0 << 15) 66# define RADEON_GMC_CONVERSION_TEMP_9300 (1 << 15) 67# define RADEON_GMC_ROP3_MASK (0xff << 16) 68# define RADEON_DP_SRC_SOURCE_MASK (7 << 24) 69# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) 70# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) 71# define RADEON_GMC_3D_FCN_EN (1 << 27) 72# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) 73# define RADEON_GMC_AUX_CLIP_DIS (1 << 29) 74# define RADEON_GMC_WR_MSK_DIS (1 << 30) 75# define RADEON_GMC_LD_BRUSH_Y_X (1 << 31) 76# define RADEON_ROP3_ZERO 0x00000000 77# define RADEON_ROP3_DSa 0x00880000 78# define RADEON_ROP3_SDna 0x00440000 79# define RADEON_ROP3_S 0x00cc0000 80# define RADEON_ROP3_DSna 0x00220000 81# define RADEON_ROP3_D 0x00aa0000 82# define RADEON_ROP3_DSx 0x00660000 83# define RADEON_ROP3_DSo 0x00ee0000 84# define RADEON_ROP3_DSon 0x00110000 85# define RADEON_ROP3_DSxn 0x00990000 86# define RADEON_ROP3_Dn 0x00550000 87# define RADEON_ROP3_SDno 0x00dd0000 88# define RADEON_ROP3_Sn 0x00330000 89# define RADEON_ROP3_DSno 0x00bb0000 90# define RADEON_ROP3_DSan 0x00770000 91# define RADEON_ROP3_ONE 0x00ff0000 92# define RADEON_ROP3_DPa 0x00a00000 93# define RADEON_ROP3_PDna 0x00500000 94# define RADEON_ROP3_P 0x00f00000 95# define RADEON_ROP3_DPna 0x000a0000 96# define RADEON_ROP3_D 0x00aa0000 97# define RADEON_ROP3_DPx 0x005a0000 98# define RADEON_ROP3_DPo 0x00fa0000 99# define RADEON_ROP3_DPon 0x00050000 100# define RADEON_ROP3_PDxn 0x00a50000 101# define RADEON_ROP3_PDno 0x00f50000 102# define RADEON_ROP3_Pn 0x000f0000 103# define RADEON_ROP3_DPno 0x00af0000 104# define RADEON_ROP3_DPan 0x005f0000 105 106#define RADEON_DP_GUI_MASTER_CNTL_C 0x1c84 107#define RADEON_DP_MIX 0x16c8 108#define RADEON_DP_SRC_BKGD_CLR 0x15dc 109#define RADEON_DP_SRC_FRGD_CLR 0x15d8 110#define RADEON_DP_WRITE_MASK 0x16cc 111 112#define RADEON_BRUSH_SCALE 0x1470 113#define RADEON_BRUSH_Y_X 0x1474 114#define RADEON_BRUSH_DATA0 0x1480 115#define RADEON_BRUSH_DATA1 0x1484 116#define RADEON_BRUSH_DATA2 0x1488 117#define RADEON_BRUSH_DATA3 0x148c 118#define RADEON_BRUSH_DATA4 0x1490 119#define RADEON_BRUSH_DATA5 0x1494 120#define RADEON_BRUSH_DATA6 0x1498 121#define RADEON_BRUSH_DATA7 0x149c 122#define RADEON_BRUSH_DATA8 0x14a0 123#define RADEON_BRUSH_DATA9 0x14a4 124#define RADEON_BRUSH_DATA10 0x14a8 125#define RADEON_BRUSH_DATA11 0x14ac 126#define RADEON_BRUSH_DATA12 0x14b0 127#define RADEON_BRUSH_DATA13 0x14b4 128#define RADEON_BRUSH_DATA14 0x14b8 129#define RADEON_BRUSH_DATA15 0x14bc 130#define RADEON_BRUSH_DATA16 0x14c0 131#define RADEON_BRUSH_DATA17 0x14c4 132#define RADEON_BRUSH_DATA18 0x14c8 133#define RADEON_BRUSH_DATA19 0x14cc 134#define RADEON_BRUSH_DATA20 0x14d0 135#define RADEON_BRUSH_DATA21 0x14d4 136#define RADEON_BRUSH_DATA22 0x14d8 137#define RADEON_BRUSH_DATA23 0x14dc 138#define RADEON_BRUSH_DATA24 0x14e0 139#define RADEON_BRUSH_DATA25 0x14e4 140#define RADEON_BRUSH_DATA26 0x14e8 141#define RADEON_BRUSH_DATA27 0x14ec 142#define RADEON_BRUSH_DATA28 0x14f0 143#define RADEON_BRUSH_DATA29 0x14f4 144#define RADEON_BRUSH_DATA30 0x14f8 145#define RADEON_BRUSH_DATA31 0x14fc 146#define RADEON_BRUSH_DATA32 0x1500 147#define RADEON_BRUSH_DATA33 0x1504 148#define RADEON_BRUSH_DATA34 0x1508 149#define RADEON_BRUSH_DATA35 0x150c 150#define RADEON_BRUSH_DATA36 0x1510 151#define RADEON_BRUSH_DATA37 0x1514 152#define RADEON_BRUSH_DATA38 0x1518 153#define RADEON_BRUSH_DATA39 0x151c 154#define RADEON_BRUSH_DATA40 0x1520 155#define RADEON_BRUSH_DATA41 0x1524 156#define RADEON_BRUSH_DATA42 0x1528 157#define RADEON_BRUSH_DATA43 0x152c 158#define RADEON_BRUSH_DATA44 0x1530 159#define RADEON_BRUSH_DATA45 0x1534 160#define RADEON_BRUSH_DATA46 0x1538 161#define RADEON_BRUSH_DATA47 0x153c 162#define RADEON_BRUSH_DATA48 0x1540 163#define RADEON_BRUSH_DATA49 0x1544 164#define RADEON_BRUSH_DATA50 0x1548 165#define RADEON_BRUSH_DATA51 0x154c 166#define RADEON_BRUSH_DATA52 0x1550 167#define RADEON_BRUSH_DATA53 0x1554 168#define RADEON_BRUSH_DATA54 0x1558 169#define RADEON_BRUSH_DATA55 0x155c 170#define RADEON_BRUSH_DATA56 0x1560 171#define RADEON_BRUSH_DATA57 0x1564 172#define RADEON_BRUSH_DATA58 0x1568 173#define RADEON_BRUSH_DATA59 0x156c 174#define RADEON_BRUSH_DATA60 0x1570 175#define RADEON_BRUSH_DATA61 0x1574 176#define RADEON_BRUSH_DATA62 0x1578 177#define RADEON_BRUSH_DATA63 0x157c 178 179#define RADEON_DEFAULT_SC_BOTTOM_RIGHT 0x16e8 180# define RADEON_DEFAULT_SC_RIGHT_MAX (0x1fff << 0) 181# define RADEON_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) 182 183#define RADEON_DST_LINE_START 0x1600 184#define RADEON_DST_LINE_END 0x1604 185#define RADEON_DST_LINE_PATCOUNT 0x1608 186# define RADEON_BRES_CNTL_SHIFT 8 187#define RADEON_DEFAULT_OFFSET 0x16e0 188#define RADEON_DEFAULT_PITCH 0x16e4 189 190#define RADEON_SRC_PITCH_OFFSET 0x1428 191#define RADEON_DST_PITCH_OFFSET 0x142c 192 193 194#endif 195