1/* Target-dependent code for the Fujitsu FR-V, for GDB, the GNU Debugger. 2 Copyright 2002, 2003, 2004 Free Software Foundation, Inc. 3 4 This file is part of GDB. 5 6 This program is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 2 of the License, or 9 (at your option) any later version. 10 11 This program is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program; if not, write to the Free Software 18 Foundation, Inc., 59 Temple Place - Suite 330, 19 Boston, MA 02111-1307, USA. */ 20 21#include "defs.h" 22#include "gdb_string.h" 23#include "inferior.h" 24#include "gdbcore.h" 25#include "arch-utils.h" 26#include "regcache.h" 27#include "frame.h" 28#include "frame-unwind.h" 29#include "frame-base.h" 30#include "trad-frame.h" 31#include "dis-asm.h" 32#include "gdb_assert.h" 33#include "sim-regno.h" 34#include "gdb/sim-frv.h" 35#include "opcodes/frv-desc.h" /* for the H_SPR_... enums */ 36#include "symtab.h" 37#include "elf-bfd.h" 38#include "elf/frv.h" 39#include "osabi.h" 40#include "infcall.h" 41#include "frv-tdep.h" 42 43extern void _initialize_frv_tdep (void); 44 45static gdbarch_init_ftype frv_gdbarch_init; 46 47static gdbarch_register_name_ftype frv_register_name; 48static gdbarch_breakpoint_from_pc_ftype frv_breakpoint_from_pc; 49static gdbarch_adjust_breakpoint_address_ftype frv_gdbarch_adjust_breakpoint_address; 50static gdbarch_skip_prologue_ftype frv_skip_prologue; 51 52 53struct frv_unwind_cache /* was struct frame_extra_info */ 54 { 55 /* The previous frame's inner-most stack address. Used as this 56 frame ID's stack_addr. */ 57 CORE_ADDR prev_sp; 58 59 /* The frame's base, optionally used by the high-level debug info. */ 60 CORE_ADDR base; 61 62 /* Table indicating the location of each and every register. */ 63 struct trad_frame_saved_reg *saved_regs; 64 }; 65 66/* A structure describing a particular variant of the FRV. 67 We allocate and initialize one of these structures when we create 68 the gdbarch object for a variant. 69 70 At the moment, all the FR variants we support differ only in which 71 registers are present; the portable code of GDB knows that 72 registers whose names are the empty string don't exist, so the 73 `register_names' array captures all the per-variant information we 74 need. 75 76 in the future, if we need to have per-variant maps for raw size, 77 virtual type, etc., we should replace register_names with an array 78 of structures, each of which gives all the necessary info for one 79 register. Don't stick parallel arrays in here --- that's so 80 Fortran. */ 81struct gdbarch_tdep 82{ 83 /* Which ABI is in use? */ 84 enum frv_abi frv_abi; 85 86 /* How many general-purpose registers does this variant have? */ 87 int num_gprs; 88 89 /* How many floating-point registers does this variant have? */ 90 int num_fprs; 91 92 /* How many hardware watchpoints can it support? */ 93 int num_hw_watchpoints; 94 95 /* How many hardware breakpoints can it support? */ 96 int num_hw_breakpoints; 97 98 /* Register names. */ 99 char **register_names; 100}; 101 102#define CURRENT_VARIANT (gdbarch_tdep (current_gdbarch)) 103 104/* Return the FR-V ABI associated with GDBARCH. */ 105enum frv_abi 106frv_abi (struct gdbarch *gdbarch) 107{ 108 return gdbarch_tdep (gdbarch)->frv_abi; 109} 110 111/* Fetch the interpreter and executable loadmap addresses (for shared 112 library support) for the FDPIC ABI. Return 0 if successful, -1 if 113 not. (E.g, -1 will be returned if the ABI isn't the FDPIC ABI.) */ 114int 115frv_fdpic_loadmap_addresses (struct gdbarch *gdbarch, CORE_ADDR *interp_addr, 116 CORE_ADDR *exec_addr) 117{ 118 if (frv_abi (gdbarch) != FRV_ABI_FDPIC) 119 return -1; 120 else 121 { 122 if (interp_addr != NULL) 123 { 124 ULONGEST val; 125 regcache_cooked_read_unsigned (current_regcache, 126 fdpic_loadmap_interp_regnum, &val); 127 *interp_addr = val; 128 } 129 if (exec_addr != NULL) 130 { 131 ULONGEST val; 132 regcache_cooked_read_unsigned (current_regcache, 133 fdpic_loadmap_exec_regnum, &val); 134 *exec_addr = val; 135 } 136 return 0; 137 } 138} 139 140/* Allocate a new variant structure, and set up default values for all 141 the fields. */ 142static struct gdbarch_tdep * 143new_variant (void) 144{ 145 struct gdbarch_tdep *var; 146 int r; 147 char buf[20]; 148 149 var = xmalloc (sizeof (*var)); 150 memset (var, 0, sizeof (*var)); 151 152 var->frv_abi = FRV_ABI_EABI; 153 var->num_gprs = 64; 154 var->num_fprs = 64; 155 var->num_hw_watchpoints = 0; 156 var->num_hw_breakpoints = 0; 157 158 /* By default, don't supply any general-purpose or floating-point 159 register names. */ 160 var->register_names 161 = (char **) xmalloc ((frv_num_regs + frv_num_pseudo_regs) 162 * sizeof (char *)); 163 for (r = 0; r < frv_num_regs + frv_num_pseudo_regs; r++) 164 var->register_names[r] = ""; 165 166 /* Do, however, supply default names for the known special-purpose 167 registers. */ 168 169 var->register_names[pc_regnum] = "pc"; 170 var->register_names[lr_regnum] = "lr"; 171 var->register_names[lcr_regnum] = "lcr"; 172 173 var->register_names[psr_regnum] = "psr"; 174 var->register_names[ccr_regnum] = "ccr"; 175 var->register_names[cccr_regnum] = "cccr"; 176 var->register_names[tbr_regnum] = "tbr"; 177 178 /* Debug registers. */ 179 var->register_names[brr_regnum] = "brr"; 180 var->register_names[dbar0_regnum] = "dbar0"; 181 var->register_names[dbar1_regnum] = "dbar1"; 182 var->register_names[dbar2_regnum] = "dbar2"; 183 var->register_names[dbar3_regnum] = "dbar3"; 184 185 /* iacc0 (Only found on MB93405.) */ 186 var->register_names[iacc0h_regnum] = "iacc0h"; 187 var->register_names[iacc0l_regnum] = "iacc0l"; 188 var->register_names[iacc0_regnum] = "iacc0"; 189 190 /* fsr0 (Found on FR555 and FR501.) */ 191 var->register_names[fsr0_regnum] = "fsr0"; 192 193 /* acc0 - acc7. The architecture provides for the possibility of many 194 more (up to 64 total), but we don't want to make that big of a hole 195 in the G packet. If we need more in the future, we'll add them 196 elsewhere. */ 197 for (r = acc0_regnum; r <= acc7_regnum; r++) 198 { 199 char *buf; 200 buf = xstrprintf ("acc%d", r - acc0_regnum); 201 var->register_names[r] = buf; 202 } 203 204 /* accg0 - accg7: These are one byte registers. The remote protocol 205 provides the raw values packed four into a slot. accg0123 and 206 accg4567 correspond to accg0 - accg3 and accg4-accg7 respectively. 207 We don't provide names for accg0123 and accg4567 since the user will 208 likely not want to see these raw values. */ 209 210 for (r = accg0_regnum; r <= accg7_regnum; r++) 211 { 212 char *buf; 213 buf = xstrprintf ("accg%d", r - accg0_regnum); 214 var->register_names[r] = buf; 215 } 216 217 /* msr0 and msr1. */ 218 219 var->register_names[msr0_regnum] = "msr0"; 220 var->register_names[msr1_regnum] = "msr1"; 221 222 /* gner and fner registers. */ 223 var->register_names[gner0_regnum] = "gner0"; 224 var->register_names[gner1_regnum] = "gner1"; 225 var->register_names[fner0_regnum] = "fner0"; 226 var->register_names[fner1_regnum] = "fner1"; 227 228 return var; 229} 230 231 232/* Indicate that the variant VAR has NUM_GPRS general-purpose 233 registers, and fill in the names array appropriately. */ 234static void 235set_variant_num_gprs (struct gdbarch_tdep *var, int num_gprs) 236{ 237 int r; 238 239 var->num_gprs = num_gprs; 240 241 for (r = 0; r < num_gprs; ++r) 242 { 243 char buf[20]; 244 245 sprintf (buf, "gr%d", r); 246 var->register_names[first_gpr_regnum + r] = xstrdup (buf); 247 } 248} 249 250 251/* Indicate that the variant VAR has NUM_FPRS floating-point 252 registers, and fill in the names array appropriately. */ 253static void 254set_variant_num_fprs (struct gdbarch_tdep *var, int num_fprs) 255{ 256 int r; 257 258 var->num_fprs = num_fprs; 259 260 for (r = 0; r < num_fprs; ++r) 261 { 262 char buf[20]; 263 264 sprintf (buf, "fr%d", r); 265 var->register_names[first_fpr_regnum + r] = xstrdup (buf); 266 } 267} 268 269static void 270set_variant_abi_fdpic (struct gdbarch_tdep *var) 271{ 272 var->frv_abi = FRV_ABI_FDPIC; 273 var->register_names[fdpic_loadmap_exec_regnum] = xstrdup ("loadmap_exec"); 274 var->register_names[fdpic_loadmap_interp_regnum] = xstrdup ("loadmap_interp"); 275} 276 277static void 278set_variant_scratch_registers (struct gdbarch_tdep *var) 279{ 280 var->register_names[scr0_regnum] = xstrdup ("scr0"); 281 var->register_names[scr1_regnum] = xstrdup ("scr1"); 282 var->register_names[scr2_regnum] = xstrdup ("scr2"); 283 var->register_names[scr3_regnum] = xstrdup ("scr3"); 284} 285 286static const char * 287frv_register_name (int reg) 288{ 289 if (reg < 0) 290 return "?toosmall?"; 291 if (reg >= frv_num_regs + frv_num_pseudo_regs) 292 return "?toolarge?"; 293 294 return CURRENT_VARIANT->register_names[reg]; 295} 296 297 298static struct type * 299frv_register_type (struct gdbarch *gdbarch, int reg) 300{ 301 if (reg >= first_fpr_regnum && reg <= last_fpr_regnum) 302 return builtin_type_float; 303 else if (reg == iacc0_regnum) 304 return builtin_type_int64; 305 else 306 return builtin_type_int32; 307} 308 309static void 310frv_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, 311 int reg, void *buffer) 312{ 313 if (reg == iacc0_regnum) 314 { 315 regcache_raw_read (regcache, iacc0h_regnum, buffer); 316 regcache_raw_read (regcache, iacc0l_regnum, (bfd_byte *) buffer + 4); 317 } 318 else if (accg0_regnum <= reg && reg <= accg7_regnum) 319 { 320 /* The accg raw registers have four values in each slot with the 321 lowest register number occupying the first byte. */ 322 323 int raw_regnum = accg0123_regnum + (reg - accg0_regnum) / 4; 324 int byte_num = (reg - accg0_regnum) % 4; 325 bfd_byte buf[4]; 326 327 regcache_raw_read (regcache, raw_regnum, buf); 328 memset (buffer, 0, 4); 329 /* FR-V is big endian, so put the requested byte in the first byte 330 of the buffer allocated to hold the pseudo-register. */ 331 ((bfd_byte *) buffer)[0] = buf[byte_num]; 332 } 333} 334 335static void 336frv_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, 337 int reg, const void *buffer) 338{ 339 if (reg == iacc0_regnum) 340 { 341 regcache_raw_write (regcache, iacc0h_regnum, buffer); 342 regcache_raw_write (regcache, iacc0l_regnum, (bfd_byte *) buffer + 4); 343 } 344 else if (accg0_regnum <= reg && reg <= accg7_regnum) 345 { 346 /* The accg raw registers have four values in each slot with the 347 lowest register number occupying the first byte. */ 348 349 int raw_regnum = accg0123_regnum + (reg - accg0_regnum) / 4; 350 int byte_num = (reg - accg0_regnum) % 4; 351 char buf[4]; 352 353 regcache_raw_read (regcache, raw_regnum, buf); 354 buf[byte_num] = ((bfd_byte *) buffer)[0]; 355 regcache_raw_write (regcache, raw_regnum, buf); 356 } 357} 358 359static int 360frv_register_sim_regno (int reg) 361{ 362 static const int spr_map[] = 363 { 364 H_SPR_PSR, /* psr_regnum */ 365 H_SPR_CCR, /* ccr_regnum */ 366 H_SPR_CCCR, /* cccr_regnum */ 367 -1, /* fdpic_loadmap_exec_regnum */ 368 -1, /* fdpic_loadmap_interp_regnum */ 369 -1, /* 134 */ 370 H_SPR_TBR, /* tbr_regnum */ 371 H_SPR_BRR, /* brr_regnum */ 372 H_SPR_DBAR0, /* dbar0_regnum */ 373 H_SPR_DBAR1, /* dbar1_regnum */ 374 H_SPR_DBAR2, /* dbar2_regnum */ 375 H_SPR_DBAR3, /* dbar3_regnum */ 376 H_SPR_SCR0, /* scr0_regnum */ 377 H_SPR_SCR1, /* scr1_regnum */ 378 H_SPR_SCR2, /* scr2_regnum */ 379 H_SPR_SCR3, /* scr3_regnum */ 380 H_SPR_LR, /* lr_regnum */ 381 H_SPR_LCR, /* lcr_regnum */ 382 H_SPR_IACC0H, /* iacc0h_regnum */ 383 H_SPR_IACC0L, /* iacc0l_regnum */ 384 H_SPR_FSR0, /* fsr0_regnum */ 385 /* FIXME: Add infrastructure for fetching/setting ACC and ACCG regs. */ 386 -1, /* acc0_regnum */ 387 -1, /* acc1_regnum */ 388 -1, /* acc2_regnum */ 389 -1, /* acc3_regnum */ 390 -1, /* acc4_regnum */ 391 -1, /* acc5_regnum */ 392 -1, /* acc6_regnum */ 393 -1, /* acc7_regnum */ 394 -1, /* acc0123_regnum */ 395 -1, /* acc4567_regnum */ 396 H_SPR_MSR0, /* msr0_regnum */ 397 H_SPR_MSR1, /* msr1_regnum */ 398 H_SPR_GNER0, /* gner0_regnum */ 399 H_SPR_GNER1, /* gner1_regnum */ 400 H_SPR_FNER0, /* fner0_regnum */ 401 H_SPR_FNER1, /* fner1_regnum */ 402 }; 403 404 gdb_assert (reg >= 0 && reg < NUM_REGS); 405 406 if (first_gpr_regnum <= reg && reg <= last_gpr_regnum) 407 return reg - first_gpr_regnum + SIM_FRV_GR0_REGNUM; 408 else if (first_fpr_regnum <= reg && reg <= last_fpr_regnum) 409 return reg - first_fpr_regnum + SIM_FRV_FR0_REGNUM; 410 else if (pc_regnum == reg) 411 return SIM_FRV_PC_REGNUM; 412 else if (reg >= first_spr_regnum 413 && reg < first_spr_regnum + sizeof (spr_map) / sizeof (spr_map[0])) 414 { 415 int spr_reg_offset = spr_map[reg - first_spr_regnum]; 416 417 if (spr_reg_offset < 0) 418 return SIM_REGNO_DOES_NOT_EXIST; 419 else 420 return SIM_FRV_SPR0_REGNUM + spr_reg_offset; 421 } 422 423 internal_error (__FILE__, __LINE__, "Bad register number %d", reg); 424} 425 426static const unsigned char * 427frv_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenp) 428{ 429 static unsigned char breakpoint[] = {0xc0, 0x70, 0x00, 0x01}; 430 *lenp = sizeof (breakpoint); 431 return breakpoint; 432} 433 434/* Define the maximum number of instructions which may be packed into a 435 bundle (VLIW instruction). */ 436static const int max_instrs_per_bundle = 8; 437 438/* Define the size (in bytes) of an FR-V instruction. */ 439static const int frv_instr_size = 4; 440 441/* Adjust a breakpoint's address to account for the FR-V architecture's 442 constraint that a break instruction must not appear as any but the 443 first instruction in the bundle. */ 444static CORE_ADDR 445frv_gdbarch_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr) 446{ 447 int count = max_instrs_per_bundle; 448 CORE_ADDR addr = bpaddr - frv_instr_size; 449 CORE_ADDR func_start = get_pc_function_start (bpaddr); 450 451 /* Find the end of the previous packing sequence. This will be indicated 452 by either attempting to access some inaccessible memory or by finding 453 an instruction word whose packing bit is set to one. */ 454 while (count-- > 0 && addr >= func_start) 455 { 456 char instr[frv_instr_size]; 457 int status; 458 459 status = deprecated_read_memory_nobpt (addr, instr, sizeof instr); 460 461 if (status != 0) 462 break; 463 464 /* This is a big endian architecture, so byte zero will have most 465 significant byte. The most significant bit of this byte is the 466 packing bit. */ 467 if (instr[0] & 0x80) 468 break; 469 470 addr -= frv_instr_size; 471 } 472 473 if (count > 0) 474 bpaddr = addr + frv_instr_size; 475 476 return bpaddr; 477} 478 479 480/* Return true if REG is a caller-saves ("scratch") register, 481 false otherwise. */ 482static int 483is_caller_saves_reg (int reg) 484{ 485 return ((4 <= reg && reg <= 7) 486 || (14 <= reg && reg <= 15) 487 || (32 <= reg && reg <= 47)); 488} 489 490 491/* Return true if REG is a callee-saves register, false otherwise. */ 492static int 493is_callee_saves_reg (int reg) 494{ 495 return ((16 <= reg && reg <= 31) 496 || (48 <= reg && reg <= 63)); 497} 498 499 500/* Return true if REG is an argument register, false otherwise. */ 501static int 502is_argument_reg (int reg) 503{ 504 return (8 <= reg && reg <= 13); 505} 506 507/* Scan an FR-V prologue, starting at PC, until frame->PC. 508 If FRAME is non-zero, fill in its saved_regs with appropriate addresses. 509 We assume FRAME's saved_regs array has already been allocated and cleared. 510 Return the first PC value after the prologue. 511 512 Note that, for unoptimized code, we almost don't need this function 513 at all; all arguments and locals live on the stack, so we just need 514 the FP to find everything. The catch: structures passed by value 515 have their addresses living in registers; they're never spilled to 516 the stack. So if you ever want to be able to get to these 517 arguments in any frame but the top, you'll need to do this serious 518 prologue analysis. */ 519static CORE_ADDR 520frv_analyze_prologue (CORE_ADDR pc, struct frame_info *next_frame, 521 struct frv_unwind_cache *info) 522{ 523 /* When writing out instruction bitpatterns, we use the following 524 letters to label instruction fields: 525 P - The parallel bit. We don't use this. 526 J - The register number of GRj in the instruction description. 527 K - The register number of GRk in the instruction description. 528 I - The register number of GRi. 529 S - a signed imediate offset. 530 U - an unsigned immediate offset. 531 532 The dots below the numbers indicate where hex digit boundaries 533 fall, to make it easier to check the numbers. */ 534 535 /* Non-zero iff we've seen the instruction that initializes the 536 frame pointer for this function's frame. */ 537 int fp_set = 0; 538 539 /* If fp_set is non_zero, then this is the distance from 540 the stack pointer to frame pointer: fp = sp + fp_offset. */ 541 int fp_offset = 0; 542 543 /* Total size of frame prior to any alloca operations. */ 544 int framesize = 0; 545 546 /* Flag indicating if lr has been saved on the stack. */ 547 int lr_saved_on_stack = 0; 548 549 /* The number of the general-purpose register we saved the return 550 address ("link register") in, or -1 if we haven't moved it yet. */ 551 int lr_save_reg = -1; 552 553 /* Offset (from sp) at which lr has been saved on the stack. */ 554 555 int lr_sp_offset = 0; 556 557 /* If gr_saved[i] is non-zero, then we've noticed that general 558 register i has been saved at gr_sp_offset[i] from the stack 559 pointer. */ 560 char gr_saved[64]; 561 int gr_sp_offset[64]; 562 563 /* The address of the most recently scanned prologue instruction. */ 564 CORE_ADDR last_prologue_pc; 565 566 /* The address of the next instruction. */ 567 CORE_ADDR next_pc; 568 569 /* The upper bound to of the pc values to scan. */ 570 CORE_ADDR lim_pc; 571 572 memset (gr_saved, 0, sizeof (gr_saved)); 573 574 last_prologue_pc = pc; 575 576 /* Try to compute an upper limit (on how far to scan) based on the 577 line number info. */ 578 lim_pc = skip_prologue_using_sal (pc); 579 /* If there's no line number info, lim_pc will be 0. In that case, 580 set the limit to be 100 instructions away from pc. Hopefully, this 581 will be far enough away to account for the entire prologue. Don't 582 worry about overshooting the end of the function. The scan loop 583 below contains some checks to avoid scanning unreasonably far. */ 584 if (lim_pc == 0) 585 lim_pc = pc + 400; 586 587 /* If we have a frame, we don't want to scan past the frame's pc. This 588 will catch those cases where the pc is in the prologue. */ 589 if (next_frame) 590 { 591 CORE_ADDR frame_pc = frame_pc_unwind (next_frame); 592 if (frame_pc < lim_pc) 593 lim_pc = frame_pc; 594 } 595 596 /* Scan the prologue. */ 597 while (pc < lim_pc) 598 { 599 char buf[frv_instr_size]; 600 LONGEST op; 601 602 if (target_read_memory (pc, buf, sizeof buf) != 0) 603 break; 604 op = extract_signed_integer (buf, sizeof buf); 605 606 next_pc = pc + 4; 607 608 /* The tests in this chain of ifs should be in order of 609 decreasing selectivity, so that more particular patterns get 610 to fire before less particular patterns. */ 611 612 /* Some sort of control transfer instruction: stop scanning prologue. 613 Integer Conditional Branch: 614 X XXXX XX 0000110 XX XXXXXXXXXXXXXXXX 615 Floating-point / media Conditional Branch: 616 X XXXX XX 0000111 XX XXXXXXXXXXXXXXXX 617 LCR Conditional Branch to LR 618 X XXXX XX 0001110 XX XX 001 X XXXXXXXXXX 619 Integer conditional Branches to LR 620 X XXXX XX 0001110 XX XX 010 X XXXXXXXXXX 621 X XXXX XX 0001110 XX XX 011 X XXXXXXXXXX 622 Floating-point/Media Branches to LR 623 X XXXX XX 0001110 XX XX 110 X XXXXXXXXXX 624 X XXXX XX 0001110 XX XX 111 X XXXXXXXXXX 625 Jump and Link 626 X XXXXX X 0001100 XXXXXX XXXXXX XXXXXX 627 X XXXXX X 0001101 XXXXXX XXXXXX XXXXXX 628 Call 629 X XXXXXX 0001111 XXXXXXXXXXXXXXXXXX 630 Return from Trap 631 X XXXXX X 0000101 XXXXXX XXXXXX XXXXXX 632 Integer Conditional Trap 633 X XXXX XX 0000100 XXXXXX XXXX 00 XXXXXX 634 X XXXX XX 0011100 XXXXXX XXXXXXXXXXXX 635 Floating-point /media Conditional Trap 636 X XXXX XX 0000100 XXXXXX XXXX 01 XXXXXX 637 X XXXX XX 0011101 XXXXXX XXXXXXXXXXXX 638 Break 639 X XXXX XX 0000100 XXXXXX XXXX 11 XXXXXX 640 Media Trap 641 X XXXX XX 0000100 XXXXXX XXXX 10 XXXXXX */ 642 if ((op & 0x01d80000) == 0x00180000 /* Conditional branches and Call */ 643 || (op & 0x01f80000) == 0x00300000 /* Jump and Link */ 644 || (op & 0x01f80000) == 0x00100000 /* Return from Trap, Trap */ 645 || (op & 0x01f80000) == 0x00700000) /* Trap immediate */ 646 { 647 /* Stop scanning; not in prologue any longer. */ 648 break; 649 } 650 651 /* Loading something from memory into fp probably means that 652 we're in the epilogue. Stop scanning the prologue. 653 ld @(GRi, GRk), fp 654 X 000010 0000010 XXXXXX 000100 XXXXXX 655 ldi @(GRi, d12), fp 656 X 000010 0110010 XXXXXX XXXXXXXXXXXX */ 657 else if ((op & 0x7ffc0fc0) == 0x04080100 658 || (op & 0x7ffc0000) == 0x04c80000) 659 { 660 break; 661 } 662 663 /* Setting the FP from the SP: 664 ori sp, 0, fp 665 P 000010 0100010 000001 000000000000 = 0x04881000 666 0 111111 1111111 111111 111111111111 = 0x7fffffff 667 . . . . . . . . 668 We treat this as part of the prologue. */ 669 else if ((op & 0x7fffffff) == 0x04881000) 670 { 671 fp_set = 1; 672 fp_offset = 0; 673 last_prologue_pc = next_pc; 674 } 675 676 /* Move the link register to the scratch register grJ, before saving: 677 movsg lr, grJ 678 P 000100 0000011 010000 000111 JJJJJJ = 0x080d01c0 679 0 111111 1111111 111111 111111 000000 = 0x7fffffc0 680 . . . . . . . . 681 We treat this as part of the prologue. */ 682 else if ((op & 0x7fffffc0) == 0x080d01c0) 683 { 684 int gr_j = op & 0x3f; 685 686 /* If we're moving it to a scratch register, that's fine. */ 687 if (is_caller_saves_reg (gr_j)) 688 { 689 lr_save_reg = gr_j; 690 last_prologue_pc = next_pc; 691 } 692 } 693 694 /* To save multiple callee-saves registers on the stack, at 695 offset zero: 696 697 std grK,@(sp,gr0) 698 P KKKKKK 0000011 000001 000011 000000 = 0x000c10c0 699 0 000000 1111111 111111 111111 111111 = 0x01ffffff 700 701 stq grK,@(sp,gr0) 702 P KKKKKK 0000011 000001 000100 000000 = 0x000c1100 703 0 000000 1111111 111111 111111 111111 = 0x01ffffff 704 . . . . . . . . 705 We treat this as part of the prologue, and record the register's 706 saved address in the frame structure. */ 707 else if ((op & 0x01ffffff) == 0x000c10c0 708 || (op & 0x01ffffff) == 0x000c1100) 709 { 710 int gr_k = ((op >> 25) & 0x3f); 711 int ope = ((op >> 6) & 0x3f); 712 int count; 713 int i; 714 715 /* Is it an std or an stq? */ 716 if (ope == 0x03) 717 count = 2; 718 else 719 count = 4; 720 721 /* Is it really a callee-saves register? */ 722 if (is_callee_saves_reg (gr_k)) 723 { 724 for (i = 0; i < count; i++) 725 { 726 gr_saved[gr_k + i] = 1; 727 gr_sp_offset[gr_k + i] = 4 * i; 728 } 729 last_prologue_pc = next_pc; 730 } 731 } 732 733 /* Adjusting the stack pointer. (The stack pointer is GR1.) 734 addi sp, S, sp 735 P 000001 0010000 000001 SSSSSSSSSSSS = 0x02401000 736 0 111111 1111111 111111 000000000000 = 0x7ffff000 737 . . . . . . . . 738 We treat this as part of the prologue. */ 739 else if ((op & 0x7ffff000) == 0x02401000) 740 { 741 if (framesize == 0) 742 { 743 /* Sign-extend the twelve-bit field. 744 (Isn't there a better way to do this?) */ 745 int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800; 746 747 framesize -= s; 748 last_prologue_pc = pc; 749 } 750 else 751 { 752 /* If the prologue is being adjusted again, we've 753 likely gone too far; i.e. we're probably in the 754 epilogue. */ 755 break; 756 } 757 } 758 759 /* Setting the FP to a constant distance from the SP: 760 addi sp, S, fp 761 P 000010 0010000 000001 SSSSSSSSSSSS = 0x04401000 762 0 111111 1111111 111111 000000000000 = 0x7ffff000 763 . . . . . . . . 764 We treat this as part of the prologue. */ 765 else if ((op & 0x7ffff000) == 0x04401000) 766 { 767 /* Sign-extend the twelve-bit field. 768 (Isn't there a better way to do this?) */ 769 int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800; 770 fp_set = 1; 771 fp_offset = s; 772 last_prologue_pc = pc; 773 } 774 775 /* To spill an argument register to a scratch register: 776 ori GRi, 0, GRk 777 P KKKKKK 0100010 IIIIII 000000000000 = 0x00880000 778 0 000000 1111111 000000 111111111111 = 0x01fc0fff 779 . . . . . . . . 780 For the time being, we treat this as a prologue instruction, 781 assuming that GRi is an argument register. This one's kind 782 of suspicious, because it seems like it could be part of a 783 legitimate body instruction. But we only come here when the 784 source info wasn't helpful, so we have to do the best we can. 785 Hopefully once GCC and GDB agree on how to emit line number 786 info for prologues, then this code will never come into play. */ 787 else if ((op & 0x01fc0fff) == 0x00880000) 788 { 789 int gr_i = ((op >> 12) & 0x3f); 790 791 /* Make sure that the source is an arg register; if it is, we'll 792 treat it as a prologue instruction. */ 793 if (is_argument_reg (gr_i)) 794 last_prologue_pc = next_pc; 795 } 796 797 /* To spill 16-bit values to the stack: 798 sthi GRk, @(fp, s) 799 P KKKKKK 1010001 000010 SSSSSSSSSSSS = 0x01442000 800 0 000000 1111111 111111 000000000000 = 0x01fff000 801 . . . . . . . . 802 And for 8-bit values, we use STB instructions. 803 stbi GRk, @(fp, s) 804 P KKKKKK 1010000 000010 SSSSSSSSSSSS = 0x01402000 805 0 000000 1111111 111111 000000000000 = 0x01fff000 806 . . . . . . . . 807 We check that GRk is really an argument register, and treat 808 all such as part of the prologue. */ 809 else if ( (op & 0x01fff000) == 0x01442000 810 || (op & 0x01fff000) == 0x01402000) 811 { 812 int gr_k = ((op >> 25) & 0x3f); 813 814 /* Make sure that GRk is really an argument register; treat 815 it as a prologue instruction if so. */ 816 if (is_argument_reg (gr_k)) 817 last_prologue_pc = next_pc; 818 } 819 820 /* To save multiple callee-saves register on the stack, at a 821 non-zero offset: 822 823 stdi GRk, @(sp, s) 824 P KKKKKK 1010011 000001 SSSSSSSSSSSS = 0x014c1000 825 0 000000 1111111 111111 000000000000 = 0x01fff000 826 . . . . . . . . 827 stqi GRk, @(sp, s) 828 P KKKKKK 1010100 000001 SSSSSSSSSSSS = 0x01501000 829 0 000000 1111111 111111 000000000000 = 0x01fff000 830 . . . . . . . . 831 We treat this as part of the prologue, and record the register's 832 saved address in the frame structure. */ 833 else if ((op & 0x01fff000) == 0x014c1000 834 || (op & 0x01fff000) == 0x01501000) 835 { 836 int gr_k = ((op >> 25) & 0x3f); 837 int count; 838 int i; 839 840 /* Is it a stdi or a stqi? */ 841 if ((op & 0x01fff000) == 0x014c1000) 842 count = 2; 843 else 844 count = 4; 845 846 /* Is it really a callee-saves register? */ 847 if (is_callee_saves_reg (gr_k)) 848 { 849 /* Sign-extend the twelve-bit field. 850 (Isn't there a better way to do this?) */ 851 int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800; 852 853 for (i = 0; i < count; i++) 854 { 855 gr_saved[gr_k + i] = 1; 856 gr_sp_offset[gr_k + i] = s + (4 * i); 857 } 858 last_prologue_pc = next_pc; 859 } 860 } 861 862 /* Storing any kind of integer register at any constant offset 863 from any other register. 864 865 st GRk, @(GRi, gr0) 866 P KKKKKK 0000011 IIIIII 000010 000000 = 0x000c0080 867 0 000000 1111111 000000 111111 111111 = 0x01fc0fff 868 . . . . . . . . 869 sti GRk, @(GRi, d12) 870 P KKKKKK 1010010 IIIIII SSSSSSSSSSSS = 0x01480000 871 0 000000 1111111 000000 000000000000 = 0x01fc0000 872 . . . . . . . . 873 These could be almost anything, but a lot of prologue 874 instructions fall into this pattern, so let's decode the 875 instruction once, and then work at a higher level. */ 876 else if (((op & 0x01fc0fff) == 0x000c0080) 877 || ((op & 0x01fc0000) == 0x01480000)) 878 { 879 int gr_k = ((op >> 25) & 0x3f); 880 int gr_i = ((op >> 12) & 0x3f); 881 int offset; 882 883 /* Are we storing with gr0 as an offset, or using an 884 immediate value? */ 885 if ((op & 0x01fc0fff) == 0x000c0080) 886 offset = 0; 887 else 888 offset = (((op & 0xfff) - 0x800) & 0xfff) - 0x800; 889 890 /* If the address isn't relative to the SP or FP, it's not a 891 prologue instruction. */ 892 if (gr_i != sp_regnum && gr_i != fp_regnum) 893 { 894 /* Do nothing; not a prologue instruction. */ 895 } 896 897 /* Saving the old FP in the new frame (relative to the SP). */ 898 else if (gr_k == fp_regnum && gr_i == sp_regnum) 899 { 900 gr_saved[fp_regnum] = 1; 901 gr_sp_offset[fp_regnum] = offset; 902 last_prologue_pc = next_pc; 903 } 904 905 /* Saving callee-saves register(s) on the stack, relative to 906 the SP. */ 907 else if (gr_i == sp_regnum 908 && is_callee_saves_reg (gr_k)) 909 { 910 gr_saved[gr_k] = 1; 911 if (gr_i == sp_regnum) 912 gr_sp_offset[gr_k] = offset; 913 else 914 gr_sp_offset[gr_k] = offset + fp_offset; 915 last_prologue_pc = next_pc; 916 } 917 918 /* Saving the scratch register holding the return address. */ 919 else if (lr_save_reg != -1 920 && gr_k == lr_save_reg) 921 { 922 lr_saved_on_stack = 1; 923 if (gr_i == sp_regnum) 924 lr_sp_offset = offset; 925 else 926 lr_sp_offset = offset + fp_offset; 927 last_prologue_pc = next_pc; 928 } 929 930 /* Spilling int-sized arguments to the stack. */ 931 else if (is_argument_reg (gr_k)) 932 last_prologue_pc = next_pc; 933 } 934 pc = next_pc; 935 } 936 937 if (next_frame && info) 938 { 939 int i; 940 ULONGEST this_base; 941 942 /* If we know the relationship between the stack and frame 943 pointers, record the addresses of the registers we noticed. 944 Note that we have to do this as a separate step at the end, 945 because instructions may save relative to the SP, but we need 946 their addresses relative to the FP. */ 947 if (fp_set) 948 frame_unwind_unsigned_register (next_frame, fp_regnum, &this_base); 949 else 950 frame_unwind_unsigned_register (next_frame, sp_regnum, &this_base); 951 952 for (i = 0; i < 64; i++) 953 if (gr_saved[i]) 954 info->saved_regs[i].addr = this_base - fp_offset + gr_sp_offset[i]; 955 956 info->prev_sp = this_base - fp_offset + framesize; 957 info->base = this_base; 958 959 /* If LR was saved on the stack, record its location. */ 960 if (lr_saved_on_stack) 961 info->saved_regs[lr_regnum].addr = this_base - fp_offset + lr_sp_offset; 962 963 /* The call instruction moves the caller's PC in the callee's LR. 964 Since this is an unwind, do the reverse. Copy the location of LR 965 into PC (the address / regnum) so that a request for PC will be 966 converted into a request for the LR. */ 967 info->saved_regs[pc_regnum] = info->saved_regs[lr_regnum]; 968 969 /* Save the previous frame's computed SP value. */ 970 trad_frame_set_value (info->saved_regs, sp_regnum, info->prev_sp); 971 } 972 973 return last_prologue_pc; 974} 975 976 977static CORE_ADDR 978frv_skip_prologue (CORE_ADDR pc) 979{ 980 CORE_ADDR func_addr, func_end, new_pc; 981 982 new_pc = pc; 983 984 /* If the line table has entry for a line *within* the function 985 (i.e., not in the prologue, and not past the end), then that's 986 our location. */ 987 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) 988 { 989 struct symtab_and_line sal; 990 991 sal = find_pc_line (func_addr, 0); 992 993 if (sal.line != 0 && sal.end < func_end) 994 { 995 new_pc = sal.end; 996 } 997 } 998 999 /* The FR-V prologue is at least five instructions long (twenty bytes). 1000 If we didn't find a real source location past that, then 1001 do a full analysis of the prologue. */ 1002 if (new_pc < pc + 20) 1003 new_pc = frv_analyze_prologue (pc, 0, 0); 1004 1005 return new_pc; 1006} 1007 1008 1009static struct frv_unwind_cache * 1010frv_frame_unwind_cache (struct frame_info *next_frame, 1011 void **this_prologue_cache) 1012{ 1013 struct gdbarch *gdbarch = get_frame_arch (next_frame); 1014 CORE_ADDR pc; 1015 ULONGEST this_base; 1016 struct frv_unwind_cache *info; 1017 1018 if ((*this_prologue_cache)) 1019 return (*this_prologue_cache); 1020 1021 info = FRAME_OBSTACK_ZALLOC (struct frv_unwind_cache); 1022 (*this_prologue_cache) = info; 1023 info->saved_regs = trad_frame_alloc_saved_regs (next_frame); 1024 1025 /* Prologue analysis does the rest... */ 1026 frv_analyze_prologue (frame_func_unwind (next_frame), next_frame, info); 1027 1028 return info; 1029} 1030 1031static void 1032frv_extract_return_value (struct type *type, struct regcache *regcache, 1033 void *valbuf) 1034{ 1035 int len = TYPE_LENGTH (type); 1036 1037 if (len <= 4) 1038 { 1039 ULONGEST gpr8_val; 1040 regcache_cooked_read_unsigned (regcache, 8, &gpr8_val); 1041 store_unsigned_integer (valbuf, len, gpr8_val); 1042 } 1043 else if (len == 8) 1044 { 1045 ULONGEST regval; 1046 regcache_cooked_read_unsigned (regcache, 8, ®val); 1047 store_unsigned_integer (valbuf, 4, regval); 1048 regcache_cooked_read_unsigned (regcache, 9, ®val); 1049 store_unsigned_integer ((bfd_byte *) valbuf + 4, 4, regval); 1050 } 1051 else 1052 internal_error (__FILE__, __LINE__, "Illegal return value length: %d", len); 1053} 1054 1055static CORE_ADDR 1056frv_extract_struct_value_address (struct regcache *regcache) 1057{ 1058 ULONGEST addr; 1059 regcache_cooked_read_unsigned (regcache, struct_return_regnum, &addr); 1060 return addr; 1061} 1062 1063static void 1064frv_store_struct_return (CORE_ADDR addr, CORE_ADDR sp) 1065{ 1066 write_register (struct_return_regnum, addr); 1067} 1068 1069static CORE_ADDR 1070frv_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) 1071{ 1072 /* Require dword alignment. */ 1073 return align_down (sp, 8); 1074} 1075 1076static CORE_ADDR 1077find_func_descr (struct gdbarch *gdbarch, CORE_ADDR entry_point) 1078{ 1079 CORE_ADDR descr; 1080 char valbuf[4]; 1081 1082 descr = frv_fdpic_find_canonical_descriptor (entry_point); 1083 1084 if (descr != 0) 1085 return descr; 1086 1087 /* Construct a non-canonical descriptor from space allocated on 1088 the stack. */ 1089 1090 descr = value_as_long (value_allocate_space_in_inferior (8)); 1091 store_unsigned_integer (valbuf, 4, entry_point); 1092 write_memory (descr, valbuf, 4); 1093 store_unsigned_integer (valbuf, 4, 1094 frv_fdpic_find_global_pointer (entry_point)); 1095 write_memory (descr + 4, valbuf, 4); 1096 return descr; 1097} 1098 1099static CORE_ADDR 1100frv_convert_from_func_ptr_addr (struct gdbarch *gdbarch, CORE_ADDR addr, 1101 struct target_ops *targ) 1102{ 1103 CORE_ADDR entry_point; 1104 CORE_ADDR got_address; 1105 1106 entry_point = get_target_memory_unsigned (targ, addr, 4); 1107 got_address = get_target_memory_unsigned (targ, addr + 4, 4); 1108 1109 if (got_address == frv_fdpic_find_global_pointer (entry_point)) 1110 return entry_point; 1111 else 1112 return addr; 1113} 1114 1115static CORE_ADDR 1116frv_push_dummy_call (struct gdbarch *gdbarch, struct value *function, 1117 struct regcache *regcache, CORE_ADDR bp_addr, 1118 int nargs, struct value **args, CORE_ADDR sp, 1119 int struct_return, CORE_ADDR struct_addr) 1120{ 1121 int argreg; 1122 int argnum; 1123 char *val; 1124 char valbuf[4]; 1125 struct value *arg; 1126 struct type *arg_type; 1127 int len; 1128 enum type_code typecode; 1129 CORE_ADDR regval; 1130 int stack_space; 1131 int stack_offset; 1132 enum frv_abi abi = frv_abi (gdbarch); 1133 CORE_ADDR func_addr = find_function_addr (function, NULL); 1134 1135#if 0 1136 printf("Push %d args at sp = %x, struct_return=%d (%x)\n", 1137 nargs, (int) sp, struct_return, struct_addr); 1138#endif 1139 1140 stack_space = 0; 1141 for (argnum = 0; argnum < nargs; ++argnum) 1142 stack_space += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), 4); 1143 1144 stack_space -= (6 * 4); 1145 if (stack_space > 0) 1146 sp -= stack_space; 1147 1148 /* Make sure stack is dword aligned. */ 1149 sp = align_down (sp, 8); 1150 1151 stack_offset = 0; 1152 1153 argreg = 8; 1154 1155 if (struct_return) 1156 regcache_cooked_write_unsigned (regcache, struct_return_regnum, 1157 struct_addr); 1158 1159 for (argnum = 0; argnum < nargs; ++argnum) 1160 { 1161 arg = args[argnum]; 1162 arg_type = check_typedef (VALUE_TYPE (arg)); 1163 len = TYPE_LENGTH (arg_type); 1164 typecode = TYPE_CODE (arg_type); 1165 1166 if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) 1167 { 1168 store_unsigned_integer (valbuf, 4, VALUE_ADDRESS (arg)); 1169 typecode = TYPE_CODE_PTR; 1170 len = 4; 1171 val = valbuf; 1172 } 1173 else if (abi == FRV_ABI_FDPIC 1174 && len == 4 1175 && typecode == TYPE_CODE_PTR 1176 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type)) == TYPE_CODE_FUNC) 1177 { 1178 /* The FDPIC ABI requires function descriptors to be passed instead 1179 of entry points. */ 1180 store_unsigned_integer 1181 (valbuf, 4, 1182 find_func_descr (gdbarch, 1183 extract_unsigned_integer (VALUE_CONTENTS (arg), 1184 4))); 1185 typecode = TYPE_CODE_PTR; 1186 len = 4; 1187 val = valbuf; 1188 } 1189 else 1190 { 1191 val = (char *) VALUE_CONTENTS (arg); 1192 } 1193 1194 while (len > 0) 1195 { 1196 int partial_len = (len < 4 ? len : 4); 1197 1198 if (argreg < 14) 1199 { 1200 regval = extract_unsigned_integer (val, partial_len); 1201#if 0 1202 printf(" Argnum %d data %x -> reg %d\n", 1203 argnum, (int) regval, argreg); 1204#endif 1205 regcache_cooked_write_unsigned (regcache, argreg, regval); 1206 ++argreg; 1207 } 1208 else 1209 { 1210#if 0 1211 printf(" Argnum %d data %x -> offset %d (%x)\n", 1212 argnum, *((int *)val), stack_offset, (int) (sp + stack_offset)); 1213#endif 1214 write_memory (sp + stack_offset, val, partial_len); 1215 stack_offset += align_up (partial_len, 4); 1216 } 1217 len -= partial_len; 1218 val += partial_len; 1219 } 1220 } 1221 1222 /* Set the return address. For the frv, the return breakpoint is 1223 always at BP_ADDR. */ 1224 regcache_cooked_write_unsigned (regcache, lr_regnum, bp_addr); 1225 1226 if (abi == FRV_ABI_FDPIC) 1227 { 1228 /* Set the GOT register for the FDPIC ABI. */ 1229 regcache_cooked_write_unsigned 1230 (regcache, first_gpr_regnum + 15, 1231 frv_fdpic_find_global_pointer (func_addr)); 1232 } 1233 1234 /* Finally, update the SP register. */ 1235 regcache_cooked_write_unsigned (regcache, sp_regnum, sp); 1236 1237 return sp; 1238} 1239 1240static void 1241frv_store_return_value (struct type *type, struct regcache *regcache, 1242 const void *valbuf) 1243{ 1244 int len = TYPE_LENGTH (type); 1245 1246 if (len <= 4) 1247 { 1248 bfd_byte val[4]; 1249 memset (val, 0, sizeof (val)); 1250 memcpy (val + (4 - len), valbuf, len); 1251 regcache_cooked_write (regcache, 8, val); 1252 } 1253 else if (len == 8) 1254 { 1255 regcache_cooked_write (regcache, 8, valbuf); 1256 regcache_cooked_write (regcache, 9, (bfd_byte *) valbuf + 4); 1257 } 1258 else 1259 internal_error (__FILE__, __LINE__, 1260 "Don't know how to return a %d-byte value.", len); 1261} 1262 1263 1264/* Hardware watchpoint / breakpoint support for the FR500 1265 and FR400. */ 1266 1267int 1268frv_check_watch_resources (int type, int cnt, int ot) 1269{ 1270 struct gdbarch_tdep *var = CURRENT_VARIANT; 1271 1272 /* Watchpoints not supported on simulator. */ 1273 if (strcmp (target_shortname, "sim") == 0) 1274 return 0; 1275 1276 if (type == bp_hardware_breakpoint) 1277 { 1278 if (var->num_hw_breakpoints == 0) 1279 return 0; 1280 else if (cnt <= var->num_hw_breakpoints) 1281 return 1; 1282 } 1283 else 1284 { 1285 if (var->num_hw_watchpoints == 0) 1286 return 0; 1287 else if (ot) 1288 return -1; 1289 else if (cnt <= var->num_hw_watchpoints) 1290 return 1; 1291 } 1292 return -1; 1293} 1294 1295 1296int 1297frv_stopped_data_address (CORE_ADDR *addr_p) 1298{ 1299 CORE_ADDR brr, dbar0, dbar1, dbar2, dbar3; 1300 1301 brr = read_register (brr_regnum); 1302 dbar0 = read_register (dbar0_regnum); 1303 dbar1 = read_register (dbar1_regnum); 1304 dbar2 = read_register (dbar2_regnum); 1305 dbar3 = read_register (dbar3_regnum); 1306 1307 if (brr & (1<<11)) 1308 *addr_p = dbar0; 1309 else if (brr & (1<<10)) 1310 *addr_p = dbar1; 1311 else if (brr & (1<<9)) 1312 *addr_p = dbar2; 1313 else if (brr & (1<<8)) 1314 *addr_p = dbar3; 1315 else 1316 return 0; 1317 1318 return 1; 1319} 1320 1321int 1322frv_have_stopped_data_address (void) 1323{ 1324 CORE_ADDR addr = 0; 1325 return frv_stopped_data_address (&addr); 1326} 1327 1328static CORE_ADDR 1329frv_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) 1330{ 1331 return frame_unwind_register_unsigned (next_frame, pc_regnum); 1332} 1333 1334/* Given a GDB frame, determine the address of the calling function's 1335 frame. This will be used to create a new GDB frame struct. */ 1336 1337static void 1338frv_frame_this_id (struct frame_info *next_frame, 1339 void **this_prologue_cache, struct frame_id *this_id) 1340{ 1341 struct frv_unwind_cache *info 1342 = frv_frame_unwind_cache (next_frame, this_prologue_cache); 1343 CORE_ADDR base; 1344 CORE_ADDR func; 1345 struct minimal_symbol *msym_stack; 1346 struct frame_id id; 1347 1348 /* The FUNC is easy. */ 1349 func = frame_func_unwind (next_frame); 1350 1351 /* Check if the stack is empty. */ 1352 msym_stack = lookup_minimal_symbol ("_stack", NULL, NULL); 1353 if (msym_stack && info->base == SYMBOL_VALUE_ADDRESS (msym_stack)) 1354 return; 1355 1356 /* Hopefully the prologue analysis either correctly determined the 1357 frame's base (which is the SP from the previous frame), or set 1358 that base to "NULL". */ 1359 base = info->prev_sp; 1360 if (base == 0) 1361 return; 1362 1363 id = frame_id_build (base, func); 1364 (*this_id) = id; 1365} 1366 1367static void 1368frv_frame_prev_register (struct frame_info *next_frame, 1369 void **this_prologue_cache, 1370 int regnum, int *optimizedp, 1371 enum lval_type *lvalp, CORE_ADDR *addrp, 1372 int *realnump, void *bufferp) 1373{ 1374 struct frv_unwind_cache *info 1375 = frv_frame_unwind_cache (next_frame, this_prologue_cache); 1376 trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, 1377 optimizedp, lvalp, addrp, realnump, bufferp); 1378} 1379 1380static const struct frame_unwind frv_frame_unwind = { 1381 NORMAL_FRAME, 1382 frv_frame_this_id, 1383 frv_frame_prev_register 1384}; 1385 1386static const struct frame_unwind * 1387frv_frame_sniffer (struct frame_info *next_frame) 1388{ 1389 return &frv_frame_unwind; 1390} 1391 1392static CORE_ADDR 1393frv_frame_base_address (struct frame_info *next_frame, void **this_cache) 1394{ 1395 struct frv_unwind_cache *info 1396 = frv_frame_unwind_cache (next_frame, this_cache); 1397 return info->base; 1398} 1399 1400static const struct frame_base frv_frame_base = { 1401 &frv_frame_unwind, 1402 frv_frame_base_address, 1403 frv_frame_base_address, 1404 frv_frame_base_address 1405}; 1406 1407static CORE_ADDR 1408frv_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) 1409{ 1410 return frame_unwind_register_unsigned (next_frame, sp_regnum); 1411} 1412 1413 1414/* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that 1415 dummy frame. The frame ID's base needs to match the TOS value 1416 saved by save_dummy_frame_tos(), and the PC match the dummy frame's 1417 breakpoint. */ 1418 1419static struct frame_id 1420frv_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) 1421{ 1422 return frame_id_build (frv_unwind_sp (gdbarch, next_frame), 1423 frame_pc_unwind (next_frame)); 1424} 1425 1426static struct gdbarch * 1427frv_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) 1428{ 1429 struct gdbarch *gdbarch; 1430 struct gdbarch_tdep *var; 1431 int elf_flags = 0; 1432 1433 /* Check to see if we've already built an appropriate architecture 1434 object for this executable. */ 1435 arches = gdbarch_list_lookup_by_info (arches, &info); 1436 if (arches) 1437 return arches->gdbarch; 1438 1439 /* Select the right tdep structure for this variant. */ 1440 var = new_variant (); 1441 switch (info.bfd_arch_info->mach) 1442 { 1443 case bfd_mach_frv: 1444 case bfd_mach_frvsimple: 1445 case bfd_mach_fr500: 1446 case bfd_mach_frvtomcat: 1447 case bfd_mach_fr550: 1448 set_variant_num_gprs (var, 64); 1449 set_variant_num_fprs (var, 64); 1450 break; 1451 1452 case bfd_mach_fr400: 1453 case bfd_mach_fr450: 1454 set_variant_num_gprs (var, 32); 1455 set_variant_num_fprs (var, 32); 1456 break; 1457 1458 default: 1459 /* Never heard of this variant. */ 1460 return 0; 1461 } 1462 1463 /* Extract the ELF flags, if available. */ 1464 if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) 1465 elf_flags = elf_elfheader (info.abfd)->e_flags; 1466 1467 if (elf_flags & EF_FRV_FDPIC) 1468 set_variant_abi_fdpic (var); 1469 1470 if (elf_flags & EF_FRV_CPU_FR450) 1471 set_variant_scratch_registers (var); 1472 1473 gdbarch = gdbarch_alloc (&info, var); 1474 1475 set_gdbarch_short_bit (gdbarch, 16); 1476 set_gdbarch_int_bit (gdbarch, 32); 1477 set_gdbarch_long_bit (gdbarch, 32); 1478 set_gdbarch_long_long_bit (gdbarch, 64); 1479 set_gdbarch_float_bit (gdbarch, 32); 1480 set_gdbarch_double_bit (gdbarch, 64); 1481 set_gdbarch_long_double_bit (gdbarch, 64); 1482 set_gdbarch_ptr_bit (gdbarch, 32); 1483 1484 set_gdbarch_num_regs (gdbarch, frv_num_regs); 1485 set_gdbarch_num_pseudo_regs (gdbarch, frv_num_pseudo_regs); 1486 1487 set_gdbarch_sp_regnum (gdbarch, sp_regnum); 1488 set_gdbarch_deprecated_fp_regnum (gdbarch, fp_regnum); 1489 set_gdbarch_pc_regnum (gdbarch, pc_regnum); 1490 1491 set_gdbarch_register_name (gdbarch, frv_register_name); 1492 set_gdbarch_register_type (gdbarch, frv_register_type); 1493 set_gdbarch_register_sim_regno (gdbarch, frv_register_sim_regno); 1494 1495 set_gdbarch_pseudo_register_read (gdbarch, frv_pseudo_register_read); 1496 set_gdbarch_pseudo_register_write (gdbarch, frv_pseudo_register_write); 1497 1498 set_gdbarch_skip_prologue (gdbarch, frv_skip_prologue); 1499 set_gdbarch_breakpoint_from_pc (gdbarch, frv_breakpoint_from_pc); 1500 set_gdbarch_adjust_breakpoint_address (gdbarch, frv_gdbarch_adjust_breakpoint_address); 1501 1502 set_gdbarch_deprecated_use_struct_convention (gdbarch, always_use_struct_convention); 1503 set_gdbarch_extract_return_value (gdbarch, frv_extract_return_value); 1504 1505 set_gdbarch_deprecated_store_struct_return (gdbarch, frv_store_struct_return); 1506 set_gdbarch_store_return_value (gdbarch, frv_store_return_value); 1507 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, frv_extract_struct_value_address); 1508 1509 /* Frame stuff. */ 1510 set_gdbarch_unwind_pc (gdbarch, frv_unwind_pc); 1511 set_gdbarch_unwind_sp (gdbarch, frv_unwind_sp); 1512 set_gdbarch_frame_align (gdbarch, frv_frame_align); 1513 frame_base_set_default (gdbarch, &frv_frame_base); 1514 /* We set the sniffer lower down after the OSABI hooks have been 1515 established. */ 1516 1517 /* Settings for calling functions in the inferior. */ 1518 set_gdbarch_push_dummy_call (gdbarch, frv_push_dummy_call); 1519 set_gdbarch_unwind_dummy_id (gdbarch, frv_unwind_dummy_id); 1520 1521 /* Settings that should be unnecessary. */ 1522 set_gdbarch_inner_than (gdbarch, core_addr_lessthan); 1523 1524 set_gdbarch_write_pc (gdbarch, generic_target_write_pc); 1525 1526 set_gdbarch_remote_translate_xfer_address 1527 (gdbarch, generic_remote_translate_xfer_address); 1528 1529 /* Hardware watchpoint / breakpoint support. */ 1530 switch (info.bfd_arch_info->mach) 1531 { 1532 case bfd_mach_frv: 1533 case bfd_mach_frvsimple: 1534 case bfd_mach_fr500: 1535 case bfd_mach_frvtomcat: 1536 /* fr500-style hardware debugging support. */ 1537 var->num_hw_watchpoints = 4; 1538 var->num_hw_breakpoints = 4; 1539 break; 1540 1541 case bfd_mach_fr400: 1542 case bfd_mach_fr450: 1543 /* fr400-style hardware debugging support. */ 1544 var->num_hw_watchpoints = 2; 1545 var->num_hw_breakpoints = 4; 1546 break; 1547 1548 default: 1549 /* Otherwise, assume we don't have hardware debugging support. */ 1550 var->num_hw_watchpoints = 0; 1551 var->num_hw_breakpoints = 0; 1552 break; 1553 } 1554 1555 set_gdbarch_print_insn (gdbarch, print_insn_frv); 1556 if (frv_abi (gdbarch) == FRV_ABI_FDPIC) 1557 set_gdbarch_convert_from_func_ptr_addr (gdbarch, 1558 frv_convert_from_func_ptr_addr); 1559 1560 /* Hook in ABI-specific overrides, if they have been registered. */ 1561 gdbarch_init_osabi (info, gdbarch); 1562 1563 /* Set the fallback (prologue based) frame sniffer. */ 1564 frame_unwind_append_sniffer (gdbarch, frv_frame_sniffer); 1565 1566 return gdbarch; 1567} 1568 1569void 1570_initialize_frv_tdep (void) 1571{ 1572 register_gdbarch_init (bfd_arch_frv, frv_gdbarch_init); 1573} 1574