1/* Subroutines for insn-output.c for Matsushita MN10200 series 2 Copyright (C) 1997 Free Software Foundation, Inc. 3 Contributed by Jeff Law (law@cygnus.com). 4 5This file is part of GNU CC. 6 7GNU CC is free software; you can redistribute it and/or modify 8it under the terms of the GNU General Public License as published by 9the Free Software Foundation; either version 2, or (at your option) 10any later version. 11 12GNU CC is distributed in the hope that it will be useful, 13but WITHOUT ANY WARRANTY; without even the implied warranty of 14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15GNU General Public License for more details. 16 17You should have received a copy of the GNU General Public License 18along with GNU CC; see the file COPYING. If not, write to 19the Free Software Foundation, 59 Temple Place - Suite 330, 20Boston, MA 02111-1307, USA. */ 21 22#include "config.h" 23#include <stdio.h> 24#include "rtl.h" 25#include "regs.h" 26#include "hard-reg-set.h" 27#include "real.h" 28#include "insn-config.h" 29#include "conditions.h" 30#include "insn-flags.h" 31#include "output.h" 32#include "insn-attr.h" 33#include "flags.h" 34#include "recog.h" 35#include "expr.h" 36#include "tree.h" 37#include "obstack.h" 38 39/* Global registers known to hold the value zero. 40 41 Normally we'd depend on CSE and combine to put zero into a 42 register and re-use it. 43 44 However, on the mn10x00 processors we implicitly use the constant 45 zero in tst instructions, so we might be able to do better by 46 loading the value into a register in the prologue, then re-useing 47 that register throughout the function. 48 49 We could perform similar optimizations for other constants, but with 50 gcse due soon, it doesn't seem worth the effort. 51 52 These variables hold a rtx for a register known to hold the value 53 zero throughout the entire function, or NULL if no register of 54 the appropriate class has such a value throughout the life of the 55 function. */ 56rtx zero_dreg; 57rtx zero_areg; 58 59/* Note whether or not we need an out of line epilogue. */ 60static int out_of_line_epilogue; 61 62/* Indicate this file was compiled by gcc and what optimization 63 level was used. */ 64void 65asm_file_start (file) 66 FILE *file; 67{ 68 fprintf (file, "#\tGCC For the Matsushita MN10200\n"); 69 if (optimize) 70 fprintf (file, "# -O%d\n", optimize); 71 else 72 fprintf (file, "\n\n"); 73 output_file_directive (file, main_input_filename); 74} 75 76/* Print operand X using operand code CODE to assembly language output file 77 FILE. */ 78 79void 80print_operand (file, x, code) 81 FILE *file; 82 rtx x; 83 int code; 84{ 85 switch (code) 86 { 87 case 'b': 88 case 'B': 89 /* These are normal and reversed branches. */ 90 switch (code == 'b' ? GET_CODE (x) : reverse_condition (GET_CODE (x))) 91 { 92 case NE: 93 fprintf (file, "ne"); 94 break; 95 case EQ: 96 fprintf (file, "eq"); 97 break; 98 case GE: 99 fprintf (file, "ge"); 100 break; 101 case GT: 102 fprintf (file, "gt"); 103 break; 104 case LE: 105 fprintf (file, "le"); 106 break; 107 case LT: 108 fprintf (file, "lt"); 109 break; 110 case GEU: 111 fprintf (file, "cc"); 112 break; 113 case GTU: 114 fprintf (file, "hi"); 115 break; 116 case LEU: 117 fprintf (file, "ls"); 118 break; 119 case LTU: 120 fprintf (file, "cs"); 121 break; 122 default: 123 abort (); 124 } 125 break; 126 case 'C': 127 /* This is used for the operand to a call instruction; 128 if it's a REG, enclose it in parens, else output 129 the operand normally. */ 130 if (GET_CODE (x) == REG) 131 { 132 fputc ('(', file); 133 print_operand (file, x, 0); 134 fputc (')', file); 135 } 136 else 137 print_operand (file, x, 0); 138 break; 139 140 /* These are the least significant word in a 32bit value. 141 'o' allows us to sign extend a constant if doing so 142 makes for more compact code. */ 143 case 'L': 144 case 'o': 145 switch (GET_CODE (x)) 146 { 147 case MEM: 148 fputc ('(', file); 149 output_address (XEXP (x, 0)); 150 fputc (')', file); 151 break; 152 153 case REG: 154 fprintf (file, "%s", reg_names[REGNO (x)]); 155 break; 156 157 case SUBREG: 158 fprintf (file, "%s", 159 reg_names[REGNO (SUBREG_REG (x)) + SUBREG_WORD (x)]); 160 break; 161 162 case CONST_DOUBLE: 163 if (code == 'L') 164 { 165 long val; 166 REAL_VALUE_TYPE rv; 167 168 REAL_VALUE_FROM_CONST_DOUBLE (rv, x); 169 REAL_VALUE_TO_TARGET_SINGLE (rv, val); 170 print_operand_address (file, GEN_INT (val & 0xffff)); 171 } 172 else 173 { 174 long val; 175 REAL_VALUE_TYPE rv; 176 177 REAL_VALUE_FROM_CONST_DOUBLE (rv, x); 178 REAL_VALUE_TO_TARGET_SINGLE (rv, val); 179 180 val &= 0xffff; 181 val = (((val) & 0xffff) ^ (~0x7fff)) + 0x8000; 182 print_operand_address (file, GEN_INT (val)); 183 } 184 break; 185 186 case CONST_INT: 187 if (code == 'L') 188 print_operand_address (file, GEN_INT ((INTVAL (x) & 0xffff))); 189 else 190 { 191 unsigned int val = INTVAL (x) & 0xffff; 192 val = (((val) & 0xffff) ^ (~0x7fff)) + 0x8000; 193 print_operand_address (file, GEN_INT (val)); 194 } 195 break; 196 default: 197 abort (); 198 } 199 break; 200 201 /* Similarly, but for the most significant word. */ 202 case 'H': 203 case 'h': 204 switch (GET_CODE (x)) 205 { 206 case MEM: 207 fputc ('(', file); 208 x = adj_offsettable_operand (x, 2); 209 output_address (XEXP (x, 0)); 210 fputc (')', file); 211 break; 212 213 case REG: 214 fprintf (file, "%s", reg_names[REGNO (x) + 1]); 215 break; 216 217 case SUBREG: 218 fprintf (file, "%s", 219 reg_names[REGNO (SUBREG_REG (x)) + SUBREG_WORD (x)] + 1); 220 break; 221 222 case CONST_DOUBLE: 223 if (code == 'H') 224 { 225 long val; 226 REAL_VALUE_TYPE rv; 227 228 REAL_VALUE_FROM_CONST_DOUBLE (rv, x); 229 REAL_VALUE_TO_TARGET_SINGLE (rv, val); 230 231 print_operand_address (file, GEN_INT ((val >> 16) & 0xffff)); 232 } 233 else 234 { 235 long val; 236 REAL_VALUE_TYPE rv; 237 238 REAL_VALUE_FROM_CONST_DOUBLE (rv, x); 239 REAL_VALUE_TO_TARGET_SINGLE (rv, val); 240 241 val = (val >> 16) & 0xffff; 242 val = (((val) & 0xffff) ^ (~0x7fff)) + 0x8000; 243 244 print_operand_address (file, GEN_INT (val)); 245 } 246 break; 247 248 case CONST_INT: 249 if (code == 'H') 250 print_operand_address (file, 251 GEN_INT ((INTVAL (x) >> 16) & 0xffff)); 252 else 253 { 254 unsigned int val = (INTVAL (x) >> 16) & 0xffff; 255 val = (((val) & 0xffff) ^ (~0x7fff)) + 0x8000; 256 257 print_operand_address (file, GEN_INT (val)); 258 } 259 break; 260 default: 261 abort (); 262 } 263 break; 264 265 /* Output ~CONST_INT. */ 266 case 'N': 267 if (GET_CODE (x) != CONST_INT) 268 abort (); 269 fprintf (file, "%d", ~INTVAL (x)); 270 break; 271 272 /* An address which can not be register indirect, if it is 273 register indirect, then turn it into reg + disp. */ 274 case 'A': 275 if (GET_CODE (x) != MEM) 276 abort (); 277 if (GET_CODE (XEXP (x, 0)) == REG) 278 x = gen_rtx (PLUS, PSImode, XEXP (x, 0), GEN_INT (0)); 279 else 280 x = XEXP (x, 0); 281 fputc ('(', file); 282 output_address (x); 283 fputc (')', file); 284 break; 285 286 case 'Z': 287 print_operand (file, XEXP (x, 1), 0); 288 break; 289 290 /* More cases where we can sign-extend a CONST_INT if it 291 results in more compact code. */ 292 case 's': 293 case 'S': 294 if (GET_CODE (x) == CONST_INT) 295 { 296 int val = INTVAL (x); 297 298 if (code == 's') 299 x = GEN_INT (((val & 0xffff) ^ (~0x7fff)) + 0x8000); 300 else 301 x = GEN_INT (((val & 0xff) ^ (~0x7f)) + 0x80); 302 } 303 /* FALL THROUGH */ 304 default: 305 switch (GET_CODE (x)) 306 { 307 case MEM: 308 fputc ('(', file); 309 output_address (XEXP (x, 0)); 310 fputc (')', file); 311 break; 312 313 case REG: 314 fprintf (file, "%s", reg_names[REGNO (x)]); 315 break; 316 317 case SUBREG: 318 fprintf (file, "%s", 319 reg_names[REGNO (SUBREG_REG (x)) + SUBREG_WORD (x)]); 320 break; 321 322 case CONST_INT: 323 case CONST_DOUBLE: 324 case SYMBOL_REF: 325 case CONST: 326 case LABEL_REF: 327 case CODE_LABEL: 328 print_operand_address (file, x); 329 break; 330 default: 331 abort (); 332 } 333 break; 334 } 335} 336 337/* Output assembly language output for the address ADDR to FILE. */ 338 339void 340print_operand_address (file, addr) 341 FILE *file; 342 rtx addr; 343{ 344 switch (GET_CODE (addr)) 345 { 346 case REG: 347 print_operand (file, addr, 0); 348 break; 349 case PLUS: 350 { 351 rtx base, index; 352 /* The base and index could be in any order, so we have 353 to figure out which is the base and which is the index. 354 Uses the same code as GO_IF_LEGITIMATE_ADDRESS. */ 355 if (REG_P (XEXP (addr, 0)) 356 && REG_OK_FOR_BASE_P (XEXP (addr, 0))) 357 base = XEXP (addr, 0), index = XEXP (addr, 1); 358 else if (REG_P (XEXP (addr, 1)) 359 && REG_OK_FOR_BASE_P (XEXP (addr, 1))) 360 base = XEXP (addr, 1), index = XEXP (addr, 0); 361 else 362 abort (); 363 print_operand (file, index, 0); 364 fputc (',', file); 365 print_operand (file, base, 0);; 366 break; 367 } 368 case SYMBOL_REF: 369 output_addr_const (file, addr); 370 break; 371 default: 372 output_addr_const (file, addr); 373 break; 374 } 375} 376 377/* Count the number of tst insns which compare an address register 378 with zero. */ 379static void 380count_tst_insns (areg_countp) 381 int *areg_countp; 382{ 383 rtx insn; 384 385 /* Assume no tst insns exist. */ 386 *areg_countp = 0; 387 388 /* If not optimizing, then quit now. */ 389 if (!optimize) 390 return; 391 392 /* Walk through all the insns. */ 393 for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) 394 { 395 rtx pat; 396 397 /* Ignore anything that is not a normal INSN. */ 398 if (GET_CODE (insn) != INSN) 399 continue; 400 401 /* Ignore anything that isn't a SET. */ 402 pat = PATTERN (insn); 403 if (GET_CODE (pat) != SET) 404 continue; 405 406 /* Check for a tst insn. */ 407 if (SET_DEST (pat) == cc0_rtx 408 && GET_CODE (SET_SRC (pat)) == REG 409 && REGNO_REG_CLASS (REGNO (SET_SRC (pat))) == ADDRESS_REGS) 410 (*areg_countp)++; 411 } 412} 413 414/* Return the total size (in bytes) of the current function's frame. 415 This is the size of the register save area + the size of locals, 416 spills, etc. */ 417int 418total_frame_size () 419{ 420 unsigned int size = get_frame_size (); 421 unsigned int outgoing_args_size = current_function_outgoing_args_size; 422 int i; 423 424 /* First figure out if we're going to use an out of line 425 prologue, if so we have to make space for all the 426 registers, even if we don't use them. */ 427 if (optimize && !current_function_needs_context && !frame_pointer_needed) 428 { 429 int inline_count, outline_count; 430 431 /* Compute how many bytes an inline prologue would take. 432 433 Each address register store takes two bytes, each data register 434 store takes three bytes. */ 435 inline_count = 0; 436 if (regs_ever_live[5]) 437 inline_count += 2; 438 if (regs_ever_live[6]) 439 inline_count += 2; 440 if (regs_ever_live[2]) 441 inline_count += 3; 442 if (regs_ever_live[3]) 443 inline_count += 3; 444 445 /* If this function has any stack, then the stack adjustment 446 will take two (or more) bytes. */ 447 if (size || outgoing_args_size 448 || regs_ever_live[5] || regs_ever_live[6] 449 || regs_ever_live[2] || regs_ever_live[3]) 450 inline_count += 2; 451 452 /* Multiply the current count by two and add one to account for the 453 epilogue insns. */ 454 inline_count = inline_count * 2 + 1; 455 456 /* Now compute how many bytes an out of line sequence would take. */ 457 /* A relaxed jsr will be three bytes. */ 458 outline_count = 3; 459 460 /* If there are outgoing arguments, then we will need a stack 461 pointer adjustment after the call to the prologue, two 462 more bytes. */ 463 outline_count += (outgoing_args_size == 0 ? 0 : 2); 464 465 /* If there is some local frame to allocate, it will need to be 466 done before the call to the prologue, two more bytes. */ 467 if (get_frame_size () != 0) 468 outline_count += 2; 469 470 /* Now account for the epilogue, multiply the base count by two, 471 then deal with optimizing away the rts instruction. */ 472 outline_count = outline_count * 2 + 1; 473 474 if (get_frame_size () == 0 && outgoing_args_size == 0) 475 outline_count -= 1; 476 477 /* If an out of line prologue is smaller, use it. */ 478 if (inline_count > outline_count) 479 return size + outgoing_args_size + 16; 480 } 481 482 483 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 484 { 485 if (regs_ever_live[i] && !call_used_regs[i] && ! fixed_regs[i] 486 || (i == FRAME_POINTER_REGNUM && frame_pointer_needed)) 487 size += 4; 488 } 489 490 return (size + outgoing_args_size); 491} 492 493/* Expand the prologue into RTL. */ 494void 495expand_prologue () 496{ 497 unsigned int size = total_frame_size (); 498 unsigned int outgoing_args_size = current_function_outgoing_args_size; 499 int offset, i; 500 501 zero_areg = NULL_RTX; 502 zero_dreg = NULL_RTX; 503 504 /* If optimizing, see if we should do an out of line prologue/epilogue 505 sequence. 506 507 We don't support out of line prologues if the current function 508 needs a context or frame pointer. */ 509 if (optimize && !current_function_needs_context && !frame_pointer_needed) 510 { 511 int inline_count, outline_count, areg_count; 512 513 /* We need to end the current sequence so that count_tst_insns can 514 look at all the insns in this function. Normally this would be 515 unsafe, but it's OK in the prologue/epilogue expanders. */ 516 end_sequence (); 517 518 /* Get a count of the number of tst insns which use address 519 registers (it's not profitable to try and improve tst insns 520 which use data registers). */ 521 count_tst_insns (&areg_count); 522 523 /* Now start a new sequence. */ 524 start_sequence (); 525 526 /* Compute how many bytes an inline prologue would take. 527 528 Each address register store takes two bytes, each data register 529 store takes three bytes. */ 530 inline_count = 0; 531 if (regs_ever_live[5]) 532 inline_count += 2; 533 if (regs_ever_live[6]) 534 inline_count += 2; 535 if (regs_ever_live[2]) 536 inline_count += 3; 537 if (regs_ever_live[3]) 538 inline_count += 3; 539 540 /* If this function has any stack, then the stack adjustment 541 will take two (or more) bytes. */ 542 if (size || outgoing_args_size 543 || regs_ever_live[5] || regs_ever_live[6] 544 || regs_ever_live[2] || regs_ever_live[3]) 545 inline_count += 2; 546 547 /* Multiply the current count by two and add one to account for the 548 epilogue insns. */ 549 inline_count = inline_count * 2 + 1; 550 551 /* Now compute how many bytes an out of line sequence would take. */ 552 /* A relaxed jsr will be three bytes. */ 553 outline_count = 3; 554 555 /* If there are outgoing arguments, then we will need a stack 556 pointer adjustment after the call to the prologue, two 557 more bytes. */ 558 outline_count += (outgoing_args_size == 0 ? 0 : 2); 559 560 /* If there is some local frame to allocate, it will need to be 561 done before the call to the prologue, two more bytes. */ 562 if (get_frame_size () != 0) 563 outline_count += 2; 564 565 /* Now account for the epilogue, multiply the base count by two, 566 then deal with optimizing away the rts instruction. */ 567 outline_count = outline_count * 2 + 1; 568 569 if (get_frame_size () == 0 && outgoing_args_size == 0) 570 outline_count -= 1; 571 572 /* If an out of line prologue is smaller, use it. */ 573 if (inline_count > outline_count) 574 { 575 if (get_frame_size () != 0) 576 emit_insn (gen_addpsi3 (stack_pointer_rtx, stack_pointer_rtx, 577 GEN_INT (-size + outgoing_args_size + 16))); 578 emit_insn (gen_outline_prologue_call ()); 579 580 if (outgoing_args_size) 581 emit_insn (gen_addpsi3 (stack_pointer_rtx, stack_pointer_rtx, 582 GEN_INT (-outgoing_args_size))); 583 584 out_of_line_epilogue = 1; 585 586 /* Determine if it is profitable to put the value zero into a register 587 for the entire function. If so, set ZERO_DREG and ZERO_AREG. */ 588 589 /* First see if we could load the value into a data register 590 since that's the most efficient way. */ 591 if (areg_count > 1 592 && (!regs_ever_live[2] || !regs_ever_live[3])) 593 { 594 if (!regs_ever_live[2]) 595 { 596 regs_ever_live[2] = 1; 597 zero_dreg = gen_rtx (REG, HImode, 2); 598 } 599 if (!regs_ever_live[3]) 600 { 601 regs_ever_live[3] = 1; 602 zero_dreg = gen_rtx (REG, HImode, 3); 603 } 604 } 605 606 /* Now see if we could load the value into a address register. */ 607 if (zero_dreg == NULL_RTX 608 && areg_count > 2 609 && (!regs_ever_live[5] || !regs_ever_live[6])) 610 { 611 if (!regs_ever_live[5]) 612 { 613 regs_ever_live[5] = 1; 614 zero_areg = gen_rtx (REG, HImode, 5); 615 } 616 if (!regs_ever_live[6]) 617 { 618 regs_ever_live[6] = 1; 619 zero_areg = gen_rtx (REG, HImode, 6); 620 } 621 } 622 623 if (zero_dreg) 624 emit_move_insn (zero_dreg, const0_rtx); 625 626 if (zero_areg) 627 emit_move_insn (zero_areg, const0_rtx); 628 629 return; 630 } 631 } 632 633 out_of_line_epilogue = 0; 634 635 /* Temporarily stuff the static chain onto the stack so we can 636 use a0 as a scratch register during the prologue. */ 637 if (current_function_needs_context) 638 { 639 emit_insn (gen_addpsi3 (stack_pointer_rtx, stack_pointer_rtx, 640 GEN_INT (-4))); 641 emit_move_insn (gen_rtx (MEM, PSImode, stack_pointer_rtx), 642 gen_rtx (REG, PSImode, STATIC_CHAIN_REGNUM)); 643 } 644 645 if (frame_pointer_needed) 646 { 647 /* Store a2 into a0 temporarily. */ 648 emit_move_insn (gen_rtx (REG, PSImode, 4), frame_pointer_rtx); 649 650 /* Set up the frame pointer. */ 651 emit_move_insn (frame_pointer_rtx, stack_pointer_rtx); 652 } 653 654 /* Make any necessary space for the saved registers and local frame. */ 655 if (size) 656 emit_insn (gen_addpsi3 (stack_pointer_rtx, stack_pointer_rtx, 657 GEN_INT (-size))); 658 659 /* Save the callee saved registers. They're saved into the top 660 of the frame, using the stack pointer. */ 661 for (i = 0, offset = outgoing_args_size; 662 i < FIRST_PSEUDO_REGISTER; i++) 663 { 664 if (regs_ever_live[i] && !call_used_regs[i] && ! fixed_regs[i] 665 || (i == FRAME_POINTER_REGNUM && frame_pointer_needed)) 666 { 667 int regno; 668 669 /* If we're saving the frame pointer, then it will be found in 670 register 4 (a0). */ 671 regno = (i == FRAME_POINTER_REGNUM && frame_pointer_needed) ? 4 : i; 672 673 emit_move_insn (gen_rtx (MEM, PSImode, 674 gen_rtx (PLUS, Pmode, 675 stack_pointer_rtx, 676 GEN_INT (offset))), 677 gen_rtx (REG, PSImode, regno)); 678 offset += 4; 679 } 680 } 681 682 /* Now put the static chain back where the rest of the function 683 expects to find it. */ 684 if (current_function_needs_context) 685 { 686 emit_move_insn (gen_rtx (REG, PSImode, STATIC_CHAIN_REGNUM), 687 gen_rtx (MEM, PSImode, 688 gen_rtx (PLUS, PSImode, stack_pointer_rtx, 689 GEN_INT (size)))); 690 } 691} 692 693/* Expand the epilogue into RTL. */ 694void 695expand_epilogue () 696{ 697 unsigned int size; 698 unsigned int outgoing_args_size = current_function_outgoing_args_size; 699 int offset, i, temp_regno; 700 rtx basereg; 701 702 size = total_frame_size (); 703 704 if (DECL_RESULT (current_function_decl) 705 && DECL_RTL (DECL_RESULT (current_function_decl)) 706 && REG_P (DECL_RTL (DECL_RESULT (current_function_decl)))) 707 temp_regno = (REGNO (DECL_RTL (DECL_RESULT (current_function_decl))) == 4 708 ? 0 : 4); 709 else 710 temp_regno = 4; 711 712 /* Emit an out of line epilogue sequence if it's profitable to do so. */ 713 if (out_of_line_epilogue) 714 { 715 /* If there were no outgoing arguments and no local frame, then 716 we will be able to omit the rts at the end of this function, 717 so just jump to the epilogue_noreturn routine. */ 718 if (get_frame_size () == 0 && outgoing_args_size == 0) 719 { 720 emit_jump_insn (gen_outline_epilogue_jump ()); 721 return; 722 } 723 724 if (outgoing_args_size) 725 emit_insn (gen_addpsi3 (stack_pointer_rtx, stack_pointer_rtx, 726 GEN_INT (outgoing_args_size))); 727 728 if (temp_regno == 0) 729 emit_insn (gen_outline_epilogue_call_d0 ()); 730 else if (temp_regno == 4) 731 emit_insn (gen_outline_epilogue_call_a0 ()); 732 733 if (get_frame_size () != 0) 734 emit_insn (gen_addpsi3 (stack_pointer_rtx, stack_pointer_rtx, 735 GEN_INT (size - outgoing_args_size - 16))); 736 emit_jump_insn (gen_return_internal ()); 737 return; 738 } 739 740 /* Registers are restored from the frame pointer if we have one, 741 else they're restored from the stack pointer. Figure out 742 the appropriate offset to the register save area for both cases. */ 743 if (frame_pointer_needed) 744 { 745 basereg = frame_pointer_rtx; 746 offset = -(size - outgoing_args_size); 747 } 748 else 749 { 750 basereg = stack_pointer_rtx; 751 offset = outgoing_args_size; 752 } 753 754 /* Restore each register. */ 755 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 756 { 757 if (regs_ever_live[i] && !call_used_regs[i] && ! fixed_regs[i] 758 || (i == FRAME_POINTER_REGNUM && frame_pointer_needed)) 759 { 760 int regno; 761 762 /* Restore the frame pointer (if it exists) into a temporary 763 register. */ 764 regno = ((i == FRAME_POINTER_REGNUM && frame_pointer_needed) 765 ? temp_regno : i); 766 767 emit_move_insn (gen_rtx (REG, PSImode, regno), 768 gen_rtx (MEM, PSImode, 769 gen_rtx (PLUS, Pmode, 770 basereg, 771 GEN_INT (offset)))); 772 offset += 4; 773 } 774 } 775 776 if (frame_pointer_needed) 777 { 778 /* Deallocate this frame's stack. */ 779 emit_move_insn (stack_pointer_rtx, frame_pointer_rtx); 780 /* Restore the old frame pointer. */ 781 emit_move_insn (frame_pointer_rtx, gen_rtx (REG, PSImode, temp_regno)); 782 } 783 else if (size) 784 { 785 /* Deallocate this function's stack. */ 786 emit_insn (gen_addpsi3 (stack_pointer_rtx, stack_pointer_rtx, 787 GEN_INT (size))); 788 } 789 790 /* If we had to allocate a slot to save the context pointer, 791 then it must be deallocated here. */ 792 if (current_function_needs_context) 793 emit_insn (gen_addpsi3 (stack_pointer_rtx, stack_pointer_rtx, GEN_INT (4))); 794 795 /* Emit the return insn, if this function had no stack, then we 796 can use the standard return (which allows more optimizations), 797 else we have to use the special one which inhibits optimizations. */ 798 if (size == 0 && !current_function_needs_context) 799 emit_jump_insn (gen_return ()); 800 else 801 emit_jump_insn (gen_return_internal ()); 802} 803 804/* Update the condition code from the insn. */ 805 806void 807notice_update_cc (body, insn) 808 rtx body; 809 rtx insn; 810{ 811 switch (get_attr_cc (insn)) 812 { 813 case CC_NONE: 814 /* Insn does not affect CC at all. */ 815 break; 816 817 case CC_NONE_0HIT: 818 /* Insn does not change CC, but the 0'th operand has been changed. */ 819 if (cc_status.value1 != 0 820 && reg_overlap_mentioned_p (recog_operand[0], cc_status.value1)) 821 cc_status.value1 = 0; 822 break; 823 824 case CC_SET_ZN: 825 /* Insn sets the Z,N flags of CC to recog_operand[0]. 826 V,C is in an unusable state. */ 827 CC_STATUS_INIT; 828 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY; 829 cc_status.value1 = recog_operand[0]; 830 break; 831 832 case CC_SET_ZNV: 833 /* Insn sets the Z,N,V flags of CC to recog_operand[0]. 834 C is in an unusable state. */ 835 CC_STATUS_INIT; 836 cc_status.flags |= CC_NO_CARRY; 837 cc_status.value1 = recog_operand[0]; 838 break; 839 840 case CC_COMPARE: 841 /* The insn is a compare instruction. */ 842 CC_STATUS_INIT; 843 cc_status.value1 = SET_SRC (body); 844 break; 845 846 case CC_CLOBBER: 847 /* Insn doesn't leave CC in a usable state. */ 848 CC_STATUS_INIT; 849 break; 850 851 default: 852 CC_STATUS_INIT; 853 break; 854 } 855} 856 857/* Return true if OP is a valid call operand. Valid call operands 858 are SYMBOL_REFs and REGs. */ 859int 860call_address_operand (op, mode) 861 rtx op; 862 enum machine_mode mode; 863{ 864 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == REG); 865} 866 867/* Return true if OP is a memory operand with a constant address. 868 A special PSImode move pattern uses this predicate. */ 869int 870constant_memory_operand (op, mode) 871 rtx op; 872 enum machine_mode mode; 873{ 874 return GET_CODE (op) == MEM && CONSTANT_ADDRESS_P (XEXP (op, 0)); 875} 876 877/* What (if any) secondary registers are needed to move IN with mode 878 MODE into a register from in register class CLASS. 879 880 We might be able to simplify this. */ 881enum reg_class 882secondary_reload_class (class, mode, in, input) 883 enum reg_class class; 884 enum machine_mode mode; 885 rtx in; 886 int input; 887{ 888 int regno; 889 890 /* Memory loads less than a full word wide can't have an 891 address or stack pointer destination. They must use 892 a data register as an intermediate register. */ 893 if (input 894 && GET_CODE (in) == MEM 895 && (mode == QImode) 896 && class == ADDRESS_REGS) 897 return DATA_REGS; 898 899 /* Address register stores which are not PSImode need a scratch register. */ 900 if (! input 901 && GET_CODE (in) == MEM 902 && (mode != PSImode) 903 && class == ADDRESS_REGS) 904 return DATA_REGS; 905 906 /* Otherwise assume no secondary reloads are needed. */ 907 return NO_REGS; 908} 909 910 911/* Shifts. 912 913 We devote a fair bit of code to getting efficient shifts since we can only 914 shift one bit at a time, and each single bit shift may take multiple 915 instructions. 916 917 The basic shift methods: 918 919 * loop shifts -- emit a loop using one (or two on H8/S) bit shifts; 920 this is the default. SHIFT_LOOP 921 922 * inlined shifts -- emit straight line code for the shift; this is 923 used when a straight line shift is about the same size or smaller 924 than a loop. We allow the inline version to be slightly longer in 925 some cases as it saves a register. SHIFT_INLINE 926 927 * There other oddballs. Not worth explaining. SHIFT_SPECIAL 928 929 930 HImode shifts: 931 932 1-4 do them inline 933 934 5-7 If ashift, then multiply, else loop. 935 936 8-14 - If ashift, then multiply, if lshiftrt, then divide, else loop. 937 15 - rotate the bit we want into the carry, clear the destination, 938 (use mov 0,dst, not sub as sub will clobber the carry), then 939 move bit into place. 940 941 Don't Panic, it's not nearly as bad as the H8 shifting code!!! */ 942 943int 944nshift_operator (x, mode) 945 rtx x; 946 enum machine_mode mode; 947{ 948 switch (GET_CODE (x)) 949 { 950 case ASHIFTRT: 951 case LSHIFTRT: 952 case ASHIFT: 953 return 1; 954 955 default: 956 return 0; 957 } 958} 959 960/* Called from the .md file to emit code to do shifts. 961 Returns a boolean indicating success 962 (currently this is always TRUE). */ 963 964int 965expand_a_shift (mode, code, operands) 966 enum machine_mode mode; 967 int code; 968 rtx operands[]; 969{ 970 emit_move_insn (operands[0], operands[1]); 971 972 /* need a loop to get all the bits we want - we generate the 973 code at emit time, but need to allocate a scratch reg now */ 974 975 emit_insn (gen_rtx 976 (PARALLEL, VOIDmode, 977 gen_rtvec (2, 978 gen_rtx (SET, VOIDmode, operands[0], 979 gen_rtx (code, mode, 980 operands[0], operands[2])), 981 gen_rtx (CLOBBER, VOIDmode, 982 gen_rtx (SCRATCH, HImode, 0))))); 983 984 return 1; 985} 986 987/* Shift algorithm determination. 988 989 There are various ways of doing a shift: 990 SHIFT_INLINE: If the amount is small enough, just generate as many one-bit 991 shifts as we need. 992 SHIFT_SPECIAL: Hand crafted assembler. 993 SHIFT_LOOP: If the above methods fail, just loop. */ 994 995enum shift_alg 996{ 997 SHIFT_INLINE, 998 SHIFT_SPECIAL, 999 SHIFT_LOOP, 1000 SHIFT_MAX 1001}; 1002 1003/* Symbols of the various shifts which can be used as indices. */ 1004 1005enum shift_type 1006 { 1007 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT 1008 }; 1009 1010/* Symbols of the various modes which can be used as indices. */ 1011 1012enum shift_mode 1013 { 1014 HIshift, 1015 }; 1016 1017/* For single bit shift insns, record assembler and what bits of the 1018 condition code are valid afterwards (represented as various CC_FOO 1019 bits, 0 means CC isn't left in a usable state). */ 1020 1021struct shift_insn 1022{ 1023 char *assembler; 1024 int cc_valid; 1025}; 1026 1027/* Assembler instruction shift table. 1028 1029 These tables are used to look up the basic shifts. 1030 They are indexed by cpu, shift_type, and mode. 1031*/ 1032 1033static const struct shift_insn shift_one[3][3] = 1034{ 1035 { 1036/* SHIFT_ASHIFT */ 1037 { "add\t%0,%0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY }, 1038 }, 1039/* SHIFT_LSHIFTRT */ 1040 { 1041 { "lsr\t%0", CC_NO_CARRY }, 1042 }, 1043/* SHIFT_ASHIFTRT */ 1044 { 1045 { "asr\t%0", CC_NO_CARRY }, 1046 }, 1047}; 1048 1049/* Given CPU, MODE, SHIFT_TYPE, and shift count COUNT, determine the best 1050 algorithm for doing the shift. The assembler code is stored in ASSEMBLER. 1051 We don't achieve maximum efficiency in all cases, but the hooks are here 1052 to do so. 1053 1054 For now we just use lots of switch statements. Since we don't even come 1055 close to supporting all the cases, this is simplest. If this function ever 1056 gets too big, perhaps resort to a more table based lookup. Of course, 1057 at this point you may just wish to do it all in rtl. */ 1058 1059static enum shift_alg 1060get_shift_alg (shift_type, mode, count, assembler_p, cc_valid_p) 1061 enum shift_type shift_type; 1062 enum machine_mode mode; 1063 int count; 1064 const char **assembler_p; 1065 int *cc_valid_p; 1066{ 1067 /* The default is to loop. */ 1068 enum shift_alg alg = SHIFT_LOOP; 1069 enum shift_mode shift_mode; 1070 1071 /* We don't handle negative shifts or shifts greater than the word size, 1072 they should have been handled already. */ 1073 1074 if (count < 0 || count > GET_MODE_BITSIZE (mode)) 1075 abort (); 1076 1077 switch (mode) 1078 { 1079 case HImode: 1080 shift_mode = HIshift; 1081 break; 1082 default: 1083 abort (); 1084 } 1085 1086 /* Assume either SHIFT_LOOP or SHIFT_INLINE. 1087 It is up to the caller to know that looping clobbers cc. */ 1088 *assembler_p = shift_one[shift_type][shift_mode].assembler; 1089 *cc_valid_p = shift_one[shift_type][shift_mode].cc_valid; 1090 1091 /* Now look for cases we want to optimize. */ 1092 1093 switch (shift_mode) 1094 { 1095 case HIshift: 1096 if (count <= 4) 1097 return SHIFT_INLINE; 1098 else if (count < 15 && shift_type != SHIFT_ASHIFTRT) 1099 { 1100 switch (count) 1101 { 1102 case 5: 1103 if (shift_type == SHIFT_ASHIFT) 1104 *assembler_p = "mov 32,%4\n\tmul %4,%0"; 1105 else if (shift_type == SHIFT_LSHIFTRT) 1106 *assembler_p 1107 = "sub %4,%4\n\tmov %4,mdr\n\tmov 32,%4\n\tdivu %4,%0"; 1108 *cc_valid_p = CC_NO_CARRY; 1109 return SHIFT_SPECIAL; 1110 case 6: 1111 if (shift_type == SHIFT_ASHIFT) 1112 *assembler_p = "mov 64,%4\n\tmul %4,%0"; 1113 else if (shift_type == SHIFT_LSHIFTRT) 1114 *assembler_p 1115 = "sub %4,%4\n\tmov %4,mdr\n\tmov 64,%4\n\tdivu %4,%0"; 1116 *cc_valid_p = CC_NO_CARRY; 1117 return SHIFT_SPECIAL; 1118 case 7: 1119 if (shift_type == SHIFT_ASHIFT) 1120 *assembler_p = "mov 128,%4\n\tmul %4,%0"; 1121 else if (shift_type == SHIFT_LSHIFTRT) 1122 *assembler_p 1123 = "sub %4,%4\n\tmov %4,mdr\n\tmov 128,%4\n\tdivu %4,%0"; 1124 *cc_valid_p = CC_NO_CARRY; 1125 return SHIFT_SPECIAL; 1126 case 8: 1127 if (shift_type == SHIFT_ASHIFT) 1128 *assembler_p = "mov 256,%4\n\tmul %4,%0"; 1129 else if (shift_type == SHIFT_LSHIFTRT) 1130 *assembler_p 1131 = "sub %4,%4\n\tmov %4,mdr\n\tmov 256,%4\n\tdivu %4,%0"; 1132 *cc_valid_p = CC_NO_CARRY; 1133 return SHIFT_SPECIAL; 1134 case 9: 1135 if (shift_type == SHIFT_ASHIFT) 1136 *assembler_p = "mov 512,%4\n\tmul %4,%0"; 1137 else if (shift_type == SHIFT_LSHIFTRT) 1138 *assembler_p 1139 = "sub %4,%4\n\tmov %4,mdr\n\tmov 512,%4\n\tdivu %4,%0"; 1140 *cc_valid_p = CC_NO_CARRY; 1141 return SHIFT_SPECIAL; 1142 case 10: 1143 if (shift_type == SHIFT_ASHIFT) 1144 *assembler_p = "mov 1024,%4\n\tmul %4,%0"; 1145 else if (shift_type == SHIFT_LSHIFTRT) 1146 *assembler_p 1147 = "sub %4,%4\n\tmov %4,mdr\n\tmov 1024,%4\n\tdivu %4,%0"; 1148 *cc_valid_p = CC_NO_CARRY; 1149 return SHIFT_SPECIAL; 1150 case 11: 1151 if (shift_type == SHIFT_ASHIFT) 1152 *assembler_p = "mov 2048,%4\n\tmul %4,%0"; 1153 else if (shift_type == SHIFT_LSHIFTRT) 1154 *assembler_p 1155 = "sub %4,%4\n\tmov %4,mdr\n\tmov 2048,%4\n\tdivu %4,%0"; 1156 *cc_valid_p = CC_NO_CARRY; 1157 return SHIFT_SPECIAL; 1158 case 12: 1159 if (shift_type == SHIFT_ASHIFT) 1160 *assembler_p = "mov 4096,%4\n\tmul %4,%0"; 1161 else if (shift_type == SHIFT_LSHIFTRT) 1162 *assembler_p 1163 = "sub %4,%4\n\tmov %4,mdr\n\tmov 4096,%4\n\tdivu %4,%0"; 1164 *cc_valid_p = CC_NO_CARRY; 1165 return SHIFT_SPECIAL; 1166 case 13: 1167 if (shift_type == SHIFT_ASHIFT) 1168 *assembler_p = "mov 8192,%4\n\tmul %4,%0"; 1169 else if (shift_type == SHIFT_LSHIFTRT) 1170 *assembler_p 1171 = "sub %4,%4\n\tmov %4,mdr\n\tmov 8192,%4\n\tdivu %4,%0"; 1172 *cc_valid_p = CC_NO_CARRY; 1173 return SHIFT_SPECIAL; 1174 case 14: 1175 if (shift_type == SHIFT_ASHIFT) 1176 *assembler_p = "mov 16384,%4\n\tmul %4,%0"; 1177 else if (shift_type == SHIFT_LSHIFTRT) 1178 *assembler_p 1179 = "sub %4,%4\n\tmov %4,mdr\n\tmov 16384,%4\n\tdivu %4,%0"; 1180 *cc_valid_p = CC_NO_CARRY; 1181 return SHIFT_SPECIAL; 1182 } 1183 } 1184 else if (count == 15) 1185 { 1186 if (shift_type == SHIFT_ASHIFTRT) 1187 { 1188 *assembler_p = "add\t%0,%0\n\tsubc\t%0,%0\n"; 1189 *cc_valid_p = CC_NO_CARRY; 1190 return SHIFT_SPECIAL; 1191 } 1192 if (shift_type == SHIFT_LSHIFTRT) 1193 { 1194 *assembler_p = "add\t%0,%0\n\tmov 0,%0\n\trol %0\n"; 1195 *cc_valid_p = CC_NO_CARRY; 1196 return SHIFT_SPECIAL; 1197 } 1198 if (shift_type == SHIFT_ASHIFT) 1199 { 1200 *assembler_p = "ror\t%0\n\tmov 0,%0\n\tror %0\n"; 1201 *cc_valid_p = CC_NO_CARRY; 1202 return SHIFT_SPECIAL; 1203 } 1204 } 1205 break; 1206 1207 default: 1208 abort (); 1209 } 1210 1211 return alg; 1212} 1213 1214/* Emit the assembler code for doing shifts. */ 1215 1216char * 1217emit_a_shift (insn, operands) 1218 rtx insn; 1219 rtx *operands; 1220{ 1221 static int loopend_lab; 1222 char *assembler; 1223 int cc_valid; 1224 rtx inside = PATTERN (insn); 1225 rtx shift = operands[3]; 1226 enum machine_mode mode = GET_MODE (shift); 1227 enum rtx_code code = GET_CODE (shift); 1228 enum shift_type shift_type; 1229 enum shift_mode shift_mode; 1230 1231 loopend_lab++; 1232 1233 switch (mode) 1234 { 1235 case HImode: 1236 shift_mode = HIshift; 1237 break; 1238 default: 1239 abort (); 1240 } 1241 1242 switch (code) 1243 { 1244 case ASHIFTRT: 1245 shift_type = SHIFT_ASHIFTRT; 1246 break; 1247 case LSHIFTRT: 1248 shift_type = SHIFT_LSHIFTRT; 1249 break; 1250 case ASHIFT: 1251 shift_type = SHIFT_ASHIFT; 1252 break; 1253 default: 1254 abort (); 1255 } 1256 1257 if (GET_CODE (operands[2]) != CONST_INT) 1258 { 1259 /* Indexing by reg, so have to loop and test at top */ 1260 output_asm_insn ("mov %2,%4", operands); 1261 output_asm_insn ("cmp 0,%4", operands); 1262 fprintf (asm_out_file, "\tble .Lle%d\n", loopend_lab); 1263 1264 /* Get the assembler code to do one shift. */ 1265 get_shift_alg (shift_type, mode, 1, &assembler, &cc_valid); 1266 } 1267 else 1268 { 1269 int n = INTVAL (operands[2]); 1270 enum shift_alg alg; 1271 1272 /* If the count is negative, make it 0. */ 1273 if (n < 0) 1274 n = 0; 1275 /* If the count is too big, truncate it. 1276 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to 1277 do the intuitive thing. */ 1278 else if (n > GET_MODE_BITSIZE (mode)) 1279 n = GET_MODE_BITSIZE (mode); 1280 1281 alg = get_shift_alg (shift_type, mode, n, &assembler, &cc_valid); 1282 1283 1284 switch (alg) 1285 { 1286 case SHIFT_INLINE: 1287 /* Emit one bit shifts. */ 1288 while (n > 0) 1289 { 1290 output_asm_insn (assembler, operands); 1291 n -= 1; 1292 } 1293 1294 /* Keep track of CC. */ 1295 if (cc_valid) 1296 { 1297 cc_status.value1 = operands[0]; 1298 cc_status.flags |= cc_valid; 1299 } 1300 return ""; 1301 1302 case SHIFT_SPECIAL: 1303 output_asm_insn (assembler, operands); 1304 1305 /* Keep track of CC. */ 1306 if (cc_valid) 1307 { 1308 cc_status.value1 = operands[0]; 1309 cc_status.flags |= cc_valid; 1310 } 1311 return ""; 1312 } 1313 1314 { 1315 fprintf (asm_out_file, "\tmov %d,%s\n", n, 1316 reg_names[REGNO (operands[4])]); 1317 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab); 1318 output_asm_insn (assembler, operands); 1319 output_asm_insn ("add -1,%4", operands); 1320 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab); 1321 return ""; 1322 } 1323 } 1324 1325 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab); 1326 output_asm_insn (assembler, operands); 1327 output_asm_insn ("add -1,%4", operands); 1328 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab); 1329 fprintf (asm_out_file, ".Lle%d:\n", loopend_lab); 1330 1331 return ""; 1332} 1333 1334/* Return an RTX to represent where a value with mode MODE will be returned 1335 from a function. If the result is 0, the argument is pushed. */ 1336 1337rtx 1338function_arg (cum, mode, type, named) 1339 CUMULATIVE_ARGS *cum; 1340 enum machine_mode mode; 1341 tree type; 1342 int named; 1343{ 1344 rtx result = 0; 1345 int size, align; 1346 1347 /* We only support using 2 data registers as argument registers. */ 1348 int nregs = 2; 1349 1350 /* Only pass named arguments in registers. */ 1351 if (!named) 1352 return NULL_RTX; 1353 1354 /* Figure out the size of the object to be passed. We lie and claim 1355 PSImode values are only two bytes since they fit in a single 1356 register. */ 1357 if (mode == BLKmode) 1358 size = int_size_in_bytes (type); 1359 else if (mode == PSImode) 1360 size = 2; 1361 else 1362 size = GET_MODE_SIZE (mode); 1363 1364 /* Figure out the alignment of the object to be passed. */ 1365 align = size; 1366 1367 cum->nbytes = (cum->nbytes + 1) & ~1; 1368 1369 /* Don't pass this arg via a register if all the argument registers 1370 are used up. */ 1371 if (cum->nbytes + size > nregs * UNITS_PER_WORD) 1372 return 0; 1373 1374 switch (cum->nbytes / UNITS_PER_WORD) 1375 { 1376 case 0: 1377 result = gen_rtx (REG, mode, 0); 1378 break; 1379 case 1: 1380 result = gen_rtx (REG, mode, 1); 1381 break; 1382 default: 1383 result = 0; 1384 } 1385 1386 return result; 1387} 1388 1389/* Return the number of registers to use for an argument passed partially 1390 in registers and partially in memory. */ 1391 1392int 1393function_arg_partial_nregs (cum, mode, type, named) 1394 CUMULATIVE_ARGS *cum; 1395 enum machine_mode mode; 1396 tree type; 1397 int named; 1398{ 1399 int size, align; 1400 1401 /* We only support using 2 data registers as argument registers. */ 1402 int nregs = 2; 1403 1404 return 0; 1405 /* Only pass named arguments in registers. */ 1406 if (!named) 1407 return 0; 1408 1409 /* Figure out the size of the object to be passed. */ 1410 if (mode == BLKmode) 1411 size = int_size_in_bytes (type); 1412 else if (mode == PSImode) 1413 size = 2; 1414 else 1415 size = GET_MODE_SIZE (mode); 1416 1417 /* Figure out the alignment of the object to be passed. */ 1418 align = size; 1419 1420 cum->nbytes = (cum->nbytes + 1) & ~1; 1421 1422 /* Don't pass this arg via a register if all the argument registers 1423 are used up. */ 1424 if (cum->nbytes > nregs * UNITS_PER_WORD) 1425 return 0; 1426 1427 if (cum->nbytes + size <= nregs * UNITS_PER_WORD) 1428 return 0; 1429 1430 /* Don't pass this arg via a register if it would be split between 1431 registers and memory. */ 1432 if (type == NULL_TREE 1433 && cum->nbytes + size > nregs * UNITS_PER_WORD) 1434 return 0; 1435 1436 return (nregs * UNITS_PER_WORD - cum->nbytes) / UNITS_PER_WORD; 1437} 1438 1439char * 1440output_tst (operand, insn) 1441 rtx operand, insn; 1442{ 1443 1444 rtx temp; 1445 int past_call = 0; 1446 1447 /* Only tst insns using address registers can be optimized. */ 1448 if (REGNO_REG_CLASS (REGNO (operand)) != ADDRESS_REGS) 1449 return "cmp 0,%0"; 1450 1451 /* If testing an address register against zero, we can do better if 1452 we know there's a register already holding the value zero. First 1453 see if a global register has been set to zero, else we do a search 1454 for a register holding zero, if both of those fail, then we use a 1455 compare against zero. */ 1456 if (zero_dreg || zero_areg) 1457 { 1458 rtx xoperands[2]; 1459 xoperands[0] = operand; 1460 xoperands[1] = zero_dreg ? zero_dreg : zero_areg; 1461 1462 output_asm_insn ("cmp %1,%0", xoperands); 1463 return ""; 1464 } 1465 1466 /* We can save a byte if we can find a register which has the value 1467 zero in it. */ 1468 temp = PREV_INSN (insn); 1469 while (temp) 1470 { 1471 rtx set; 1472 1473 /* We allow the search to go through call insns. We record 1474 the fact that we've past a CALL_INSN and reject matches which 1475 use call clobbered registers. */ 1476 if (GET_CODE (temp) == CODE_LABEL 1477 || GET_CODE (temp) == JUMP_INSN 1478 || GET_CODE (temp) == BARRIER) 1479 break; 1480 1481 if (GET_CODE (temp) == CALL_INSN) 1482 past_call = 1; 1483 1484 if (GET_CODE (temp) == NOTE) 1485 { 1486 temp = PREV_INSN (temp); 1487 continue; 1488 } 1489 1490 /* It must be an insn, see if it is a simple set. */ 1491 set = single_set (temp); 1492 if (!set) 1493 { 1494 temp = PREV_INSN (temp); 1495 continue; 1496 } 1497 1498 /* Are we setting a register to zero? 1499 1500 If it's a call clobbered register, have we past a call? */ 1501 if (REG_P (SET_DEST (set)) 1502 && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set))) 1503 && !reg_set_between_p (SET_DEST (set), temp, insn) 1504 && (!past_call 1505 || !call_used_regs[REGNO (SET_DEST (set))])) 1506 { 1507 rtx xoperands[2]; 1508 xoperands[0] = operand; 1509 xoperands[1] = SET_DEST (set); 1510 1511 output_asm_insn ("cmp %1,%0", xoperands); 1512 return ""; 1513 } 1514 temp = PREV_INSN (temp); 1515 } 1516 return "cmp 0,%0"; 1517} 1518 1519/* Return nonzero if OP is a valid operand for a {zero,sign}_extendpsisi 1520 instruction. 1521 1522 It accepts anything that is a general operand or the sum of the 1523 stack pointer and a general operand. */ 1524extendpsi_operand (op, mode) 1525 rtx op; 1526 enum machine_mode mode; 1527{ 1528 return (general_operand (op, mode) 1529 || (GET_CODE (op) == PLUS 1530 && XEXP (op, 0) == stack_pointer_rtx 1531 && general_operand (XEXP (op, 1), VOIDmode))); 1532} 1533