1/* Subroutines for insn-output.c for Hitachi H8/300. 2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000 3 Free Software Foundation, Inc. 4 Contributed by Steve Chamberlain (sac@cygnus.com), 5 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com). 6 7This file is part of GNU CC. 8 9GNU CC is free software; you can redistribute it and/or modify 10it under the terms of the GNU General Public License as published by 11the Free Software Foundation; either version 2, or (at your option) 12any later version. 13 14GNU CC is distributed in the hope that it will be useful, 15but WITHOUT ANY WARRANTY; without even the implied warranty of 16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17GNU General Public License for more details. 18 19You should have received a copy of the GNU General Public License 20along with GNU CC; see the file COPYING. If not, write to 21the Free Software Foundation, 59 Temple Place - Suite 330, 22Boston, MA 02111-1307, USA. */ 23 24#include "config.h" 25#include <stdio.h> 26#include "rtl.h" 27#include "regs.h" 28#include "hard-reg-set.h" 29#include "real.h" 30#include "insn-config.h" 31#include "conditions.h" 32#include "insn-flags.h" 33#include "output.h" 34#include "insn-attr.h" 35#include "flags.h" 36#include "recog.h" 37#include "expr.h" 38#include "tree.h" 39#include "obstack.h" 40 41/* Forward declarations. */ 42void print_operand_address (); 43char *index (); 44 45static int h8300_interrupt_function_p PROTO ((tree)); 46static int h8300_monitor_function_p PROTO ((tree)); 47static int h8300_os_task_function_p PROTO ((tree)); 48 49/* CPU_TYPE, says what cpu we're compiling for. */ 50int cpu_type; 51 52/* True if the current function is an interrupt handler 53 (either via #pragma or an attribute specification). */ 54int interrupt_handler; 55 56/* True if the current function is an OS Task 57 (via an attribute specification). */ 58int os_task; 59 60/* True if the current function is a monitor 61 (via an attribute specification). */ 62int monitor; 63 64/* True if a #pragma saveall has been seen for the current function. */ 65int pragma_saveall; 66 67static char *names_big[] = 68{"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7"}; 69 70static char *names_extended[] = 71{"er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7"}; 72 73static char *names_upper_extended[] = 74{"e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7"}; 75 76/* Points to one of the above. */ 77/* ??? The above could be put in an array indexed by CPU_TYPE. */ 78char **h8_reg_names; 79 80/* Various operations needed by the following, indexed by CPU_TYPE. */ 81 82static char *h8_push_ops[2] = 83{"push", "push.l"}; 84static char *h8_pop_ops[2] = 85{"pop", "pop.l"}; 86static char *h8_mov_ops[2] = 87{"mov.w", "mov.l"}; 88 89char *h8_push_op, *h8_pop_op, *h8_mov_op; 90 91/* Initialize various cpu specific globals at start up. */ 92 93void 94h8300_init_once () 95{ 96 if (TARGET_H8300) 97 { 98 cpu_type = (int) CPU_H8300; 99 h8_reg_names = names_big; 100 } 101 else 102 { 103 /* For this we treat the H8/300 and H8/S the same. */ 104 cpu_type = (int) CPU_H8300H; 105 h8_reg_names = names_extended; 106 } 107 h8_push_op = h8_push_ops[cpu_type]; 108 h8_pop_op = h8_pop_ops[cpu_type]; 109 h8_mov_op = h8_mov_ops[cpu_type]; 110} 111 112char * 113byte_reg (x, b) 114 rtx x; 115 int b; 116{ 117 static char *names_small[] = 118 {"r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h", 119 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"}; 120 121 return names_small[REGNO (x) * 2 + b]; 122} 123 124/* REGNO must be saved/restored across calls if this macro is true. */ 125 126#define WORD_REG_USED(regno) \ 127 (regno < 7 && \ 128 (interrupt_handler \ 129 || pragma_saveall \ 130 || (regno == FRAME_POINTER_REGNUM && regs_ever_live[regno]) \ 131 || (regs_ever_live[regno] && !call_used_regs[regno]))) 132 133/* Output assembly language to FILE for the operation OP with operand size 134 SIZE to adjust the stack pointer. */ 135 136static void 137dosize (file, op, size) 138 FILE *file; 139 char *op; 140 unsigned int size; 141{ 142 /* On the h8300h and h8300s, for sizes <= 8 bytes it is as good or 143 better to use adds/subs insns rather than add.l/sub.l 144 with an immediate value. */ 145 if (size > 4 && size <= 8 && (TARGET_H8300H || TARGET_H8300S)) 146 { 147 /* Crank the size down to <= 4 */ 148 fprintf (file, "\t%ss\t#%d,sp\n", op, 4); 149 size -= 4; 150 } 151 152 switch (size) 153 { 154 case 4: 155 if (TARGET_H8300H || TARGET_H8300S) 156 { 157 fprintf (file, "\t%ss\t#%d,sp\n", op, 4); 158 size = 0; 159 break; 160 } 161 case 3: 162 fprintf (file, "\t%ss\t#%d,sp\n", op, 2); 163 size -= 2; 164 /* Fall through... */ 165 case 2: 166 case 1: 167 fprintf (file, "\t%ss\t#%d,sp\n", op, size); 168 size = 0; 169 break; 170 case 0: 171 break; 172 default: 173 if (TARGET_H8300) 174 { 175 if (current_function_needs_context 176 && strcmp (op, "sub") == 0) 177 { 178 /* Egad. We don't have a temporary to hold the 179 size of the frame in the prologue! Just inline 180 the bastard since this shouldn't happen often. */ 181 while (size >= 2) 182 { 183 fprintf (file, "\tsubs\t#2,sp\n"); 184 size -= 2; 185 } 186 187 if (size) 188 fprintf (file, "\tsubs\t#1,sp\n"); 189 190 size = 0; 191 } 192 else 193 fprintf (file, "\tmov.w\t#%d,r3\n\t%s.w\tr3,sp\n", size, op); 194 } 195 else 196 fprintf (file, "\t%s\t#%d,sp\n", op, size); 197 size = 0; 198 break; 199 } 200} 201 202/* Output assembly language code for the function prologue. */ 203static int push_order[FIRST_PSEUDO_REGISTER] = 204{0, 1, 2, 3, 4, 5, 6, -1, -1, -1}; 205static int pop_order[FIRST_PSEUDO_REGISTER] = 206{6, 5, 4, 3, 2, 1, 0, -1, -1, -1}; 207 208/* This is what the stack looks like after the prolog of 209 a function with a frame has been set up: 210 211 <args> 212 PC 213 FP <- fp 214 <locals> 215 <saved registers> <- sp 216 217 This is what the stack looks like after the prolog of 218 a function which doesn't have a frame: 219 220 <args> 221 PC 222 <locals> 223 <saved registers> <- sp 224*/ 225 226void 227function_prologue (file, size) 228 FILE *file; 229 int size; 230{ 231 register int mask = 0; 232 int fsize = (size + STACK_BOUNDARY / 8 - 1) & -STACK_BOUNDARY / 8; 233 int idx; 234 235 /* Note a function with the interrupt attribute and set interrupt_handler 236 accordingly. */ 237 if (h8300_interrupt_function_p (current_function_decl)) 238 interrupt_handler = 1; 239 240 /* If the current function has the OS_Task attribute set, then 241 we have a naked prologue. */ 242 if (h8300_os_task_function_p (current_function_decl)) 243 { 244 fprintf (file, ";OS_Task prologue\n"); 245 os_task = 1; 246 return; 247 } 248 249 if (h8300_monitor_function_p (current_function_decl)) 250 { 251 /* My understanding of monitor functions is they act just 252 like interrupt functions, except the prologue must 253 mask interrupts. */ 254 fprintf (file, ";monitor prologue\n"); 255 interrupt_handler = 1; 256 monitor = 1; 257 if (TARGET_H8300) 258 { 259 fprintf (file, "\tsubs\t#2,sp\n"); 260 fprintf (file, "\tpush\tr0\n"); 261 fprintf (file, "\tstc\tccr,r0l\n"); 262 fprintf (file, "\torc\t#128,ccr\n"); 263 fprintf (file, "\tmov.b\tr0l,@(4,sp)\n"); 264 } 265 else 266 { 267 fprintf (file, "\tpush\ter0\n"); 268 fprintf (file, "\tstc\tccr,r0l\n"); 269 fprintf (file, "\torc\t#128,ccr\n"); 270 fprintf (file, "\tmov.b\tr0l,@(4,sp)\n"); 271 } 272 } 273 274 if (frame_pointer_needed) 275 { 276 /* Push fp */ 277 fprintf (file, "\t%s\t%s\n", h8_push_op, 278 h8_reg_names[FRAME_POINTER_REGNUM]); 279 fprintf (file, "\t%s\t%s,%s\n", h8_mov_op, 280 h8_reg_names[STACK_POINTER_REGNUM], 281 h8_reg_names[FRAME_POINTER_REGNUM]); 282 } 283 284 /* leave room for locals */ 285 dosize (file, "sub", fsize); 286 287 /* Push the rest of the registers */ 288 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++) 289 { 290 int regno = push_order[idx]; 291 292 if (regno >= 0 293 && WORD_REG_USED (regno) 294 && (!frame_pointer_needed || regno != FRAME_POINTER_REGNUM)) 295 { 296 if (TARGET_H8300S) 297 { 298 /* Try to push multiple registers. */ 299 if (regno == 0 || regno == 4) 300 { 301 int second_regno = push_order[idx + 1]; 302 int third_regno = push_order[idx + 2]; 303 int fourth_regno = push_order[idx + 3]; 304 305 if (fourth_regno >= 0 306 && WORD_REG_USED (fourth_regno) 307 && (!frame_pointer_needed 308 || fourth_regno != FRAME_POINTER_REGNUM) 309 && third_regno >= 0 310 && WORD_REG_USED (third_regno) 311 && (!frame_pointer_needed 312 || third_regno != FRAME_POINTER_REGNUM) 313 && second_regno >= 0 314 && WORD_REG_USED (second_regno) 315 && (!frame_pointer_needed 316 || second_regno != FRAME_POINTER_REGNUM)) 317 { 318 fprintf (file, "\tstm.l %s-%s,@-sp\n", 319 h8_reg_names[regno], 320 h8_reg_names[fourth_regno]); 321 idx += 3; 322 continue; 323 } 324 } 325 if (regno == 0 || regno == 4) 326 { 327 int second_regno = push_order[idx + 1]; 328 int third_regno = push_order[idx + 2]; 329 330 if (third_regno >= 0 331 && WORD_REG_USED (third_regno) 332 && (!frame_pointer_needed 333 || third_regno != FRAME_POINTER_REGNUM) 334 && second_regno >= 0 335 && WORD_REG_USED (second_regno) 336 && (!frame_pointer_needed 337 || second_regno != FRAME_POINTER_REGNUM)) 338 { 339 fprintf (file, "\tstm.l %s-%s,@-sp\n", 340 h8_reg_names[regno], 341 h8_reg_names[third_regno]); 342 idx += 2; 343 continue; 344 } 345 } 346 if (regno == 0 || regno == 2 || regno == 4 || regno == 6) 347 { 348 int second_regno = push_order[idx + 1]; 349 350 if (second_regno >= 0 351 && WORD_REG_USED (second_regno) 352 && (!frame_pointer_needed 353 || second_regno != FRAME_POINTER_REGNUM)) 354 { 355 fprintf (file, "\tstm.l %s-%s,@-sp\n", 356 h8_reg_names[regno], 357 h8_reg_names[second_regno]); 358 idx += 1; 359 continue; 360 } 361 } 362 } 363 fprintf (file, "\t%s\t%s\n", h8_push_op, h8_reg_names[regno]); 364 } 365 } 366} 367 368/* Output assembly language code for the function epilogue. */ 369 370void 371function_epilogue (file, size) 372 FILE *file; 373 int size; 374{ 375 register int regno; 376 register int mask = 0; 377 int fsize = (size + STACK_BOUNDARY / 8 - 1) & -STACK_BOUNDARY / 8; 378 int idx; 379 rtx insn = get_last_insn (); 380 381 if (os_task) 382 { 383 /* OS_Task epilogues are nearly naked -- they just have an 384 rts instruction. */ 385 fprintf (file, ";OS_task epilogue\n"); 386 fprintf (file, "\trts\n"); 387 goto out; 388 } 389 390 /* monitor epilogues are the same as interrupt function epilogues. 391 Just make a note that we're in an monitor epilogue. */ 392 if (monitor) 393 fprintf(file, ";monitor epilogue\n"); 394 395 /* If the last insn was a BARRIER, we don't have to write any code. */ 396 if (GET_CODE (insn) == NOTE) 397 insn = prev_nonnote_insn (insn); 398 if (insn && GET_CODE (insn) == BARRIER) 399 goto out; 400 401 /* Pop the saved registers. */ 402 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++) 403 { 404 int regno = pop_order[idx]; 405 406 if (regno >= 0 407 && WORD_REG_USED (regno) 408 && (!frame_pointer_needed || regno != FRAME_POINTER_REGNUM)) 409 { 410 if (TARGET_H8300S) 411 { 412 /* Try to pop multiple registers. */ 413 if (regno == 7 || regno == 3) 414 { 415 int second_regno = pop_order[idx + 1]; 416 int third_regno = pop_order[idx + 2]; 417 int fourth_regno = pop_order[idx + 3]; 418 419 if (fourth_regno >= 0 420 && WORD_REG_USED (fourth_regno) 421 && (!frame_pointer_needed 422 || fourth_regno != FRAME_POINTER_REGNUM) 423 && third_regno >= 0 424 && WORD_REG_USED (third_regno) 425 && (!frame_pointer_needed 426 || third_regno != FRAME_POINTER_REGNUM) 427 && second_regno >= 0 428 && WORD_REG_USED (second_regno) 429 && (!frame_pointer_needed 430 || second_regno != FRAME_POINTER_REGNUM)) 431 { 432 fprintf (file, "\tldm.l @sp+,%s-%s\n", 433 h8_reg_names[fourth_regno], 434 h8_reg_names[regno]); 435 idx += 3; 436 continue; 437 } 438 } 439 if (regno == 6 || regno == 2) 440 { 441 int second_regno = pop_order[idx + 1]; 442 int third_regno = pop_order[idx + 2]; 443 444 if (third_regno >= 0 445 && WORD_REG_USED (third_regno) 446 && (!frame_pointer_needed 447 || third_regno != FRAME_POINTER_REGNUM) 448 && second_regno >= 0 449 && WORD_REG_USED (second_regno) 450 && (!frame_pointer_needed 451 || second_regno != FRAME_POINTER_REGNUM)) 452 { 453 fprintf (file, "\tldm.l @sp+,%s-%s\n", 454 h8_reg_names[third_regno], 455 h8_reg_names[regno]); 456 idx += 2; 457 continue; 458 } 459 } 460 if (regno == 7 || regno == 5 || regno == 3 || regno == 1) 461 { 462 int second_regno = pop_order[idx + 1]; 463 464 if (second_regno >= 0 465 && WORD_REG_USED (second_regno) 466 && (!frame_pointer_needed 467 || second_regno != FRAME_POINTER_REGNUM)) 468 { 469 fprintf (file, "\tldm.l @sp+,%s-%s\n", 470 h8_reg_names[second_regno], 471 h8_reg_names[regno]); 472 idx += 1; 473 continue; 474 } 475 } 476 } 477 fprintf (file, "\t%s\t%s\n", h8_pop_op, h8_reg_names[regno]); 478 } 479 } 480 481 /* deallocate locals */ 482 dosize (file, "add", fsize); 483 484 /* pop frame pointer if we had one. */ 485 if (frame_pointer_needed) 486 fprintf (file, "\t%s\t%s\n", h8_pop_op, h8_reg_names[FRAME_POINTER_REGNUM]); 487 488 /* If this is a monitor function, there is one register still left on 489 the stack. */ 490 if (monitor) 491 fprintf (file, "\t%s\t%s\n", h8_pop_op, h8_reg_names[0]); 492 493 if (interrupt_handler) 494 fprintf (file, "\trte\n"); 495 else 496 fprintf (file, "\trts\n"); 497 498out: 499 interrupt_handler = 0; 500 os_task = 0; 501 monitor = 0; 502 pragma_saveall = 0; 503} 504 505/* Output assembly code for the start of the file. */ 506 507asm_file_start (file) 508 FILE *file; 509{ 510 fprintf (file, ";\tGCC For the Hitachi H8/300\n"); 511 fprintf (file, ";\tBy Hitachi America Ltd and Cygnus Support\n"); 512 fprintf (file, ";\trelease F-1\n"); 513 if (optimize) 514 fprintf (file, "; -O%d\n", optimize); 515 if (TARGET_H8300H) 516 fprintf (file, "\n\t.h8300h\n"); 517 else if (TARGET_H8300S) 518 fprintf (file, "\n\t.h8300s\n"); 519 else 520 fprintf (file, "\n\n"); 521 output_file_directive (file, main_input_filename); 522} 523 524/* Output assembly language code for the end of file. */ 525 526void 527asm_file_end (file) 528 FILE *file; 529{ 530 fprintf (file, "\t.end\n"); 531} 532 533/* Return true if VALUE is a valid constant for constraint 'P'. 534 IE: VALUE is a power of two <= 2**15. */ 535 536int 537small_power_of_two (value) 538 int value; 539{ 540 switch (value) 541 { 542 case 1: 543 case 2: 544 case 4: 545 case 8: 546 case 16: 547 case 32: 548 case 64: 549 case 128: 550 case 256: 551 case 512: 552 case 1024: 553 case 2048: 554 case 4096: 555 case 8192: 556 case 16384: 557 case 32768: 558 return 1; 559 } 560 return 0; 561} 562 563/* Return true if VALUE is a valid constant for constraint 'O', which 564 means that the constant would be ok to use as a bit for a bclr 565 instruction. */ 566 567int 568ok_for_bclr (value) 569 int value; 570{ 571 return small_power_of_two ((~value) & 0xff); 572} 573 574/* Return true is OP is a valid source operand for an integer move 575 instruction. */ 576 577int 578general_operand_src (op, mode) 579 rtx op; 580 enum machine_mode mode; 581{ 582 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == POST_INC) 583 return 1; 584 return general_operand (op, mode); 585} 586 587/* Return true if OP is a valid destination operand for an integer move 588 instruction. */ 589 590int 591general_operand_dst (op, mode) 592 rtx op; 593 enum machine_mode mode; 594{ 595 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == PRE_DEC) 596 return 1; 597 return general_operand (op, mode); 598} 599 600/* Return true if OP is a const valid for a bit clear instruction. */ 601 602int 603o_operand (operand, mode) 604 rtx operand; 605 enum machine_mode mode; 606{ 607 return (GET_CODE (operand) == CONST_INT 608 && CONST_OK_FOR_O (INTVAL (operand))); 609} 610 611/* Return true if OP is a const valid for a bit set or bit xor instruction. */ 612 613int 614p_operand (operand, mode) 615 rtx operand; 616 enum machine_mode mode; 617{ 618 return (GET_CODE (operand) == CONST_INT 619 && CONST_OK_FOR_P (INTVAL (operand))); 620} 621 622/* Return true if OP is a valid call operand. */ 623 624int 625call_insn_operand (op, mode) 626 rtx op; 627 enum machine_mode mode; 628{ 629 if (GET_CODE (op) == MEM) 630 { 631 rtx inside = XEXP (op, 0); 632 if (register_operand (inside, Pmode)) 633 return 1; 634 if (CONSTANT_ADDRESS_P (inside)) 635 return 1; 636 } 637 return 0; 638} 639 640int 641adds_subs_operand (op, mode) 642 rtx op; 643 enum machine_mode mode; 644{ 645 if (GET_CODE (op) == CONST_INT) 646 { 647 if (INTVAL (op) <= 4 && INTVAL (op) >= 0) 648 return 1; 649 if (INTVAL (op) >= -4 && INTVAL (op) <= 0) 650 return 1; 651 if ((TARGET_H8300H || TARGET_H8300S) 652 && INTVAL (op) != 7 653 && (INTVAL (op) <= 8 && INTVAL (op) >= 0)) 654 return 1; 655 if ((TARGET_H8300H || TARGET_H8300S) 656 && INTVAL (op) != -7 657 && (INTVAL (op) >= -8 && INTVAL (op) <= 0)) 658 return 1; 659 } 660 return 0; 661} 662 663/* Return nonzero if op is an adds/subs operand which only requires 664 one insn to implement. It is assumed that OP is already an adds/subs 665 operand. */ 666int 667one_insn_adds_subs_operand (op, mode) 668 rtx op; 669 enum machine_mode mode; 670{ 671 int val = INTVAL (op); 672 673 if (val == 1 || val == -1 674 || val == 2 || val == -2 675 || ((TARGET_H8300H || TARGET_H8300S) 676 && (val == 4 || val == -4))) 677 return 1; 678 return 0; 679} 680 681char * 682output_adds_subs (operands) 683 rtx *operands; 684{ 685 int val = INTVAL (operands[2]); 686 687 /* First get the value into the range -4..4 inclusive. 688 689 The only way it can be out of this range is when TARGET_H8300H 690 or TARGET_H8300S is true, thus it is safe to use adds #4 and subs #4. */ 691 if (val > 4) 692 { 693 output_asm_insn ("adds #4,%A0", operands); 694 val -= 4; 695 } 696 697 if (val < -4) 698 { 699 output_asm_insn ("subs #4,%A0", operands); 700 val += 4; 701 } 702 703 /* Handle case were val == 4 or val == -4 and we're compiling 704 for TARGET_H8300H or TARGET_H8300S. */ 705 if ((TARGET_H8300H || TARGET_H8300S) 706 && val == 4) 707 return "adds #4,%A0"; 708 709 if ((TARGET_H8300H || TARGET_H8300S) 710 && val == -4) 711 return "subs #4,%A0"; 712 713 if (val > 2) 714 { 715 output_asm_insn ("adds #2,%A0", operands); 716 val -= 2; 717 } 718 719 if (val < -2) 720 { 721 output_asm_insn ("subs #2,%A0", operands); 722 val += 2; 723 } 724 725 /* val should be one or two now. */ 726 if (val == 2) 727 return "adds #2,%A0"; 728 729 if (val == -2) 730 return "subs #2,%A0"; 731 732 /* val should be one now. */ 733 if (val == 1) 734 return "adds #1,%A0"; 735 736 if (val == -1) 737 return "subs #1,%A0"; 738 739 /* If not optimizing, we might be asked to add 0. */ 740 if (val == 0) 741 return ""; 742 743 /* In theory, this can't happen. */ 744 abort (); 745} 746 747/* Return true if OP is a valid call operand, and OP represents 748 an operand for a small call (4 bytes instead of 6 bytes). */ 749 750int 751small_call_insn_operand (op, mode) 752 rtx op; 753 enum machine_mode mode; 754{ 755 if (GET_CODE (op) == MEM) 756 { 757 rtx inside = XEXP (op, 0); 758 759 /* Register indirect is a small call. */ 760 if (register_operand (inside, Pmode)) 761 return 1; 762 763 /* A call through the function vector is a small 764 call too. */ 765 if (GET_CODE (inside) == SYMBOL_REF 766 && SYMBOL_REF_FLAG (inside)) 767 return 1; 768 } 769 /* Otherwise it's a large call. */ 770 return 0; 771} 772 773/* Return true if OP is a valid jump operand. */ 774 775int 776jump_address_operand (op, mode) 777 rtx op; 778 enum machine_mode mode; 779{ 780 if (GET_CODE (op) == REG) 781 return mode == Pmode; 782 783 if (GET_CODE (op) == MEM) 784 { 785 rtx inside = XEXP (op, 0); 786 if (register_operand (inside, Pmode)) 787 return 1; 788 if (CONSTANT_ADDRESS_P (inside)) 789 return 1; 790 } 791 return 0; 792} 793 794/* Recognize valid operands for bitfield instructions. */ 795 796extern int rtx_equal_function_value_matters; 797 798int 799bit_operand (op, mode) 800 rtx op; 801 enum machine_mode mode; 802{ 803 /* We can except any general operand, expept that MEM operands must 804 be limited to those that use addresses valid for the 'U' constraint. */ 805 if (!general_operand (op, mode)) 806 return 0; 807 808 /* Accept any mem during RTL generation. Otherwise, the code that does 809 insv and extzv will think that we can not handle memory. However, 810 to avoid reload problems, we only accept 'U' MEM operands after RTL 811 generation. This means that any named pattern which uses this predicate 812 must force its operands to match 'U' before emitting RTL. */ 813 814 if (GET_CODE (op) == REG) 815 return 1; 816 if (GET_CODE (op) == SUBREG) 817 return 1; 818 if (!rtx_equal_function_value_matters) 819 { 820 /* We're building rtl */ 821 return GET_CODE (op) == MEM; 822 } 823 else 824 { 825 return (GET_CODE (op) == MEM 826 && EXTRA_CONSTRAINT (op, 'U')); 827 } 828} 829 830int 831bit_memory_operand (op, mode) 832 rtx op; 833 enum machine_mode mode; 834{ 835 return (GET_CODE (op) == MEM 836 && EXTRA_CONSTRAINT (op, 'U')); 837} 838 839/* Recognize valid operators for bit test. */ 840 841int 842eq_operator (x, mode) 843 rtx x; 844 enum machine_mode mode; 845{ 846 return (GET_CODE (x) == EQ || GET_CODE (x) == NE); 847} 848 849/* Handle machine specific pragmas for compatibility with existing 850 compilers for the H8/300. 851 852 pragma saveall generates prolog/epilog code which saves and 853 restores all the registers on function entry. 854 855 pragma interrupt saves and restores all registers, and exits with 856 an rte instruction rather than an rts. A pointer to a function 857 with this attribute may be safely used in an interrupt vector. */ 858 859int 860handle_pragma (p_getc, p_ungetc, pname) 861 int (* p_getc) PROTO ((void)); 862 void (* p_ungetc) PROTO ((int)); 863 char * pname; 864{ 865 int retval = 0; 866 867 if (strcmp (pname, "interrupt") == 0) 868 interrupt_handler = retval = 1; 869 else if (strcmp (pname, "saveall") == 0) 870 pragma_saveall = retval = 1; 871 872 return retval; 873} 874 875/* If the next arg with MODE and TYPE is to be passed in a register, return 876 the rtx to represent where it is passed. CUM represents the state after 877 the last argument. NAMED is not used. */ 878 879static char *hand_list[] = 880{ 881 "__main", 882 "__cmpsi2", 883 "__divhi3", 884 "__modhi3", 885 "__udivhi3", 886 "__umodhi3", 887 "__divsi3", 888 "__modsi3", 889 "__udivsi3", 890 "__umodsi3", 891 "__mulhi3", 892 "__mulsi3", 893 "__reg_memcpy", 894 "__reg_memset", 895 "__ucmpsi2", 896 0, 897}; 898 899/* Return an RTX to represent where a value with mode MODE will be returned 900 from a function. If the result is 0, the argument is pushed. */ 901 902rtx 903function_arg (cum, mode, type, named) 904 CUMULATIVE_ARGS *cum; 905 enum machine_mode mode; 906 tree type; 907 int named; 908{ 909 rtx result = 0; 910 char *fname; 911 int regpass = 0; 912 913 /* Never pass unnamed arguments in registers. */ 914 if (!named) 915 return 0; 916 917 /* Pass 3 regs worth of data in regs when user asked on the command line. */ 918 if (TARGET_QUICKCALL) 919 regpass = 3; 920 921 /* If calling hand written assembler, use 4 regs of args. */ 922 923 if (cum->libcall) 924 { 925 char **p; 926 927 fname = XSTR (cum->libcall, 0); 928 929 /* See if this libcall is one of the hand coded ones. */ 930 931 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++) 932 ; 933 934 if (*p) 935 regpass = 4; 936 } 937 938 if (regpass) 939 { 940 int size; 941 942 if (mode == BLKmode) 943 size = int_size_in_bytes (type); 944 else 945 size = GET_MODE_SIZE (mode); 946 947 if (size + cum->nbytes > regpass * UNITS_PER_WORD) 948 { 949 result = 0; 950 } 951 else 952 { 953 switch (cum->nbytes / UNITS_PER_WORD) 954 { 955 case 0: 956 result = gen_rtx (REG, mode, 0); 957 break; 958 case 1: 959 result = gen_rtx (REG, mode, 1); 960 break; 961 case 2: 962 result = gen_rtx (REG, mode, 2); 963 break; 964 case 3: 965 result = gen_rtx (REG, mode, 3); 966 break; 967 default: 968 result = 0; 969 } 970 } 971 } 972 973 return result; 974} 975 976/* Return the cost of the rtx R with code CODE. */ 977 978int 979const_costs (r, c) 980 rtx r; 981 enum rtx_code c; 982{ 983 switch (c) 984 { 985 case CONST_INT: 986 switch (INTVAL (r)) 987 { 988 case 0: 989 case 1: 990 case 2: 991 case -1: 992 case -2: 993 return 0; 994 case 4: 995 case -4: 996 if (TARGET_H8300H || TARGET_H8300S) 997 return 0; 998 else 999 return 1; 1000 default: 1001 return 1; 1002 } 1003 1004 case CONST: 1005 case LABEL_REF: 1006 case SYMBOL_REF: 1007 return 3; 1008 1009 case CONST_DOUBLE: 1010 return 20; 1011 1012 default: 1013 return 4; 1014 } 1015} 1016 1017/* Documentation for the machine specific operand escapes: 1018 1019 'A' print rn in h8/300 mode, erN in H8/300H mode 1020 'C' print (operand - 2). 1021 'E' like s but negative. 1022 'F' like t but negative. 1023 'G' constant just the negative 1024 'M' turn a 'M' constant into its negative mod 2. 1025 'P' if operand is incing/decing sp, print .w, otherwise .b. 1026 'R' print operand as a byte:8 address if appropriate, else fall back to 1027 'X' handling. 1028 'S' print operand as a long word 1029 'T' print operand as a word 1030 'U' if operand is incing/decing sp, print l, otherwise nothing. 1031 'V' find the set bit, and print its number. 1032 'W' find the clear bit, and print its number. 1033 'X' print operand as a byte 1034 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8. 1035 If this operand isn't a register, fall back to 'R' handling. 1036 'Z' print int & 7. 1037 'b' print the bit opcode 1038 'c' print the ibit opcode 1039 'd' bcc if EQ, bcs if NE 1040 'e' first word of 32 bit value - if reg, then least reg. if mem 1041 then least. if const then most sig word 1042 'f' second word of 32 bit value - if reg, then biggest reg. if mem 1043 then +2. if const then least sig word 1044 'g' bcs if EQ, bcc if NE 1045 'j' print operand as condition code. 1046 'k' print operand as reverse condition code. 1047 's' print as low byte of 16 bit value 1048 't' print as high byte of 16 bit value 1049 'w' print as low byte of 32 bit value 1050 'x' print as 2nd byte of 32 bit value 1051 'y' print as 3rd byte of 32 bit value 1052 'z' print as msb of 32 bit value 1053*/ 1054 1055/* Return assembly language string which identifies a comparison type. */ 1056 1057static char * 1058cond_string (code) 1059 enum rtx_code code; 1060{ 1061 switch (code) 1062 { 1063 case NE: 1064 return "ne"; 1065 case EQ: 1066 return "eq"; 1067 case GE: 1068 return "ge"; 1069 case GT: 1070 return "gt"; 1071 case LE: 1072 return "le"; 1073 case LT: 1074 return "lt"; 1075 case GEU: 1076 return "hs"; 1077 case GTU: 1078 return "hi"; 1079 case LEU: 1080 return "ls"; 1081 case LTU: 1082 return "lo"; 1083 default: 1084 abort (); 1085 } 1086} 1087 1088/* Print operand X using operand code CODE to assembly language output file 1089 FILE. */ 1090 1091void 1092print_operand (file, x, code) 1093 FILE *file; 1094 rtx x; 1095 int code; 1096{ 1097 /* This is used for communication between the 'P' and 'U' codes. */ 1098 static char *last_p; 1099 1100 /* This is used for communication between codes V,W,Z and Y. */ 1101 static int bitint; 1102 1103 switch (code) 1104 { 1105 case 'A': 1106 if (GET_CODE (x) == REG) 1107 fprintf (file, "%s", h8_reg_names[REGNO (x)]); 1108 else 1109 goto def; 1110 break; 1111 case 'C': 1112 fprintf (file, "#%d", INTVAL (x) - 2); 1113 break; 1114 case 'E': 1115 switch (GET_CODE (x)) 1116 { 1117 case REG: 1118 fprintf (file, "%sl", names_big[REGNO (x)]); 1119 break; 1120 case CONST_INT: 1121 fprintf (file, "#%d", (-INTVAL (x)) & 0xff); 1122 break; 1123 default: 1124 abort (); 1125 } 1126 break; 1127 case 'F': 1128 switch (GET_CODE (x)) 1129 { 1130 case REG: 1131 fprintf (file, "%sh", names_big[REGNO (x)]); 1132 break; 1133 case CONST_INT: 1134 fprintf (file, "#%d", ((-INTVAL (x)) & 0xff00) >> 8); 1135 break; 1136 default: 1137 abort (); 1138 } 1139 break; 1140 case 'G': 1141 if (GET_CODE (x) != CONST_INT) 1142 abort (); 1143 fprintf (file, "#%d", 0xff & (-INTVAL (x))); 1144 break; 1145 case 'M': 1146 /* For 3/-3 and 4/-4, the other 2 is handled separately. */ 1147 switch (INTVAL (x)) 1148 { 1149 case 2: 1150 case 4: 1151 case -2: 1152 case -4: 1153 fprintf (file, "#2"); 1154 break; 1155 case 1: 1156 case 3: 1157 case -1: 1158 case -3: 1159 fprintf (file, "#1"); 1160 break; 1161 default: 1162 abort (); 1163 } 1164 break; 1165 case 'P': 1166 if (REGNO (XEXP (XEXP (x, 0), 0)) == STACK_POINTER_REGNUM) 1167 { 1168 last_p = ""; 1169 fprintf (file, ".w"); 1170 } 1171 else 1172 { 1173 last_p = "l"; 1174 fprintf (file, ".b"); 1175 } 1176 break; 1177 case 'S': 1178 if (GET_CODE (x) == REG) 1179 fprintf (file, "%s", names_extended[REGNO (x)]); 1180 else 1181 goto def; 1182 break; 1183 case 'T': 1184 if (GET_CODE (x) == REG) 1185 fprintf (file, "%s", names_big[REGNO (x)]); 1186 else 1187 goto def; 1188 break; 1189 case 'U': 1190 fprintf (file, "%s%s", names_big[REGNO (x)], last_p); 1191 break; 1192 case 'V': 1193 bitint = exact_log2 (INTVAL (x)); 1194 if (bitint == -1) 1195 abort (); 1196 fprintf (file, "#%d", bitint & 7); 1197 break; 1198 case 'W': 1199 bitint = exact_log2 ((~INTVAL (x)) & 0xff); 1200 if (bitint == -1) 1201 abort (); 1202 fprintf (file, "#%d", bitint & 7); 1203 break; 1204 case 'R': 1205 case 'X': 1206 if (GET_CODE (x) == REG) 1207 fprintf (file, "%s", byte_reg (x, 0)); 1208 else 1209 goto def; 1210 break; 1211 case 'Y': 1212 if (bitint == -1) 1213 abort (); 1214 if (GET_CODE (x) == REG) 1215 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l'); 1216 else 1217 print_operand (file, x, 'R'); 1218 bitint = -1; 1219 break; 1220 case 'Z': 1221 bitint = INTVAL (x); 1222 fprintf (file, "#%d", bitint & 7); 1223 break; 1224 case 'b': 1225 switch (GET_CODE (x)) 1226 { 1227 case IOR: 1228 fprintf (file, "bor"); 1229 break; 1230 case XOR: 1231 fprintf (file, "bxor"); 1232 break; 1233 case AND: 1234 fprintf (file, "band"); 1235 break; 1236 } 1237 break; 1238 case 'c': 1239 switch (GET_CODE (x)) 1240 { 1241 case IOR: 1242 fprintf (file, "bior"); 1243 break; 1244 case XOR: 1245 fprintf (file, "bixor"); 1246 break; 1247 case AND: 1248 fprintf (file, "biand"); 1249 break; 1250 } 1251 break; 1252 case 'd': 1253 switch (GET_CODE (x)) 1254 { 1255 case EQ: 1256 fprintf (file, "bcc"); 1257 break; 1258 case NE: 1259 fprintf (file, "bcs"); 1260 break; 1261 default: 1262 abort (); 1263 } 1264 break; 1265 case 'e': 1266 switch (GET_CODE (x)) 1267 { 1268 case REG: 1269 if (TARGET_H8300) 1270 fprintf (file, "%s", names_big[REGNO (x)]); 1271 else 1272 fprintf (file, "%s", names_upper_extended[REGNO (x)]); 1273 break; 1274 case MEM: 1275 x = adj_offsettable_operand (x, 0); 1276 print_operand (file, x, 0); 1277 break; 1278 case CONST_INT: 1279 fprintf (file, "#%d", ((INTVAL (x) >> 16) & 0xffff)); 1280 break; 1281 case CONST_DOUBLE: 1282 { 1283 long val; 1284 REAL_VALUE_TYPE rv; 1285 REAL_VALUE_FROM_CONST_DOUBLE (rv, x); 1286 REAL_VALUE_TO_TARGET_SINGLE (rv, val); 1287 fprintf (file, "#%d", ((val >> 16) & 0xffff)); 1288 break; 1289 } 1290 default: 1291 abort (); 1292 break; 1293 } 1294 break; 1295 case 'f': 1296 switch (GET_CODE (x)) 1297 { 1298 case REG: 1299 if (TARGET_H8300) 1300 fprintf (file, "%s", names_big[REGNO (x) + 1]); 1301 else 1302 fprintf (file, "%s", names_big[REGNO (x)]); 1303 break; 1304 case MEM: 1305 x = adj_offsettable_operand (x, 2); 1306 print_operand (file, x, 0); 1307 break; 1308 case CONST_INT: 1309 fprintf (file, "#%d", INTVAL (x) & 0xffff); 1310 break; 1311 case CONST_DOUBLE: 1312 { 1313 long val; 1314 REAL_VALUE_TYPE rv; 1315 REAL_VALUE_FROM_CONST_DOUBLE (rv, x); 1316 REAL_VALUE_TO_TARGET_SINGLE (rv, val); 1317 fprintf (file, "#%d", (val & 0xffff)); 1318 break; 1319 } 1320 default: 1321 abort (); 1322 } 1323 break; 1324 case 'g': 1325 switch (GET_CODE (x)) 1326 { 1327 case NE: 1328 fprintf (file, "bcc"); 1329 break; 1330 case EQ: 1331 fprintf (file, "bcs"); 1332 break; 1333 default: 1334 abort (); 1335 } 1336 break; 1337 case 'j': 1338 asm_fprintf (file, cond_string (GET_CODE (x))); 1339 break; 1340 case 'k': 1341 asm_fprintf (file, cond_string (reverse_condition (GET_CODE (x)))); 1342 break; 1343 case 's': 1344 if (GET_CODE (x) == CONST_INT) 1345 fprintf (file, "#%d", (INTVAL (x)) & 0xff); 1346 else 1347 fprintf (file, "%s", byte_reg (x, 0)); 1348 break; 1349 case 't': 1350 if (GET_CODE (x) == CONST_INT) 1351 fprintf (file, "#%d", (INTVAL (x) >> 8) & 0xff); 1352 else 1353 fprintf (file, "%s", byte_reg (x, 1)); 1354 break; 1355 case 'u': 1356 if (GET_CODE (x) != CONST_INT) 1357 abort (); 1358 fprintf (file, "%d", INTVAL (x)); 1359 break; 1360 case 'w': 1361 if (GET_CODE (x) == CONST_INT) 1362 fprintf (file, "#%d", INTVAL (x) & 0xff); 1363 else 1364 fprintf (file, "%s", 1365 byte_reg (x, TARGET_H8300 ? 2 : 0)); 1366 break; 1367 case 'x': 1368 if (GET_CODE (x) == CONST_INT) 1369 fprintf (file, "#%d", (INTVAL (x) >> 8) & 0xff); 1370 else 1371 fprintf (file, "%s", 1372 byte_reg (x, TARGET_H8300 ? 3 : 1)); 1373 break; 1374 case 'y': 1375 if (GET_CODE (x) == CONST_INT) 1376 fprintf (file, "#%d", (INTVAL (x) >> 16) & 0xff); 1377 else 1378 fprintf (file, "%s", byte_reg (x, 0)); 1379 break; 1380 case 'z': 1381 if (GET_CODE (x) == CONST_INT) 1382 fprintf (file, "#%d", (INTVAL (x) >> 24) & 0xff); 1383 else 1384 fprintf (file, "%s", byte_reg (x, 1)); 1385 break; 1386 1387 default: 1388 def: 1389 switch (GET_CODE (x)) 1390 { 1391 case REG: 1392 switch (GET_MODE (x)) 1393 { 1394 case QImode: 1395#if 0 /* Is it asm ("mov.b %0,r2l", ...) */ 1396 fprintf (file, "%s", byte_reg (x, 0)); 1397#else /* ... or is it asm ("mov.b %0l,r2l", ...) */ 1398 fprintf (file, "%s", names_big[REGNO (x)]); 1399#endif 1400 break; 1401 case HImode: 1402 fprintf (file, "%s", names_big[REGNO (x)]); 1403 break; 1404 case SImode: 1405 case SFmode: 1406 fprintf (file, "%s", names_extended[REGNO (x)]); 1407 break; 1408 default: 1409 abort (); 1410 } 1411 break; 1412 1413 case MEM: 1414 fprintf (file, "@"); 1415 output_address (XEXP (x, 0)); 1416 1417 /* If this is an 'R' operand (reference into the 8-bit 1418 area), then specify a symbolic address as "foo:8", 1419 otherwise if operand is still in eight bit section, use 1420 "foo:16". */ 1421 if (GET_CODE (XEXP (x, 0)) == SYMBOL_REF 1422 && SYMBOL_REF_FLAG (XEXP (x, 0))) 1423 fprintf (file, (code == 'R' ? ":8" : ":16")); 1424 else if (GET_CODE (XEXP (x, 0)) == SYMBOL_REF 1425 && TINY_DATA_NAME_P (XSTR (XEXP (x, 0), 0))) 1426 fprintf (file, ":16"); 1427 break; 1428 1429 case CONST_INT: 1430 case SYMBOL_REF: 1431 case CONST: 1432 case LABEL_REF: 1433 fprintf (file, "#"); 1434 print_operand_address (file, x); 1435 break; 1436 case CONST_DOUBLE: 1437 { 1438 long val; 1439 REAL_VALUE_TYPE rv; 1440 REAL_VALUE_FROM_CONST_DOUBLE (rv, x); 1441 REAL_VALUE_TO_TARGET_SINGLE (rv, val); 1442 fprintf (file, "#%d", val); 1443 break; 1444 } 1445 } 1446 } 1447} 1448 1449/* Output assembly language output for the address ADDR to FILE. */ 1450 1451void 1452print_operand_address (file, addr) 1453 FILE *file; 1454 rtx addr; 1455{ 1456 switch (GET_CODE (addr)) 1457 { 1458 case REG: 1459 fprintf (file, "%s", h8_reg_names[REGNO (addr)]); 1460 break; 1461 1462 case PRE_DEC: 1463 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]); 1464 break; 1465 1466 case POST_INC: 1467 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]); 1468 break; 1469 1470 case PLUS: 1471 fprintf (file, "("); 1472 if (GET_CODE (XEXP (addr, 0)) == REG) 1473 { 1474 /* reg,foo */ 1475 print_operand_address (file, XEXP (addr, 1)); 1476 fprintf (file, ","); 1477 print_operand_address (file, XEXP (addr, 0)); 1478 } 1479 else 1480 { 1481 /* foo+k */ 1482 print_operand_address (file, XEXP (addr, 0)); 1483 fprintf (file, "+"); 1484 print_operand_address (file, XEXP (addr, 1)); 1485 } 1486 fprintf (file, ")"); 1487 break; 1488 1489 case CONST_INT: 1490 { 1491 /* Since the h8/300 only has 16 bit pointers, negative values are also 1492 those >= 32768. This happens for example with pointer minus a 1493 constant. We don't want to turn (char *p - 2) into 1494 (char *p + 65534) because loop unrolling can build upon this 1495 (IE: char *p + 131068). */ 1496 int n = INTVAL (addr); 1497 if (TARGET_H8300) 1498 n = (int) (short) n; 1499 if (n < 0) 1500 /* ??? Why the special case for -ve values? */ 1501 fprintf (file, "-%d", -n); 1502 else 1503 fprintf (file, "%d", n); 1504 break; 1505 } 1506 1507 default: 1508 output_addr_const (file, addr); 1509 break; 1510 } 1511} 1512 1513/* Output all insn addresses and their sizes into the assembly language 1514 output file. This is helpful for debugging whether the length attributes 1515 in the md file are correct. This is not meant to be a user selectable 1516 option. */ 1517 1518void 1519final_prescan_insn (insn, operand, num_operands) 1520 rtx insn, *operand; 1521 int num_operands; 1522{ 1523 /* This holds the last insn address. */ 1524 static int last_insn_address = 0; 1525 1526 int uid = INSN_UID (insn); 1527 1528 if (TARGET_RTL_DUMP) 1529 { 1530 fprintf (asm_out_file, "\n****************"); 1531 print_rtl (asm_out_file, PATTERN (insn)); 1532 fprintf (asm_out_file, "\n"); 1533 } 1534 1535 if (TARGET_ADDRESSES) 1536 { 1537 fprintf (asm_out_file, "; 0x%x %d\n", insn_addresses[uid], 1538 insn_addresses[uid] - last_insn_address); 1539 last_insn_address = insn_addresses[uid]; 1540 } 1541} 1542 1543/* Prepare for an SI sized move. */ 1544 1545int 1546do_movsi (operands) 1547 rtx operands[]; 1548{ 1549 rtx src = operands[1]; 1550 rtx dst = operands[0]; 1551 if (!reload_in_progress && !reload_completed) 1552 { 1553 if (!register_operand (dst, GET_MODE (dst))) 1554 { 1555 rtx tmp = gen_reg_rtx (GET_MODE (dst)); 1556 emit_move_insn (tmp, src); 1557 operands[1] = tmp; 1558 } 1559 } 1560 return 0; 1561} 1562 1563/* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET). 1564 Define the offset between two registers, one to be eliminated, and the other 1565 its replacement, at the start of a routine. */ 1566 1567int 1568initial_offset (from, to) 1569{ 1570 int offset = 0; 1571 1572 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM) 1573 offset = UNITS_PER_WORD + frame_pointer_needed * UNITS_PER_WORD; 1574 else 1575 { 1576 int regno; 1577 1578 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) 1579 if (WORD_REG_USED (regno)) 1580 offset += UNITS_PER_WORD; 1581 1582 /* See the comments for get_frame_size. We need to round it up to 1583 STACK_BOUNDARY. */ 1584 1585 offset += ((get_frame_size () + STACK_BOUNDARY / BITS_PER_UNIT - 1) 1586 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1)); 1587 1588 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) 1589 offset += UNITS_PER_WORD; /* Skip saved PC */ 1590 } 1591 return offset; 1592} 1593 1594/* Update the condition code from the insn. */ 1595 1596int 1597notice_update_cc (body, insn) 1598 rtx body; 1599 rtx insn; 1600{ 1601 switch (get_attr_cc (insn)) 1602 { 1603 case CC_NONE: 1604 /* Insn does not affect CC at all. */ 1605 break; 1606 1607 case CC_NONE_0HIT: 1608 /* Insn does not change CC, but the 0'th operand has been changed. */ 1609 if (cc_status.value1 != 0 1610 && reg_overlap_mentioned_p (recog_operand[0], cc_status.value1)) 1611 cc_status.value1 = 0; 1612 break; 1613 1614 case CC_SET_ZN: 1615 /* Insn sets the Z,N flags of CC to recog_operand[0]. 1616 The V flag is unusable. The C flag may or may not be known but 1617 that's ok because alter_cond will change tests to use EQ/NE. */ 1618 CC_STATUS_INIT; 1619 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY; 1620 cc_status.value1 = recog_operand[0]; 1621 break; 1622 1623 case CC_SET_ZNV: 1624 /* Insn sets the Z,N,V flags of CC to recog_operand[0]. 1625 The C flag may or may not be known but that's ok because 1626 alter_cond will change tests to use EQ/NE. */ 1627 CC_STATUS_INIT; 1628 cc_status.flags |= CC_NO_CARRY; 1629 cc_status.value1 = recog_operand[0]; 1630 break; 1631 1632 case CC_COMPARE: 1633 /* The insn is a compare instruction. */ 1634 CC_STATUS_INIT; 1635 cc_status.value1 = SET_SRC (body); 1636 break; 1637 1638 case CC_CLOBBER: 1639 /* Insn doesn't leave CC in a usable state. */ 1640 CC_STATUS_INIT; 1641 break; 1642 } 1643} 1644 1645/* Recognize valid operators for bit instructions */ 1646 1647int 1648bit_operator (x, mode) 1649 rtx x; 1650 enum machine_mode mode; 1651{ 1652 enum rtx_code code = GET_CODE (x); 1653 1654 return (code == XOR 1655 || code == AND 1656 || code == IOR); 1657} 1658 1659/* Shifts. 1660 1661 We devote a fair bit of code to getting efficient shifts since we can only 1662 shift one bit at a time on the H8/300 and H8/300H and only one or two 1663 bits at a time on the H8/S. 1664 1665 The basic shift methods: 1666 1667 * loop shifts -- emit a loop using one (or two on H8/S) bit shifts; 1668 this is the default. SHIFT_LOOP 1669 1670 * inlined shifts -- emit straight line code for the shift; this is 1671 used when a straight line shift is about the same size or smaller 1672 than a loop. We allow the inline version to be slightly longer in 1673 some cases as it saves a register. SHIFT_INLINE 1674 1675 * rotate + and -- rotate the value the opposite direction, then 1676 mask off the values we don't need. This is used when only a few 1677 of the bits in the original value will survive in the shifted value. 1678 Again, this is used when it's about the same size or smaller than 1679 a loop. We allow this version to be slightly longer as it is usually 1680 much faster than a loop. SHIFT_ROT_AND 1681 1682 * swap (+ shifts) -- often it's possible to swap bytes/words to 1683 simulate a shift by 8/16. Once swapped a few inline shifts can be 1684 added if the shift count is slightly more than 8 or 16. This is used 1685 when it's about the same size or smaller than a loop. We allow this 1686 version to be slightly longer as it is usually much faster than a loop. 1687 SHIFT_SPECIAL 1688 1689 * There other oddballs. Not worth explaining. SHIFT_SPECIAL 1690 1691 1692 Here are some thoughts on what the absolutely positively best code is. 1693 "Best" here means some rational trade-off between code size and speed, 1694 where speed is more preferred but not at the expense of generating 20 insns. 1695 1696 A trailing '*' after the shift count indicates the "best" mode isn't 1697 implemented. 1698 1699 H8/300 QImode shifts 1700 1-4 - do them inline 1701 5-6 - ASHIFT | LSHIFTRT: rotate, mask off other bits 1702 ASHIFTRT: loop 1703 7 - ASHIFT | LSHIFTRT: rotate, mask off other bits 1704 ASHIFTRT: shll, subx (propagate carry bit to all bits) 1705 1706 H8/300 HImode shifts 1707 1-4 - do them inline 1708 5-6 - loop 1709 7 - shift 2nd half other way into carry. 1710 copy 1st half into 2nd half 1711 rotate 2nd half other way with carry 1712 rotate 1st half other way (no carry) 1713 mask off bits in 1st half (ASHIFT | LSHIFTRT). 1714 sign extend 1st half (ASHIFTRT) 1715 8 - move byte, zero (ASHIFT | LSHIFTRT) or sign extend other (ASHIFTRT) 1716 9-12 - do shift by 8, inline remaining shifts 1717 13-14* - ASHIFT | LSHIFTRT: rotate 3/2, mask, move byte, set other byte to 0 1718 - ASHIFTRT: loop 1719 15 - ASHIFT | LSHIFTRT: rotate 1, mask, move byte, set other byte to 0 1720 - ASHIFTRT: shll, subx, set other byte 1721 1722 H8/300 SImode shifts 1723 1-2 - do them inline 1724 3-6 - loop 1725 7* - shift other way once, move bytes into place, 1726 move carry into place (possibly with sign extension) 1727 8 - move bytes into place, zero or sign extend other 1728 9-14 - loop 1729 15* - shift other way once, move word into place, move carry into place 1730 16 - move word, zero or sign extend other 1731 17-23 - loop 1732 24* - move bytes into place, zero or sign extend other 1733 25-27 - loop 1734 28-30* - ASHIFT | LSHIFTRT: rotate top byte, mask, move byte into place, 1735 zero others 1736 ASHIFTRT: loop 1737 31 - ASHIFT | LSHIFTRT: rotate top byte, mask, move byte into place, 1738 zero others 1739 ASHIFTRT: shll top byte, subx, copy to other bytes 1740 1741 H8/300H QImode shifts (same as H8/300 QImode shifts) 1742 1-4 - do them inline 1743 5-6 - ASHIFT | LSHIFTRT: rotate, mask off other bits 1744 ASHIFTRT: loop 1745 7 - ASHIFT | LSHIFTRT: rotate, mask off other bits 1746 ASHIFTRT: shll, subx (propagate carry bit to all bits) 1747 1748 1749 H8/300H HImode shifts 1750 1-4 - do them inline 1751 5-6 - loop 1752 7 - shift 2nd half other way into carry. 1753 copy 1st half into 2nd half 1754 rotate entire word other way using carry 1755 mask off remaining bits (ASHIFT | LSHIFTRT) 1756 sign extend remaining bits (ASHIFTRT) 1757 8 - move byte, zero (ASHIFT | LSHIFTRT) or sign extend other (ASHIFTRT) 1758 9-12 - do shift by 8, inline remaining shifts 1759 13-14 - ASHIFT | LSHIFTRT: rotate 3/2, mask, move byte, set other byte to 0 1760 - ASHIFTRT: loop 1761 15 - ASHIFT | LSHIFTRT: rotate 1, mask, move byte, set other byte to 0 1762 - ASHIFTRT: shll, subx, set other byte 1763 1764 H8/300H SImode shifts 1765 (These are complicated by the fact that we don't have byte level access to 1766 the top word.) 1767 A word is: bytes 3,2,1,0 (msb -> lsb), word 1,0 (msw -> lsw) 1768 1-4 - do them inline 1769 5-14 - loop 1770 15* - shift other way once, move word into place, move carry into place 1771 (with sign extension for ASHIFTRT) 1772 16 - move word into place, zero or sign extend other 1773 17-20 - do 16bit shift, then inline remaining shifts 1774 20-23 - loop 1775 24* - ASHIFT: move byte 0(msb) to byte 1, zero byte 0, 1776 move word 0 to word 1, zero word 0 1777 LSHIFTRT: move word 1 to word 0, move byte 1 to byte 0, 1778 zero word 1, zero byte 1 1779 ASHIFTRT: move word 1 to word 0, move byte 1 to byte 0, 1780 sign extend byte 0, sign extend word 0 1781 25-27* - either loop, or 1782 do 24 bit shift, inline rest 1783 28-30 - ASHIFT: rotate 4/3/2, mask 1784 LSHIFTRT: rotate 4/3/2, mask 1785 ASHIFTRT: loop 1786 31 - shll, subx byte 0, sign extend byte 0, sign extend word 0 1787 1788 H8/S QImode shifts 1789 1-6 - do them inline 1790 7 - ASHIFT | LSHIFTRT: rotate, mask off other bits 1791 ASHIFTRT: shll, subx (propagate carry bit to all bits) 1792 1793 H8/S HImode shifts 1794 1-7 - do them inline 1795 8 - move byte, zero (ASHIFT | LSHIFTRT) or sign extend other (ASHIFTRT) 1796 9-12 - do shift by 8, inline remaining shifts 1797 13-14 - ASHIFT | LSHIFTRT: rotate 3/2, mask, move byte, set other byte to 0 1798 - ASHIFTRT: loop 1799 15 - ASHIFT | LSHIFTRT: rotate 1, mask, move byte, set other byte to 0 1800 - ASHIFTRT: shll, subx, set other byte 1801 1802 H8/S SImode shifts 1803 (These are complicated by the fact that we don't have byte level access to 1804 the top word.) 1805 A word is: bytes 3,2,1,0 (msb -> lsb), word 1,0 (msw -> lsw) 1806 1-10 - do them inline 1807 11-14 - loop 1808 15* - shift other way once, move word into place, move carry into place 1809 (with sign extension for ASHIFTRT) 1810 16 - move word into place, zero or sign extend other 1811 17-20 - do 16bit shift, then inline remaining shifts 1812 20-23 - loop 1813 24* - ASHIFT: move byte 0(msb) to byte 1, zero byte 0, 1814 move word 0 to word 1, zero word 0 1815 LSHIFTRT: move word 1 to word 0, move byte 1 to byte 0, 1816 zero word 1, zero byte 1 1817 ASHIFTRT: move word 1 to word 0, move byte 1 to byte 0, 1818 sign extend byte 0, sign extend word 0 1819 25-27* - either loop, or 1820 do 24 bit shift, inline rest 1821 28-30 - ASHIFT: rotate 4/3/2, mask 1822 LSHIFTRT: rotate 4/3/2, mask 1823 ASHIFTRT: loop 1824 31 - shll, subx byte 0, sign extend byte 0, sign extend word 0 1825 1826 Panic!!! */ 1827 1828int 1829nshift_operator (x, mode) 1830 rtx x; 1831 enum machine_mode mode; 1832{ 1833 switch (GET_CODE (x)) 1834 { 1835 case ASHIFTRT: 1836 case LSHIFTRT: 1837 case ASHIFT: 1838 return 1; 1839 1840 default: 1841 return 0; 1842 } 1843} 1844 1845/* Called from the .md file to emit code to do shifts. 1846 Returns a boolean indicating success 1847 (currently this is always TRUE). */ 1848 1849int 1850expand_a_shift (mode, code, operands) 1851 enum machine_mode mode; 1852 int code; 1853 rtx operands[]; 1854{ 1855 emit_move_insn (operands[0], operands[1]); 1856 1857 /* need a loop to get all the bits we want - we generate the 1858 code at emit time, but need to allocate a scratch reg now */ 1859 1860 emit_insn (gen_rtx 1861 (PARALLEL, VOIDmode, 1862 gen_rtvec (2, 1863 gen_rtx (SET, VOIDmode, operands[0], 1864 gen_rtx (code, mode, operands[0], operands[2])), 1865 gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, QImode, 0))))); 1866 1867 return 1; 1868} 1869 1870/* Shift algorithm determination. 1871 1872 There are various ways of doing a shift: 1873 SHIFT_INLINE: If the amount is small enough, just generate as many one-bit 1874 shifts as we need. 1875 SHIFT_ROT_AND: If the amount is large but close to either end, rotate the 1876 necessary bits into position and then set the rest to zero. 1877 SHIFT_SPECIAL: Hand crafted assembler. 1878 SHIFT_LOOP: If the above methods fail, just loop. */ 1879 1880enum shift_alg 1881{ 1882 SHIFT_INLINE, 1883 SHIFT_ROT_AND, 1884 SHIFT_SPECIAL, 1885 SHIFT_LOOP, 1886 SHIFT_MAX 1887}; 1888 1889/* Symbols of the various shifts which can be used as indices. */ 1890 1891enum shift_type 1892 { 1893 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT 1894 }; 1895 1896/* Symbols of the various modes which can be used as indices. */ 1897 1898enum shift_mode 1899 { 1900 QIshift, HIshift, SIshift 1901 }; 1902 1903/* For single bit shift insns, record assembler and what bits of the 1904 condition code are valid afterwards (represented as various CC_FOO 1905 bits, 0 means CC isn't left in a usable state). */ 1906 1907struct shift_insn 1908{ 1909 char *assembler; 1910 int cc_valid; 1911}; 1912 1913/* Assembler instruction shift table. 1914 1915 These tables are used to look up the basic shifts. 1916 They are indexed by cpu, shift_type, and mode. 1917*/ 1918 1919static const struct shift_insn shift_one[2][3][3] = 1920{ 1921/* H8/300 */ 1922 { 1923/* SHIFT_ASHIFT */ 1924 { 1925 { "shll\t%X0", CC_NO_CARRY }, 1926 { "add.w\t%T0,%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY }, 1927 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", 0 } 1928 }, 1929/* SHIFT_LSHIFTRT */ 1930 { 1931 { "shlr\t%X0", CC_NO_CARRY }, 1932 { "shlr\t%t0\n\trotxr\t%s0", 0 }, 1933 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", 0 } 1934 }, 1935/* SHIFT_ASHIFTRT */ 1936 { 1937 { "shar\t%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY }, 1938 { "shar\t%t0\n\trotxr\t%s0", 0 }, 1939 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", 0 } 1940 } 1941 }, 1942/* H8/300H */ 1943 { 1944/* SHIFT_ASHIFT */ 1945 { 1946 { "shll.b\t%X0", CC_NO_CARRY }, 1947 { "shll.w\t%T0", CC_NO_CARRY }, 1948 { "shll.l\t%S0", CC_NO_CARRY } 1949 }, 1950/* SHIFT_LSHIFTRT */ 1951 { 1952 { "shlr.b\t%X0", CC_NO_CARRY }, 1953 { "shlr.w\t%T0", CC_NO_CARRY }, 1954 { "shlr.l\t%S0", CC_NO_CARRY } 1955 }, 1956/* SHIFT_ASHIFTRT */ 1957 { 1958 { "shar.b\t%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY }, 1959 { "shar.w\t%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY }, 1960 { "shar.l\t%S0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY } 1961 } 1962 } 1963}; 1964 1965static const struct shift_insn shift_two[3][3] = 1966{ 1967/* SHIFT_ASHIFT */ 1968 { 1969 { "shll.b\t#2,%X0", CC_NO_CARRY }, 1970 { "shll.w\t#2,%T0", CC_NO_CARRY }, 1971 { "shll.l\t#2,%S0", CC_NO_CARRY } 1972 }, 1973/* SHIFT_LSHIFTRT */ 1974 { 1975 { "shlr.b\t#2,%X0", CC_NO_CARRY }, 1976 { "shlr.w\t#2,%T0", CC_NO_CARRY }, 1977 { "shlr.l\t#2,%S0", CC_NO_CARRY } 1978 }, 1979/* SHIFT_ASHIFTRT */ 1980 { 1981 { "shar.b\t#2,%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY }, 1982 { "shar.w\t#2,%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY }, 1983 { "shar.l\t#2,%S0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY } 1984 } 1985}; 1986 1987/* Rotates are organized by which shift they'll be used in implementing. 1988 There's no need to record whether the cc is valid afterwards because 1989 it is the AND insn that will decide this. */ 1990 1991static const char *const rotate_one[2][3][3] = 1992{ 1993/* H8/300 */ 1994 { 1995/* SHIFT_ASHIFT */ 1996 { 1997 "rotr\t%X0", 1998 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0", 1999 0 2000 }, 2001/* SHIFT_LSHIFTRT */ 2002 { 2003 "rotl\t%X0", 2004 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0", 2005 0 2006 }, 2007/* SHIFT_ASHIFTRT */ 2008 { 2009 "rotl\t%X0", 2010 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0", 2011 0 2012 } 2013 }, 2014/* H8/300H */ 2015 { 2016/* SHIFT_ASHIFT */ 2017 { 2018 "rotr.b\t%X0", 2019 "rotr.w\t%T0", 2020 "rotr.l\t%S0" 2021 }, 2022/* SHIFT_LSHIFTRT */ 2023 { 2024 "rotl.b\t%X0", 2025 "rotl.w\t%T0", 2026 "rotl.l\t%S0" 2027 }, 2028/* SHIFT_ASHIFTRT */ 2029 { 2030 "rotl.b\t%X0", 2031 "rotl.w\t%T0", 2032 "rotl.l\t%S0" 2033 } 2034 } 2035}; 2036 2037static const char *const rotate_two[3][3] = 2038{ 2039/* SHIFT_ASHIFT */ 2040 { 2041 "rotr.b\t#2,%X0", 2042 "rotr.w\t#2,%T0", 2043 "rotr.l\t#2,%S0" 2044 }, 2045/* SHIFT_LSHIFTRT */ 2046 { 2047 "rotl.b\t#2,%X0", 2048 "rotl.w\t#2,%T0", 2049 "rotl.l\t#2,%S0" 2050 }, 2051/* SHIFT_ASHIFTRT */ 2052 { 2053 "rotl.b\t#2,%X0", 2054 "rotl.w\t#2,%T0", 2055 "rotl.l\t#2,%S0" 2056 } 2057}; 2058 2059/* Given CPU, MODE, SHIFT_TYPE, and shift count COUNT, determine the best 2060 algorithm for doing the shift. The assembler code is stored in ASSEMBLER. 2061 We don't achieve maximum efficiency in all cases, but the hooks are here 2062 to do so. 2063 2064 For now we just use lots of switch statements. Since we don't even come 2065 close to supporting all the cases, this is simplest. If this function ever 2066 gets too big, perhaps resort to a more table based lookup. Of course, 2067 at this point you may just wish to do it all in rtl. 2068 2069 WARNING: The constraints on insns shiftbyn_QI/HI/SI assume shifts of 2070 1,2,3,4 will be inlined (1,2 for SI). */ 2071 2072static enum shift_alg 2073get_shift_alg (cpu, shift_type, mode, count, assembler_p, 2074 assembler2_p, cc_valid_p) 2075 enum attr_cpu cpu; 2076 enum shift_type shift_type; 2077 enum machine_mode mode; 2078 int count; 2079 const char **assembler_p; 2080 const char **assembler2_p; 2081 int *cc_valid_p; 2082{ 2083 /* The default is to loop. */ 2084 enum shift_alg alg = SHIFT_LOOP; 2085 enum shift_mode shift_mode; 2086 2087 /* We don't handle negative shifts or shifts greater than the word size, 2088 they should have been handled already. */ 2089 2090 if (count < 0 || count > GET_MODE_BITSIZE (mode)) 2091 abort (); 2092 2093 switch (mode) 2094 { 2095 case QImode: 2096 shift_mode = QIshift; 2097 break; 2098 case HImode: 2099 shift_mode = HIshift; 2100 break; 2101 case SImode: 2102 shift_mode = SIshift; 2103 break; 2104 default: 2105 abort (); 2106 } 2107 2108 /* Assume either SHIFT_LOOP or SHIFT_INLINE. 2109 It is up to the caller to know that looping clobbers cc. */ 2110 *assembler_p = shift_one[cpu][shift_type][shift_mode].assembler; 2111 if (TARGET_H8300S) 2112 *assembler2_p = shift_two[shift_type][shift_mode].assembler; 2113 else 2114 *assembler2_p = NULL; 2115 *cc_valid_p = shift_one[cpu][shift_type][shift_mode].cc_valid; 2116 2117 /* Now look for cases we want to optimize. */ 2118 2119 switch (shift_mode) 2120 { 2121 case QIshift: 2122 if (count <= 4) 2123 return SHIFT_INLINE; 2124 else 2125 { 2126 /* Shift by 5/6 are only 3 insns on the H8/S, so it's just as 2127 fast as SHIFT_ROT_AND, plus CC is valid. */ 2128 if (TARGET_H8300S && count <= 6) 2129 return SHIFT_INLINE; 2130 2131 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated 2132 through the entire value. */ 2133 if (shift_type == SHIFT_ASHIFTRT && count == 7) 2134 { 2135 *assembler_p = "shll\t%X0\n\tsubx\t%X0,%X0"; 2136 *cc_valid_p = 0; 2137 return SHIFT_SPECIAL; 2138 } 2139 2140 /* Other ASHIFTRTs are too much of a pain. */ 2141 if (shift_type == SHIFT_ASHIFTRT) 2142 return SHIFT_LOOP; 2143 2144 /* Other shifts by 5, 6, or 7 bits use SHIFT_ROT_AND. */ 2145 *assembler_p = rotate_one[cpu][shift_type][shift_mode]; 2146 if (TARGET_H8300S) 2147 *assembler2_p = rotate_two[shift_type][shift_mode]; 2148 *cc_valid_p = 0; 2149 return SHIFT_ROT_AND; 2150 } 2151 2152 case HIshift: 2153 if (count <= 4) 2154 return SHIFT_INLINE; 2155 else if (TARGET_H8300S && count <= 7) 2156 return SHIFT_INLINE; 2157 else if (count == 7) 2158 { 2159 if (shift_type == SHIFT_ASHIFT && TARGET_H8300) 2160 { 2161 *assembler_p = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0"; 2162 *cc_valid_p = 0; 2163 return SHIFT_SPECIAL; 2164 } 2165 2166 if (shift_type == SHIFT_ASHIFT && TARGET_H8300H) 2167 { 2168 *assembler_p = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0"; 2169 *cc_valid_p = 0; 2170 return SHIFT_SPECIAL; 2171 } 2172 2173 if (shift_type == SHIFT_LSHIFTRT && TARGET_H8300) 2174 { 2175 *assembler_p = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0"; 2176 *cc_valid_p = 0; 2177 return SHIFT_SPECIAL; 2178 } 2179 2180 if (shift_type == SHIFT_LSHIFTRT && TARGET_H8300H) 2181 { 2182 *assembler_p = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0"; 2183 *cc_valid_p = 0; 2184 return SHIFT_SPECIAL; 2185 } 2186 2187 if (shift_type == SHIFT_ASHIFTRT) 2188 { 2189 *assembler_p = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0"; 2190 *cc_valid_p = 0; 2191 return SHIFT_SPECIAL; 2192 } 2193 } 2194 else if (count == 8) 2195 { 2196 switch (shift_type) 2197 { 2198 case SHIFT_ASHIFT: 2199 *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0"; 2200 *cc_valid_p = 0; 2201 return SHIFT_SPECIAL; 2202 case SHIFT_LSHIFTRT: 2203 *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0"; 2204 *cc_valid_p = 0; 2205 return SHIFT_SPECIAL; 2206 case SHIFT_ASHIFTRT: 2207 if (TARGET_H8300) 2208 *assembler_p = "mov.b\t%t0,%s0\n\tshll\t%t0\n\tsubx\t%t0,%t0\t"; 2209 else 2210 *assembler_p = "mov.b\t%t0,%s0\n\texts.w\t%T0"; 2211 *cc_valid_p = 0; 2212 return SHIFT_SPECIAL; 2213 } 2214 } 2215 else if (count == 9) 2216 { 2217 switch (shift_type) 2218 { 2219 case SHIFT_ASHIFT: 2220 *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t%t0"; 2221 *cc_valid_p = 0; 2222 return SHIFT_SPECIAL; 2223 case SHIFT_LSHIFTRT: 2224 *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t%s0"; 2225 *cc_valid_p = 0; 2226 return SHIFT_SPECIAL; 2227 case SHIFT_ASHIFTRT: 2228 if (TARGET_H8300) 2229 *assembler_p = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0\n\tshar.b\t%s0"; 2230 else 2231 *assembler_p = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t%s0"; 2232 *cc_valid_p = 0; 2233 return SHIFT_SPECIAL; 2234 } 2235 } 2236 else if (count == 10) 2237 { 2238 switch (shift_type) 2239 { 2240 case SHIFT_ASHIFT: 2241 if (TARGET_H8300S) 2242 *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t#2,%t0\n\t"; 2243 else 2244 *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t%t0\n\tshal.b\t%t0"; 2245 *cc_valid_p = 0; 2246 return SHIFT_SPECIAL; 2247 case SHIFT_LSHIFTRT: 2248 if (TARGET_H8300S) 2249 *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t#2,%s0"; 2250 else 2251 *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t%s0\n\tshlr.b\t%s0"; 2252 *cc_valid_p = 0; 2253 return SHIFT_SPECIAL; 2254 case SHIFT_ASHIFTRT: 2255 if (TARGET_H8300) 2256 *assembler_p = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0\n\tshar.b\t%s0\n\tshar.b\t%s0"; 2257 else if (TARGET_H8300H) 2258 *assembler_p = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t%s0\n\tshar.b\t%s0"; 2259 else if (TARGET_H8300S) 2260 *assembler_p = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t#2,%s0"; 2261 *cc_valid_p = 0; 2262 return SHIFT_SPECIAL; 2263 } 2264 } 2265 else if (count == 11) 2266 { 2267 switch (shift_type) 2268 { 2269 case SHIFT_ASHIFT: 2270 if (TARGET_H8300S) 2271 *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t#2,%t0\n\tshal.b\t%t0"; 2272 else 2273 *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t%t0\n\tshal.b\t%t0\n\tshal.b\t%t0"; 2274 *cc_valid_p = 0; 2275 return SHIFT_SPECIAL; 2276 case SHIFT_LSHIFTRT: 2277 if (TARGET_H8300S) 2278 *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t#2,%s0\n\tshlr.b\t%s0"; 2279 else 2280 *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t%s0\n\tshlr.b\t%s0\n\tshlr.b\t%s0"; 2281 *cc_valid_p = 0; 2282 return SHIFT_SPECIAL; 2283 case SHIFT_ASHIFTRT: 2284 if (TARGET_H8300) 2285 *assembler_p = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0"; 2286 else if (TARGET_H8300H) 2287 *assembler_p = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0"; 2288 else if (TARGET_H8300S) 2289 *assembler_p = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t#2,%s0\n\tshar.b\t%s0"; 2290 *cc_valid_p = 0; 2291 return SHIFT_SPECIAL; 2292 } 2293 } 2294 else if (count == 12) 2295 { 2296 switch (shift_type) 2297 { 2298 case SHIFT_ASHIFT: 2299 if (TARGET_H8300S) 2300 *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t#2,%t0\n\tshal.b\t#2,%t0"; 2301 else 2302 *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t%t0\n\tshal.b\t%t0\n\tshal.b\t%t0\n\tshal.b\t%t0"; 2303 *cc_valid_p = 0; 2304 return SHIFT_SPECIAL; 2305 case SHIFT_LSHIFTRT: 2306 if (TARGET_H8300S) 2307 *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t#2,%s0\n\tshlr.b\t#2,%s0"; 2308 else 2309 *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t%s0\n\tshlr.b\t%s0\n\tshlr.b\t%s0\n\tshlr.b\t%s0"; 2310 *cc_valid_p = 0; 2311 return SHIFT_SPECIAL; 2312 case SHIFT_ASHIFTRT: 2313 if (TARGET_H8300) 2314 *assembler_p = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0"; 2315 else if (TARGET_H8300H) 2316 *assembler_p = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0"; 2317 else if (TARGET_H8300S) 2318 *assembler_p = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t#2,%s0\n\tshar.b\t#2,%s0"; 2319 *cc_valid_p = 0; 2320 return SHIFT_SPECIAL; 2321 } 2322 } 2323 else if (!TARGET_H8300 && (count == 13 || count == 14) 2324 || count == 15) 2325 { 2326 if (count == 15 && shift_type == SHIFT_ASHIFTRT) 2327 { 2328 *assembler_p = "shll\t%t0,%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0"; 2329 *cc_valid_p = 0; 2330 return SHIFT_SPECIAL; 2331 } 2332 else if (shift_type != SHIFT_ASHIFTRT) 2333 { 2334 *assembler_p = rotate_one[cpu][shift_type][shift_mode]; 2335 if (TARGET_H8300S) 2336 *assembler2_p = rotate_two[shift_type][shift_mode]; 2337 else 2338 *assembler2_p = NULL; 2339 *cc_valid_p = 0; 2340 return SHIFT_ROT_AND; 2341 } 2342 } 2343 break; 2344 2345 case SIshift: 2346 if (count <= (TARGET_H8300 ? 2 : 4)) 2347 return SHIFT_INLINE; 2348 else if (TARGET_H8300S && count <= 10) 2349 return SHIFT_INLINE; 2350 else if (count == 8 && TARGET_H8300) 2351 { 2352 switch (shift_type) 2353 { 2354 case SHIFT_ASHIFT: 2355 *assembler_p = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0"; 2356 *cc_valid_p = 0; 2357 return SHIFT_SPECIAL; 2358 case SHIFT_LSHIFTRT: 2359 *assembler_p = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0"; 2360 *cc_valid_p = 0; 2361 return SHIFT_SPECIAL; 2362 case SHIFT_ASHIFTRT: 2363 *assembler_p = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0"; 2364 *cc_valid_p = 0; 2365 return SHIFT_SPECIAL; 2366 } 2367 } 2368 else if (count == 8 && !TARGET_H8300) 2369 { 2370 switch (shift_type) 2371 { 2372 case SHIFT_ASHIFT: 2373 *assembler_p = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0"; 2374 *cc_valid_p = 0; 2375 return SHIFT_SPECIAL; 2376 case SHIFT_LSHIFTRT: 2377 *assembler_p = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0"; 2378 *cc_valid_p = 0; 2379 return SHIFT_SPECIAL; 2380 case SHIFT_ASHIFTRT: 2381 *assembler_p = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0"; 2382 *cc_valid_p = 0; 2383 return SHIFT_SPECIAL; 2384 } 2385 } 2386 else if (count == 16) 2387 { 2388 switch (shift_type) 2389 { 2390 case SHIFT_ASHIFT: 2391 *assembler_p = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0"; 2392 *cc_valid_p = 0; 2393 return SHIFT_SPECIAL; 2394 case SHIFT_LSHIFTRT: 2395 *assembler_p = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0"; 2396 *cc_valid_p = 0; 2397 return SHIFT_SPECIAL; 2398 case SHIFT_ASHIFTRT: 2399 if (TARGET_H8300) 2400 *assembler_p = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0"; 2401 else 2402 *assembler_p = "mov.w\t%e0,%f0\n\texts.l\t%S0"; 2403 *cc_valid_p = 0; 2404 return SHIFT_SPECIAL; 2405 } 2406 } 2407 else if (count == 17 && !TARGET_H8300) 2408 { 2409 switch (shift_type) 2410 { 2411 case SHIFT_ASHIFT: 2412 *assembler_p = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t%S0"; 2413 *cc_valid_p = 0; 2414 return SHIFT_SPECIAL; 2415 case SHIFT_LSHIFTRT: 2416 *assembler_p = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t%S0"; 2417 *cc_valid_p = 0; 2418 return SHIFT_SPECIAL; 2419 case SHIFT_ASHIFTRT: 2420 *assembler_p = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t%S0"; 2421 *cc_valid_p = 0; 2422 return SHIFT_SPECIAL; 2423 } 2424 } 2425 else if (count == 18 && !TARGET_H8300) 2426 { 2427 switch (shift_type) 2428 { 2429 case SHIFT_ASHIFT: 2430 if (TARGET_H8300S) 2431 *assembler_p = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t#2,%S0"; 2432 else 2433 *assembler_p = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t%S0\n\tshll.l\t%S0"; 2434 *cc_valid_p = 0; 2435 return SHIFT_SPECIAL; 2436 case SHIFT_LSHIFTRT: 2437 if (TARGET_H8300S) 2438 *assembler_p = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t#2,%S0"; 2439 else 2440 *assembler_p = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t%S0\n\tshlr.l\t%S0"; 2441 *cc_valid_p = 0; 2442 return SHIFT_SPECIAL; 2443 case SHIFT_ASHIFTRT: 2444 if (TARGET_H8300S) 2445 *assembler_p = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t#2,%S0"; 2446 else 2447 *assembler_p = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t%S0\n\tshar.l\t%S0"; 2448 *cc_valid_p = 0; 2449 return SHIFT_SPECIAL; 2450 } 2451 } 2452 else if (count == 19 && !TARGET_H8300) 2453 { 2454 switch (shift_type) 2455 { 2456 case SHIFT_ASHIFT: 2457 if (TARGET_H8300S) 2458 *assembler_p = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t#2,%S0\n\tshll.l\t%S0"; 2459 else 2460 *assembler_p = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t%S0\n\tshll.l\t%S0\n\tshll.l\t%S0"; 2461 *cc_valid_p = 0; 2462 return SHIFT_SPECIAL; 2463 case SHIFT_LSHIFTRT: 2464 if (TARGET_H8300S) 2465 *assembler_p = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t#2,%S0\n\tshlr.l\t%S0"; 2466 else 2467 *assembler_p = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t%S0\n\tshlr.l\t%S0\n\tshlr.l\t%S0"; 2468 *cc_valid_p = 0; 2469 return SHIFT_SPECIAL; 2470 case SHIFT_ASHIFTRT: 2471 if (TARGET_H8300S) 2472 *assembler_p = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t#2,%S0\n\tshar.l\t%S0"; 2473 else 2474 *assembler_p = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t%S0\n\tshar.l\t%S0\n\tshar.l\t%S0"; 2475 *cc_valid_p = 0; 2476 return SHIFT_SPECIAL; 2477 } 2478 } 2479 else if (count == 20 && TARGET_H8300S) 2480 { 2481 switch (shift_type) 2482 { 2483 case SHIFT_ASHIFT: 2484 *assembler_p = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t#2,%S0\n\tshll.l\t#2,%S0"; 2485 *cc_valid_p = 0; 2486 return SHIFT_SPECIAL; 2487 case SHIFT_LSHIFTRT: 2488 *assembler_p = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t#2,%S0\n\tshlr.l\t#2,%S0"; 2489 *cc_valid_p = 0; 2490 return SHIFT_SPECIAL; 2491 case SHIFT_ASHIFTRT: 2492 *assembler_p = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t#2,%S0\n\tshar.l\t#2,%S0"; 2493 *cc_valid_p = 0; 2494 return SHIFT_SPECIAL; 2495 } 2496 } 2497 else if (count == 24 && !TARGET_H8300) 2498 { 2499 switch (shift_type) 2500 { 2501 case SHIFT_ASHIFT: 2502 *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0"; 2503 *cc_valid_p = 0; 2504 return SHIFT_SPECIAL; 2505 case SHIFT_LSHIFTRT: 2506 *assembler_p = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0"; 2507 *cc_valid_p = 0; 2508 return SHIFT_SPECIAL; 2509 case SHIFT_ASHIFTRT: 2510 *assembler_p = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0"; 2511 *cc_valid_p = 0; 2512 return SHIFT_SPECIAL; 2513 } 2514 } 2515 else if (count >= 28 && count <= 30 && !TARGET_H8300) 2516 { 2517 if (shift_type == SHIFT_ASHIFTRT) 2518 { 2519 return SHIFT_LOOP; 2520 } 2521 else 2522 { 2523 *assembler_p = rotate_one[cpu][shift_type][shift_mode]; 2524 if (TARGET_H8300S) 2525 *assembler2_p = rotate_two[shift_type][shift_mode]; 2526 else 2527 *assembler2_p = NULL; 2528 *cc_valid_p = 0; 2529 return SHIFT_ROT_AND; 2530 } 2531 } 2532 else if (count == 31) 2533 { 2534 if (shift_type == SHIFT_ASHIFTRT) 2535 { 2536 if (TARGET_H8300) 2537 *assembler_p = "shll\t%z0\n\tsubx %w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0"; 2538 else 2539 *assembler_p = "shll\t%e0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0"; 2540 *cc_valid_p = 0; 2541 return SHIFT_SPECIAL; 2542 } 2543 else 2544 { 2545 if (TARGET_H8300) 2546 { 2547 if (shift_type == SHIFT_ASHIFT) 2548 *assembler_p = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0"; 2549 else 2550 *assembler_p = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0"; 2551 *cc_valid_p = 0; 2552 return SHIFT_SPECIAL; 2553 } 2554 else 2555 { 2556 *assembler_p = rotate_one[cpu][shift_type][shift_mode]; 2557 if (TARGET_H8300S) 2558 *assembler2_p = rotate_two[shift_type][shift_mode]; 2559 else 2560 *assembler2_p = NULL; 2561 *cc_valid_p = 0; 2562 return SHIFT_ROT_AND; 2563 } 2564 } 2565 } 2566 break; 2567 2568 default: 2569 abort (); 2570 } 2571 2572 return alg; 2573} 2574 2575/* Emit the assembler code for doing shifts. */ 2576 2577char * 2578emit_a_shift (insn, operands) 2579 rtx insn; 2580 rtx *operands; 2581{ 2582 static int loopend_lab; 2583 char *assembler; 2584 char *assembler2; 2585 int cc_valid; 2586 rtx inside = PATTERN (insn); 2587 rtx shift = operands[3]; 2588 enum machine_mode mode = GET_MODE (shift); 2589 enum rtx_code code = GET_CODE (shift); 2590 enum shift_type shift_type; 2591 enum shift_mode shift_mode; 2592 2593 loopend_lab++; 2594 2595 switch (mode) 2596 { 2597 case QImode: 2598 shift_mode = QIshift; 2599 break; 2600 case HImode: 2601 shift_mode = HIshift; 2602 break; 2603 case SImode: 2604 shift_mode = SIshift; 2605 break; 2606 default: 2607 abort (); 2608 } 2609 2610 switch (code) 2611 { 2612 case ASHIFTRT: 2613 shift_type = SHIFT_ASHIFTRT; 2614 break; 2615 case LSHIFTRT: 2616 shift_type = SHIFT_LSHIFTRT; 2617 break; 2618 case ASHIFT: 2619 shift_type = SHIFT_ASHIFT; 2620 break; 2621 default: 2622 abort (); 2623 } 2624 2625 if (GET_CODE (operands[2]) != CONST_INT) 2626 { 2627 /* Indexing by reg, so have to loop and test at top */ 2628 output_asm_insn ("mov.b %X2,%X4", operands); 2629 fprintf (asm_out_file, "\tble .Lle%d\n", loopend_lab); 2630 2631 /* Get the assembler code to do one shift. */ 2632 get_shift_alg (cpu_type, shift_type, mode, 1, &assembler, 2633 &assembler2, &cc_valid); 2634 } 2635 else 2636 { 2637 int n = INTVAL (operands[2]); 2638 enum shift_alg alg; 2639 2640 /* If the count is negative, make it 0. */ 2641 if (n < 0) 2642 n = 0; 2643 /* If the count is too big, truncate it. 2644 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to 2645 do the intuitive thing. */ 2646 else if (n > GET_MODE_BITSIZE (mode)) 2647 n = GET_MODE_BITSIZE (mode); 2648 2649 alg = get_shift_alg (cpu_type, shift_type, mode, n, &assembler, 2650 &assembler2, &cc_valid); 2651 2652 switch (alg) 2653 { 2654 case SHIFT_INLINE: 2655 /* Emit two bit shifts first. */ 2656 while (n > 1 && assembler2 != NULL) 2657 { 2658 output_asm_insn (assembler2, operands); 2659 n -= 2; 2660 } 2661 2662 /* Now emit one bit shifts for any residual. */ 2663 while (n > 0) 2664 { 2665 output_asm_insn (assembler, operands); 2666 n -= 1; 2667 } 2668 2669 /* Keep track of CC. */ 2670 if (cc_valid) 2671 { 2672 cc_status.value1 = operands[0]; 2673 cc_status.flags |= cc_valid; 2674 } 2675 return ""; 2676 2677 case SHIFT_ROT_AND: 2678 { 2679 int m = GET_MODE_BITSIZE (mode) - n; 2680 int mask = (shift_type == SHIFT_ASHIFT 2681 ? ((1 << GET_MODE_BITSIZE (mode) - n) - 1) << n 2682 : (1 << GET_MODE_BITSIZE (mode) - n) - 1); 2683 char insn_buf[200]; 2684 /* Not all possibilities of rotate are supported. They shouldn't 2685 be generated, but let's watch for 'em. */ 2686 if (assembler == 0) 2687 abort (); 2688 2689 /* Emit two bit rotates first. */ 2690 while (m > 1 && assembler2 != NULL) 2691 { 2692 output_asm_insn (assembler2, operands); 2693 m -= 2; 2694 } 2695 2696 /* Now single bit rotates for any residual. */ 2697 while (m > 0) 2698 { 2699 output_asm_insn (assembler, operands); 2700 m -= 1; 2701 } 2702 2703 /* Now mask off the high bits. */ 2704 if (TARGET_H8300) 2705 { 2706 switch (mode) 2707 { 2708 case QImode: 2709 sprintf (insn_buf, "and #%d,%%X0", 2710 mask, n); 2711 cc_status.value1 = operands[0]; 2712 cc_status.flags |= CC_NO_CARRY; 2713 break; 2714 case HImode: 2715 sprintf (insn_buf, "and #%d,%%s0\n\tand #%d,%%t0", 2716 mask & 255, mask >> 8, n); 2717 break; 2718 case SImode: 2719 abort (); 2720 } 2721 } 2722 else 2723 { 2724 sprintf (insn_buf, "and.%c #%d,%%%c0", 2725 "bwl"[shift_mode], mask, 2726 mode == QImode ? 'X' : mode == HImode ? 'T' : 'S'); 2727 cc_status.value1 = operands[0]; 2728 cc_status.flags |= CC_NO_CARRY; 2729 } 2730 output_asm_insn (insn_buf, operands); 2731 return ""; 2732 } 2733 case SHIFT_SPECIAL: 2734 output_asm_insn (assembler, operands); 2735 return ""; 2736 } 2737 2738 /* A loop to shift by a "large" constant value. 2739 If we have shift-by-2 insns, use them. */ 2740 if (assembler2 != NULL) 2741 { 2742 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2, 2743 names_big[REGNO (operands[4])]); 2744 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab); 2745 output_asm_insn (assembler2, operands); 2746 output_asm_insn ("add #0xff,%X4", operands); 2747 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab); 2748 if (n % 2) 2749 output_asm_insn (assembler, operands); 2750 return ""; 2751 } 2752 else 2753 { 2754 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n, 2755 names_big[REGNO (operands[4])]); 2756 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab); 2757 output_asm_insn (assembler, operands); 2758 output_asm_insn ("add #0xff,%X4", operands); 2759 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab); 2760 return ""; 2761 } 2762 } 2763 2764 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab); 2765 output_asm_insn (assembler, operands); 2766 output_asm_insn ("add #0xff,%X4", operands); 2767 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab); 2768 fprintf (asm_out_file, ".Lle%d:\n", loopend_lab); 2769 2770 return ""; 2771} 2772 2773/* Fix the operands of a gen_xxx so that it could become a bit 2774 operating insn. */ 2775 2776int 2777fix_bit_operand (operands, what, type) 2778 rtx *operands; 2779 char what; 2780 enum rtx_code type; 2781{ 2782 /* The bit_operand predicate accepts any memory during RTL generation, but 2783 only 'U' memory afterwards, so if this is a MEM operand, we must force 2784 it to be valid for 'U' by reloading the address. */ 2785 2786 if (GET_CODE (operands[2]) == CONST_INT) 2787 { 2788 if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), what)) 2789 { 2790 /* Ok to have a memory dest. */ 2791 if (GET_CODE (operands[0]) == MEM && !EXTRA_CONSTRAINT (operands[0], 'U')) 2792 { 2793 rtx mem; 2794 mem = gen_rtx (MEM, GET_MODE (operands[0]), 2795 copy_to_mode_reg (Pmode, XEXP (operands[0], 0))); 2796 RTX_UNCHANGING_P (mem) = RTX_UNCHANGING_P (operands[0]); 2797 MEM_COPY_ATTRIBUTES (mem, operands[0]); 2798 operands[0] = mem; 2799 } 2800 2801 if (GET_CODE (operands[1]) == MEM && !EXTRA_CONSTRAINT (operands[1], 'U')) 2802 { 2803 rtx mem; 2804 mem = gen_rtx (MEM, GET_MODE (operands[1]), 2805 copy_to_mode_reg (Pmode, XEXP (operands[1], 0))); 2806 RTX_UNCHANGING_P (mem) = RTX_UNCHANGING_P (operands[1]); 2807 MEM_COPY_ATTRIBUTES (mem, operands[0]); 2808 operands[1] = mem; 2809 } 2810 return 0; 2811 } 2812 } 2813 2814 /* Dest and src op must be register. */ 2815 2816 operands[1] = force_reg (QImode, operands[1]); 2817 { 2818 rtx res = gen_reg_rtx (QImode); 2819 emit_insn (gen_rtx (SET, VOIDmode, res, gen_rtx (type, QImode, operands[1], operands[2]))); 2820 emit_insn (gen_rtx (SET, VOIDmode, operands[0], res)); 2821 } 2822 return 1; 2823} 2824 2825/* Return nonzero if FUNC is an interrupt function as specified 2826 by the "interrupt" attribute. */ 2827 2828static int 2829h8300_interrupt_function_p (func) 2830 tree func; 2831{ 2832 tree a; 2833 2834 if (TREE_CODE (func) != FUNCTION_DECL) 2835 return 0; 2836 2837 a = lookup_attribute ("interrupt_handler", DECL_MACHINE_ATTRIBUTES (func)); 2838 return a != NULL_TREE; 2839} 2840 2841/* Return nonzero if FUNC is an OS_Task function as specified 2842 by the "OS_Task" attribute. */ 2843 2844static int 2845h8300_os_task_function_p (func) 2846 tree func; 2847{ 2848 tree a; 2849 2850 if (TREE_CODE (func) != FUNCTION_DECL) 2851 return 0; 2852 2853 a = lookup_attribute ("OS_Task", DECL_MACHINE_ATTRIBUTES (func)); 2854 return a != NULL_TREE; 2855} 2856 2857/* Return nonzero if FUNC is a monitor function as specified 2858 by the "monitor" attribute. */ 2859 2860static int 2861h8300_monitor_function_p (func) 2862 tree func; 2863{ 2864 tree a; 2865 2866 if (TREE_CODE (func) != FUNCTION_DECL) 2867 return 0; 2868 2869 a = lookup_attribute ("monitor", DECL_MACHINE_ATTRIBUTES (func)); 2870 return a != NULL_TREE; 2871} 2872 2873/* Return nonzero if FUNC is a function that should be called 2874 through the function vector. */ 2875 2876int 2877h8300_funcvec_function_p (func) 2878 tree func; 2879{ 2880 tree a; 2881 2882 if (TREE_CODE (func) != FUNCTION_DECL) 2883 return 0; 2884 2885 a = lookup_attribute ("function_vector", DECL_MACHINE_ATTRIBUTES (func)); 2886 return a != NULL_TREE; 2887} 2888 2889/* Return nonzero if DECL is a variable that's in the eight bit 2890 data area. */ 2891 2892int 2893h8300_eightbit_data_p (decl) 2894 tree decl; 2895{ 2896 tree a; 2897 2898 if (TREE_CODE (decl) != VAR_DECL) 2899 return 0; 2900 2901 a = lookup_attribute ("eightbit_data", DECL_MACHINE_ATTRIBUTES (decl)); 2902 return a != NULL_TREE; 2903} 2904 2905/* Return nonzero if DECL is a variable that's in the tiny 2906 data area. */ 2907 2908int 2909h8300_tiny_data_p (decl) 2910 tree decl; 2911{ 2912 tree a; 2913 2914 if (TREE_CODE (decl) != VAR_DECL) 2915 return 0; 2916 2917 a = lookup_attribute ("tiny_data", DECL_MACHINE_ATTRIBUTES (decl)); 2918 return a != NULL_TREE; 2919} 2920 2921/* Return nonzero if ATTR is a valid attribute for DECL. 2922 ATTRIBUTES are any existing attributes and ARGS are the arguments 2923 supplied with ATTR. 2924 2925 Supported attributes: 2926 2927 interrupt_handler: output a prologue and epilogue suitable for an 2928 interrupt handler. 2929 2930 function_vector: This function should be called through the 2931 function vector. 2932 2933 eightbit_data: This variable lives in the 8-bit data area and can 2934 be referenced with 8-bit absolute memory addresses. 2935 2936 tiny_data: This variable lives in the tiny data area and can be 2937 referenced with 16-bit absolute memory references. */ 2938 2939int 2940h8300_valid_machine_decl_attribute (decl, attributes, attr, args) 2941 tree decl; 2942 tree attributes; 2943 tree attr; 2944 tree args; 2945{ 2946 if (args != NULL_TREE) 2947 return 0; 2948 2949 if (is_attribute_p ("interrupt_handler", attr) 2950 || is_attribute_p ("OS_Task", attr) 2951 || is_attribute_p ("monitor", attr) 2952 || is_attribute_p ("function_vector", attr)) 2953 return TREE_CODE (decl) == FUNCTION_DECL; 2954 2955 if (is_attribute_p ("eightbit_data", attr) 2956 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))) 2957 { 2958 if (DECL_INITIAL (decl) == NULL_TREE) 2959 { 2960 warning ("Only initialized variables can be placed into the 8-bit area."); 2961 return 0; 2962 } 2963 DECL_SECTION_NAME (decl) = build_string (7, ".eight"); 2964 return 1; 2965 } 2966 2967 if (is_attribute_p ("tiny_data", attr) 2968 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))) 2969 { 2970 if (DECL_INITIAL (decl) == NULL_TREE) 2971 { 2972 warning ("Only initialized variables can be placed into the 8-bit area."); 2973 return 0; 2974 } 2975 DECL_SECTION_NAME (decl) = build_string (6, ".tiny"); 2976 return 1; 2977 } 2978 2979 return 0; 2980} 2981 2982extern struct obstack *saveable_obstack; 2983 2984h8300_encode_label (decl) 2985 tree decl; 2986{ 2987 char *str = XSTR (XEXP (DECL_RTL (decl), 0), 0); 2988 int len = strlen (str); 2989 char *newstr; 2990 2991 newstr = obstack_alloc (saveable_obstack, len + 2); 2992 2993 strcpy (newstr + 1, str); 2994 *newstr = '&'; 2995 XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr; 2996} 2997 2998char * 2999output_simode_bld (bild, log2, operands) 3000 int bild; 3001 int log2; 3002 rtx operands[]; 3003{ 3004 /* Clear the destination register. */ 3005 if (TARGET_H8300H || TARGET_H8300S) 3006 output_asm_insn ("sub.l\t%S0,%S0", operands); 3007 else 3008 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands); 3009 3010 /* Get the bit number we want to load. */ 3011 if (log2) 3012 operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2]))); 3013 3014 /* Now output the bit load or bit inverse load, and store it in 3015 the destination. */ 3016 if (bild) 3017 output_asm_insn ("bild\t%Z2,%Y1\n\tbst\t#0,%w0", operands); 3018 else 3019 output_asm_insn ("bld\t%Z2,%Y1\n\tbst\t#0,%w0", operands); 3020 3021 /* All done. */ 3022 return ""; 3023} 3024 3025/* Given INSN and its current length LENGTH, return the adjustment 3026 (in bytes) to correctly compute INSN's length. 3027 3028 We use this to get the lengths of various memory references correct. */ 3029 3030h8300_adjust_insn_length (insn, length) 3031 rtx insn; 3032 int length; 3033{ 3034 rtx pat; 3035 3036 /* We must filter these ou before calling get_attr_adjust_length. */ 3037 if (GET_CODE (PATTERN (insn)) == USE 3038 || GET_CODE (PATTERN (insn)) == CLOBBER 3039 || GET_CODE (PATTERN (insn)) == SEQUENCE 3040 || GET_CODE (PATTERN (insn)) == ADDR_VEC 3041 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC) 3042 return 0; 3043 3044 if (get_attr_adjust_length (insn) == ADJUST_LENGTH_NO) 3045 return 0; 3046 3047 pat = PATTERN (insn); 3048 3049 /* Adjust length for reg->mem and mem->reg copies. */ 3050 if (GET_CODE (pat) == SET 3051 && (GET_CODE (SET_SRC (pat)) == MEM 3052 || GET_CODE (SET_DEST (pat)) == MEM)) 3053 { 3054 /* This insn might need a length adjustment. */ 3055 rtx addr; 3056 3057 if (GET_CODE (SET_SRC (pat)) == MEM) 3058 addr = XEXP (SET_SRC (pat), 0); 3059 else 3060 addr = XEXP (SET_DEST (pat), 0); 3061 3062 /* On the H8/300, only one adjustment is necessary; if the 3063 address mode is register indirect, then this insn is two 3064 bytes shorter than indicated in the machine description. */ 3065 if (TARGET_H8300 && GET_CODE (addr) == REG) 3066 return -2; 3067 3068 /* On the H8/300H and H8/S, register indirect is 6 bytes shorter than 3069 indicated in the machine description. */ 3070 if ((TARGET_H8300H || TARGET_H8300S) 3071 && GET_CODE (addr) == REG) 3072 return -6; 3073 3074 /* On the H8/300H and H8/300S, reg + d, for small displacements is 4 3075 bytes shorter than indicated in the machine description. */ 3076 if ((TARGET_H8300H || TARGET_H8300S) 3077 && GET_CODE (addr) == PLUS 3078 && GET_CODE (XEXP (addr, 0)) == REG 3079 && GET_CODE (XEXP (addr, 1)) == CONST_INT 3080 && INTVAL (XEXP (addr, 1)) > -32768 3081 && INTVAL (XEXP (addr, 1)) < 32767) 3082 return -4; 3083 3084 /* On the H8/300H and H8/300S, abs:16 is two bytes shorter than the 3085 more general abs:24. */ 3086 if ((TARGET_H8300H || TARGET_H8300S) 3087 && GET_CODE (addr) == SYMBOL_REF 3088 && TINY_DATA_NAME_P (XSTR (addr, 0))) 3089 return -2; 3090 } 3091 3092 /* Loading some constants needs adjustment. */ 3093 if (GET_CODE (pat) == SET 3094 && GET_CODE (SET_SRC (pat)) == CONST_INT 3095 && GET_MODE (SET_DEST (pat)) == SImode 3096 && INTVAL (SET_SRC (pat)) != 0) 3097 { 3098 if (TARGET_H8300 3099 && ((INTVAL (SET_SRC (pat)) & 0xffff) == 0 3100 || ((INTVAL (SET_SRC (pat)) >> 16) & 0xffff) == 0)) 3101 return -2; 3102 3103 if (TARGET_H8300H || TARGET_H8300S) 3104 { 3105 int val = INTVAL (SET_SRC (pat)); 3106 3107 if (val == (val & 0xff) 3108 || val == (val & 0xff00)) 3109 return -6; 3110 3111 if (val == -4 || val == -2 || val == -1) 3112 return -6; 3113 } 3114 } 3115 3116 /* Shifts need various adjustments. */ 3117 if (GET_CODE (pat) == PARALLEL 3118 && GET_CODE (XVECEXP (pat, 0, 0)) == SET 3119 && (GET_CODE (SET_SRC (XVECEXP (pat, 0, 0))) == ASHIFTRT 3120 || GET_CODE (SET_SRC (XVECEXP (pat, 0, 0))) == LSHIFTRT 3121 || GET_CODE (SET_SRC (XVECEXP (pat, 0, 0))) == ASHIFT)) 3122 { 3123 rtx src = SET_SRC (XVECEXP (pat, 0, 0)); 3124 enum machine_mode mode = GET_MODE (src); 3125 int shift; 3126 3127 if (GET_CODE (XEXP (src, 1)) != CONST_INT) 3128 return 0; 3129 3130 shift = INTVAL (XEXP (src, 1)); 3131 /* According to ANSI, negative shift is undefined. It is 3132 considered to be zero in this case (see function 3133 emit_a_shift above). */ 3134 if (shift < 0) 3135 shift = 0; 3136 3137 /* QImode shifts by small constants take one insn 3138 per shift. So the adjustment is 20 (md length) - 3139 # shifts * 2. */ 3140 if (mode == QImode && shift <= 4) 3141 return -(20 - shift * 2); 3142 3143 /* Similarly for HImode and SImode shifts by 3144 small constants on the H8/300H and H8/300S. */ 3145 if ((TARGET_H8300H || TARGET_H8300S) 3146 && (mode == HImode || mode == SImode) && shift <= 4) 3147 return -(20 - shift * 2); 3148 3149 /* HImode shifts by small constants for the H8/300. */ 3150 if (mode == HImode && shift <= 4) 3151 return -(20 - (shift * (GET_CODE (src) == ASHIFT ? 2 : 4))); 3152 3153 /* SImode shifts by small constants for the H8/300. */ 3154 if (mode == SImode && shift <= 2) 3155 return -(20 - (shift * (GET_CODE (src) == ASHIFT ? 6 : 8))); 3156 3157 /* XXX ??? Could check for more shift/rotate cases here. */ 3158 } 3159 3160 return 0; 3161} 3162