1/* Optimize by combining instructions for GNU compiler. 2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 3 1999, 2000 Free Software Foundation, Inc. 4 5This file is part of GNU CC. 6 7GNU CC is free software; you can redistribute it and/or modify 8it under the terms of the GNU General Public License as published by 9the Free Software Foundation; either version 2, or (at your option) 10any later version. 11 12GNU CC is distributed in the hope that it will be useful, 13but WITHOUT ANY WARRANTY; without even the implied warranty of 14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15GNU General Public License for more details. 16 17You should have received a copy of the GNU General Public License 18along with GNU CC; see the file COPYING. If not, write to 19the Free Software Foundation, 59 Temple Place - Suite 330, 20Boston, MA 02111-1307, USA. */ 21 22 23/* This module is essentially the "combiner" phase of the U. of Arizona 24 Portable Optimizer, but redone to work on our list-structured 25 representation for RTL instead of their string representation. 26 27 The LOG_LINKS of each insn identify the most recent assignment 28 to each REG used in the insn. It is a list of previous insns, 29 each of which contains a SET for a REG that is used in this insn 30 and not used or set in between. LOG_LINKs never cross basic blocks. 31 They were set up by the preceding pass (lifetime analysis). 32 33 We try to combine each pair of insns joined by a logical link. 34 We also try to combine triples of insns A, B and C when 35 C has a link back to B and B has a link back to A. 36 37 LOG_LINKS does not have links for use of the CC0. They don't 38 need to, because the insn that sets the CC0 is always immediately 39 before the insn that tests it. So we always regard a branch 40 insn as having a logical link to the preceding insn. The same is true 41 for an insn explicitly using CC0. 42 43 We check (with use_crosses_set_p) to avoid combining in such a way 44 as to move a computation to a place where its value would be different. 45 46 Combination is done by mathematically substituting the previous 47 insn(s) values for the regs they set into the expressions in 48 the later insns that refer to these regs. If the result is a valid insn 49 for our target machine, according to the machine description, 50 we install it, delete the earlier insns, and update the data flow 51 information (LOG_LINKS and REG_NOTES) for what we did. 52 53 There are a few exceptions where the dataflow information created by 54 flow.c aren't completely updated: 55 56 - reg_live_length is not updated 57 - reg_n_refs is not adjusted in the rare case when a register is 58 no longer required in a computation 59 - there are extremely rare cases (see distribute_regnotes) when a 60 REG_DEAD note is lost 61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be 62 removed because there is no way to know which register it was 63 linking 64 65 To simplify substitution, we combine only when the earlier insn(s) 66 consist of only a single assignment. To simplify updating afterward, 67 we never combine when a subroutine call appears in the middle. 68 69 Since we do not represent assignments to CC0 explicitly except when that 70 is all an insn does, there is no LOG_LINKS entry in an insn that uses 71 the condition code for the insn that set the condition code. 72 Fortunately, these two insns must be consecutive. 73 Therefore, every JUMP_INSN is taken to have an implicit logical link 74 to the preceding insn. This is not quite right, since non-jumps can 75 also use the condition code; but in practice such insns would not 76 combine anyway. */ 77 78#include "config.h" 79#include "system.h" 80#include "rtl.h" /* stdio.h must precede rtl.h for FFS. */ 81#include "flags.h" 82#include "regs.h" 83#include "hard-reg-set.h" 84#include "basic-block.h" 85#include "insn-config.h" 86/* Include expr.h after insn-config.h so we get HAVE_conditional_move. */ 87#include "expr.h" 88#include "insn-flags.h" 89#include "insn-codes.h" 90#include "insn-attr.h" 91#include "recog.h" 92#include "real.h" 93#include "toplev.h" 94 95/* It is not safe to use ordinary gen_lowpart in combine. 96 Use gen_lowpart_for_combine instead. See comments there. */ 97#define gen_lowpart dont_use_gen_lowpart_you_dummy 98 99/* Number of attempts to combine instructions in this function. */ 100 101static int combine_attempts; 102 103/* Number of attempts that got as far as substitution in this function. */ 104 105static int combine_merges; 106 107/* Number of instructions combined with added SETs in this function. */ 108 109static int combine_extras; 110 111/* Number of instructions combined in this function. */ 112 113static int combine_successes; 114 115/* Totals over entire compilation. */ 116 117static int total_attempts, total_merges, total_extras, total_successes; 118 119/* Define a default value for REVERSIBLE_CC_MODE. 120 We can never assume that a condition code mode is safe to reverse unless 121 the md tells us so. */ 122#ifndef REVERSIBLE_CC_MODE 123#define REVERSIBLE_CC_MODE(MODE) 0 124#endif 125 126/* Vector mapping INSN_UIDs to cuids. 127 The cuids are like uids but increase monotonically always. 128 Combine always uses cuids so that it can compare them. 129 But actually renumbering the uids, which we used to do, 130 proves to be a bad idea because it makes it hard to compare 131 the dumps produced by earlier passes with those from later passes. */ 132 133static int *uid_cuid; 134static int max_uid_cuid; 135 136/* Get the cuid of an insn. */ 137 138#define INSN_CUID(INSN) \ 139(INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)]) 140 141/* Maximum register number, which is the size of the tables below. */ 142 143static int combine_max_regno; 144 145/* Record last point of death of (hard or pseudo) register n. */ 146 147static rtx *reg_last_death; 148 149/* Record last point of modification of (hard or pseudo) register n. */ 150 151static rtx *reg_last_set; 152 153/* Record the cuid of the last insn that invalidated memory 154 (anything that writes memory, and subroutine calls, but not pushes). */ 155 156static int mem_last_set; 157 158/* Record the cuid of the last CALL_INSN 159 so we can tell whether a potential combination crosses any calls. */ 160 161static int last_call_cuid; 162 163/* When `subst' is called, this is the insn that is being modified 164 (by combining in a previous insn). The PATTERN of this insn 165 is still the old pattern partially modified and it should not be 166 looked at, but this may be used to examine the successors of the insn 167 to judge whether a simplification is valid. */ 168 169static rtx subst_insn; 170 171/* This is an insn that belongs before subst_insn, but is not currently 172 on the insn chain. */ 173 174static rtx subst_prev_insn; 175 176/* This is the lowest CUID that `subst' is currently dealing with. 177 get_last_value will not return a value if the register was set at or 178 after this CUID. If not for this mechanism, we could get confused if 179 I2 or I1 in try_combine were an insn that used the old value of a register 180 to obtain a new value. In that case, we might erroneously get the 181 new value of the register when we wanted the old one. */ 182 183static int subst_low_cuid; 184 185/* This contains any hard registers that are used in newpat; reg_dead_at_p 186 must consider all these registers to be always live. */ 187 188static HARD_REG_SET newpat_used_regs; 189 190/* This is an insn to which a LOG_LINKS entry has been added. If this 191 insn is the earlier than I2 or I3, combine should rescan starting at 192 that location. */ 193 194static rtx added_links_insn; 195 196/* Basic block number of the block in which we are performing combines. */ 197static int this_basic_block; 198 199/* The next group of arrays allows the recording of the last value assigned 200 to (hard or pseudo) register n. We use this information to see if a 201 operation being processed is redundant given a prior operation performed 202 on the register. For example, an `and' with a constant is redundant if 203 all the zero bits are already known to be turned off. 204 205 We use an approach similar to that used by cse, but change it in the 206 following ways: 207 208 (1) We do not want to reinitialize at each label. 209 (2) It is useful, but not critical, to know the actual value assigned 210 to a register. Often just its form is helpful. 211 212 Therefore, we maintain the following arrays: 213 214 reg_last_set_value the last value assigned 215 reg_last_set_label records the value of label_tick when the 216 register was assigned 217 reg_last_set_table_tick records the value of label_tick when a 218 value using the register is assigned 219 reg_last_set_invalid set to non-zero when it is not valid 220 to use the value of this register in some 221 register's value 222 223 To understand the usage of these tables, it is important to understand 224 the distinction between the value in reg_last_set_value being valid 225 and the register being validly contained in some other expression in the 226 table. 227 228 Entry I in reg_last_set_value is valid if it is non-zero, and either 229 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick. 230 231 Register I may validly appear in any expression returned for the value 232 of another register if reg_n_sets[i] is 1. It may also appear in the 233 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or 234 reg_last_set_invalid[j] is zero. 235 236 If an expression is found in the table containing a register which may 237 not validly appear in an expression, the register is replaced by 238 something that won't match, (clobber (const_int 0)). 239 240 reg_last_set_invalid[i] is set non-zero when register I is being assigned 241 to and reg_last_set_table_tick[i] == label_tick. */ 242 243/* Record last value assigned to (hard or pseudo) register n. */ 244 245static rtx *reg_last_set_value; 246 247/* Record the value of label_tick when the value for register n is placed in 248 reg_last_set_value[n]. */ 249 250static int *reg_last_set_label; 251 252/* Record the value of label_tick when an expression involving register n 253 is placed in reg_last_set_value. */ 254 255static int *reg_last_set_table_tick; 256 257/* Set non-zero if references to register n in expressions should not be 258 used. */ 259 260static char *reg_last_set_invalid; 261 262/* Incremented for each label. */ 263 264static int label_tick; 265 266/* Some registers that are set more than once and used in more than one 267 basic block are nevertheless always set in similar ways. For example, 268 a QImode register may be loaded from memory in two places on a machine 269 where byte loads zero extend. 270 271 We record in the following array what we know about the nonzero 272 bits of a register, specifically which bits are known to be zero. 273 274 If an entry is zero, it means that we don't know anything special. */ 275 276static unsigned HOST_WIDE_INT *reg_nonzero_bits; 277 278/* Mode used to compute significance in reg_nonzero_bits. It is the largest 279 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */ 280 281static enum machine_mode nonzero_bits_mode; 282 283/* Nonzero if we know that a register has some leading bits that are always 284 equal to the sign bit. */ 285 286static char *reg_sign_bit_copies; 287 288/* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used. 289 It is zero while computing them and after combine has completed. This 290 former test prevents propagating values based on previously set values, 291 which can be incorrect if a variable is modified in a loop. */ 292 293static int nonzero_sign_valid; 294 295/* These arrays are maintained in parallel with reg_last_set_value 296 and are used to store the mode in which the register was last set, 297 the bits that were known to be zero when it was last set, and the 298 number of sign bits copies it was known to have when it was last set. */ 299 300static enum machine_mode *reg_last_set_mode; 301static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits; 302static char *reg_last_set_sign_bit_copies; 303 304/* Record one modification to rtl structure 305 to be undone by storing old_contents into *where. 306 is_int is 1 if the contents are an int. */ 307 308struct undo 309{ 310 struct undo *next; 311 int is_int; 312 union {rtx r; int i;} old_contents; 313 union {rtx *r; int *i;} where; 314}; 315 316/* Record a bunch of changes to be undone, up to MAX_UNDO of them. 317 num_undo says how many are currently recorded. 318 319 storage is nonzero if we must undo the allocation of new storage. 320 The value of storage is what to pass to obfree. 321 322 other_insn is nonzero if we have modified some other insn in the process 323 of working on subst_insn. It must be verified too. 324 325 previous_undos is the value of undobuf.undos when we started processing 326 this substitution. This will prevent gen_rtx_combine from re-used a piece 327 from the previous expression. Doing so can produce circular rtl 328 structures. */ 329 330struct undobuf 331{ 332 char *storage; 333 struct undo *undos; 334 struct undo *frees; 335 struct undo *previous_undos; 336 rtx other_insn; 337}; 338 339static struct undobuf undobuf; 340 341/* Substitute NEWVAL, an rtx expression, into INTO, a place in some 342 insn. The substitution can be undone by undo_all. If INTO is already 343 set to NEWVAL, do not record this change. Because computing NEWVAL might 344 also call SUBST, we have to compute it before we put anything into 345 the undo table. */ 346 347#define SUBST(INTO, NEWVAL) \ 348 do { rtx _new = (NEWVAL); \ 349 struct undo *_buf; \ 350 \ 351 if (undobuf.frees) \ 352 _buf = undobuf.frees, undobuf.frees = _buf->next; \ 353 else \ 354 _buf = (struct undo *) xmalloc (sizeof (struct undo)); \ 355 \ 356 _buf->is_int = 0; \ 357 _buf->where.r = &INTO; \ 358 _buf->old_contents.r = INTO; \ 359 INTO = _new; \ 360 if (_buf->old_contents.r == INTO) \ 361 _buf->next = undobuf.frees, undobuf.frees = _buf; \ 362 else \ 363 _buf->next = undobuf.undos, undobuf.undos = _buf; \ 364 } while (0) 365 366/* Similar to SUBST, but NEWVAL is an int expression. Note that substitution 367 for the value of a HOST_WIDE_INT value (including CONST_INT) is 368 not safe. */ 369 370#define SUBST_INT(INTO, NEWVAL) \ 371 do { struct undo *_buf; \ 372 \ 373 if (undobuf.frees) \ 374 _buf = undobuf.frees, undobuf.frees = _buf->next; \ 375 else \ 376 _buf = (struct undo *) xmalloc (sizeof (struct undo)); \ 377 \ 378 _buf->is_int = 1; \ 379 _buf->where.i = (int *) &INTO; \ 380 _buf->old_contents.i = INTO; \ 381 INTO = NEWVAL; \ 382 if (_buf->old_contents.i == INTO) \ 383 _buf->next = undobuf.frees, undobuf.frees = _buf; \ 384 else \ 385 _buf->next = undobuf.undos, undobuf.undos = _buf; \ 386 } while (0) 387 388/* Number of times the pseudo being substituted for 389 was found and replaced. */ 390 391static int n_occurrences; 392 393static void init_reg_last_arrays PROTO((void)); 394static void setup_incoming_promotions PROTO((void)); 395static void set_nonzero_bits_and_sign_copies PROTO((rtx, rtx)); 396static int cant_combine_insn_p PROTO((rtx)); 397static int can_combine_p PROTO((rtx, rtx, rtx, rtx, rtx *, rtx *)); 398static int sets_function_arg_p PROTO((rtx)); 399static int combinable_i3pat PROTO((rtx, rtx *, rtx, rtx, int, rtx *)); 400static rtx try_combine PROTO((rtx, rtx, rtx)); 401static void undo_all PROTO((void)); 402static rtx *find_split_point PROTO((rtx *, rtx)); 403static rtx subst PROTO((rtx, rtx, rtx, int, int)); 404static rtx simplify_rtx PROTO((rtx, enum machine_mode, int, int)); 405static rtx simplify_if_then_else PROTO((rtx)); 406static rtx simplify_set PROTO((rtx)); 407static rtx simplify_logical PROTO((rtx, int)); 408static rtx expand_compound_operation PROTO((rtx)); 409static rtx expand_field_assignment PROTO((rtx)); 410static rtx make_extraction PROTO((enum machine_mode, rtx, int, rtx, int, 411 int, int, int)); 412static rtx extract_left_shift PROTO((rtx, int)); 413static rtx make_compound_operation PROTO((rtx, enum rtx_code)); 414static int get_pos_from_mask PROTO((unsigned HOST_WIDE_INT, int *)); 415static rtx force_to_mode PROTO((rtx, enum machine_mode, 416 unsigned HOST_WIDE_INT, rtx, int)); 417static rtx if_then_else_cond PROTO((rtx, rtx *, rtx *)); 418static rtx known_cond PROTO((rtx, enum rtx_code, rtx, rtx)); 419static int rtx_equal_for_field_assignment_p PROTO((rtx, rtx)); 420static rtx make_field_assignment PROTO((rtx)); 421static rtx apply_distributive_law PROTO((rtx)); 422static rtx simplify_and_const_int PROTO((rtx, enum machine_mode, rtx, 423 unsigned HOST_WIDE_INT)); 424static unsigned HOST_WIDE_INT nonzero_bits PROTO((rtx, enum machine_mode)); 425static int num_sign_bit_copies PROTO((rtx, enum machine_mode)); 426static int merge_outer_ops PROTO((enum rtx_code *, HOST_WIDE_INT *, 427 enum rtx_code, HOST_WIDE_INT, 428 enum machine_mode, int *)); 429static rtx simplify_shift_const PROTO((rtx, enum rtx_code, enum machine_mode, 430 rtx, int)); 431static int recog_for_combine PROTO((rtx *, rtx, rtx *)); 432static rtx gen_lowpart_for_combine PROTO((enum machine_mode, rtx)); 433static rtx gen_rtx_combine PVPROTO((enum rtx_code code, enum machine_mode mode, 434 ...)); 435static rtx gen_binary PROTO((enum rtx_code, enum machine_mode, 436 rtx, rtx)); 437static rtx gen_unary PROTO((enum rtx_code, enum machine_mode, 438 enum machine_mode, rtx)); 439static enum rtx_code simplify_comparison PROTO((enum rtx_code, rtx *, rtx *)); 440static int reversible_comparison_p PROTO((rtx)); 441static void update_table_tick PROTO((rtx)); 442static void record_value_for_reg PROTO((rtx, rtx, rtx)); 443static void record_dead_and_set_regs_1 PROTO((rtx, rtx)); 444static void record_dead_and_set_regs PROTO((rtx)); 445static int get_last_value_validate PROTO((rtx *, rtx, int, int)); 446static rtx get_last_value PROTO((rtx)); 447static int use_crosses_set_p PROTO((rtx, int)); 448static void reg_dead_at_p_1 PROTO((rtx, rtx)); 449static int reg_dead_at_p PROTO((rtx, rtx)); 450static void move_deaths PROTO((rtx, rtx, int, rtx, rtx *)); 451static int reg_bitfield_target_p PROTO((rtx, rtx)); 452static void distribute_notes PROTO((rtx, rtx, rtx, rtx, rtx, rtx)); 453static void distribute_links PROTO((rtx)); 454static void mark_used_regs_combine PROTO((rtx)); 455static int insn_cuid PROTO((rtx)); 456 457/* Main entry point for combiner. F is the first insn of the function. 458 NREGS is the first unused pseudo-reg number. */ 459 460void 461combine_instructions (f, nregs) 462 rtx f; 463 int nregs; 464{ 465 register rtx insn, next; 466#ifdef HAVE_cc0 467 register rtx prev; 468#endif 469 register int i; 470 register rtx links, nextlinks; 471 472 combine_attempts = 0; 473 combine_merges = 0; 474 combine_extras = 0; 475 combine_successes = 0; 476 undobuf.undos = undobuf.previous_undos = 0; 477 478 combine_max_regno = nregs; 479 480 reg_nonzero_bits 481 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT)); 482 reg_sign_bit_copies = (char *) alloca (nregs * sizeof (char)); 483 484 bzero ((char *) reg_nonzero_bits, nregs * sizeof (HOST_WIDE_INT)); 485 bzero (reg_sign_bit_copies, nregs * sizeof (char)); 486 487 reg_last_death = (rtx *) alloca (nregs * sizeof (rtx)); 488 reg_last_set = (rtx *) alloca (nregs * sizeof (rtx)); 489 reg_last_set_value = (rtx *) alloca (nregs * sizeof (rtx)); 490 reg_last_set_table_tick = (int *) alloca (nregs * sizeof (int)); 491 reg_last_set_label = (int *) alloca (nregs * sizeof (int)); 492 reg_last_set_invalid = (char *) alloca (nregs * sizeof (char)); 493 reg_last_set_mode 494 = (enum machine_mode *) alloca (nregs * sizeof (enum machine_mode)); 495 reg_last_set_nonzero_bits 496 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT)); 497 reg_last_set_sign_bit_copies 498 = (char *) alloca (nregs * sizeof (char)); 499 500 init_reg_last_arrays (); 501 502 init_recog_no_volatile (); 503 504 /* Compute maximum uid value so uid_cuid can be allocated. */ 505 506 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn)) 507 if (INSN_UID (insn) > i) 508 i = INSN_UID (insn); 509 510 uid_cuid = (int *) alloca ((i + 1) * sizeof (int)); 511 max_uid_cuid = i; 512 513 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0); 514 515 /* Don't use reg_nonzero_bits when computing it. This can cause problems 516 when, for example, we have j <<= 1 in a loop. */ 517 518 nonzero_sign_valid = 0; 519 520 /* Compute the mapping from uids to cuids. 521 Cuids are numbers assigned to insns, like uids, 522 except that cuids increase monotonically through the code. 523 524 Scan all SETs and see if we can deduce anything about what 525 bits are known to be zero for some registers and how many copies 526 of the sign bit are known to exist for those registers. 527 528 Also set any known values so that we can use it while searching 529 for what bits are known to be set. */ 530 531 label_tick = 1; 532 533 /* We need to initialize it here, because record_dead_and_set_regs may call 534 get_last_value. */ 535 subst_prev_insn = NULL_RTX; 536 537 setup_incoming_promotions (); 538 539 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn)) 540 { 541 uid_cuid[INSN_UID (insn)] = ++i; 542 subst_low_cuid = i; 543 subst_insn = insn; 544 545 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') 546 { 547 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies); 548 record_dead_and_set_regs (insn); 549 550#ifdef AUTO_INC_DEC 551 for (links = REG_NOTES (insn); links; links = XEXP (links, 1)) 552 if (REG_NOTE_KIND (links) == REG_INC) 553 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX); 554#endif 555 } 556 557 if (GET_CODE (insn) == CODE_LABEL) 558 label_tick++; 559 } 560 561 nonzero_sign_valid = 1; 562 563 /* Now scan all the insns in forward order. */ 564 565 this_basic_block = -1; 566 label_tick = 1; 567 last_call_cuid = 0; 568 mem_last_set = 0; 569 init_reg_last_arrays (); 570 setup_incoming_promotions (); 571 572 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn)) 573 { 574 next = 0; 575 576 /* If INSN starts a new basic block, update our basic block number. */ 577 if (this_basic_block + 1 < n_basic_blocks 578 && BLOCK_HEAD (this_basic_block + 1) == insn) 579 this_basic_block++; 580 581 if (GET_CODE (insn) == CODE_LABEL) 582 label_tick++; 583 584 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') 585 { 586 /* Try this insn with each insn it links back to. */ 587 588 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) 589 if ((next = try_combine (insn, XEXP (links, 0), NULL_RTX)) != 0) 590 goto retry; 591 592 /* Try each sequence of three linked insns ending with this one. */ 593 594 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) 595 for (nextlinks = LOG_LINKS (XEXP (links, 0)); nextlinks; 596 nextlinks = XEXP (nextlinks, 1)) 597 if ((next = try_combine (insn, XEXP (links, 0), 598 XEXP (nextlinks, 0))) != 0) 599 goto retry; 600 601#ifdef HAVE_cc0 602 /* Try to combine a jump insn that uses CC0 603 with a preceding insn that sets CC0, and maybe with its 604 logical predecessor as well. 605 This is how we make decrement-and-branch insns. 606 We need this special code because data flow connections 607 via CC0 do not get entered in LOG_LINKS. */ 608 609 if (GET_CODE (insn) == JUMP_INSN 610 && (prev = prev_nonnote_insn (insn)) != 0 611 && GET_CODE (prev) == INSN 612 && sets_cc0_p (PATTERN (prev))) 613 { 614 if ((next = try_combine (insn, prev, NULL_RTX)) != 0) 615 goto retry; 616 617 for (nextlinks = LOG_LINKS (prev); nextlinks; 618 nextlinks = XEXP (nextlinks, 1)) 619 if ((next = try_combine (insn, prev, 620 XEXP (nextlinks, 0))) != 0) 621 goto retry; 622 } 623 624 /* Do the same for an insn that explicitly references CC0. */ 625 if (GET_CODE (insn) == INSN 626 && (prev = prev_nonnote_insn (insn)) != 0 627 && GET_CODE (prev) == INSN 628 && sets_cc0_p (PATTERN (prev)) 629 && GET_CODE (PATTERN (insn)) == SET 630 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn)))) 631 { 632 if ((next = try_combine (insn, prev, NULL_RTX)) != 0) 633 goto retry; 634 635 for (nextlinks = LOG_LINKS (prev); nextlinks; 636 nextlinks = XEXP (nextlinks, 1)) 637 if ((next = try_combine (insn, prev, 638 XEXP (nextlinks, 0))) != 0) 639 goto retry; 640 } 641 642 /* Finally, see if any of the insns that this insn links to 643 explicitly references CC0. If so, try this insn, that insn, 644 and its predecessor if it sets CC0. */ 645 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) 646 if (GET_CODE (XEXP (links, 0)) == INSN 647 && GET_CODE (PATTERN (XEXP (links, 0))) == SET 648 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0)))) 649 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0 650 && GET_CODE (prev) == INSN 651 && sets_cc0_p (PATTERN (prev)) 652 && (next = try_combine (insn, XEXP (links, 0), prev)) != 0) 653 goto retry; 654#endif 655 656 /* Try combining an insn with two different insns whose results it 657 uses. */ 658 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) 659 for (nextlinks = XEXP (links, 1); nextlinks; 660 nextlinks = XEXP (nextlinks, 1)) 661 if ((next = try_combine (insn, XEXP (links, 0), 662 XEXP (nextlinks, 0))) != 0) 663 goto retry; 664 665 if (GET_CODE (insn) != NOTE) 666 record_dead_and_set_regs (insn); 667 668 retry: 669 ; 670 } 671 } 672 673 total_attempts += combine_attempts; 674 total_merges += combine_merges; 675 total_extras += combine_extras; 676 total_successes += combine_successes; 677 678 nonzero_sign_valid = 0; 679 680 /* Make recognizer allow volatile MEMs again. */ 681 init_recog (); 682} 683 684/* Wipe the reg_last_xxx arrays in preparation for another pass. */ 685 686static void 687init_reg_last_arrays () 688{ 689 int nregs = combine_max_regno; 690 691 bzero ((char *) reg_last_death, nregs * sizeof (rtx)); 692 bzero ((char *) reg_last_set, nregs * sizeof (rtx)); 693 bzero ((char *) reg_last_set_value, nregs * sizeof (rtx)); 694 bzero ((char *) reg_last_set_table_tick, nregs * sizeof (int)); 695 bzero ((char *) reg_last_set_label, nregs * sizeof (int)); 696 bzero (reg_last_set_invalid, nregs * sizeof (char)); 697 bzero ((char *) reg_last_set_mode, nregs * sizeof (enum machine_mode)); 698 bzero ((char *) reg_last_set_nonzero_bits, nregs * sizeof (HOST_WIDE_INT)); 699 bzero (reg_last_set_sign_bit_copies, nregs * sizeof (char)); 700} 701 702/* Set up any promoted values for incoming argument registers. */ 703 704static void 705setup_incoming_promotions () 706{ 707#ifdef PROMOTE_FUNCTION_ARGS 708 int regno; 709 rtx reg; 710 enum machine_mode mode; 711 int unsignedp; 712 rtx first = get_insns (); 713 714 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) 715 if (FUNCTION_ARG_REGNO_P (regno) 716 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0) 717 { 718 record_value_for_reg 719 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND 720 : SIGN_EXTEND), 721 GET_MODE (reg), 722 gen_rtx_CLOBBER (mode, const0_rtx))); 723 } 724#endif 725} 726 727/* Called via note_stores. If X is a pseudo that is narrower than 728 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero. 729 730 If we are setting only a portion of X and we can't figure out what 731 portion, assume all bits will be used since we don't know what will 732 be happening. 733 734 Similarly, set how many bits of X are known to be copies of the sign bit 735 at all locations in the function. This is the smallest number implied 736 by any set of X. */ 737 738static void 739set_nonzero_bits_and_sign_copies (x, set) 740 rtx x; 741 rtx set; 742{ 743 int num; 744 745 if (GET_CODE (x) == REG 746 && REGNO (x) >= FIRST_PSEUDO_REGISTER 747 /* If this register is undefined at the start of the file, we can't 748 say what its contents were. */ 749 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, REGNO (x)) 750 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT) 751 { 752 if (set == 0 || GET_CODE (set) == CLOBBER) 753 { 754 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x)); 755 reg_sign_bit_copies[REGNO (x)] = 1; 756 return; 757 } 758 759 /* If this is a complex assignment, see if we can convert it into a 760 simple assignment. */ 761 set = expand_field_assignment (set); 762 763 /* If this is a simple assignment, or we have a paradoxical SUBREG, 764 set what we know about X. */ 765 766 if (SET_DEST (set) == x 767 || (GET_CODE (SET_DEST (set)) == SUBREG 768 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set))) 769 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set))))) 770 && SUBREG_REG (SET_DEST (set)) == x)) 771 { 772 rtx src = SET_SRC (set); 773 774#ifdef SHORT_IMMEDIATES_SIGN_EXTEND 775 /* If X is narrower than a word and SRC is a non-negative 776 constant that would appear negative in the mode of X, 777 sign-extend it for use in reg_nonzero_bits because some 778 machines (maybe most) will actually do the sign-extension 779 and this is the conservative approach. 780 781 ??? For 2.5, try to tighten up the MD files in this regard 782 instead of this kludge. */ 783 784 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD 785 && GET_CODE (src) == CONST_INT 786 && INTVAL (src) > 0 787 && 0 != (INTVAL (src) 788 & ((HOST_WIDE_INT) 1 789 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1)))) 790 src = GEN_INT (INTVAL (src) 791 | ((HOST_WIDE_INT) (-1) 792 << GET_MODE_BITSIZE (GET_MODE (x)))); 793#endif 794 795 reg_nonzero_bits[REGNO (x)] 796 |= nonzero_bits (src, nonzero_bits_mode); 797 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x)); 798 if (reg_sign_bit_copies[REGNO (x)] == 0 799 || reg_sign_bit_copies[REGNO (x)] > num) 800 reg_sign_bit_copies[REGNO (x)] = num; 801 } 802 else 803 { 804 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x)); 805 reg_sign_bit_copies[REGNO (x)] = 1; 806 } 807 } 808} 809 810/* See if INSN can be combined into I3. PRED and SUCC are optionally 811 insns that were previously combined into I3 or that will be combined 812 into the merger of INSN and I3. 813 814 Return 0 if the combination is not allowed for any reason. 815 816 If the combination is allowed, *PDEST will be set to the single 817 destination of INSN and *PSRC to the single source, and this function 818 will return 1. */ 819 820static int 821can_combine_p (insn, i3, pred, succ, pdest, psrc) 822 rtx insn; 823 rtx i3; 824 rtx pred ATTRIBUTE_UNUSED; 825 rtx succ; 826 rtx *pdest, *psrc; 827{ 828 int i; 829 rtx set = 0, src, dest; 830 rtx p; 831#ifdef AUTO_INC_DEC 832 rtx link; 833#endif 834 int all_adjacent = (succ ? (next_active_insn (insn) == succ 835 && next_active_insn (succ) == i3) 836 : next_active_insn (insn) == i3); 837 838 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0. 839 or a PARALLEL consisting of such a SET and CLOBBERs. 840 841 If INSN has CLOBBER parallel parts, ignore them for our processing. 842 By definition, these happen during the execution of the insn. When it 843 is merged with another insn, all bets are off. If they are, in fact, 844 needed and aren't also supplied in I3, they may be added by 845 recog_for_combine. Otherwise, it won't match. 846 847 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED 848 note. 849 850 Get the source and destination of INSN. If more than one, can't 851 combine. */ 852 853 if (GET_CODE (PATTERN (insn)) == SET) 854 set = PATTERN (insn); 855 else if (GET_CODE (PATTERN (insn)) == PARALLEL 856 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET) 857 { 858 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) 859 { 860 rtx elt = XVECEXP (PATTERN (insn), 0, i); 861 862 switch (GET_CODE (elt)) 863 { 864 /* This is important to combine floating point insns 865 for the SH4 port. */ 866 case USE: 867 /* Combining an isolated USE doesn't make sense. 868 We depend here on combinable_i3_pat to reject them. */ 869 /* The code below this loop only verifies that the inputs of 870 the SET in INSN do not change. We call reg_set_between_p 871 to verify that the REG in the USE does not change betweeen 872 I3 and INSN. 873 If the USE in INSN was for a pseudo register, the matching 874 insn pattern will likely match any register; combining this 875 with any other USE would only be safe if we knew that the 876 used registers have identical values, or if there was 877 something to tell them apart, e.g. different modes. For 878 now, we forgo such compilcated tests and simply disallow 879 combining of USES of pseudo registers with any other USE. */ 880 if (GET_CODE (XEXP (elt, 0)) == REG 881 && GET_CODE (PATTERN (i3)) == PARALLEL) 882 { 883 rtx i3pat = PATTERN (i3); 884 int i = XVECLEN (i3pat, 0) - 1; 885 int regno = REGNO (XEXP (elt, 0)); 886 do 887 { 888 rtx i3elt = XVECEXP (i3pat, 0, i); 889 if (GET_CODE (i3elt) == USE 890 && GET_CODE (XEXP (i3elt, 0)) == REG 891 && (REGNO (XEXP (i3elt, 0)) == regno 892 ? reg_set_between_p (XEXP (elt, 0), 893 PREV_INSN (insn), i3) 894 : regno >= FIRST_PSEUDO_REGISTER)) 895 return 0; 896 } 897 while (--i >= 0); 898 } 899 break; 900 901 /* We can ignore CLOBBERs. */ 902 case CLOBBER: 903 break; 904 905 case SET: 906 /* Ignore SETs whose result isn't used but not those that 907 have side-effects. */ 908 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt)) 909 && ! side_effects_p (elt)) 910 break; 911 912 /* If we have already found a SET, this is a second one and 913 so we cannot combine with this insn. */ 914 if (set) 915 return 0; 916 917 set = elt; 918 break; 919 920 default: 921 /* Anything else means we can't combine. */ 922 return 0; 923 } 924 } 925 926 if (set == 0 927 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs, 928 so don't do anything with it. */ 929 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS) 930 return 0; 931 } 932 else 933 return 0; 934 935 if (set == 0) 936 return 0; 937 938 set = expand_field_assignment (set); 939 src = SET_SRC (set), dest = SET_DEST (set); 940 941 /* Don't eliminate a store in the stack pointer. */ 942 if (dest == stack_pointer_rtx 943 /* If we couldn't eliminate a field assignment, we can't combine. */ 944 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART 945 /* Don't combine with an insn that sets a register to itself if it has 946 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */ 947 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX)) 948 /* Can't merge a function call. */ 949 || GET_CODE (src) == CALL 950 /* Don't eliminate a function call argument. */ 951 || (GET_CODE (i3) == CALL_INSN 952 && (find_reg_fusage (i3, USE, dest) 953 || (GET_CODE (dest) == REG 954 && REGNO (dest) < FIRST_PSEUDO_REGISTER 955 && global_regs[REGNO (dest)]))) 956 /* Don't substitute into an incremented register. */ 957 || FIND_REG_INC_NOTE (i3, dest) 958 || (succ && FIND_REG_INC_NOTE (succ, dest)) 959#if 0 960 /* Don't combine the end of a libcall into anything. */ 961 /* ??? This gives worse code, and appears to be unnecessary, since no 962 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does 963 use REG_RETVAL notes for noconflict blocks, but other code here 964 makes sure that those insns don't disappear. */ 965 || find_reg_note (insn, REG_RETVAL, NULL_RTX) 966#endif 967 /* Make sure that DEST is not used after SUCC but before I3. */ 968 || (succ && ! all_adjacent 969 && reg_used_between_p (dest, succ, i3)) 970 /* Make sure that the value that is to be substituted for the register 971 does not use any registers whose values alter in between. However, 972 If the insns are adjacent, a use can't cross a set even though we 973 think it might (this can happen for a sequence of insns each setting 974 the same destination; reg_last_set of that register might point to 975 a NOTE). If INSN has a REG_EQUIV note, the register is always 976 equivalent to the memory so the substitution is valid even if there 977 are intervening stores. Also, don't move a volatile asm or 978 UNSPEC_VOLATILE across any other insns. */ 979 || (! all_adjacent 980 && (((GET_CODE (src) != MEM 981 || ! find_reg_note (insn, REG_EQUIV, src)) 982 && use_crosses_set_p (src, INSN_CUID (insn))) 983 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src)) 984 || GET_CODE (src) == UNSPEC_VOLATILE)) 985 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get 986 better register allocation by not doing the combine. */ 987 || find_reg_note (i3, REG_NO_CONFLICT, dest) 988 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest)) 989 /* Don't combine across a CALL_INSN, because that would possibly 990 change whether the life span of some REGs crosses calls or not, 991 and it is a pain to update that information. 992 Exception: if source is a constant, moving it later can't hurt. 993 Accept that special case, because it helps -fforce-addr a lot. */ 994 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src))) 995 return 0; 996 997 /* DEST must either be a REG or CC0. */ 998 if (GET_CODE (dest) == REG) 999 { 1000 /* If register alignment is being enforced for multi-word items in all 1001 cases except for parameters, it is possible to have a register copy 1002 insn referencing a hard register that is not allowed to contain the 1003 mode being copied and which would not be valid as an operand of most 1004 insns. Eliminate this problem by not combining with such an insn. 1005 1006 Also, on some machines we don't want to extend the life of a hard 1007 register. 1008 1009 This is the same test done in can_combine except that we don't test 1010 if SRC is a CALL operation to permit a hard register with 1011 SMALL_REGISTER_CLASSES, and that we have to take all_adjacent 1012 into account. */ 1013 1014 if (GET_CODE (src) == REG 1015 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER 1016 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest))) 1017 /* Don't extend the life of a hard register unless it is 1018 user variable (if we have few registers) or it can't 1019 fit into the desired register (meaning something special 1020 is going on). 1021 Also avoid substituting a return register into I3, because 1022 reload can't handle a conflict with constraints of other 1023 inputs. */ 1024 || (REGNO (src) < FIRST_PSEUDO_REGISTER 1025 && (! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)) 1026 || (SMALL_REGISTER_CLASSES 1027 && ((! all_adjacent && ! REG_USERVAR_P (src)) 1028 || (FUNCTION_VALUE_REGNO_P (REGNO (src)) 1029 && ! REG_USERVAR_P (src)))))))) 1030 return 0; 1031 } 1032 else if (GET_CODE (dest) != CC0) 1033 return 0; 1034 1035 /* Don't substitute for a register intended as a clobberable operand. 1036 Similarly, don't substitute an expression containing a register that 1037 will be clobbered in I3. */ 1038 if (GET_CODE (PATTERN (i3)) == PARALLEL) 1039 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--) 1040 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER 1041 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), 1042 src) 1043 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest))) 1044 return 0; 1045 1046 /* If INSN contains anything volatile, or is an `asm' (whether volatile 1047 or not), reject, unless nothing volatile comes between it and I3 */ 1048 1049 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src)) 1050 { 1051 /* Make sure succ doesn't contain a volatile reference. */ 1052 if (succ != 0 && volatile_refs_p (PATTERN (succ))) 1053 return 0; 1054 1055 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p)) 1056 if (GET_RTX_CLASS (GET_CODE (p)) == 'i' 1057 && p != succ && volatile_refs_p (PATTERN (p))) 1058 return 0; 1059 } 1060 1061 /* If INSN is an asm, and DEST is a hard register, reject, since it has 1062 to be an explicit register variable, and was chosen for a reason. */ 1063 1064 if (GET_CODE (src) == ASM_OPERANDS 1065 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER) 1066 return 0; 1067 1068 /* If there are any volatile insns between INSN and I3, reject, because 1069 they might affect machine state. */ 1070 1071 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p)) 1072 if (GET_RTX_CLASS (GET_CODE (p)) == 'i' 1073 && p != succ && volatile_insn_p (PATTERN (p))) 1074 return 0; 1075 1076 /* If INSN or I2 contains an autoincrement or autodecrement, 1077 make sure that register is not used between there and I3, 1078 and not already used in I3 either. 1079 Also insist that I3 not be a jump; if it were one 1080 and the incremented register were spilled, we would lose. */ 1081 1082#ifdef AUTO_INC_DEC 1083 for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) 1084 if (REG_NOTE_KIND (link) == REG_INC 1085 && (GET_CODE (i3) == JUMP_INSN 1086 || reg_used_between_p (XEXP (link, 0), insn, i3) 1087 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3)))) 1088 return 0; 1089#endif 1090 1091#ifdef HAVE_cc0 1092 /* Don't combine an insn that follows a CC0-setting insn. 1093 An insn that uses CC0 must not be separated from the one that sets it. 1094 We do, however, allow I2 to follow a CC0-setting insn if that insn 1095 is passed as I1; in that case it will be deleted also. 1096 We also allow combining in this case if all the insns are adjacent 1097 because that would leave the two CC0 insns adjacent as well. 1098 It would be more logical to test whether CC0 occurs inside I1 or I2, 1099 but that would be much slower, and this ought to be equivalent. */ 1100 1101 p = prev_nonnote_insn (insn); 1102 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p)) 1103 && ! all_adjacent) 1104 return 0; 1105#endif 1106 1107 /* If we get here, we have passed all the tests and the combination is 1108 to be allowed. */ 1109 1110 *pdest = dest; 1111 *psrc = src; 1112 1113 return 1; 1114} 1115 1116/* Check if PAT is an insn - or a part of it - used to set up an 1117 argument for a function in a hard register. */ 1118 1119static int 1120sets_function_arg_p (pat) 1121 rtx pat; 1122{ 1123 int i; 1124 rtx inner_dest; 1125 1126 switch (GET_CODE (pat)) 1127 { 1128 case INSN: 1129 return sets_function_arg_p (PATTERN (pat)); 1130 1131 case PARALLEL: 1132 for (i = XVECLEN (pat, 0); --i >= 0;) 1133 if (sets_function_arg_p (XVECEXP (pat, 0, i))) 1134 return 1; 1135 1136 break; 1137 1138 case SET: 1139 inner_dest = SET_DEST (pat); 1140 while (GET_CODE (inner_dest) == STRICT_LOW_PART 1141 || GET_CODE (inner_dest) == SUBREG 1142 || GET_CODE (inner_dest) == ZERO_EXTRACT) 1143 inner_dest = XEXP (inner_dest, 0); 1144 1145 return (GET_CODE (inner_dest) == REG 1146 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER 1147 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest))); 1148 1149 default: 1150 break; 1151 } 1152 1153 return 0; 1154} 1155 1156/* LOC is the location within I3 that contains its pattern or the component 1157 of a PARALLEL of the pattern. We validate that it is valid for combining. 1158 1159 One problem is if I3 modifies its output, as opposed to replacing it 1160 entirely, we can't allow the output to contain I2DEST or I1DEST as doing 1161 so would produce an insn that is not equivalent to the original insns. 1162 1163 Consider: 1164 1165 (set (reg:DI 101) (reg:DI 100)) 1166 (set (subreg:SI (reg:DI 101) 0) <foo>) 1167 1168 This is NOT equivalent to: 1169 1170 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>) 1171 (set (reg:DI 101) (reg:DI 100))]) 1172 1173 Not only does this modify 100 (in which case it might still be valid 1174 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100. 1175 1176 We can also run into a problem if I2 sets a register that I1 1177 uses and I1 gets directly substituted into I3 (not via I2). In that 1178 case, we would be getting the wrong value of I2DEST into I3, so we 1179 must reject the combination. This case occurs when I2 and I1 both 1180 feed into I3, rather than when I1 feeds into I2, which feeds into I3. 1181 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source 1182 of a SET must prevent combination from occurring. 1183 1184 On machines where SMALL_REGISTER_CLASSES is non-zero, we don't combine 1185 if the destination of a SET is a hard register that isn't a user 1186 variable. 1187 1188 Before doing the above check, we first try to expand a field assignment 1189 into a set of logical operations. 1190 1191 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which 1192 we place a register that is both set and used within I3. If more than one 1193 such register is detected, we fail. 1194 1195 Return 1 if the combination is valid, zero otherwise. */ 1196 1197static int 1198combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed) 1199 rtx i3; 1200 rtx *loc; 1201 rtx i2dest; 1202 rtx i1dest; 1203 int i1_not_in_src; 1204 rtx *pi3dest_killed; 1205{ 1206 rtx x = *loc; 1207 1208 if (GET_CODE (x) == SET) 1209 { 1210 rtx set = expand_field_assignment (x); 1211 rtx dest = SET_DEST (set); 1212 rtx src = SET_SRC (set); 1213 rtx inner_dest = dest; 1214 1215#if 0 1216 rtx inner_src = src; 1217#endif 1218 1219 SUBST (*loc, set); 1220 1221 while (GET_CODE (inner_dest) == STRICT_LOW_PART 1222 || GET_CODE (inner_dest) == SUBREG 1223 || GET_CODE (inner_dest) == ZERO_EXTRACT) 1224 inner_dest = XEXP (inner_dest, 0); 1225 1226 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS 1227 was added. */ 1228#if 0 1229 while (GET_CODE (inner_src) == STRICT_LOW_PART 1230 || GET_CODE (inner_src) == SUBREG 1231 || GET_CODE (inner_src) == ZERO_EXTRACT) 1232 inner_src = XEXP (inner_src, 0); 1233 1234 /* If it is better that two different modes keep two different pseudos, 1235 avoid combining them. This avoids producing the following pattern 1236 on a 386: 1237 (set (subreg:SI (reg/v:QI 21) 0) 1238 (lshiftrt:SI (reg/v:SI 20) 1239 (const_int 24))) 1240 If that were made, reload could not handle the pair of 1241 reg 20/21, since it would try to get any GENERAL_REGS 1242 but some of them don't handle QImode. */ 1243 1244 if (rtx_equal_p (inner_src, i2dest) 1245 && GET_CODE (inner_dest) == REG 1246 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest))) 1247 return 0; 1248#endif 1249 1250 /* Check for the case where I3 modifies its output, as 1251 discussed above. */ 1252 if ((inner_dest != dest 1253 && (reg_overlap_mentioned_p (i2dest, inner_dest) 1254 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest)))) 1255 1256 /* This is the same test done in can_combine_p except that we 1257 allow a hard register with SMALL_REGISTER_CLASSES if SRC is a 1258 CALL operation. Moreover, we can't test all_adjacent; we don't 1259 have to, since this instruction will stay in place, thus we are 1260 not considering increasing the lifetime of INNER_DEST. 1261 1262 Also, if this insn sets a function argument, combining it with 1263 something that might need a spill could clobber a previous 1264 function argument; the all_adjacent test in can_combine_p also 1265 checks this; here, we do a more specific test for this case. */ 1266 1267 || (GET_CODE (inner_dest) == REG 1268 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER 1269 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest), 1270 GET_MODE (inner_dest)) 1271 || (SMALL_REGISTER_CLASSES && GET_CODE (src) != CALL 1272 && ! REG_USERVAR_P (inner_dest) 1273 && (FUNCTION_VALUE_REGNO_P (REGNO (inner_dest)) 1274 || (FUNCTION_ARG_REGNO_P (REGNO (inner_dest)) 1275 && i3 != 0 1276 && sets_function_arg_p (prev_nonnote_insn (i3))))))) 1277 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))) 1278 return 0; 1279 1280 /* If DEST is used in I3, it is being killed in this insn, 1281 so record that for later. 1282 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the 1283 STACK_POINTER_REGNUM, since these are always considered to be 1284 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */ 1285 if (pi3dest_killed && GET_CODE (dest) == REG 1286 && reg_referenced_p (dest, PATTERN (i3)) 1287 && REGNO (dest) != FRAME_POINTER_REGNUM 1288#if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM 1289 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM 1290#endif 1291#if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM 1292 && (REGNO (dest) != ARG_POINTER_REGNUM 1293 || ! fixed_regs [REGNO (dest)]) 1294#endif 1295 && REGNO (dest) != STACK_POINTER_REGNUM) 1296 { 1297 if (*pi3dest_killed) 1298 return 0; 1299 1300 *pi3dest_killed = dest; 1301 } 1302 } 1303 1304 else if (GET_CODE (x) == PARALLEL) 1305 { 1306 int i; 1307 1308 for (i = 0; i < XVECLEN (x, 0); i++) 1309 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, 1310 i1_not_in_src, pi3dest_killed)) 1311 return 0; 1312 } 1313 1314 return 1; 1315} 1316 1317/* Determine whether INSN can be used in a combination. Return nonzero if 1318 not. This is used in try_combine to detect early some cases where we 1319 can't perform combinations. */ 1320 1321static int 1322cant_combine_insn_p (insn) 1323 rtx insn; 1324{ 1325 rtx set; 1326 rtx src, dest; 1327 1328 /* If this isn't really an insn, we can't do anything. 1329 This can occur when flow deletes an insn that it has merged into an 1330 auto-increment address. */ 1331 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') 1332 return 1; 1333 1334 /* For the 2.95.3 release, restrict this code to only handle the machines 1335 where it's strictly needed. */ 1336 if (! SMALL_REGISTER_CLASSES) 1337 return 0; 1338 1339 /* Never combine loads and stores involving hard regs. The register 1340 allocator can usually handle such reg-reg moves by tying. If we allow 1341 the combiner to make substitutions of hard regs, we risk aborting in 1342 reload on machines that have SMALL_REGISTER_CLASSES. 1343 As an exception, we allow combinations involving fixed regs; these are 1344 not available to the register allocator so there's no risk involved. */ 1345 1346 set = single_set (insn); 1347 if (! set) 1348 return 0; 1349 src = SET_SRC (set); 1350 dest = SET_DEST (set); 1351 if (GET_CODE (src) == SUBREG) 1352 src = SUBREG_REG (src); 1353 if (GET_CODE (dest) == SUBREG) 1354 dest = SUBREG_REG (dest); 1355 if (REG_P (src) && REG_P (dest) 1356 && ((REGNO (src) < FIRST_PSEUDO_REGISTER 1357 && ! fixed_regs[REGNO (src)]) 1358 || (REGNO (dest) < FIRST_PSEUDO_REGISTER 1359 && ! fixed_regs[REGNO (dest)]))) 1360 return 1; 1361 1362 return 0; 1363} 1364 1365/* Try to combine the insns I1 and I2 into I3. 1366 Here I1 and I2 appear earlier than I3. 1367 I1 can be zero; then we combine just I2 into I3. 1368 1369 It we are combining three insns and the resulting insn is not recognized, 1370 try splitting it into two insns. If that happens, I2 and I3 are retained 1371 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2 1372 are pseudo-deleted. 1373 1374 Return 0 if the combination does not work. Then nothing is changed. 1375 If we did the combination, return the insn at which combine should 1376 resume scanning. */ 1377 1378static rtx 1379try_combine (i3, i2, i1) 1380 register rtx i3, i2, i1; 1381{ 1382 /* New patterns for I3 and I3, respectively. */ 1383 rtx newpat, newi2pat = 0; 1384 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */ 1385 int added_sets_1, added_sets_2; 1386 /* Total number of SETs to put into I3. */ 1387 int total_sets; 1388 /* Nonzero is I2's body now appears in I3. */ 1389 int i2_is_used; 1390 /* INSN_CODEs for new I3, new I2, and user of condition code. */ 1391 int insn_code_number, i2_code_number, other_code_number; 1392 /* Contains I3 if the destination of I3 is used in its source, which means 1393 that the old life of I3 is being killed. If that usage is placed into 1394 I2 and not in I3, a REG_DEAD note must be made. */ 1395 rtx i3dest_killed = 0; 1396 /* SET_DEST and SET_SRC of I2 and I1. */ 1397 rtx i2dest, i2src, i1dest = 0, i1src = 0; 1398 /* PATTERN (I2), or a copy of it in certain cases. */ 1399 rtx i2pat; 1400 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */ 1401 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0; 1402 int i1_feeds_i3 = 0; 1403 /* Notes that must be added to REG_NOTES in I3 and I2. */ 1404 rtx new_i3_notes, new_i2_notes; 1405 /* Notes that we substituted I3 into I2 instead of the normal case. */ 1406 int i3_subst_into_i2 = 0; 1407 /* Notes that I1, I2 or I3 is a MULT operation. */ 1408 int have_mult = 0; 1409 1410 int maxreg; 1411 rtx temp; 1412 register rtx link; 1413 int i; 1414 1415 /* Exit early if one of the insns involved can't be used for 1416 combinations. */ 1417 if (cant_combine_insn_p (i3) 1418 || cant_combine_insn_p (i2) 1419 || (i1 && cant_combine_insn_p (i1)) 1420 /* We also can't do anything if I3 has a 1421 REG_LIBCALL note since we don't want to disrupt the contiguity of a 1422 libcall. */ 1423#if 0 1424 /* ??? This gives worse code, and appears to be unnecessary, since no 1425 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */ 1426 || find_reg_note (i3, REG_LIBCALL, NULL_RTX) 1427#endif 1428 ) 1429 return 0; 1430 1431 combine_attempts++; 1432 1433 undobuf.undos = undobuf.previous_undos = 0; 1434 undobuf.other_insn = 0; 1435 1436 /* Save the current high-water-mark so we can free storage if we didn't 1437 accept this combination. */ 1438 undobuf.storage = (char *) oballoc (0); 1439 1440 /* Reset the hard register usage information. */ 1441 CLEAR_HARD_REG_SET (newpat_used_regs); 1442 1443 /* If I1 and I2 both feed I3, they can be in any order. To simplify the 1444 code below, set I1 to be the earlier of the two insns. */ 1445 if (i1 && INSN_CUID (i1) > INSN_CUID (i2)) 1446 temp = i1, i1 = i2, i2 = temp; 1447 1448 added_links_insn = 0; 1449 1450 /* First check for one important special-case that the code below will 1451 not handle. Namely, the case where I1 is zero, I2 has multiple sets, 1452 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case, 1453 we may be able to replace that destination with the destination of I3. 1454 This occurs in the common code where we compute both a quotient and 1455 remainder into a structure, in which case we want to do the computation 1456 directly into the structure to avoid register-register copies. 1457 1458 We make very conservative checks below and only try to handle the 1459 most common cases of this. For example, we only handle the case 1460 where I2 and I3 are adjacent to avoid making difficult register 1461 usage tests. */ 1462 1463 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET 1464 && GET_CODE (SET_SRC (PATTERN (i3))) == REG 1465 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER 1466 && (! SMALL_REGISTER_CLASSES 1467 || (GET_CODE (SET_DEST (PATTERN (i3))) != REG 1468 || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER 1469 || REG_USERVAR_P (SET_DEST (PATTERN (i3))))) 1470 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3))) 1471 && GET_CODE (PATTERN (i2)) == PARALLEL 1472 && ! side_effects_p (SET_DEST (PATTERN (i3))) 1473 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code 1474 below would need to check what is inside (and reg_overlap_mentioned_p 1475 doesn't support those codes anyway). Don't allow those destinations; 1476 the resulting insn isn't likely to be recognized anyway. */ 1477 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT 1478 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART 1479 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)), 1480 SET_DEST (PATTERN (i3))) 1481 && next_real_insn (i2) == i3) 1482 { 1483 rtx p2 = PATTERN (i2); 1484 1485 /* Make sure that the destination of I3, 1486 which we are going to substitute into one output of I2, 1487 is not used within another output of I2. We must avoid making this: 1488 (parallel [(set (mem (reg 69)) ...) 1489 (set (reg 69) ...)]) 1490 which is not well-defined as to order of actions. 1491 (Besides, reload can't handle output reloads for this.) 1492 1493 The problem can also happen if the dest of I3 is a memory ref, 1494 if another dest in I2 is an indirect memory ref. */ 1495 for (i = 0; i < XVECLEN (p2, 0); i++) 1496 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET 1497 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER) 1498 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)), 1499 SET_DEST (XVECEXP (p2, 0, i)))) 1500 break; 1501 1502 if (i == XVECLEN (p2, 0)) 1503 for (i = 0; i < XVECLEN (p2, 0); i++) 1504 if (SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3))) 1505 { 1506 combine_merges++; 1507 1508 subst_insn = i3; 1509 subst_low_cuid = INSN_CUID (i2); 1510 1511 added_sets_2 = added_sets_1 = 0; 1512 i2dest = SET_SRC (PATTERN (i3)); 1513 1514 /* Replace the dest in I2 with our dest and make the resulting 1515 insn the new pattern for I3. Then skip to where we 1516 validate the pattern. Everything was set up above. */ 1517 SUBST (SET_DEST (XVECEXP (p2, 0, i)), 1518 SET_DEST (PATTERN (i3))); 1519 1520 newpat = p2; 1521 i3_subst_into_i2 = 1; 1522 goto validate_replacement; 1523 } 1524 } 1525 1526#ifndef HAVE_cc0 1527 /* If we have no I1 and I2 looks like: 1528 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0))) 1529 (set Y OP)]) 1530 make up a dummy I1 that is 1531 (set Y OP) 1532 and change I2 to be 1533 (set (reg:CC X) (compare:CC Y (const_int 0))) 1534 1535 (We can ignore any trailing CLOBBERs.) 1536 1537 This undoes a previous combination and allows us to match a branch-and- 1538 decrement insn. */ 1539 1540 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL 1541 && XVECLEN (PATTERN (i2), 0) >= 2 1542 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET 1543 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)))) 1544 == MODE_CC) 1545 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE 1546 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx 1547 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET 1548 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG 1549 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0), 1550 SET_SRC (XVECEXP (PATTERN (i2), 0, 1)))) 1551 { 1552 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--) 1553 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER) 1554 break; 1555 1556 if (i == 1) 1557 { 1558 /* We make I1 with the same INSN_UID as I2. This gives it 1559 the same INSN_CUID for value tracking. Our fake I1 will 1560 never appear in the insn stream so giving it the same INSN_UID 1561 as I2 will not cause a problem. */ 1562 1563 subst_prev_insn = i1 1564 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2, 1565 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX, 1566 NULL_RTX); 1567 1568 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0)); 1569 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0), 1570 SET_DEST (PATTERN (i1))); 1571 } 1572 } 1573#endif 1574 1575 /* Verify that I2 and I1 are valid for combining. */ 1576 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src) 1577 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src))) 1578 { 1579 undo_all (); 1580 return 0; 1581 } 1582 1583 /* Record whether I2DEST is used in I2SRC and similarly for the other 1584 cases. Knowing this will help in register status updating below. */ 1585 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src); 1586 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src); 1587 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src); 1588 1589 /* See if I1 directly feeds into I3. It does if I1DEST is not used 1590 in I2SRC. */ 1591 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src); 1592 1593 /* Ensure that I3's pattern can be the destination of combines. */ 1594 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, 1595 i1 && i2dest_in_i1src && i1_feeds_i3, 1596 &i3dest_killed)) 1597 { 1598 undo_all (); 1599 return 0; 1600 } 1601 1602 /* See if any of the insns is a MULT operation. Unless one is, we will 1603 reject a combination that is, since it must be slower. Be conservative 1604 here. */ 1605 if (GET_CODE (i2src) == MULT 1606 || (i1 != 0 && GET_CODE (i1src) == MULT) 1607 || (GET_CODE (PATTERN (i3)) == SET 1608 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT)) 1609 have_mult = 1; 1610 1611 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd. 1612 We used to do this EXCEPT in one case: I3 has a post-inc in an 1613 output operand. However, that exception can give rise to insns like 1614 mov r3,(r3)+ 1615 which is a famous insn on the PDP-11 where the value of r3 used as the 1616 source was model-dependent. Avoid this sort of thing. */ 1617 1618#if 0 1619 if (!(GET_CODE (PATTERN (i3)) == SET 1620 && GET_CODE (SET_SRC (PATTERN (i3))) == REG 1621 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM 1622 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC 1623 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC))) 1624 /* It's not the exception. */ 1625#endif 1626#ifdef AUTO_INC_DEC 1627 for (link = REG_NOTES (i3); link; link = XEXP (link, 1)) 1628 if (REG_NOTE_KIND (link) == REG_INC 1629 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2)) 1630 || (i1 != 0 1631 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1))))) 1632 { 1633 undo_all (); 1634 return 0; 1635 } 1636#endif 1637 1638 /* See if the SETs in I1 or I2 need to be kept around in the merged 1639 instruction: whenever the value set there is still needed past I3. 1640 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3. 1641 1642 For the SET in I1, we have two cases: If I1 and I2 independently 1643 feed into I3, the set in I1 needs to be kept around if I1DEST dies 1644 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set 1645 in I1 needs to be kept around unless I1DEST dies or is set in either 1646 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions 1647 I1DEST. If so, we know I1 feeds into I2. */ 1648 1649 added_sets_2 = ! dead_or_set_p (i3, i2dest); 1650 1651 added_sets_1 1652 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest) 1653 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest))); 1654 1655 /* If the set in I2 needs to be kept around, we must make a copy of 1656 PATTERN (I2), so that when we substitute I1SRC for I1DEST in 1657 PATTERN (I2), we are only substituting for the original I1DEST, not into 1658 an already-substituted copy. This also prevents making self-referential 1659 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to 1660 I2DEST. */ 1661 1662 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL 1663 ? gen_rtx_SET (VOIDmode, i2dest, i2src) 1664 : PATTERN (i2)); 1665 1666 if (added_sets_2) 1667 i2pat = copy_rtx (i2pat); 1668 1669 combine_merges++; 1670 1671 /* Substitute in the latest insn for the regs set by the earlier ones. */ 1672 1673 maxreg = max_reg_num (); 1674 1675 subst_insn = i3; 1676 1677 /* It is possible that the source of I2 or I1 may be performing an 1678 unneeded operation, such as a ZERO_EXTEND of something that is known 1679 to have the high part zero. Handle that case by letting subst look at 1680 the innermost one of them. 1681 1682 Another way to do this would be to have a function that tries to 1683 simplify a single insn instead of merging two or more insns. We don't 1684 do this because of the potential of infinite loops and because 1685 of the potential extra memory required. However, doing it the way 1686 we are is a bit of a kludge and doesn't catch all cases. 1687 1688 But only do this if -fexpensive-optimizations since it slows things down 1689 and doesn't usually win. */ 1690 1691 if (flag_expensive_optimizations) 1692 { 1693 /* Pass pc_rtx so no substitutions are done, just simplifications. 1694 The cases that we are interested in here do not involve the few 1695 cases were is_replaced is checked. */ 1696 if (i1) 1697 { 1698 subst_low_cuid = INSN_CUID (i1); 1699 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0); 1700 } 1701 else 1702 { 1703 subst_low_cuid = INSN_CUID (i2); 1704 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0); 1705 } 1706 1707 undobuf.previous_undos = undobuf.undos; 1708 } 1709 1710#ifndef HAVE_cc0 1711 /* Many machines that don't use CC0 have insns that can both perform an 1712 arithmetic operation and set the condition code. These operations will 1713 be represented as a PARALLEL with the first element of the vector 1714 being a COMPARE of an arithmetic operation with the constant zero. 1715 The second element of the vector will set some pseudo to the result 1716 of the same arithmetic operation. If we simplify the COMPARE, we won't 1717 match such a pattern and so will generate an extra insn. Here we test 1718 for this case, where both the comparison and the operation result are 1719 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with 1720 I2SRC. Later we will make the PARALLEL that contains I2. */ 1721 1722 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET 1723 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE 1724 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx 1725 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest)) 1726 { 1727#ifdef EXTRA_CC_MODES 1728 rtx *cc_use; 1729 enum machine_mode compare_mode; 1730#endif 1731 1732 newpat = PATTERN (i3); 1733 SUBST (XEXP (SET_SRC (newpat), 0), i2src); 1734 1735 i2_is_used = 1; 1736 1737#ifdef EXTRA_CC_MODES 1738 /* See if a COMPARE with the operand we substituted in should be done 1739 with the mode that is currently being used. If not, do the same 1740 processing we do in `subst' for a SET; namely, if the destination 1741 is used only once, try to replace it with a register of the proper 1742 mode and also replace the COMPARE. */ 1743 if (undobuf.other_insn == 0 1744 && (cc_use = find_single_use (SET_DEST (newpat), i3, 1745 &undobuf.other_insn)) 1746 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use), 1747 i2src, const0_rtx)) 1748 != GET_MODE (SET_DEST (newpat)))) 1749 { 1750 int regno = REGNO (SET_DEST (newpat)); 1751 rtx new_dest = gen_rtx_REG (compare_mode, regno); 1752 1753 if (regno < FIRST_PSEUDO_REGISTER 1754 || (REG_N_SETS (regno) == 1 && ! added_sets_2 1755 && ! REG_USERVAR_P (SET_DEST (newpat)))) 1756 { 1757 if (regno >= FIRST_PSEUDO_REGISTER) 1758 SUBST (regno_reg_rtx[regno], new_dest); 1759 1760 SUBST (SET_DEST (newpat), new_dest); 1761 SUBST (XEXP (*cc_use, 0), new_dest); 1762 SUBST (SET_SRC (newpat), 1763 gen_rtx_combine (COMPARE, compare_mode, 1764 i2src, const0_rtx)); 1765 } 1766 else 1767 undobuf.other_insn = 0; 1768 } 1769#endif 1770 } 1771 else 1772#endif 1773 { 1774 n_occurrences = 0; /* `subst' counts here */ 1775 1776 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we 1777 need to make a unique copy of I2SRC each time we substitute it 1778 to avoid self-referential rtl. */ 1779 1780 subst_low_cuid = INSN_CUID (i2); 1781 newpat = subst (PATTERN (i3), i2dest, i2src, 0, 1782 ! i1_feeds_i3 && i1dest_in_i1src); 1783 undobuf.previous_undos = undobuf.undos; 1784 1785 /* Record whether i2's body now appears within i3's body. */ 1786 i2_is_used = n_occurrences; 1787 } 1788 1789 /* If we already got a failure, don't try to do more. Otherwise, 1790 try to substitute in I1 if we have it. */ 1791 1792 if (i1 && GET_CODE (newpat) != CLOBBER) 1793 { 1794 /* Before we can do this substitution, we must redo the test done 1795 above (see detailed comments there) that ensures that I1DEST 1796 isn't mentioned in any SETs in NEWPAT that are field assignments. */ 1797 1798 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, 1799 0, NULL_PTR)) 1800 { 1801 undo_all (); 1802 return 0; 1803 } 1804 1805 n_occurrences = 0; 1806 subst_low_cuid = INSN_CUID (i1); 1807 newpat = subst (newpat, i1dest, i1src, 0, 0); 1808 undobuf.previous_undos = undobuf.undos; 1809 } 1810 1811 /* Fail if an autoincrement side-effect has been duplicated. Be careful 1812 to count all the ways that I2SRC and I1SRC can be used. */ 1813 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0 1814 && i2_is_used + added_sets_2 > 1) 1815 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0 1816 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3) 1817 > 1)) 1818 /* Fail if we tried to make a new register (we used to abort, but there's 1819 really no reason to). */ 1820 || max_reg_num () != maxreg 1821 /* Fail if we couldn't do something and have a CLOBBER. */ 1822 || GET_CODE (newpat) == CLOBBER 1823 /* Fail if this new pattern is a MULT and we didn't have one before 1824 at the outer level. */ 1825 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT 1826 && ! have_mult)) 1827 { 1828 undo_all (); 1829 return 0; 1830 } 1831 1832 /* If the actions of the earlier insns must be kept 1833 in addition to substituting them into the latest one, 1834 we must make a new PARALLEL for the latest insn 1835 to hold additional the SETs. */ 1836 1837 if (added_sets_1 || added_sets_2) 1838 { 1839 combine_extras++; 1840 1841 if (GET_CODE (newpat) == PARALLEL) 1842 { 1843 rtvec old = XVEC (newpat, 0); 1844 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2; 1845 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets)); 1846 bcopy ((char *) &old->elem[0], (char *) XVEC (newpat, 0)->elem, 1847 sizeof (old->elem[0]) * old->num_elem); 1848 } 1849 else 1850 { 1851 rtx old = newpat; 1852 total_sets = 1 + added_sets_1 + added_sets_2; 1853 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets)); 1854 XVECEXP (newpat, 0, 0) = old; 1855 } 1856 1857 if (added_sets_1) 1858 XVECEXP (newpat, 0, --total_sets) 1859 = (GET_CODE (PATTERN (i1)) == PARALLEL 1860 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1)); 1861 1862 if (added_sets_2) 1863 { 1864 /* If there is no I1, use I2's body as is. We used to also not do 1865 the subst call below if I2 was substituted into I3, 1866 but that could lose a simplification. */ 1867 if (i1 == 0) 1868 XVECEXP (newpat, 0, --total_sets) = i2pat; 1869 else 1870 /* See comment where i2pat is assigned. */ 1871 XVECEXP (newpat, 0, --total_sets) 1872 = subst (i2pat, i1dest, i1src, 0, 0); 1873 } 1874 } 1875 1876 /* We come here when we are replacing a destination in I2 with the 1877 destination of I3. */ 1878 validate_replacement: 1879 1880 /* Note which hard regs this insn has as inputs. */ 1881 mark_used_regs_combine (newpat); 1882 1883 /* Is the result of combination a valid instruction? */ 1884 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 1885 1886 /* If the result isn't valid, see if it is a PARALLEL of two SETs where 1887 the second SET's destination is a register that is unused. In that case, 1888 we just need the first SET. This can occur when simplifying a divmod 1889 insn. We *must* test for this case here because the code below that 1890 splits two independent SETs doesn't handle this case correctly when it 1891 updates the register status. Also check the case where the first 1892 SET's destination is unused. That would not cause incorrect code, but 1893 does cause an unneeded insn to remain. */ 1894 1895 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL 1896 && XVECLEN (newpat, 0) == 2 1897 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET 1898 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET 1899 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG 1900 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1))) 1901 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1))) 1902 && asm_noperands (newpat) < 0) 1903 { 1904 newpat = XVECEXP (newpat, 0, 0); 1905 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 1906 } 1907 1908 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL 1909 && XVECLEN (newpat, 0) == 2 1910 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET 1911 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET 1912 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG 1913 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0))) 1914 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0))) 1915 && asm_noperands (newpat) < 0) 1916 { 1917 newpat = XVECEXP (newpat, 0, 1); 1918 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 1919 } 1920 1921 /* If we were combining three insns and the result is a simple SET 1922 with no ASM_OPERANDS that wasn't recognized, try to split it into two 1923 insns. There are two ways to do this. It can be split using a 1924 machine-specific method (like when you have an addition of a large 1925 constant) or by combine in the function find_split_point. */ 1926 1927 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET 1928 && asm_noperands (newpat) < 0) 1929 { 1930 rtx m_split, *split; 1931 rtx ni2dest = i2dest; 1932 1933 /* See if the MD file can split NEWPAT. If it can't, see if letting it 1934 use I2DEST as a scratch register will help. In the latter case, 1935 convert I2DEST to the mode of the source of NEWPAT if we can. */ 1936 1937 m_split = split_insns (newpat, i3); 1938 1939 /* We can only use I2DEST as a scratch reg if it doesn't overlap any 1940 inputs of NEWPAT. */ 1941 1942 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be 1943 possible to try that as a scratch reg. This would require adding 1944 more code to make it work though. */ 1945 1946 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat)) 1947 { 1948 /* If I2DEST is a hard register or the only use of a pseudo, 1949 we can change its mode. */ 1950 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest) 1951 && GET_MODE (SET_DEST (newpat)) != VOIDmode 1952 && GET_CODE (i2dest) == REG 1953 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER 1954 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2 1955 && ! REG_USERVAR_P (i2dest)))) 1956 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)), 1957 REGNO (i2dest)); 1958 1959 m_split = split_insns 1960 (gen_rtx_PARALLEL (VOIDmode, 1961 gen_rtvec (2, newpat, 1962 gen_rtx_CLOBBER (VOIDmode, 1963 ni2dest))), 1964 i3); 1965 } 1966 1967 if (m_split && GET_CODE (m_split) == SEQUENCE 1968 && XVECLEN (m_split, 0) == 2 1969 && (next_real_insn (i2) == i3 1970 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)), 1971 INSN_CUID (i2)))) 1972 { 1973 rtx i2set, i3set; 1974 rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1)); 1975 newi2pat = PATTERN (XVECEXP (m_split, 0, 0)); 1976 1977 i3set = single_set (XVECEXP (m_split, 0, 1)); 1978 i2set = single_set (XVECEXP (m_split, 0, 0)); 1979 1980 /* In case we changed the mode of I2DEST, replace it in the 1981 pseudo-register table here. We can't do it above in case this 1982 code doesn't get executed and we do a split the other way. */ 1983 1984 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER) 1985 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest); 1986 1987 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); 1988 1989 /* If I2 or I3 has multiple SETs, we won't know how to track 1990 register status, so don't use these insns. If I2's destination 1991 is used between I2 and I3, we also can't use these insns. */ 1992 1993 if (i2_code_number >= 0 && i2set && i3set 1994 && (next_real_insn (i2) == i3 1995 || ! reg_used_between_p (SET_DEST (i2set), i2, i3))) 1996 insn_code_number = recog_for_combine (&newi3pat, i3, 1997 &new_i3_notes); 1998 if (insn_code_number >= 0) 1999 newpat = newi3pat; 2000 2001 /* It is possible that both insns now set the destination of I3. 2002 If so, we must show an extra use of it. */ 2003 2004 if (insn_code_number >= 0) 2005 { 2006 rtx new_i3_dest = SET_DEST (i3set); 2007 rtx new_i2_dest = SET_DEST (i2set); 2008 2009 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT 2010 || GET_CODE (new_i3_dest) == STRICT_LOW_PART 2011 || GET_CODE (new_i3_dest) == SUBREG) 2012 new_i3_dest = XEXP (new_i3_dest, 0); 2013 2014 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT 2015 || GET_CODE (new_i2_dest) == STRICT_LOW_PART 2016 || GET_CODE (new_i2_dest) == SUBREG) 2017 new_i2_dest = XEXP (new_i2_dest, 0); 2018 2019 if (GET_CODE (new_i3_dest) == REG 2020 && GET_CODE (new_i2_dest) == REG 2021 && REGNO (new_i3_dest) == REGNO (new_i2_dest)) 2022 REG_N_SETS (REGNO (new_i2_dest))++; 2023 } 2024 } 2025 2026 /* If we can split it and use I2DEST, go ahead and see if that 2027 helps things be recognized. Verify that none of the registers 2028 are set between I2 and I3. */ 2029 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0 2030#ifdef HAVE_cc0 2031 && GET_CODE (i2dest) == REG 2032#endif 2033 /* We need I2DEST in the proper mode. If it is a hard register 2034 or the only use of a pseudo, we can change its mode. */ 2035 && (GET_MODE (*split) == GET_MODE (i2dest) 2036 || GET_MODE (*split) == VOIDmode 2037 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER 2038 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2 2039 && ! REG_USERVAR_P (i2dest))) 2040 && (next_real_insn (i2) == i3 2041 || ! use_crosses_set_p (*split, INSN_CUID (i2))) 2042 /* We can't overwrite I2DEST if its value is still used by 2043 NEWPAT. */ 2044 && ! reg_referenced_p (i2dest, newpat)) 2045 { 2046 rtx newdest = i2dest; 2047 enum rtx_code split_code = GET_CODE (*split); 2048 enum machine_mode split_mode = GET_MODE (*split); 2049 2050 /* Get NEWDEST as a register in the proper mode. We have already 2051 validated that we can do this. */ 2052 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode) 2053 { 2054 newdest = gen_rtx_REG (split_mode, REGNO (i2dest)); 2055 2056 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER) 2057 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest); 2058 } 2059 2060 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to 2061 an ASHIFT. This can occur if it was inside a PLUS and hence 2062 appeared to be a memory address. This is a kludge. */ 2063 if (split_code == MULT 2064 && GET_CODE (XEXP (*split, 1)) == CONST_INT 2065 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0) 2066 { 2067 SUBST (*split, gen_rtx_combine (ASHIFT, split_mode, 2068 XEXP (*split, 0), GEN_INT (i))); 2069 /* Update split_code because we may not have a multiply 2070 anymore. */ 2071 split_code = GET_CODE (*split); 2072 } 2073 2074#ifdef INSN_SCHEDULING 2075 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should 2076 be written as a ZERO_EXTEND. */ 2077 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM) 2078 SUBST (*split, gen_rtx_combine (ZERO_EXTEND, split_mode, 2079 XEXP (*split, 0))); 2080#endif 2081 2082 newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split); 2083 SUBST (*split, newdest); 2084 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); 2085 2086 /* If the split point was a MULT and we didn't have one before, 2087 don't use one now. */ 2088 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult)) 2089 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 2090 } 2091 } 2092 2093 /* Check for a case where we loaded from memory in a narrow mode and 2094 then sign extended it, but we need both registers. In that case, 2095 we have a PARALLEL with both loads from the same memory location. 2096 We can split this into a load from memory followed by a register-register 2097 copy. This saves at least one insn, more if register allocation can 2098 eliminate the copy. 2099 2100 We cannot do this if the destination of the second assignment is 2101 a register that we have already assumed is zero-extended. Similarly 2102 for a SUBREG of such a register. */ 2103 2104 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0 2105 && GET_CODE (newpat) == PARALLEL 2106 && XVECLEN (newpat, 0) == 2 2107 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET 2108 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND 2109 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET 2110 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)), 2111 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0)) 2112 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)), 2113 INSN_CUID (i2)) 2114 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT 2115 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART 2116 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)), 2117 (GET_CODE (temp) == REG 2118 && reg_nonzero_bits[REGNO (temp)] != 0 2119 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD 2120 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT 2121 && (reg_nonzero_bits[REGNO (temp)] 2122 != GET_MODE_MASK (word_mode)))) 2123 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG 2124 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))), 2125 (GET_CODE (temp) == REG 2126 && reg_nonzero_bits[REGNO (temp)] != 0 2127 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD 2128 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT 2129 && (reg_nonzero_bits[REGNO (temp)] 2130 != GET_MODE_MASK (word_mode))))) 2131 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)), 2132 SET_SRC (XVECEXP (newpat, 0, 1))) 2133 && ! find_reg_note (i3, REG_UNUSED, 2134 SET_DEST (XVECEXP (newpat, 0, 0)))) 2135 { 2136 rtx ni2dest; 2137 2138 newi2pat = XVECEXP (newpat, 0, 0); 2139 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0)); 2140 newpat = XVECEXP (newpat, 0, 1); 2141 SUBST (SET_SRC (newpat), 2142 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest)); 2143 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); 2144 2145 if (i2_code_number >= 0) 2146 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 2147 2148 if (insn_code_number >= 0) 2149 { 2150 rtx insn; 2151 rtx link; 2152 2153 /* If we will be able to accept this, we have made a change to the 2154 destination of I3. This can invalidate a LOG_LINKS pointing 2155 to I3. No other part of combine.c makes such a transformation. 2156 2157 The new I3 will have a destination that was previously the 2158 destination of I1 or I2 and which was used in i2 or I3. Call 2159 distribute_links to make a LOG_LINK from the next use of 2160 that destination. */ 2161 2162 PATTERN (i3) = newpat; 2163 distribute_links (gen_rtx_INSN_LIST (VOIDmode, i3, NULL_RTX)); 2164 2165 /* I3 now uses what used to be its destination and which is 2166 now I2's destination. That means we need a LOG_LINK from 2167 I3 to I2. But we used to have one, so we still will. 2168 2169 However, some later insn might be using I2's dest and have 2170 a LOG_LINK pointing at I3. We must remove this link. 2171 The simplest way to remove the link is to point it at I1, 2172 which we know will be a NOTE. */ 2173 2174 for (insn = NEXT_INSN (i3); 2175 insn && (this_basic_block == n_basic_blocks - 1 2176 || insn != BLOCK_HEAD (this_basic_block + 1)); 2177 insn = NEXT_INSN (insn)) 2178 { 2179 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i' 2180 && reg_referenced_p (ni2dest, PATTERN (insn))) 2181 { 2182 for (link = LOG_LINKS (insn); link; 2183 link = XEXP (link, 1)) 2184 if (XEXP (link, 0) == i3) 2185 XEXP (link, 0) = i1; 2186 2187 break; 2188 } 2189 } 2190 } 2191 } 2192 2193 /* Similarly, check for a case where we have a PARALLEL of two independent 2194 SETs but we started with three insns. In this case, we can do the sets 2195 as two separate insns. This case occurs when some SET allows two 2196 other insns to combine, but the destination of that SET is still live. */ 2197 2198 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0 2199 && GET_CODE (newpat) == PARALLEL 2200 && XVECLEN (newpat, 0) == 2 2201 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET 2202 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT 2203 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART 2204 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET 2205 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT 2206 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART 2207 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)), 2208 INSN_CUID (i2)) 2209 /* Don't pass sets with (USE (MEM ...)) dests to the following. */ 2210 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE 2211 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE 2212 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)), 2213 XVECEXP (newpat, 0, 0)) 2214 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)), 2215 XVECEXP (newpat, 0, 1))) 2216 { 2217 /* Normally, it doesn't matter which of the two is done first, 2218 but it does if one references cc0. In that case, it has to 2219 be first. */ 2220#ifdef HAVE_cc0 2221 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))) 2222 { 2223 newi2pat = XVECEXP (newpat, 0, 0); 2224 newpat = XVECEXP (newpat, 0, 1); 2225 } 2226 else 2227#endif 2228 { 2229 newi2pat = XVECEXP (newpat, 0, 1); 2230 newpat = XVECEXP (newpat, 0, 0); 2231 } 2232 2233 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); 2234 2235 if (i2_code_number >= 0) 2236 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 2237 } 2238 2239 /* If it still isn't recognized, fail and change things back the way they 2240 were. */ 2241 if ((insn_code_number < 0 2242 /* Is the result a reasonable ASM_OPERANDS? */ 2243 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2))) 2244 { 2245 undo_all (); 2246 return 0; 2247 } 2248 2249 /* If we had to change another insn, make sure it is valid also. */ 2250 if (undobuf.other_insn) 2251 { 2252 rtx other_pat = PATTERN (undobuf.other_insn); 2253 rtx new_other_notes; 2254 rtx note, next; 2255 2256 CLEAR_HARD_REG_SET (newpat_used_regs); 2257 2258 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn, 2259 &new_other_notes); 2260 2261 if (other_code_number < 0 && ! check_asm_operands (other_pat)) 2262 { 2263 undo_all (); 2264 return 0; 2265 } 2266 2267 PATTERN (undobuf.other_insn) = other_pat; 2268 2269 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they 2270 are still valid. Then add any non-duplicate notes added by 2271 recog_for_combine. */ 2272 for (note = REG_NOTES (undobuf.other_insn); note; note = next) 2273 { 2274 next = XEXP (note, 1); 2275 2276 if (REG_NOTE_KIND (note) == REG_UNUSED 2277 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn))) 2278 { 2279 if (GET_CODE (XEXP (note, 0)) == REG) 2280 REG_N_DEATHS (REGNO (XEXP (note, 0)))--; 2281 2282 remove_note (undobuf.other_insn, note); 2283 } 2284 } 2285 2286 for (note = new_other_notes; note; note = XEXP (note, 1)) 2287 if (GET_CODE (XEXP (note, 0)) == REG) 2288 REG_N_DEATHS (REGNO (XEXP (note, 0)))++; 2289 2290 distribute_notes (new_other_notes, undobuf.other_insn, 2291 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX); 2292 } 2293 2294 /* We now know that we can do this combination. Merge the insns and 2295 update the status of registers and LOG_LINKS. */ 2296 2297 { 2298 rtx i3notes, i2notes, i1notes = 0; 2299 rtx i3links, i2links, i1links = 0; 2300 rtx midnotes = 0; 2301 register int regno; 2302 /* Compute which registers we expect to eliminate. newi2pat may be setting 2303 either i3dest or i2dest, so we must check it. Also, i1dest may be the 2304 same as i3dest, in which case newi2pat may be setting i1dest. */ 2305 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat)) 2306 || i2dest_in_i2src || i2dest_in_i1src 2307 ? 0 : i2dest); 2308 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src 2309 || (newi2pat && reg_set_p (i1dest, newi2pat)) 2310 ? 0 : i1dest); 2311 2312 /* Get the old REG_NOTES and LOG_LINKS from all our insns and 2313 clear them. */ 2314 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3); 2315 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2); 2316 if (i1) 2317 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1); 2318 2319 /* Ensure that we do not have something that should not be shared but 2320 occurs multiple times in the new insns. Check this by first 2321 resetting all the `used' flags and then copying anything is shared. */ 2322 2323 reset_used_flags (i3notes); 2324 reset_used_flags (i2notes); 2325 reset_used_flags (i1notes); 2326 reset_used_flags (newpat); 2327 reset_used_flags (newi2pat); 2328 if (undobuf.other_insn) 2329 reset_used_flags (PATTERN (undobuf.other_insn)); 2330 2331 i3notes = copy_rtx_if_shared (i3notes); 2332 i2notes = copy_rtx_if_shared (i2notes); 2333 i1notes = copy_rtx_if_shared (i1notes); 2334 newpat = copy_rtx_if_shared (newpat); 2335 newi2pat = copy_rtx_if_shared (newi2pat); 2336 if (undobuf.other_insn) 2337 reset_used_flags (PATTERN (undobuf.other_insn)); 2338 2339 INSN_CODE (i3) = insn_code_number; 2340 PATTERN (i3) = newpat; 2341 if (undobuf.other_insn) 2342 INSN_CODE (undobuf.other_insn) = other_code_number; 2343 2344 /* We had one special case above where I2 had more than one set and 2345 we replaced a destination of one of those sets with the destination 2346 of I3. In that case, we have to update LOG_LINKS of insns later 2347 in this basic block. Note that this (expensive) case is rare. 2348 2349 Also, in this case, we must pretend that all REG_NOTEs for I2 2350 actually came from I3, so that REG_UNUSED notes from I2 will be 2351 properly handled. */ 2352 2353 if (i3_subst_into_i2) 2354 { 2355 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++) 2356 if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG 2357 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest 2358 && ! find_reg_note (i2, REG_UNUSED, 2359 SET_DEST (XVECEXP (PATTERN (i2), 0, i)))) 2360 for (temp = NEXT_INSN (i2); 2361 temp && (this_basic_block == n_basic_blocks - 1 2362 || BLOCK_HEAD (this_basic_block) != temp); 2363 temp = NEXT_INSN (temp)) 2364 if (temp != i3 && GET_RTX_CLASS (GET_CODE (temp)) == 'i') 2365 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1)) 2366 if (XEXP (link, 0) == i2) 2367 XEXP (link, 0) = i3; 2368 2369 if (i3notes) 2370 { 2371 rtx link = i3notes; 2372 while (XEXP (link, 1)) 2373 link = XEXP (link, 1); 2374 XEXP (link, 1) = i2notes; 2375 } 2376 else 2377 i3notes = i2notes; 2378 i2notes = 0; 2379 } 2380 2381 LOG_LINKS (i3) = 0; 2382 REG_NOTES (i3) = 0; 2383 LOG_LINKS (i2) = 0; 2384 REG_NOTES (i2) = 0; 2385 2386 if (newi2pat) 2387 { 2388 INSN_CODE (i2) = i2_code_number; 2389 PATTERN (i2) = newi2pat; 2390 } 2391 else 2392 { 2393 PUT_CODE (i2, NOTE); 2394 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED; 2395 NOTE_SOURCE_FILE (i2) = 0; 2396 } 2397 2398 if (i1) 2399 { 2400 LOG_LINKS (i1) = 0; 2401 REG_NOTES (i1) = 0; 2402 PUT_CODE (i1, NOTE); 2403 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED; 2404 NOTE_SOURCE_FILE (i1) = 0; 2405 } 2406 2407 /* Get death notes for everything that is now used in either I3 or 2408 I2 and used to die in a previous insn. If we built two new 2409 patterns, move from I1 to I2 then I2 to I3 so that we get the 2410 proper movement on registers that I2 modifies. */ 2411 2412 if (newi2pat) 2413 { 2414 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes); 2415 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes); 2416 } 2417 else 2418 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2), 2419 i3, &midnotes); 2420 2421 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */ 2422 if (i3notes) 2423 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX, 2424 elim_i2, elim_i1); 2425 if (i2notes) 2426 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX, 2427 elim_i2, elim_i1); 2428 if (i1notes) 2429 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX, 2430 elim_i2, elim_i1); 2431 if (midnotes) 2432 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX, 2433 elim_i2, elim_i1); 2434 2435 /* Distribute any notes added to I2 or I3 by recog_for_combine. We 2436 know these are REG_UNUSED and want them to go to the desired insn, 2437 so we always pass it as i3. We have not counted the notes in 2438 reg_n_deaths yet, so we need to do so now. */ 2439 2440 if (newi2pat && new_i2_notes) 2441 { 2442 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1)) 2443 if (GET_CODE (XEXP (temp, 0)) == REG) 2444 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++; 2445 2446 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX); 2447 } 2448 2449 if (new_i3_notes) 2450 { 2451 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1)) 2452 if (GET_CODE (XEXP (temp, 0)) == REG) 2453 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++; 2454 2455 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX); 2456 } 2457 2458 /* If I3DEST was used in I3SRC, it really died in I3. We may need to 2459 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets 2460 I3DEST, the death must be somewhere before I2, not I3. If we passed I3 2461 in that case, it might delete I2. Similarly for I2 and I1. 2462 Show an additional death due to the REG_DEAD note we make here. If 2463 we discard it in distribute_notes, we will decrement it again. */ 2464 2465 if (i3dest_killed) 2466 { 2467 if (GET_CODE (i3dest_killed) == REG) 2468 REG_N_DEATHS (REGNO (i3dest_killed))++; 2469 2470 if (newi2pat && reg_set_p (i3dest_killed, newi2pat)) 2471 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed, 2472 NULL_RTX), 2473 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1); 2474 else 2475 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed, 2476 NULL_RTX), 2477 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX, 2478 elim_i2, elim_i1); 2479 } 2480 2481 if (i2dest_in_i2src) 2482 { 2483 if (GET_CODE (i2dest) == REG) 2484 REG_N_DEATHS (REGNO (i2dest))++; 2485 2486 if (newi2pat && reg_set_p (i2dest, newi2pat)) 2487 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX), 2488 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX); 2489 else 2490 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX), 2491 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX, 2492 NULL_RTX, NULL_RTX); 2493 } 2494 2495 if (i1dest_in_i1src) 2496 { 2497 if (GET_CODE (i1dest) == REG) 2498 REG_N_DEATHS (REGNO (i1dest))++; 2499 2500 if (newi2pat && reg_set_p (i1dest, newi2pat)) 2501 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX), 2502 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX); 2503 else 2504 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX), 2505 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX, 2506 NULL_RTX, NULL_RTX); 2507 } 2508 2509 distribute_links (i3links); 2510 distribute_links (i2links); 2511 distribute_links (i1links); 2512 2513 if (GET_CODE (i2dest) == REG) 2514 { 2515 rtx link; 2516 rtx i2_insn = 0, i2_val = 0, set; 2517 2518 /* The insn that used to set this register doesn't exist, and 2519 this life of the register may not exist either. See if one of 2520 I3's links points to an insn that sets I2DEST. If it does, 2521 that is now the last known value for I2DEST. If we don't update 2522 this and I2 set the register to a value that depended on its old 2523 contents, we will get confused. If this insn is used, thing 2524 will be set correctly in combine_instructions. */ 2525 2526 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1)) 2527 if ((set = single_set (XEXP (link, 0))) != 0 2528 && rtx_equal_p (i2dest, SET_DEST (set))) 2529 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set); 2530 2531 record_value_for_reg (i2dest, i2_insn, i2_val); 2532 2533 /* If the reg formerly set in I2 died only once and that was in I3, 2534 zero its use count so it won't make `reload' do any work. */ 2535 if (! added_sets_2 2536 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat)) 2537 && ! i2dest_in_i2src) 2538 { 2539 regno = REGNO (i2dest); 2540 REG_N_SETS (regno)--; 2541 if (REG_N_SETS (regno) == 0 2542 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, 2543 regno)) 2544 REG_N_REFS (regno) = 0; 2545 } 2546 } 2547 2548 if (i1 && GET_CODE (i1dest) == REG) 2549 { 2550 rtx link; 2551 rtx i1_insn = 0, i1_val = 0, set; 2552 2553 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1)) 2554 if ((set = single_set (XEXP (link, 0))) != 0 2555 && rtx_equal_p (i1dest, SET_DEST (set))) 2556 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set); 2557 2558 record_value_for_reg (i1dest, i1_insn, i1_val); 2559 2560 regno = REGNO (i1dest); 2561 if (! added_sets_1 && ! i1dest_in_i1src) 2562 { 2563 REG_N_SETS (regno)--; 2564 if (REG_N_SETS (regno) == 0 2565 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, 2566 regno)) 2567 REG_N_REFS (regno) = 0; 2568 } 2569 } 2570 2571 /* Update reg_nonzero_bits et al for any changes that may have been made 2572 to this insn. */ 2573 2574 note_stores (newpat, set_nonzero_bits_and_sign_copies); 2575 if (newi2pat) 2576 note_stores (newi2pat, set_nonzero_bits_and_sign_copies); 2577 2578 /* If I3 is now an unconditional jump, ensure that it has a 2579 BARRIER following it since it may have initially been a 2580 conditional jump. It may also be the last nonnote insn. */ 2581 2582 if ((GET_CODE (newpat) == RETURN || simplejump_p (i3)) 2583 && ((temp = next_nonnote_insn (i3)) == NULL_RTX 2584 || GET_CODE (temp) != BARRIER)) 2585 emit_barrier_after (i3); 2586 } 2587 2588 combine_successes++; 2589 2590 /* Clear this here, so that subsequent get_last_value calls are not 2591 affected. */ 2592 subst_prev_insn = NULL_RTX; 2593 2594 if (added_links_insn 2595 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2)) 2596 && INSN_CUID (added_links_insn) < INSN_CUID (i3)) 2597 return added_links_insn; 2598 else 2599 return newi2pat ? i2 : i3; 2600} 2601 2602/* Undo all the modifications recorded in undobuf. */ 2603 2604static void 2605undo_all () 2606{ 2607 struct undo *undo, *next; 2608 2609 for (undo = undobuf.undos; undo; undo = next) 2610 { 2611 next = undo->next; 2612 if (undo->is_int) 2613 *undo->where.i = undo->old_contents.i; 2614 else 2615 *undo->where.r = undo->old_contents.r; 2616 2617 undo->next = undobuf.frees; 2618 undobuf.frees = undo; 2619 } 2620 2621 obfree (undobuf.storage); 2622 undobuf.undos = undobuf.previous_undos = 0; 2623 2624 /* Clear this here, so that subsequent get_last_value calls are not 2625 affected. */ 2626 subst_prev_insn = NULL_RTX; 2627} 2628 2629/* Find the innermost point within the rtx at LOC, possibly LOC itself, 2630 where we have an arithmetic expression and return that point. LOC will 2631 be inside INSN. 2632 2633 try_combine will call this function to see if an insn can be split into 2634 two insns. */ 2635 2636static rtx * 2637find_split_point (loc, insn) 2638 rtx *loc; 2639 rtx insn; 2640{ 2641 rtx x = *loc; 2642 enum rtx_code code = GET_CODE (x); 2643 rtx *split; 2644 int len = 0, pos, unsignedp; 2645 rtx inner; 2646 2647 /* First special-case some codes. */ 2648 switch (code) 2649 { 2650 case SUBREG: 2651#ifdef INSN_SCHEDULING 2652 /* If we are making a paradoxical SUBREG invalid, it becomes a split 2653 point. */ 2654 if (GET_CODE (SUBREG_REG (x)) == MEM) 2655 return loc; 2656#endif 2657 return find_split_point (&SUBREG_REG (x), insn); 2658 2659 case MEM: 2660#ifdef HAVE_lo_sum 2661 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it 2662 using LO_SUM and HIGH. */ 2663 if (GET_CODE (XEXP (x, 0)) == CONST 2664 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF) 2665 { 2666 SUBST (XEXP (x, 0), 2667 gen_rtx_combine (LO_SUM, Pmode, 2668 gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)), 2669 XEXP (x, 0))); 2670 return &XEXP (XEXP (x, 0), 0); 2671 } 2672#endif 2673 2674 /* If we have a PLUS whose second operand is a constant and the 2675 address is not valid, perhaps will can split it up using 2676 the machine-specific way to split large constants. We use 2677 the first pseudo-reg (one of the virtual regs) as a placeholder; 2678 it will not remain in the result. */ 2679 if (GET_CODE (XEXP (x, 0)) == PLUS 2680 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 2681 && ! memory_address_p (GET_MODE (x), XEXP (x, 0))) 2682 { 2683 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER]; 2684 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)), 2685 subst_insn); 2686 2687 /* This should have produced two insns, each of which sets our 2688 placeholder. If the source of the second is a valid address, 2689 we can make put both sources together and make a split point 2690 in the middle. */ 2691 2692 if (seq && XVECLEN (seq, 0) == 2 2693 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN 2694 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET 2695 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg 2696 && ! reg_mentioned_p (reg, 2697 SET_SRC (PATTERN (XVECEXP (seq, 0, 0)))) 2698 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN 2699 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET 2700 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg 2701 && memory_address_p (GET_MODE (x), 2702 SET_SRC (PATTERN (XVECEXP (seq, 0, 1))))) 2703 { 2704 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0))); 2705 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1))); 2706 2707 /* Replace the placeholder in SRC2 with SRC1. If we can 2708 find where in SRC2 it was placed, that can become our 2709 split point and we can replace this address with SRC2. 2710 Just try two obvious places. */ 2711 2712 src2 = replace_rtx (src2, reg, src1); 2713 split = 0; 2714 if (XEXP (src2, 0) == src1) 2715 split = &XEXP (src2, 0); 2716 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e' 2717 && XEXP (XEXP (src2, 0), 0) == src1) 2718 split = &XEXP (XEXP (src2, 0), 0); 2719 2720 if (split) 2721 { 2722 SUBST (XEXP (x, 0), src2); 2723 return split; 2724 } 2725 } 2726 2727 /* If that didn't work, perhaps the first operand is complex and 2728 needs to be computed separately, so make a split point there. 2729 This will occur on machines that just support REG + CONST 2730 and have a constant moved through some previous computation. */ 2731 2732 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o' 2733 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG 2734 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0)))) 2735 == 'o'))) 2736 return &XEXP (XEXP (x, 0), 0); 2737 } 2738 break; 2739 2740 case SET: 2741#ifdef HAVE_cc0 2742 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a 2743 ZERO_EXTRACT, the most likely reason why this doesn't match is that 2744 we need to put the operand into a register. So split at that 2745 point. */ 2746 2747 if (SET_DEST (x) == cc0_rtx 2748 && GET_CODE (SET_SRC (x)) != COMPARE 2749 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT 2750 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o' 2751 && ! (GET_CODE (SET_SRC (x)) == SUBREG 2752 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o')) 2753 return &SET_SRC (x); 2754#endif 2755 2756 /* See if we can split SET_SRC as it stands. */ 2757 split = find_split_point (&SET_SRC (x), insn); 2758 if (split && split != &SET_SRC (x)) 2759 return split; 2760 2761 /* See if we can split SET_DEST as it stands. */ 2762 split = find_split_point (&SET_DEST (x), insn); 2763 if (split && split != &SET_DEST (x)) 2764 return split; 2765 2766 /* See if this is a bitfield assignment with everything constant. If 2767 so, this is an IOR of an AND, so split it into that. */ 2768 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT 2769 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))) 2770 <= HOST_BITS_PER_WIDE_INT) 2771 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT 2772 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT 2773 && GET_CODE (SET_SRC (x)) == CONST_INT 2774 && ((INTVAL (XEXP (SET_DEST (x), 1)) 2775 + INTVAL (XEXP (SET_DEST (x), 2))) 2776 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))) 2777 && ! side_effects_p (XEXP (SET_DEST (x), 0))) 2778 { 2779 int pos = INTVAL (XEXP (SET_DEST (x), 2)); 2780 int len = INTVAL (XEXP (SET_DEST (x), 1)); 2781 int src = INTVAL (SET_SRC (x)); 2782 rtx dest = XEXP (SET_DEST (x), 0); 2783 enum machine_mode mode = GET_MODE (dest); 2784 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1; 2785 2786 if (BITS_BIG_ENDIAN) 2787 pos = GET_MODE_BITSIZE (mode) - len - pos; 2788 2789 if ((unsigned HOST_WIDE_INT) src == mask) 2790 SUBST (SET_SRC (x), 2791 gen_binary (IOR, mode, dest, GEN_INT (src << pos))); 2792 else 2793 SUBST (SET_SRC (x), 2794 gen_binary (IOR, mode, 2795 gen_binary (AND, mode, dest, 2796 GEN_INT (~ (mask << pos) 2797 & GET_MODE_MASK (mode))), 2798 GEN_INT (src << pos))); 2799 2800 SUBST (SET_DEST (x), dest); 2801 2802 split = find_split_point (&SET_SRC (x), insn); 2803 if (split && split != &SET_SRC (x)) 2804 return split; 2805 } 2806 2807 /* Otherwise, see if this is an operation that we can split into two. 2808 If so, try to split that. */ 2809 code = GET_CODE (SET_SRC (x)); 2810 2811 switch (code) 2812 { 2813 case AND: 2814 /* If we are AND'ing with a large constant that is only a single 2815 bit and the result is only being used in a context where we 2816 need to know if it is zero or non-zero, replace it with a bit 2817 extraction. This will avoid the large constant, which might 2818 have taken more than one insn to make. If the constant were 2819 not a valid argument to the AND but took only one insn to make, 2820 this is no worse, but if it took more than one insn, it will 2821 be better. */ 2822 2823 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT 2824 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG 2825 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7 2826 && GET_CODE (SET_DEST (x)) == REG 2827 && (split = find_single_use (SET_DEST (x), insn, NULL_PTR)) != 0 2828 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE) 2829 && XEXP (*split, 0) == SET_DEST (x) 2830 && XEXP (*split, 1) == const0_rtx) 2831 { 2832 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)), 2833 XEXP (SET_SRC (x), 0), 2834 pos, NULL_RTX, 1, 1, 0, 0); 2835 if (extraction != 0) 2836 { 2837 SUBST (SET_SRC (x), extraction); 2838 return find_split_point (loc, insn); 2839 } 2840 } 2841 break; 2842 2843 case NE: 2844 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X 2845 is known to be on, this can be converted into a NEG of a shift. */ 2846 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx 2847 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0)) 2848 && 1 <= (pos = exact_log2 2849 (nonzero_bits (XEXP (SET_SRC (x), 0), 2850 GET_MODE (XEXP (SET_SRC (x), 0)))))) 2851 { 2852 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0)); 2853 2854 SUBST (SET_SRC (x), 2855 gen_rtx_combine (NEG, mode, 2856 gen_rtx_combine (LSHIFTRT, mode, 2857 XEXP (SET_SRC (x), 0), 2858 GEN_INT (pos)))); 2859 2860 split = find_split_point (&SET_SRC (x), insn); 2861 if (split && split != &SET_SRC (x)) 2862 return split; 2863 } 2864 break; 2865 2866 case SIGN_EXTEND: 2867 inner = XEXP (SET_SRC (x), 0); 2868 2869 /* We can't optimize if either mode is a partial integer 2870 mode as we don't know how many bits are significant 2871 in those modes. */ 2872 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT 2873 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT) 2874 break; 2875 2876 pos = 0; 2877 len = GET_MODE_BITSIZE (GET_MODE (inner)); 2878 unsignedp = 0; 2879 break; 2880 2881 case SIGN_EXTRACT: 2882 case ZERO_EXTRACT: 2883 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT 2884 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT) 2885 { 2886 inner = XEXP (SET_SRC (x), 0); 2887 len = INTVAL (XEXP (SET_SRC (x), 1)); 2888 pos = INTVAL (XEXP (SET_SRC (x), 2)); 2889 2890 if (BITS_BIG_ENDIAN) 2891 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos; 2892 unsignedp = (code == ZERO_EXTRACT); 2893 } 2894 break; 2895 2896 default: 2897 break; 2898 } 2899 2900 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner))) 2901 { 2902 enum machine_mode mode = GET_MODE (SET_SRC (x)); 2903 2904 /* For unsigned, we have a choice of a shift followed by an 2905 AND or two shifts. Use two shifts for field sizes where the 2906 constant might be too large. We assume here that we can 2907 always at least get 8-bit constants in an AND insn, which is 2908 true for every current RISC. */ 2909 2910 if (unsignedp && len <= 8) 2911 { 2912 SUBST (SET_SRC (x), 2913 gen_rtx_combine 2914 (AND, mode, 2915 gen_rtx_combine (LSHIFTRT, mode, 2916 gen_lowpart_for_combine (mode, inner), 2917 GEN_INT (pos)), 2918 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1))); 2919 2920 split = find_split_point (&SET_SRC (x), insn); 2921 if (split && split != &SET_SRC (x)) 2922 return split; 2923 } 2924 else 2925 { 2926 SUBST (SET_SRC (x), 2927 gen_rtx_combine 2928 (unsignedp ? LSHIFTRT : ASHIFTRT, mode, 2929 gen_rtx_combine (ASHIFT, mode, 2930 gen_lowpart_for_combine (mode, inner), 2931 GEN_INT (GET_MODE_BITSIZE (mode) 2932 - len - pos)), 2933 GEN_INT (GET_MODE_BITSIZE (mode) - len))); 2934 2935 split = find_split_point (&SET_SRC (x), insn); 2936 if (split && split != &SET_SRC (x)) 2937 return split; 2938 } 2939 } 2940 2941 /* See if this is a simple operation with a constant as the second 2942 operand. It might be that this constant is out of range and hence 2943 could be used as a split point. */ 2944 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2' 2945 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c' 2946 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<') 2947 && CONSTANT_P (XEXP (SET_SRC (x), 1)) 2948 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o' 2949 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG 2950 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0)))) 2951 == 'o')))) 2952 return &XEXP (SET_SRC (x), 1); 2953 2954 /* Finally, see if this is a simple operation with its first operand 2955 not in a register. The operation might require this operand in a 2956 register, so return it as a split point. We can always do this 2957 because if the first operand were another operation, we would have 2958 already found it as a split point. */ 2959 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2' 2960 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c' 2961 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<' 2962 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1') 2963 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode)) 2964 return &XEXP (SET_SRC (x), 0); 2965 2966 return 0; 2967 2968 case AND: 2969 case IOR: 2970 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR, 2971 it is better to write this as (not (ior A B)) so we can split it. 2972 Similarly for IOR. */ 2973 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT) 2974 { 2975 SUBST (*loc, 2976 gen_rtx_combine (NOT, GET_MODE (x), 2977 gen_rtx_combine (code == IOR ? AND : IOR, 2978 GET_MODE (x), 2979 XEXP (XEXP (x, 0), 0), 2980 XEXP (XEXP (x, 1), 0)))); 2981 return find_split_point (loc, insn); 2982 } 2983 2984 /* Many RISC machines have a large set of logical insns. If the 2985 second operand is a NOT, put it first so we will try to split the 2986 other operand first. */ 2987 if (GET_CODE (XEXP (x, 1)) == NOT) 2988 { 2989 rtx tem = XEXP (x, 0); 2990 SUBST (XEXP (x, 0), XEXP (x, 1)); 2991 SUBST (XEXP (x, 1), tem); 2992 } 2993 break; 2994 2995 default: 2996 break; 2997 } 2998 2999 /* Otherwise, select our actions depending on our rtx class. */ 3000 switch (GET_RTX_CLASS (code)) 3001 { 3002 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */ 3003 case '3': 3004 split = find_split_point (&XEXP (x, 2), insn); 3005 if (split) 3006 return split; 3007 /* ... fall through ... */ 3008 case '2': 3009 case 'c': 3010 case '<': 3011 split = find_split_point (&XEXP (x, 1), insn); 3012 if (split) 3013 return split; 3014 /* ... fall through ... */ 3015 case '1': 3016 /* Some machines have (and (shift ...) ...) insns. If X is not 3017 an AND, but XEXP (X, 0) is, use it as our split point. */ 3018 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND) 3019 return &XEXP (x, 0); 3020 3021 split = find_split_point (&XEXP (x, 0), insn); 3022 if (split) 3023 return split; 3024 return loc; 3025 } 3026 3027 /* Otherwise, we don't have a split point. */ 3028 return 0; 3029} 3030 3031/* Throughout X, replace FROM with TO, and return the result. 3032 The result is TO if X is FROM; 3033 otherwise the result is X, but its contents may have been modified. 3034 If they were modified, a record was made in undobuf so that 3035 undo_all will (among other things) return X to its original state. 3036 3037 If the number of changes necessary is too much to record to undo, 3038 the excess changes are not made, so the result is invalid. 3039 The changes already made can still be undone. 3040 undobuf.num_undo is incremented for such changes, so by testing that 3041 the caller can tell whether the result is valid. 3042 3043 `n_occurrences' is incremented each time FROM is replaced. 3044 3045 IN_DEST is non-zero if we are processing the SET_DEST of a SET. 3046 3047 UNIQUE_COPY is non-zero if each substitution must be unique. We do this 3048 by copying if `n_occurrences' is non-zero. */ 3049 3050static rtx 3051subst (x, from, to, in_dest, unique_copy) 3052 register rtx x, from, to; 3053 int in_dest; 3054 int unique_copy; 3055{ 3056 register enum rtx_code code = GET_CODE (x); 3057 enum machine_mode op0_mode = VOIDmode; 3058 register char *fmt; 3059 register int len, i; 3060 rtx new; 3061 3062/* Two expressions are equal if they are identical copies of a shared 3063 RTX or if they are both registers with the same register number 3064 and mode. */ 3065 3066#define COMBINE_RTX_EQUAL_P(X,Y) \ 3067 ((X) == (Y) \ 3068 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \ 3069 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y))) 3070 3071 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from)) 3072 { 3073 n_occurrences++; 3074 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to); 3075 } 3076 3077 /* If X and FROM are the same register but different modes, they will 3078 not have been seen as equal above. However, flow.c will make a 3079 LOG_LINKS entry for that case. If we do nothing, we will try to 3080 rerecognize our original insn and, when it succeeds, we will 3081 delete the feeding insn, which is incorrect. 3082 3083 So force this insn not to match in this (rare) case. */ 3084 if (! in_dest && code == REG && GET_CODE (from) == REG 3085 && REGNO (x) == REGNO (from)) 3086 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); 3087 3088 /* If this is an object, we are done unless it is a MEM or LO_SUM, both 3089 of which may contain things that can be combined. */ 3090 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o') 3091 return x; 3092 3093 /* It is possible to have a subexpression appear twice in the insn. 3094 Suppose that FROM is a register that appears within TO. 3095 Then, after that subexpression has been scanned once by `subst', 3096 the second time it is scanned, TO may be found. If we were 3097 to scan TO here, we would find FROM within it and create a 3098 self-referent rtl structure which is completely wrong. */ 3099 if (COMBINE_RTX_EQUAL_P (x, to)) 3100 return to; 3101 3102 /* Parallel asm_operands need special attention because all of the 3103 inputs are shared across the arms. Furthermore, unsharing the 3104 rtl results in recognition failures. Failure to handle this case 3105 specially can result in circular rtl. 3106 3107 Solve this by doing a normal pass across the first entry of the 3108 parallel, and only processing the SET_DESTs of the subsequent 3109 entries. Ug. */ 3110 3111 if (code == PARALLEL 3112 && GET_CODE (XVECEXP (x, 0, 0)) == SET 3113 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS) 3114 { 3115 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy); 3116 3117 /* If this substitution failed, this whole thing fails. */ 3118 if (GET_CODE (new) == CLOBBER 3119 && XEXP (new, 0) == const0_rtx) 3120 return new; 3121 3122 SUBST (XVECEXP (x, 0, 0), new); 3123 3124 for (i = XVECLEN (x, 0) - 1; i >= 1; i--) 3125 { 3126 rtx dest = SET_DEST (XVECEXP (x, 0, i)); 3127 3128 if (GET_CODE (dest) != REG 3129 && GET_CODE (dest) != CC0 3130 && GET_CODE (dest) != PC) 3131 { 3132 new = subst (dest, from, to, 0, unique_copy); 3133 3134 /* If this substitution failed, this whole thing fails. */ 3135 if (GET_CODE (new) == CLOBBER 3136 && XEXP (new, 0) == const0_rtx) 3137 return new; 3138 3139 SUBST (SET_DEST (XVECEXP (x, 0, i)), new); 3140 } 3141 } 3142 } 3143 else 3144 { 3145 len = GET_RTX_LENGTH (code); 3146 fmt = GET_RTX_FORMAT (code); 3147 3148 /* We don't need to process a SET_DEST that is a register, CC0, 3149 or PC, so set up to skip this common case. All other cases 3150 where we want to suppress replacing something inside a 3151 SET_SRC are handled via the IN_DEST operand. */ 3152 if (code == SET 3153 && (GET_CODE (SET_DEST (x)) == REG 3154 || GET_CODE (SET_DEST (x)) == CC0 3155 || GET_CODE (SET_DEST (x)) == PC)) 3156 fmt = "ie"; 3157 3158 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a 3159 constant. */ 3160 if (fmt[0] == 'e') 3161 op0_mode = GET_MODE (XEXP (x, 0)); 3162 3163 for (i = 0; i < len; i++) 3164 { 3165 if (fmt[i] == 'E') 3166 { 3167 register int j; 3168 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 3169 { 3170 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from)) 3171 { 3172 new = (unique_copy && n_occurrences 3173 ? copy_rtx (to) : to); 3174 n_occurrences++; 3175 } 3176 else 3177 { 3178 new = subst (XVECEXP (x, i, j), from, to, 0, 3179 unique_copy); 3180 3181 /* If this substitution failed, this whole thing 3182 fails. */ 3183 if (GET_CODE (new) == CLOBBER 3184 && XEXP (new, 0) == const0_rtx) 3185 return new; 3186 } 3187 3188 SUBST (XVECEXP (x, i, j), new); 3189 } 3190 } 3191 else if (fmt[i] == 'e') 3192 { 3193 if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from)) 3194 { 3195 /* In general, don't install a subreg involving two 3196 modes not tieable. It can worsen register 3197 allocation, and can even make invalid reload 3198 insns, since the reg inside may need to be copied 3199 from in the outside mode, and that may be invalid 3200 if it is an fp reg copied in integer mode. 3201 3202 We allow two exceptions to this: It is valid if 3203 it is inside another SUBREG and the mode of that 3204 SUBREG and the mode of the inside of TO is 3205 tieable and it is valid if X is a SET that copies 3206 FROM to CC0. */ 3207 3208 if (GET_CODE (to) == SUBREG 3209 && ! MODES_TIEABLE_P (GET_MODE (to), 3210 GET_MODE (SUBREG_REG (to))) 3211 && ! (code == SUBREG 3212 && MODES_TIEABLE_P (GET_MODE (x), 3213 GET_MODE (SUBREG_REG (to)))) 3214#ifdef HAVE_cc0 3215 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx) 3216#endif 3217 ) 3218 return gen_rtx_CLOBBER (VOIDmode, const0_rtx); 3219 3220 new = (unique_copy && n_occurrences ? copy_rtx (to) : to); 3221 n_occurrences++; 3222 } 3223 else 3224 /* If we are in a SET_DEST, suppress most cases unless we 3225 have gone inside a MEM, in which case we want to 3226 simplify the address. We assume here that things that 3227 are actually part of the destination have their inner 3228 parts in the first expression. This is true for SUBREG, 3229 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only 3230 things aside from REG and MEM that should appear in a 3231 SET_DEST. */ 3232 new = subst (XEXP (x, i), from, to, 3233 (((in_dest 3234 && (code == SUBREG || code == STRICT_LOW_PART 3235 || code == ZERO_EXTRACT)) 3236 || code == SET) 3237 && i == 0), unique_copy); 3238 3239 /* If we found that we will have to reject this combination, 3240 indicate that by returning the CLOBBER ourselves, rather than 3241 an expression containing it. This will speed things up as 3242 well as prevent accidents where two CLOBBERs are considered 3243 to be equal, thus producing an incorrect simplification. */ 3244 3245 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx) 3246 return new; 3247 3248 SUBST (XEXP (x, i), new); 3249 } 3250 } 3251 } 3252 3253 /* Try to simplify X. If the simplification changed the code, it is likely 3254 that further simplification will help, so loop, but limit the number 3255 of repetitions that will be performed. */ 3256 3257 for (i = 0; i < 4; i++) 3258 { 3259 /* If X is sufficiently simple, don't bother trying to do anything 3260 with it. */ 3261 if (code != CONST_INT && code != REG && code != CLOBBER) 3262 x = simplify_rtx (x, op0_mode, i == 3, in_dest); 3263 3264 if (GET_CODE (x) == code) 3265 break; 3266 3267 code = GET_CODE (x); 3268 3269 /* We no longer know the original mode of operand 0 since we 3270 have changed the form of X) */ 3271 op0_mode = VOIDmode; 3272 } 3273 3274 return x; 3275} 3276 3277/* Simplify X, a piece of RTL. We just operate on the expression at the 3278 outer level; call `subst' to simplify recursively. Return the new 3279 expression. 3280 3281 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this 3282 will be the iteration even if an expression with a code different from 3283 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */ 3284 3285static rtx 3286simplify_rtx (x, op0_mode, last, in_dest) 3287 rtx x; 3288 enum machine_mode op0_mode; 3289 int last; 3290 int in_dest; 3291{ 3292 enum rtx_code code = GET_CODE (x); 3293 enum machine_mode mode = GET_MODE (x); 3294 rtx temp; 3295 int i; 3296 3297 /* If this is a commutative operation, put a constant last and a complex 3298 expression first. We don't need to do this for comparisons here. */ 3299 if (GET_RTX_CLASS (code) == 'c' 3300 && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT) 3301 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o' 3302 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o') 3303 || (GET_CODE (XEXP (x, 0)) == SUBREG 3304 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o' 3305 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'))) 3306 { 3307 temp = XEXP (x, 0); 3308 SUBST (XEXP (x, 0), XEXP (x, 1)); 3309 SUBST (XEXP (x, 1), temp); 3310 } 3311 3312 /* If this is a PLUS, MINUS, or MULT, and the first operand is the 3313 sign extension of a PLUS with a constant, reverse the order of the sign 3314 extension and the addition. Note that this not the same as the original 3315 code, but overflow is undefined for signed values. Also note that the 3316 PLUS will have been partially moved "inside" the sign-extension, so that 3317 the first operand of X will really look like: 3318 (ashiftrt (plus (ashift A C4) C5) C4). 3319 We convert this to 3320 (plus (ashiftrt (ashift A C4) C2) C4) 3321 and replace the first operand of X with that expression. Later parts 3322 of this function may simplify the expression further. 3323 3324 For example, if we start with (mult (sign_extend (plus A C1)) C2), 3325 we swap the SIGN_EXTEND and PLUS. Later code will apply the 3326 distributive law to produce (plus (mult (sign_extend X) C1) C3). 3327 3328 We do this to simplify address expressions. */ 3329 3330 if ((code == PLUS || code == MINUS || code == MULT) 3331 && GET_CODE (XEXP (x, 0)) == ASHIFTRT 3332 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS 3333 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT 3334 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT 3335 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 3336 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1) 3337 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT 3338 && (temp = simplify_binary_operation (ASHIFTRT, mode, 3339 XEXP (XEXP (XEXP (x, 0), 0), 1), 3340 XEXP (XEXP (x, 0), 1))) != 0) 3341 { 3342 rtx new 3343 = simplify_shift_const (NULL_RTX, ASHIFT, mode, 3344 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0), 3345 INTVAL (XEXP (XEXP (x, 0), 1))); 3346 3347 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new, 3348 INTVAL (XEXP (XEXP (x, 0), 1))); 3349 3350 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp)); 3351 } 3352 3353 /* If this is a simple operation applied to an IF_THEN_ELSE, try 3354 applying it to the arms of the IF_THEN_ELSE. This often simplifies 3355 things. Check for cases where both arms are testing the same 3356 condition. 3357 3358 Don't do anything if all operands are very simple. */ 3359 3360 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c' 3361 || GET_RTX_CLASS (code) == '<') 3362 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o' 3363 && ! (GET_CODE (XEXP (x, 0)) == SUBREG 3364 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) 3365 == 'o'))) 3366 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o' 3367 && ! (GET_CODE (XEXP (x, 1)) == SUBREG 3368 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1)))) 3369 == 'o'))))) 3370 || (GET_RTX_CLASS (code) == '1' 3371 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o' 3372 && ! (GET_CODE (XEXP (x, 0)) == SUBREG 3373 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) 3374 == 'o')))))) 3375 { 3376 rtx cond, true, false; 3377 3378 cond = if_then_else_cond (x, &true, &false); 3379 if (cond != 0 3380 /* If everything is a comparison, what we have is highly unlikely 3381 to be simpler, so don't use it. */ 3382 && ! (GET_RTX_CLASS (code) == '<' 3383 && (GET_RTX_CLASS (GET_CODE (true)) == '<' 3384 || GET_RTX_CLASS (GET_CODE (false)) == '<'))) 3385 { 3386 rtx cop1 = const0_rtx; 3387 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1); 3388 3389 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<') 3390 return x; 3391 3392 /* Simplify the alternative arms; this may collapse the true and 3393 false arms to store-flag values. */ 3394 true = subst (true, pc_rtx, pc_rtx, 0, 0); 3395 false = subst (false, pc_rtx, pc_rtx, 0, 0); 3396 3397 /* Restarting if we generate a store-flag expression will cause 3398 us to loop. Just drop through in this case. */ 3399 3400 /* If the result values are STORE_FLAG_VALUE and zero, we can 3401 just make the comparison operation. */ 3402 if (true == const_true_rtx && false == const0_rtx) 3403 x = gen_binary (cond_code, mode, cond, cop1); 3404 else if (true == const0_rtx && false == const_true_rtx) 3405 x = gen_binary (reverse_condition (cond_code), mode, cond, cop1); 3406 3407 /* Likewise, we can make the negate of a comparison operation 3408 if the result values are - STORE_FLAG_VALUE and zero. */ 3409 else if (GET_CODE (true) == CONST_INT 3410 && INTVAL (true) == - STORE_FLAG_VALUE 3411 && false == const0_rtx) 3412 x = gen_unary (NEG, mode, mode, 3413 gen_binary (cond_code, mode, cond, cop1)); 3414 else if (GET_CODE (false) == CONST_INT 3415 && INTVAL (false) == - STORE_FLAG_VALUE 3416 && true == const0_rtx) 3417 x = gen_unary (NEG, mode, mode, 3418 gen_binary (reverse_condition (cond_code), 3419 mode, cond, cop1)); 3420 else 3421 return gen_rtx_IF_THEN_ELSE (mode, 3422 gen_binary (cond_code, VOIDmode, 3423 cond, cop1), 3424 true, false); 3425 3426 code = GET_CODE (x); 3427 op0_mode = VOIDmode; 3428 } 3429 } 3430 3431 /* Try to fold this expression in case we have constants that weren't 3432 present before. */ 3433 temp = 0; 3434 switch (GET_RTX_CLASS (code)) 3435 { 3436 case '1': 3437 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode); 3438 break; 3439 case '<': 3440 temp = simplify_relational_operation (code, op0_mode, 3441 XEXP (x, 0), XEXP (x, 1)); 3442#ifdef FLOAT_STORE_FLAG_VALUE 3443 if (temp != 0 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) 3444 temp = ((temp == const0_rtx) ? CONST0_RTX (GET_MODE (x)) 3445 : immed_real_const_1 (FLOAT_STORE_FLAG_VALUE, GET_MODE (x))); 3446#endif 3447 break; 3448 case 'c': 3449 case '2': 3450 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1)); 3451 break; 3452 case 'b': 3453 case '3': 3454 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0), 3455 XEXP (x, 1), XEXP (x, 2)); 3456 break; 3457 } 3458 3459 if (temp) 3460 x = temp, code = GET_CODE (temp); 3461 3462 /* First see if we can apply the inverse distributive law. */ 3463 if (code == PLUS || code == MINUS 3464 || code == AND || code == IOR || code == XOR) 3465 { 3466 x = apply_distributive_law (x); 3467 code = GET_CODE (x); 3468 } 3469 3470 /* If CODE is an associative operation not otherwise handled, see if we 3471 can associate some operands. This can win if they are constants or 3472 if they are logically related (i.e. (a & b) & a. */ 3473 if ((code == PLUS || code == MINUS 3474 || code == MULT || code == AND || code == IOR || code == XOR 3475 || code == DIV || code == UDIV 3476 || code == SMAX || code == SMIN || code == UMAX || code == UMIN) 3477 && INTEGRAL_MODE_P (mode)) 3478 { 3479 if (GET_CODE (XEXP (x, 0)) == code) 3480 { 3481 rtx other = XEXP (XEXP (x, 0), 0); 3482 rtx inner_op0 = XEXP (XEXP (x, 0), 1); 3483 rtx inner_op1 = XEXP (x, 1); 3484 rtx inner; 3485 3486 /* Make sure we pass the constant operand if any as the second 3487 one if this is a commutative operation. */ 3488 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c') 3489 { 3490 rtx tem = inner_op0; 3491 inner_op0 = inner_op1; 3492 inner_op1 = tem; 3493 } 3494 inner = simplify_binary_operation (code == MINUS ? PLUS 3495 : code == DIV ? MULT 3496 : code == UDIV ? MULT 3497 : code, 3498 mode, inner_op0, inner_op1); 3499 3500 /* For commutative operations, try the other pair if that one 3501 didn't simplify. */ 3502 if (inner == 0 && GET_RTX_CLASS (code) == 'c') 3503 { 3504 other = XEXP (XEXP (x, 0), 1); 3505 inner = simplify_binary_operation (code, mode, 3506 XEXP (XEXP (x, 0), 0), 3507 XEXP (x, 1)); 3508 } 3509 3510 if (inner) 3511 return gen_binary (code, mode, other, inner); 3512 } 3513 } 3514 3515 /* A little bit of algebraic simplification here. */ 3516 switch (code) 3517 { 3518 case MEM: 3519 /* Ensure that our address has any ASHIFTs converted to MULT in case 3520 address-recognizing predicates are called later. */ 3521 temp = make_compound_operation (XEXP (x, 0), MEM); 3522 SUBST (XEXP (x, 0), temp); 3523 break; 3524 3525 case SUBREG: 3526 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG 3527 is paradoxical. If we can't do that safely, then it becomes 3528 something nonsensical so that this combination won't take place. */ 3529 3530 if (GET_CODE (SUBREG_REG (x)) == MEM 3531 && (GET_MODE_SIZE (mode) 3532 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))) 3533 { 3534 rtx inner = SUBREG_REG (x); 3535 int endian_offset = 0; 3536 /* Don't change the mode of the MEM 3537 if that would change the meaning of the address. */ 3538 if (MEM_VOLATILE_P (SUBREG_REG (x)) 3539 || mode_dependent_address_p (XEXP (inner, 0))) 3540 return gen_rtx_CLOBBER (mode, const0_rtx); 3541 3542 if (BYTES_BIG_ENDIAN) 3543 { 3544 if (GET_MODE_SIZE (mode) < UNITS_PER_WORD) 3545 endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode); 3546 if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD) 3547 endian_offset -= (UNITS_PER_WORD 3548 - GET_MODE_SIZE (GET_MODE (inner))); 3549 } 3550 /* Note if the plus_constant doesn't make a valid address 3551 then this combination won't be accepted. */ 3552 x = gen_rtx_MEM (mode, 3553 plus_constant (XEXP (inner, 0), 3554 (SUBREG_WORD (x) * UNITS_PER_WORD 3555 + endian_offset))); 3556 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (inner); 3557 MEM_COPY_ATTRIBUTES (x, inner); 3558 return x; 3559 } 3560 3561 /* If we are in a SET_DEST, these other cases can't apply. */ 3562 if (in_dest) 3563 return x; 3564 3565 /* Changing mode twice with SUBREG => just change it once, 3566 or not at all if changing back to starting mode. */ 3567 if (GET_CODE (SUBREG_REG (x)) == SUBREG) 3568 { 3569 if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x))) 3570 && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0) 3571 return SUBREG_REG (SUBREG_REG (x)); 3572 3573 SUBST_INT (SUBREG_WORD (x), 3574 SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x))); 3575 SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x))); 3576 } 3577 3578 /* SUBREG of a hard register => just change the register number 3579 and/or mode. If the hard register is not valid in that mode, 3580 suppress this combination. If the hard register is the stack, 3581 frame, or argument pointer, leave this as a SUBREG. */ 3582 3583 if (GET_CODE (SUBREG_REG (x)) == REG 3584 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER 3585 && REGNO (SUBREG_REG (x)) != FRAME_POINTER_REGNUM 3586#if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM 3587 && REGNO (SUBREG_REG (x)) != HARD_FRAME_POINTER_REGNUM 3588#endif 3589#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM 3590 && REGNO (SUBREG_REG (x)) != ARG_POINTER_REGNUM 3591#endif 3592 && REGNO (SUBREG_REG (x)) != STACK_POINTER_REGNUM) 3593 { 3594 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x), 3595 mode)) 3596 return gen_rtx_REG (mode, 3597 REGNO (SUBREG_REG (x)) + SUBREG_WORD (x)); 3598 else 3599 return gen_rtx_CLOBBER (mode, const0_rtx); 3600 } 3601 3602 /* For a constant, try to pick up the part we want. Handle a full 3603 word and low-order part. Only do this if we are narrowing 3604 the constant; if it is being widened, we have no idea what 3605 the extra bits will have been set to. */ 3606 3607 if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode 3608 && GET_MODE_SIZE (mode) == UNITS_PER_WORD 3609 && GET_MODE_SIZE (op0_mode) > UNITS_PER_WORD 3610 && GET_MODE_CLASS (mode) == MODE_INT) 3611 { 3612 temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x), 3613 0, op0_mode); 3614 if (temp) 3615 return temp; 3616 } 3617 3618 /* If we want a subreg of a constant, at offset 0, 3619 take the low bits. On a little-endian machine, that's 3620 always valid. On a big-endian machine, it's valid 3621 only if the constant's mode fits in one word. Note that we 3622 cannot use subreg_lowpart_p since SUBREG_REG may be VOIDmode. */ 3623 if (CONSTANT_P (SUBREG_REG (x)) 3624 && ((GET_MODE_SIZE (op0_mode) <= UNITS_PER_WORD 3625 || ! WORDS_BIG_ENDIAN) 3626 ? SUBREG_WORD (x) == 0 3627 : (SUBREG_WORD (x) 3628 == ((GET_MODE_SIZE (op0_mode) 3629 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD)) 3630 / UNITS_PER_WORD))) 3631 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (op0_mode) 3632 && (! WORDS_BIG_ENDIAN 3633 || GET_MODE_BITSIZE (op0_mode) <= BITS_PER_WORD)) 3634 return gen_lowpart_for_combine (mode, SUBREG_REG (x)); 3635 3636 /* A paradoxical SUBREG of a VOIDmode constant is the same constant, 3637 since we are saying that the high bits don't matter. */ 3638 if (CONSTANT_P (SUBREG_REG (x)) && GET_MODE (SUBREG_REG (x)) == VOIDmode 3639 && GET_MODE_SIZE (mode) > GET_MODE_SIZE (op0_mode)) 3640 return SUBREG_REG (x); 3641 3642 /* Note that we cannot do any narrowing for non-constants since 3643 we might have been counting on using the fact that some bits were 3644 zero. We now do this in the SET. */ 3645 3646 break; 3647 3648 case NOT: 3649 /* (not (plus X -1)) can become (neg X). */ 3650 if (GET_CODE (XEXP (x, 0)) == PLUS 3651 && XEXP (XEXP (x, 0), 1) == constm1_rtx) 3652 return gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0)); 3653 3654 /* Similarly, (not (neg X)) is (plus X -1). */ 3655 if (GET_CODE (XEXP (x, 0)) == NEG) 3656 return gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0), 3657 constm1_rtx); 3658 3659 /* (not (xor X C)) for C constant is (xor X D) with D = ~ C. */ 3660 if (GET_CODE (XEXP (x, 0)) == XOR 3661 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 3662 && (temp = simplify_unary_operation (NOT, mode, 3663 XEXP (XEXP (x, 0), 1), 3664 mode)) != 0) 3665 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp); 3666 3667 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands 3668 other than 1, but that is not valid. We could do a similar 3669 simplification for (not (lshiftrt C X)) where C is just the sign bit, 3670 but this doesn't seem common enough to bother with. */ 3671 if (GET_CODE (XEXP (x, 0)) == ASHIFT 3672 && XEXP (XEXP (x, 0), 0) == const1_rtx) 3673 return gen_rtx_ROTATE (mode, gen_unary (NOT, mode, mode, const1_rtx), 3674 XEXP (XEXP (x, 0), 1)); 3675 3676 if (GET_CODE (XEXP (x, 0)) == SUBREG 3677 && subreg_lowpart_p (XEXP (x, 0)) 3678 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) 3679 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0))))) 3680 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT 3681 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx) 3682 { 3683 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0))); 3684 3685 x = gen_rtx_ROTATE (inner_mode, 3686 gen_unary (NOT, inner_mode, inner_mode, 3687 const1_rtx), 3688 XEXP (SUBREG_REG (XEXP (x, 0)), 1)); 3689 return gen_lowpart_for_combine (mode, x); 3690 } 3691 3692 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by 3693 reversing the comparison code if valid. */ 3694 if (STORE_FLAG_VALUE == -1 3695 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' 3696 && reversible_comparison_p (XEXP (x, 0))) 3697 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))), 3698 mode, XEXP (XEXP (x, 0), 0), 3699 XEXP (XEXP (x, 0), 1)); 3700 3701 /* (ashiftrt foo C) where C is the number of bits in FOO minus 1 3702 is (lt foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can 3703 perform the above simplification. */ 3704 3705 if (STORE_FLAG_VALUE == -1 3706 && XEXP (x, 1) == const1_rtx 3707 && GET_CODE (XEXP (x, 0)) == ASHIFTRT 3708 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 3709 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1) 3710 return gen_rtx_combine (GE, mode, XEXP (XEXP (x, 0), 0), const0_rtx); 3711 3712 /* Apply De Morgan's laws to reduce number of patterns for machines 3713 with negating logical insns (and-not, nand, etc.). If result has 3714 only one NOT, put it first, since that is how the patterns are 3715 coded. */ 3716 3717 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND) 3718 { 3719 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1); 3720 3721 if (GET_CODE (in1) == NOT) 3722 in1 = XEXP (in1, 0); 3723 else 3724 in1 = gen_rtx_combine (NOT, GET_MODE (in1), in1); 3725 3726 if (GET_CODE (in2) == NOT) 3727 in2 = XEXP (in2, 0); 3728 else if (GET_CODE (in2) == CONST_INT 3729 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) 3730 in2 = GEN_INT (GET_MODE_MASK (mode) & ~ INTVAL (in2)); 3731 else 3732 in2 = gen_rtx_combine (NOT, GET_MODE (in2), in2); 3733 3734 if (GET_CODE (in2) == NOT) 3735 { 3736 rtx tem = in2; 3737 in2 = in1; in1 = tem; 3738 } 3739 3740 return gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR, 3741 mode, in1, in2); 3742 } 3743 break; 3744 3745 case NEG: 3746 /* (neg (plus X 1)) can become (not X). */ 3747 if (GET_CODE (XEXP (x, 0)) == PLUS 3748 && XEXP (XEXP (x, 0), 1) == const1_rtx) 3749 return gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0)); 3750 3751 /* Similarly, (neg (not X)) is (plus X 1). */ 3752 if (GET_CODE (XEXP (x, 0)) == NOT) 3753 return plus_constant (XEXP (XEXP (x, 0), 0), 1); 3754 3755 /* (neg (minus X Y)) can become (minus Y X). */ 3756 if (GET_CODE (XEXP (x, 0)) == MINUS 3757 && (! FLOAT_MODE_P (mode) 3758 /* x-y != -(y-x) with IEEE floating point. */ 3759 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT 3760 || flag_fast_math)) 3761 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1), 3762 XEXP (XEXP (x, 0), 0)); 3763 3764 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */ 3765 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx 3766 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1) 3767 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx); 3768 3769 /* NEG commutes with ASHIFT since it is multiplication. Only do this 3770 if we can then eliminate the NEG (e.g., 3771 if the operand is a constant). */ 3772 3773 if (GET_CODE (XEXP (x, 0)) == ASHIFT) 3774 { 3775 temp = simplify_unary_operation (NEG, mode, 3776 XEXP (XEXP (x, 0), 0), mode); 3777 if (temp) 3778 { 3779 SUBST (XEXP (XEXP (x, 0), 0), temp); 3780 return XEXP (x, 0); 3781 } 3782 } 3783 3784 temp = expand_compound_operation (XEXP (x, 0)); 3785 3786 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be 3787 replaced by (lshiftrt X C). This will convert 3788 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */ 3789 3790 if (GET_CODE (temp) == ASHIFTRT 3791 && GET_CODE (XEXP (temp, 1)) == CONST_INT 3792 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1) 3793 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0), 3794 INTVAL (XEXP (temp, 1))); 3795 3796 /* If X has only a single bit that might be nonzero, say, bit I, convert 3797 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of 3798 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to 3799 (sign_extract X 1 Y). But only do this if TEMP isn't a register 3800 or a SUBREG of one since we'd be making the expression more 3801 complex if it was just a register. */ 3802 3803 if (GET_CODE (temp) != REG 3804 && ! (GET_CODE (temp) == SUBREG 3805 && GET_CODE (SUBREG_REG (temp)) == REG) 3806 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0) 3807 { 3808 rtx temp1 = simplify_shift_const 3809 (NULL_RTX, ASHIFTRT, mode, 3810 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp, 3811 GET_MODE_BITSIZE (mode) - 1 - i), 3812 GET_MODE_BITSIZE (mode) - 1 - i); 3813 3814 /* If all we did was surround TEMP with the two shifts, we 3815 haven't improved anything, so don't use it. Otherwise, 3816 we are better off with TEMP1. */ 3817 if (GET_CODE (temp1) != ASHIFTRT 3818 || GET_CODE (XEXP (temp1, 0)) != ASHIFT 3819 || XEXP (XEXP (temp1, 0), 0) != temp) 3820 return temp1; 3821 } 3822 break; 3823 3824 case TRUNCATE: 3825 /* We can't handle truncation to a partial integer mode here 3826 because we don't know the real bitsize of the partial 3827 integer mode. */ 3828 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) 3829 break; 3830 3831 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 3832 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode), 3833 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))) 3834 SUBST (XEXP (x, 0), 3835 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)), 3836 GET_MODE_MASK (mode), NULL_RTX, 0)); 3837 3838 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */ 3839 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND 3840 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND) 3841 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode) 3842 return XEXP (XEXP (x, 0), 0); 3843 3844 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is 3845 (OP:SI foo:SI) if OP is NEG or ABS. */ 3846 if ((GET_CODE (XEXP (x, 0)) == ABS 3847 || GET_CODE (XEXP (x, 0)) == NEG) 3848 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND 3849 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND) 3850 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode) 3851 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode, 3852 XEXP (XEXP (XEXP (x, 0), 0), 0)); 3853 3854 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is 3855 (truncate:SI x). */ 3856 if (GET_CODE (XEXP (x, 0)) == SUBREG 3857 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE 3858 && subreg_lowpart_p (XEXP (x, 0))) 3859 return SUBREG_REG (XEXP (x, 0)); 3860 3861 /* If we know that the value is already truncated, we can 3862 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION is 3863 nonzero for the corresponding modes. */ 3864 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode), 3865 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))) 3866 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))) 3867 >= GET_MODE_BITSIZE (mode) + 1) 3868 return gen_lowpart_for_combine (mode, XEXP (x, 0)); 3869 3870 /* A truncate of a comparison can be replaced with a subreg if 3871 STORE_FLAG_VALUE permits. This is like the previous test, 3872 but it works even if the comparison is done in a mode larger 3873 than HOST_BITS_PER_WIDE_INT. */ 3874 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 3875 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' 3876 && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0) 3877 return gen_lowpart_for_combine (mode, XEXP (x, 0)); 3878 3879 /* Similarly, a truncate of a register whose value is a 3880 comparison can be replaced with a subreg if STORE_FLAG_VALUE 3881 permits. */ 3882 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 3883 && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0 3884 && (temp = get_last_value (XEXP (x, 0))) 3885 && GET_RTX_CLASS (GET_CODE (temp)) == '<') 3886 return gen_lowpart_for_combine (mode, XEXP (x, 0)); 3887 3888 break; 3889 3890 case FLOAT_TRUNCATE: 3891 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */ 3892 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND 3893 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode) 3894 return XEXP (XEXP (x, 0), 0); 3895 3896 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is 3897 (OP:SF foo:SF) if OP is NEG or ABS. */ 3898 if ((GET_CODE (XEXP (x, 0)) == ABS 3899 || GET_CODE (XEXP (x, 0)) == NEG) 3900 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND 3901 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode) 3902 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode, 3903 XEXP (XEXP (XEXP (x, 0), 0), 0)); 3904 3905 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0)) 3906 is (float_truncate:SF x). */ 3907 if (GET_CODE (XEXP (x, 0)) == SUBREG 3908 && subreg_lowpart_p (XEXP (x, 0)) 3909 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE) 3910 return SUBREG_REG (XEXP (x, 0)); 3911 break; 3912 3913#ifdef HAVE_cc0 3914 case COMPARE: 3915 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't 3916 using cc0, in which case we want to leave it as a COMPARE 3917 so we can distinguish it from a register-register-copy. */ 3918 if (XEXP (x, 1) == const0_rtx) 3919 return XEXP (x, 0); 3920 3921 /* In IEEE floating point, x-0 is not the same as x. */ 3922 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT 3923 || ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0))) 3924 || flag_fast_math) 3925 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0)))) 3926 return XEXP (x, 0); 3927 break; 3928#endif 3929 3930 case CONST: 3931 /* (const (const X)) can become (const X). Do it this way rather than 3932 returning the inner CONST since CONST can be shared with a 3933 REG_EQUAL note. */ 3934 if (GET_CODE (XEXP (x, 0)) == CONST) 3935 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); 3936 break; 3937 3938#ifdef HAVE_lo_sum 3939 case LO_SUM: 3940 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we 3941 can add in an offset. find_split_point will split this address up 3942 again if it doesn't match. */ 3943 if (GET_CODE (XEXP (x, 0)) == HIGH 3944 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))) 3945 return XEXP (x, 1); 3946 break; 3947#endif 3948 3949 case PLUS: 3950 /* If we have (plus (plus (A const) B)), associate it so that CONST is 3951 outermost. That's because that's the way indexed addresses are 3952 supposed to appear. This code used to check many more cases, but 3953 they are now checked elsewhere. */ 3954 if (GET_CODE (XEXP (x, 0)) == PLUS 3955 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1))) 3956 return gen_binary (PLUS, mode, 3957 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), 3958 XEXP (x, 1)), 3959 XEXP (XEXP (x, 0), 1)); 3960 3961 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>) 3962 when c is (const_int (pow2 + 1) / 2) is a sign extension of a 3963 bit-field and can be replaced by either a sign_extend or a 3964 sign_extract. The `and' may be a zero_extend. */ 3965 if (GET_CODE (XEXP (x, 0)) == XOR 3966 && GET_CODE (XEXP (x, 1)) == CONST_INT 3967 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 3968 && INTVAL (XEXP (x, 1)) == - INTVAL (XEXP (XEXP (x, 0), 1)) 3969 && (i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0 3970 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 3971 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND 3972 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT 3973 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)) 3974 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1)) 3975 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND 3976 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0))) 3977 == i + 1)))) 3978 return simplify_shift_const 3979 (NULL_RTX, ASHIFTRT, mode, 3980 simplify_shift_const (NULL_RTX, ASHIFT, mode, 3981 XEXP (XEXP (XEXP (x, 0), 0), 0), 3982 GET_MODE_BITSIZE (mode) - (i + 1)), 3983 GET_MODE_BITSIZE (mode) - (i + 1)); 3984 3985 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if 3986 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE 3987 is 1. This produces better code than the alternative immediately 3988 below. */ 3989 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' 3990 && reversible_comparison_p (XEXP (x, 0)) 3991 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx) 3992 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx))) 3993 return 3994 gen_unary (NEG, mode, mode, 3995 gen_binary (reverse_condition (GET_CODE (XEXP (x, 0))), 3996 mode, XEXP (XEXP (x, 0), 0), 3997 XEXP (XEXP (x, 0), 1))); 3998 3999 /* If only the low-order bit of X is possibly nonzero, (plus x -1) 4000 can become (ashiftrt (ashift (xor x 1) C) C) where C is 4001 the bitsize of the mode - 1. This allows simplification of 4002 "a = (b & 8) == 0;" */ 4003 if (XEXP (x, 1) == constm1_rtx 4004 && GET_CODE (XEXP (x, 0)) != REG 4005 && ! (GET_CODE (XEXP (x,0)) == SUBREG 4006 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG) 4007 && nonzero_bits (XEXP (x, 0), mode) == 1) 4008 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode, 4009 simplify_shift_const (NULL_RTX, ASHIFT, mode, 4010 gen_rtx_combine (XOR, mode, 4011 XEXP (x, 0), const1_rtx), 4012 GET_MODE_BITSIZE (mode) - 1), 4013 GET_MODE_BITSIZE (mode) - 1); 4014 4015 /* If we are adding two things that have no bits in common, convert 4016 the addition into an IOR. This will often be further simplified, 4017 for example in cases like ((a & 1) + (a & 2)), which can 4018 become a & 3. */ 4019 4020 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 4021 && (nonzero_bits (XEXP (x, 0), mode) 4022 & nonzero_bits (XEXP (x, 1), mode)) == 0) 4023 return gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1)); 4024 break; 4025 4026 case MINUS: 4027 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done 4028 by reversing the comparison code if valid. */ 4029 if (STORE_FLAG_VALUE == 1 4030 && XEXP (x, 0) == const1_rtx 4031 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<' 4032 && reversible_comparison_p (XEXP (x, 1))) 4033 return gen_binary (reverse_condition (GET_CODE (XEXP (x, 1))), 4034 mode, XEXP (XEXP (x, 1), 0), 4035 XEXP (XEXP (x, 1), 1)); 4036 4037 /* (minus <foo> (and <foo> (const_int -pow2))) becomes 4038 (and <foo> (const_int pow2-1)) */ 4039 if (GET_CODE (XEXP (x, 1)) == AND 4040 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT 4041 && exact_log2 (- INTVAL (XEXP (XEXP (x, 1), 1))) >= 0 4042 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0))) 4043 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0), 4044 - INTVAL (XEXP (XEXP (x, 1), 1)) - 1); 4045 4046 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for 4047 integers. */ 4048 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode)) 4049 return gen_binary (MINUS, mode, 4050 gen_binary (MINUS, mode, XEXP (x, 0), 4051 XEXP (XEXP (x, 1), 0)), 4052 XEXP (XEXP (x, 1), 1)); 4053 break; 4054 4055 case MULT: 4056 /* If we have (mult (plus A B) C), apply the distributive law and then 4057 the inverse distributive law to see if things simplify. This 4058 occurs mostly in addresses, often when unrolling loops. */ 4059 4060 if (GET_CODE (XEXP (x, 0)) == PLUS) 4061 { 4062 x = apply_distributive_law 4063 (gen_binary (PLUS, mode, 4064 gen_binary (MULT, mode, 4065 XEXP (XEXP (x, 0), 0), XEXP (x, 1)), 4066 gen_binary (MULT, mode, 4067 XEXP (XEXP (x, 0), 1), 4068 copy_rtx (XEXP (x, 1))))); 4069 4070 if (GET_CODE (x) != MULT) 4071 return x; 4072 } 4073 break; 4074 4075 case UDIV: 4076 /* If this is a divide by a power of two, treat it as a shift if 4077 its first operand is a shift. */ 4078 if (GET_CODE (XEXP (x, 1)) == CONST_INT 4079 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0 4080 && (GET_CODE (XEXP (x, 0)) == ASHIFT 4081 || GET_CODE (XEXP (x, 0)) == LSHIFTRT 4082 || GET_CODE (XEXP (x, 0)) == ASHIFTRT 4083 || GET_CODE (XEXP (x, 0)) == ROTATE 4084 || GET_CODE (XEXP (x, 0)) == ROTATERT)) 4085 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i); 4086 break; 4087 4088 case EQ: case NE: 4089 case GT: case GTU: case GE: case GEU: 4090 case LT: case LTU: case LE: case LEU: 4091 /* If the first operand is a condition code, we can't do anything 4092 with it. */ 4093 if (GET_CODE (XEXP (x, 0)) == COMPARE 4094 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC 4095#ifdef HAVE_cc0 4096 && XEXP (x, 0) != cc0_rtx 4097#endif 4098 )) 4099 { 4100 rtx op0 = XEXP (x, 0); 4101 rtx op1 = XEXP (x, 1); 4102 enum rtx_code new_code; 4103 4104 if (GET_CODE (op0) == COMPARE) 4105 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0); 4106 4107 /* Simplify our comparison, if possible. */ 4108 new_code = simplify_comparison (code, &op0, &op1); 4109 4110 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X 4111 if only the low-order bit is possibly nonzero in X (such as when 4112 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to 4113 (xor X 1) or (minus 1 X); we use the former. Finally, if X is 4114 known to be either 0 or -1, NE becomes a NEG and EQ becomes 4115 (plus X 1). 4116 4117 Remove any ZERO_EXTRACT we made when thinking this was a 4118 comparison. It may now be simpler to use, e.g., an AND. If a 4119 ZERO_EXTRACT is indeed appropriate, it will be placed back by 4120 the call to make_compound_operation in the SET case. */ 4121 4122 if (STORE_FLAG_VALUE == 1 4123 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT 4124 && op1 == const0_rtx && nonzero_bits (op0, mode) == 1) 4125 return gen_lowpart_for_combine (mode, 4126 expand_compound_operation (op0)); 4127 4128 else if (STORE_FLAG_VALUE == 1 4129 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT 4130 && op1 == const0_rtx 4131 && (num_sign_bit_copies (op0, mode) 4132 == GET_MODE_BITSIZE (mode))) 4133 { 4134 op0 = expand_compound_operation (op0); 4135 return gen_unary (NEG, mode, mode, 4136 gen_lowpart_for_combine (mode, op0)); 4137 } 4138 4139 else if (STORE_FLAG_VALUE == 1 4140 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT 4141 && op1 == const0_rtx 4142 && nonzero_bits (op0, mode) == 1) 4143 { 4144 op0 = expand_compound_operation (op0); 4145 return gen_binary (XOR, mode, 4146 gen_lowpart_for_combine (mode, op0), 4147 const1_rtx); 4148 } 4149 4150 else if (STORE_FLAG_VALUE == 1 4151 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT 4152 && op1 == const0_rtx 4153 && (num_sign_bit_copies (op0, mode) 4154 == GET_MODE_BITSIZE (mode))) 4155 { 4156 op0 = expand_compound_operation (op0); 4157 return plus_constant (gen_lowpart_for_combine (mode, op0), 1); 4158 } 4159 4160 /* If STORE_FLAG_VALUE is -1, we have cases similar to 4161 those above. */ 4162 if (STORE_FLAG_VALUE == -1 4163 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT 4164 && op1 == const0_rtx 4165 && (num_sign_bit_copies (op0, mode) 4166 == GET_MODE_BITSIZE (mode))) 4167 return gen_lowpart_for_combine (mode, 4168 expand_compound_operation (op0)); 4169 4170 else if (STORE_FLAG_VALUE == -1 4171 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT 4172 && op1 == const0_rtx 4173 && nonzero_bits (op0, mode) == 1) 4174 { 4175 op0 = expand_compound_operation (op0); 4176 return gen_unary (NEG, mode, mode, 4177 gen_lowpart_for_combine (mode, op0)); 4178 } 4179 4180 else if (STORE_FLAG_VALUE == -1 4181 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT 4182 && op1 == const0_rtx 4183 && (num_sign_bit_copies (op0, mode) 4184 == GET_MODE_BITSIZE (mode))) 4185 { 4186 op0 = expand_compound_operation (op0); 4187 return gen_unary (NOT, mode, mode, 4188 gen_lowpart_for_combine (mode, op0)); 4189 } 4190 4191 /* If X is 0/1, (eq X 0) is X-1. */ 4192 else if (STORE_FLAG_VALUE == -1 4193 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT 4194 && op1 == const0_rtx 4195 && nonzero_bits (op0, mode) == 1) 4196 { 4197 op0 = expand_compound_operation (op0); 4198 return plus_constant (gen_lowpart_for_combine (mode, op0), -1); 4199 } 4200 4201 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just 4202 one bit that might be nonzero, we can convert (ne x 0) to 4203 (ashift x c) where C puts the bit in the sign bit. Remove any 4204 AND with STORE_FLAG_VALUE when we are done, since we are only 4205 going to test the sign bit. */ 4206 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT 4207 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 4208 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode)) 4209 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE(mode)-1)) 4210 && op1 == const0_rtx 4211 && mode == GET_MODE (op0) 4212 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0) 4213 { 4214 x = simplify_shift_const (NULL_RTX, ASHIFT, mode, 4215 expand_compound_operation (op0), 4216 GET_MODE_BITSIZE (mode) - 1 - i); 4217 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx) 4218 return XEXP (x, 0); 4219 else 4220 return x; 4221 } 4222 4223 /* If the code changed, return a whole new comparison. */ 4224 if (new_code != code) 4225 return gen_rtx_combine (new_code, mode, op0, op1); 4226 4227 /* Otherwise, keep this operation, but maybe change its operands. 4228 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */ 4229 SUBST (XEXP (x, 0), op0); 4230 SUBST (XEXP (x, 1), op1); 4231 } 4232 break; 4233 4234 case IF_THEN_ELSE: 4235 return simplify_if_then_else (x); 4236 4237 case ZERO_EXTRACT: 4238 case SIGN_EXTRACT: 4239 case ZERO_EXTEND: 4240 case SIGN_EXTEND: 4241 /* If we are processing SET_DEST, we are done. */ 4242 if (in_dest) 4243 return x; 4244 4245 return expand_compound_operation (x); 4246 4247 case SET: 4248 return simplify_set (x); 4249 4250 case AND: 4251 case IOR: 4252 case XOR: 4253 return simplify_logical (x, last); 4254 4255 case ABS: 4256 /* (abs (neg <foo>)) -> (abs <foo>) */ 4257 if (GET_CODE (XEXP (x, 0)) == NEG) 4258 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); 4259 4260 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS), 4261 do nothing. */ 4262 if (GET_MODE (XEXP (x, 0)) == VOIDmode) 4263 break; 4264 4265 /* If operand is something known to be positive, ignore the ABS. */ 4266 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS 4267 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) 4268 <= HOST_BITS_PER_WIDE_INT) 4269 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0))) 4270 & ((HOST_WIDE_INT) 1 4271 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))) 4272 == 0))) 4273 return XEXP (x, 0); 4274 4275 4276 /* If operand is known to be only -1 or 0, convert ABS to NEG. */ 4277 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode)) 4278 return gen_rtx_combine (NEG, mode, XEXP (x, 0)); 4279 4280 break; 4281 4282 case FFS: 4283 /* (ffs (*_extend <X>)) = (ffs <X>) */ 4284 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND 4285 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND) 4286 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); 4287 break; 4288 4289 case FLOAT: 4290 /* (float (sign_extend <X>)) = (float <X>). */ 4291 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND) 4292 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); 4293 break; 4294 4295 case ASHIFT: 4296 case LSHIFTRT: 4297 case ASHIFTRT: 4298 case ROTATE: 4299 case ROTATERT: 4300 /* If this is a shift by a constant amount, simplify it. */ 4301 if (GET_CODE (XEXP (x, 1)) == CONST_INT) 4302 return simplify_shift_const (x, code, mode, XEXP (x, 0), 4303 INTVAL (XEXP (x, 1))); 4304 4305#ifdef SHIFT_COUNT_TRUNCATED 4306 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG) 4307 SUBST (XEXP (x, 1), 4308 force_to_mode (XEXP (x, 1), GET_MODE (x), 4309 ((HOST_WIDE_INT) 1 4310 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x)))) 4311 - 1, 4312 NULL_RTX, 0)); 4313#endif 4314 4315 break; 4316 4317 default: 4318 break; 4319 } 4320 4321 return x; 4322} 4323 4324/* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */ 4325 4326static rtx 4327simplify_if_then_else (x) 4328 rtx x; 4329{ 4330 enum machine_mode mode = GET_MODE (x); 4331 rtx cond = XEXP (x, 0); 4332 rtx true = XEXP (x, 1); 4333 rtx false = XEXP (x, 2); 4334 enum rtx_code true_code = GET_CODE (cond); 4335 int comparison_p = GET_RTX_CLASS (true_code) == '<'; 4336 rtx temp; 4337 int i; 4338 4339 /* Simplify storing of the truth value. */ 4340 if (comparison_p && true == const_true_rtx && false == const0_rtx) 4341 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1)); 4342 4343 /* Also when the truth value has to be reversed. */ 4344 if (comparison_p && reversible_comparison_p (cond) 4345 && true == const0_rtx && false == const_true_rtx) 4346 return gen_binary (reverse_condition (true_code), 4347 mode, XEXP (cond, 0), XEXP (cond, 1)); 4348 4349 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used 4350 in it is being compared against certain values. Get the true and false 4351 comparisons and see if that says anything about the value of each arm. */ 4352 4353 if (comparison_p && reversible_comparison_p (cond) 4354 && GET_CODE (XEXP (cond, 0)) == REG) 4355 { 4356 HOST_WIDE_INT nzb; 4357 rtx from = XEXP (cond, 0); 4358 enum rtx_code false_code = reverse_condition (true_code); 4359 rtx true_val = XEXP (cond, 1); 4360 rtx false_val = true_val; 4361 int swapped = 0; 4362 4363 /* If FALSE_CODE is EQ, swap the codes and arms. */ 4364 4365 if (false_code == EQ) 4366 { 4367 swapped = 1, true_code = EQ, false_code = NE; 4368 temp = true, true = false, false = temp; 4369 } 4370 4371 /* If we are comparing against zero and the expression being tested has 4372 only a single bit that might be nonzero, that is its value when it is 4373 not equal to zero. Similarly if it is known to be -1 or 0. */ 4374 4375 if (true_code == EQ && true_val == const0_rtx 4376 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0) 4377 false_code = EQ, false_val = GEN_INT (nzb); 4378 else if (true_code == EQ && true_val == const0_rtx 4379 && (num_sign_bit_copies (from, GET_MODE (from)) 4380 == GET_MODE_BITSIZE (GET_MODE (from)))) 4381 false_code = EQ, false_val = constm1_rtx; 4382 4383 /* Now simplify an arm if we know the value of the register in the 4384 branch and it is used in the arm. Be careful due to the potential 4385 of locally-shared RTL. */ 4386 4387 if (reg_mentioned_p (from, true)) 4388 true = subst (known_cond (copy_rtx (true), true_code, from, true_val), 4389 pc_rtx, pc_rtx, 0, 0); 4390 if (reg_mentioned_p (from, false)) 4391 false = subst (known_cond (copy_rtx (false), false_code, 4392 from, false_val), 4393 pc_rtx, pc_rtx, 0, 0); 4394 4395 SUBST (XEXP (x, 1), swapped ? false : true); 4396 SUBST (XEXP (x, 2), swapped ? true : false); 4397 4398 true = XEXP (x, 1), false = XEXP (x, 2), true_code = GET_CODE (cond); 4399 } 4400 4401 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be 4402 reversed, do so to avoid needing two sets of patterns for 4403 subtract-and-branch insns. Similarly if we have a constant in the true 4404 arm, the false arm is the same as the first operand of the comparison, or 4405 the false arm is more complicated than the true arm. */ 4406 4407 if (comparison_p && reversible_comparison_p (cond) 4408 && (true == pc_rtx 4409 || (CONSTANT_P (true) 4410 && GET_CODE (false) != CONST_INT && false != pc_rtx) 4411 || true == const0_rtx 4412 || (GET_RTX_CLASS (GET_CODE (true)) == 'o' 4413 && GET_RTX_CLASS (GET_CODE (false)) != 'o') 4414 || (GET_CODE (true) == SUBREG 4415 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true))) == 'o' 4416 && GET_RTX_CLASS (GET_CODE (false)) != 'o') 4417 || reg_mentioned_p (true, false) 4418 || rtx_equal_p (false, XEXP (cond, 0)))) 4419 { 4420 true_code = reverse_condition (true_code); 4421 SUBST (XEXP (x, 0), 4422 gen_binary (true_code, GET_MODE (cond), XEXP (cond, 0), 4423 XEXP (cond, 1))); 4424 4425 SUBST (XEXP (x, 1), false); 4426 SUBST (XEXP (x, 2), true); 4427 4428 temp = true, true = false, false = temp, cond = XEXP (x, 0); 4429 4430 /* It is possible that the conditional has been simplified out. */ 4431 true_code = GET_CODE (cond); 4432 comparison_p = GET_RTX_CLASS (true_code) == '<'; 4433 } 4434 4435 /* If the two arms are identical, we don't need the comparison. */ 4436 4437 if (rtx_equal_p (true, false) && ! side_effects_p (cond)) 4438 return true; 4439 4440 /* Convert a == b ? b : a to "a". */ 4441 if (true_code == EQ && ! side_effects_p (cond) 4442 && rtx_equal_p (XEXP (cond, 0), false) 4443 && rtx_equal_p (XEXP (cond, 1), true)) 4444 return false; 4445 else if (true_code == NE && ! side_effects_p (cond) 4446 && rtx_equal_p (XEXP (cond, 0), true) 4447 && rtx_equal_p (XEXP (cond, 1), false)) 4448 return true; 4449 4450 /* Look for cases where we have (abs x) or (neg (abs X)). */ 4451 4452 if (GET_MODE_CLASS (mode) == MODE_INT 4453 && GET_CODE (false) == NEG 4454 && rtx_equal_p (true, XEXP (false, 0)) 4455 && comparison_p 4456 && rtx_equal_p (true, XEXP (cond, 0)) 4457 && ! side_effects_p (true)) 4458 switch (true_code) 4459 { 4460 case GT: 4461 case GE: 4462 return gen_unary (ABS, mode, mode, true); 4463 case LT: 4464 case LE: 4465 return gen_unary (NEG, mode, mode, gen_unary (ABS, mode, mode, true)); 4466 default: 4467 break; 4468 } 4469 4470 /* Look for MIN or MAX. */ 4471 4472 if ((! FLOAT_MODE_P (mode) || flag_fast_math) 4473 && comparison_p 4474 && rtx_equal_p (XEXP (cond, 0), true) 4475 && rtx_equal_p (XEXP (cond, 1), false) 4476 && ! side_effects_p (cond)) 4477 switch (true_code) 4478 { 4479 case GE: 4480 case GT: 4481 return gen_binary (SMAX, mode, true, false); 4482 case LE: 4483 case LT: 4484 return gen_binary (SMIN, mode, true, false); 4485 case GEU: 4486 case GTU: 4487 return gen_binary (UMAX, mode, true, false); 4488 case LEU: 4489 case LTU: 4490 return gen_binary (UMIN, mode, true, false); 4491 default: 4492 break; 4493 } 4494 4495 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its 4496 second operand is zero, this can be done as (OP Z (mult COND C2)) where 4497 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or 4498 SIGN_EXTEND as long as Z is already extended (so we don't destroy it). 4499 We can do this kind of thing in some cases when STORE_FLAG_VALUE is 4500 neither 1 or -1, but it isn't worth checking for. */ 4501 4502 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) 4503 && comparison_p && mode != VOIDmode && ! side_effects_p (x)) 4504 { 4505 rtx t = make_compound_operation (true, SET); 4506 rtx f = make_compound_operation (false, SET); 4507 rtx cond_op0 = XEXP (cond, 0); 4508 rtx cond_op1 = XEXP (cond, 1); 4509 enum rtx_code op, extend_op = NIL; 4510 enum machine_mode m = mode; 4511 rtx z = 0, c1; 4512 4513 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS 4514 || GET_CODE (t) == IOR || GET_CODE (t) == XOR 4515 || GET_CODE (t) == ASHIFT 4516 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT) 4517 && rtx_equal_p (XEXP (t, 0), f)) 4518 c1 = XEXP (t, 1), op = GET_CODE (t), z = f; 4519 4520 /* If an identity-zero op is commutative, check whether there 4521 would be a match if we swapped the operands. */ 4522 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR 4523 || GET_CODE (t) == XOR) 4524 && rtx_equal_p (XEXP (t, 1), f)) 4525 c1 = XEXP (t, 0), op = GET_CODE (t), z = f; 4526 else if (GET_CODE (t) == SIGN_EXTEND 4527 && (GET_CODE (XEXP (t, 0)) == PLUS 4528 || GET_CODE (XEXP (t, 0)) == MINUS 4529 || GET_CODE (XEXP (t, 0)) == IOR 4530 || GET_CODE (XEXP (t, 0)) == XOR 4531 || GET_CODE (XEXP (t, 0)) == ASHIFT 4532 || GET_CODE (XEXP (t, 0)) == LSHIFTRT 4533 || GET_CODE (XEXP (t, 0)) == ASHIFTRT) 4534 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG 4535 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0)) 4536 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f) 4537 && (num_sign_bit_copies (f, GET_MODE (f)) 4538 > (GET_MODE_BITSIZE (mode) 4539 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0)))))) 4540 { 4541 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0)); 4542 extend_op = SIGN_EXTEND; 4543 m = GET_MODE (XEXP (t, 0)); 4544 } 4545 else if (GET_CODE (t) == SIGN_EXTEND 4546 && (GET_CODE (XEXP (t, 0)) == PLUS 4547 || GET_CODE (XEXP (t, 0)) == IOR 4548 || GET_CODE (XEXP (t, 0)) == XOR) 4549 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG 4550 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1)) 4551 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f) 4552 && (num_sign_bit_copies (f, GET_MODE (f)) 4553 > (GET_MODE_BITSIZE (mode) 4554 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1)))))) 4555 { 4556 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0)); 4557 extend_op = SIGN_EXTEND; 4558 m = GET_MODE (XEXP (t, 0)); 4559 } 4560 else if (GET_CODE (t) == ZERO_EXTEND 4561 && (GET_CODE (XEXP (t, 0)) == PLUS 4562 || GET_CODE (XEXP (t, 0)) == MINUS 4563 || GET_CODE (XEXP (t, 0)) == IOR 4564 || GET_CODE (XEXP (t, 0)) == XOR 4565 || GET_CODE (XEXP (t, 0)) == ASHIFT 4566 || GET_CODE (XEXP (t, 0)) == LSHIFTRT 4567 || GET_CODE (XEXP (t, 0)) == ASHIFTRT) 4568 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG 4569 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 4570 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0)) 4571 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f) 4572 && ((nonzero_bits (f, GET_MODE (f)) 4573 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0)))) 4574 == 0)) 4575 { 4576 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0)); 4577 extend_op = ZERO_EXTEND; 4578 m = GET_MODE (XEXP (t, 0)); 4579 } 4580 else if (GET_CODE (t) == ZERO_EXTEND 4581 && (GET_CODE (XEXP (t, 0)) == PLUS 4582 || GET_CODE (XEXP (t, 0)) == IOR 4583 || GET_CODE (XEXP (t, 0)) == XOR) 4584 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG 4585 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 4586 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1)) 4587 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f) 4588 && ((nonzero_bits (f, GET_MODE (f)) 4589 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1)))) 4590 == 0)) 4591 { 4592 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0)); 4593 extend_op = ZERO_EXTEND; 4594 m = GET_MODE (XEXP (t, 0)); 4595 } 4596 4597 if (z) 4598 { 4599 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1), 4600 pc_rtx, pc_rtx, 0, 0); 4601 temp = gen_binary (MULT, m, temp, 4602 gen_binary (MULT, m, c1, const_true_rtx)); 4603 temp = subst (temp, pc_rtx, pc_rtx, 0, 0); 4604 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp); 4605 4606 if (extend_op != NIL) 4607 temp = gen_unary (extend_op, mode, m, temp); 4608 4609 return temp; 4610 } 4611 } 4612 4613 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or 4614 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the 4615 negation of a single bit, we can convert this operation to a shift. We 4616 can actually do this more generally, but it doesn't seem worth it. */ 4617 4618 if (true_code == NE && XEXP (cond, 1) == const0_rtx 4619 && false == const0_rtx && GET_CODE (true) == CONST_INT 4620 && ((1 == nonzero_bits (XEXP (cond, 0), mode) 4621 && (i = exact_log2 (INTVAL (true))) >= 0) 4622 || ((num_sign_bit_copies (XEXP (cond, 0), mode) 4623 == GET_MODE_BITSIZE (mode)) 4624 && (i = exact_log2 (- INTVAL (true))) >= 0))) 4625 return 4626 simplify_shift_const (NULL_RTX, ASHIFT, mode, 4627 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i); 4628 4629 return x; 4630} 4631 4632/* Simplify X, a SET expression. Return the new expression. */ 4633 4634static rtx 4635simplify_set (x) 4636 rtx x; 4637{ 4638 rtx src = SET_SRC (x); 4639 rtx dest = SET_DEST (x); 4640 enum machine_mode mode 4641 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest); 4642 rtx other_insn; 4643 rtx *cc_use; 4644 4645 /* (set (pc) (return)) gets written as (return). */ 4646 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN) 4647 return src; 4648 4649 /* Now that we know for sure which bits of SRC we are using, see if we can 4650 simplify the expression for the object knowing that we only need the 4651 low-order bits. */ 4652 4653 if (GET_MODE_CLASS (mode) == MODE_INT) 4654 src = force_to_mode (src, mode, GET_MODE_MASK (mode), NULL_RTX, 0); 4655 4656 /* If we are setting CC0 or if the source is a COMPARE, look for the use of 4657 the comparison result and try to simplify it unless we already have used 4658 undobuf.other_insn. */ 4659 if ((GET_CODE (src) == COMPARE 4660#ifdef HAVE_cc0 4661 || dest == cc0_rtx 4662#endif 4663 ) 4664 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0 4665 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn) 4666 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<' 4667 && rtx_equal_p (XEXP (*cc_use, 0), dest)) 4668 { 4669 enum rtx_code old_code = GET_CODE (*cc_use); 4670 enum rtx_code new_code; 4671 rtx op0, op1; 4672 int other_changed = 0; 4673 enum machine_mode compare_mode = GET_MODE (dest); 4674 4675 if (GET_CODE (src) == COMPARE) 4676 op0 = XEXP (src, 0), op1 = XEXP (src, 1); 4677 else 4678 op0 = src, op1 = const0_rtx; 4679 4680 /* Simplify our comparison, if possible. */ 4681 new_code = simplify_comparison (old_code, &op0, &op1); 4682 4683#ifdef EXTRA_CC_MODES 4684 /* If this machine has CC modes other than CCmode, check to see if we 4685 need to use a different CC mode here. */ 4686 compare_mode = SELECT_CC_MODE (new_code, op0, op1); 4687#endif /* EXTRA_CC_MODES */ 4688 4689#if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES) 4690 /* If the mode changed, we have to change SET_DEST, the mode in the 4691 compare, and the mode in the place SET_DEST is used. If SET_DEST is 4692 a hard register, just build new versions with the proper mode. If it 4693 is a pseudo, we lose unless it is only time we set the pseudo, in 4694 which case we can safely change its mode. */ 4695 if (compare_mode != GET_MODE (dest)) 4696 { 4697 int regno = REGNO (dest); 4698 rtx new_dest = gen_rtx_REG (compare_mode, regno); 4699 4700 if (regno < FIRST_PSEUDO_REGISTER 4701 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest))) 4702 { 4703 if (regno >= FIRST_PSEUDO_REGISTER) 4704 SUBST (regno_reg_rtx[regno], new_dest); 4705 4706 SUBST (SET_DEST (x), new_dest); 4707 SUBST (XEXP (*cc_use, 0), new_dest); 4708 other_changed = 1; 4709 4710 dest = new_dest; 4711 } 4712 } 4713#endif 4714 4715 /* If the code changed, we have to build a new comparison in 4716 undobuf.other_insn. */ 4717 if (new_code != old_code) 4718 { 4719 unsigned HOST_WIDE_INT mask; 4720 4721 SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use), 4722 dest, const0_rtx)); 4723 4724 /* If the only change we made was to change an EQ into an NE or 4725 vice versa, OP0 has only one bit that might be nonzero, and OP1 4726 is zero, check if changing the user of the condition code will 4727 produce a valid insn. If it won't, we can keep the original code 4728 in that insn by surrounding our operation with an XOR. */ 4729 4730 if (((old_code == NE && new_code == EQ) 4731 || (old_code == EQ && new_code == NE)) 4732 && ! other_changed && op1 == const0_rtx 4733 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT 4734 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0) 4735 { 4736 rtx pat = PATTERN (other_insn), note = 0; 4737 4738 if ((recog_for_combine (&pat, other_insn, ¬e) < 0 4739 && ! check_asm_operands (pat))) 4740 { 4741 PUT_CODE (*cc_use, old_code); 4742 other_insn = 0; 4743 4744 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask)); 4745 } 4746 } 4747 4748 other_changed = 1; 4749 } 4750 4751 if (other_changed) 4752 undobuf.other_insn = other_insn; 4753 4754#ifdef HAVE_cc0 4755 /* If we are now comparing against zero, change our source if 4756 needed. If we do not use cc0, we always have a COMPARE. */ 4757 if (op1 == const0_rtx && dest == cc0_rtx) 4758 { 4759 SUBST (SET_SRC (x), op0); 4760 src = op0; 4761 } 4762 else 4763#endif 4764 4765 /* Otherwise, if we didn't previously have a COMPARE in the 4766 correct mode, we need one. */ 4767 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode) 4768 { 4769 SUBST (SET_SRC (x), 4770 gen_rtx_combine (COMPARE, compare_mode, op0, op1)); 4771 src = SET_SRC (x); 4772 } 4773 else 4774 { 4775 /* Otherwise, update the COMPARE if needed. */ 4776 SUBST (XEXP (src, 0), op0); 4777 SUBST (XEXP (src, 1), op1); 4778 } 4779 } 4780 else 4781 { 4782 /* Get SET_SRC in a form where we have placed back any 4783 compound expressions. Then do the checks below. */ 4784 src = make_compound_operation (src, SET); 4785 SUBST (SET_SRC (x), src); 4786 } 4787 4788 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation, 4789 and X being a REG or (subreg (reg)), we may be able to convert this to 4790 (set (subreg:m2 x) (op)). 4791 4792 We can always do this if M1 is narrower than M2 because that means that 4793 we only care about the low bits of the result. 4794 4795 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot 4796 perform a narrower operation than requested since the high-order bits will 4797 be undefined. On machine where it is defined, this transformation is safe 4798 as long as M1 and M2 have the same number of words. */ 4799 4800 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src) 4801 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o' 4802 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1)) 4803 / UNITS_PER_WORD) 4804 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))) 4805 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)) 4806#ifndef WORD_REGISTER_OPERATIONS 4807 && (GET_MODE_SIZE (GET_MODE (src)) 4808 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))) 4809#endif 4810#ifdef CLASS_CANNOT_CHANGE_SIZE 4811 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER 4812 && (TEST_HARD_REG_BIT 4813 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE], 4814 REGNO (dest))) 4815 && (GET_MODE_SIZE (GET_MODE (src)) 4816 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))) 4817#endif 4818 && (GET_CODE (dest) == REG 4819 || (GET_CODE (dest) == SUBREG 4820 && GET_CODE (SUBREG_REG (dest)) == REG))) 4821 { 4822 SUBST (SET_DEST (x), 4823 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)), 4824 dest)); 4825 SUBST (SET_SRC (x), SUBREG_REG (src)); 4826 4827 src = SET_SRC (x), dest = SET_DEST (x); 4828 } 4829 4830#ifdef LOAD_EXTEND_OP 4831 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this 4832 would require a paradoxical subreg. Replace the subreg with a 4833 zero_extend to avoid the reload that would otherwise be required. */ 4834 4835 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src) 4836 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL 4837 && SUBREG_WORD (src) == 0 4838 && (GET_MODE_SIZE (GET_MODE (src)) 4839 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))) 4840 && GET_CODE (SUBREG_REG (src)) == MEM) 4841 { 4842 SUBST (SET_SRC (x), 4843 gen_rtx_combine (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))), 4844 GET_MODE (src), XEXP (src, 0))); 4845 4846 src = SET_SRC (x); 4847 } 4848#endif 4849 4850 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we 4851 are comparing an item known to be 0 or -1 against 0, use a logical 4852 operation instead. Check for one of the arms being an IOR of the other 4853 arm with some value. We compute three terms to be IOR'ed together. In 4854 practice, at most two will be nonzero. Then we do the IOR's. */ 4855 4856 if (GET_CODE (dest) != PC 4857 && GET_CODE (src) == IF_THEN_ELSE 4858 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT 4859 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE) 4860 && XEXP (XEXP (src, 0), 1) == const0_rtx 4861 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0)) 4862#ifdef HAVE_conditional_move 4863 && ! can_conditionally_move_p (GET_MODE (src)) 4864#endif 4865 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0), 4866 GET_MODE (XEXP (XEXP (src, 0), 0))) 4867 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0)))) 4868 && ! side_effects_p (src)) 4869 { 4870 rtx true = (GET_CODE (XEXP (src, 0)) == NE 4871 ? XEXP (src, 1) : XEXP (src, 2)); 4872 rtx false = (GET_CODE (XEXP (src, 0)) == NE 4873 ? XEXP (src, 2) : XEXP (src, 1)); 4874 rtx term1 = const0_rtx, term2, term3; 4875 4876 if (GET_CODE (true) == IOR && rtx_equal_p (XEXP (true, 0), false)) 4877 term1 = false, true = XEXP (true, 1), false = const0_rtx; 4878 else if (GET_CODE (true) == IOR 4879 && rtx_equal_p (XEXP (true, 1), false)) 4880 term1 = false, true = XEXP (true, 0), false = const0_rtx; 4881 else if (GET_CODE (false) == IOR 4882 && rtx_equal_p (XEXP (false, 0), true)) 4883 term1 = true, false = XEXP (false, 1), true = const0_rtx; 4884 else if (GET_CODE (false) == IOR 4885 && rtx_equal_p (XEXP (false, 1), true)) 4886 term1 = true, false = XEXP (false, 0), true = const0_rtx; 4887 4888 term2 = gen_binary (AND, GET_MODE (src), XEXP (XEXP (src, 0), 0), true); 4889 term3 = gen_binary (AND, GET_MODE (src), 4890 gen_unary (NOT, GET_MODE (src), GET_MODE (src), 4891 XEXP (XEXP (src, 0), 0)), 4892 false); 4893 4894 SUBST (SET_SRC (x), 4895 gen_binary (IOR, GET_MODE (src), 4896 gen_binary (IOR, GET_MODE (src), term1, term2), 4897 term3)); 4898 4899 src = SET_SRC (x); 4900 } 4901 4902 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this 4903 whole thing fail. */ 4904 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx) 4905 return src; 4906 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx) 4907 return dest; 4908 else 4909 /* Convert this into a field assignment operation, if possible. */ 4910 return make_field_assignment (x); 4911} 4912 4913/* Simplify, X, and AND, IOR, or XOR operation, and return the simplified 4914 result. LAST is nonzero if this is the last retry. */ 4915 4916static rtx 4917simplify_logical (x, last) 4918 rtx x; 4919 int last; 4920{ 4921 enum machine_mode mode = GET_MODE (x); 4922 rtx op0 = XEXP (x, 0); 4923 rtx op1 = XEXP (x, 1); 4924 4925 switch (GET_CODE (x)) 4926 { 4927 case AND: 4928 /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single 4929 insn (and may simplify more). */ 4930 if (GET_CODE (op0) == XOR 4931 && rtx_equal_p (XEXP (op0, 0), op1) 4932 && ! side_effects_p (op1)) 4933 x = gen_binary (AND, mode, 4934 gen_unary (NOT, mode, mode, XEXP (op0, 1)), op1); 4935 4936 if (GET_CODE (op0) == XOR 4937 && rtx_equal_p (XEXP (op0, 1), op1) 4938 && ! side_effects_p (op1)) 4939 x = gen_binary (AND, mode, 4940 gen_unary (NOT, mode, mode, XEXP (op0, 0)), op1); 4941 4942 /* Similarly for (~ (A ^ B)) & A. */ 4943 if (GET_CODE (op0) == NOT 4944 && GET_CODE (XEXP (op0, 0)) == XOR 4945 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1) 4946 && ! side_effects_p (op1)) 4947 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1); 4948 4949 if (GET_CODE (op0) == NOT 4950 && GET_CODE (XEXP (op0, 0)) == XOR 4951 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1) 4952 && ! side_effects_p (op1)) 4953 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1); 4954 4955 if (GET_CODE (op1) == CONST_INT) 4956 { 4957 x = simplify_and_const_int (x, mode, op0, INTVAL (op1)); 4958 4959 /* If we have (ior (and (X C1) C2)) and the next restart would be 4960 the last, simplify this by making C1 as small as possible 4961 and then exit. */ 4962 if (last 4963 && GET_CODE (x) == IOR && GET_CODE (op0) == AND 4964 && GET_CODE (XEXP (op0, 1)) == CONST_INT 4965 && GET_CODE (op1) == CONST_INT) 4966 return gen_binary (IOR, mode, 4967 gen_binary (AND, mode, XEXP (op0, 0), 4968 GEN_INT (INTVAL (XEXP (op0, 1)) 4969 & ~ INTVAL (op1))), op1); 4970 4971 if (GET_CODE (x) != AND) 4972 return x; 4973 4974 if (GET_RTX_CLASS (GET_CODE (x)) == 'c' 4975 || GET_RTX_CLASS (GET_CODE (x)) == '2') 4976 op0 = XEXP (x, 0), op1 = XEXP (x, 1); 4977 } 4978 4979 /* Convert (A | B) & A to A. */ 4980 if (GET_CODE (op0) == IOR 4981 && (rtx_equal_p (XEXP (op0, 0), op1) 4982 || rtx_equal_p (XEXP (op0, 1), op1)) 4983 && ! side_effects_p (XEXP (op0, 0)) 4984 && ! side_effects_p (XEXP (op0, 1))) 4985 return op1; 4986 4987 /* In the following group of tests (and those in case IOR below), 4988 we start with some combination of logical operations and apply 4989 the distributive law followed by the inverse distributive law. 4990 Most of the time, this results in no change. However, if some of 4991 the operands are the same or inverses of each other, simplifications 4992 will result. 4993 4994 For example, (and (ior A B) (not B)) can occur as the result of 4995 expanding a bit field assignment. When we apply the distributive 4996 law to this, we get (ior (and (A (not B))) (and (B (not B)))), 4997 which then simplifies to (and (A (not B))). 4998 4999 If we have (and (ior A B) C), apply the distributive law and then 5000 the inverse distributive law to see if things simplify. */ 5001 5002 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR) 5003 { 5004 x = apply_distributive_law 5005 (gen_binary (GET_CODE (op0), mode, 5006 gen_binary (AND, mode, XEXP (op0, 0), op1), 5007 gen_binary (AND, mode, XEXP (op0, 1), 5008 copy_rtx (op1)))); 5009 if (GET_CODE (x) != AND) 5010 return x; 5011 } 5012 5013 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR) 5014 return apply_distributive_law 5015 (gen_binary (GET_CODE (op1), mode, 5016 gen_binary (AND, mode, XEXP (op1, 0), op0), 5017 gen_binary (AND, mode, XEXP (op1, 1), 5018 copy_rtx (op0)))); 5019 5020 /* Similarly, taking advantage of the fact that 5021 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */ 5022 5023 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR) 5024 return apply_distributive_law 5025 (gen_binary (XOR, mode, 5026 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)), 5027 gen_binary (IOR, mode, copy_rtx (XEXP (op0, 0)), 5028 XEXP (op1, 1)))); 5029 5030 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR) 5031 return apply_distributive_law 5032 (gen_binary (XOR, mode, 5033 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)), 5034 gen_binary (IOR, mode, copy_rtx (XEXP (op1, 0)), XEXP (op0, 1)))); 5035 break; 5036 5037 case IOR: 5038 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */ 5039 if (GET_CODE (op1) == CONST_INT 5040 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 5041 && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0) 5042 return op1; 5043 5044 /* Convert (A & B) | A to A. */ 5045 if (GET_CODE (op0) == AND 5046 && (rtx_equal_p (XEXP (op0, 0), op1) 5047 || rtx_equal_p (XEXP (op0, 1), op1)) 5048 && ! side_effects_p (XEXP (op0, 0)) 5049 && ! side_effects_p (XEXP (op0, 1))) 5050 return op1; 5051 5052 /* If we have (ior (and A B) C), apply the distributive law and then 5053 the inverse distributive law to see if things simplify. */ 5054 5055 if (GET_CODE (op0) == AND) 5056 { 5057 x = apply_distributive_law 5058 (gen_binary (AND, mode, 5059 gen_binary (IOR, mode, XEXP (op0, 0), op1), 5060 gen_binary (IOR, mode, XEXP (op0, 1), 5061 copy_rtx (op1)))); 5062 5063 if (GET_CODE (x) != IOR) 5064 return x; 5065 } 5066 5067 if (GET_CODE (op1) == AND) 5068 { 5069 x = apply_distributive_law 5070 (gen_binary (AND, mode, 5071 gen_binary (IOR, mode, XEXP (op1, 0), op0), 5072 gen_binary (IOR, mode, XEXP (op1, 1), 5073 copy_rtx (op0)))); 5074 5075 if (GET_CODE (x) != IOR) 5076 return x; 5077 } 5078 5079 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the 5080 mode size to (rotate A CX). */ 5081 5082 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT) 5083 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT)) 5084 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0)) 5085 && GET_CODE (XEXP (op0, 1)) == CONST_INT 5086 && GET_CODE (XEXP (op1, 1)) == CONST_INT 5087 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1)) 5088 == GET_MODE_BITSIZE (mode))) 5089 return gen_rtx_ROTATE (mode, XEXP (op0, 0), 5090 (GET_CODE (op0) == ASHIFT 5091 ? XEXP (op0, 1) : XEXP (op1, 1))); 5092 5093 /* If OP0 is (ashiftrt (plus ...) C), it might actually be 5094 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS 5095 does not affect any of the bits in OP1, it can really be done 5096 as a PLUS and we can associate. We do this by seeing if OP1 5097 can be safely shifted left C bits. */ 5098 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT 5099 && GET_CODE (XEXP (op0, 0)) == PLUS 5100 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT 5101 && GET_CODE (XEXP (op0, 1)) == CONST_INT 5102 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT) 5103 { 5104 int count = INTVAL (XEXP (op0, 1)); 5105 HOST_WIDE_INT mask = INTVAL (op1) << count; 5106 5107 if (mask >> count == INTVAL (op1) 5108 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0) 5109 { 5110 SUBST (XEXP (XEXP (op0, 0), 1), 5111 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask)); 5112 return op0; 5113 } 5114 } 5115 break; 5116 5117 case XOR: 5118 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y). 5119 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for 5120 (NOT y). */ 5121 { 5122 int num_negated = 0; 5123 5124 if (GET_CODE (op0) == NOT) 5125 num_negated++, op0 = XEXP (op0, 0); 5126 if (GET_CODE (op1) == NOT) 5127 num_negated++, op1 = XEXP (op1, 0); 5128 5129 if (num_negated == 2) 5130 { 5131 SUBST (XEXP (x, 0), op0); 5132 SUBST (XEXP (x, 1), op1); 5133 } 5134 else if (num_negated == 1) 5135 return gen_unary (NOT, mode, mode, gen_binary (XOR, mode, op0, op1)); 5136 } 5137 5138 /* Convert (xor (and A B) B) to (and (not A) B). The latter may 5139 correspond to a machine insn or result in further simplifications 5140 if B is a constant. */ 5141 5142 if (GET_CODE (op0) == AND 5143 && rtx_equal_p (XEXP (op0, 1), op1) 5144 && ! side_effects_p (op1)) 5145 return gen_binary (AND, mode, 5146 gen_unary (NOT, mode, mode, XEXP (op0, 0)), 5147 op1); 5148 5149 else if (GET_CODE (op0) == AND 5150 && rtx_equal_p (XEXP (op0, 0), op1) 5151 && ! side_effects_p (op1)) 5152 return gen_binary (AND, mode, 5153 gen_unary (NOT, mode, mode, XEXP (op0, 1)), 5154 op1); 5155 5156 /* (xor (comparison foo bar) (const_int 1)) can become the reversed 5157 comparison if STORE_FLAG_VALUE is 1. */ 5158 if (STORE_FLAG_VALUE == 1 5159 && op1 == const1_rtx 5160 && GET_RTX_CLASS (GET_CODE (op0)) == '<' 5161 && reversible_comparison_p (op0)) 5162 return gen_rtx_combine (reverse_condition (GET_CODE (op0)), 5163 mode, XEXP (op0, 0), XEXP (op0, 1)); 5164 5165 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1 5166 is (lt foo (const_int 0)), so we can perform the above 5167 simplification if STORE_FLAG_VALUE is 1. */ 5168 5169 if (STORE_FLAG_VALUE == 1 5170 && op1 == const1_rtx 5171 && GET_CODE (op0) == LSHIFTRT 5172 && GET_CODE (XEXP (op0, 1)) == CONST_INT 5173 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1) 5174 return gen_rtx_combine (GE, mode, XEXP (op0, 0), const0_rtx); 5175 5176 /* (xor (comparison foo bar) (const_int sign-bit)) 5177 when STORE_FLAG_VALUE is the sign bit. */ 5178 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 5179 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode)) 5180 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1)) 5181 && op1 == const_true_rtx 5182 && GET_RTX_CLASS (GET_CODE (op0)) == '<' 5183 && reversible_comparison_p (op0)) 5184 return gen_rtx_combine (reverse_condition (GET_CODE (op0)), 5185 mode, XEXP (op0, 0), XEXP (op0, 1)); 5186 break; 5187 5188 default: 5189 abort (); 5190 } 5191 5192 return x; 5193} 5194 5195/* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound 5196 operations" because they can be replaced with two more basic operations. 5197 ZERO_EXTEND is also considered "compound" because it can be replaced with 5198 an AND operation, which is simpler, though only one operation. 5199 5200 The function expand_compound_operation is called with an rtx expression 5201 and will convert it to the appropriate shifts and AND operations, 5202 simplifying at each stage. 5203 5204 The function make_compound_operation is called to convert an expression 5205 consisting of shifts and ANDs into the equivalent compound expression. 5206 It is the inverse of this function, loosely speaking. */ 5207 5208static rtx 5209expand_compound_operation (x) 5210 rtx x; 5211{ 5212 int pos = 0, len; 5213 int unsignedp = 0; 5214 int modewidth; 5215 rtx tem; 5216 5217 switch (GET_CODE (x)) 5218 { 5219 case ZERO_EXTEND: 5220 unsignedp = 1; 5221 case SIGN_EXTEND: 5222 /* We can't necessarily use a const_int for a multiword mode; 5223 it depends on implicitly extending the value. 5224 Since we don't know the right way to extend it, 5225 we can't tell whether the implicit way is right. 5226 5227 Even for a mode that is no wider than a const_int, 5228 we can't win, because we need to sign extend one of its bits through 5229 the rest of it, and we don't know which bit. */ 5230 if (GET_CODE (XEXP (x, 0)) == CONST_INT) 5231 return x; 5232 5233 /* Return if (subreg:MODE FROM 0) is not a safe replacement for 5234 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM 5235 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be 5236 reloaded. If not for that, MEM's would very rarely be safe. 5237 5238 Reject MODEs bigger than a word, because we might not be able 5239 to reference a two-register group starting with an arbitrary register 5240 (and currently gen_lowpart might crash for a SUBREG). */ 5241 5242 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD) 5243 return x; 5244 5245 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))); 5246 /* If the inner object has VOIDmode (the only way this can happen 5247 is if it is a ASM_OPERANDS), we can't do anything since we don't 5248 know how much masking to do. */ 5249 if (len == 0) 5250 return x; 5251 5252 break; 5253 5254 case ZERO_EXTRACT: 5255 unsignedp = 1; 5256 case SIGN_EXTRACT: 5257 /* If the operand is a CLOBBER, just return it. */ 5258 if (GET_CODE (XEXP (x, 0)) == CLOBBER) 5259 return XEXP (x, 0); 5260 5261 if (GET_CODE (XEXP (x, 1)) != CONST_INT 5262 || GET_CODE (XEXP (x, 2)) != CONST_INT 5263 || GET_MODE (XEXP (x, 0)) == VOIDmode) 5264 return x; 5265 5266 len = INTVAL (XEXP (x, 1)); 5267 pos = INTVAL (XEXP (x, 2)); 5268 5269 /* If this goes outside the object being extracted, replace the object 5270 with a (use (mem ...)) construct that only combine understands 5271 and is used only for this purpose. */ 5272 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))) 5273 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0))); 5274 5275 if (BITS_BIG_ENDIAN) 5276 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos; 5277 5278 break; 5279 5280 default: 5281 return x; 5282 } 5283 5284 /* We can optimize some special cases of ZERO_EXTEND. */ 5285 if (GET_CODE (x) == ZERO_EXTEND) 5286 { 5287 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we 5288 know that the last value didn't have any inappropriate bits 5289 set. */ 5290 if (GET_CODE (XEXP (x, 0)) == TRUNCATE 5291 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x) 5292 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT 5293 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x)) 5294 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) 5295 return XEXP (XEXP (x, 0), 0); 5296 5297 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */ 5298 if (GET_CODE (XEXP (x, 0)) == SUBREG 5299 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x) 5300 && subreg_lowpart_p (XEXP (x, 0)) 5301 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT 5302 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x)) 5303 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) 5304 return SUBREG_REG (XEXP (x, 0)); 5305 5306 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo 5307 is a comparison and STORE_FLAG_VALUE permits. This is like 5308 the first case, but it works even when GET_MODE (x) is larger 5309 than HOST_WIDE_INT. */ 5310 if (GET_CODE (XEXP (x, 0)) == TRUNCATE 5311 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x) 5312 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<' 5313 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) 5314 <= HOST_BITS_PER_WIDE_INT) 5315 && ((HOST_WIDE_INT) STORE_FLAG_VALUE 5316 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) 5317 return XEXP (XEXP (x, 0), 0); 5318 5319 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */ 5320 if (GET_CODE (XEXP (x, 0)) == SUBREG 5321 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x) 5322 && subreg_lowpart_p (XEXP (x, 0)) 5323 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<' 5324 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) 5325 <= HOST_BITS_PER_WIDE_INT) 5326 && ((HOST_WIDE_INT) STORE_FLAG_VALUE 5327 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) 5328 return SUBREG_REG (XEXP (x, 0)); 5329 5330 /* If sign extension is cheaper than zero extension, then use it 5331 if we know that no extraneous bits are set, and that the high 5332 bit is not set. */ 5333 if (flag_expensive_optimizations 5334 && ((GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT 5335 && ((nonzero_bits (XEXP (x, 0), GET_MODE (x)) 5336 & ~ (((unsigned HOST_WIDE_INT) 5337 GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) 5338 >> 1)) 5339 == 0)) 5340 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' 5341 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) 5342 <= HOST_BITS_PER_WIDE_INT) 5343 && (((HOST_WIDE_INT) STORE_FLAG_VALUE 5344 & ~ (((unsigned HOST_WIDE_INT) 5345 GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) 5346 >> 1)) 5347 == 0)))) 5348 { 5349 rtx temp = gen_rtx_SIGN_EXTEND (GET_MODE (x), XEXP (x, 0)); 5350 5351 if (rtx_cost (temp, SET) < rtx_cost (x, SET)) 5352 return expand_compound_operation (temp); 5353 } 5354 } 5355 5356 /* If we reach here, we want to return a pair of shifts. The inner 5357 shift is a left shift of BITSIZE - POS - LEN bits. The outer 5358 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or 5359 logical depending on the value of UNSIGNEDP. 5360 5361 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be 5362 converted into an AND of a shift. 5363 5364 We must check for the case where the left shift would have a negative 5365 count. This can happen in a case like (x >> 31) & 255 on machines 5366 that can't shift by a constant. On those machines, we would first 5367 combine the shift with the AND to produce a variable-position 5368 extraction. Then the constant of 31 would be substituted in to produce 5369 a such a position. */ 5370 5371 modewidth = GET_MODE_BITSIZE (GET_MODE (x)); 5372 if (modewidth >= pos - len) 5373 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT, 5374 GET_MODE (x), 5375 simplify_shift_const (NULL_RTX, ASHIFT, 5376 GET_MODE (x), 5377 XEXP (x, 0), 5378 modewidth - pos - len), 5379 modewidth - len); 5380 5381 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT) 5382 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x), 5383 simplify_shift_const (NULL_RTX, LSHIFTRT, 5384 GET_MODE (x), 5385 XEXP (x, 0), pos), 5386 ((HOST_WIDE_INT) 1 << len) - 1); 5387 else 5388 /* Any other cases we can't handle. */ 5389 return x; 5390 5391 5392 /* If we couldn't do this for some reason, return the original 5393 expression. */ 5394 if (GET_CODE (tem) == CLOBBER) 5395 return x; 5396 5397 return tem; 5398} 5399 5400/* X is a SET which contains an assignment of one object into 5401 a part of another (such as a bit-field assignment, STRICT_LOW_PART, 5402 or certain SUBREGS). If possible, convert it into a series of 5403 logical operations. 5404 5405 We half-heartedly support variable positions, but do not at all 5406 support variable lengths. */ 5407 5408static rtx 5409expand_field_assignment (x) 5410 rtx x; 5411{ 5412 rtx inner; 5413 rtx pos; /* Always counts from low bit. */ 5414 int len; 5415 rtx mask; 5416 enum machine_mode compute_mode; 5417 5418 /* Loop until we find something we can't simplify. */ 5419 while (1) 5420 { 5421 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART 5422 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG) 5423 { 5424 inner = SUBREG_REG (XEXP (SET_DEST (x), 0)); 5425 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))); 5426 pos = GEN_INT (BITS_PER_WORD * SUBREG_WORD (XEXP (SET_DEST (x), 0))); 5427 } 5428 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT 5429 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT) 5430 { 5431 inner = XEXP (SET_DEST (x), 0); 5432 len = INTVAL (XEXP (SET_DEST (x), 1)); 5433 pos = XEXP (SET_DEST (x), 2); 5434 5435 /* If the position is constant and spans the width of INNER, 5436 surround INNER with a USE to indicate this. */ 5437 if (GET_CODE (pos) == CONST_INT 5438 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner))) 5439 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner); 5440 5441 if (BITS_BIG_ENDIAN) 5442 { 5443 if (GET_CODE (pos) == CONST_INT) 5444 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len 5445 - INTVAL (pos)); 5446 else if (GET_CODE (pos) == MINUS 5447 && GET_CODE (XEXP (pos, 1)) == CONST_INT 5448 && (INTVAL (XEXP (pos, 1)) 5449 == GET_MODE_BITSIZE (GET_MODE (inner)) - len)) 5450 /* If position is ADJUST - X, new position is X. */ 5451 pos = XEXP (pos, 0); 5452 else 5453 pos = gen_binary (MINUS, GET_MODE (pos), 5454 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) 5455 - len), 5456 pos); 5457 } 5458 } 5459 5460 /* A SUBREG between two modes that occupy the same numbers of words 5461 can be done by moving the SUBREG to the source. */ 5462 else if (GET_CODE (SET_DEST (x)) == SUBREG 5463 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x))) 5464 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) 5465 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x)))) 5466 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))) 5467 { 5468 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)), 5469 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_DEST (x))), 5470 SET_SRC (x))); 5471 continue; 5472 } 5473 else 5474 break; 5475 5476 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner)) 5477 inner = SUBREG_REG (inner); 5478 5479 compute_mode = GET_MODE (inner); 5480 5481 /* Don't attempt bitwise arithmetic on non-integral modes. */ 5482 if (! INTEGRAL_MODE_P (compute_mode)) 5483 { 5484 enum machine_mode imode; 5485 5486 /* Something is probably seriously wrong if this matches. */ 5487 if (! FLOAT_MODE_P (compute_mode)) 5488 break; 5489 5490 /* Try to find an integral mode to pun with. */ 5491 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0); 5492 if (imode == BLKmode) 5493 break; 5494 5495 compute_mode = imode; 5496 inner = gen_lowpart_for_combine (imode, inner); 5497 } 5498 5499 /* Compute a mask of LEN bits, if we can do this on the host machine. */ 5500 if (len < HOST_BITS_PER_WIDE_INT) 5501 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1); 5502 else 5503 break; 5504 5505 /* Now compute the equivalent expression. Make a copy of INNER 5506 for the SET_DEST in case it is a MEM into which we will substitute; 5507 we don't want shared RTL in that case. */ 5508 x = gen_rtx_SET (VOIDmode, copy_rtx (inner), 5509 gen_binary (IOR, compute_mode, 5510 gen_binary (AND, compute_mode, 5511 gen_unary (NOT, compute_mode, 5512 compute_mode, 5513 gen_binary (ASHIFT, 5514 compute_mode, 5515 mask, pos)), 5516 inner), 5517 gen_binary (ASHIFT, compute_mode, 5518 gen_binary (AND, compute_mode, 5519 gen_lowpart_for_combine 5520 (compute_mode, 5521 SET_SRC (x)), 5522 mask), 5523 pos))); 5524 } 5525 5526 return x; 5527} 5528 5529/* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero, 5530 it is an RTX that represents a variable starting position; otherwise, 5531 POS is the (constant) starting bit position (counted from the LSB). 5532 5533 INNER may be a USE. This will occur when we started with a bitfield 5534 that went outside the boundary of the object in memory, which is 5535 allowed on most machines. To isolate this case, we produce a USE 5536 whose mode is wide enough and surround the MEM with it. The only 5537 code that understands the USE is this routine. If it is not removed, 5538 it will cause the resulting insn not to match. 5539 5540 UNSIGNEDP is non-zero for an unsigned reference and zero for a 5541 signed reference. 5542 5543 IN_DEST is non-zero if this is a reference in the destination of a 5544 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero, 5545 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will 5546 be used. 5547 5548 IN_COMPARE is non-zero if we are in a COMPARE. This means that a 5549 ZERO_EXTRACT should be built even for bits starting at bit 0. 5550 5551 MODE is the desired mode of the result (if IN_DEST == 0). 5552 5553 The result is an RTX for the extraction or NULL_RTX if the target 5554 can't handle it. */ 5555 5556static rtx 5557make_extraction (mode, inner, pos, pos_rtx, len, 5558 unsignedp, in_dest, in_compare) 5559 enum machine_mode mode; 5560 rtx inner; 5561 int pos; 5562 rtx pos_rtx; 5563 int len; 5564 int unsignedp; 5565 int in_dest, in_compare; 5566{ 5567 /* This mode describes the size of the storage area 5568 to fetch the overall value from. Within that, we 5569 ignore the POS lowest bits, etc. */ 5570 enum machine_mode is_mode = GET_MODE (inner); 5571 enum machine_mode inner_mode; 5572 enum machine_mode wanted_inner_mode = byte_mode; 5573 enum machine_mode wanted_inner_reg_mode = word_mode; 5574 enum machine_mode pos_mode = word_mode; 5575 enum machine_mode extraction_mode = word_mode; 5576 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1); 5577 int spans_byte = 0; 5578 rtx new = 0; 5579 rtx orig_pos_rtx = pos_rtx; 5580 int orig_pos; 5581 5582 /* Get some information about INNER and get the innermost object. */ 5583 if (GET_CODE (inner) == USE) 5584 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */ 5585 /* We don't need to adjust the position because we set up the USE 5586 to pretend that it was a full-word object. */ 5587 spans_byte = 1, inner = XEXP (inner, 0); 5588 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner)) 5589 { 5590 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...), 5591 consider just the QI as the memory to extract from. 5592 The subreg adds or removes high bits; its mode is 5593 irrelevant to the meaning of this extraction, 5594 since POS and LEN count from the lsb. */ 5595 if (GET_CODE (SUBREG_REG (inner)) == MEM) 5596 is_mode = GET_MODE (SUBREG_REG (inner)); 5597 inner = SUBREG_REG (inner); 5598 } 5599 5600 inner_mode = GET_MODE (inner); 5601 5602 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT) 5603 pos = INTVAL (pos_rtx), pos_rtx = 0; 5604 5605 /* See if this can be done without an extraction. We never can if the 5606 width of the field is not the same as that of some integer mode. For 5607 registers, we can only avoid the extraction if the position is at the 5608 low-order bit and this is either not in the destination or we have the 5609 appropriate STRICT_LOW_PART operation available. 5610 5611 For MEM, we can avoid an extract if the field starts on an appropriate 5612 boundary and we can change the mode of the memory reference. However, 5613 we cannot directly access the MEM if we have a USE and the underlying 5614 MEM is not TMODE. This combination means that MEM was being used in a 5615 context where bits outside its mode were being referenced; that is only 5616 valid in bit-field insns. */ 5617 5618 if (tmode != BLKmode 5619 && ! (spans_byte && inner_mode != tmode) 5620 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0 5621 && GET_CODE (inner) != MEM 5622 && (! in_dest 5623 || (GET_CODE (inner) == REG 5624 && (movstrict_optab->handlers[(int) tmode].insn_code 5625 != CODE_FOR_nothing)))) 5626 || (GET_CODE (inner) == MEM && pos_rtx == 0 5627 && (pos 5628 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode) 5629 : BITS_PER_UNIT)) == 0 5630 /* We can't do this if we are widening INNER_MODE (it 5631 may not be aligned, for one thing). */ 5632 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode) 5633 && (inner_mode == tmode 5634 || (! mode_dependent_address_p (XEXP (inner, 0)) 5635 && ! MEM_VOLATILE_P (inner)))))) 5636 { 5637 /* If INNER is a MEM, make a new MEM that encompasses just the desired 5638 field. If the original and current mode are the same, we need not 5639 adjust the offset. Otherwise, we do if bytes big endian. 5640 5641 If INNER is not a MEM, get a piece consisting of just the field 5642 of interest (in this case POS % BITS_PER_WORD must be 0). */ 5643 5644 if (GET_CODE (inner) == MEM) 5645 { 5646 int offset; 5647 /* POS counts from lsb, but make OFFSET count in memory order. */ 5648 if (BYTES_BIG_ENDIAN) 5649 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT; 5650 else 5651 offset = pos / BITS_PER_UNIT; 5652 5653 new = gen_rtx_MEM (tmode, plus_constant (XEXP (inner, 0), offset)); 5654 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner); 5655 MEM_COPY_ATTRIBUTES (new, inner); 5656 } 5657 else if (GET_CODE (inner) == REG) 5658 { 5659 /* We can't call gen_lowpart_for_combine here since we always want 5660 a SUBREG and it would sometimes return a new hard register. */ 5661 if (tmode != inner_mode) 5662 new = gen_rtx_SUBREG (tmode, inner, 5663 (WORDS_BIG_ENDIAN 5664 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD 5665 ? (((GET_MODE_SIZE (inner_mode) 5666 - GET_MODE_SIZE (tmode)) 5667 / UNITS_PER_WORD) 5668 - pos / BITS_PER_WORD) 5669 : pos / BITS_PER_WORD)); 5670 else 5671 new = inner; 5672 } 5673 else 5674 new = force_to_mode (inner, tmode, 5675 len >= HOST_BITS_PER_WIDE_INT 5676 ? GET_MODE_MASK (tmode) 5677 : ((HOST_WIDE_INT) 1 << len) - 1, 5678 NULL_RTX, 0); 5679 5680 /* If this extraction is going into the destination of a SET, 5681 make a STRICT_LOW_PART unless we made a MEM. */ 5682 5683 if (in_dest) 5684 return (GET_CODE (new) == MEM ? new 5685 : (GET_CODE (new) != SUBREG 5686 ? gen_rtx_CLOBBER (tmode, const0_rtx) 5687 : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new))); 5688 5689 /* Otherwise, sign- or zero-extend unless we already are in the 5690 proper mode. */ 5691 5692 return (mode == tmode ? new 5693 : gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND, 5694 mode, new)); 5695 } 5696 5697 /* Unless this is a COMPARE or we have a funny memory reference, 5698 don't do anything with zero-extending field extracts starting at 5699 the low-order bit since they are simple AND operations. */ 5700 if (pos_rtx == 0 && pos == 0 && ! in_dest 5701 && ! in_compare && ! spans_byte && unsignedp) 5702 return 0; 5703 5704 /* Unless we are allowed to span bytes, reject this if we would be 5705 spanning bytes or if the position is not a constant and the length 5706 is not 1. In all other cases, we would only be going outside 5707 out object in cases when an original shift would have been 5708 undefined. */ 5709 if (! spans_byte 5710 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode)) 5711 || (pos_rtx != 0 && len != 1))) 5712 return 0; 5713 5714 /* Get the mode to use should INNER not be a MEM, the mode for the position, 5715 and the mode for the result. */ 5716#ifdef HAVE_insv 5717 if (in_dest) 5718 { 5719 wanted_inner_reg_mode 5720 = (insn_operand_mode[(int) CODE_FOR_insv][0] == VOIDmode 5721 ? word_mode 5722 : insn_operand_mode[(int) CODE_FOR_insv][0]); 5723 pos_mode = (insn_operand_mode[(int) CODE_FOR_insv][2] == VOIDmode 5724 ? word_mode : insn_operand_mode[(int) CODE_FOR_insv][2]); 5725 extraction_mode = (insn_operand_mode[(int) CODE_FOR_insv][3] == VOIDmode 5726 ? word_mode 5727 : insn_operand_mode[(int) CODE_FOR_insv][3]); 5728 } 5729#endif 5730 5731#ifdef HAVE_extzv 5732 if (! in_dest && unsignedp) 5733 { 5734 wanted_inner_reg_mode 5735 = (insn_operand_mode[(int) CODE_FOR_extzv][1] == VOIDmode 5736 ? word_mode 5737 : insn_operand_mode[(int) CODE_FOR_extzv][1]); 5738 pos_mode = (insn_operand_mode[(int) CODE_FOR_extzv][3] == VOIDmode 5739 ? word_mode : insn_operand_mode[(int) CODE_FOR_extzv][3]); 5740 extraction_mode = (insn_operand_mode[(int) CODE_FOR_extzv][0] == VOIDmode 5741 ? word_mode 5742 : insn_operand_mode[(int) CODE_FOR_extzv][0]); 5743 } 5744#endif 5745 5746#ifdef HAVE_extv 5747 if (! in_dest && ! unsignedp) 5748 { 5749 wanted_inner_reg_mode 5750 = (insn_operand_mode[(int) CODE_FOR_extv][1] == VOIDmode 5751 ? word_mode 5752 : insn_operand_mode[(int) CODE_FOR_extv][1]); 5753 pos_mode = (insn_operand_mode[(int) CODE_FOR_extv][3] == VOIDmode 5754 ? word_mode : insn_operand_mode[(int) CODE_FOR_extv][3]); 5755 extraction_mode = (insn_operand_mode[(int) CODE_FOR_extv][0] == VOIDmode 5756 ? word_mode 5757 : insn_operand_mode[(int) CODE_FOR_extv][0]); 5758 } 5759#endif 5760 5761 /* Never narrow an object, since that might not be safe. */ 5762 5763 if (mode != VOIDmode 5764 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode)) 5765 extraction_mode = mode; 5766 5767 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode 5768 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx))) 5769 pos_mode = GET_MODE (pos_rtx); 5770 5771 /* If this is not from memory, the desired mode is wanted_inner_reg_mode; 5772 if we have to change the mode of memory and cannot, the desired mode is 5773 EXTRACTION_MODE. */ 5774 if (GET_CODE (inner) != MEM) 5775 wanted_inner_mode = wanted_inner_reg_mode; 5776 else if (inner_mode != wanted_inner_mode 5777 && (mode_dependent_address_p (XEXP (inner, 0)) 5778 || MEM_VOLATILE_P (inner))) 5779 wanted_inner_mode = extraction_mode; 5780 5781 orig_pos = pos; 5782 5783 if (BITS_BIG_ENDIAN) 5784 { 5785 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to 5786 BITS_BIG_ENDIAN style. If position is constant, compute new 5787 position. Otherwise, build subtraction. 5788 Note that POS is relative to the mode of the original argument. 5789 If it's a MEM we need to recompute POS relative to that. 5790 However, if we're extracting from (or inserting into) a register, 5791 we want to recompute POS relative to wanted_inner_mode. */ 5792 int width = (GET_CODE (inner) == MEM 5793 ? GET_MODE_BITSIZE (is_mode) 5794 : GET_MODE_BITSIZE (wanted_inner_mode)); 5795 5796 if (pos_rtx == 0) 5797 pos = width - len - pos; 5798 else 5799 pos_rtx 5800 = gen_rtx_combine (MINUS, GET_MODE (pos_rtx), 5801 GEN_INT (width - len), pos_rtx); 5802 /* POS may be less than 0 now, but we check for that below. 5803 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */ 5804 } 5805 5806 /* If INNER has a wider mode, make it smaller. If this is a constant 5807 extract, try to adjust the byte to point to the byte containing 5808 the value. */ 5809 if (wanted_inner_mode != VOIDmode 5810 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode) 5811 && ((GET_CODE (inner) == MEM 5812 && (inner_mode == wanted_inner_mode 5813 || (! mode_dependent_address_p (XEXP (inner, 0)) 5814 && ! MEM_VOLATILE_P (inner)))))) 5815 { 5816 int offset = 0; 5817 5818 /* The computations below will be correct if the machine is big 5819 endian in both bits and bytes or little endian in bits and bytes. 5820 If it is mixed, we must adjust. */ 5821 5822 /* If bytes are big endian and we had a paradoxical SUBREG, we must 5823 adjust OFFSET to compensate. */ 5824 if (BYTES_BIG_ENDIAN 5825 && ! spans_byte 5826 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode)) 5827 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode); 5828 5829 /* If this is a constant position, we can move to the desired byte. */ 5830 if (pos_rtx == 0) 5831 { 5832 offset += pos / BITS_PER_UNIT; 5833 pos %= GET_MODE_BITSIZE (wanted_inner_mode); 5834 } 5835 5836 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN 5837 && ! spans_byte 5838 && is_mode != wanted_inner_mode) 5839 offset = (GET_MODE_SIZE (is_mode) 5840 - GET_MODE_SIZE (wanted_inner_mode) - offset); 5841 5842 if (offset != 0 || inner_mode != wanted_inner_mode) 5843 { 5844 rtx newmem = gen_rtx_MEM (wanted_inner_mode, 5845 plus_constant (XEXP (inner, 0), offset)); 5846 RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (inner); 5847 MEM_COPY_ATTRIBUTES (newmem, inner); 5848 inner = newmem; 5849 } 5850 } 5851 5852 /* If INNER is not memory, we can always get it into the proper mode. If we 5853 are changing its mode, POS must be a constant and smaller than the size 5854 of the new mode. */ 5855 else if (GET_CODE (inner) != MEM) 5856 { 5857 if (GET_MODE (inner) != wanted_inner_mode 5858 && (pos_rtx != 0 5859 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode))) 5860 return 0; 5861 5862 inner = force_to_mode (inner, wanted_inner_mode, 5863 pos_rtx 5864 || len + orig_pos >= HOST_BITS_PER_WIDE_INT 5865 ? GET_MODE_MASK (wanted_inner_mode) 5866 : (((HOST_WIDE_INT) 1 << len) - 1) << orig_pos, 5867 NULL_RTX, 0); 5868 } 5869 5870 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we 5871 have to zero extend. Otherwise, we can just use a SUBREG. */ 5872 if (pos_rtx != 0 5873 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx))) 5874 pos_rtx = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx); 5875 else if (pos_rtx != 0 5876 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx))) 5877 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx); 5878 5879 /* Make POS_RTX unless we already have it and it is correct. If we don't 5880 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must 5881 be a CONST_INT. */ 5882 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos) 5883 pos_rtx = orig_pos_rtx; 5884 5885 else if (pos_rtx == 0) 5886 pos_rtx = GEN_INT (pos); 5887 5888 /* Make the required operation. See if we can use existing rtx. */ 5889 new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT, 5890 extraction_mode, inner, GEN_INT (len), pos_rtx); 5891 if (! in_dest) 5892 new = gen_lowpart_for_combine (mode, new); 5893 5894 return new; 5895} 5896 5897/* See if X contains an ASHIFT of COUNT or more bits that can be commuted 5898 with any other operations in X. Return X without that shift if so. */ 5899 5900static rtx 5901extract_left_shift (x, count) 5902 rtx x; 5903 int count; 5904{ 5905 enum rtx_code code = GET_CODE (x); 5906 enum machine_mode mode = GET_MODE (x); 5907 rtx tem; 5908 5909 switch (code) 5910 { 5911 case ASHIFT: 5912 /* This is the shift itself. If it is wide enough, we will return 5913 either the value being shifted if the shift count is equal to 5914 COUNT or a shift for the difference. */ 5915 if (GET_CODE (XEXP (x, 1)) == CONST_INT 5916 && INTVAL (XEXP (x, 1)) >= count) 5917 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0), 5918 INTVAL (XEXP (x, 1)) - count); 5919 break; 5920 5921 case NEG: case NOT: 5922 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0) 5923 return gen_unary (code, mode, mode, tem); 5924 5925 break; 5926 5927 case PLUS: case IOR: case XOR: case AND: 5928 /* If we can safely shift this constant and we find the inner shift, 5929 make a new operation. */ 5930 if (GET_CODE (XEXP (x,1)) == CONST_INT 5931 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0 5932 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0) 5933 return gen_binary (code, mode, tem, 5934 GEN_INT (INTVAL (XEXP (x, 1)) >> count)); 5935 5936 break; 5937 5938 default: 5939 break; 5940 } 5941 5942 return 0; 5943} 5944 5945/* Look at the expression rooted at X. Look for expressions 5946 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND. 5947 Form these expressions. 5948 5949 Return the new rtx, usually just X. 5950 5951 Also, for machines like the Vax that don't have logical shift insns, 5952 try to convert logical to arithmetic shift operations in cases where 5953 they are equivalent. This undoes the canonicalizations to logical 5954 shifts done elsewhere. 5955 5956 We try, as much as possible, to re-use rtl expressions to save memory. 5957 5958 IN_CODE says what kind of expression we are processing. Normally, it is 5959 SET. In a memory address (inside a MEM, PLUS or minus, the latter two 5960 being kludges), it is MEM. When processing the arguments of a comparison 5961 or a COMPARE against zero, it is COMPARE. */ 5962 5963static rtx 5964make_compound_operation (x, in_code) 5965 rtx x; 5966 enum rtx_code in_code; 5967{ 5968 enum rtx_code code = GET_CODE (x); 5969 enum machine_mode mode = GET_MODE (x); 5970 int mode_width = GET_MODE_BITSIZE (mode); 5971 rtx rhs, lhs; 5972 enum rtx_code next_code; 5973 int i; 5974 rtx new = 0; 5975 rtx tem; 5976 char *fmt; 5977 5978 /* Select the code to be used in recursive calls. Once we are inside an 5979 address, we stay there. If we have a comparison, set to COMPARE, 5980 but once inside, go back to our default of SET. */ 5981 5982 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM 5983 : ((code == COMPARE || GET_RTX_CLASS (code) == '<') 5984 && XEXP (x, 1) == const0_rtx) ? COMPARE 5985 : in_code == COMPARE ? SET : in_code); 5986 5987 /* Process depending on the code of this operation. If NEW is set 5988 non-zero, it will be returned. */ 5989 5990 switch (code) 5991 { 5992 case ASHIFT: 5993 /* Convert shifts by constants into multiplications if inside 5994 an address. */ 5995 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT 5996 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT 5997 && INTVAL (XEXP (x, 1)) >= 0) 5998 { 5999 new = make_compound_operation (XEXP (x, 0), next_code); 6000 new = gen_rtx_combine (MULT, mode, new, 6001 GEN_INT ((HOST_WIDE_INT) 1 6002 << INTVAL (XEXP (x, 1)))); 6003 } 6004 break; 6005 6006 case AND: 6007 /* If the second operand is not a constant, we can't do anything 6008 with it. */ 6009 if (GET_CODE (XEXP (x, 1)) != CONST_INT) 6010 break; 6011 6012 /* If the constant is a power of two minus one and the first operand 6013 is a logical right shift, make an extraction. */ 6014 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT 6015 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0) 6016 { 6017 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code); 6018 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1, 6019 0, in_code == COMPARE); 6020 } 6021 6022 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */ 6023 else if (GET_CODE (XEXP (x, 0)) == SUBREG 6024 && subreg_lowpart_p (XEXP (x, 0)) 6025 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT 6026 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0) 6027 { 6028 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0), 6029 next_code); 6030 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0, 6031 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1, 6032 0, in_code == COMPARE); 6033 } 6034 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */ 6035 else if ((GET_CODE (XEXP (x, 0)) == XOR 6036 || GET_CODE (XEXP (x, 0)) == IOR) 6037 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT 6038 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT 6039 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0) 6040 { 6041 /* Apply the distributive law, and then try to make extractions. */ 6042 new = gen_rtx_combine (GET_CODE (XEXP (x, 0)), mode, 6043 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0), 6044 XEXP (x, 1)), 6045 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1), 6046 XEXP (x, 1))); 6047 new = make_compound_operation (new, in_code); 6048 } 6049 6050 /* If we are have (and (rotate X C) M) and C is larger than the number 6051 of bits in M, this is an extraction. */ 6052 6053 else if (GET_CODE (XEXP (x, 0)) == ROTATE 6054 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 6055 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0 6056 && i <= INTVAL (XEXP (XEXP (x, 0), 1))) 6057 { 6058 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code); 6059 new = make_extraction (mode, new, 6060 (GET_MODE_BITSIZE (mode) 6061 - INTVAL (XEXP (XEXP (x, 0), 1))), 6062 NULL_RTX, i, 1, 0, in_code == COMPARE); 6063 } 6064 6065 /* On machines without logical shifts, if the operand of the AND is 6066 a logical shift and our mask turns off all the propagated sign 6067 bits, we can replace the logical shift with an arithmetic shift. */ 6068 else if (ashr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing 6069 && (lshr_optab->handlers[(int) mode].insn_code 6070 == CODE_FOR_nothing) 6071 && GET_CODE (XEXP (x, 0)) == LSHIFTRT 6072 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 6073 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0 6074 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT 6075 && mode_width <= HOST_BITS_PER_WIDE_INT) 6076 { 6077 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode); 6078 6079 mask >>= INTVAL (XEXP (XEXP (x, 0), 1)); 6080 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0) 6081 SUBST (XEXP (x, 0), 6082 gen_rtx_combine (ASHIFTRT, mode, 6083 make_compound_operation (XEXP (XEXP (x, 0), 0), 6084 next_code), 6085 XEXP (XEXP (x, 0), 1))); 6086 } 6087 6088 /* If the constant is one less than a power of two, this might be 6089 representable by an extraction even if no shift is present. 6090 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless 6091 we are in a COMPARE. */ 6092 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0) 6093 new = make_extraction (mode, 6094 make_compound_operation (XEXP (x, 0), 6095 next_code), 6096 0, NULL_RTX, i, 1, 0, in_code == COMPARE); 6097 6098 /* If we are in a comparison and this is an AND with a power of two, 6099 convert this into the appropriate bit extract. */ 6100 else if (in_code == COMPARE 6101 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0) 6102 new = make_extraction (mode, 6103 make_compound_operation (XEXP (x, 0), 6104 next_code), 6105 i, NULL_RTX, 1, 1, 0, 1); 6106 6107 break; 6108 6109 case LSHIFTRT: 6110 /* If the sign bit is known to be zero, replace this with an 6111 arithmetic shift. */ 6112 if (ashr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing 6113 && lshr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing 6114 && mode_width <= HOST_BITS_PER_WIDE_INT 6115 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0) 6116 { 6117 new = gen_rtx_combine (ASHIFTRT, mode, 6118 make_compound_operation (XEXP (x, 0), 6119 next_code), 6120 XEXP (x, 1)); 6121 break; 6122 } 6123 6124 /* ... fall through ... */ 6125 6126 case ASHIFTRT: 6127 lhs = XEXP (x, 0); 6128 rhs = XEXP (x, 1); 6129 6130 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1, 6131 this is a SIGN_EXTRACT. */ 6132 if (GET_CODE (rhs) == CONST_INT 6133 && GET_CODE (lhs) == ASHIFT 6134 && GET_CODE (XEXP (lhs, 1)) == CONST_INT 6135 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))) 6136 { 6137 new = make_compound_operation (XEXP (lhs, 0), next_code); 6138 new = make_extraction (mode, new, 6139 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)), 6140 NULL_RTX, mode_width - INTVAL (rhs), 6141 code == LSHIFTRT, 0, in_code == COMPARE); 6142 } 6143 6144 /* See if we have operations between an ASHIFTRT and an ASHIFT. 6145 If so, try to merge the shifts into a SIGN_EXTEND. We could 6146 also do this for some cases of SIGN_EXTRACT, but it doesn't 6147 seem worth the effort; the case checked for occurs on Alpha. */ 6148 6149 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o' 6150 && ! (GET_CODE (lhs) == SUBREG 6151 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o')) 6152 && GET_CODE (rhs) == CONST_INT 6153 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT 6154 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0) 6155 new = make_extraction (mode, make_compound_operation (new, next_code), 6156 0, NULL_RTX, mode_width - INTVAL (rhs), 6157 code == LSHIFTRT, 0, in_code == COMPARE); 6158 6159 break; 6160 6161 case SUBREG: 6162 /* Call ourselves recursively on the inner expression. If we are 6163 narrowing the object and it has a different RTL code from 6164 what it originally did, do this SUBREG as a force_to_mode. */ 6165 6166 tem = make_compound_operation (SUBREG_REG (x), in_code); 6167 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x)) 6168 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem)) 6169 && subreg_lowpart_p (x)) 6170 { 6171 rtx newer = force_to_mode (tem, mode, 6172 GET_MODE_MASK (mode), NULL_RTX, 0); 6173 6174 /* If we have something other than a SUBREG, we might have 6175 done an expansion, so rerun outselves. */ 6176 if (GET_CODE (newer) != SUBREG) 6177 newer = make_compound_operation (newer, in_code); 6178 6179 return newer; 6180 } 6181 6182 /* If this is a paradoxical subreg, and the new code is a sign or 6183 zero extension, omit the subreg and widen the extension. If it 6184 is a regular subreg, we can still get rid of the subreg by not 6185 widening so much, or in fact removing the extension entirely. */ 6186 if ((GET_CODE (tem) == SIGN_EXTEND 6187 || GET_CODE (tem) == ZERO_EXTEND) 6188 && subreg_lowpart_p (x)) 6189 { 6190 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem)) 6191 || (GET_MODE_SIZE (mode) > 6192 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0))))) 6193 tem = gen_rtx_combine (GET_CODE (tem), mode, XEXP (tem, 0)); 6194 else 6195 tem = gen_lowpart_for_combine (mode, XEXP (tem, 0)); 6196 return tem; 6197 } 6198 break; 6199 6200 default: 6201 break; 6202 } 6203 6204 if (new) 6205 { 6206 x = gen_lowpart_for_combine (mode, new); 6207 code = GET_CODE (x); 6208 } 6209 6210 /* Now recursively process each operand of this operation. */ 6211 fmt = GET_RTX_FORMAT (code); 6212 for (i = 0; i < GET_RTX_LENGTH (code); i++) 6213 if (fmt[i] == 'e') 6214 { 6215 new = make_compound_operation (XEXP (x, i), next_code); 6216 SUBST (XEXP (x, i), new); 6217 } 6218 6219 return x; 6220} 6221 6222/* Given M see if it is a value that would select a field of bits 6223 within an item, but not the entire word. Return -1 if not. 6224 Otherwise, return the starting position of the field, where 0 is the 6225 low-order bit. 6226 6227 *PLEN is set to the length of the field. */ 6228 6229static int 6230get_pos_from_mask (m, plen) 6231 unsigned HOST_WIDE_INT m; 6232 int *plen; 6233{ 6234 /* Get the bit number of the first 1 bit from the right, -1 if none. */ 6235 int pos = exact_log2 (m & - m); 6236 6237 if (pos < 0) 6238 return -1; 6239 6240 /* Now shift off the low-order zero bits and see if we have a power of 6241 two minus 1. */ 6242 *plen = exact_log2 ((m >> pos) + 1); 6243 6244 if (*plen <= 0) 6245 return -1; 6246 6247 return pos; 6248} 6249 6250/* See if X can be simplified knowing that we will only refer to it in 6251 MODE and will only refer to those bits that are nonzero in MASK. 6252 If other bits are being computed or if masking operations are done 6253 that select a superset of the bits in MASK, they can sometimes be 6254 ignored. 6255 6256 Return a possibly simplified expression, but always convert X to 6257 MODE. If X is a CONST_INT, AND the CONST_INT with MASK. 6258 6259 Also, if REG is non-zero and X is a register equal in value to REG, 6260 replace X with REG. 6261 6262 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK 6263 are all off in X. This is used when X will be complemented, by either 6264 NOT, NEG, or XOR. */ 6265 6266static rtx 6267force_to_mode (x, mode, mask, reg, just_select) 6268 rtx x; 6269 enum machine_mode mode; 6270 unsigned HOST_WIDE_INT mask; 6271 rtx reg; 6272 int just_select; 6273{ 6274 enum rtx_code code = GET_CODE (x); 6275 int next_select = just_select || code == XOR || code == NOT || code == NEG; 6276 enum machine_mode op_mode; 6277 unsigned HOST_WIDE_INT fuller_mask, nonzero; 6278 rtx op0, op1, temp; 6279 6280 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the 6281 code below will do the wrong thing since the mode of such an 6282 expression is VOIDmode. 6283 6284 Also do nothing if X is a CLOBBER; this can happen if X was 6285 the return value from a call to gen_lowpart_for_combine. */ 6286 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER) 6287 return x; 6288 6289 /* We want to perform the operation is its present mode unless we know 6290 that the operation is valid in MODE, in which case we do the operation 6291 in MODE. */ 6292 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x)) 6293 && code_to_optab[(int) code] != 0 6294 && (code_to_optab[(int) code]->handlers[(int) mode].insn_code 6295 != CODE_FOR_nothing)) 6296 ? mode : GET_MODE (x)); 6297 6298 /* It is not valid to do a right-shift in a narrower mode 6299 than the one it came in with. */ 6300 if ((code == LSHIFTRT || code == ASHIFTRT) 6301 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x))) 6302 op_mode = GET_MODE (x); 6303 6304 /* Truncate MASK to fit OP_MODE. */ 6305 if (op_mode) 6306 mask &= GET_MODE_MASK (op_mode); 6307 6308 /* When we have an arithmetic operation, or a shift whose count we 6309 do not know, we need to assume that all bit the up to the highest-order 6310 bit in MASK will be needed. This is how we form such a mask. */ 6311 if (op_mode) 6312 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT 6313 ? GET_MODE_MASK (op_mode) 6314 : ((HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1)) - 1); 6315 else 6316 fuller_mask = ~ (HOST_WIDE_INT) 0; 6317 6318 /* Determine what bits of X are guaranteed to be (non)zero. */ 6319 nonzero = nonzero_bits (x, mode); 6320 6321 /* If none of the bits in X are needed, return a zero. */ 6322 if (! just_select && (nonzero & mask) == 0) 6323 return const0_rtx; 6324 6325 /* If X is a CONST_INT, return a new one. Do this here since the 6326 test below will fail. */ 6327 if (GET_CODE (x) == CONST_INT) 6328 { 6329 HOST_WIDE_INT cval = INTVAL (x) & mask; 6330 int width = GET_MODE_BITSIZE (mode); 6331 6332 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative 6333 number, sign extend it. */ 6334 if (width > 0 && width < HOST_BITS_PER_WIDE_INT 6335 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0) 6336 cval |= (HOST_WIDE_INT) -1 << width; 6337 6338 return GEN_INT (cval); 6339 } 6340 6341 /* If X is narrower than MODE and we want all the bits in X's mode, just 6342 get X in the proper mode. */ 6343 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode) 6344 && (GET_MODE_MASK (GET_MODE (x)) & ~ mask) == 0) 6345 return gen_lowpart_for_combine (mode, x); 6346 6347 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in 6348 MASK are already known to be zero in X, we need not do anything. */ 6349 if (GET_MODE (x) == mode && code != SUBREG && (~ mask & nonzero) == 0) 6350 return x; 6351 6352 switch (code) 6353 { 6354 case CLOBBER: 6355 /* If X is a (clobber (const_int)), return it since we know we are 6356 generating something that won't match. */ 6357 return x; 6358 6359 case USE: 6360 /* X is a (use (mem ..)) that was made from a bit-field extraction that 6361 spanned the boundary of the MEM. If we are now masking so it is 6362 within that boundary, we don't need the USE any more. */ 6363 if (! BITS_BIG_ENDIAN 6364 && (mask & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) 6365 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select); 6366 break; 6367 6368 case SIGN_EXTEND: 6369 case ZERO_EXTEND: 6370 case ZERO_EXTRACT: 6371 case SIGN_EXTRACT: 6372 x = expand_compound_operation (x); 6373 if (GET_CODE (x) != code) 6374 return force_to_mode (x, mode, mask, reg, next_select); 6375 break; 6376 6377 case REG: 6378 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x) 6379 || rtx_equal_p (reg, get_last_value (x)))) 6380 x = reg; 6381 break; 6382 6383 case SUBREG: 6384 if (subreg_lowpart_p (x) 6385 /* We can ignore the effect of this SUBREG if it narrows the mode or 6386 if the constant masks to zero all the bits the mode doesn't 6387 have. */ 6388 && ((GET_MODE_SIZE (GET_MODE (x)) 6389 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) 6390 || (0 == (mask 6391 & GET_MODE_MASK (GET_MODE (x)) 6392 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x))))))) 6393 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select); 6394 break; 6395 6396 case AND: 6397 /* If this is an AND with a constant, convert it into an AND 6398 whose constant is the AND of that constant with MASK. If it 6399 remains an AND of MASK, delete it since it is redundant. */ 6400 6401 if (GET_CODE (XEXP (x, 1)) == CONST_INT) 6402 { 6403 x = simplify_and_const_int (x, op_mode, XEXP (x, 0), 6404 mask & INTVAL (XEXP (x, 1))); 6405 6406 /* If X is still an AND, see if it is an AND with a mask that 6407 is just some low-order bits. If so, and it is MASK, we don't 6408 need it. */ 6409 6410 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT 6411 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == mask) 6412 x = XEXP (x, 0); 6413 6414 /* If it remains an AND, try making another AND with the bits 6415 in the mode mask that aren't in MASK turned on. If the 6416 constant in the AND is wide enough, this might make a 6417 cheaper constant. */ 6418 6419 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT 6420 && GET_MODE_MASK (GET_MODE (x)) != mask 6421 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT) 6422 { 6423 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1)) 6424 | (GET_MODE_MASK (GET_MODE (x)) & ~ mask)); 6425 int width = GET_MODE_BITSIZE (GET_MODE (x)); 6426 rtx y; 6427 6428 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative 6429 number, sign extend it. */ 6430 if (width > 0 && width < HOST_BITS_PER_WIDE_INT 6431 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0) 6432 cval |= (HOST_WIDE_INT) -1 << width; 6433 6434 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval)); 6435 if (rtx_cost (y, SET) < rtx_cost (x, SET)) 6436 x = y; 6437 } 6438 6439 break; 6440 } 6441 6442 goto binop; 6443 6444 case PLUS: 6445 /* In (and (plus FOO C1) M), if M is a mask that just turns off 6446 low-order bits (as in an alignment operation) and FOO is already 6447 aligned to that boundary, mask C1 to that boundary as well. 6448 This may eliminate that PLUS and, later, the AND. */ 6449 6450 { 6451 int width = GET_MODE_BITSIZE (mode); 6452 unsigned HOST_WIDE_INT smask = mask; 6453 6454 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative 6455 number, sign extend it. */ 6456 6457 if (width < HOST_BITS_PER_WIDE_INT 6458 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0) 6459 smask |= (HOST_WIDE_INT) -1 << width; 6460 6461 if (GET_CODE (XEXP (x, 1)) == CONST_INT 6462 && exact_log2 (- smask) >= 0) 6463 { 6464#ifdef STACK_BIAS 6465 if (STACK_BIAS 6466 && (XEXP (x, 0) == stack_pointer_rtx 6467 || XEXP (x, 0) == frame_pointer_rtx)) 6468 { 6469 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT; 6470 unsigned HOST_WIDE_INT sp_mask = GET_MODE_MASK (mode); 6471 6472 sp_mask &= ~ (sp_alignment - 1); 6473 if ((sp_mask & ~ smask) == 0 6474 && ((INTVAL (XEXP (x, 1)) - STACK_BIAS) & ~ smask) != 0) 6475 return force_to_mode (plus_constant (XEXP (x, 0), 6476 ((INTVAL (XEXP (x, 1)) - 6477 STACK_BIAS) & smask) 6478 + STACK_BIAS), 6479 mode, smask, reg, next_select); 6480 } 6481#endif 6482 if ((nonzero_bits (XEXP (x, 0), mode) & ~ smask) == 0 6483 && (INTVAL (XEXP (x, 1)) & ~ smask) != 0) 6484 return force_to_mode (plus_constant (XEXP (x, 0), 6485 (INTVAL (XEXP (x, 1)) 6486 & smask)), 6487 mode, smask, reg, next_select); 6488 } 6489 } 6490 6491 /* ... fall through ... */ 6492 6493 case MINUS: 6494 case MULT: 6495 /* For PLUS, MINUS and MULT, we need any bits less significant than the 6496 most significant bit in MASK since carries from those bits will 6497 affect the bits we are interested in. */ 6498 mask = fuller_mask; 6499 goto binop; 6500 6501 case IOR: 6502 case XOR: 6503 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and 6504 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...) 6505 operation which may be a bitfield extraction. Ensure that the 6506 constant we form is not wider than the mode of X. */ 6507 6508 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT 6509 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 6510 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0 6511 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT 6512 && GET_CODE (XEXP (x, 1)) == CONST_INT 6513 && ((INTVAL (XEXP (XEXP (x, 0), 1)) 6514 + floor_log2 (INTVAL (XEXP (x, 1)))) 6515 < GET_MODE_BITSIZE (GET_MODE (x))) 6516 && (INTVAL (XEXP (x, 1)) 6517 & ~ nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0) 6518 { 6519 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask) 6520 << INTVAL (XEXP (XEXP (x, 0), 1))); 6521 temp = gen_binary (GET_CODE (x), GET_MODE (x), 6522 XEXP (XEXP (x, 0), 0), temp); 6523 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, 6524 XEXP (XEXP (x, 0), 1)); 6525 return force_to_mode (x, mode, mask, reg, next_select); 6526 } 6527 6528 binop: 6529 /* For most binary operations, just propagate into the operation and 6530 change the mode if we have an operation of that mode. */ 6531 6532 op0 = gen_lowpart_for_combine (op_mode, 6533 force_to_mode (XEXP (x, 0), mode, mask, 6534 reg, next_select)); 6535 op1 = gen_lowpart_for_combine (op_mode, 6536 force_to_mode (XEXP (x, 1), mode, mask, 6537 reg, next_select)); 6538 6539 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside 6540 MASK since OP1 might have been sign-extended but we never want 6541 to turn on extra bits, since combine might have previously relied 6542 on them being off. */ 6543 if (GET_CODE (op1) == CONST_INT && (code == IOR || code == XOR) 6544 && (INTVAL (op1) & mask) != 0) 6545 op1 = GEN_INT (INTVAL (op1) & mask); 6546 6547 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1)) 6548 x = gen_binary (code, op_mode, op0, op1); 6549 break; 6550 6551 case ASHIFT: 6552 /* For left shifts, do the same, but just for the first operand. 6553 However, we cannot do anything with shifts where we cannot 6554 guarantee that the counts are smaller than the size of the mode 6555 because such a count will have a different meaning in a 6556 wider mode. */ 6557 6558 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT 6559 && INTVAL (XEXP (x, 1)) >= 0 6560 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode)) 6561 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode 6562 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1))) 6563 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode)))) 6564 break; 6565 6566 /* If the shift count is a constant and we can do arithmetic in 6567 the mode of the shift, refine which bits we need. Otherwise, use the 6568 conservative form of the mask. */ 6569 if (GET_CODE (XEXP (x, 1)) == CONST_INT 6570 && INTVAL (XEXP (x, 1)) >= 0 6571 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode) 6572 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT) 6573 mask >>= INTVAL (XEXP (x, 1)); 6574 else 6575 mask = fuller_mask; 6576 6577 op0 = gen_lowpart_for_combine (op_mode, 6578 force_to_mode (XEXP (x, 0), op_mode, 6579 mask, reg, next_select)); 6580 6581 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0)) 6582 x = gen_binary (code, op_mode, op0, XEXP (x, 1)); 6583 break; 6584 6585 case LSHIFTRT: 6586 /* Here we can only do something if the shift count is a constant, 6587 this shift constant is valid for the host, and we can do arithmetic 6588 in OP_MODE. */ 6589 6590 if (GET_CODE (XEXP (x, 1)) == CONST_INT 6591 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT 6592 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT) 6593 { 6594 rtx inner = XEXP (x, 0); 6595 6596 /* Select the mask of the bits we need for the shift operand. */ 6597 mask <<= INTVAL (XEXP (x, 1)); 6598 6599 /* We can only change the mode of the shift if we can do arithmetic 6600 in the mode of the shift and MASK is no wider than the width of 6601 OP_MODE. */ 6602 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT 6603 || (mask & ~ GET_MODE_MASK (op_mode)) != 0) 6604 op_mode = GET_MODE (x); 6605 6606 inner = force_to_mode (inner, op_mode, mask, reg, next_select); 6607 6608 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0)) 6609 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1)); 6610 } 6611 6612 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the 6613 shift and AND produces only copies of the sign bit (C2 is one less 6614 than a power of two), we can do this with just a shift. */ 6615 6616 if (GET_CODE (x) == LSHIFTRT 6617 && GET_CODE (XEXP (x, 1)) == CONST_INT 6618 && ((INTVAL (XEXP (x, 1)) 6619 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))) 6620 >= GET_MODE_BITSIZE (GET_MODE (x))) 6621 && exact_log2 (mask + 1) >= 0 6622 && (num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))) 6623 >= exact_log2 (mask + 1))) 6624 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), 6625 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x)) 6626 - exact_log2 (mask + 1))); 6627 break; 6628 6629 case ASHIFTRT: 6630 /* If we are just looking for the sign bit, we don't need this shift at 6631 all, even if it has a variable count. */ 6632 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT 6633 && (mask == ((unsigned HOST_WIDE_INT) 1 6634 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1)))) 6635 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select); 6636 6637 /* If this is a shift by a constant, get a mask that contains those bits 6638 that are not copies of the sign bit. We then have two cases: If 6639 MASK only includes those bits, this can be a logical shift, which may 6640 allow simplifications. If MASK is a single-bit field not within 6641 those bits, we are requesting a copy of the sign bit and hence can 6642 shift the sign bit to the appropriate location. */ 6643 6644 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0 6645 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT) 6646 { 6647 int i = -1; 6648 6649 /* If the considered data is wider then HOST_WIDE_INT, we can't 6650 represent a mask for all its bits in a single scalar. 6651 But we only care about the lower bits, so calculate these. */ 6652 6653 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT) 6654 { 6655 nonzero = ~ (HOST_WIDE_INT) 0; 6656 6657 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1)) 6658 is the number of bits a full-width mask would have set. 6659 We need only shift if these are fewer than nonzero can 6660 hold. If not, we must keep all bits set in nonzero. */ 6661 6662 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1)) 6663 < HOST_BITS_PER_WIDE_INT) 6664 nonzero >>= INTVAL (XEXP (x, 1)) 6665 + HOST_BITS_PER_WIDE_INT 6666 - GET_MODE_BITSIZE (GET_MODE (x)) ; 6667 } 6668 else 6669 { 6670 nonzero = GET_MODE_MASK (GET_MODE (x)); 6671 nonzero >>= INTVAL (XEXP (x, 1)); 6672 } 6673 6674 if ((mask & ~ nonzero) == 0 6675 || (i = exact_log2 (mask)) >= 0) 6676 { 6677 x = simplify_shift_const 6678 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0), 6679 i < 0 ? INTVAL (XEXP (x, 1)) 6680 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i); 6681 6682 if (GET_CODE (x) != ASHIFTRT) 6683 return force_to_mode (x, mode, mask, reg, next_select); 6684 } 6685 } 6686 6687 /* If MASK is 1, convert this to a LSHIFTRT. This can be done 6688 even if the shift count isn't a constant. */ 6689 if (mask == 1) 6690 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1)); 6691 6692 /* If this is a sign-extension operation that just affects bits 6693 we don't care about, remove it. Be sure the call above returned 6694 something that is still a shift. */ 6695 6696 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT) 6697 && GET_CODE (XEXP (x, 1)) == CONST_INT 6698 && INTVAL (XEXP (x, 1)) >= 0 6699 && (INTVAL (XEXP (x, 1)) 6700 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1)) 6701 && GET_CODE (XEXP (x, 0)) == ASHIFT 6702 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 6703 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1))) 6704 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask, 6705 reg, next_select); 6706 6707 break; 6708 6709 case ROTATE: 6710 case ROTATERT: 6711 /* If the shift count is constant and we can do computations 6712 in the mode of X, compute where the bits we care about are. 6713 Otherwise, we can't do anything. Don't change the mode of 6714 the shift or propagate MODE into the shift, though. */ 6715 if (GET_CODE (XEXP (x, 1)) == CONST_INT 6716 && INTVAL (XEXP (x, 1)) >= 0) 6717 { 6718 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE, 6719 GET_MODE (x), GEN_INT (mask), 6720 XEXP (x, 1)); 6721 if (temp && GET_CODE(temp) == CONST_INT) 6722 SUBST (XEXP (x, 0), 6723 force_to_mode (XEXP (x, 0), GET_MODE (x), 6724 INTVAL (temp), reg, next_select)); 6725 } 6726 break; 6727 6728 case NEG: 6729 /* If we just want the low-order bit, the NEG isn't needed since it 6730 won't change the low-order bit. */ 6731 if (mask == 1) 6732 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select); 6733 6734 /* We need any bits less significant than the most significant bit in 6735 MASK since carries from those bits will affect the bits we are 6736 interested in. */ 6737 mask = fuller_mask; 6738 goto unop; 6739 6740 case NOT: 6741 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the 6742 same as the XOR case above. Ensure that the constant we form is not 6743 wider than the mode of X. */ 6744 6745 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT 6746 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 6747 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0 6748 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask) 6749 < GET_MODE_BITSIZE (GET_MODE (x))) 6750 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT) 6751 { 6752 temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1))); 6753 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp); 6754 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1)); 6755 6756 return force_to_mode (x, mode, mask, reg, next_select); 6757 } 6758 6759 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must 6760 use the full mask inside the NOT. */ 6761 mask = fuller_mask; 6762 6763 unop: 6764 op0 = gen_lowpart_for_combine (op_mode, 6765 force_to_mode (XEXP (x, 0), mode, mask, 6766 reg, next_select)); 6767 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0)) 6768 x = gen_unary (code, op_mode, op_mode, op0); 6769 break; 6770 6771 case NE: 6772 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included 6773 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero, 6774 which is equal to STORE_FLAG_VALUE. */ 6775 if ((mask & ~ STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx 6776 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0 6777 && nonzero_bits (XEXP (x, 0), mode) == STORE_FLAG_VALUE) 6778 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select); 6779 6780 break; 6781 6782 case IF_THEN_ELSE: 6783 /* We have no way of knowing if the IF_THEN_ELSE can itself be 6784 written in a narrower mode. We play it safe and do not do so. */ 6785 6786 SUBST (XEXP (x, 1), 6787 gen_lowpart_for_combine (GET_MODE (x), 6788 force_to_mode (XEXP (x, 1), mode, 6789 mask, reg, next_select))); 6790 SUBST (XEXP (x, 2), 6791 gen_lowpart_for_combine (GET_MODE (x), 6792 force_to_mode (XEXP (x, 2), mode, 6793 mask, reg,next_select))); 6794 break; 6795 6796 default: 6797 break; 6798 } 6799 6800 /* Ensure we return a value of the proper mode. */ 6801 return gen_lowpart_for_combine (mode, x); 6802} 6803 6804/* Return nonzero if X is an expression that has one of two values depending on 6805 whether some other value is zero or nonzero. In that case, we return the 6806 value that is being tested, *PTRUE is set to the value if the rtx being 6807 returned has a nonzero value, and *PFALSE is set to the other alternative. 6808 6809 If we return zero, we set *PTRUE and *PFALSE to X. */ 6810 6811static rtx 6812if_then_else_cond (x, ptrue, pfalse) 6813 rtx x; 6814 rtx *ptrue, *pfalse; 6815{ 6816 enum machine_mode mode = GET_MODE (x); 6817 enum rtx_code code = GET_CODE (x); 6818 int size = GET_MODE_BITSIZE (mode); 6819 rtx cond0, cond1, true0, true1, false0, false1; 6820 unsigned HOST_WIDE_INT nz; 6821 6822 /* If this is a unary operation whose operand has one of two values, apply 6823 our opcode to compute those values. */ 6824 if (GET_RTX_CLASS (code) == '1' 6825 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0) 6826 { 6827 *ptrue = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), true0); 6828 *pfalse = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), false0); 6829 return cond0; 6830 } 6831 6832 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would 6833 make can't possibly match and would suppress other optimizations. */ 6834 else if (code == COMPARE) 6835 ; 6836 6837 /* If this is a binary operation, see if either side has only one of two 6838 values. If either one does or if both do and they are conditional on 6839 the same value, compute the new true and false values. */ 6840 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2' 6841 || GET_RTX_CLASS (code) == '<') 6842 { 6843 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0); 6844 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1); 6845 6846 if ((cond0 != 0 || cond1 != 0) 6847 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1))) 6848 { 6849 /* If if_then_else_cond returned zero, then true/false are the 6850 same rtl. We must copy one of them to prevent invalid rtl 6851 sharing. */ 6852 if (cond0 == 0) 6853 true0 = copy_rtx (true0); 6854 else if (cond1 == 0) 6855 true1 = copy_rtx (true1); 6856 6857 *ptrue = gen_binary (code, mode, true0, true1); 6858 *pfalse = gen_binary (code, mode, false0, false1); 6859 return cond0 ? cond0 : cond1; 6860 } 6861 6862 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the 6863 operands is zero when the other is non-zero, and vice-versa, 6864 and STORE_FLAG_VALUE is 1 or -1. */ 6865 6866 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) 6867 && (code == PLUS || code == IOR || code == XOR || code == MINUS 6868 || code == UMAX) 6869 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT) 6870 { 6871 rtx op0 = XEXP (XEXP (x, 0), 1); 6872 rtx op1 = XEXP (XEXP (x, 1), 1); 6873 6874 cond0 = XEXP (XEXP (x, 0), 0); 6875 cond1 = XEXP (XEXP (x, 1), 0); 6876 6877 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<' 6878 && GET_RTX_CLASS (GET_CODE (cond1)) == '<' 6879 && reversible_comparison_p (cond1) 6880 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1)) 6881 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0)) 6882 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1))) 6883 || ((swap_condition (GET_CODE (cond0)) 6884 == reverse_condition (GET_CODE (cond1))) 6885 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1)) 6886 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0)))) 6887 && ! side_effects_p (x)) 6888 { 6889 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx); 6890 *pfalse = gen_binary (MULT, mode, 6891 (code == MINUS 6892 ? gen_unary (NEG, mode, mode, op1) : op1), 6893 const_true_rtx); 6894 return cond0; 6895 } 6896 } 6897 6898 /* Similarly for MULT, AND and UMIN, execpt that for these the result 6899 is always zero. */ 6900 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) 6901 && (code == MULT || code == AND || code == UMIN) 6902 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT) 6903 { 6904 cond0 = XEXP (XEXP (x, 0), 0); 6905 cond1 = XEXP (XEXP (x, 1), 0); 6906 6907 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<' 6908 && GET_RTX_CLASS (GET_CODE (cond1)) == '<' 6909 && reversible_comparison_p (cond1) 6910 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1)) 6911 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0)) 6912 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1))) 6913 || ((swap_condition (GET_CODE (cond0)) 6914 == reverse_condition (GET_CODE (cond1))) 6915 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1)) 6916 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0)))) 6917 && ! side_effects_p (x)) 6918 { 6919 *ptrue = *pfalse = const0_rtx; 6920 return cond0; 6921 } 6922 } 6923 } 6924 6925 else if (code == IF_THEN_ELSE) 6926 { 6927 /* If we have IF_THEN_ELSE already, extract the condition and 6928 canonicalize it if it is NE or EQ. */ 6929 cond0 = XEXP (x, 0); 6930 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2); 6931 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx) 6932 return XEXP (cond0, 0); 6933 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx) 6934 { 6935 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1); 6936 return XEXP (cond0, 0); 6937 } 6938 else 6939 return cond0; 6940 } 6941 6942 /* If X is a normal SUBREG with both inner and outer modes integral, 6943 we can narrow both the true and false values of the inner expression, 6944 if there is a condition. */ 6945 else if (code == SUBREG && GET_MODE_CLASS (mode) == MODE_INT 6946 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_INT 6947 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) 6948 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x), 6949 &true0, &false0))) 6950 { 6951 *ptrue = force_to_mode (true0, mode, GET_MODE_MASK (mode), NULL_RTX, 0); 6952 *pfalse 6953 = force_to_mode (false0, mode, GET_MODE_MASK (mode), NULL_RTX, 0); 6954 6955 return cond0; 6956 } 6957 6958 /* If X is a constant, this isn't special and will cause confusions 6959 if we treat it as such. Likewise if it is equivalent to a constant. */ 6960 else if (CONSTANT_P (x) 6961 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0))) 6962 ; 6963 6964 /* If X is known to be either 0 or -1, those are the true and 6965 false values when testing X. */ 6966 else if (num_sign_bit_copies (x, mode) == size) 6967 { 6968 *ptrue = constm1_rtx, *pfalse = const0_rtx; 6969 return x; 6970 } 6971 6972 /* Likewise for 0 or a single bit. */ 6973 else if (exact_log2 (nz = nonzero_bits (x, mode)) >= 0) 6974 { 6975 *ptrue = GEN_INT (nz), *pfalse = const0_rtx; 6976 return x; 6977 } 6978 6979 /* Otherwise fail; show no condition with true and false values the same. */ 6980 *ptrue = *pfalse = x; 6981 return 0; 6982} 6983 6984/* Return the value of expression X given the fact that condition COND 6985 is known to be true when applied to REG as its first operand and VAL 6986 as its second. X is known to not be shared and so can be modified in 6987 place. 6988 6989 We only handle the simplest cases, and specifically those cases that 6990 arise with IF_THEN_ELSE expressions. */ 6991 6992static rtx 6993known_cond (x, cond, reg, val) 6994 rtx x; 6995 enum rtx_code cond; 6996 rtx reg, val; 6997{ 6998 enum rtx_code code = GET_CODE (x); 6999 rtx temp; 7000 char *fmt; 7001 int i, j; 7002 7003 if (side_effects_p (x)) 7004 return x; 7005 7006 if (cond == EQ && rtx_equal_p (x, reg)) 7007 return val; 7008 7009 /* If X is (abs REG) and we know something about REG's relationship 7010 with zero, we may be able to simplify this. */ 7011 7012 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx) 7013 switch (cond) 7014 { 7015 case GE: case GT: case EQ: 7016 return XEXP (x, 0); 7017 case LT: case LE: 7018 return gen_unary (NEG, GET_MODE (XEXP (x, 0)), GET_MODE (XEXP (x, 0)), 7019 XEXP (x, 0)); 7020 default: 7021 break; 7022 } 7023 7024 /* The only other cases we handle are MIN, MAX, and comparisons if the 7025 operands are the same as REG and VAL. */ 7026 7027 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c') 7028 { 7029 if (rtx_equal_p (XEXP (x, 0), val)) 7030 cond = swap_condition (cond), temp = val, val = reg, reg = temp; 7031 7032 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val)) 7033 { 7034 if (GET_RTX_CLASS (code) == '<') 7035 return (comparison_dominates_p (cond, code) ? const_true_rtx 7036 : (comparison_dominates_p (cond, 7037 reverse_condition (code)) 7038 ? const0_rtx : x)); 7039 7040 else if (code == SMAX || code == SMIN 7041 || code == UMIN || code == UMAX) 7042 { 7043 int unsignedp = (code == UMIN || code == UMAX); 7044 7045 if (code == SMAX || code == UMAX) 7046 cond = reverse_condition (cond); 7047 7048 switch (cond) 7049 { 7050 case GE: case GT: 7051 return unsignedp ? x : XEXP (x, 1); 7052 case LE: case LT: 7053 return unsignedp ? x : XEXP (x, 0); 7054 case GEU: case GTU: 7055 return unsignedp ? XEXP (x, 1) : x; 7056 case LEU: case LTU: 7057 return unsignedp ? XEXP (x, 0) : x; 7058 default: 7059 break; 7060 } 7061 } 7062 } 7063 } 7064 7065 fmt = GET_RTX_FORMAT (code); 7066 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 7067 { 7068 if (fmt[i] == 'e') 7069 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val)); 7070 else if (fmt[i] == 'E') 7071 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 7072 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j), 7073 cond, reg, val)); 7074 } 7075 7076 return x; 7077} 7078 7079/* See if X and Y are equal for the purposes of seeing if we can rewrite an 7080 assignment as a field assignment. */ 7081 7082static int 7083rtx_equal_for_field_assignment_p (x, y) 7084 rtx x; 7085 rtx y; 7086{ 7087 if (x == y || rtx_equal_p (x, y)) 7088 return 1; 7089 7090 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y)) 7091 return 0; 7092 7093 /* Check for a paradoxical SUBREG of a MEM compared with the MEM. 7094 Note that all SUBREGs of MEM are paradoxical; otherwise they 7095 would have been rewritten. */ 7096 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG 7097 && GET_CODE (SUBREG_REG (y)) == MEM 7098 && rtx_equal_p (SUBREG_REG (y), 7099 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x))) 7100 return 1; 7101 7102 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG 7103 && GET_CODE (SUBREG_REG (x)) == MEM 7104 && rtx_equal_p (SUBREG_REG (x), 7105 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y))) 7106 return 1; 7107 7108 /* We used to see if get_last_value of X and Y were the same but that's 7109 not correct. In one direction, we'll cause the assignment to have 7110 the wrong destination and in the case, we'll import a register into this 7111 insn that might have already have been dead. So fail if none of the 7112 above cases are true. */ 7113 return 0; 7114} 7115 7116/* See if X, a SET operation, can be rewritten as a bit-field assignment. 7117 Return that assignment if so. 7118 7119 We only handle the most common cases. */ 7120 7121static rtx 7122make_field_assignment (x) 7123 rtx x; 7124{ 7125 rtx dest = SET_DEST (x); 7126 rtx src = SET_SRC (x); 7127 rtx assign; 7128 rtx rhs, lhs; 7129 HOST_WIDE_INT c1; 7130 int pos, len; 7131 rtx other; 7132 enum machine_mode mode; 7133 7134 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is 7135 a clear of a one-bit field. We will have changed it to 7136 (and (rotate (const_int -2) POS) DEST), so check for that. Also check 7137 for a SUBREG. */ 7138 7139 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE 7140 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT 7141 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2 7142 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1))) 7143 { 7144 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1), 7145 1, 1, 1, 0); 7146 if (assign != 0) 7147 return gen_rtx_SET (VOIDmode, assign, const0_rtx); 7148 return x; 7149 } 7150 7151 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG 7152 && subreg_lowpart_p (XEXP (src, 0)) 7153 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0))) 7154 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0))))) 7155 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE 7156 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2 7157 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1))) 7158 { 7159 assign = make_extraction (VOIDmode, dest, 0, 7160 XEXP (SUBREG_REG (XEXP (src, 0)), 1), 7161 1, 1, 1, 0); 7162 if (assign != 0) 7163 return gen_rtx_SET (VOIDmode, assign, const0_rtx); 7164 return x; 7165 } 7166 7167 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a 7168 one-bit field. */ 7169 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT 7170 && XEXP (XEXP (src, 0), 0) == const1_rtx 7171 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1))) 7172 { 7173 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1), 7174 1, 1, 1, 0); 7175 if (assign != 0) 7176 return gen_rtx_SET (VOIDmode, assign, const1_rtx); 7177 return x; 7178 } 7179 7180 /* The other case we handle is assignments into a constant-position 7181 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents 7182 a mask that has all one bits except for a group of zero bits and 7183 OTHER is known to have zeros where C1 has ones, this is such an 7184 assignment. Compute the position and length from C1. Shift OTHER 7185 to the appropriate position, force it to the required mode, and 7186 make the extraction. Check for the AND in both operands. */ 7187 7188 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR) 7189 return x; 7190 7191 rhs = expand_compound_operation (XEXP (src, 0)); 7192 lhs = expand_compound_operation (XEXP (src, 1)); 7193 7194 if (GET_CODE (rhs) == AND 7195 && GET_CODE (XEXP (rhs, 1)) == CONST_INT 7196 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest)) 7197 c1 = INTVAL (XEXP (rhs, 1)), other = lhs; 7198 else if (GET_CODE (lhs) == AND 7199 && GET_CODE (XEXP (lhs, 1)) == CONST_INT 7200 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest)) 7201 c1 = INTVAL (XEXP (lhs, 1)), other = rhs; 7202 else 7203 return x; 7204 7205 pos = get_pos_from_mask ((~ c1) & GET_MODE_MASK (GET_MODE (dest)), &len); 7206 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest)) 7207 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT 7208 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0) 7209 return x; 7210 7211 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0); 7212 if (assign == 0) 7213 return x; 7214 7215 /* The mode to use for the source is the mode of the assignment, or of 7216 what is inside a possible STRICT_LOW_PART. */ 7217 mode = (GET_CODE (assign) == STRICT_LOW_PART 7218 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign)); 7219 7220 /* Shift OTHER right POS places and make it the source, restricting it 7221 to the proper length and mode. */ 7222 7223 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT, 7224 GET_MODE (src), other, pos), 7225 mode, 7226 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT 7227 ? GET_MODE_MASK (mode) 7228 : ((HOST_WIDE_INT) 1 << len) - 1, 7229 dest, 0); 7230 7231 return gen_rtx_combine (SET, VOIDmode, assign, src); 7232} 7233 7234/* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c) 7235 if so. */ 7236 7237static rtx 7238apply_distributive_law (x) 7239 rtx x; 7240{ 7241 enum rtx_code code = GET_CODE (x); 7242 rtx lhs, rhs, other; 7243 rtx tem; 7244 enum rtx_code inner_code; 7245 7246 /* Distributivity is not true for floating point. 7247 It can change the value. So don't do it. 7248 -- rms and moshier@world.std.com. */ 7249 if (FLOAT_MODE_P (GET_MODE (x))) 7250 return x; 7251 7252 /* The outer operation can only be one of the following: */ 7253 if (code != IOR && code != AND && code != XOR 7254 && code != PLUS && code != MINUS) 7255 return x; 7256 7257 lhs = XEXP (x, 0), rhs = XEXP (x, 1); 7258 7259 /* If either operand is a primitive we can't do anything, so get out 7260 fast. */ 7261 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o' 7262 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o') 7263 return x; 7264 7265 lhs = expand_compound_operation (lhs); 7266 rhs = expand_compound_operation (rhs); 7267 inner_code = GET_CODE (lhs); 7268 if (inner_code != GET_CODE (rhs)) 7269 return x; 7270 7271 /* See if the inner and outer operations distribute. */ 7272 switch (inner_code) 7273 { 7274 case LSHIFTRT: 7275 case ASHIFTRT: 7276 case AND: 7277 case IOR: 7278 /* These all distribute except over PLUS. */ 7279 if (code == PLUS || code == MINUS) 7280 return x; 7281 break; 7282 7283 case MULT: 7284 if (code != PLUS && code != MINUS) 7285 return x; 7286 break; 7287 7288 case ASHIFT: 7289 /* This is also a multiply, so it distributes over everything. */ 7290 break; 7291 7292 case SUBREG: 7293 /* Non-paradoxical SUBREGs distributes over all operations, provided 7294 the inner modes and word numbers are the same, this is an extraction 7295 of a low-order part, we don't convert an fp operation to int or 7296 vice versa, and we would not be converting a single-word 7297 operation into a multi-word operation. The latter test is not 7298 required, but it prevents generating unneeded multi-word operations. 7299 Some of the previous tests are redundant given the latter test, but 7300 are retained because they are required for correctness. 7301 7302 We produce the result slightly differently in this case. */ 7303 7304 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs)) 7305 || SUBREG_WORD (lhs) != SUBREG_WORD (rhs) 7306 || ! subreg_lowpart_p (lhs) 7307 || (GET_MODE_CLASS (GET_MODE (lhs)) 7308 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs)))) 7309 || (GET_MODE_SIZE (GET_MODE (lhs)) 7310 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs)))) 7311 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD) 7312 return x; 7313 7314 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)), 7315 SUBREG_REG (lhs), SUBREG_REG (rhs)); 7316 return gen_lowpart_for_combine (GET_MODE (x), tem); 7317 7318 default: 7319 return x; 7320 } 7321 7322 /* Set LHS and RHS to the inner operands (A and B in the example 7323 above) and set OTHER to the common operand (C in the example). 7324 These is only one way to do this unless the inner operation is 7325 commutative. */ 7326 if (GET_RTX_CLASS (inner_code) == 'c' 7327 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0))) 7328 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1); 7329 else if (GET_RTX_CLASS (inner_code) == 'c' 7330 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1))) 7331 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0); 7332 else if (GET_RTX_CLASS (inner_code) == 'c' 7333 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0))) 7334 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1); 7335 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1))) 7336 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0); 7337 else 7338 return x; 7339 7340 /* Form the new inner operation, seeing if it simplifies first. */ 7341 tem = gen_binary (code, GET_MODE (x), lhs, rhs); 7342 7343 /* There is one exception to the general way of distributing: 7344 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */ 7345 if (code == XOR && inner_code == IOR) 7346 { 7347 inner_code = AND; 7348 other = gen_unary (NOT, GET_MODE (x), GET_MODE (x), other); 7349 } 7350 7351 /* We may be able to continuing distributing the result, so call 7352 ourselves recursively on the inner operation before forming the 7353 outer operation, which we return. */ 7354 return gen_binary (inner_code, GET_MODE (x), 7355 apply_distributive_law (tem), other); 7356} 7357 7358/* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done 7359 in MODE. 7360 7361 Return an equivalent form, if different from X. Otherwise, return X. If 7362 X is zero, we are to always construct the equivalent form. */ 7363 7364static rtx 7365simplify_and_const_int (x, mode, varop, constop) 7366 rtx x; 7367 enum machine_mode mode; 7368 rtx varop; 7369 unsigned HOST_WIDE_INT constop; 7370{ 7371 unsigned HOST_WIDE_INT nonzero; 7372 int width = GET_MODE_BITSIZE (mode); 7373 int i; 7374 7375 /* Simplify VAROP knowing that we will be only looking at some of the 7376 bits in it. */ 7377 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0); 7378 7379 /* If VAROP is a CLOBBER, we will fail so return it; if it is a 7380 CONST_INT, we are done. */ 7381 if (GET_CODE (varop) == CLOBBER || GET_CODE (varop) == CONST_INT) 7382 return varop; 7383 7384 /* See what bits may be nonzero in VAROP. Unlike the general case of 7385 a call to nonzero_bits, here we don't care about bits outside 7386 MODE. */ 7387 7388 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode); 7389 7390 /* If this would be an entire word for the target, but is not for 7391 the host, then sign-extend on the host so that the number will look 7392 the same way on the host that it would on the target. 7393 7394 For example, when building a 64 bit alpha hosted 32 bit sparc 7395 targeted compiler, then we want the 32 bit unsigned value -1 to be 7396 represented as a 64 bit value -1, and not as 0x00000000ffffffff. 7397 The later confuses the sparc backend. */ 7398 7399 if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width 7400 && (nonzero & ((HOST_WIDE_INT) 1 << (width - 1)))) 7401 nonzero |= ((HOST_WIDE_INT) (-1) << width); 7402 7403 /* Turn off all bits in the constant that are known to already be zero. 7404 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS 7405 which is tested below. */ 7406 7407 constop &= nonzero; 7408 7409 /* If we don't have any bits left, return zero. */ 7410 if (constop == 0) 7411 return const0_rtx; 7412 7413 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is 7414 a power of two, we can replace this with a ASHIFT. */ 7415 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1 7416 && (i = exact_log2 (constop)) >= 0) 7417 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i); 7418 7419 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR 7420 or XOR, then try to apply the distributive law. This may eliminate 7421 operations if either branch can be simplified because of the AND. 7422 It may also make some cases more complex, but those cases probably 7423 won't match a pattern either with or without this. */ 7424 7425 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR) 7426 return 7427 gen_lowpart_for_combine 7428 (mode, 7429 apply_distributive_law 7430 (gen_binary (GET_CODE (varop), GET_MODE (varop), 7431 simplify_and_const_int (NULL_RTX, GET_MODE (varop), 7432 XEXP (varop, 0), constop), 7433 simplify_and_const_int (NULL_RTX, GET_MODE (varop), 7434 XEXP (varop, 1), constop)))); 7435 7436 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG 7437 if we already had one (just check for the simplest cases). */ 7438 if (x && GET_CODE (XEXP (x, 0)) == SUBREG 7439 && GET_MODE (XEXP (x, 0)) == mode 7440 && SUBREG_REG (XEXP (x, 0)) == varop) 7441 varop = XEXP (x, 0); 7442 else 7443 varop = gen_lowpart_for_combine (mode, varop); 7444 7445 /* If we can't make the SUBREG, try to return what we were given. */ 7446 if (GET_CODE (varop) == CLOBBER) 7447 return x ? x : varop; 7448 7449 /* If we are only masking insignificant bits, return VAROP. */ 7450 if (constop == nonzero) 7451 x = varop; 7452 7453 /* Otherwise, return an AND. See how much, if any, of X we can use. */ 7454 else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode) 7455 x = gen_binary (AND, mode, varop, GEN_INT (constop)); 7456 7457 else 7458 { 7459 if (GET_CODE (XEXP (x, 1)) != CONST_INT 7460 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop) 7461 SUBST (XEXP (x, 1), GEN_INT (constop)); 7462 7463 SUBST (XEXP (x, 0), varop); 7464 } 7465 7466 return x; 7467} 7468 7469/* We let num_sign_bit_copies recur into nonzero_bits as that is useful. 7470 We don't let nonzero_bits recur into num_sign_bit_copies, because that 7471 is less useful. We can't allow both, because that results in exponential 7472 run time recursion. There is a nullstone testcase that triggered 7473 this. This macro avoids accidental uses of num_sign_bit_copies. */ 7474#define num_sign_bit_copies() 7475 7476/* Given an expression, X, compute which bits in X can be non-zero. 7477 We don't care about bits outside of those defined in MODE. 7478 7479 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is 7480 a shift, AND, or zero_extract, we can do better. */ 7481 7482static unsigned HOST_WIDE_INT 7483nonzero_bits (x, mode) 7484 rtx x; 7485 enum machine_mode mode; 7486{ 7487 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode); 7488 unsigned HOST_WIDE_INT inner_nz; 7489 enum rtx_code code; 7490 int mode_width = GET_MODE_BITSIZE (mode); 7491 rtx tem; 7492 7493 /* For floating-point values, assume all bits are needed. */ 7494 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode)) 7495 return nonzero; 7496 7497 /* If X is wider than MODE, use its mode instead. */ 7498 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width) 7499 { 7500 mode = GET_MODE (x); 7501 nonzero = GET_MODE_MASK (mode); 7502 mode_width = GET_MODE_BITSIZE (mode); 7503 } 7504 7505 if (mode_width > HOST_BITS_PER_WIDE_INT) 7506 /* Our only callers in this case look for single bit values. So 7507 just return the mode mask. Those tests will then be false. */ 7508 return nonzero; 7509 7510#ifndef WORD_REGISTER_OPERATIONS 7511 /* If MODE is wider than X, but both are a single word for both the host 7512 and target machines, we can compute this from which bits of the 7513 object might be nonzero in its own mode, taking into account the fact 7514 that on many CISC machines, accessing an object in a wider mode 7515 causes the high-order bits to become undefined. So they are 7516 not known to be zero. */ 7517 7518 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode 7519 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD 7520 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT 7521 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x))) 7522 { 7523 nonzero &= nonzero_bits (x, GET_MODE (x)); 7524 nonzero |= GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)); 7525 return nonzero; 7526 } 7527#endif 7528 7529 code = GET_CODE (x); 7530 switch (code) 7531 { 7532 case REG: 7533#ifdef POINTERS_EXTEND_UNSIGNED 7534 /* If pointers extend unsigned and this is a pointer in Pmode, say that 7535 all the bits above ptr_mode are known to be zero. */ 7536 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode 7537 && REGNO_POINTER_FLAG (REGNO (x))) 7538 nonzero &= GET_MODE_MASK (ptr_mode); 7539#endif 7540 7541#ifdef STACK_BOUNDARY 7542 /* If this is the stack pointer, we may know something about its 7543 alignment. If PUSH_ROUNDING is defined, it is possible for the 7544 stack to be momentarily aligned only to that amount, so we pick 7545 the least alignment. */ 7546 7547 /* We can't check for arg_pointer_rtx here, because it is not 7548 guaranteed to have as much alignment as the stack pointer. 7549 In particular, in the Irix6 n64 ABI, the stack has 128 bit 7550 alignment but the argument pointer has only 64 bit alignment. */ 7551 7552 if ((x == frame_pointer_rtx 7553 || x == stack_pointer_rtx 7554 || x == hard_frame_pointer_rtx 7555 || (REGNO (x) >= FIRST_VIRTUAL_REGISTER 7556 && REGNO (x) <= LAST_VIRTUAL_REGISTER)) 7557#ifdef STACK_BIAS 7558 && !STACK_BIAS 7559#endif 7560 ) 7561 { 7562 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT; 7563 7564#ifdef PUSH_ROUNDING 7565 if (REGNO (x) == STACK_POINTER_REGNUM) 7566 sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment); 7567#endif 7568 7569 /* We must return here, otherwise we may get a worse result from 7570 one of the choices below. There is nothing useful below as 7571 far as the stack pointer is concerned. */ 7572 return nonzero &= ~ (sp_alignment - 1); 7573 } 7574#endif 7575 7576 /* If X is a register whose nonzero bits value is current, use it. 7577 Otherwise, if X is a register whose value we can find, use that 7578 value. Otherwise, use the previously-computed global nonzero bits 7579 for this register. */ 7580 7581 if (reg_last_set_value[REGNO (x)] != 0 7582 && reg_last_set_mode[REGNO (x)] == mode 7583 && (reg_last_set_label[REGNO (x)] == label_tick 7584 || (REGNO (x) >= FIRST_PSEUDO_REGISTER 7585 && REG_N_SETS (REGNO (x)) == 1 7586 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, 7587 REGNO (x)))) 7588 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid) 7589 return reg_last_set_nonzero_bits[REGNO (x)]; 7590 7591 tem = get_last_value (x); 7592 7593 if (tem) 7594 { 7595#ifdef SHORT_IMMEDIATES_SIGN_EXTEND 7596 /* If X is narrower than MODE and TEM is a non-negative 7597 constant that would appear negative in the mode of X, 7598 sign-extend it for use in reg_nonzero_bits because some 7599 machines (maybe most) will actually do the sign-extension 7600 and this is the conservative approach. 7601 7602 ??? For 2.5, try to tighten up the MD files in this regard 7603 instead of this kludge. */ 7604 7605 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width 7606 && GET_CODE (tem) == CONST_INT 7607 && INTVAL (tem) > 0 7608 && 0 != (INTVAL (tem) 7609 & ((HOST_WIDE_INT) 1 7610 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1)))) 7611 tem = GEN_INT (INTVAL (tem) 7612 | ((HOST_WIDE_INT) (-1) 7613 << GET_MODE_BITSIZE (GET_MODE (x)))); 7614#endif 7615 return nonzero_bits (tem, mode); 7616 } 7617 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)]) 7618 return reg_nonzero_bits[REGNO (x)] & nonzero; 7619 else 7620 return nonzero; 7621 7622 case CONST_INT: 7623#ifdef SHORT_IMMEDIATES_SIGN_EXTEND 7624 /* If X is negative in MODE, sign-extend the value. */ 7625 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD 7626 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1)))) 7627 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width)); 7628#endif 7629 7630 return INTVAL (x); 7631 7632 case MEM: 7633#ifdef LOAD_EXTEND_OP 7634 /* In many, if not most, RISC machines, reading a byte from memory 7635 zeros the rest of the register. Noticing that fact saves a lot 7636 of extra zero-extends. */ 7637 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND) 7638 nonzero &= GET_MODE_MASK (GET_MODE (x)); 7639#endif 7640 break; 7641 7642 case EQ: case NE: 7643 case GT: case GTU: 7644 case LT: case LTU: 7645 case GE: case GEU: 7646 case LE: case LEU: 7647 7648 /* If this produces an integer result, we know which bits are set. 7649 Code here used to clear bits outside the mode of X, but that is 7650 now done above. */ 7651 7652 if (GET_MODE_CLASS (mode) == MODE_INT 7653 && mode_width <= HOST_BITS_PER_WIDE_INT) 7654 nonzero = STORE_FLAG_VALUE; 7655 break; 7656 7657 case NEG: 7658#if 0 7659 /* Disabled to avoid exponential mutual recursion between nonzero_bits 7660 and num_sign_bit_copies. */ 7661 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x)) 7662 == GET_MODE_BITSIZE (GET_MODE (x))) 7663 nonzero = 1; 7664#endif 7665 7666 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width) 7667 nonzero |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x))); 7668 break; 7669 7670 case ABS: 7671#if 0 7672 /* Disabled to avoid exponential mutual recursion between nonzero_bits 7673 and num_sign_bit_copies. */ 7674 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x)) 7675 == GET_MODE_BITSIZE (GET_MODE (x))) 7676 nonzero = 1; 7677#endif 7678 break; 7679 7680 case TRUNCATE: 7681 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode)); 7682 break; 7683 7684 case ZERO_EXTEND: 7685 nonzero &= nonzero_bits (XEXP (x, 0), mode); 7686 if (GET_MODE (XEXP (x, 0)) != VOIDmode) 7687 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0))); 7688 break; 7689 7690 case SIGN_EXTEND: 7691 /* If the sign bit is known clear, this is the same as ZERO_EXTEND. 7692 Otherwise, show all the bits in the outer mode but not the inner 7693 may be non-zero. */ 7694 inner_nz = nonzero_bits (XEXP (x, 0), mode); 7695 if (GET_MODE (XEXP (x, 0)) != VOIDmode) 7696 { 7697 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0))); 7698 if (inner_nz 7699 & (((HOST_WIDE_INT) 1 7700 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))) 7701 inner_nz |= (GET_MODE_MASK (mode) 7702 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))); 7703 } 7704 7705 nonzero &= inner_nz; 7706 break; 7707 7708 case AND: 7709 nonzero &= (nonzero_bits (XEXP (x, 0), mode) 7710 & nonzero_bits (XEXP (x, 1), mode)); 7711 break; 7712 7713 case XOR: case IOR: 7714 case UMIN: case UMAX: case SMIN: case SMAX: 7715 nonzero &= (nonzero_bits (XEXP (x, 0), mode) 7716 | nonzero_bits (XEXP (x, 1), mode)); 7717 break; 7718 7719 case PLUS: case MINUS: 7720 case MULT: 7721 case DIV: case UDIV: 7722 case MOD: case UMOD: 7723 /* We can apply the rules of arithmetic to compute the number of 7724 high- and low-order zero bits of these operations. We start by 7725 computing the width (position of the highest-order non-zero bit) 7726 and the number of low-order zero bits for each value. */ 7727 { 7728 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode); 7729 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode); 7730 int width0 = floor_log2 (nz0) + 1; 7731 int width1 = floor_log2 (nz1) + 1; 7732 int low0 = floor_log2 (nz0 & -nz0); 7733 int low1 = floor_log2 (nz1 & -nz1); 7734 HOST_WIDE_INT op0_maybe_minusp 7735 = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1))); 7736 HOST_WIDE_INT op1_maybe_minusp 7737 = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1))); 7738 int result_width = mode_width; 7739 int result_low = 0; 7740 7741 switch (code) 7742 { 7743 case PLUS: 7744#ifdef STACK_BIAS 7745 if (STACK_BIAS 7746 && (XEXP (x, 0) == stack_pointer_rtx 7747 || XEXP (x, 0) == frame_pointer_rtx) 7748 && GET_CODE (XEXP (x, 1)) == CONST_INT) 7749 { 7750 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT; 7751 7752 nz0 = (GET_MODE_MASK (mode) & ~ (sp_alignment - 1)); 7753 nz1 = INTVAL (XEXP (x, 1)) - STACK_BIAS; 7754 width0 = floor_log2 (nz0) + 1; 7755 width1 = floor_log2 (nz1) + 1; 7756 low0 = floor_log2 (nz0 & -nz0); 7757 low1 = floor_log2 (nz1 & -nz1); 7758 } 7759#endif 7760 result_width = MAX (width0, width1) + 1; 7761 result_low = MIN (low0, low1); 7762 break; 7763 case MINUS: 7764 result_low = MIN (low0, low1); 7765 break; 7766 case MULT: 7767 result_width = width0 + width1; 7768 result_low = low0 + low1; 7769 break; 7770 case DIV: 7771 if (! op0_maybe_minusp && ! op1_maybe_minusp) 7772 result_width = width0; 7773 break; 7774 case UDIV: 7775 result_width = width0; 7776 break; 7777 case MOD: 7778 if (! op0_maybe_minusp && ! op1_maybe_minusp) 7779 result_width = MIN (width0, width1); 7780 result_low = MIN (low0, low1); 7781 break; 7782 case UMOD: 7783 result_width = MIN (width0, width1); 7784 result_low = MIN (low0, low1); 7785 break; 7786 default: 7787 abort (); 7788 } 7789 7790 if (result_width < mode_width) 7791 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1; 7792 7793 if (result_low > 0) 7794 nonzero &= ~ (((HOST_WIDE_INT) 1 << result_low) - 1); 7795 } 7796 break; 7797 7798 case ZERO_EXTRACT: 7799 if (GET_CODE (XEXP (x, 1)) == CONST_INT 7800 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT) 7801 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1; 7802 break; 7803 7804 case SUBREG: 7805 /* If this is a SUBREG formed for a promoted variable that has 7806 been zero-extended, we know that at least the high-order bits 7807 are zero, though others might be too. */ 7808 7809 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x)) 7810 nonzero = (GET_MODE_MASK (GET_MODE (x)) 7811 & nonzero_bits (SUBREG_REG (x), GET_MODE (x))); 7812 7813 /* If the inner mode is a single word for both the host and target 7814 machines, we can compute this from which bits of the inner 7815 object might be nonzero. */ 7816 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD 7817 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) 7818 <= HOST_BITS_PER_WIDE_INT)) 7819 { 7820 nonzero &= nonzero_bits (SUBREG_REG (x), mode); 7821 7822#if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP) 7823 /* If this is a typical RISC machine, we only have to worry 7824 about the way loads are extended. */ 7825 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND 7826 ? (nonzero 7827 & (1L << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1))) 7828 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND) 7829#endif 7830 { 7831 /* On many CISC machines, accessing an object in a wider mode 7832 causes the high-order bits to become undefined. So they are 7833 not known to be zero. */ 7834 if (GET_MODE_SIZE (GET_MODE (x)) 7835 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) 7836 nonzero |= (GET_MODE_MASK (GET_MODE (x)) 7837 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))); 7838 } 7839 } 7840 break; 7841 7842 case ASHIFTRT: 7843 case LSHIFTRT: 7844 case ASHIFT: 7845 case ROTATE: 7846 /* The nonzero bits are in two classes: any bits within MODE 7847 that aren't in GET_MODE (x) are always significant. The rest of the 7848 nonzero bits are those that are significant in the operand of 7849 the shift when shifted the appropriate number of bits. This 7850 shows that high-order bits are cleared by the right shift and 7851 low-order bits by left shifts. */ 7852 if (GET_CODE (XEXP (x, 1)) == CONST_INT 7853 && INTVAL (XEXP (x, 1)) >= 0 7854 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT) 7855 { 7856 enum machine_mode inner_mode = GET_MODE (x); 7857 int width = GET_MODE_BITSIZE (inner_mode); 7858 int count = INTVAL (XEXP (x, 1)); 7859 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode); 7860 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode); 7861 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask; 7862 unsigned HOST_WIDE_INT outer = 0; 7863 7864 if (mode_width > width) 7865 outer = (op_nonzero & nonzero & ~ mode_mask); 7866 7867 if (code == LSHIFTRT) 7868 inner >>= count; 7869 else if (code == ASHIFTRT) 7870 { 7871 inner >>= count; 7872 7873 /* If the sign bit may have been nonzero before the shift, we 7874 need to mark all the places it could have been copied to 7875 by the shift as possibly nonzero. */ 7876 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count))) 7877 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count); 7878 } 7879 else if (code == ASHIFT) 7880 inner <<= count; 7881 else 7882 inner = ((inner << (count % width) 7883 | (inner >> (width - (count % width)))) & mode_mask); 7884 7885 nonzero &= (outer | inner); 7886 } 7887 break; 7888 7889 case FFS: 7890 /* This is at most the number of bits in the mode. */ 7891 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1; 7892 break; 7893 7894 case IF_THEN_ELSE: 7895 nonzero &= (nonzero_bits (XEXP (x, 1), mode) 7896 | nonzero_bits (XEXP (x, 2), mode)); 7897 break; 7898 7899 default: 7900 break; 7901 } 7902 7903 return nonzero; 7904} 7905 7906/* See the macro definition above. */ 7907#undef num_sign_bit_copies 7908 7909/* Return the number of bits at the high-order end of X that are known to 7910 be equal to the sign bit. X will be used in mode MODE; if MODE is 7911 VOIDmode, X will be used in its own mode. The returned value will always 7912 be between 1 and the number of bits in MODE. */ 7913 7914static int 7915num_sign_bit_copies (x, mode) 7916 rtx x; 7917 enum machine_mode mode; 7918{ 7919 enum rtx_code code = GET_CODE (x); 7920 int bitwidth; 7921 int num0, num1, result; 7922 unsigned HOST_WIDE_INT nonzero; 7923 rtx tem; 7924 7925 /* If we weren't given a mode, use the mode of X. If the mode is still 7926 VOIDmode, we don't know anything. Likewise if one of the modes is 7927 floating-point. */ 7928 7929 if (mode == VOIDmode) 7930 mode = GET_MODE (x); 7931 7932 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x))) 7933 return 1; 7934 7935 bitwidth = GET_MODE_BITSIZE (mode); 7936 7937 /* For a smaller object, just ignore the high bits. */ 7938 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x))) 7939 return MAX (1, (num_sign_bit_copies (x, GET_MODE (x)) 7940 - (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth))); 7941 7942 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x))) 7943 { 7944#ifndef WORD_REGISTER_OPERATIONS 7945 /* If this machine does not do all register operations on the entire 7946 register and MODE is wider than the mode of X, we can say nothing 7947 at all about the high-order bits. */ 7948 return 1; 7949#else 7950 /* Likewise on machines that do, if the mode of the object is smaller 7951 than a word and loads of that size don't sign extend, we can say 7952 nothing about the high order bits. */ 7953 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD 7954#ifdef LOAD_EXTEND_OP 7955 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND 7956#endif 7957 ) 7958 return 1; 7959#endif 7960 } 7961 7962 switch (code) 7963 { 7964 case REG: 7965 7966#ifdef POINTERS_EXTEND_UNSIGNED 7967 /* If pointers extend signed and this is a pointer in Pmode, say that 7968 all the bits above ptr_mode are known to be sign bit copies. */ 7969 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode 7970 && REGNO_POINTER_FLAG (REGNO (x))) 7971 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1; 7972#endif 7973 7974 if (reg_last_set_value[REGNO (x)] != 0 7975 && reg_last_set_mode[REGNO (x)] == mode 7976 && (reg_last_set_label[REGNO (x)] == label_tick 7977 || (REGNO (x) >= FIRST_PSEUDO_REGISTER 7978 && REG_N_SETS (REGNO (x)) == 1 7979 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, 7980 REGNO (x)))) 7981 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid) 7982 return reg_last_set_sign_bit_copies[REGNO (x)]; 7983 7984 tem = get_last_value (x); 7985 if (tem != 0) 7986 return num_sign_bit_copies (tem, mode); 7987 7988 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0) 7989 return reg_sign_bit_copies[REGNO (x)]; 7990 break; 7991 7992 case MEM: 7993#ifdef LOAD_EXTEND_OP 7994 /* Some RISC machines sign-extend all loads of smaller than a word. */ 7995 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND) 7996 return MAX (1, bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1); 7997#endif 7998 break; 7999 8000 case CONST_INT: 8001 /* If the constant is negative, take its 1's complement and remask. 8002 Then see how many zero bits we have. */ 8003 nonzero = INTVAL (x) & GET_MODE_MASK (mode); 8004 if (bitwidth <= HOST_BITS_PER_WIDE_INT 8005 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0) 8006 nonzero = (~ nonzero) & GET_MODE_MASK (mode); 8007 8008 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1); 8009 8010 case SUBREG: 8011 /* If this is a SUBREG for a promoted object that is sign-extended 8012 and we are looking at it in a wider mode, we know that at least the 8013 high-order bits are known to be sign bit copies. */ 8014 8015 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x)) 8016 return MAX (bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1, 8017 num_sign_bit_copies (SUBREG_REG (x), mode)); 8018 8019 /* For a smaller object, just ignore the high bits. */ 8020 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))) 8021 { 8022 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode); 8023 return MAX (1, (num0 8024 - (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) 8025 - bitwidth))); 8026 } 8027 8028#ifdef WORD_REGISTER_OPERATIONS 8029#ifdef LOAD_EXTEND_OP 8030 /* For paradoxical SUBREGs on machines where all register operations 8031 affect the entire register, just look inside. Note that we are 8032 passing MODE to the recursive call, so the number of sign bit copies 8033 will remain relative to that mode, not the inner mode. */ 8034 8035 /* This works only if loads sign extend. Otherwise, if we get a 8036 reload for the inner part, it may be loaded from the stack, and 8037 then we lose all sign bit copies that existed before the store 8038 to the stack. */ 8039 8040 if ((GET_MODE_SIZE (GET_MODE (x)) 8041 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) 8042 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND) 8043 return num_sign_bit_copies (SUBREG_REG (x), mode); 8044#endif 8045#endif 8046 break; 8047 8048 case SIGN_EXTRACT: 8049 if (GET_CODE (XEXP (x, 1)) == CONST_INT) 8050 return MAX (1, bitwidth - INTVAL (XEXP (x, 1))); 8051 break; 8052 8053 case SIGN_EXTEND: 8054 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) 8055 + num_sign_bit_copies (XEXP (x, 0), VOIDmode)); 8056 8057 case TRUNCATE: 8058 /* For a smaller object, just ignore the high bits. */ 8059 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode); 8060 return MAX (1, (num0 - (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) 8061 - bitwidth))); 8062 8063 case NOT: 8064 return num_sign_bit_copies (XEXP (x, 0), mode); 8065 8066 case ROTATE: case ROTATERT: 8067 /* If we are rotating left by a number of bits less than the number 8068 of sign bit copies, we can just subtract that amount from the 8069 number. */ 8070 if (GET_CODE (XEXP (x, 1)) == CONST_INT 8071 && INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) < bitwidth) 8072 { 8073 num0 = num_sign_bit_copies (XEXP (x, 0), mode); 8074 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1)) 8075 : bitwidth - INTVAL (XEXP (x, 1)))); 8076 } 8077 break; 8078 8079 case NEG: 8080 /* In general, this subtracts one sign bit copy. But if the value 8081 is known to be positive, the number of sign bit copies is the 8082 same as that of the input. Finally, if the input has just one bit 8083 that might be nonzero, all the bits are copies of the sign bit. */ 8084 num0 = num_sign_bit_copies (XEXP (x, 0), mode); 8085 if (bitwidth > HOST_BITS_PER_WIDE_INT) 8086 return num0 > 1 ? num0 - 1 : 1; 8087 8088 nonzero = nonzero_bits (XEXP (x, 0), mode); 8089 if (nonzero == 1) 8090 return bitwidth; 8091 8092 if (num0 > 1 8093 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero)) 8094 num0--; 8095 8096 return num0; 8097 8098 case IOR: case AND: case XOR: 8099 case SMIN: case SMAX: case UMIN: case UMAX: 8100 /* Logical operations will preserve the number of sign-bit copies. 8101 MIN and MAX operations always return one of the operands. */ 8102 num0 = num_sign_bit_copies (XEXP (x, 0), mode); 8103 num1 = num_sign_bit_copies (XEXP (x, 1), mode); 8104 return MIN (num0, num1); 8105 8106 case PLUS: case MINUS: 8107 /* For addition and subtraction, we can have a 1-bit carry. However, 8108 if we are subtracting 1 from a positive number, there will not 8109 be such a carry. Furthermore, if the positive number is known to 8110 be 0 or 1, we know the result is either -1 or 0. */ 8111 8112 if (code == PLUS && XEXP (x, 1) == constm1_rtx 8113 && bitwidth <= HOST_BITS_PER_WIDE_INT) 8114 { 8115 nonzero = nonzero_bits (XEXP (x, 0), mode); 8116 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0) 8117 return (nonzero == 1 || nonzero == 0 ? bitwidth 8118 : bitwidth - floor_log2 (nonzero) - 1); 8119 } 8120 8121 num0 = num_sign_bit_copies (XEXP (x, 0), mode); 8122 num1 = num_sign_bit_copies (XEXP (x, 1), mode); 8123 return MAX (1, MIN (num0, num1) - 1); 8124 8125 case MULT: 8126 /* The number of bits of the product is the sum of the number of 8127 bits of both terms. However, unless one of the terms if known 8128 to be positive, we must allow for an additional bit since negating 8129 a negative number can remove one sign bit copy. */ 8130 8131 num0 = num_sign_bit_copies (XEXP (x, 0), mode); 8132 num1 = num_sign_bit_copies (XEXP (x, 1), mode); 8133 8134 result = bitwidth - (bitwidth - num0) - (bitwidth - num1); 8135 if (result > 0 8136 && (bitwidth > HOST_BITS_PER_WIDE_INT 8137 || (((nonzero_bits (XEXP (x, 0), mode) 8138 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0) 8139 && ((nonzero_bits (XEXP (x, 1), mode) 8140 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)))) 8141 result--; 8142 8143 return MAX (1, result); 8144 8145 case UDIV: 8146 /* The result must be <= the first operand. If the first operand 8147 has the high bit set, we know nothing about the number of sign 8148 bit copies. */ 8149 if (bitwidth > HOST_BITS_PER_WIDE_INT) 8150 return 1; 8151 else if ((nonzero_bits (XEXP (x, 0), mode) 8152 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0) 8153 return 1; 8154 else 8155 return num_sign_bit_copies (XEXP (x, 0), mode); 8156 8157 case UMOD: 8158 /* The result must be <= the scond operand. */ 8159 return num_sign_bit_copies (XEXP (x, 1), mode); 8160 8161 case DIV: 8162 /* Similar to unsigned division, except that we have to worry about 8163 the case where the divisor is negative, in which case we have 8164 to add 1. */ 8165 result = num_sign_bit_copies (XEXP (x, 0), mode); 8166 if (result > 1 8167 && (bitwidth > HOST_BITS_PER_WIDE_INT 8168 || (nonzero_bits (XEXP (x, 1), mode) 8169 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)) 8170 result--; 8171 8172 return result; 8173 8174 case MOD: 8175 result = num_sign_bit_copies (XEXP (x, 1), mode); 8176 if (result > 1 8177 && (bitwidth > HOST_BITS_PER_WIDE_INT 8178 || (nonzero_bits (XEXP (x, 1), mode) 8179 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)) 8180 result--; 8181 8182 return result; 8183 8184 case ASHIFTRT: 8185 /* Shifts by a constant add to the number of bits equal to the 8186 sign bit. */ 8187 num0 = num_sign_bit_copies (XEXP (x, 0), mode); 8188 if (GET_CODE (XEXP (x, 1)) == CONST_INT 8189 && INTVAL (XEXP (x, 1)) > 0) 8190 num0 = MIN (bitwidth, num0 + INTVAL (XEXP (x, 1))); 8191 8192 return num0; 8193 8194 case ASHIFT: 8195 /* Left shifts destroy copies. */ 8196 if (GET_CODE (XEXP (x, 1)) != CONST_INT 8197 || INTVAL (XEXP (x, 1)) < 0 8198 || INTVAL (XEXP (x, 1)) >= bitwidth) 8199 return 1; 8200 8201 num0 = num_sign_bit_copies (XEXP (x, 0), mode); 8202 return MAX (1, num0 - INTVAL (XEXP (x, 1))); 8203 8204 case IF_THEN_ELSE: 8205 num0 = num_sign_bit_copies (XEXP (x, 1), mode); 8206 num1 = num_sign_bit_copies (XEXP (x, 2), mode); 8207 return MIN (num0, num1); 8208 8209 case EQ: case NE: case GE: case GT: case LE: case LT: 8210 case GEU: case GTU: case LEU: case LTU: 8211 if (STORE_FLAG_VALUE == -1) 8212 return bitwidth; 8213 break; 8214 8215 default: 8216 break; 8217 } 8218 8219 /* If we haven't been able to figure it out by one of the above rules, 8220 see if some of the high-order bits are known to be zero. If so, 8221 count those bits and return one less than that amount. If we can't 8222 safely compute the mask for this mode, always return BITWIDTH. */ 8223 8224 if (bitwidth > HOST_BITS_PER_WIDE_INT) 8225 return 1; 8226 8227 nonzero = nonzero_bits (x, mode); 8228 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1)) 8229 ? 1 : bitwidth - floor_log2 (nonzero) - 1); 8230} 8231 8232/* Return the number of "extended" bits there are in X, when interpreted 8233 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For 8234 unsigned quantities, this is the number of high-order zero bits. 8235 For signed quantities, this is the number of copies of the sign bit 8236 minus 1. In both case, this function returns the number of "spare" 8237 bits. For example, if two quantities for which this function returns 8238 at least 1 are added, the addition is known not to overflow. 8239 8240 This function will always return 0 unless called during combine, which 8241 implies that it must be called from a define_split. */ 8242 8243int 8244extended_count (x, mode, unsignedp) 8245 rtx x; 8246 enum machine_mode mode; 8247 int unsignedp; 8248{ 8249 if (nonzero_sign_valid == 0) 8250 return 0; 8251 8252 return (unsignedp 8253 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 8254 && (GET_MODE_BITSIZE (mode) - 1 8255 - floor_log2 (nonzero_bits (x, mode)))) 8256 : num_sign_bit_copies (x, mode) - 1); 8257} 8258 8259/* This function is called from `simplify_shift_const' to merge two 8260 outer operations. Specifically, we have already found that we need 8261 to perform operation *POP0 with constant *PCONST0 at the outermost 8262 position. We would now like to also perform OP1 with constant CONST1 8263 (with *POP0 being done last). 8264 8265 Return 1 if we can do the operation and update *POP0 and *PCONST0 with 8266 the resulting operation. *PCOMP_P is set to 1 if we would need to 8267 complement the innermost operand, otherwise it is unchanged. 8268 8269 MODE is the mode in which the operation will be done. No bits outside 8270 the width of this mode matter. It is assumed that the width of this mode 8271 is smaller than or equal to HOST_BITS_PER_WIDE_INT. 8272 8273 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS, 8274 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper 8275 result is simply *PCONST0. 8276 8277 If the resulting operation cannot be expressed as one operation, we 8278 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */ 8279 8280static int 8281merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p) 8282 enum rtx_code *pop0; 8283 HOST_WIDE_INT *pconst0; 8284 enum rtx_code op1; 8285 HOST_WIDE_INT const1; 8286 enum machine_mode mode; 8287 int *pcomp_p; 8288{ 8289 enum rtx_code op0 = *pop0; 8290 HOST_WIDE_INT const0 = *pconst0; 8291 int width = GET_MODE_BITSIZE (mode); 8292 8293 const0 &= GET_MODE_MASK (mode); 8294 const1 &= GET_MODE_MASK (mode); 8295 8296 /* If OP0 is an AND, clear unimportant bits in CONST1. */ 8297 if (op0 == AND) 8298 const1 &= const0; 8299 8300 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or 8301 if OP0 is SET. */ 8302 8303 if (op1 == NIL || op0 == SET) 8304 return 1; 8305 8306 else if (op0 == NIL) 8307 op0 = op1, const0 = const1; 8308 8309 else if (op0 == op1) 8310 { 8311 switch (op0) 8312 { 8313 case AND: 8314 const0 &= const1; 8315 break; 8316 case IOR: 8317 const0 |= const1; 8318 break; 8319 case XOR: 8320 const0 ^= const1; 8321 break; 8322 case PLUS: 8323 const0 += const1; 8324 break; 8325 case NEG: 8326 op0 = NIL; 8327 break; 8328 default: 8329 break; 8330 } 8331 } 8332 8333 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */ 8334 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG) 8335 return 0; 8336 8337 /* If the two constants aren't the same, we can't do anything. The 8338 remaining six cases can all be done. */ 8339 else if (const0 != const1) 8340 return 0; 8341 8342 else 8343 switch (op0) 8344 { 8345 case IOR: 8346 if (op1 == AND) 8347 /* (a & b) | b == b */ 8348 op0 = SET; 8349 else /* op1 == XOR */ 8350 /* (a ^ b) | b == a | b */ 8351 {;} 8352 break; 8353 8354 case XOR: 8355 if (op1 == AND) 8356 /* (a & b) ^ b == (~a) & b */ 8357 op0 = AND, *pcomp_p = 1; 8358 else /* op1 == IOR */ 8359 /* (a | b) ^ b == a & ~b */ 8360 op0 = AND, *pconst0 = ~ const0; 8361 break; 8362 8363 case AND: 8364 if (op1 == IOR) 8365 /* (a | b) & b == b */ 8366 op0 = SET; 8367 else /* op1 == XOR */ 8368 /* (a ^ b) & b) == (~a) & b */ 8369 *pcomp_p = 1; 8370 break; 8371 default: 8372 break; 8373 } 8374 8375 /* Check for NO-OP cases. */ 8376 const0 &= GET_MODE_MASK (mode); 8377 if (const0 == 0 8378 && (op0 == IOR || op0 == XOR || op0 == PLUS)) 8379 op0 = NIL; 8380 else if (const0 == 0 && op0 == AND) 8381 op0 = SET; 8382 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode) 8383 && op0 == AND) 8384 op0 = NIL; 8385 8386 /* If this would be an entire word for the target, but is not for 8387 the host, then sign-extend on the host so that the number will look 8388 the same way on the host that it would on the target. 8389 8390 For example, when building a 64 bit alpha hosted 32 bit sparc 8391 targeted compiler, then we want the 32 bit unsigned value -1 to be 8392 represented as a 64 bit value -1, and not as 0x00000000ffffffff. 8393 The later confuses the sparc backend. */ 8394 8395 if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width 8396 && (const0 & ((HOST_WIDE_INT) 1 << (width - 1)))) 8397 const0 |= ((HOST_WIDE_INT) (-1) << width); 8398 8399 *pop0 = op0; 8400 *pconst0 = const0; 8401 8402 return 1; 8403} 8404 8405/* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift. 8406 The result of the shift is RESULT_MODE. X, if non-zero, is an expression 8407 that we started with. 8408 8409 The shift is normally computed in the widest mode we find in VAROP, as 8410 long as it isn't a different number of words than RESULT_MODE. Exceptions 8411 are ASHIFTRT and ROTATE, which are always done in their original mode, */ 8412 8413static rtx 8414simplify_shift_const (x, code, result_mode, varop, count) 8415 rtx x; 8416 enum rtx_code code; 8417 enum machine_mode result_mode; 8418 rtx varop; 8419 int count; 8420{ 8421 enum rtx_code orig_code = code; 8422 int orig_count = count; 8423 enum machine_mode mode = result_mode; 8424 enum machine_mode shift_mode, tmode; 8425 int mode_words 8426 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD; 8427 /* We form (outer_op (code varop count) (outer_const)). */ 8428 enum rtx_code outer_op = NIL; 8429 HOST_WIDE_INT outer_const = 0; 8430 rtx const_rtx; 8431 int complement_p = 0; 8432 rtx new; 8433 8434 /* If we were given an invalid count, don't do anything except exactly 8435 what was requested. */ 8436 8437 if (count < 0 || count > GET_MODE_BITSIZE (mode)) 8438 { 8439 if (x) 8440 return x; 8441 8442 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (count)); 8443 } 8444 8445 /* Unless one of the branches of the `if' in this loop does a `continue', 8446 we will `break' the loop after the `if'. */ 8447 8448 while (count != 0) 8449 { 8450 /* If we have an operand of (clobber (const_int 0)), just return that 8451 value. */ 8452 if (GET_CODE (varop) == CLOBBER) 8453 return varop; 8454 8455 /* If we discovered we had to complement VAROP, leave. Making a NOT 8456 here would cause an infinite loop. */ 8457 if (complement_p) 8458 break; 8459 8460 /* Convert ROTATERT to ROTATE. */ 8461 if (code == ROTATERT) 8462 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count; 8463 8464 /* We need to determine what mode we will do the shift in. If the 8465 shift is a right shift or a ROTATE, we must always do it in the mode 8466 it was originally done in. Otherwise, we can do it in MODE, the 8467 widest mode encountered. */ 8468 shift_mode 8469 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE 8470 ? result_mode : mode); 8471 8472 /* Handle cases where the count is greater than the size of the mode 8473 minus 1. For ASHIFT, use the size minus one as the count (this can 8474 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates, 8475 take the count modulo the size. For other shifts, the result is 8476 zero. 8477 8478 Since these shifts are being produced by the compiler by combining 8479 multiple operations, each of which are defined, we know what the 8480 result is supposed to be. */ 8481 8482 if (count > GET_MODE_BITSIZE (shift_mode) - 1) 8483 { 8484 if (code == ASHIFTRT) 8485 count = GET_MODE_BITSIZE (shift_mode) - 1; 8486 else if (code == ROTATE || code == ROTATERT) 8487 count %= GET_MODE_BITSIZE (shift_mode); 8488 else 8489 { 8490 /* We can't simply return zero because there may be an 8491 outer op. */ 8492 varop = const0_rtx; 8493 count = 0; 8494 break; 8495 } 8496 } 8497 8498 /* Negative counts are invalid and should not have been made (a 8499 programmer-specified negative count should have been handled 8500 above). */ 8501 else if (count < 0) 8502 abort (); 8503 8504 /* An arithmetic right shift of a quantity known to be -1 or 0 8505 is a no-op. */ 8506 if (code == ASHIFTRT 8507 && (num_sign_bit_copies (varop, shift_mode) 8508 == GET_MODE_BITSIZE (shift_mode))) 8509 { 8510 count = 0; 8511 break; 8512 } 8513 8514 /* If we are doing an arithmetic right shift and discarding all but 8515 the sign bit copies, this is equivalent to doing a shift by the 8516 bitsize minus one. Convert it into that shift because it will often 8517 allow other simplifications. */ 8518 8519 if (code == ASHIFTRT 8520 && (count + num_sign_bit_copies (varop, shift_mode) 8521 >= GET_MODE_BITSIZE (shift_mode))) 8522 count = GET_MODE_BITSIZE (shift_mode) - 1; 8523 8524 /* We simplify the tests below and elsewhere by converting 8525 ASHIFTRT to LSHIFTRT if we know the sign bit is clear. 8526 `make_compound_operation' will convert it to a ASHIFTRT for 8527 those machines (such as Vax) that don't have a LSHIFTRT. */ 8528 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT 8529 && code == ASHIFTRT 8530 && ((nonzero_bits (varop, shift_mode) 8531 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1))) 8532 == 0)) 8533 code = LSHIFTRT; 8534 8535 switch (GET_CODE (varop)) 8536 { 8537 case SIGN_EXTEND: 8538 case ZERO_EXTEND: 8539 case SIGN_EXTRACT: 8540 case ZERO_EXTRACT: 8541 new = expand_compound_operation (varop); 8542 if (new != varop) 8543 { 8544 varop = new; 8545 continue; 8546 } 8547 break; 8548 8549 case MEM: 8550 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH 8551 minus the width of a smaller mode, we can do this with a 8552 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */ 8553 if ((code == ASHIFTRT || code == LSHIFTRT) 8554 && ! mode_dependent_address_p (XEXP (varop, 0)) 8555 && ! MEM_VOLATILE_P (varop) 8556 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count, 8557 MODE_INT, 1)) != BLKmode) 8558 { 8559 if (BYTES_BIG_ENDIAN) 8560 new = gen_rtx_MEM (tmode, XEXP (varop, 0)); 8561 else 8562 new = gen_rtx_MEM (tmode, 8563 plus_constant (XEXP (varop, 0), 8564 count / BITS_PER_UNIT)); 8565 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop); 8566 MEM_COPY_ATTRIBUTES (new, varop); 8567 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND 8568 : ZERO_EXTEND, mode, new); 8569 count = 0; 8570 continue; 8571 } 8572 break; 8573 8574 case USE: 8575 /* Similar to the case above, except that we can only do this if 8576 the resulting mode is the same as that of the underlying 8577 MEM and adjust the address depending on the *bits* endianness 8578 because of the way that bit-field extract insns are defined. */ 8579 if ((code == ASHIFTRT || code == LSHIFTRT) 8580 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count, 8581 MODE_INT, 1)) != BLKmode 8582 && tmode == GET_MODE (XEXP (varop, 0))) 8583 { 8584 if (BITS_BIG_ENDIAN) 8585 new = XEXP (varop, 0); 8586 else 8587 { 8588 new = copy_rtx (XEXP (varop, 0)); 8589 SUBST (XEXP (new, 0), 8590 plus_constant (XEXP (new, 0), 8591 count / BITS_PER_UNIT)); 8592 } 8593 8594 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND 8595 : ZERO_EXTEND, mode, new); 8596 count = 0; 8597 continue; 8598 } 8599 break; 8600 8601 case SUBREG: 8602 /* If VAROP is a SUBREG, strip it as long as the inner operand has 8603 the same number of words as what we've seen so far. Then store 8604 the widest mode in MODE. */ 8605 if (subreg_lowpart_p (varop) 8606 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop))) 8607 > GET_MODE_SIZE (GET_MODE (varop))) 8608 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop))) 8609 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) 8610 == mode_words)) 8611 { 8612 varop = SUBREG_REG (varop); 8613 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode)) 8614 mode = GET_MODE (varop); 8615 continue; 8616 } 8617 break; 8618 8619 case MULT: 8620 /* Some machines use MULT instead of ASHIFT because MULT 8621 is cheaper. But it is still better on those machines to 8622 merge two shifts into one. */ 8623 if (GET_CODE (XEXP (varop, 1)) == CONST_INT 8624 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0) 8625 { 8626 varop = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0), 8627 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));; 8628 continue; 8629 } 8630 break; 8631 8632 case UDIV: 8633 /* Similar, for when divides are cheaper. */ 8634 if (GET_CODE (XEXP (varop, 1)) == CONST_INT 8635 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0) 8636 { 8637 varop = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0), 8638 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1))))); 8639 continue; 8640 } 8641 break; 8642 8643 case ASHIFTRT: 8644 /* If we are extracting just the sign bit of an arithmetic right 8645 shift, that shift is not needed. */ 8646 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1) 8647 { 8648 varop = XEXP (varop, 0); 8649 continue; 8650 } 8651 8652 /* ... fall through ... */ 8653 8654 case LSHIFTRT: 8655 case ASHIFT: 8656 case ROTATE: 8657 /* Here we have two nested shifts. The result is usually the 8658 AND of a new shift with a mask. We compute the result below. */ 8659 if (GET_CODE (XEXP (varop, 1)) == CONST_INT 8660 && INTVAL (XEXP (varop, 1)) >= 0 8661 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop)) 8662 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT 8663 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) 8664 { 8665 enum rtx_code first_code = GET_CODE (varop); 8666 int first_count = INTVAL (XEXP (varop, 1)); 8667 unsigned HOST_WIDE_INT mask; 8668 rtx mask_rtx; 8669 8670 /* We have one common special case. We can't do any merging if 8671 the inner code is an ASHIFTRT of a smaller mode. However, if 8672 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2) 8673 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2), 8674 we can convert it to 8675 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1). 8676 This simplifies certain SIGN_EXTEND operations. */ 8677 if (code == ASHIFT && first_code == ASHIFTRT 8678 && (GET_MODE_BITSIZE (result_mode) 8679 - GET_MODE_BITSIZE (GET_MODE (varop))) == count) 8680 { 8681 /* C3 has the low-order C1 bits zero. */ 8682 8683 mask = (GET_MODE_MASK (mode) 8684 & ~ (((HOST_WIDE_INT) 1 << first_count) - 1)); 8685 8686 varop = simplify_and_const_int (NULL_RTX, result_mode, 8687 XEXP (varop, 0), mask); 8688 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode, 8689 varop, count); 8690 count = first_count; 8691 code = ASHIFTRT; 8692 continue; 8693 } 8694 8695 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more 8696 than C1 high-order bits equal to the sign bit, we can convert 8697 this to either an ASHIFT or a ASHIFTRT depending on the 8698 two counts. 8699 8700 We cannot do this if VAROP's mode is not SHIFT_MODE. */ 8701 8702 if (code == ASHIFTRT && first_code == ASHIFT 8703 && GET_MODE (varop) == shift_mode 8704 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode) 8705 > first_count)) 8706 { 8707 count -= first_count; 8708 if (count < 0) 8709 count = - count, code = ASHIFT; 8710 varop = XEXP (varop, 0); 8711 continue; 8712 } 8713 8714 /* There are some cases we can't do. If CODE is ASHIFTRT, 8715 we can only do this if FIRST_CODE is also ASHIFTRT. 8716 8717 We can't do the case when CODE is ROTATE and FIRST_CODE is 8718 ASHIFTRT. 8719 8720 If the mode of this shift is not the mode of the outer shift, 8721 we can't do this if either shift is a right shift or ROTATE. 8722 8723 Finally, we can't do any of these if the mode is too wide 8724 unless the codes are the same. 8725 8726 Handle the case where the shift codes are the same 8727 first. */ 8728 8729 if (code == first_code) 8730 { 8731 if (GET_MODE (varop) != result_mode 8732 && (code == ASHIFTRT || code == LSHIFTRT 8733 || code == ROTATE)) 8734 break; 8735 8736 count += first_count; 8737 varop = XEXP (varop, 0); 8738 continue; 8739 } 8740 8741 if (code == ASHIFTRT 8742 || (code == ROTATE && first_code == ASHIFTRT) 8743 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT 8744 || (GET_MODE (varop) != result_mode 8745 && (first_code == ASHIFTRT || first_code == LSHIFTRT 8746 || first_code == ROTATE 8747 || code == ROTATE))) 8748 break; 8749 8750 /* To compute the mask to apply after the shift, shift the 8751 nonzero bits of the inner shift the same way the 8752 outer shift will. */ 8753 8754 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop))); 8755 8756 mask_rtx 8757 = simplify_binary_operation (code, result_mode, mask_rtx, 8758 GEN_INT (count)); 8759 8760 /* Give up if we can't compute an outer operation to use. */ 8761 if (mask_rtx == 0 8762 || GET_CODE (mask_rtx) != CONST_INT 8763 || ! merge_outer_ops (&outer_op, &outer_const, AND, 8764 INTVAL (mask_rtx), 8765 result_mode, &complement_p)) 8766 break; 8767 8768 /* If the shifts are in the same direction, we add the 8769 counts. Otherwise, we subtract them. */ 8770 if ((code == ASHIFTRT || code == LSHIFTRT) 8771 == (first_code == ASHIFTRT || first_code == LSHIFTRT)) 8772 count += first_count; 8773 else 8774 count -= first_count; 8775 8776 /* If COUNT is positive, the new shift is usually CODE, 8777 except for the two exceptions below, in which case it is 8778 FIRST_CODE. If the count is negative, FIRST_CODE should 8779 always be used */ 8780 if (count > 0 8781 && ((first_code == ROTATE && code == ASHIFT) 8782 || (first_code == ASHIFTRT && code == LSHIFTRT))) 8783 code = first_code; 8784 else if (count < 0) 8785 code = first_code, count = - count; 8786 8787 varop = XEXP (varop, 0); 8788 continue; 8789 } 8790 8791 /* If we have (A << B << C) for any shift, we can convert this to 8792 (A << C << B). This wins if A is a constant. Only try this if 8793 B is not a constant. */ 8794 8795 else if (GET_CODE (varop) == code 8796 && GET_CODE (XEXP (varop, 1)) != CONST_INT 8797 && 0 != (new 8798 = simplify_binary_operation (code, mode, 8799 XEXP (varop, 0), 8800 GEN_INT (count)))) 8801 { 8802 varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1)); 8803 count = 0; 8804 continue; 8805 } 8806 break; 8807 8808 case NOT: 8809 /* Make this fit the case below. */ 8810 varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0), 8811 GEN_INT (GET_MODE_MASK (mode))); 8812 continue; 8813 8814 case IOR: 8815 case AND: 8816 case XOR: 8817 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C) 8818 with C the size of VAROP - 1 and the shift is logical if 8819 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1, 8820 we have an (le X 0) operation. If we have an arithmetic shift 8821 and STORE_FLAG_VALUE is 1 or we have a logical shift with 8822 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */ 8823 8824 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS 8825 && XEXP (XEXP (varop, 0), 1) == constm1_rtx 8826 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) 8827 && (code == LSHIFTRT || code == ASHIFTRT) 8828 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1 8829 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1))) 8830 { 8831 count = 0; 8832 varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1), 8833 const0_rtx); 8834 8835 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT) 8836 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop); 8837 8838 continue; 8839 } 8840 8841 /* If we have (shift (logical)), move the logical to the outside 8842 to allow it to possibly combine with another logical and the 8843 shift to combine with another shift. This also canonicalizes to 8844 what a ZERO_EXTRACT looks like. Also, some machines have 8845 (and (shift)) insns. */ 8846 8847 if (GET_CODE (XEXP (varop, 1)) == CONST_INT 8848 && (new = simplify_binary_operation (code, result_mode, 8849 XEXP (varop, 1), 8850 GEN_INT (count))) != 0 8851 && GET_CODE(new) == CONST_INT 8852 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop), 8853 INTVAL (new), result_mode, &complement_p)) 8854 { 8855 varop = XEXP (varop, 0); 8856 continue; 8857 } 8858 8859 /* If we can't do that, try to simplify the shift in each arm of the 8860 logical expression, make a new logical expression, and apply 8861 the inverse distributive law. */ 8862 { 8863 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode, 8864 XEXP (varop, 0), count); 8865 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode, 8866 XEXP (varop, 1), count); 8867 8868 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs); 8869 varop = apply_distributive_law (varop); 8870 8871 count = 0; 8872 } 8873 break; 8874 8875 case EQ: 8876 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE 8877 says that the sign bit can be tested, FOO has mode MODE, C is 8878 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit 8879 that may be nonzero. */ 8880 if (code == LSHIFTRT 8881 && XEXP (varop, 1) == const0_rtx 8882 && GET_MODE (XEXP (varop, 0)) == result_mode 8883 && count == GET_MODE_BITSIZE (result_mode) - 1 8884 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT 8885 && ((STORE_FLAG_VALUE 8886 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (result_mode) - 1)))) 8887 && nonzero_bits (XEXP (varop, 0), result_mode) == 1 8888 && merge_outer_ops (&outer_op, &outer_const, XOR, 8889 (HOST_WIDE_INT) 1, result_mode, 8890 &complement_p)) 8891 { 8892 varop = XEXP (varop, 0); 8893 count = 0; 8894 continue; 8895 } 8896 break; 8897 8898 case NEG: 8899 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less 8900 than the number of bits in the mode is equivalent to A. */ 8901 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1 8902 && nonzero_bits (XEXP (varop, 0), result_mode) == 1) 8903 { 8904 varop = XEXP (varop, 0); 8905 count = 0; 8906 continue; 8907 } 8908 8909 /* NEG commutes with ASHIFT since it is multiplication. Move the 8910 NEG outside to allow shifts to combine. */ 8911 if (code == ASHIFT 8912 && merge_outer_ops (&outer_op, &outer_const, NEG, 8913 (HOST_WIDE_INT) 0, result_mode, 8914 &complement_p)) 8915 { 8916 varop = XEXP (varop, 0); 8917 continue; 8918 } 8919 break; 8920 8921 case PLUS: 8922 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C 8923 is one less than the number of bits in the mode is 8924 equivalent to (xor A 1). */ 8925 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1 8926 && XEXP (varop, 1) == constm1_rtx 8927 && nonzero_bits (XEXP (varop, 0), result_mode) == 1 8928 && merge_outer_ops (&outer_op, &outer_const, XOR, 8929 (HOST_WIDE_INT) 1, result_mode, 8930 &complement_p)) 8931 { 8932 count = 0; 8933 varop = XEXP (varop, 0); 8934 continue; 8935 } 8936 8937 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits 8938 that might be nonzero in BAR are those being shifted out and those 8939 bits are known zero in FOO, we can replace the PLUS with FOO. 8940 Similarly in the other operand order. This code occurs when 8941 we are computing the size of a variable-size array. */ 8942 8943 if ((code == ASHIFTRT || code == LSHIFTRT) 8944 && count < HOST_BITS_PER_WIDE_INT 8945 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0 8946 && (nonzero_bits (XEXP (varop, 1), result_mode) 8947 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0) 8948 { 8949 varop = XEXP (varop, 0); 8950 continue; 8951 } 8952 else if ((code == ASHIFTRT || code == LSHIFTRT) 8953 && count < HOST_BITS_PER_WIDE_INT 8954 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT 8955 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode) 8956 >> count) 8957 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode) 8958 & nonzero_bits (XEXP (varop, 1), 8959 result_mode))) 8960 { 8961 varop = XEXP (varop, 1); 8962 continue; 8963 } 8964 8965 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */ 8966 if (code == ASHIFT 8967 && GET_CODE (XEXP (varop, 1)) == CONST_INT 8968 && (new = simplify_binary_operation (ASHIFT, result_mode, 8969 XEXP (varop, 1), 8970 GEN_INT (count))) != 0 8971 && GET_CODE(new) == CONST_INT 8972 && merge_outer_ops (&outer_op, &outer_const, PLUS, 8973 INTVAL (new), result_mode, &complement_p)) 8974 { 8975 varop = XEXP (varop, 0); 8976 continue; 8977 } 8978 break; 8979 8980 case MINUS: 8981 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C) 8982 with C the size of VAROP - 1 and the shift is logical if 8983 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1, 8984 we have a (gt X 0) operation. If the shift is arithmetic with 8985 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1, 8986 we have a (neg (gt X 0)) operation. */ 8987 8988 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) 8989 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT 8990 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1 8991 && (code == LSHIFTRT || code == ASHIFTRT) 8992 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT 8993 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count 8994 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1))) 8995 { 8996 count = 0; 8997 varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1), 8998 const0_rtx); 8999 9000 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT) 9001 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop); 9002 9003 continue; 9004 } 9005 break; 9006 9007 case TRUNCATE: 9008 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt)) 9009 if the truncate does not affect the value. */ 9010 if (code == LSHIFTRT 9011 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT 9012 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT 9013 && (INTVAL (XEXP (XEXP (varop, 0), 1)) 9014 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0))) 9015 - GET_MODE_BITSIZE (GET_MODE (varop))))) 9016 { 9017 rtx varop_inner = XEXP (varop, 0); 9018 9019 varop_inner = gen_rtx_combine (LSHIFTRT, 9020 GET_MODE (varop_inner), 9021 XEXP (varop_inner, 0), 9022 GEN_INT (count + INTVAL (XEXP (varop_inner, 1)))); 9023 varop = gen_rtx_combine (TRUNCATE, GET_MODE (varop), 9024 varop_inner); 9025 count = 0; 9026 continue; 9027 } 9028 break; 9029 9030 default: 9031 break; 9032 } 9033 9034 break; 9035 } 9036 9037 /* We need to determine what mode to do the shift in. If the shift is 9038 a right shift or ROTATE, we must always do it in the mode it was 9039 originally done in. Otherwise, we can do it in MODE, the widest mode 9040 encountered. The code we care about is that of the shift that will 9041 actually be done, not the shift that was originally requested. */ 9042 shift_mode 9043 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE 9044 ? result_mode : mode); 9045 9046 /* We have now finished analyzing the shift. The result should be 9047 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If 9048 OUTER_OP is non-NIL, it is an operation that needs to be applied 9049 to the result of the shift. OUTER_CONST is the relevant constant, 9050 but we must turn off all bits turned off in the shift. 9051 9052 If we were passed a value for X, see if we can use any pieces of 9053 it. If not, make new rtx. */ 9054 9055 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2' 9056 && GET_CODE (XEXP (x, 1)) == CONST_INT 9057 && INTVAL (XEXP (x, 1)) == count) 9058 const_rtx = XEXP (x, 1); 9059 else 9060 const_rtx = GEN_INT (count); 9061 9062 if (x && GET_CODE (XEXP (x, 0)) == SUBREG 9063 && GET_MODE (XEXP (x, 0)) == shift_mode 9064 && SUBREG_REG (XEXP (x, 0)) == varop) 9065 varop = XEXP (x, 0); 9066 else if (GET_MODE (varop) != shift_mode) 9067 varop = gen_lowpart_for_combine (shift_mode, varop); 9068 9069 /* If we can't make the SUBREG, try to return what we were given. */ 9070 if (GET_CODE (varop) == CLOBBER) 9071 return x ? x : varop; 9072 9073 new = simplify_binary_operation (code, shift_mode, varop, const_rtx); 9074 if (new != 0) 9075 x = new; 9076 else 9077 { 9078 if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode) 9079 x = gen_rtx_combine (code, shift_mode, varop, const_rtx); 9080 9081 SUBST (XEXP (x, 0), varop); 9082 SUBST (XEXP (x, 1), const_rtx); 9083 } 9084 9085 /* If we have an outer operation and we just made a shift, it is 9086 possible that we could have simplified the shift were it not 9087 for the outer operation. So try to do the simplification 9088 recursively. */ 9089 9090 if (outer_op != NIL && GET_CODE (x) == code 9091 && GET_CODE (XEXP (x, 1)) == CONST_INT) 9092 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0), 9093 INTVAL (XEXP (x, 1))); 9094 9095 /* If we were doing a LSHIFTRT in a wider mode than it was originally, 9096 turn off all the bits that the shift would have turned off. */ 9097 if (orig_code == LSHIFTRT && result_mode != shift_mode) 9098 x = simplify_and_const_int (NULL_RTX, shift_mode, x, 9099 GET_MODE_MASK (result_mode) >> orig_count); 9100 9101 /* Do the remainder of the processing in RESULT_MODE. */ 9102 x = gen_lowpart_for_combine (result_mode, x); 9103 9104 /* If COMPLEMENT_P is set, we have to complement X before doing the outer 9105 operation. */ 9106 if (complement_p) 9107 x = gen_unary (NOT, result_mode, result_mode, x); 9108 9109 if (outer_op != NIL) 9110 { 9111 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT) 9112 { 9113 int width = GET_MODE_BITSIZE (result_mode); 9114 9115 outer_const &= GET_MODE_MASK (result_mode); 9116 9117 /* If this would be an entire word for the target, but is not for 9118 the host, then sign-extend on the host so that the number will 9119 look the same way on the host that it would on the target. 9120 9121 For example, when building a 64 bit alpha hosted 32 bit sparc 9122 targeted compiler, then we want the 32 bit unsigned value -1 to be 9123 represented as a 64 bit value -1, and not as 0x00000000ffffffff. 9124 The later confuses the sparc backend. */ 9125 9126 if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width 9127 && (outer_const & ((HOST_WIDE_INT) 1 << (width - 1)))) 9128 outer_const |= ((HOST_WIDE_INT) (-1) << width); 9129 } 9130 9131 if (outer_op == AND) 9132 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const); 9133 else if (outer_op == SET) 9134 /* This means that we have determined that the result is 9135 equivalent to a constant. This should be rare. */ 9136 x = GEN_INT (outer_const); 9137 else if (GET_RTX_CLASS (outer_op) == '1') 9138 x = gen_unary (outer_op, result_mode, result_mode, x); 9139 else 9140 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const)); 9141 } 9142 9143 return x; 9144} 9145 9146/* Like recog, but we receive the address of a pointer to a new pattern. 9147 We try to match the rtx that the pointer points to. 9148 If that fails, we may try to modify or replace the pattern, 9149 storing the replacement into the same pointer object. 9150 9151 Modifications include deletion or addition of CLOBBERs. 9152 9153 PNOTES is a pointer to a location where any REG_UNUSED notes added for 9154 the CLOBBERs are placed. 9155 9156 The value is the final insn code from the pattern ultimately matched, 9157 or -1. */ 9158 9159static int 9160recog_for_combine (pnewpat, insn, pnotes) 9161 rtx *pnewpat; 9162 rtx insn; 9163 rtx *pnotes; 9164{ 9165 register rtx pat = *pnewpat; 9166 int insn_code_number; 9167 int num_clobbers_to_add = 0; 9168 int i; 9169 rtx notes = 0; 9170 9171 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER 9172 we use to indicate that something didn't match. If we find such a 9173 thing, force rejection. */ 9174 if (GET_CODE (pat) == PARALLEL) 9175 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--) 9176 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER 9177 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx) 9178 return -1; 9179 9180 /* Is the result of combination a valid instruction? */ 9181 insn_code_number = recog (pat, insn, &num_clobbers_to_add); 9182 9183 /* If it isn't, there is the possibility that we previously had an insn 9184 that clobbered some register as a side effect, but the combined 9185 insn doesn't need to do that. So try once more without the clobbers 9186 unless this represents an ASM insn. */ 9187 9188 if (insn_code_number < 0 && ! check_asm_operands (pat) 9189 && GET_CODE (pat) == PARALLEL) 9190 { 9191 int pos; 9192 9193 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++) 9194 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER) 9195 { 9196 if (i != pos) 9197 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i)); 9198 pos++; 9199 } 9200 9201 SUBST_INT (XVECLEN (pat, 0), pos); 9202 9203 if (pos == 1) 9204 pat = XVECEXP (pat, 0, 0); 9205 9206 insn_code_number = recog (pat, insn, &num_clobbers_to_add); 9207 } 9208 9209 /* If we had any clobbers to add, make a new pattern than contains 9210 them. Then check to make sure that all of them are dead. */ 9211 if (num_clobbers_to_add) 9212 { 9213 rtx newpat = gen_rtx_PARALLEL (VOIDmode, 9214 gen_rtvec (GET_CODE (pat) == PARALLEL 9215 ? XVECLEN (pat, 0) + num_clobbers_to_add 9216 : num_clobbers_to_add + 1)); 9217 9218 if (GET_CODE (pat) == PARALLEL) 9219 for (i = 0; i < XVECLEN (pat, 0); i++) 9220 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i); 9221 else 9222 XVECEXP (newpat, 0, 0) = pat; 9223 9224 add_clobbers (newpat, insn_code_number); 9225 9226 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add; 9227 i < XVECLEN (newpat, 0); i++) 9228 { 9229 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG 9230 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn)) 9231 return -1; 9232 notes = gen_rtx_EXPR_LIST (REG_UNUSED, 9233 XEXP (XVECEXP (newpat, 0, i), 0), notes); 9234 } 9235 pat = newpat; 9236 } 9237 9238 *pnewpat = pat; 9239 *pnotes = notes; 9240 9241 return insn_code_number; 9242} 9243 9244/* Like gen_lowpart but for use by combine. In combine it is not possible 9245 to create any new pseudoregs. However, it is safe to create 9246 invalid memory addresses, because combine will try to recognize 9247 them and all they will do is make the combine attempt fail. 9248 9249 If for some reason this cannot do its job, an rtx 9250 (clobber (const_int 0)) is returned. 9251 An insn containing that will not be recognized. */ 9252 9253#undef gen_lowpart 9254 9255static rtx 9256gen_lowpart_for_combine (mode, x) 9257 enum machine_mode mode; 9258 register rtx x; 9259{ 9260 rtx result; 9261 9262 if (GET_MODE (x) == mode) 9263 return x; 9264 9265 /* We can only support MODE being wider than a word if X is a 9266 constant integer or has a mode the same size. */ 9267 9268 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD 9269 && ! ((GET_MODE (x) == VOIDmode 9270 && (GET_CODE (x) == CONST_INT 9271 || GET_CODE (x) == CONST_DOUBLE)) 9272 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode))) 9273 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); 9274 9275 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart 9276 won't know what to do. So we will strip off the SUBREG here and 9277 process normally. */ 9278 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM) 9279 { 9280 x = SUBREG_REG (x); 9281 if (GET_MODE (x) == mode) 9282 return x; 9283 } 9284 9285 result = gen_lowpart_common (mode, x); 9286 if (result != 0 9287 && GET_CODE (result) == SUBREG 9288 && GET_CODE (SUBREG_REG (result)) == REG 9289 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER 9290 && (GET_MODE_SIZE (GET_MODE (result)) 9291 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (result))))) 9292 REG_CHANGES_SIZE (REGNO (SUBREG_REG (result))) = 1; 9293 9294 if (result) 9295 return result; 9296 9297 if (GET_CODE (x) == MEM) 9298 { 9299 register int offset = 0; 9300 rtx new; 9301 9302 /* Refuse to work on a volatile memory ref or one with a mode-dependent 9303 address. */ 9304 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0))) 9305 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); 9306 9307 /* If we want to refer to something bigger than the original memref, 9308 generate a perverse subreg instead. That will force a reload 9309 of the original memref X. */ 9310 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)) 9311 return gen_rtx_SUBREG (mode, x, 0); 9312 9313 if (WORDS_BIG_ENDIAN) 9314 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD) 9315 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD)); 9316 if (BYTES_BIG_ENDIAN) 9317 { 9318 /* Adjust the address so that the address-after-the-data is 9319 unchanged. */ 9320 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)) 9321 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x)))); 9322 } 9323 new = gen_rtx_MEM (mode, plus_constant (XEXP (x, 0), offset)); 9324 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x); 9325 MEM_COPY_ATTRIBUTES (new, x); 9326 return new; 9327 } 9328 9329 /* If X is a comparison operator, rewrite it in a new mode. This 9330 probably won't match, but may allow further simplifications. */ 9331 else if (GET_RTX_CLASS (GET_CODE (x)) == '<') 9332 return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1)); 9333 9334 /* If we couldn't simplify X any other way, just enclose it in a 9335 SUBREG. Normally, this SUBREG won't match, but some patterns may 9336 include an explicit SUBREG or we may simplify it further in combine. */ 9337 else 9338 { 9339 int word = 0; 9340 9341 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD) 9342 word = ((GET_MODE_SIZE (GET_MODE (x)) 9343 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD)) 9344 / UNITS_PER_WORD); 9345 return gen_rtx_SUBREG (mode, x, word); 9346 } 9347} 9348 9349/* Make an rtx expression. This is a subset of gen_rtx and only supports 9350 expressions of 1, 2, or 3 operands, each of which are rtx expressions. 9351 9352 If the identical expression was previously in the insn (in the undobuf), 9353 it will be returned. Only if it is not found will a new expression 9354 be made. */ 9355 9356/*VARARGS2*/ 9357static rtx 9358gen_rtx_combine VPROTO((enum rtx_code code, enum machine_mode mode, ...)) 9359{ 9360#ifndef ANSI_PROTOTYPES 9361 enum rtx_code code; 9362 enum machine_mode mode; 9363#endif 9364 va_list p; 9365 int n_args; 9366 rtx args[3]; 9367 int j; 9368 char *fmt; 9369 rtx rt; 9370 struct undo *undo; 9371 9372 VA_START (p, mode); 9373 9374#ifndef ANSI_PROTOTYPES 9375 code = va_arg (p, enum rtx_code); 9376 mode = va_arg (p, enum machine_mode); 9377#endif 9378 9379 n_args = GET_RTX_LENGTH (code); 9380 fmt = GET_RTX_FORMAT (code); 9381 9382 if (n_args == 0 || n_args > 3) 9383 abort (); 9384 9385 /* Get each arg and verify that it is supposed to be an expression. */ 9386 for (j = 0; j < n_args; j++) 9387 { 9388 if (*fmt++ != 'e') 9389 abort (); 9390 9391 args[j] = va_arg (p, rtx); 9392 } 9393 9394 /* See if this is in undobuf. Be sure we don't use objects that came 9395 from another insn; this could produce circular rtl structures. */ 9396 9397 for (undo = undobuf.undos; undo != undobuf.previous_undos; undo = undo->next) 9398 if (!undo->is_int 9399 && GET_CODE (undo->old_contents.r) == code 9400 && GET_MODE (undo->old_contents.r) == mode) 9401 { 9402 for (j = 0; j < n_args; j++) 9403 if (XEXP (undo->old_contents.r, j) != args[j]) 9404 break; 9405 9406 if (j == n_args) 9407 return undo->old_contents.r; 9408 } 9409 9410 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args. 9411 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */ 9412 rt = rtx_alloc (code); 9413 PUT_MODE (rt, mode); 9414 XEXP (rt, 0) = args[0]; 9415 if (n_args > 1) 9416 { 9417 XEXP (rt, 1) = args[1]; 9418 if (n_args > 2) 9419 XEXP (rt, 2) = args[2]; 9420 } 9421 return rt; 9422} 9423 9424/* These routines make binary and unary operations by first seeing if they 9425 fold; if not, a new expression is allocated. */ 9426 9427static rtx 9428gen_binary (code, mode, op0, op1) 9429 enum rtx_code code; 9430 enum machine_mode mode; 9431 rtx op0, op1; 9432{ 9433 rtx result; 9434 rtx tem; 9435 9436 if (GET_RTX_CLASS (code) == 'c' 9437 && (GET_CODE (op0) == CONST_INT 9438 || (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT))) 9439 tem = op0, op0 = op1, op1 = tem; 9440 9441 if (GET_RTX_CLASS (code) == '<') 9442 { 9443 enum machine_mode op_mode = GET_MODE (op0); 9444 9445 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get 9446 just (REL_OP X Y). */ 9447 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx) 9448 { 9449 op1 = XEXP (op0, 1); 9450 op0 = XEXP (op0, 0); 9451 op_mode = GET_MODE (op0); 9452 } 9453 9454 if (op_mode == VOIDmode) 9455 op_mode = GET_MODE (op1); 9456 result = simplify_relational_operation (code, op_mode, op0, op1); 9457 } 9458 else 9459 result = simplify_binary_operation (code, mode, op0, op1); 9460 9461 if (result) 9462 return result; 9463 9464 /* Put complex operands first and constants second. */ 9465 if (GET_RTX_CLASS (code) == 'c' 9466 && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT) 9467 || (GET_RTX_CLASS (GET_CODE (op0)) == 'o' 9468 && GET_RTX_CLASS (GET_CODE (op1)) != 'o') 9469 || (GET_CODE (op0) == SUBREG 9470 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o' 9471 && GET_RTX_CLASS (GET_CODE (op1)) != 'o'))) 9472 return gen_rtx_combine (code, mode, op1, op0); 9473 9474 /* If we are turning off bits already known off in OP0, we need not do 9475 an AND. */ 9476 else if (code == AND && GET_CODE (op1) == CONST_INT 9477 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 9478 && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0) 9479 return op0; 9480 9481 return gen_rtx_combine (code, mode, op0, op1); 9482} 9483 9484static rtx 9485gen_unary (code, mode, op0_mode, op0) 9486 enum rtx_code code; 9487 enum machine_mode mode, op0_mode; 9488 rtx op0; 9489{ 9490 rtx result = simplify_unary_operation (code, mode, op0, op0_mode); 9491 9492 if (result) 9493 return result; 9494 9495 return gen_rtx_combine (code, mode, op0); 9496} 9497 9498/* Simplify a comparison between *POP0 and *POP1 where CODE is the 9499 comparison code that will be tested. 9500 9501 The result is a possibly different comparison code to use. *POP0 and 9502 *POP1 may be updated. 9503 9504 It is possible that we might detect that a comparison is either always 9505 true or always false. However, we do not perform general constant 9506 folding in combine, so this knowledge isn't useful. Such tautologies 9507 should have been detected earlier. Hence we ignore all such cases. */ 9508 9509static enum rtx_code 9510simplify_comparison (code, pop0, pop1) 9511 enum rtx_code code; 9512 rtx *pop0; 9513 rtx *pop1; 9514{ 9515 rtx op0 = *pop0; 9516 rtx op1 = *pop1; 9517 rtx tem, tem1; 9518 int i; 9519 enum machine_mode mode, tmode; 9520 9521 /* Try a few ways of applying the same transformation to both operands. */ 9522 while (1) 9523 { 9524#ifndef WORD_REGISTER_OPERATIONS 9525 /* The test below this one won't handle SIGN_EXTENDs on these machines, 9526 so check specially. */ 9527 if (code != GTU && code != GEU && code != LTU && code != LEU 9528 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT 9529 && GET_CODE (XEXP (op0, 0)) == ASHIFT 9530 && GET_CODE (XEXP (op1, 0)) == ASHIFT 9531 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG 9532 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG 9533 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))) 9534 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0)))) 9535 && GET_CODE (XEXP (op0, 1)) == CONST_INT 9536 && GET_CODE (XEXP (op1, 1)) == CONST_INT 9537 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT 9538 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT 9539 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1)) 9540 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1)) 9541 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1)) 9542 && (INTVAL (XEXP (op0, 1)) 9543 == (GET_MODE_BITSIZE (GET_MODE (op0)) 9544 - (GET_MODE_BITSIZE 9545 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))))))) 9546 { 9547 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0)); 9548 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0)); 9549 } 9550#endif 9551 9552 /* If both operands are the same constant shift, see if we can ignore the 9553 shift. We can if the shift is a rotate or if the bits shifted out of 9554 this shift are known to be zero for both inputs and if the type of 9555 comparison is compatible with the shift. */ 9556 if (GET_CODE (op0) == GET_CODE (op1) 9557 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT 9558 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ)) 9559 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT) 9560 && (code != GT && code != LT && code != GE && code != LE)) 9561 || (GET_CODE (op0) == ASHIFTRT 9562 && (code != GTU && code != LTU 9563 && code != GEU && code != GEU))) 9564 && GET_CODE (XEXP (op0, 1)) == CONST_INT 9565 && INTVAL (XEXP (op0, 1)) >= 0 9566 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT 9567 && XEXP (op0, 1) == XEXP (op1, 1)) 9568 { 9569 enum machine_mode mode = GET_MODE (op0); 9570 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode); 9571 int shift_count = INTVAL (XEXP (op0, 1)); 9572 9573 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT) 9574 mask &= (mask >> shift_count) << shift_count; 9575 else if (GET_CODE (op0) == ASHIFT) 9576 mask = (mask & (mask << shift_count)) >> shift_count; 9577 9578 if ((nonzero_bits (XEXP (op0, 0), mode) & ~ mask) == 0 9579 && (nonzero_bits (XEXP (op1, 0), mode) & ~ mask) == 0) 9580 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0); 9581 else 9582 break; 9583 } 9584 9585 /* If both operands are AND's of a paradoxical SUBREG by constant, the 9586 SUBREGs are of the same mode, and, in both cases, the AND would 9587 be redundant if the comparison was done in the narrower mode, 9588 do the comparison in the narrower mode (e.g., we are AND'ing with 1 9589 and the operand's possibly nonzero bits are 0xffffff01; in that case 9590 if we only care about QImode, we don't need the AND). This case 9591 occurs if the output mode of an scc insn is not SImode and 9592 STORE_FLAG_VALUE == 1 (e.g., the 386). 9593 9594 Similarly, check for a case where the AND's are ZERO_EXTEND 9595 operations from some narrower mode even though a SUBREG is not 9596 present. */ 9597 9598 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND 9599 && GET_CODE (XEXP (op0, 1)) == CONST_INT 9600 && GET_CODE (XEXP (op1, 1)) == CONST_INT) 9601 { 9602 rtx inner_op0 = XEXP (op0, 0); 9603 rtx inner_op1 = XEXP (op1, 0); 9604 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1)); 9605 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1)); 9606 int changed = 0; 9607 9608 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG 9609 && (GET_MODE_SIZE (GET_MODE (inner_op0)) 9610 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0)))) 9611 && (GET_MODE (SUBREG_REG (inner_op0)) 9612 == GET_MODE (SUBREG_REG (inner_op1))) 9613 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0))) 9614 <= HOST_BITS_PER_WIDE_INT) 9615 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0), 9616 GET_MODE (SUBREG_REG (inner_op0))))) 9617 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1), 9618 GET_MODE (SUBREG_REG (inner_op1)))))) 9619 { 9620 op0 = SUBREG_REG (inner_op0); 9621 op1 = SUBREG_REG (inner_op1); 9622 9623 /* The resulting comparison is always unsigned since we masked 9624 off the original sign bit. */ 9625 code = unsigned_condition (code); 9626 9627 changed = 1; 9628 } 9629 9630 else if (c0 == c1) 9631 for (tmode = GET_CLASS_NARROWEST_MODE 9632 (GET_MODE_CLASS (GET_MODE (op0))); 9633 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode)) 9634 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode)) 9635 { 9636 op0 = gen_lowpart_for_combine (tmode, inner_op0); 9637 op1 = gen_lowpart_for_combine (tmode, inner_op1); 9638 code = unsigned_condition (code); 9639 changed = 1; 9640 break; 9641 } 9642 9643 if (! changed) 9644 break; 9645 } 9646 9647 /* If both operands are NOT, we can strip off the outer operation 9648 and adjust the comparison code for swapped operands; similarly for 9649 NEG, except that this must be an equality comparison. */ 9650 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT) 9651 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG 9652 && (code == EQ || code == NE))) 9653 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code); 9654 9655 else 9656 break; 9657 } 9658 9659 /* If the first operand is a constant, swap the operands and adjust the 9660 comparison code appropriately, but don't do this if the second operand 9661 is already a constant integer. */ 9662 if (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT) 9663 { 9664 tem = op0, op0 = op1, op1 = tem; 9665 code = swap_condition (code); 9666 } 9667 9668 /* We now enter a loop during which we will try to simplify the comparison. 9669 For the most part, we only are concerned with comparisons with zero, 9670 but some things may really be comparisons with zero but not start 9671 out looking that way. */ 9672 9673 while (GET_CODE (op1) == CONST_INT) 9674 { 9675 enum machine_mode mode = GET_MODE (op0); 9676 int mode_width = GET_MODE_BITSIZE (mode); 9677 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode); 9678 int equality_comparison_p; 9679 int sign_bit_comparison_p; 9680 int unsigned_comparison_p; 9681 HOST_WIDE_INT const_op; 9682 9683 /* We only want to handle integral modes. This catches VOIDmode, 9684 CCmode, and the floating-point modes. An exception is that we 9685 can handle VOIDmode if OP0 is a COMPARE or a comparison 9686 operation. */ 9687 9688 if (GET_MODE_CLASS (mode) != MODE_INT 9689 && ! (mode == VOIDmode 9690 && (GET_CODE (op0) == COMPARE 9691 || GET_RTX_CLASS (GET_CODE (op0)) == '<'))) 9692 break; 9693 9694 /* Get the constant we are comparing against and turn off all bits 9695 not on in our mode. */ 9696 const_op = INTVAL (op1); 9697 if (mode_width <= HOST_BITS_PER_WIDE_INT) 9698 const_op &= mask; 9699 9700 /* If we are comparing against a constant power of two and the value 9701 being compared can only have that single bit nonzero (e.g., it was 9702 `and'ed with that bit), we can replace this with a comparison 9703 with zero. */ 9704 if (const_op 9705 && (code == EQ || code == NE || code == GE || code == GEU 9706 || code == LT || code == LTU) 9707 && mode_width <= HOST_BITS_PER_WIDE_INT 9708 && exact_log2 (const_op) >= 0 9709 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op) 9710 { 9711 code = (code == EQ || code == GE || code == GEU ? NE : EQ); 9712 op1 = const0_rtx, const_op = 0; 9713 } 9714 9715 /* Similarly, if we are comparing a value known to be either -1 or 9716 0 with -1, change it to the opposite comparison against zero. */ 9717 9718 if (const_op == -1 9719 && (code == EQ || code == NE || code == GT || code == LE 9720 || code == GEU || code == LTU) 9721 && num_sign_bit_copies (op0, mode) == mode_width) 9722 { 9723 code = (code == EQ || code == LE || code == GEU ? NE : EQ); 9724 op1 = const0_rtx, const_op = 0; 9725 } 9726 9727 /* Do some canonicalizations based on the comparison code. We prefer 9728 comparisons against zero and then prefer equality comparisons. 9729 If we can reduce the size of a constant, we will do that too. */ 9730 9731 switch (code) 9732 { 9733 case LT: 9734 /* < C is equivalent to <= (C - 1) */ 9735 if (const_op > 0) 9736 { 9737 const_op -= 1; 9738 op1 = GEN_INT (const_op); 9739 code = LE; 9740 /* ... fall through to LE case below. */ 9741 } 9742 else 9743 break; 9744 9745 case LE: 9746 /* <= C is equivalent to < (C + 1); we do this for C < 0 */ 9747 if (const_op < 0) 9748 { 9749 const_op += 1; 9750 op1 = GEN_INT (const_op); 9751 code = LT; 9752 } 9753 9754 /* If we are doing a <= 0 comparison on a value known to have 9755 a zero sign bit, we can replace this with == 0. */ 9756 else if (const_op == 0 9757 && mode_width <= HOST_BITS_PER_WIDE_INT 9758 && (nonzero_bits (op0, mode) 9759 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0) 9760 code = EQ; 9761 break; 9762 9763 case GE: 9764 /* >= C is equivalent to > (C - 1). */ 9765 if (const_op > 0) 9766 { 9767 const_op -= 1; 9768 op1 = GEN_INT (const_op); 9769 code = GT; 9770 /* ... fall through to GT below. */ 9771 } 9772 else 9773 break; 9774 9775 case GT: 9776 /* > C is equivalent to >= (C + 1); we do this for C < 0*/ 9777 if (const_op < 0) 9778 { 9779 const_op += 1; 9780 op1 = GEN_INT (const_op); 9781 code = GE; 9782 } 9783 9784 /* If we are doing a > 0 comparison on a value known to have 9785 a zero sign bit, we can replace this with != 0. */ 9786 else if (const_op == 0 9787 && mode_width <= HOST_BITS_PER_WIDE_INT 9788 && (nonzero_bits (op0, mode) 9789 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0) 9790 code = NE; 9791 break; 9792 9793 case LTU: 9794 /* < C is equivalent to <= (C - 1). */ 9795 if (const_op > 0) 9796 { 9797 const_op -= 1; 9798 op1 = GEN_INT (const_op); 9799 code = LEU; 9800 /* ... fall through ... */ 9801 } 9802 9803 /* (unsigned) < 0x80000000 is equivalent to >= 0. */ 9804 else if ((mode_width <= HOST_BITS_PER_WIDE_INT) 9805 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1))) 9806 { 9807 const_op = 0, op1 = const0_rtx; 9808 code = GE; 9809 break; 9810 } 9811 else 9812 break; 9813 9814 case LEU: 9815 /* unsigned <= 0 is equivalent to == 0 */ 9816 if (const_op == 0) 9817 code = EQ; 9818 9819 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */ 9820 else if ((mode_width <= HOST_BITS_PER_WIDE_INT) 9821 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)) 9822 { 9823 const_op = 0, op1 = const0_rtx; 9824 code = GE; 9825 } 9826 break; 9827 9828 case GEU: 9829 /* >= C is equivalent to < (C - 1). */ 9830 if (const_op > 1) 9831 { 9832 const_op -= 1; 9833 op1 = GEN_INT (const_op); 9834 code = GTU; 9835 /* ... fall through ... */ 9836 } 9837 9838 /* (unsigned) >= 0x80000000 is equivalent to < 0. */ 9839 else if ((mode_width <= HOST_BITS_PER_WIDE_INT) 9840 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1))) 9841 { 9842 const_op = 0, op1 = const0_rtx; 9843 code = LT; 9844 break; 9845 } 9846 else 9847 break; 9848 9849 case GTU: 9850 /* unsigned > 0 is equivalent to != 0 */ 9851 if (const_op == 0) 9852 code = NE; 9853 9854 /* (unsigned) > 0x7fffffff is equivalent to < 0. */ 9855 else if ((mode_width <= HOST_BITS_PER_WIDE_INT) 9856 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)) 9857 { 9858 const_op = 0, op1 = const0_rtx; 9859 code = LT; 9860 } 9861 break; 9862 9863 default: 9864 break; 9865 } 9866 9867 /* Compute some predicates to simplify code below. */ 9868 9869 equality_comparison_p = (code == EQ || code == NE); 9870 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0); 9871 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU 9872 || code == LEU); 9873 9874 /* If this is a sign bit comparison and we can do arithmetic in 9875 MODE, say that we will only be needing the sign bit of OP0. */ 9876 if (sign_bit_comparison_p 9877 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) 9878 op0 = force_to_mode (op0, mode, 9879 ((HOST_WIDE_INT) 1 9880 << (GET_MODE_BITSIZE (mode) - 1)), 9881 NULL_RTX, 0); 9882 9883 /* Now try cases based on the opcode of OP0. If none of the cases 9884 does a "continue", we exit this loop immediately after the 9885 switch. */ 9886 9887 switch (GET_CODE (op0)) 9888 { 9889 case ZERO_EXTRACT: 9890 /* If we are extracting a single bit from a variable position in 9891 a constant that has only a single bit set and are comparing it 9892 with zero, we can convert this into an equality comparison 9893 between the position and the location of the single bit. */ 9894 9895 if (GET_CODE (XEXP (op0, 0)) == CONST_INT 9896 && XEXP (op0, 1) == const1_rtx 9897 && equality_comparison_p && const_op == 0 9898 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0) 9899 { 9900 if (BITS_BIG_ENDIAN) 9901 { 9902#ifdef HAVE_extzv 9903 mode = insn_operand_mode[(int) CODE_FOR_extzv][1]; 9904 if (mode == VOIDmode) 9905 mode = word_mode; 9906 i = (GET_MODE_BITSIZE (mode) - 1 - i); 9907#else 9908 i = BITS_PER_WORD - 1 - i; 9909#endif 9910 } 9911 9912 op0 = XEXP (op0, 2); 9913 op1 = GEN_INT (i); 9914 const_op = i; 9915 9916 /* Result is nonzero iff shift count is equal to I. */ 9917 code = reverse_condition (code); 9918 continue; 9919 } 9920 9921 /* ... fall through ... */ 9922 9923 case SIGN_EXTRACT: 9924 tem = expand_compound_operation (op0); 9925 if (tem != op0) 9926 { 9927 op0 = tem; 9928 continue; 9929 } 9930 break; 9931 9932 case NOT: 9933 /* If testing for equality, we can take the NOT of the constant. */ 9934 if (equality_comparison_p 9935 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0) 9936 { 9937 op0 = XEXP (op0, 0); 9938 op1 = tem; 9939 continue; 9940 } 9941 9942 /* If just looking at the sign bit, reverse the sense of the 9943 comparison. */ 9944 if (sign_bit_comparison_p) 9945 { 9946 op0 = XEXP (op0, 0); 9947 code = (code == GE ? LT : GE); 9948 continue; 9949 } 9950 break; 9951 9952 case NEG: 9953 /* If testing for equality, we can take the NEG of the constant. */ 9954 if (equality_comparison_p 9955 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0) 9956 { 9957 op0 = XEXP (op0, 0); 9958 op1 = tem; 9959 continue; 9960 } 9961 9962 /* The remaining cases only apply to comparisons with zero. */ 9963 if (const_op != 0) 9964 break; 9965 9966 /* When X is ABS or is known positive, 9967 (neg X) is < 0 if and only if X != 0. */ 9968 9969 if (sign_bit_comparison_p 9970 && (GET_CODE (XEXP (op0, 0)) == ABS 9971 || (mode_width <= HOST_BITS_PER_WIDE_INT 9972 && (nonzero_bits (XEXP (op0, 0), mode) 9973 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0))) 9974 { 9975 op0 = XEXP (op0, 0); 9976 code = (code == LT ? NE : EQ); 9977 continue; 9978 } 9979 9980 /* If we have NEG of something whose two high-order bits are the 9981 same, we know that "(-a) < 0" is equivalent to "a > 0". */ 9982 if (num_sign_bit_copies (op0, mode) >= 2) 9983 { 9984 op0 = XEXP (op0, 0); 9985 code = swap_condition (code); 9986 continue; 9987 } 9988 break; 9989 9990 case ROTATE: 9991 /* If we are testing equality and our count is a constant, we 9992 can perform the inverse operation on our RHS. */ 9993 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT 9994 && (tem = simplify_binary_operation (ROTATERT, mode, 9995 op1, XEXP (op0, 1))) != 0) 9996 { 9997 op0 = XEXP (op0, 0); 9998 op1 = tem; 9999 continue; 10000 } 10001 10002 /* If we are doing a < 0 or >= 0 comparison, it means we are testing 10003 a particular bit. Convert it to an AND of a constant of that 10004 bit. This will be converted into a ZERO_EXTRACT. */ 10005 if (const_op == 0 && sign_bit_comparison_p 10006 && GET_CODE (XEXP (op0, 1)) == CONST_INT 10007 && mode_width <= HOST_BITS_PER_WIDE_INT) 10008 { 10009 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 10010 ((HOST_WIDE_INT) 1 10011 << (mode_width - 1 10012 - INTVAL (XEXP (op0, 1))))); 10013 code = (code == LT ? NE : EQ); 10014 continue; 10015 } 10016 10017 /* ... fall through ... */ 10018 10019 case ABS: 10020 /* ABS is ignorable inside an equality comparison with zero. */ 10021 if (const_op == 0 && equality_comparison_p) 10022 { 10023 op0 = XEXP (op0, 0); 10024 continue; 10025 } 10026 break; 10027 10028 10029 case SIGN_EXTEND: 10030 /* Can simplify (compare (zero/sign_extend FOO) CONST) 10031 to (compare FOO CONST) if CONST fits in FOO's mode and we 10032 are either testing inequality or have an unsigned comparison 10033 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */ 10034 if (! unsigned_comparison_p 10035 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) 10036 <= HOST_BITS_PER_WIDE_INT) 10037 && ((unsigned HOST_WIDE_INT) const_op 10038 < (((unsigned HOST_WIDE_INT) 1 10039 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1))))) 10040 { 10041 op0 = XEXP (op0, 0); 10042 continue; 10043 } 10044 break; 10045 10046 case SUBREG: 10047 /* Check for the case where we are comparing A - C1 with C2, 10048 both constants are smaller than 1/2 the maximum positive 10049 value in MODE, and the comparison is equality or unsigned. 10050 In that case, if A is either zero-extended to MODE or has 10051 sufficient sign bits so that the high-order bit in MODE 10052 is a copy of the sign in the inner mode, we can prove that it is 10053 safe to do the operation in the wider mode. This simplifies 10054 many range checks. */ 10055 10056 if (mode_width <= HOST_BITS_PER_WIDE_INT 10057 && subreg_lowpart_p (op0) 10058 && GET_CODE (SUBREG_REG (op0)) == PLUS 10059 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT 10060 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0 10061 && (- INTVAL (XEXP (SUBREG_REG (op0), 1)) 10062 < (HOST_WIDE_INT)(GET_MODE_MASK (mode) / 2)) 10063 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2 10064 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0), 10065 GET_MODE (SUBREG_REG (op0))) 10066 & ~ GET_MODE_MASK (mode)) 10067 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0), 10068 GET_MODE (SUBREG_REG (op0))) 10069 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) 10070 - GET_MODE_BITSIZE (mode))))) 10071 { 10072 op0 = SUBREG_REG (op0); 10073 continue; 10074 } 10075 10076 /* If the inner mode is narrower and we are extracting the low part, 10077 we can treat the SUBREG as if it were a ZERO_EXTEND. */ 10078 if (subreg_lowpart_p (op0) 10079 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width) 10080 /* Fall through */ ; 10081 else 10082 break; 10083 10084 /* ... fall through ... */ 10085 10086 case ZERO_EXTEND: 10087 if ((unsigned_comparison_p || equality_comparison_p) 10088 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) 10089 <= HOST_BITS_PER_WIDE_INT) 10090 && ((unsigned HOST_WIDE_INT) const_op 10091 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0))))) 10092 { 10093 op0 = XEXP (op0, 0); 10094 continue; 10095 } 10096 break; 10097 10098 case PLUS: 10099 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do 10100 this for equality comparisons due to pathological cases involving 10101 overflows. */ 10102 if (equality_comparison_p 10103 && 0 != (tem = simplify_binary_operation (MINUS, mode, 10104 op1, XEXP (op0, 1)))) 10105 { 10106 op0 = XEXP (op0, 0); 10107 op1 = tem; 10108 continue; 10109 } 10110 10111 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */ 10112 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx 10113 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p) 10114 { 10115 op0 = XEXP (XEXP (op0, 0), 0); 10116 code = (code == LT ? EQ : NE); 10117 continue; 10118 } 10119 break; 10120 10121 case MINUS: 10122 /* (eq (minus A B) C) -> (eq A (plus B C)) or 10123 (eq B (minus A C)), whichever simplifies. We can only do 10124 this for equality comparisons due to pathological cases involving 10125 overflows. */ 10126 if (equality_comparison_p 10127 && 0 != (tem = simplify_binary_operation (PLUS, mode, 10128 XEXP (op0, 1), op1))) 10129 { 10130 op0 = XEXP (op0, 0); 10131 op1 = tem; 10132 continue; 10133 } 10134 10135 if (equality_comparison_p 10136 && 0 != (tem = simplify_binary_operation (MINUS, mode, 10137 XEXP (op0, 0), op1))) 10138 { 10139 op0 = XEXP (op0, 1); 10140 op1 = tem; 10141 continue; 10142 } 10143 10144 /* The sign bit of (minus (ashiftrt X C) X), where C is the number 10145 of bits in X minus 1, is one iff X > 0. */ 10146 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT 10147 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT 10148 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1 10149 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1))) 10150 { 10151 op0 = XEXP (op0, 1); 10152 code = (code == GE ? LE : GT); 10153 continue; 10154 } 10155 break; 10156 10157 case XOR: 10158 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification 10159 if C is zero or B is a constant. */ 10160 if (equality_comparison_p 10161 && 0 != (tem = simplify_binary_operation (XOR, mode, 10162 XEXP (op0, 1), op1))) 10163 { 10164 op0 = XEXP (op0, 0); 10165 op1 = tem; 10166 continue; 10167 } 10168 break; 10169 10170 case EQ: case NE: 10171 case LT: case LTU: case LE: case LEU: 10172 case GT: case GTU: case GE: case GEU: 10173 /* We can't do anything if OP0 is a condition code value, rather 10174 than an actual data value. */ 10175 if (const_op != 0 10176#ifdef HAVE_cc0 10177 || XEXP (op0, 0) == cc0_rtx 10178#endif 10179 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC) 10180 break; 10181 10182 /* Get the two operands being compared. */ 10183 if (GET_CODE (XEXP (op0, 0)) == COMPARE) 10184 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1); 10185 else 10186 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1); 10187 10188 /* Check for the cases where we simply want the result of the 10189 earlier test or the opposite of that result. */ 10190 if (code == NE 10191 || (code == EQ && reversible_comparison_p (op0)) 10192 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT 10193 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT 10194 && (STORE_FLAG_VALUE 10195 & (((HOST_WIDE_INT) 1 10196 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1)))) 10197 && (code == LT 10198 || (code == GE && reversible_comparison_p (op0))))) 10199 { 10200 code = (code == LT || code == NE 10201 ? GET_CODE (op0) : reverse_condition (GET_CODE (op0))); 10202 op0 = tem, op1 = tem1; 10203 continue; 10204 } 10205 break; 10206 10207 case IOR: 10208 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero 10209 iff X <= 0. */ 10210 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS 10211 && XEXP (XEXP (op0, 0), 1) == constm1_rtx 10212 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1))) 10213 { 10214 op0 = XEXP (op0, 1); 10215 code = (code == GE ? GT : LE); 10216 continue; 10217 } 10218 break; 10219 10220 case AND: 10221 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This 10222 will be converted to a ZERO_EXTRACT later. */ 10223 if (const_op == 0 && equality_comparison_p 10224 && GET_CODE (XEXP (op0, 0)) == ASHIFT 10225 && XEXP (XEXP (op0, 0), 0) == const1_rtx) 10226 { 10227 op0 = simplify_and_const_int 10228 (op0, mode, gen_rtx_combine (LSHIFTRT, mode, 10229 XEXP (op0, 1), 10230 XEXP (XEXP (op0, 0), 1)), 10231 (HOST_WIDE_INT) 1); 10232 continue; 10233 } 10234 10235 /* If we are comparing (and (lshiftrt X C1) C2) for equality with 10236 zero and X is a comparison and C1 and C2 describe only bits set 10237 in STORE_FLAG_VALUE, we can compare with X. */ 10238 if (const_op == 0 && equality_comparison_p 10239 && mode_width <= HOST_BITS_PER_WIDE_INT 10240 && GET_CODE (XEXP (op0, 1)) == CONST_INT 10241 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT 10242 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT 10243 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0 10244 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT) 10245 { 10246 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode)) 10247 << INTVAL (XEXP (XEXP (op0, 0), 1))); 10248 if ((~ STORE_FLAG_VALUE & mask) == 0 10249 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<' 10250 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0 10251 && GET_RTX_CLASS (GET_CODE (tem)) == '<'))) 10252 { 10253 op0 = XEXP (XEXP (op0, 0), 0); 10254 continue; 10255 } 10256 } 10257 10258 /* If we are doing an equality comparison of an AND of a bit equal 10259 to the sign bit, replace this with a LT or GE comparison of 10260 the underlying value. */ 10261 if (equality_comparison_p 10262 && const_op == 0 10263 && GET_CODE (XEXP (op0, 1)) == CONST_INT 10264 && mode_width <= HOST_BITS_PER_WIDE_INT 10265 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode)) 10266 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))) 10267 { 10268 op0 = XEXP (op0, 0); 10269 code = (code == EQ ? GE : LT); 10270 continue; 10271 } 10272 10273 /* If this AND operation is really a ZERO_EXTEND from a narrower 10274 mode, the constant fits within that mode, and this is either an 10275 equality or unsigned comparison, try to do this comparison in 10276 the narrower mode. */ 10277 if ((equality_comparison_p || unsigned_comparison_p) 10278 && GET_CODE (XEXP (op0, 1)) == CONST_INT 10279 && (i = exact_log2 ((INTVAL (XEXP (op0, 1)) 10280 & GET_MODE_MASK (mode)) 10281 + 1)) >= 0 10282 && const_op >> i == 0 10283 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode) 10284 { 10285 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0)); 10286 continue; 10287 } 10288 10289 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits 10290 in both M1 and M2 and the SUBREG is either paradoxical or 10291 represents the low part, permute the SUBREG and the AND and 10292 try again. */ 10293 if (GET_CODE (XEXP (op0, 0)) == SUBREG 10294 && ((mode_width 10295 >= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))) 10296#ifdef WORD_REGISTER_OPERATIONS 10297 || subreg_lowpart_p (XEXP (op0, 0)) 10298#endif 10299 ) 10300#ifndef WORD_REGISTER_OPERATIONS 10301 /* It is unsafe to commute the AND into the SUBREG if the SUBREG 10302 is paradoxical and WORD_REGISTER_OPERATIONS is not defined. 10303 As originally written the upper bits have a defined value 10304 due to the AND operation. However, if we commute the AND 10305 inside the SUBREG then they no longer have defined values 10306 and the meaning of the code has been changed. */ 10307 && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))) 10308 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))) 10309#endif 10310 && GET_CODE (XEXP (op0, 1)) == CONST_INT 10311 && mode_width <= HOST_BITS_PER_WIDE_INT 10312 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))) 10313 <= HOST_BITS_PER_WIDE_INT) 10314 && (INTVAL (XEXP (op0, 1)) & ~ mask) == 0 10315 && 0 == (~ GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0)))) 10316 & INTVAL (XEXP (op0, 1))) 10317 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) != mask 10318 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) 10319 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))) 10320 10321 { 10322 op0 10323 = gen_lowpart_for_combine 10324 (mode, 10325 gen_binary (AND, GET_MODE (SUBREG_REG (XEXP (op0, 0))), 10326 SUBREG_REG (XEXP (op0, 0)), XEXP (op0, 1))); 10327 continue; 10328 } 10329 10330 break; 10331 10332 case ASHIFT: 10333 /* If we have (compare (ashift FOO N) (const_int C)) and 10334 the high order N bits of FOO (N+1 if an inequality comparison) 10335 are known to be zero, we can do this by comparing FOO with C 10336 shifted right N bits so long as the low-order N bits of C are 10337 zero. */ 10338 if (GET_CODE (XEXP (op0, 1)) == CONST_INT 10339 && INTVAL (XEXP (op0, 1)) >= 0 10340 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p) 10341 < HOST_BITS_PER_WIDE_INT) 10342 && ((const_op 10343 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0) 10344 && mode_width <= HOST_BITS_PER_WIDE_INT 10345 && (nonzero_bits (XEXP (op0, 0), mode) 10346 & ~ (mask >> (INTVAL (XEXP (op0, 1)) 10347 + ! equality_comparison_p))) == 0) 10348 { 10349 const_op >>= INTVAL (XEXP (op0, 1)); 10350 op1 = GEN_INT (const_op); 10351 op0 = XEXP (op0, 0); 10352 continue; 10353 } 10354 10355 /* If we are doing a sign bit comparison, it means we are testing 10356 a particular bit. Convert it to the appropriate AND. */ 10357 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT 10358 && mode_width <= HOST_BITS_PER_WIDE_INT) 10359 { 10360 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 10361 ((HOST_WIDE_INT) 1 10362 << (mode_width - 1 10363 - INTVAL (XEXP (op0, 1))))); 10364 code = (code == LT ? NE : EQ); 10365 continue; 10366 } 10367 10368 /* If this an equality comparison with zero and we are shifting 10369 the low bit to the sign bit, we can convert this to an AND of the 10370 low-order bit. */ 10371 if (const_op == 0 && equality_comparison_p 10372 && GET_CODE (XEXP (op0, 1)) == CONST_INT 10373 && INTVAL (XEXP (op0, 1)) == mode_width - 1) 10374 { 10375 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 10376 (HOST_WIDE_INT) 1); 10377 continue; 10378 } 10379 break; 10380 10381 case ASHIFTRT: 10382 /* If this is an equality comparison with zero, we can do this 10383 as a logical shift, which might be much simpler. */ 10384 if (equality_comparison_p && const_op == 0 10385 && GET_CODE (XEXP (op0, 1)) == CONST_INT) 10386 { 10387 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode, 10388 XEXP (op0, 0), 10389 INTVAL (XEXP (op0, 1))); 10390 continue; 10391 } 10392 10393 /* If OP0 is a sign extension and CODE is not an unsigned comparison, 10394 do the comparison in a narrower mode. */ 10395 if (! unsigned_comparison_p 10396 && GET_CODE (XEXP (op0, 1)) == CONST_INT 10397 && GET_CODE (XEXP (op0, 0)) == ASHIFT 10398 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1) 10399 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)), 10400 MODE_INT, 1)) != BLKmode 10401 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode) 10402 || ((unsigned HOST_WIDE_INT) - const_op 10403 <= GET_MODE_MASK (tmode)))) 10404 { 10405 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0)); 10406 continue; 10407 } 10408 10409 /* ... fall through ... */ 10410 case LSHIFTRT: 10411 /* If we have (compare (xshiftrt FOO N) (const_int C)) and 10412 the low order N bits of FOO are known to be zero, we can do this 10413 by comparing FOO with C shifted left N bits so long as no 10414 overflow occurs. */ 10415 if (GET_CODE (XEXP (op0, 1)) == CONST_INT 10416 && INTVAL (XEXP (op0, 1)) >= 0 10417 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT 10418 && mode_width <= HOST_BITS_PER_WIDE_INT 10419 && (nonzero_bits (XEXP (op0, 0), mode) 10420 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0 10421 && (const_op == 0 10422 || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1)) 10423 < mode_width))) 10424 { 10425 const_op <<= INTVAL (XEXP (op0, 1)); 10426 op1 = GEN_INT (const_op); 10427 op0 = XEXP (op0, 0); 10428 continue; 10429 } 10430 10431 /* If we are using this shift to extract just the sign bit, we 10432 can replace this with an LT or GE comparison. */ 10433 if (const_op == 0 10434 && (equality_comparison_p || sign_bit_comparison_p) 10435 && GET_CODE (XEXP (op0, 1)) == CONST_INT 10436 && INTVAL (XEXP (op0, 1)) == mode_width - 1) 10437 { 10438 op0 = XEXP (op0, 0); 10439 code = (code == NE || code == GT ? LT : GE); 10440 continue; 10441 } 10442 break; 10443 10444 default: 10445 break; 10446 } 10447 10448 break; 10449 } 10450 10451 /* Now make any compound operations involved in this comparison. Then, 10452 check for an outmost SUBREG on OP0 that is not doing anything or is 10453 paradoxical. The latter case can only occur when it is known that the 10454 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG. 10455 We can never remove a SUBREG for a non-equality comparison because the 10456 sign bit is in a different place in the underlying object. */ 10457 10458 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET); 10459 op1 = make_compound_operation (op1, SET); 10460 10461 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0) 10462 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT 10463 && (code == NE || code == EQ) 10464 && ((GET_MODE_SIZE (GET_MODE (op0)) 10465 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0)))))) 10466 { 10467 op0 = SUBREG_REG (op0); 10468 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1); 10469 } 10470 10471 else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0) 10472 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT 10473 && (code == NE || code == EQ) 10474 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) 10475 <= HOST_BITS_PER_WIDE_INT) 10476 && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0))) 10477 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0 10478 && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)), 10479 op1), 10480 (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0))) 10481 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0)) 10482 op0 = SUBREG_REG (op0), op1 = tem; 10483 10484 /* We now do the opposite procedure: Some machines don't have compare 10485 insns in all modes. If OP0's mode is an integer mode smaller than a 10486 word and we can't do a compare in that mode, see if there is a larger 10487 mode for which we can do the compare. There are a number of cases in 10488 which we can use the wider mode. */ 10489 10490 mode = GET_MODE (op0); 10491 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT 10492 && GET_MODE_SIZE (mode) < UNITS_PER_WORD 10493 && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing) 10494 for (tmode = GET_MODE_WIDER_MODE (mode); 10495 (tmode != VOIDmode 10496 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT); 10497 tmode = GET_MODE_WIDER_MODE (tmode)) 10498 if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing) 10499 { 10500 /* If the only nonzero bits in OP0 and OP1 are those in the 10501 narrower mode and this is an equality or unsigned comparison, 10502 we can use the wider mode. Similarly for sign-extended 10503 values, in which case it is true for all comparisons. */ 10504 if (((code == EQ || code == NE 10505 || code == GEU || code == GTU || code == LEU || code == LTU) 10506 && (nonzero_bits (op0, tmode) & ~ GET_MODE_MASK (mode)) == 0 10507 && (nonzero_bits (op1, tmode) & ~ GET_MODE_MASK (mode)) == 0) 10508 || ((num_sign_bit_copies (op0, tmode) 10509 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode)) 10510 && (num_sign_bit_copies (op1, tmode) 10511 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode)))) 10512 { 10513 op0 = gen_lowpart_for_combine (tmode, op0); 10514 op1 = gen_lowpart_for_combine (tmode, op1); 10515 break; 10516 } 10517 10518 /* If this is a test for negative, we can make an explicit 10519 test of the sign bit. */ 10520 10521 if (op1 == const0_rtx && (code == LT || code == GE) 10522 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) 10523 { 10524 op0 = gen_binary (AND, tmode, 10525 gen_lowpart_for_combine (tmode, op0), 10526 GEN_INT ((HOST_WIDE_INT) 1 10527 << (GET_MODE_BITSIZE (mode) - 1))); 10528 code = (code == LT) ? NE : EQ; 10529 break; 10530 } 10531 } 10532 10533#ifdef CANONICALIZE_COMPARISON 10534 /* If this machine only supports a subset of valid comparisons, see if we 10535 can convert an unsupported one into a supported one. */ 10536 CANONICALIZE_COMPARISON (code, op0, op1); 10537#endif 10538 10539 *pop0 = op0; 10540 *pop1 = op1; 10541 10542 return code; 10543} 10544 10545/* Return 1 if we know that X, a comparison operation, is not operating 10546 on a floating-point value or is EQ or NE, meaning that we can safely 10547 reverse it. */ 10548 10549static int 10550reversible_comparison_p (x) 10551 rtx x; 10552{ 10553 if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT 10554 || flag_fast_math 10555 || GET_CODE (x) == NE || GET_CODE (x) == EQ) 10556 return 1; 10557 10558 switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0)))) 10559 { 10560 case MODE_INT: 10561 case MODE_PARTIAL_INT: 10562 case MODE_COMPLEX_INT: 10563 return 1; 10564 10565 case MODE_CC: 10566 /* If the mode of the condition codes tells us that this is safe, 10567 we need look no further. */ 10568 if (REVERSIBLE_CC_MODE (GET_MODE (XEXP (x, 0)))) 10569 return 1; 10570 10571 /* Otherwise try and find where the condition codes were last set and 10572 use that. */ 10573 x = get_last_value (XEXP (x, 0)); 10574 return (x && GET_CODE (x) == COMPARE 10575 && ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0)))); 10576 10577 default: 10578 return 0; 10579 } 10580} 10581 10582/* Utility function for following routine. Called when X is part of a value 10583 being stored into reg_last_set_value. Sets reg_last_set_table_tick 10584 for each register mentioned. Similar to mention_regs in cse.c */ 10585 10586static void 10587update_table_tick (x) 10588 rtx x; 10589{ 10590 register enum rtx_code code = GET_CODE (x); 10591 register char *fmt = GET_RTX_FORMAT (code); 10592 register int i; 10593 10594 if (code == REG) 10595 { 10596 int regno = REGNO (x); 10597 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER 10598 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1); 10599 10600 for (i = regno; i < endregno; i++) 10601 reg_last_set_table_tick[i] = label_tick; 10602 10603 return; 10604 } 10605 10606 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 10607 /* Note that we can't have an "E" in values stored; see 10608 get_last_value_validate. */ 10609 if (fmt[i] == 'e') 10610 update_table_tick (XEXP (x, i)); 10611} 10612 10613/* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we 10614 are saying that the register is clobbered and we no longer know its 10615 value. If INSN is zero, don't update reg_last_set; this is only permitted 10616 with VALUE also zero and is used to invalidate the register. */ 10617 10618static void 10619record_value_for_reg (reg, insn, value) 10620 rtx reg; 10621 rtx insn; 10622 rtx value; 10623{ 10624 int regno = REGNO (reg); 10625 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER 10626 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1); 10627 int i; 10628 10629 /* If VALUE contains REG and we have a previous value for REG, substitute 10630 the previous value. */ 10631 if (value && insn && reg_overlap_mentioned_p (reg, value)) 10632 { 10633 rtx tem; 10634 10635 /* Set things up so get_last_value is allowed to see anything set up to 10636 our insn. */ 10637 subst_low_cuid = INSN_CUID (insn); 10638 tem = get_last_value (reg); 10639 10640 if (tem) 10641 value = replace_rtx (copy_rtx (value), reg, tem); 10642 } 10643 10644 /* For each register modified, show we don't know its value, that 10645 we don't know about its bitwise content, that its value has been 10646 updated, and that we don't know the location of the death of the 10647 register. */ 10648 for (i = regno; i < endregno; i ++) 10649 { 10650 if (insn) 10651 reg_last_set[i] = insn; 10652 reg_last_set_value[i] = 0; 10653 reg_last_set_mode[i] = 0; 10654 reg_last_set_nonzero_bits[i] = 0; 10655 reg_last_set_sign_bit_copies[i] = 0; 10656 reg_last_death[i] = 0; 10657 } 10658 10659 /* Mark registers that are being referenced in this value. */ 10660 if (value) 10661 update_table_tick (value); 10662 10663 /* Now update the status of each register being set. 10664 If someone is using this register in this block, set this register 10665 to invalid since we will get confused between the two lives in this 10666 basic block. This makes using this register always invalid. In cse, we 10667 scan the table to invalidate all entries using this register, but this 10668 is too much work for us. */ 10669 10670 for (i = regno; i < endregno; i++) 10671 { 10672 reg_last_set_label[i] = label_tick; 10673 if (value && reg_last_set_table_tick[i] == label_tick) 10674 reg_last_set_invalid[i] = 1; 10675 else 10676 reg_last_set_invalid[i] = 0; 10677 } 10678 10679 /* The value being assigned might refer to X (like in "x++;"). In that 10680 case, we must replace it with (clobber (const_int 0)) to prevent 10681 infinite loops. */ 10682 if (value && ! get_last_value_validate (&value, insn, 10683 reg_last_set_label[regno], 0)) 10684 { 10685 value = copy_rtx (value); 10686 if (! get_last_value_validate (&value, insn, 10687 reg_last_set_label[regno], 1)) 10688 value = 0; 10689 } 10690 10691 /* For the main register being modified, update the value, the mode, the 10692 nonzero bits, and the number of sign bit copies. */ 10693 10694 reg_last_set_value[regno] = value; 10695 10696 if (value) 10697 { 10698 subst_low_cuid = INSN_CUID (insn); 10699 reg_last_set_mode[regno] = GET_MODE (reg); 10700 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, GET_MODE (reg)); 10701 reg_last_set_sign_bit_copies[regno] 10702 = num_sign_bit_copies (value, GET_MODE (reg)); 10703 } 10704} 10705 10706/* Used for communication between the following two routines. */ 10707static rtx record_dead_insn; 10708 10709/* Called via note_stores from record_dead_and_set_regs to handle one 10710 SET or CLOBBER in an insn. */ 10711 10712static void 10713record_dead_and_set_regs_1 (dest, setter) 10714 rtx dest, setter; 10715{ 10716 if (GET_CODE (dest) == SUBREG) 10717 dest = SUBREG_REG (dest); 10718 10719 if (GET_CODE (dest) == REG) 10720 { 10721 /* If we are setting the whole register, we know its value. Otherwise 10722 show that we don't know the value. We can handle SUBREG in 10723 some cases. */ 10724 if (GET_CODE (setter) == SET && dest == SET_DEST (setter)) 10725 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter)); 10726 else if (GET_CODE (setter) == SET 10727 && GET_CODE (SET_DEST (setter)) == SUBREG 10728 && SUBREG_REG (SET_DEST (setter)) == dest 10729 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD 10730 && subreg_lowpart_p (SET_DEST (setter))) 10731 record_value_for_reg (dest, record_dead_insn, 10732 gen_lowpart_for_combine (GET_MODE (dest), 10733 SET_SRC (setter))); 10734 else 10735 record_value_for_reg (dest, record_dead_insn, NULL_RTX); 10736 } 10737 else if (GET_CODE (dest) == MEM 10738 /* Ignore pushes, they clobber nothing. */ 10739 && ! push_operand (dest, GET_MODE (dest))) 10740 mem_last_set = INSN_CUID (record_dead_insn); 10741} 10742 10743/* Update the records of when each REG was most recently set or killed 10744 for the things done by INSN. This is the last thing done in processing 10745 INSN in the combiner loop. 10746 10747 We update reg_last_set, reg_last_set_value, reg_last_set_mode, 10748 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death, 10749 and also the similar information mem_last_set (which insn most recently 10750 modified memory) and last_call_cuid (which insn was the most recent 10751 subroutine call). */ 10752 10753static void 10754record_dead_and_set_regs (insn) 10755 rtx insn; 10756{ 10757 register rtx link; 10758 int i; 10759 10760 for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) 10761 { 10762 if (REG_NOTE_KIND (link) == REG_DEAD 10763 && GET_CODE (XEXP (link, 0)) == REG) 10764 { 10765 int regno = REGNO (XEXP (link, 0)); 10766 int endregno 10767 = regno + (regno < FIRST_PSEUDO_REGISTER 10768 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0))) 10769 : 1); 10770 10771 for (i = regno; i < endregno; i++) 10772 reg_last_death[i] = insn; 10773 } 10774 else if (REG_NOTE_KIND (link) == REG_INC) 10775 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX); 10776 } 10777 10778 if (GET_CODE (insn) == CALL_INSN) 10779 { 10780 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 10781 if (call_used_regs[i]) 10782 { 10783 reg_last_set_value[i] = 0; 10784 reg_last_set_mode[i] = 0; 10785 reg_last_set_nonzero_bits[i] = 0; 10786 reg_last_set_sign_bit_copies[i] = 0; 10787 reg_last_death[i] = 0; 10788 } 10789 10790 last_call_cuid = mem_last_set = INSN_CUID (insn); 10791 } 10792 10793 record_dead_insn = insn; 10794 note_stores (PATTERN (insn), record_dead_and_set_regs_1); 10795} 10796 10797/* Utility routine for the following function. Verify that all the registers 10798 mentioned in *LOC are valid when *LOC was part of a value set when 10799 label_tick == TICK. Return 0 if some are not. 10800 10801 If REPLACE is non-zero, replace the invalid reference with 10802 (clobber (const_int 0)) and return 1. This replacement is useful because 10803 we often can get useful information about the form of a value (e.g., if 10804 it was produced by a shift that always produces -1 or 0) even though 10805 we don't know exactly what registers it was produced from. */ 10806 10807static int 10808get_last_value_validate (loc, insn, tick, replace) 10809 rtx *loc; 10810 rtx insn; 10811 int tick; 10812 int replace; 10813{ 10814 rtx x = *loc; 10815 char *fmt = GET_RTX_FORMAT (GET_CODE (x)); 10816 int len = GET_RTX_LENGTH (GET_CODE (x)); 10817 int i; 10818 10819 if (GET_CODE (x) == REG) 10820 { 10821 int regno = REGNO (x); 10822 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER 10823 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1); 10824 int j; 10825 10826 for (j = regno; j < endregno; j++) 10827 if (reg_last_set_invalid[j] 10828 /* If this is a pseudo-register that was only set once and not 10829 live at the beginning of the function, it is always valid. */ 10830 || (! (regno >= FIRST_PSEUDO_REGISTER 10831 && REG_N_SETS (regno) == 1 10832 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, regno)) 10833 && reg_last_set_label[j] > tick)) 10834 { 10835 if (replace) 10836 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); 10837 return replace; 10838 } 10839 10840 return 1; 10841 } 10842 /* If this is a memory reference, make sure that there were 10843 no stores after it that might have clobbered the value. We don't 10844 have alias info, so we assume any store invalidates it. */ 10845 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x) 10846 && INSN_CUID (insn) <= mem_last_set) 10847 { 10848 if (replace) 10849 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); 10850 return replace; 10851 } 10852 10853 for (i = 0; i < len; i++) 10854 if ((fmt[i] == 'e' 10855 && get_last_value_validate (&XEXP (x, i), insn, tick, replace) == 0) 10856 /* Don't bother with these. They shouldn't occur anyway. */ 10857 || fmt[i] == 'E') 10858 return 0; 10859 10860 /* If we haven't found a reason for it to be invalid, it is valid. */ 10861 return 1; 10862} 10863 10864/* Get the last value assigned to X, if known. Some registers 10865 in the value may be replaced with (clobber (const_int 0)) if their value 10866 is known longer known reliably. */ 10867 10868static rtx 10869get_last_value (x) 10870 rtx x; 10871{ 10872 int regno; 10873 rtx value; 10874 10875 /* If this is a non-paradoxical SUBREG, get the value of its operand and 10876 then convert it to the desired mode. If this is a paradoxical SUBREG, 10877 we cannot predict what values the "extra" bits might have. */ 10878 if (GET_CODE (x) == SUBREG 10879 && subreg_lowpart_p (x) 10880 && (GET_MODE_SIZE (GET_MODE (x)) 10881 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) 10882 && (value = get_last_value (SUBREG_REG (x))) != 0) 10883 return gen_lowpart_for_combine (GET_MODE (x), value); 10884 10885 if (GET_CODE (x) != REG) 10886 return 0; 10887 10888 regno = REGNO (x); 10889 value = reg_last_set_value[regno]; 10890 10891 /* If we don't have a value, or if it isn't for this basic block and 10892 it's either a hard register, set more than once, or it's a live 10893 at the beginning of the function, return 0. 10894 10895 Because if it's not live at the beginnning of the function then the reg 10896 is always set before being used (is never used without being set). 10897 And, if it's set only once, and it's always set before use, then all 10898 uses must have the same last value, even if it's not from this basic 10899 block. */ 10900 10901 if (value == 0 10902 || (reg_last_set_label[regno] != label_tick 10903 && (regno < FIRST_PSEUDO_REGISTER 10904 || REG_N_SETS (regno) != 1 10905 || REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, regno)))) 10906 return 0; 10907 10908 /* If the value was set in a later insn than the ones we are processing, 10909 we can't use it even if the register was only set once. */ 10910 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid) 10911 return 0; 10912 10913 /* If the value has all its registers valid, return it. */ 10914 if (get_last_value_validate (&value, reg_last_set[regno], 10915 reg_last_set_label[regno], 0)) 10916 return value; 10917 10918 /* Otherwise, make a copy and replace any invalid register with 10919 (clobber (const_int 0)). If that fails for some reason, return 0. */ 10920 10921 value = copy_rtx (value); 10922 if (get_last_value_validate (&value, reg_last_set[regno], 10923 reg_last_set_label[regno], 1)) 10924 return value; 10925 10926 return 0; 10927} 10928 10929/* Return nonzero if expression X refers to a REG or to memory 10930 that is set in an instruction more recent than FROM_CUID. */ 10931 10932static int 10933use_crosses_set_p (x, from_cuid) 10934 register rtx x; 10935 int from_cuid; 10936{ 10937 register char *fmt; 10938 register int i; 10939 register enum rtx_code code = GET_CODE (x); 10940 10941 if (code == REG) 10942 { 10943 register int regno = REGNO (x); 10944 int endreg = regno + (regno < FIRST_PSEUDO_REGISTER 10945 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1); 10946 10947#ifdef PUSH_ROUNDING 10948 /* Don't allow uses of the stack pointer to be moved, 10949 because we don't know whether the move crosses a push insn. */ 10950 if (regno == STACK_POINTER_REGNUM) 10951 return 1; 10952#endif 10953 for (;regno < endreg; regno++) 10954 if (reg_last_set[regno] 10955 && INSN_CUID (reg_last_set[regno]) > from_cuid) 10956 return 1; 10957 return 0; 10958 } 10959 10960 if (code == MEM && mem_last_set > from_cuid) 10961 return 1; 10962 10963 fmt = GET_RTX_FORMAT (code); 10964 10965 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 10966 { 10967 if (fmt[i] == 'E') 10968 { 10969 register int j; 10970 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 10971 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid)) 10972 return 1; 10973 } 10974 else if (fmt[i] == 'e' 10975 && use_crosses_set_p (XEXP (x, i), from_cuid)) 10976 return 1; 10977 } 10978 return 0; 10979} 10980 10981/* Define three variables used for communication between the following 10982 routines. */ 10983 10984static int reg_dead_regno, reg_dead_endregno; 10985static int reg_dead_flag; 10986 10987/* Function called via note_stores from reg_dead_at_p. 10988 10989 If DEST is within [reg_dead_regno, reg_dead_endregno), set 10990 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */ 10991 10992static void 10993reg_dead_at_p_1 (dest, x) 10994 rtx dest; 10995 rtx x; 10996{ 10997 int regno, endregno; 10998 10999 if (GET_CODE (dest) != REG) 11000 return; 11001 11002 regno = REGNO (dest); 11003 endregno = regno + (regno < FIRST_PSEUDO_REGISTER 11004 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1); 11005 11006 if (reg_dead_endregno > regno && reg_dead_regno < endregno) 11007 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1; 11008} 11009 11010/* Return non-zero if REG is known to be dead at INSN. 11011 11012 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER 11013 referencing REG, it is dead. If we hit a SET referencing REG, it is 11014 live. Otherwise, see if it is live or dead at the start of the basic 11015 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS 11016 must be assumed to be always live. */ 11017 11018static int 11019reg_dead_at_p (reg, insn) 11020 rtx reg; 11021 rtx insn; 11022{ 11023 int block, i; 11024 11025 /* Set variables for reg_dead_at_p_1. */ 11026 reg_dead_regno = REGNO (reg); 11027 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER 11028 ? HARD_REGNO_NREGS (reg_dead_regno, 11029 GET_MODE (reg)) 11030 : 1); 11031 11032 reg_dead_flag = 0; 11033 11034 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */ 11035 if (reg_dead_regno < FIRST_PSEUDO_REGISTER) 11036 { 11037 for (i = reg_dead_regno; i < reg_dead_endregno; i++) 11038 if (TEST_HARD_REG_BIT (newpat_used_regs, i)) 11039 return 0; 11040 } 11041 11042 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or 11043 beginning of function. */ 11044 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER; 11045 insn = prev_nonnote_insn (insn)) 11046 { 11047 note_stores (PATTERN (insn), reg_dead_at_p_1); 11048 if (reg_dead_flag) 11049 return reg_dead_flag == 1 ? 1 : 0; 11050 11051 if (find_regno_note (insn, REG_DEAD, reg_dead_regno)) 11052 return 1; 11053 } 11054 11055 /* Get the basic block number that we were in. */ 11056 if (insn == 0) 11057 block = 0; 11058 else 11059 { 11060 for (block = 0; block < n_basic_blocks; block++) 11061 if (insn == BLOCK_HEAD (block)) 11062 break; 11063 11064 if (block == n_basic_blocks) 11065 return 0; 11066 } 11067 11068 for (i = reg_dead_regno; i < reg_dead_endregno; i++) 11069 if (REGNO_REG_SET_P (BASIC_BLOCK (block)->global_live_at_start, i)) 11070 return 0; 11071 11072 return 1; 11073} 11074 11075/* Note hard registers in X that are used. This code is similar to 11076 that in flow.c, but much simpler since we don't care about pseudos. */ 11077 11078static void 11079mark_used_regs_combine (x) 11080 rtx x; 11081{ 11082 register RTX_CODE code = GET_CODE (x); 11083 register int regno; 11084 int i; 11085 11086 switch (code) 11087 { 11088 case LABEL_REF: 11089 case SYMBOL_REF: 11090 case CONST_INT: 11091 case CONST: 11092 case CONST_DOUBLE: 11093 case PC: 11094 case ADDR_VEC: 11095 case ADDR_DIFF_VEC: 11096 case ASM_INPUT: 11097#ifdef HAVE_cc0 11098 /* CC0 must die in the insn after it is set, so we don't need to take 11099 special note of it here. */ 11100 case CC0: 11101#endif 11102 return; 11103 11104 case CLOBBER: 11105 /* If we are clobbering a MEM, mark any hard registers inside the 11106 address as used. */ 11107 if (GET_CODE (XEXP (x, 0)) == MEM) 11108 mark_used_regs_combine (XEXP (XEXP (x, 0), 0)); 11109 return; 11110 11111 case REG: 11112 regno = REGNO (x); 11113 /* A hard reg in a wide mode may really be multiple registers. 11114 If so, mark all of them just like the first. */ 11115 if (regno < FIRST_PSEUDO_REGISTER) 11116 { 11117 /* None of this applies to the stack, frame or arg pointers */ 11118 if (regno == STACK_POINTER_REGNUM 11119#if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM 11120 || regno == HARD_FRAME_POINTER_REGNUM 11121#endif 11122#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM 11123 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno]) 11124#endif 11125 || regno == FRAME_POINTER_REGNUM) 11126 return; 11127 11128 i = HARD_REGNO_NREGS (regno, GET_MODE (x)); 11129 while (i-- > 0) 11130 SET_HARD_REG_BIT (newpat_used_regs, regno + i); 11131 } 11132 return; 11133 11134 case SET: 11135 { 11136 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in 11137 the address. */ 11138 register rtx testreg = SET_DEST (x); 11139 11140 while (GET_CODE (testreg) == SUBREG 11141 || GET_CODE (testreg) == ZERO_EXTRACT 11142 || GET_CODE (testreg) == SIGN_EXTRACT 11143 || GET_CODE (testreg) == STRICT_LOW_PART) 11144 testreg = XEXP (testreg, 0); 11145 11146 if (GET_CODE (testreg) == MEM) 11147 mark_used_regs_combine (XEXP (testreg, 0)); 11148 11149 mark_used_regs_combine (SET_SRC (x)); 11150 } 11151 return; 11152 11153 default: 11154 break; 11155 } 11156 11157 /* Recursively scan the operands of this expression. */ 11158 11159 { 11160 register char *fmt = GET_RTX_FORMAT (code); 11161 11162 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 11163 { 11164 if (fmt[i] == 'e') 11165 mark_used_regs_combine (XEXP (x, i)); 11166 else if (fmt[i] == 'E') 11167 { 11168 register int j; 11169 11170 for (j = 0; j < XVECLEN (x, i); j++) 11171 mark_used_regs_combine (XVECEXP (x, i, j)); 11172 } 11173 } 11174 } 11175} 11176 11177 11178/* Remove register number REGNO from the dead registers list of INSN. 11179 11180 Return the note used to record the death, if there was one. */ 11181 11182rtx 11183remove_death (regno, insn) 11184 int regno; 11185 rtx insn; 11186{ 11187 register rtx note = find_regno_note (insn, REG_DEAD, regno); 11188 11189 if (note) 11190 { 11191 REG_N_DEATHS (regno)--; 11192 remove_note (insn, note); 11193 } 11194 11195 return note; 11196} 11197 11198/* For each register (hardware or pseudo) used within expression X, if its 11199 death is in an instruction with cuid between FROM_CUID (inclusive) and 11200 TO_INSN (exclusive), put a REG_DEAD note for that register in the 11201 list headed by PNOTES. 11202 11203 That said, don't move registers killed by maybe_kill_insn. 11204 11205 This is done when X is being merged by combination into TO_INSN. These 11206 notes will then be distributed as needed. */ 11207 11208static void 11209move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes) 11210 rtx x; 11211 rtx maybe_kill_insn; 11212 int from_cuid; 11213 rtx to_insn; 11214 rtx *pnotes; 11215{ 11216 register char *fmt; 11217 register int len, i; 11218 register enum rtx_code code = GET_CODE (x); 11219 11220 if (code == REG) 11221 { 11222 register int regno = REGNO (x); 11223 register rtx where_dead = reg_last_death[regno]; 11224 register rtx before_dead, after_dead; 11225 11226 /* Don't move the register if it gets killed in between from and to */ 11227 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn) 11228 && !reg_referenced_p (x, maybe_kill_insn)) 11229 return; 11230 11231 /* WHERE_DEAD could be a USE insn made by combine, so first we 11232 make sure that we have insns with valid INSN_CUID values. */ 11233 before_dead = where_dead; 11234 while (before_dead && INSN_UID (before_dead) > max_uid_cuid) 11235 before_dead = PREV_INSN (before_dead); 11236 after_dead = where_dead; 11237 while (after_dead && INSN_UID (after_dead) > max_uid_cuid) 11238 after_dead = NEXT_INSN (after_dead); 11239 11240 if (before_dead && after_dead 11241 && INSN_CUID (before_dead) >= from_cuid 11242 && (INSN_CUID (after_dead) < INSN_CUID (to_insn) 11243 || (where_dead != after_dead 11244 && INSN_CUID (after_dead) == INSN_CUID (to_insn)))) 11245 { 11246 rtx note = remove_death (regno, where_dead); 11247 11248 /* It is possible for the call above to return 0. This can occur 11249 when reg_last_death points to I2 or I1 that we combined with. 11250 In that case make a new note. 11251 11252 We must also check for the case where X is a hard register 11253 and NOTE is a death note for a range of hard registers 11254 including X. In that case, we must put REG_DEAD notes for 11255 the remaining registers in place of NOTE. */ 11256 11257 if (note != 0 && regno < FIRST_PSEUDO_REGISTER 11258 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0))) 11259 > GET_MODE_SIZE (GET_MODE (x)))) 11260 { 11261 int deadregno = REGNO (XEXP (note, 0)); 11262 int deadend 11263 = (deadregno + HARD_REGNO_NREGS (deadregno, 11264 GET_MODE (XEXP (note, 0)))); 11265 int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x)); 11266 int i; 11267 11268 for (i = deadregno; i < deadend; i++) 11269 if (i < regno || i >= ourend) 11270 REG_NOTES (where_dead) 11271 = gen_rtx_EXPR_LIST (REG_DEAD, 11272 gen_rtx_REG (reg_raw_mode[i], i), 11273 REG_NOTES (where_dead)); 11274 } 11275 /* If we didn't find any note, or if we found a REG_DEAD note that 11276 covers only part of the given reg, and we have a multi-reg hard 11277 register, then to be safe we must check for REG_DEAD notes 11278 for each register other than the first. They could have 11279 their own REG_DEAD notes lying around. */ 11280 else if ((note == 0 11281 || (note != 0 11282 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0))) 11283 < GET_MODE_SIZE (GET_MODE (x))))) 11284 && regno < FIRST_PSEUDO_REGISTER 11285 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1) 11286 { 11287 int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x)); 11288 int i, offset; 11289 rtx oldnotes = 0; 11290 11291 if (note) 11292 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))); 11293 else 11294 offset = 1; 11295 11296 for (i = regno + offset; i < ourend; i++) 11297 move_deaths (gen_rtx_REG (reg_raw_mode[i], i), 11298 maybe_kill_insn, from_cuid, to_insn, &oldnotes); 11299 } 11300 11301 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x)) 11302 { 11303 XEXP (note, 1) = *pnotes; 11304 *pnotes = note; 11305 } 11306 else 11307 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes); 11308 11309 REG_N_DEATHS (regno)++; 11310 } 11311 11312 return; 11313 } 11314 11315 else if (GET_CODE (x) == SET) 11316 { 11317 rtx dest = SET_DEST (x); 11318 11319 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes); 11320 11321 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG 11322 that accesses one word of a multi-word item, some 11323 piece of everything register in the expression is used by 11324 this insn, so remove any old death. */ 11325 11326 if (GET_CODE (dest) == ZERO_EXTRACT 11327 || GET_CODE (dest) == STRICT_LOW_PART 11328 || (GET_CODE (dest) == SUBREG 11329 && (((GET_MODE_SIZE (GET_MODE (dest)) 11330 + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 11331 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest))) 11332 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))) 11333 { 11334 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes); 11335 return; 11336 } 11337 11338 /* If this is some other SUBREG, we know it replaces the entire 11339 value, so use that as the destination. */ 11340 if (GET_CODE (dest) == SUBREG) 11341 dest = SUBREG_REG (dest); 11342 11343 /* If this is a MEM, adjust deaths of anything used in the address. 11344 For a REG (the only other possibility), the entire value is 11345 being replaced so the old value is not used in this insn. */ 11346 11347 if (GET_CODE (dest) == MEM) 11348 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid, 11349 to_insn, pnotes); 11350 return; 11351 } 11352 11353 else if (GET_CODE (x) == CLOBBER) 11354 return; 11355 11356 len = GET_RTX_LENGTH (code); 11357 fmt = GET_RTX_FORMAT (code); 11358 11359 for (i = 0; i < len; i++) 11360 { 11361 if (fmt[i] == 'E') 11362 { 11363 register int j; 11364 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 11365 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid, 11366 to_insn, pnotes); 11367 } 11368 else if (fmt[i] == 'e') 11369 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes); 11370 } 11371} 11372 11373/* Return 1 if X is the target of a bit-field assignment in BODY, the 11374 pattern of an insn. X must be a REG. */ 11375 11376static int 11377reg_bitfield_target_p (x, body) 11378 rtx x; 11379 rtx body; 11380{ 11381 int i; 11382 11383 if (GET_CODE (body) == SET) 11384 { 11385 rtx dest = SET_DEST (body); 11386 rtx target; 11387 int regno, tregno, endregno, endtregno; 11388 11389 if (GET_CODE (dest) == ZERO_EXTRACT) 11390 target = XEXP (dest, 0); 11391 else if (GET_CODE (dest) == STRICT_LOW_PART) 11392 target = SUBREG_REG (XEXP (dest, 0)); 11393 else 11394 return 0; 11395 11396 if (GET_CODE (target) == SUBREG) 11397 target = SUBREG_REG (target); 11398 11399 if (GET_CODE (target) != REG) 11400 return 0; 11401 11402 tregno = REGNO (target), regno = REGNO (x); 11403 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER) 11404 return target == x; 11405 11406 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target)); 11407 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x)); 11408 11409 return endregno > tregno && regno < endtregno; 11410 } 11411 11412 else if (GET_CODE (body) == PARALLEL) 11413 for (i = XVECLEN (body, 0) - 1; i >= 0; i--) 11414 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i))) 11415 return 1; 11416 11417 return 0; 11418} 11419 11420/* Given a chain of REG_NOTES originally from FROM_INSN, try to place them 11421 as appropriate. I3 and I2 are the insns resulting from the combination 11422 insns including FROM (I2 may be zero). 11423 11424 ELIM_I2 and ELIM_I1 are either zero or registers that we know will 11425 not need REG_DEAD notes because they are being substituted for. This 11426 saves searching in the most common cases. 11427 11428 Each note in the list is either ignored or placed on some insns, depending 11429 on the type of note. */ 11430 11431static void 11432distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1) 11433 rtx notes; 11434 rtx from_insn; 11435 rtx i3, i2; 11436 rtx elim_i2, elim_i1; 11437{ 11438 rtx note, next_note; 11439 rtx tem; 11440 11441 for (note = notes; note; note = next_note) 11442 { 11443 rtx place = 0, place2 = 0; 11444 11445 /* If this NOTE references a pseudo register, ensure it references 11446 the latest copy of that register. */ 11447 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG 11448 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER) 11449 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))]; 11450 11451 next_note = XEXP (note, 1); 11452 switch (REG_NOTE_KIND (note)) 11453 { 11454 case REG_BR_PROB: 11455 case REG_EXEC_COUNT: 11456 /* Doesn't matter much where we put this, as long as it's somewhere. 11457 It is preferable to keep these notes on branches, which is most 11458 likely to be i3. */ 11459 place = i3; 11460 break; 11461 11462 case REG_EH_REGION: 11463 /* This note must remain with the call. It should not be possible 11464 for both I2 and I3 to be a call. */ 11465 if (GET_CODE (i3) == CALL_INSN) 11466 place = i3; 11467 else if (i2 && GET_CODE (i2) == CALL_INSN) 11468 place = i2; 11469 else 11470 abort (); 11471 break; 11472 11473 case REG_UNUSED: 11474 /* Any clobbers for i3 may still exist, and so we must process 11475 REG_UNUSED notes from that insn. 11476 11477 Any clobbers from i2 or i1 can only exist if they were added by 11478 recog_for_combine. In that case, recog_for_combine created the 11479 necessary REG_UNUSED notes. Trying to keep any original 11480 REG_UNUSED notes from these insns can cause incorrect output 11481 if it is for the same register as the original i3 dest. 11482 In that case, we will notice that the register is set in i3, 11483 and then add a REG_UNUSED note for the destination of i3, which 11484 is wrong. However, it is possible to have REG_UNUSED notes from 11485 i2 or i1 for register which were both used and clobbered, so 11486 we keep notes from i2 or i1 if they will turn into REG_DEAD 11487 notes. */ 11488 11489 /* If this register is set or clobbered in I3, put the note there 11490 unless there is one already. */ 11491 if (reg_set_p (XEXP (note, 0), PATTERN (i3))) 11492 { 11493 if (from_insn != i3) 11494 break; 11495 11496 if (! (GET_CODE (XEXP (note, 0)) == REG 11497 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0))) 11498 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0)))) 11499 place = i3; 11500 } 11501 /* Otherwise, if this register is used by I3, then this register 11502 now dies here, so we must put a REG_DEAD note here unless there 11503 is one already. */ 11504 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)) 11505 && ! (GET_CODE (XEXP (note, 0)) == REG 11506 ? find_regno_note (i3, REG_DEAD, REGNO (XEXP (note, 0))) 11507 : find_reg_note (i3, REG_DEAD, XEXP (note, 0)))) 11508 { 11509 PUT_REG_NOTE_KIND (note, REG_DEAD); 11510 place = i3; 11511 } 11512 break; 11513 11514 case REG_EQUAL: 11515 case REG_EQUIV: 11516 case REG_NONNEG: 11517 case REG_NOALIAS: 11518 /* These notes say something about results of an insn. We can 11519 only support them if they used to be on I3 in which case they 11520 remain on I3. Otherwise they are ignored. 11521 11522 If the note refers to an expression that is not a constant, we 11523 must also ignore the note since we cannot tell whether the 11524 equivalence is still true. It might be possible to do 11525 slightly better than this (we only have a problem if I2DEST 11526 or I1DEST is present in the expression), but it doesn't 11527 seem worth the trouble. */ 11528 11529 if (from_insn == i3 11530 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0)))) 11531 place = i3; 11532 break; 11533 11534 case REG_INC: 11535 case REG_NO_CONFLICT: 11536 /* These notes say something about how a register is used. They must 11537 be present on any use of the register in I2 or I3. */ 11538 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))) 11539 place = i3; 11540 11541 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2))) 11542 { 11543 if (place) 11544 place2 = i2; 11545 else 11546 place = i2; 11547 } 11548 break; 11549 11550 case REG_LABEL: 11551 /* This can show up in several ways -- either directly in the 11552 pattern, or hidden off in the constant pool with (or without?) 11553 a REG_EQUAL note. */ 11554 /* ??? Ignore the without-reg_equal-note problem for now. */ 11555 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)) 11556 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX)) 11557 && GET_CODE (XEXP (tem, 0)) == LABEL_REF 11558 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))) 11559 place = i3; 11560 11561 if (i2 11562 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2)) 11563 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX)) 11564 && GET_CODE (XEXP (tem, 0)) == LABEL_REF 11565 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))) 11566 { 11567 if (place) 11568 place2 = i2; 11569 else 11570 place = i2; 11571 } 11572 break; 11573 11574 case REG_WAS_0: 11575 /* It is too much trouble to try to see if this note is still 11576 correct in all situations. It is better to simply delete it. */ 11577 break; 11578 11579 case REG_RETVAL: 11580 /* If the insn previously containing this note still exists, 11581 put it back where it was. Otherwise move it to the previous 11582 insn. Adjust the corresponding REG_LIBCALL note. */ 11583 if (GET_CODE (from_insn) != NOTE) 11584 place = from_insn; 11585 else 11586 { 11587 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX); 11588 place = prev_real_insn (from_insn); 11589 if (tem && place) 11590 XEXP (tem, 0) = place; 11591 } 11592 break; 11593 11594 case REG_LIBCALL: 11595 /* This is handled similarly to REG_RETVAL. */ 11596 if (GET_CODE (from_insn) != NOTE) 11597 place = from_insn; 11598 else 11599 { 11600 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX); 11601 place = next_real_insn (from_insn); 11602 if (tem && place) 11603 XEXP (tem, 0) = place; 11604 } 11605 break; 11606 11607 case REG_DEAD: 11608 /* If the register is used as an input in I3, it dies there. 11609 Similarly for I2, if it is non-zero and adjacent to I3. 11610 11611 If the register is not used as an input in either I3 or I2 11612 and it is not one of the registers we were supposed to eliminate, 11613 there are two possibilities. We might have a non-adjacent I2 11614 or we might have somehow eliminated an additional register 11615 from a computation. For example, we might have had A & B where 11616 we discover that B will always be zero. In this case we will 11617 eliminate the reference to A. 11618 11619 In both cases, we must search to see if we can find a previous 11620 use of A and put the death note there. */ 11621 11622 if (from_insn 11623 && GET_CODE (from_insn) == CALL_INSN 11624 && find_reg_fusage (from_insn, USE, XEXP (note, 0))) 11625 place = from_insn; 11626 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))) 11627 place = i3; 11628 else if (i2 != 0 && next_nonnote_insn (i2) == i3 11629 && reg_referenced_p (XEXP (note, 0), PATTERN (i2))) 11630 place = i2; 11631 11632 if (XEXP (note, 0) == elim_i2 || XEXP (note, 0) == elim_i1) 11633 break; 11634 11635 /* If the register is used in both I2 and I3 and it dies in I3, 11636 we might have added another reference to it. If reg_n_refs 11637 was 2, bump it to 3. This has to be correct since the 11638 register must have been set somewhere. The reason this is 11639 done is because local-alloc.c treats 2 references as a 11640 special case. */ 11641 11642 if (place == i3 && i2 != 0 && GET_CODE (XEXP (note, 0)) == REG 11643 && REG_N_REFS (REGNO (XEXP (note, 0)))== 2 11644 && reg_referenced_p (XEXP (note, 0), PATTERN (i2))) 11645 REG_N_REFS (REGNO (XEXP (note, 0))) = 3; 11646 11647 if (place == 0) 11648 { 11649 for (tem = prev_nonnote_insn (i3); 11650 place == 0 && tem 11651 && (GET_CODE (tem) == INSN || GET_CODE (tem) == CALL_INSN); 11652 tem = prev_nonnote_insn (tem)) 11653 { 11654 /* If the register is being set at TEM, see if that is all 11655 TEM is doing. If so, delete TEM. Otherwise, make this 11656 into a REG_UNUSED note instead. */ 11657 if (reg_set_p (XEXP (note, 0), PATTERN (tem))) 11658 { 11659 rtx set = single_set (tem); 11660 rtx inner_dest = 0; 11661#ifdef HAVE_cc0 11662 rtx cc0_setter = NULL_RTX; 11663#endif 11664 11665 if (set != 0) 11666 for (inner_dest = SET_DEST (set); 11667 GET_CODE (inner_dest) == STRICT_LOW_PART 11668 || GET_CODE (inner_dest) == SUBREG 11669 || GET_CODE (inner_dest) == ZERO_EXTRACT; 11670 inner_dest = XEXP (inner_dest, 0)) 11671 ; 11672 11673 /* Verify that it was the set, and not a clobber that 11674 modified the register. 11675 11676 CC0 targets must be careful to maintain setter/user 11677 pairs. If we cannot delete the setter due to side 11678 effects, mark the user with an UNUSED note instead 11679 of deleting it. */ 11680 11681 if (set != 0 && ! side_effects_p (SET_SRC (set)) 11682 && rtx_equal_p (XEXP (note, 0), inner_dest) 11683#ifdef HAVE_cc0 11684 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set)) 11685 || ((cc0_setter = prev_cc0_setter (tem)) != NULL 11686 && sets_cc0_p (PATTERN (cc0_setter)) > 0)) 11687#endif 11688 ) 11689 { 11690 /* Move the notes and links of TEM elsewhere. 11691 This might delete other dead insns recursively. 11692 First set the pattern to something that won't use 11693 any register. */ 11694 11695 PATTERN (tem) = pc_rtx; 11696 11697 distribute_notes (REG_NOTES (tem), tem, tem, 11698 NULL_RTX, NULL_RTX, NULL_RTX); 11699 distribute_links (LOG_LINKS (tem)); 11700 11701 PUT_CODE (tem, NOTE); 11702 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED; 11703 NOTE_SOURCE_FILE (tem) = 0; 11704 11705#ifdef HAVE_cc0 11706 /* Delete the setter too. */ 11707 if (cc0_setter) 11708 { 11709 PATTERN (cc0_setter) = pc_rtx; 11710 11711 distribute_notes (REG_NOTES (cc0_setter), 11712 cc0_setter, cc0_setter, 11713 NULL_RTX, NULL_RTX, NULL_RTX); 11714 distribute_links (LOG_LINKS (cc0_setter)); 11715 11716 PUT_CODE (cc0_setter, NOTE); 11717 NOTE_LINE_NUMBER (cc0_setter) = NOTE_INSN_DELETED; 11718 NOTE_SOURCE_FILE (cc0_setter) = 0; 11719 } 11720#endif 11721 } 11722 /* If the register is both set and used here, put the 11723 REG_DEAD note here, but place a REG_UNUSED note 11724 here too unless there already is one. */ 11725 else if (reg_referenced_p (XEXP (note, 0), 11726 PATTERN (tem))) 11727 { 11728 place = tem; 11729 11730 if (! find_regno_note (tem, REG_UNUSED, 11731 REGNO (XEXP (note, 0)))) 11732 REG_NOTES (tem) 11733 = gen_rtx_EXPR_LIST (REG_UNUSED, 11734 XEXP (note, 0), 11735 REG_NOTES (tem)); 11736 } 11737 else 11738 { 11739 PUT_REG_NOTE_KIND (note, REG_UNUSED); 11740 11741 /* If there isn't already a REG_UNUSED note, put one 11742 here. */ 11743 if (! find_regno_note (tem, REG_UNUSED, 11744 REGNO (XEXP (note, 0)))) 11745 place = tem; 11746 break; 11747 } 11748 } 11749 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem)) 11750 || (GET_CODE (tem) == CALL_INSN 11751 && find_reg_fusage (tem, USE, XEXP (note, 0)))) 11752 { 11753 place = tem; 11754 11755 /* If we are doing a 3->2 combination, and we have a 11756 register which formerly died in i3 and was not used 11757 by i2, which now no longer dies in i3 and is used in 11758 i2 but does not die in i2, and place is between i2 11759 and i3, then we may need to move a link from place to 11760 i2. */ 11761 if (i2 && INSN_UID (place) <= max_uid_cuid 11762 && INSN_CUID (place) > INSN_CUID (i2) 11763 && from_insn && INSN_CUID (from_insn) > INSN_CUID (i2) 11764 && reg_referenced_p (XEXP (note, 0), PATTERN (i2))) 11765 { 11766 rtx links = LOG_LINKS (place); 11767 LOG_LINKS (place) = 0; 11768 distribute_links (links); 11769 } 11770 break; 11771 } 11772 } 11773 11774 /* If we haven't found an insn for the death note and it 11775 is still a REG_DEAD note, but we have hit a CODE_LABEL, 11776 insert a USE insn for the register at that label and 11777 put the death node there. This prevents problems with 11778 call-state tracking in caller-save.c. */ 11779 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0 && tem != 0) 11780 { 11781 place 11782 = emit_insn_after (gen_rtx_USE (VOIDmode, XEXP (note, 0)), 11783 tem); 11784 11785 /* If this insn was emitted between blocks, then update 11786 BLOCK_HEAD of the current block to include it. */ 11787 if (BLOCK_END (this_basic_block - 1) == tem) 11788 BLOCK_HEAD (this_basic_block) = place; 11789 } 11790 } 11791 11792 /* If the register is set or already dead at PLACE, we needn't do 11793 anything with this note if it is still a REG_DEAD note. 11794 We can here if it is set at all, not if is it totally replace, 11795 which is what `dead_or_set_p' checks, so also check for it being 11796 set partially. */ 11797 11798 11799 if (place && REG_NOTE_KIND (note) == REG_DEAD) 11800 { 11801 int regno = REGNO (XEXP (note, 0)); 11802 11803 if (dead_or_set_p (place, XEXP (note, 0)) 11804 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place))) 11805 { 11806 /* Unless the register previously died in PLACE, clear 11807 reg_last_death. [I no longer understand why this is 11808 being done.] */ 11809 if (reg_last_death[regno] != place) 11810 reg_last_death[regno] = 0; 11811 place = 0; 11812 } 11813 else 11814 reg_last_death[regno] = place; 11815 11816 /* If this is a death note for a hard reg that is occupying 11817 multiple registers, ensure that we are still using all 11818 parts of the object. If we find a piece of the object 11819 that is unused, we must add a USE for that piece before 11820 PLACE and put the appropriate REG_DEAD note on it. 11821 11822 An alternative would be to put a REG_UNUSED for the pieces 11823 on the insn that set the register, but that can't be done if 11824 it is not in the same block. It is simpler, though less 11825 efficient, to add the USE insns. */ 11826 11827 if (place && regno < FIRST_PSEUDO_REGISTER 11828 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1) 11829 { 11830 int endregno 11831 = regno + HARD_REGNO_NREGS (regno, 11832 GET_MODE (XEXP (note, 0))); 11833 int all_used = 1; 11834 int i; 11835 11836 for (i = regno; i < endregno; i++) 11837 if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0) 11838 && ! find_regno_fusage (place, USE, i)) 11839 { 11840 rtx piece = gen_rtx_REG (reg_raw_mode[i], i); 11841 rtx p; 11842 11843 /* See if we already placed a USE note for this 11844 register in front of PLACE. */ 11845 for (p = place; 11846 GET_CODE (PREV_INSN (p)) == INSN 11847 && GET_CODE (PATTERN (PREV_INSN (p))) == USE; 11848 p = PREV_INSN (p)) 11849 if (rtx_equal_p (piece, 11850 XEXP (PATTERN (PREV_INSN (p)), 0))) 11851 { 11852 p = 0; 11853 break; 11854 } 11855 11856 if (p) 11857 { 11858 rtx use_insn 11859 = emit_insn_before (gen_rtx_USE (VOIDmode, 11860 piece), 11861 p); 11862 REG_NOTES (use_insn) 11863 = gen_rtx_EXPR_LIST (REG_DEAD, piece, 11864 REG_NOTES (use_insn)); 11865 } 11866 11867 all_used = 0; 11868 } 11869 11870 /* Check for the case where the register dying partially 11871 overlaps the register set by this insn. */ 11872 if (all_used) 11873 for (i = regno; i < endregno; i++) 11874 if (dead_or_set_regno_p (place, i)) 11875 { 11876 all_used = 0; 11877 break; 11878 } 11879 11880 if (! all_used) 11881 { 11882 /* Put only REG_DEAD notes for pieces that are 11883 still used and that are not already dead or set. */ 11884 11885 for (i = regno; i < endregno; i++) 11886 { 11887 rtx piece = gen_rtx_REG (reg_raw_mode[i], i); 11888 11889 if ((reg_referenced_p (piece, PATTERN (place)) 11890 || (GET_CODE (place) == CALL_INSN 11891 && find_reg_fusage (place, USE, piece))) 11892 && ! dead_or_set_p (place, piece) 11893 && ! reg_bitfield_target_p (piece, 11894 PATTERN (place))) 11895 REG_NOTES (place) 11896 = gen_rtx_EXPR_LIST (REG_DEAD, 11897 piece, REG_NOTES (place)); 11898 } 11899 11900 place = 0; 11901 } 11902 } 11903 } 11904 break; 11905 11906 default: 11907 /* Any other notes should not be present at this point in the 11908 compilation. */ 11909 abort (); 11910 } 11911 11912 if (place) 11913 { 11914 XEXP (note, 1) = REG_NOTES (place); 11915 REG_NOTES (place) = note; 11916 } 11917 else if ((REG_NOTE_KIND (note) == REG_DEAD 11918 || REG_NOTE_KIND (note) == REG_UNUSED) 11919 && GET_CODE (XEXP (note, 0)) == REG) 11920 REG_N_DEATHS (REGNO (XEXP (note, 0)))--; 11921 11922 if (place2) 11923 { 11924 if ((REG_NOTE_KIND (note) == REG_DEAD 11925 || REG_NOTE_KIND (note) == REG_UNUSED) 11926 && GET_CODE (XEXP (note, 0)) == REG) 11927 REG_N_DEATHS (REGNO (XEXP (note, 0)))++; 11928 11929 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note), 11930 REG_NOTE_KIND (note), 11931 XEXP (note, 0), 11932 REG_NOTES (place2)); 11933 } 11934 } 11935} 11936 11937/* Similarly to above, distribute the LOG_LINKS that used to be present on 11938 I3, I2, and I1 to new locations. This is also called in one case to 11939 add a link pointing at I3 when I3's destination is changed. */ 11940 11941static void 11942distribute_links (links) 11943 rtx links; 11944{ 11945 rtx link, next_link; 11946 11947 for (link = links; link; link = next_link) 11948 { 11949 rtx place = 0; 11950 rtx insn; 11951 rtx set, reg; 11952 11953 next_link = XEXP (link, 1); 11954 11955 /* If the insn that this link points to is a NOTE or isn't a single 11956 set, ignore it. In the latter case, it isn't clear what we 11957 can do other than ignore the link, since we can't tell which 11958 register it was for. Such links wouldn't be used by combine 11959 anyway. 11960 11961 It is not possible for the destination of the target of the link to 11962 have been changed by combine. The only potential of this is if we 11963 replace I3, I2, and I1 by I3 and I2. But in that case the 11964 destination of I2 also remains unchanged. */ 11965 11966 if (GET_CODE (XEXP (link, 0)) == NOTE 11967 || (set = single_set (XEXP (link, 0))) == 0) 11968 continue; 11969 11970 reg = SET_DEST (set); 11971 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT 11972 || GET_CODE (reg) == SIGN_EXTRACT 11973 || GET_CODE (reg) == STRICT_LOW_PART) 11974 reg = XEXP (reg, 0); 11975 11976 /* A LOG_LINK is defined as being placed on the first insn that uses 11977 a register and points to the insn that sets the register. Start 11978 searching at the next insn after the target of the link and stop 11979 when we reach a set of the register or the end of the basic block. 11980 11981 Note that this correctly handles the link that used to point from 11982 I3 to I2. Also note that not much searching is typically done here 11983 since most links don't point very far away. */ 11984 11985 for (insn = NEXT_INSN (XEXP (link, 0)); 11986 (insn && (this_basic_block == n_basic_blocks - 1 11987 || BLOCK_HEAD (this_basic_block + 1) != insn)); 11988 insn = NEXT_INSN (insn)) 11989 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i' 11990 && reg_overlap_mentioned_p (reg, PATTERN (insn))) 11991 { 11992 if (reg_referenced_p (reg, PATTERN (insn))) 11993 place = insn; 11994 break; 11995 } 11996 else if (GET_CODE (insn) == CALL_INSN 11997 && find_reg_fusage (insn, USE, reg)) 11998 { 11999 place = insn; 12000 break; 12001 } 12002 12003 /* If we found a place to put the link, place it there unless there 12004 is already a link to the same insn as LINK at that point. */ 12005 12006 if (place) 12007 { 12008 rtx link2; 12009 12010 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1)) 12011 if (XEXP (link2, 0) == XEXP (link, 0)) 12012 break; 12013 12014 if (link2 == 0) 12015 { 12016 XEXP (link, 1) = LOG_LINKS (place); 12017 LOG_LINKS (place) = link; 12018 12019 /* Set added_links_insn to the earliest insn we added a 12020 link to. */ 12021 if (added_links_insn == 0 12022 || INSN_CUID (added_links_insn) > INSN_CUID (place)) 12023 added_links_insn = place; 12024 } 12025 } 12026 } 12027} 12028 12029/* Compute INSN_CUID for INSN, which is an insn made by combine. */ 12030 12031static int 12032insn_cuid (insn) 12033 rtx insn; 12034{ 12035 while (insn != 0 && INSN_UID (insn) > max_uid_cuid 12036 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE) 12037 insn = NEXT_INSN (insn); 12038 12039 if (INSN_UID (insn) > max_uid_cuid) 12040 abort (); 12041 12042 return INSN_CUID (insn); 12043} 12044 12045void 12046dump_combine_stats (file) 12047 FILE *file; 12048{ 12049 fnotice 12050 (file, 12051 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n", 12052 combine_attempts, combine_merges, combine_extras, combine_successes); 12053} 12054 12055void 12056dump_combine_total_stats (file) 12057 FILE *file; 12058{ 12059 fnotice 12060 (file, 12061 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n", 12062 total_attempts, total_merges, total_extras, total_successes); 12063} 12064