1/* Communication between the Integrated Register Allocator (IRA) and
2   the rest of the compiler.
3   Copyright (C) 2006-2015 Free Software Foundation, Inc.
4   Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5
6This file is part of GCC.
7
8GCC is free software; you can redistribute it and/or modify it under
9the terms of the GNU General Public License as published by the Free
10Software Foundation; either version 3, or (at your option) any later
11version.
12
13GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14WARRANTY; without even the implied warranty of MERCHANTABILITY or
15FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
16for more details.
17
18You should have received a copy of the GNU General Public License
19along with GCC; see the file COPYING3.  If not see
20<http://www.gnu.org/licenses/>.  */
21
22#ifndef GCC_IRA_H
23#define GCC_IRA_H
24
25/* True when we use LRA instead of reload pass for the current
26   function.  */
27extern bool ira_use_lra_p;
28
29/* True if we have allocno conflicts.  It is false for non-optimized
30   mode or when the conflict table is too big.  */
31extern bool ira_conflicts_p;
32
33struct target_ira
34{
35  /* Map: hard register number -> allocno class it belongs to.  If the
36     corresponding class is NO_REGS, the hard register is not available
37     for allocation.  */
38  enum reg_class x_ira_hard_regno_allocno_class[FIRST_PSEUDO_REGISTER];
39
40  /* Number of allocno classes.  Allocno classes are register classes
41     which can be used for allocations of allocnos.  */
42  int x_ira_allocno_classes_num;
43
44  /* The array containing allocno classes.  Only first
45     IRA_ALLOCNO_CLASSES_NUM elements are used for this.  */
46  enum reg_class x_ira_allocno_classes[N_REG_CLASSES];
47
48  /* Map of all register classes to corresponding allocno classes
49     containing the given class.  If given class is not a subset of an
50     allocno class, we translate it into the cheapest allocno class.  */
51  enum reg_class x_ira_allocno_class_translate[N_REG_CLASSES];
52
53  /* Number of pressure classes.  Pressure classes are register
54     classes for which we calculate register pressure.  */
55  int x_ira_pressure_classes_num;
56
57  /* The array containing pressure classes.  Only first
58     IRA_PRESSURE_CLASSES_NUM elements are used for this.  */
59  enum reg_class x_ira_pressure_classes[N_REG_CLASSES];
60
61  /* Map of all register classes to corresponding pressure classes
62     containing the given class.  If given class is not a subset of an
63     pressure class, we translate it into the cheapest pressure
64     class.  */
65  enum reg_class x_ira_pressure_class_translate[N_REG_CLASSES];
66
67  /* Biggest pressure register class containing stack registers.
68     NO_REGS if there are no stack registers.  */
69  enum reg_class x_ira_stack_reg_pressure_class;
70
71  /* Maps: register class x machine mode -> maximal/minimal number of
72     hard registers of given class needed to store value of given
73     mode.  */
74  unsigned char x_ira_reg_class_max_nregs[N_REG_CLASSES][MAX_MACHINE_MODE];
75  unsigned char x_ira_reg_class_min_nregs[N_REG_CLASSES][MAX_MACHINE_MODE];
76
77  /* Array analogous to target hook TARGET_MEMORY_MOVE_COST.  */
78  short x_ira_memory_move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][2];
79
80  /* Array of number of hard registers of given class which are
81     available for the allocation.  The order is defined by the
82     allocation order.  */
83  short x_ira_class_hard_regs[N_REG_CLASSES][FIRST_PSEUDO_REGISTER];
84
85  /* The number of elements of the above array for given register
86     class.  */
87  int x_ira_class_hard_regs_num[N_REG_CLASSES];
88
89  /* Register class subset relation: TRUE if the first class is a subset
90     of the second one considering only hard registers available for the
91     allocation.  */
92  int x_ira_class_subset_p[N_REG_CLASSES][N_REG_CLASSES];
93
94  /* The biggest class inside of intersection of the two classes (that
95     is calculated taking only hard registers available for allocation
96     into account.  If the both classes contain no hard registers
97     available for allocation, the value is calculated with taking all
98     hard-registers including fixed ones into account.  */
99  enum reg_class x_ira_reg_class_subset[N_REG_CLASSES][N_REG_CLASSES];
100
101  /* True if the two classes (that is calculated taking only hard
102     registers available for allocation into account; are
103     intersected.  */
104  bool x_ira_reg_classes_intersect_p[N_REG_CLASSES][N_REG_CLASSES];
105
106  /* If class CL has a single allocatable register of mode M,
107     index [CL][M] gives the number of that register, otherwise it is -1.  */
108  short x_ira_class_singleton[N_REG_CLASSES][MAX_MACHINE_MODE];
109
110  /* Function specific hard registers can not be used for the register
111     allocation.  */
112  HARD_REG_SET x_ira_no_alloc_regs;
113
114  /* Array whose values are hard regset of hard registers available for
115     the allocation of given register class whose HARD_REGNO_MODE_OK
116     values for given mode are zero.  */
117  HARD_REG_SET x_ira_prohibited_class_mode_regs[N_REG_CLASSES][NUM_MACHINE_MODES];
118};
119
120extern struct target_ira default_target_ira;
121#if SWITCHABLE_TARGET
122extern struct target_ira *this_target_ira;
123#else
124#define this_target_ira (&default_target_ira)
125#endif
126
127#define ira_hard_regno_allocno_class \
128  (this_target_ira->x_ira_hard_regno_allocno_class)
129#define ira_allocno_classes_num \
130  (this_target_ira->x_ira_allocno_classes_num)
131#define ira_allocno_classes \
132  (this_target_ira->x_ira_allocno_classes)
133#define ira_allocno_class_translate \
134  (this_target_ira->x_ira_allocno_class_translate)
135#define ira_pressure_classes_num \
136  (this_target_ira->x_ira_pressure_classes_num)
137#define ira_pressure_classes \
138  (this_target_ira->x_ira_pressure_classes)
139#define ira_pressure_class_translate \
140  (this_target_ira->x_ira_pressure_class_translate)
141#define ira_stack_reg_pressure_class \
142  (this_target_ira->x_ira_stack_reg_pressure_class)
143#define ira_reg_class_max_nregs \
144  (this_target_ira->x_ira_reg_class_max_nregs)
145#define ira_reg_class_min_nregs \
146  (this_target_ira->x_ira_reg_class_min_nregs)
147#define ira_memory_move_cost \
148  (this_target_ira->x_ira_memory_move_cost)
149#define ira_class_hard_regs \
150  (this_target_ira->x_ira_class_hard_regs)
151#define ira_class_hard_regs_num \
152  (this_target_ira->x_ira_class_hard_regs_num)
153#define ira_class_subset_p \
154  (this_target_ira->x_ira_class_subset_p)
155#define ira_reg_class_subset \
156  (this_target_ira->x_ira_reg_class_subset)
157#define ira_reg_classes_intersect_p \
158  (this_target_ira->x_ira_reg_classes_intersect_p)
159#define ira_class_singleton \
160  (this_target_ira->x_ira_class_singleton)
161#define ira_no_alloc_regs \
162  (this_target_ira->x_ira_no_alloc_regs)
163#define ira_prohibited_class_mode_regs \
164  (this_target_ira->x_ira_prohibited_class_mode_regs)
165
166/* Major structure describing equivalence info for a pseudo.  */
167struct ira_reg_equiv_s
168{
169  /* True if we can use this equivalence.  */
170  bool defined_p;
171  /* True if the usage of the equivalence is profitable.  */
172  bool profitable_p;
173  /* Equiv. memory, constant, invariant, and initializing insns of
174     given pseudo-register or NULL_RTX.  */
175  rtx memory;
176  rtx constant;
177  rtx invariant;
178  /* Always NULL_RTX if defined_p is false.  */
179  rtx_insn_list *init_insns;
180};
181
182/* The length of the following array.  */
183extern int ira_reg_equiv_len;
184
185/* Info about equiv. info for each register.  */
186extern struct ira_reg_equiv_s *ira_reg_equiv;
187
188extern void ira_init_once (void);
189extern void ira_init (void);
190extern void ira_setup_eliminable_regset (void);
191extern rtx ira_eliminate_regs (rtx, machine_mode);
192extern void ira_set_pseudo_classes (bool, FILE *);
193extern void ira_expand_reg_equiv (void);
194extern void ira_update_equiv_info_by_shuffle_insn (int, int, rtx_insn *);
195
196extern void ira_sort_regnos_for_alter_reg (int *, int, unsigned int *);
197extern void ira_mark_allocation_change (int);
198extern void ira_mark_memory_move_deletion (int, int);
199extern bool ira_reassign_pseudos (int *, int, HARD_REG_SET, HARD_REG_SET *,
200				  HARD_REG_SET *, bitmap);
201extern rtx ira_reuse_stack_slot (int, unsigned int, unsigned int);
202extern void ira_mark_new_stack_slot (rtx, int, unsigned int);
203extern bool ira_better_spill_reload_regno_p (int *, int *, rtx, rtx, rtx);
204extern bool ira_bad_reload_regno (int, rtx, rtx);
205
206extern void ira_adjust_equiv_reg_cost (unsigned, int);
207
208/* ira-costs.c */
209extern void ira_costs_c_finalize (void);
210
211#endif /* GCC_IRA_H */
212