1/* Integrated Register Allocator (IRA) intercommunication header file. 2 Copyright (C) 2006-2015 Free Software Foundation, Inc. 3 Contributed by Vladimir Makarov <vmakarov@redhat.com>. 4 5This file is part of GCC. 6 7GCC is free software; you can redistribute it and/or modify it under 8the terms of the GNU General Public License as published by the Free 9Software Foundation; either version 3, or (at your option) any later 10version. 11 12GCC is distributed in the hope that it will be useful, but WITHOUT ANY 13WARRANTY; without even the implied warranty of MERCHANTABILITY or 14FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15for more details. 16 17You should have received a copy of the GNU General Public License 18along with GCC; see the file COPYING3. If not see 19<http://www.gnu.org/licenses/>. */ 20 21#ifndef GCC_IRA_INT_H 22#define GCC_IRA_INT_H 23 24#include "cfgloop.h" 25#include "ira.h" 26#include "alloc-pool.h" 27 28/* To provide consistency in naming, all IRA external variables, 29 functions, common typedefs start with prefix ira_. */ 30 31#ifdef ENABLE_CHECKING 32#define ENABLE_IRA_CHECKING 33#endif 34 35#ifdef ENABLE_IRA_CHECKING 36#define ira_assert(c) gcc_assert (c) 37#else 38/* Always define and include C, so that warnings for empty body in an 39 'if' statement and unused variable do not occur. */ 40#define ira_assert(c) ((void)(0 && (c))) 41#endif 42 43/* Compute register frequency from edge frequency FREQ. It is 44 analogous to REG_FREQ_FROM_BB. When optimizing for size, or 45 profile driven feedback is available and the function is never 46 executed, frequency is always equivalent. Otherwise rescale the 47 edge frequency. */ 48#define REG_FREQ_FROM_EDGE_FREQ(freq) \ 49 (optimize_function_for_size_p (cfun) \ 50 ? REG_FREQ_MAX : (freq * REG_FREQ_MAX / BB_FREQ_MAX) \ 51 ? (freq * REG_FREQ_MAX / BB_FREQ_MAX) : 1) 52 53/* A modified value of flag `-fira-verbose' used internally. */ 54extern int internal_flag_ira_verbose; 55 56/* Dump file of the allocator if it is not NULL. */ 57extern FILE *ira_dump_file; 58 59/* Typedefs for pointers to allocno live range, allocno, and copy of 60 allocnos. */ 61typedef struct live_range *live_range_t; 62typedef struct ira_allocno *ira_allocno_t; 63typedef struct ira_allocno_pref *ira_pref_t; 64typedef struct ira_allocno_copy *ira_copy_t; 65typedef struct ira_object *ira_object_t; 66 67/* Definition of vector of allocnos and copies. */ 68 69/* Typedef for pointer to the subsequent structure. */ 70typedef struct ira_loop_tree_node *ira_loop_tree_node_t; 71 72typedef unsigned short move_table[N_REG_CLASSES]; 73 74/* In general case, IRA is a regional allocator. The regions are 75 nested and form a tree. Currently regions are natural loops. The 76 following structure describes loop tree node (representing basic 77 block or loop). We need such tree because the loop tree from 78 cfgloop.h is not convenient for the optimization: basic blocks are 79 not a part of the tree from cfgloop.h. We also use the nodes for 80 storing additional information about basic blocks/loops for the 81 register allocation purposes. */ 82struct ira_loop_tree_node 83{ 84 /* The node represents basic block if children == NULL. */ 85 basic_block bb; /* NULL for loop. */ 86 /* NULL for BB or for loop tree root if we did not build CFG loop tree. */ 87 struct loop *loop; 88 /* NEXT/SUBLOOP_NEXT is the next node/loop-node of the same parent. 89 SUBLOOP_NEXT is always NULL for BBs. */ 90 ira_loop_tree_node_t subloop_next, next; 91 /* CHILDREN/SUBLOOPS is the first node/loop-node immediately inside 92 the node. They are NULL for BBs. */ 93 ira_loop_tree_node_t subloops, children; 94 /* The node immediately containing given node. */ 95 ira_loop_tree_node_t parent; 96 97 /* Loop level in range [0, ira_loop_tree_height). */ 98 int level; 99 100 /* All the following members are defined only for nodes representing 101 loops. */ 102 103 /* The loop number from CFG loop tree. The root number is 0. */ 104 int loop_num; 105 106 /* True if the loop was marked for removal from the register 107 allocation. */ 108 bool to_remove_p; 109 110 /* Allocnos in the loop corresponding to their regnos. If it is 111 NULL the loop does not form a separate register allocation region 112 (e.g. because it has abnormal enter/exit edges and we can not put 113 code for register shuffling on the edges if a different 114 allocation is used for a pseudo-register on different sides of 115 the edges). Caps are not in the map (remember we can have more 116 one cap with the same regno in a region). */ 117 ira_allocno_t *regno_allocno_map; 118 119 /* True if there is an entry to given loop not from its parent (or 120 grandparent) basic block. For example, it is possible for two 121 adjacent loops inside another loop. */ 122 bool entered_from_non_parent_p; 123 124 /* Maximal register pressure inside loop for given register class 125 (defined only for the pressure classes). */ 126 int reg_pressure[N_REG_CLASSES]; 127 128 /* Numbers of allocnos referred or living in the loop node (except 129 for its subloops). */ 130 bitmap all_allocnos; 131 132 /* Numbers of allocnos living at the loop borders. */ 133 bitmap border_allocnos; 134 135 /* Regnos of pseudos modified in the loop node (including its 136 subloops). */ 137 bitmap modified_regnos; 138 139 /* Numbers of copies referred in the corresponding loop. */ 140 bitmap local_copies; 141}; 142 143/* The root of the loop tree corresponding to the all function. */ 144extern ira_loop_tree_node_t ira_loop_tree_root; 145 146/* Height of the loop tree. */ 147extern int ira_loop_tree_height; 148 149/* All nodes representing basic blocks are referred through the 150 following array. We can not use basic block member `aux' for this 151 because it is used for insertion of insns on edges. */ 152extern ira_loop_tree_node_t ira_bb_nodes; 153 154/* Two access macros to the nodes representing basic blocks. */ 155#if defined ENABLE_IRA_CHECKING && (GCC_VERSION >= 2007) 156#define IRA_BB_NODE_BY_INDEX(index) __extension__ \ 157(({ ira_loop_tree_node_t _node = (&ira_bb_nodes[index]); \ 158 if (_node->children != NULL || _node->loop != NULL || _node->bb == NULL)\ 159 { \ 160 fprintf (stderr, \ 161 "\n%s: %d: error in %s: it is not a block node\n", \ 162 __FILE__, __LINE__, __FUNCTION__); \ 163 gcc_unreachable (); \ 164 } \ 165 _node; })) 166#else 167#define IRA_BB_NODE_BY_INDEX(index) (&ira_bb_nodes[index]) 168#endif 169 170#define IRA_BB_NODE(bb) IRA_BB_NODE_BY_INDEX ((bb)->index) 171 172/* All nodes representing loops are referred through the following 173 array. */ 174extern ira_loop_tree_node_t ira_loop_nodes; 175 176/* Two access macros to the nodes representing loops. */ 177#if defined ENABLE_IRA_CHECKING && (GCC_VERSION >= 2007) 178#define IRA_LOOP_NODE_BY_INDEX(index) __extension__ \ 179(({ ira_loop_tree_node_t const _node = (&ira_loop_nodes[index]); \ 180 if (_node->children == NULL || _node->bb != NULL \ 181 || (_node->loop == NULL && current_loops != NULL)) \ 182 { \ 183 fprintf (stderr, \ 184 "\n%s: %d: error in %s: it is not a loop node\n", \ 185 __FILE__, __LINE__, __FUNCTION__); \ 186 gcc_unreachable (); \ 187 } \ 188 _node; })) 189#else 190#define IRA_LOOP_NODE_BY_INDEX(index) (&ira_loop_nodes[index]) 191#endif 192 193#define IRA_LOOP_NODE(loop) IRA_LOOP_NODE_BY_INDEX ((loop)->num) 194 195 196/* The structure describes program points where a given allocno lives. 197 If the live ranges of two allocnos are intersected, the allocnos 198 are in conflict. */ 199struct live_range 200{ 201 /* Object whose live range is described by given structure. */ 202 ira_object_t object; 203 /* Program point range. */ 204 int start, finish; 205 /* Next structure describing program points where the allocno 206 lives. */ 207 live_range_t next; 208 /* Pointer to structures with the same start/finish. */ 209 live_range_t start_next, finish_next; 210}; 211 212/* Program points are enumerated by numbers from range 213 0..IRA_MAX_POINT-1. There are approximately two times more program 214 points than insns. Program points are places in the program where 215 liveness info can be changed. In most general case (there are more 216 complicated cases too) some program points correspond to places 217 where input operand dies and other ones correspond to places where 218 output operands are born. */ 219extern int ira_max_point; 220 221/* Arrays of size IRA_MAX_POINT mapping a program point to the allocno 222 live ranges with given start/finish point. */ 223extern live_range_t *ira_start_point_ranges, *ira_finish_point_ranges; 224 225/* A structure representing conflict information for an allocno 226 (or one of its subwords). */ 227struct ira_object 228{ 229 /* The allocno associated with this record. */ 230 ira_allocno_t allocno; 231 /* Vector of accumulated conflicting conflict_redords with NULL end 232 marker (if OBJECT_CONFLICT_VEC_P is true) or conflict bit vector 233 otherwise. */ 234 void *conflicts_array; 235 /* Pointer to structures describing at what program point the 236 object lives. We always maintain the list in such way that *the 237 ranges in the list are not intersected and ordered by decreasing 238 their program points*. */ 239 live_range_t live_ranges; 240 /* The subword within ALLOCNO which is represented by this object. 241 Zero means the lowest-order subword (or the entire allocno in case 242 it is not being tracked in subwords). */ 243 int subword; 244 /* Allocated size of the conflicts array. */ 245 unsigned int conflicts_array_size; 246 /* A unique number for every instance of this structure, which is used 247 to represent it in conflict bit vectors. */ 248 int id; 249 /* Before building conflicts, MIN and MAX are initialized to 250 correspondingly minimal and maximal points of the accumulated 251 live ranges. Afterwards, they hold the minimal and maximal ids 252 of other ira_objects that this one can conflict with. */ 253 int min, max; 254 /* Initial and accumulated hard registers conflicting with this 255 object and as a consequences can not be assigned to the allocno. 256 All non-allocatable hard regs and hard regs of register classes 257 different from given allocno one are included in the sets. */ 258 HARD_REG_SET conflict_hard_regs, total_conflict_hard_regs; 259 /* Number of accumulated conflicts in the vector of conflicting 260 objects. */ 261 int num_accumulated_conflicts; 262 /* TRUE if conflicts are represented by a vector of pointers to 263 ira_object structures. Otherwise, we use a bit vector indexed 264 by conflict ID numbers. */ 265 unsigned int conflict_vec_p : 1; 266}; 267 268/* A structure representing an allocno (allocation entity). Allocno 269 represents a pseudo-register in an allocation region. If 270 pseudo-register does not live in a region but it lives in the 271 nested regions, it is represented in the region by special allocno 272 called *cap*. There may be more one cap representing the same 273 pseudo-register in region. It means that the corresponding 274 pseudo-register lives in more one non-intersected subregion. */ 275struct ira_allocno 276{ 277 /* The allocno order number starting with 0. Each allocno has an 278 unique number and the number is never changed for the 279 allocno. */ 280 int num; 281 /* Regno for allocno or cap. */ 282 int regno; 283 /* Mode of the allocno which is the mode of the corresponding 284 pseudo-register. */ 285 ENUM_BITFIELD (machine_mode) mode : 8; 286 /* Widest mode of the allocno which in at least one case could be 287 for paradoxical subregs where wmode > mode. */ 288 ENUM_BITFIELD (machine_mode) wmode : 8; 289 /* Register class which should be used for allocation for given 290 allocno. NO_REGS means that we should use memory. */ 291 ENUM_BITFIELD (reg_class) aclass : 16; 292 /* During the reload, value TRUE means that we should not reassign a 293 hard register to the allocno got memory earlier. It is set up 294 when we removed memory-memory move insn before each iteration of 295 the reload. */ 296 unsigned int dont_reassign_p : 1; 297#ifdef STACK_REGS 298 /* Set to TRUE if allocno can't be assigned to the stack hard 299 register correspondingly in this region and area including the 300 region and all its subregions recursively. */ 301 unsigned int no_stack_reg_p : 1, total_no_stack_reg_p : 1; 302#endif 303 /* TRUE value means that there is no sense to spill the allocno 304 during coloring because the spill will result in additional 305 reloads in reload pass. */ 306 unsigned int bad_spill_p : 1; 307 /* TRUE if a hard register or memory has been assigned to the 308 allocno. */ 309 unsigned int assigned_p : 1; 310 /* TRUE if conflicts for given allocno are represented by vector of 311 pointers to the conflicting allocnos. Otherwise, we use a bit 312 vector where a bit with given index represents allocno with the 313 same number. */ 314 unsigned int conflict_vec_p : 1; 315 /* Hard register assigned to given allocno. Negative value means 316 that memory was allocated to the allocno. During the reload, 317 spilled allocno has value equal to the corresponding stack slot 318 number (0, ...) - 2. Value -1 is used for allocnos spilled by the 319 reload (at this point pseudo-register has only one allocno) which 320 did not get stack slot yet. */ 321 signed int hard_regno : 16; 322 /* Allocnos with the same regno are linked by the following member. 323 Allocnos corresponding to inner loops are first in the list (it 324 corresponds to depth-first traverse of the loops). */ 325 ira_allocno_t next_regno_allocno; 326 /* There may be different allocnos with the same regno in different 327 regions. Allocnos are bound to the corresponding loop tree node. 328 Pseudo-register may have only one regular allocno with given loop 329 tree node but more than one cap (see comments above). */ 330 ira_loop_tree_node_t loop_tree_node; 331 /* Accumulated usage references of the allocno. Here and below, 332 word 'accumulated' means info for given region and all nested 333 subregions. In this case, 'accumulated' means sum of references 334 of the corresponding pseudo-register in this region and in all 335 nested subregions recursively. */ 336 int nrefs; 337 /* Accumulated frequency of usage of the allocno. */ 338 int freq; 339 /* Minimal accumulated and updated costs of usage register of the 340 allocno class. */ 341 int class_cost, updated_class_cost; 342 /* Minimal accumulated, and updated costs of memory for the allocno. 343 At the allocation start, the original and updated costs are 344 equal. The updated cost may be changed after finishing 345 allocation in a region and starting allocation in a subregion. 346 The change reflects the cost of spill/restore code on the 347 subregion border if we assign memory to the pseudo in the 348 subregion. */ 349 int memory_cost, updated_memory_cost; 350 /* Accumulated number of points where the allocno lives and there is 351 excess pressure for its class. Excess pressure for a register 352 class at some point means that there are more allocnos of given 353 register class living at the point than number of hard-registers 354 of the class available for the allocation. */ 355 int excess_pressure_points_num; 356 /* Allocno hard reg preferences. */ 357 ira_pref_t allocno_prefs; 358 /* Copies to other non-conflicting allocnos. The copies can 359 represent move insn or potential move insn usually because of two 360 operand insn constraints. */ 361 ira_copy_t allocno_copies; 362 /* It is a allocno (cap) representing given allocno on upper loop tree 363 level. */ 364 ira_allocno_t cap; 365 /* It is a link to allocno (cap) on lower loop level represented by 366 given cap. Null if given allocno is not a cap. */ 367 ira_allocno_t cap_member; 368 /* The number of objects tracked in the following array. */ 369 int num_objects; 370 /* An array of structures describing conflict information and live 371 ranges for each object associated with the allocno. There may be 372 more than one such object in cases where the allocno represents a 373 multi-word register. */ 374 ira_object_t objects[2]; 375 /* Accumulated frequency of calls which given allocno 376 intersects. */ 377 int call_freq; 378 /* Accumulated number of the intersected calls. */ 379 int calls_crossed_num; 380 /* The number of calls across which it is live, but which should not 381 affect register preferences. */ 382 int cheap_calls_crossed_num; 383 /* Registers clobbered by intersected calls. */ 384 HARD_REG_SET crossed_calls_clobbered_regs; 385 /* Array of usage costs (accumulated and the one updated during 386 coloring) for each hard register of the allocno class. The 387 member value can be NULL if all costs are the same and equal to 388 CLASS_COST. For example, the costs of two different hard 389 registers can be different if one hard register is callee-saved 390 and another one is callee-used and the allocno lives through 391 calls. Another example can be case when for some insn the 392 corresponding pseudo-register value should be put in specific 393 register class (e.g. AREG for x86) which is a strict subset of 394 the allocno class (GENERAL_REGS for x86). We have updated costs 395 to reflect the situation when the usage cost of a hard register 396 is decreased because the allocno is connected to another allocno 397 by a copy and the another allocno has been assigned to the hard 398 register. */ 399 int *hard_reg_costs, *updated_hard_reg_costs; 400 /* Array of decreasing costs (accumulated and the one updated during 401 coloring) for allocnos conflicting with given allocno for hard 402 regno of the allocno class. The member value can be NULL if all 403 costs are the same. These costs are used to reflect preferences 404 of other allocnos not assigned yet during assigning to given 405 allocno. */ 406 int *conflict_hard_reg_costs, *updated_conflict_hard_reg_costs; 407 /* Different additional data. It is used to decrease size of 408 allocno data footprint. */ 409 void *add_data; 410}; 411 412 413/* All members of the allocno structures should be accessed only 414 through the following macros. */ 415#define ALLOCNO_NUM(A) ((A)->num) 416#define ALLOCNO_REGNO(A) ((A)->regno) 417#define ALLOCNO_REG(A) ((A)->reg) 418#define ALLOCNO_NEXT_REGNO_ALLOCNO(A) ((A)->next_regno_allocno) 419#define ALLOCNO_LOOP_TREE_NODE(A) ((A)->loop_tree_node) 420#define ALLOCNO_CAP(A) ((A)->cap) 421#define ALLOCNO_CAP_MEMBER(A) ((A)->cap_member) 422#define ALLOCNO_NREFS(A) ((A)->nrefs) 423#define ALLOCNO_FREQ(A) ((A)->freq) 424#define ALLOCNO_HARD_REGNO(A) ((A)->hard_regno) 425#define ALLOCNO_CALL_FREQ(A) ((A)->call_freq) 426#define ALLOCNO_CALLS_CROSSED_NUM(A) ((A)->calls_crossed_num) 427#define ALLOCNO_CHEAP_CALLS_CROSSED_NUM(A) ((A)->cheap_calls_crossed_num) 428#define ALLOCNO_CROSSED_CALLS_CLOBBERED_REGS(A) \ 429 ((A)->crossed_calls_clobbered_regs) 430#define ALLOCNO_MEM_OPTIMIZED_DEST(A) ((A)->mem_optimized_dest) 431#define ALLOCNO_MEM_OPTIMIZED_DEST_P(A) ((A)->mem_optimized_dest_p) 432#define ALLOCNO_SOMEWHERE_RENAMED_P(A) ((A)->somewhere_renamed_p) 433#define ALLOCNO_CHILD_RENAMED_P(A) ((A)->child_renamed_p) 434#define ALLOCNO_DONT_REASSIGN_P(A) ((A)->dont_reassign_p) 435#ifdef STACK_REGS 436#define ALLOCNO_NO_STACK_REG_P(A) ((A)->no_stack_reg_p) 437#define ALLOCNO_TOTAL_NO_STACK_REG_P(A) ((A)->total_no_stack_reg_p) 438#endif 439#define ALLOCNO_BAD_SPILL_P(A) ((A)->bad_spill_p) 440#define ALLOCNO_ASSIGNED_P(A) ((A)->assigned_p) 441#define ALLOCNO_MODE(A) ((A)->mode) 442#define ALLOCNO_WMODE(A) ((A)->wmode) 443#define ALLOCNO_PREFS(A) ((A)->allocno_prefs) 444#define ALLOCNO_COPIES(A) ((A)->allocno_copies) 445#define ALLOCNO_HARD_REG_COSTS(A) ((A)->hard_reg_costs) 446#define ALLOCNO_UPDATED_HARD_REG_COSTS(A) ((A)->updated_hard_reg_costs) 447#define ALLOCNO_CONFLICT_HARD_REG_COSTS(A) \ 448 ((A)->conflict_hard_reg_costs) 449#define ALLOCNO_UPDATED_CONFLICT_HARD_REG_COSTS(A) \ 450 ((A)->updated_conflict_hard_reg_costs) 451#define ALLOCNO_CLASS(A) ((A)->aclass) 452#define ALLOCNO_CLASS_COST(A) ((A)->class_cost) 453#define ALLOCNO_UPDATED_CLASS_COST(A) ((A)->updated_class_cost) 454#define ALLOCNO_MEMORY_COST(A) ((A)->memory_cost) 455#define ALLOCNO_UPDATED_MEMORY_COST(A) ((A)->updated_memory_cost) 456#define ALLOCNO_EXCESS_PRESSURE_POINTS_NUM(A) \ 457 ((A)->excess_pressure_points_num) 458#define ALLOCNO_OBJECT(A,N) ((A)->objects[N]) 459#define ALLOCNO_NUM_OBJECTS(A) ((A)->num_objects) 460#define ALLOCNO_ADD_DATA(A) ((A)->add_data) 461 462/* Typedef for pointer to the subsequent structure. */ 463typedef struct ira_emit_data *ira_emit_data_t; 464 465/* Allocno bound data used for emit pseudo live range split insns and 466 to flattening IR. */ 467struct ira_emit_data 468{ 469 /* TRUE if the allocno assigned to memory was a destination of 470 removed move (see ira-emit.c) at loop exit because the value of 471 the corresponding pseudo-register is not changed inside the 472 loop. */ 473 unsigned int mem_optimized_dest_p : 1; 474 /* TRUE if the corresponding pseudo-register has disjoint live 475 ranges and the other allocnos of the pseudo-register except this 476 one changed REG. */ 477 unsigned int somewhere_renamed_p : 1; 478 /* TRUE if allocno with the same REGNO in a subregion has been 479 renamed, in other words, got a new pseudo-register. */ 480 unsigned int child_renamed_p : 1; 481 /* Final rtx representation of the allocno. */ 482 rtx reg; 483 /* Non NULL if we remove restoring value from given allocno to 484 MEM_OPTIMIZED_DEST at loop exit (see ira-emit.c) because the 485 allocno value is not changed inside the loop. */ 486 ira_allocno_t mem_optimized_dest; 487}; 488 489#define ALLOCNO_EMIT_DATA(a) ((ira_emit_data_t) ALLOCNO_ADD_DATA (a)) 490 491/* Data used to emit live range split insns and to flattening IR. */ 492extern ira_emit_data_t ira_allocno_emit_data; 493 494/* Abbreviation for frequent emit data access. */ 495static inline rtx 496allocno_emit_reg (ira_allocno_t a) 497{ 498 return ALLOCNO_EMIT_DATA (a)->reg; 499} 500 501#define OBJECT_ALLOCNO(O) ((O)->allocno) 502#define OBJECT_SUBWORD(O) ((O)->subword) 503#define OBJECT_CONFLICT_ARRAY(O) ((O)->conflicts_array) 504#define OBJECT_CONFLICT_VEC(O) ((ira_object_t *)(O)->conflicts_array) 505#define OBJECT_CONFLICT_BITVEC(O) ((IRA_INT_TYPE *)(O)->conflicts_array) 506#define OBJECT_CONFLICT_ARRAY_SIZE(O) ((O)->conflicts_array_size) 507#define OBJECT_CONFLICT_VEC_P(O) ((O)->conflict_vec_p) 508#define OBJECT_NUM_CONFLICTS(O) ((O)->num_accumulated_conflicts) 509#define OBJECT_CONFLICT_HARD_REGS(O) ((O)->conflict_hard_regs) 510#define OBJECT_TOTAL_CONFLICT_HARD_REGS(O) ((O)->total_conflict_hard_regs) 511#define OBJECT_MIN(O) ((O)->min) 512#define OBJECT_MAX(O) ((O)->max) 513#define OBJECT_CONFLICT_ID(O) ((O)->id) 514#define OBJECT_LIVE_RANGES(O) ((O)->live_ranges) 515 516/* Map regno -> allocnos with given regno (see comments for 517 allocno member `next_regno_allocno'). */ 518extern ira_allocno_t *ira_regno_allocno_map; 519 520/* Array of references to all allocnos. The order number of the 521 allocno corresponds to the index in the array. Removed allocnos 522 have NULL element value. */ 523extern ira_allocno_t *ira_allocnos; 524 525/* The size of the previous array. */ 526extern int ira_allocnos_num; 527 528/* Map a conflict id to its corresponding ira_object structure. */ 529extern ira_object_t *ira_object_id_map; 530 531/* The size of the previous array. */ 532extern int ira_objects_num; 533 534/* The following structure represents a hard register preference of 535 allocno. The preference represent move insns or potential move 536 insns usually because of two operand insn constraints. One move 537 operand is a hard register. */ 538struct ira_allocno_pref 539{ 540 /* The unique order number of the preference node starting with 0. */ 541 int num; 542 /* Preferred hard register. */ 543 int hard_regno; 544 /* Accumulated execution frequency of insns from which the 545 preference created. */ 546 int freq; 547 /* Given allocno. */ 548 ira_allocno_t allocno; 549 /* All preferences with the same allocno are linked by the following 550 member. */ 551 ira_pref_t next_pref; 552}; 553 554/* Array of references to all allocno preferences. The order number 555 of the preference corresponds to the index in the array. */ 556extern ira_pref_t *ira_prefs; 557 558/* Size of the previous array. */ 559extern int ira_prefs_num; 560 561/* The following structure represents a copy of two allocnos. The 562 copies represent move insns or potential move insns usually because 563 of two operand insn constraints. To remove register shuffle, we 564 also create copies between allocno which is output of an insn and 565 allocno becoming dead in the insn. */ 566struct ira_allocno_copy 567{ 568 /* The unique order number of the copy node starting with 0. */ 569 int num; 570 /* Allocnos connected by the copy. The first allocno should have 571 smaller order number than the second one. */ 572 ira_allocno_t first, second; 573 /* Execution frequency of the copy. */ 574 int freq; 575 bool constraint_p; 576 /* It is a move insn which is an origin of the copy. The member 577 value for the copy representing two operand insn constraints or 578 for the copy created to remove register shuffle is NULL. In last 579 case the copy frequency is smaller than the corresponding insn 580 execution frequency. */ 581 rtx_insn *insn; 582 /* All copies with the same allocno as FIRST are linked by the two 583 following members. */ 584 ira_copy_t prev_first_allocno_copy, next_first_allocno_copy; 585 /* All copies with the same allocno as SECOND are linked by the two 586 following members. */ 587 ira_copy_t prev_second_allocno_copy, next_second_allocno_copy; 588 /* Region from which given copy is originated. */ 589 ira_loop_tree_node_t loop_tree_node; 590}; 591 592/* Array of references to all copies. The order number of the copy 593 corresponds to the index in the array. Removed copies have NULL 594 element value. */ 595extern ira_copy_t *ira_copies; 596 597/* Size of the previous array. */ 598extern int ira_copies_num; 599 600/* The following structure describes a stack slot used for spilled 601 pseudo-registers. */ 602struct ira_spilled_reg_stack_slot 603{ 604 /* pseudo-registers assigned to the stack slot. */ 605 bitmap_head spilled_regs; 606 /* RTL representation of the stack slot. */ 607 rtx mem; 608 /* Size of the stack slot. */ 609 unsigned int width; 610}; 611 612/* The number of elements in the following array. */ 613extern int ira_spilled_reg_stack_slots_num; 614 615/* The following array contains info about spilled pseudo-registers 616 stack slots used in current function so far. */ 617extern struct ira_spilled_reg_stack_slot *ira_spilled_reg_stack_slots; 618 619/* Correspondingly overall cost of the allocation, cost of the 620 allocnos assigned to hard-registers, cost of the allocnos assigned 621 to memory, cost of loads, stores and register move insns generated 622 for pseudo-register live range splitting (see ira-emit.c). */ 623extern int64_t ira_overall_cost; 624extern int64_t ira_reg_cost, ira_mem_cost; 625extern int64_t ira_load_cost, ira_store_cost, ira_shuffle_cost; 626extern int ira_move_loops_num, ira_additional_jumps_num; 627 628 629/* This page contains a bitset implementation called 'min/max sets' used to 630 record conflicts in IRA. 631 They are named min/maxs set since we keep track of a minimum and a maximum 632 bit number for each set representing the bounds of valid elements. Otherwise, 633 the implementation resembles sbitmaps in that we store an array of integers 634 whose bits directly represent the members of the set. */ 635 636/* The type used as elements in the array, and the number of bits in 637 this type. */ 638 639#define IRA_INT_BITS HOST_BITS_PER_WIDE_INT 640#define IRA_INT_TYPE HOST_WIDE_INT 641 642/* Set, clear or test bit number I in R, a bit vector of elements with 643 minimal index and maximal index equal correspondingly to MIN and 644 MAX. */ 645#if defined ENABLE_IRA_CHECKING && (GCC_VERSION >= 2007) 646 647#define SET_MINMAX_SET_BIT(R, I, MIN, MAX) __extension__ \ 648 (({ int _min = (MIN), _max = (MAX), _i = (I); \ 649 if (_i < _min || _i > _max) \ 650 { \ 651 fprintf (stderr, \ 652 "\n%s: %d: error in %s: %d not in range [%d,%d]\n", \ 653 __FILE__, __LINE__, __FUNCTION__, _i, _min, _max); \ 654 gcc_unreachable (); \ 655 } \ 656 ((R)[(unsigned) (_i - _min) / IRA_INT_BITS] \ 657 |= ((IRA_INT_TYPE) 1 << ((unsigned) (_i - _min) % IRA_INT_BITS))); })) 658 659 660#define CLEAR_MINMAX_SET_BIT(R, I, MIN, MAX) __extension__ \ 661 (({ int _min = (MIN), _max = (MAX), _i = (I); \ 662 if (_i < _min || _i > _max) \ 663 { \ 664 fprintf (stderr, \ 665 "\n%s: %d: error in %s: %d not in range [%d,%d]\n", \ 666 __FILE__, __LINE__, __FUNCTION__, _i, _min, _max); \ 667 gcc_unreachable (); \ 668 } \ 669 ((R)[(unsigned) (_i - _min) / IRA_INT_BITS] \ 670 &= ~((IRA_INT_TYPE) 1 << ((unsigned) (_i - _min) % IRA_INT_BITS))); })) 671 672#define TEST_MINMAX_SET_BIT(R, I, MIN, MAX) __extension__ \ 673 (({ int _min = (MIN), _max = (MAX), _i = (I); \ 674 if (_i < _min || _i > _max) \ 675 { \ 676 fprintf (stderr, \ 677 "\n%s: %d: error in %s: %d not in range [%d,%d]\n", \ 678 __FILE__, __LINE__, __FUNCTION__, _i, _min, _max); \ 679 gcc_unreachable (); \ 680 } \ 681 ((R)[(unsigned) (_i - _min) / IRA_INT_BITS] \ 682 & ((IRA_INT_TYPE) 1 << ((unsigned) (_i - _min) % IRA_INT_BITS))); })) 683 684#else 685 686#define SET_MINMAX_SET_BIT(R, I, MIN, MAX) \ 687 ((R)[(unsigned) ((I) - (MIN)) / IRA_INT_BITS] \ 688 |= ((IRA_INT_TYPE) 1 << ((unsigned) ((I) - (MIN)) % IRA_INT_BITS))) 689 690#define CLEAR_MINMAX_SET_BIT(R, I, MIN, MAX) \ 691 ((R)[(unsigned) ((I) - (MIN)) / IRA_INT_BITS] \ 692 &= ~((IRA_INT_TYPE) 1 << ((unsigned) ((I) - (MIN)) % IRA_INT_BITS))) 693 694#define TEST_MINMAX_SET_BIT(R, I, MIN, MAX) \ 695 ((R)[(unsigned) ((I) - (MIN)) / IRA_INT_BITS] \ 696 & ((IRA_INT_TYPE) 1 << ((unsigned) ((I) - (MIN)) % IRA_INT_BITS))) 697 698#endif 699 700/* The iterator for min/max sets. */ 701struct minmax_set_iterator { 702 703 /* Array containing the bit vector. */ 704 IRA_INT_TYPE *vec; 705 706 /* The number of the current element in the vector. */ 707 unsigned int word_num; 708 709 /* The number of bits in the bit vector. */ 710 unsigned int nel; 711 712 /* The current bit index of the bit vector. */ 713 unsigned int bit_num; 714 715 /* Index corresponding to the 1st bit of the bit vector. */ 716 int start_val; 717 718 /* The word of the bit vector currently visited. */ 719 unsigned IRA_INT_TYPE word; 720}; 721 722/* Initialize the iterator I for bit vector VEC containing minimal and 723 maximal values MIN and MAX. */ 724static inline void 725minmax_set_iter_init (minmax_set_iterator *i, IRA_INT_TYPE *vec, int min, 726 int max) 727{ 728 i->vec = vec; 729 i->word_num = 0; 730 i->nel = max < min ? 0 : max - min + 1; 731 i->start_val = min; 732 i->bit_num = 0; 733 i->word = i->nel == 0 ? 0 : vec[0]; 734} 735 736/* Return TRUE if we have more allocnos to visit, in which case *N is 737 set to the number of the element to be visited. Otherwise, return 738 FALSE. */ 739static inline bool 740minmax_set_iter_cond (minmax_set_iterator *i, int *n) 741{ 742 /* Skip words that are zeros. */ 743 for (; i->word == 0; i->word = i->vec[i->word_num]) 744 { 745 i->word_num++; 746 i->bit_num = i->word_num * IRA_INT_BITS; 747 748 /* If we have reached the end, break. */ 749 if (i->bit_num >= i->nel) 750 return false; 751 } 752 753 /* Skip bits that are zero. */ 754 for (; (i->word & 1) == 0; i->word >>= 1) 755 i->bit_num++; 756 757 *n = (int) i->bit_num + i->start_val; 758 759 return true; 760} 761 762/* Advance to the next element in the set. */ 763static inline void 764minmax_set_iter_next (minmax_set_iterator *i) 765{ 766 i->word >>= 1; 767 i->bit_num++; 768} 769 770/* Loop over all elements of a min/max set given by bit vector VEC and 771 their minimal and maximal values MIN and MAX. In each iteration, N 772 is set to the number of next allocno. ITER is an instance of 773 minmax_set_iterator used to iterate over the set. */ 774#define FOR_EACH_BIT_IN_MINMAX_SET(VEC, MIN, MAX, N, ITER) \ 775 for (minmax_set_iter_init (&(ITER), (VEC), (MIN), (MAX)); \ 776 minmax_set_iter_cond (&(ITER), &(N)); \ 777 minmax_set_iter_next (&(ITER))) 778 779struct target_ira_int { 780 ~target_ira_int (); 781 782 void free_ira_costs (); 783 void free_register_move_costs (); 784 785 /* Initialized once. It is a maximal possible size of the allocated 786 struct costs. */ 787 int x_max_struct_costs_size; 788 789 /* Allocated and initialized once, and used to initialize cost values 790 for each insn. */ 791 struct costs *x_init_cost; 792 793 /* Allocated once, and used for temporary purposes. */ 794 struct costs *x_temp_costs; 795 796 /* Allocated once, and used for the cost calculation. */ 797 struct costs *x_op_costs[MAX_RECOG_OPERANDS]; 798 struct costs *x_this_op_costs[MAX_RECOG_OPERANDS]; 799 800 /* Hard registers that can not be used for the register allocator for 801 all functions of the current compilation unit. */ 802 HARD_REG_SET x_no_unit_alloc_regs; 803 804 /* Map: hard regs X modes -> set of hard registers for storing value 805 of given mode starting with given hard register. */ 806 HARD_REG_SET (x_ira_reg_mode_hard_regset 807 [FIRST_PSEUDO_REGISTER][NUM_MACHINE_MODES]); 808 809 /* Maximum cost of moving from a register in one class to a register 810 in another class. Based on TARGET_REGISTER_MOVE_COST. */ 811 move_table *x_ira_register_move_cost[MAX_MACHINE_MODE]; 812 813 /* Similar, but here we don't have to move if the first index is a 814 subset of the second so in that case the cost is zero. */ 815 move_table *x_ira_may_move_in_cost[MAX_MACHINE_MODE]; 816 817 /* Similar, but here we don't have to move if the first index is a 818 superset of the second so in that case the cost is zero. */ 819 move_table *x_ira_may_move_out_cost[MAX_MACHINE_MODE]; 820 821 /* Keep track of the last mode we initialized move costs for. */ 822 int x_last_mode_for_init_move_cost; 823 824 /* Array analog of the macro MEMORY_MOVE_COST but they contain maximal 825 cost not minimal. */ 826 short int x_ira_max_memory_move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][2]; 827 828 /* Map class->true if class is a possible allocno class, false 829 otherwise. */ 830 bool x_ira_reg_allocno_class_p[N_REG_CLASSES]; 831 832 /* Map class->true if class is a pressure class, false otherwise. */ 833 bool x_ira_reg_pressure_class_p[N_REG_CLASSES]; 834 835 /* Array of the number of hard registers of given class which are 836 available for allocation. The order is defined by the hard 837 register numbers. */ 838 short x_ira_non_ordered_class_hard_regs[N_REG_CLASSES][FIRST_PSEUDO_REGISTER]; 839 840 /* Index (in ira_class_hard_regs; for given register class and hard 841 register (in general case a hard register can belong to several 842 register classes;. The index is negative for hard registers 843 unavailable for the allocation. */ 844 short x_ira_class_hard_reg_index[N_REG_CLASSES][FIRST_PSEUDO_REGISTER]; 845 846 /* Index [CL][M] contains R if R appears somewhere in a register of the form: 847 848 (reg:M R'), R' not in x_ira_prohibited_class_mode_regs[CL][M] 849 850 For example, if: 851 852 - (reg:M 2) is valid and occupies two registers; 853 - register 2 belongs to CL; and 854 - register 3 belongs to the same pressure class as CL 855 856 then (reg:M 2) contributes to [CL][M] and registers 2 and 3 will be 857 in the set. */ 858 HARD_REG_SET x_ira_useful_class_mode_regs[N_REG_CLASSES][NUM_MACHINE_MODES]; 859 860 /* The value is number of elements in the subsequent array. */ 861 int x_ira_important_classes_num; 862 863 /* The array containing all non-empty classes. Such classes is 864 important for calculation of the hard register usage costs. */ 865 enum reg_class x_ira_important_classes[N_REG_CLASSES]; 866 867 /* The array containing indexes of important classes in the previous 868 array. The array elements are defined only for important 869 classes. */ 870 int x_ira_important_class_nums[N_REG_CLASSES]; 871 872 /* Map class->true if class is an uniform class, false otherwise. */ 873 bool x_ira_uniform_class_p[N_REG_CLASSES]; 874 875 /* The biggest important class inside of intersection of the two 876 classes (that is calculated taking only hard registers available 877 for allocation into account;. If the both classes contain no hard 878 registers available for allocation, the value is calculated with 879 taking all hard-registers including fixed ones into account. */ 880 enum reg_class x_ira_reg_class_intersect[N_REG_CLASSES][N_REG_CLASSES]; 881 882 /* Classes with end marker LIM_REG_CLASSES which are intersected with 883 given class (the first index). That includes given class itself. 884 This is calculated taking only hard registers available for 885 allocation into account. */ 886 enum reg_class x_ira_reg_class_super_classes[N_REG_CLASSES][N_REG_CLASSES]; 887 888 /* The biggest (smallest) important class inside of (covering) union 889 of the two classes (that is calculated taking only hard registers 890 available for allocation into account). If the both classes 891 contain no hard registers available for allocation, the value is 892 calculated with taking all hard-registers including fixed ones 893 into account. In other words, the value is the corresponding 894 reg_class_subunion (reg_class_superunion) value. */ 895 enum reg_class x_ira_reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES]; 896 enum reg_class x_ira_reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES]; 897 898 /* For each reg class, table listing all the classes contained in it 899 (excluding the class itself. Non-allocatable registers are 900 excluded from the consideration). */ 901 enum reg_class x_alloc_reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES]; 902 903 /* Array whose values are hard regset of hard registers for which 904 move of the hard register in given mode into itself is 905 prohibited. */ 906 HARD_REG_SET x_ira_prohibited_mode_move_regs[NUM_MACHINE_MODES]; 907 908 /* Flag of that the above array has been initialized. */ 909 bool x_ira_prohibited_mode_move_regs_initialized_p; 910}; 911 912extern struct target_ira_int default_target_ira_int; 913#if SWITCHABLE_TARGET 914extern struct target_ira_int *this_target_ira_int; 915#else 916#define this_target_ira_int (&default_target_ira_int) 917#endif 918 919#define ira_reg_mode_hard_regset \ 920 (this_target_ira_int->x_ira_reg_mode_hard_regset) 921#define ira_register_move_cost \ 922 (this_target_ira_int->x_ira_register_move_cost) 923#define ira_max_memory_move_cost \ 924 (this_target_ira_int->x_ira_max_memory_move_cost) 925#define ira_may_move_in_cost \ 926 (this_target_ira_int->x_ira_may_move_in_cost) 927#define ira_may_move_out_cost \ 928 (this_target_ira_int->x_ira_may_move_out_cost) 929#define ira_reg_allocno_class_p \ 930 (this_target_ira_int->x_ira_reg_allocno_class_p) 931#define ira_reg_pressure_class_p \ 932 (this_target_ira_int->x_ira_reg_pressure_class_p) 933#define ira_non_ordered_class_hard_regs \ 934 (this_target_ira_int->x_ira_non_ordered_class_hard_regs) 935#define ira_class_hard_reg_index \ 936 (this_target_ira_int->x_ira_class_hard_reg_index) 937#define ira_useful_class_mode_regs \ 938 (this_target_ira_int->x_ira_useful_class_mode_regs) 939#define ira_important_classes_num \ 940 (this_target_ira_int->x_ira_important_classes_num) 941#define ira_important_classes \ 942 (this_target_ira_int->x_ira_important_classes) 943#define ira_important_class_nums \ 944 (this_target_ira_int->x_ira_important_class_nums) 945#define ira_uniform_class_p \ 946 (this_target_ira_int->x_ira_uniform_class_p) 947#define ira_reg_class_intersect \ 948 (this_target_ira_int->x_ira_reg_class_intersect) 949#define ira_reg_class_super_classes \ 950 (this_target_ira_int->x_ira_reg_class_super_classes) 951#define ira_reg_class_subunion \ 952 (this_target_ira_int->x_ira_reg_class_subunion) 953#define ira_reg_class_superunion \ 954 (this_target_ira_int->x_ira_reg_class_superunion) 955#define ira_prohibited_mode_move_regs \ 956 (this_target_ira_int->x_ira_prohibited_mode_move_regs) 957 958/* ira.c: */ 959 960extern void *ira_allocate (size_t); 961extern void ira_free (void *addr); 962extern bitmap ira_allocate_bitmap (void); 963extern void ira_free_bitmap (bitmap); 964extern void ira_print_disposition (FILE *); 965extern void ira_debug_disposition (void); 966extern void ira_debug_allocno_classes (void); 967extern void ira_init_register_move_cost (machine_mode); 968extern void ira_setup_alts (rtx_insn *insn, HARD_REG_SET &alts); 969extern int ira_get_dup_out_num (int op_num, HARD_REG_SET &alts); 970 971/* ira-build.c */ 972 973/* The current loop tree node and its regno allocno map. */ 974extern ira_loop_tree_node_t ira_curr_loop_tree_node; 975extern ira_allocno_t *ira_curr_regno_allocno_map; 976 977extern void ira_debug_pref (ira_pref_t); 978extern void ira_debug_prefs (void); 979extern void ira_debug_allocno_prefs (ira_allocno_t); 980 981extern void ira_debug_copy (ira_copy_t); 982extern void debug (ira_allocno_copy &ref); 983extern void debug (ira_allocno_copy *ptr); 984 985extern void ira_debug_copies (void); 986extern void ira_debug_allocno_copies (ira_allocno_t); 987extern void debug (ira_allocno &ref); 988extern void debug (ira_allocno *ptr); 989 990extern void ira_traverse_loop_tree (bool, ira_loop_tree_node_t, 991 void (*) (ira_loop_tree_node_t), 992 void (*) (ira_loop_tree_node_t)); 993extern ira_allocno_t ira_parent_allocno (ira_allocno_t); 994extern ira_allocno_t ira_parent_or_cap_allocno (ira_allocno_t); 995extern ira_allocno_t ira_create_allocno (int, bool, ira_loop_tree_node_t); 996extern void ira_create_allocno_objects (ira_allocno_t); 997extern void ira_set_allocno_class (ira_allocno_t, enum reg_class); 998extern bool ira_conflict_vector_profitable_p (ira_object_t, int); 999extern void ira_allocate_conflict_vec (ira_object_t, int); 1000extern void ira_allocate_object_conflicts (ira_object_t, int); 1001extern void ior_hard_reg_conflicts (ira_allocno_t, HARD_REG_SET *); 1002extern void ira_print_expanded_allocno (ira_allocno_t); 1003extern void ira_add_live_range_to_object (ira_object_t, int, int); 1004extern live_range_t ira_create_live_range (ira_object_t, int, int, 1005 live_range_t); 1006extern live_range_t ira_copy_live_range_list (live_range_t); 1007extern live_range_t ira_merge_live_ranges (live_range_t, live_range_t); 1008extern bool ira_live_ranges_intersect_p (live_range_t, live_range_t); 1009extern void ira_finish_live_range (live_range_t); 1010extern void ira_finish_live_range_list (live_range_t); 1011extern void ira_free_allocno_updated_costs (ira_allocno_t); 1012extern ira_pref_t ira_create_pref (ira_allocno_t, int, int); 1013extern void ira_add_allocno_pref (ira_allocno_t, int, int); 1014extern void ira_remove_pref (ira_pref_t); 1015extern void ira_remove_allocno_prefs (ira_allocno_t); 1016extern ira_copy_t ira_create_copy (ira_allocno_t, ira_allocno_t, 1017 int, bool, rtx_insn *, 1018 ira_loop_tree_node_t); 1019extern ira_copy_t ira_add_allocno_copy (ira_allocno_t, ira_allocno_t, int, 1020 bool, rtx_insn *, 1021 ira_loop_tree_node_t); 1022 1023extern int *ira_allocate_cost_vector (reg_class_t); 1024extern void ira_free_cost_vector (int *, reg_class_t); 1025 1026extern void ira_flattening (int, int); 1027extern bool ira_build (void); 1028extern void ira_destroy (void); 1029 1030/* ira-costs.c */ 1031extern void ira_init_costs_once (void); 1032extern void ira_init_costs (void); 1033extern void ira_costs (void); 1034extern void ira_tune_allocno_costs (void); 1035 1036/* ira-lives.c */ 1037 1038extern void ira_rebuild_start_finish_chains (void); 1039extern void ira_print_live_range_list (FILE *, live_range_t); 1040extern void debug (live_range &ref); 1041extern void debug (live_range *ptr); 1042extern void ira_debug_live_range_list (live_range_t); 1043extern void ira_debug_allocno_live_ranges (ira_allocno_t); 1044extern void ira_debug_live_ranges (void); 1045extern void ira_create_allocno_live_ranges (void); 1046extern void ira_compress_allocno_live_ranges (void); 1047extern void ira_finish_allocno_live_ranges (void); 1048extern void ira_implicitly_set_insn_hard_regs (HARD_REG_SET *, 1049 alternative_mask); 1050 1051/* ira-conflicts.c */ 1052extern void ira_debug_conflicts (bool); 1053extern void ira_build_conflicts (void); 1054 1055/* ira-color.c */ 1056extern void ira_debug_hard_regs_forest (void); 1057extern int ira_loop_edge_freq (ira_loop_tree_node_t, int, bool); 1058extern void ira_reassign_conflict_allocnos (int); 1059extern void ira_initiate_assign (void); 1060extern void ira_finish_assign (void); 1061extern void ira_color (void); 1062 1063/* ira-emit.c */ 1064extern void ira_initiate_emit_data (void); 1065extern void ira_finish_emit_data (void); 1066extern void ira_emit (bool); 1067 1068 1069 1070/* Return true if equivalence of pseudo REGNO is not a lvalue. */ 1071static inline bool 1072ira_equiv_no_lvalue_p (int regno) 1073{ 1074 if (regno >= ira_reg_equiv_len) 1075 return false; 1076 return (ira_reg_equiv[regno].constant != NULL_RTX 1077 || ira_reg_equiv[regno].invariant != NULL_RTX 1078 || (ira_reg_equiv[regno].memory != NULL_RTX 1079 && MEM_READONLY_P (ira_reg_equiv[regno].memory))); 1080} 1081 1082 1083 1084/* Initialize register costs for MODE if necessary. */ 1085static inline void 1086ira_init_register_move_cost_if_necessary (machine_mode mode) 1087{ 1088 if (ira_register_move_cost[mode] == NULL) 1089 ira_init_register_move_cost (mode); 1090} 1091 1092 1093 1094/* The iterator for all allocnos. */ 1095struct ira_allocno_iterator { 1096 /* The number of the current element in IRA_ALLOCNOS. */ 1097 int n; 1098}; 1099 1100/* Initialize the iterator I. */ 1101static inline void 1102ira_allocno_iter_init (ira_allocno_iterator *i) 1103{ 1104 i->n = 0; 1105} 1106 1107/* Return TRUE if we have more allocnos to visit, in which case *A is 1108 set to the allocno to be visited. Otherwise, return FALSE. */ 1109static inline bool 1110ira_allocno_iter_cond (ira_allocno_iterator *i, ira_allocno_t *a) 1111{ 1112 int n; 1113 1114 for (n = i->n; n < ira_allocnos_num; n++) 1115 if (ira_allocnos[n] != NULL) 1116 { 1117 *a = ira_allocnos[n]; 1118 i->n = n + 1; 1119 return true; 1120 } 1121 return false; 1122} 1123 1124/* Loop over all allocnos. In each iteration, A is set to the next 1125 allocno. ITER is an instance of ira_allocno_iterator used to iterate 1126 the allocnos. */ 1127#define FOR_EACH_ALLOCNO(A, ITER) \ 1128 for (ira_allocno_iter_init (&(ITER)); \ 1129 ira_allocno_iter_cond (&(ITER), &(A));) 1130 1131/* The iterator for all objects. */ 1132struct ira_object_iterator { 1133 /* The number of the current element in ira_object_id_map. */ 1134 int n; 1135}; 1136 1137/* Initialize the iterator I. */ 1138static inline void 1139ira_object_iter_init (ira_object_iterator *i) 1140{ 1141 i->n = 0; 1142} 1143 1144/* Return TRUE if we have more objects to visit, in which case *OBJ is 1145 set to the object to be visited. Otherwise, return FALSE. */ 1146static inline bool 1147ira_object_iter_cond (ira_object_iterator *i, ira_object_t *obj) 1148{ 1149 int n; 1150 1151 for (n = i->n; n < ira_objects_num; n++) 1152 if (ira_object_id_map[n] != NULL) 1153 { 1154 *obj = ira_object_id_map[n]; 1155 i->n = n + 1; 1156 return true; 1157 } 1158 return false; 1159} 1160 1161/* Loop over all objects. In each iteration, OBJ is set to the next 1162 object. ITER is an instance of ira_object_iterator used to iterate 1163 the objects. */ 1164#define FOR_EACH_OBJECT(OBJ, ITER) \ 1165 for (ira_object_iter_init (&(ITER)); \ 1166 ira_object_iter_cond (&(ITER), &(OBJ));) 1167 1168/* The iterator for objects associated with an allocno. */ 1169struct ira_allocno_object_iterator { 1170 /* The number of the element the allocno's object array. */ 1171 int n; 1172}; 1173 1174/* Initialize the iterator I. */ 1175static inline void 1176ira_allocno_object_iter_init (ira_allocno_object_iterator *i) 1177{ 1178 i->n = 0; 1179} 1180 1181/* Return TRUE if we have more objects to visit in allocno A, in which 1182 case *O is set to the object to be visited. Otherwise, return 1183 FALSE. */ 1184static inline bool 1185ira_allocno_object_iter_cond (ira_allocno_object_iterator *i, ira_allocno_t a, 1186 ira_object_t *o) 1187{ 1188 int n = i->n++; 1189 if (n < ALLOCNO_NUM_OBJECTS (a)) 1190 { 1191 *o = ALLOCNO_OBJECT (a, n); 1192 return true; 1193 } 1194 return false; 1195} 1196 1197/* Loop over all objects associated with allocno A. In each 1198 iteration, O is set to the next object. ITER is an instance of 1199 ira_allocno_object_iterator used to iterate the conflicts. */ 1200#define FOR_EACH_ALLOCNO_OBJECT(A, O, ITER) \ 1201 for (ira_allocno_object_iter_init (&(ITER)); \ 1202 ira_allocno_object_iter_cond (&(ITER), (A), &(O));) 1203 1204 1205/* The iterator for prefs. */ 1206struct ira_pref_iterator { 1207 /* The number of the current element in IRA_PREFS. */ 1208 int n; 1209}; 1210 1211/* Initialize the iterator I. */ 1212static inline void 1213ira_pref_iter_init (ira_pref_iterator *i) 1214{ 1215 i->n = 0; 1216} 1217 1218/* Return TRUE if we have more prefs to visit, in which case *PREF is 1219 set to the pref to be visited. Otherwise, return FALSE. */ 1220static inline bool 1221ira_pref_iter_cond (ira_pref_iterator *i, ira_pref_t *pref) 1222{ 1223 int n; 1224 1225 for (n = i->n; n < ira_prefs_num; n++) 1226 if (ira_prefs[n] != NULL) 1227 { 1228 *pref = ira_prefs[n]; 1229 i->n = n + 1; 1230 return true; 1231 } 1232 return false; 1233} 1234 1235/* Loop over all prefs. In each iteration, P is set to the next 1236 pref. ITER is an instance of ira_pref_iterator used to iterate 1237 the prefs. */ 1238#define FOR_EACH_PREF(P, ITER) \ 1239 for (ira_pref_iter_init (&(ITER)); \ 1240 ira_pref_iter_cond (&(ITER), &(P));) 1241 1242 1243/* The iterator for copies. */ 1244struct ira_copy_iterator { 1245 /* The number of the current element in IRA_COPIES. */ 1246 int n; 1247}; 1248 1249/* Initialize the iterator I. */ 1250static inline void 1251ira_copy_iter_init (ira_copy_iterator *i) 1252{ 1253 i->n = 0; 1254} 1255 1256/* Return TRUE if we have more copies to visit, in which case *CP is 1257 set to the copy to be visited. Otherwise, return FALSE. */ 1258static inline bool 1259ira_copy_iter_cond (ira_copy_iterator *i, ira_copy_t *cp) 1260{ 1261 int n; 1262 1263 for (n = i->n; n < ira_copies_num; n++) 1264 if (ira_copies[n] != NULL) 1265 { 1266 *cp = ira_copies[n]; 1267 i->n = n + 1; 1268 return true; 1269 } 1270 return false; 1271} 1272 1273/* Loop over all copies. In each iteration, C is set to the next 1274 copy. ITER is an instance of ira_copy_iterator used to iterate 1275 the copies. */ 1276#define FOR_EACH_COPY(C, ITER) \ 1277 for (ira_copy_iter_init (&(ITER)); \ 1278 ira_copy_iter_cond (&(ITER), &(C));) 1279 1280/* The iterator for object conflicts. */ 1281struct ira_object_conflict_iterator { 1282 1283 /* TRUE if the conflicts are represented by vector of allocnos. */ 1284 bool conflict_vec_p; 1285 1286 /* The conflict vector or conflict bit vector. */ 1287 void *vec; 1288 1289 /* The number of the current element in the vector (of type 1290 ira_object_t or IRA_INT_TYPE). */ 1291 unsigned int word_num; 1292 1293 /* The bit vector size. It is defined only if 1294 OBJECT_CONFLICT_VEC_P is FALSE. */ 1295 unsigned int size; 1296 1297 /* The current bit index of bit vector. It is defined only if 1298 OBJECT_CONFLICT_VEC_P is FALSE. */ 1299 unsigned int bit_num; 1300 1301 /* The object id corresponding to the 1st bit of the bit vector. It 1302 is defined only if OBJECT_CONFLICT_VEC_P is FALSE. */ 1303 int base_conflict_id; 1304 1305 /* The word of bit vector currently visited. It is defined only if 1306 OBJECT_CONFLICT_VEC_P is FALSE. */ 1307 unsigned IRA_INT_TYPE word; 1308}; 1309 1310/* Initialize the iterator I with ALLOCNO conflicts. */ 1311static inline void 1312ira_object_conflict_iter_init (ira_object_conflict_iterator *i, 1313 ira_object_t obj) 1314{ 1315 i->conflict_vec_p = OBJECT_CONFLICT_VEC_P (obj); 1316 i->vec = OBJECT_CONFLICT_ARRAY (obj); 1317 i->word_num = 0; 1318 if (i->conflict_vec_p) 1319 i->size = i->bit_num = i->base_conflict_id = i->word = 0; 1320 else 1321 { 1322 if (OBJECT_MIN (obj) > OBJECT_MAX (obj)) 1323 i->size = 0; 1324 else 1325 i->size = ((OBJECT_MAX (obj) - OBJECT_MIN (obj) 1326 + IRA_INT_BITS) 1327 / IRA_INT_BITS) * sizeof (IRA_INT_TYPE); 1328 i->bit_num = 0; 1329 i->base_conflict_id = OBJECT_MIN (obj); 1330 i->word = (i->size == 0 ? 0 : ((IRA_INT_TYPE *) i->vec)[0]); 1331 } 1332} 1333 1334/* Return TRUE if we have more conflicting allocnos to visit, in which 1335 case *A is set to the allocno to be visited. Otherwise, return 1336 FALSE. */ 1337static inline bool 1338ira_object_conflict_iter_cond (ira_object_conflict_iterator *i, 1339 ira_object_t *pobj) 1340{ 1341 ira_object_t obj; 1342 1343 if (i->conflict_vec_p) 1344 { 1345 obj = ((ira_object_t *) i->vec)[i->word_num++]; 1346 if (obj == NULL) 1347 return false; 1348 } 1349 else 1350 { 1351 unsigned IRA_INT_TYPE word = i->word; 1352 unsigned int bit_num = i->bit_num; 1353 1354 /* Skip words that are zeros. */ 1355 for (; word == 0; word = ((IRA_INT_TYPE *) i->vec)[i->word_num]) 1356 { 1357 i->word_num++; 1358 1359 /* If we have reached the end, break. */ 1360 if (i->word_num * sizeof (IRA_INT_TYPE) >= i->size) 1361 return false; 1362 1363 bit_num = i->word_num * IRA_INT_BITS; 1364 } 1365 1366 /* Skip bits that are zero. */ 1367 for (; (word & 1) == 0; word >>= 1) 1368 bit_num++; 1369 1370 obj = ira_object_id_map[bit_num + i->base_conflict_id]; 1371 i->bit_num = bit_num + 1; 1372 i->word = word >> 1; 1373 } 1374 1375 *pobj = obj; 1376 return true; 1377} 1378 1379/* Loop over all objects conflicting with OBJ. In each iteration, 1380 CONF is set to the next conflicting object. ITER is an instance 1381 of ira_object_conflict_iterator used to iterate the conflicts. */ 1382#define FOR_EACH_OBJECT_CONFLICT(OBJ, CONF, ITER) \ 1383 for (ira_object_conflict_iter_init (&(ITER), (OBJ)); \ 1384 ira_object_conflict_iter_cond (&(ITER), &(CONF));) 1385 1386 1387 1388/* The function returns TRUE if at least one hard register from ones 1389 starting with HARD_REGNO and containing value of MODE are in set 1390 HARD_REGSET. */ 1391static inline bool 1392ira_hard_reg_set_intersection_p (int hard_regno, machine_mode mode, 1393 HARD_REG_SET hard_regset) 1394{ 1395 int i; 1396 1397 gcc_assert (hard_regno >= 0); 1398 for (i = hard_regno_nregs[hard_regno][mode] - 1; i >= 0; i--) 1399 if (TEST_HARD_REG_BIT (hard_regset, hard_regno + i)) 1400 return true; 1401 return false; 1402} 1403 1404/* Return number of hard registers in hard register SET. */ 1405static inline int 1406hard_reg_set_size (HARD_REG_SET set) 1407{ 1408 int i, size; 1409 1410 for (size = i = 0; i < FIRST_PSEUDO_REGISTER; i++) 1411 if (TEST_HARD_REG_BIT (set, i)) 1412 size++; 1413 return size; 1414} 1415 1416/* The function returns TRUE if hard registers starting with 1417 HARD_REGNO and containing value of MODE are fully in set 1418 HARD_REGSET. */ 1419static inline bool 1420ira_hard_reg_in_set_p (int hard_regno, machine_mode mode, 1421 HARD_REG_SET hard_regset) 1422{ 1423 int i; 1424 1425 ira_assert (hard_regno >= 0); 1426 for (i = hard_regno_nregs[hard_regno][mode] - 1; i >= 0; i--) 1427 if (!TEST_HARD_REG_BIT (hard_regset, hard_regno + i)) 1428 return false; 1429 return true; 1430} 1431 1432 1433 1434/* To save memory we use a lazy approach for allocation and 1435 initialization of the cost vectors. We do this only when it is 1436 really necessary. */ 1437 1438/* Allocate cost vector *VEC for hard registers of ACLASS and 1439 initialize the elements by VAL if it is necessary */ 1440static inline void 1441ira_allocate_and_set_costs (int **vec, reg_class_t aclass, int val) 1442{ 1443 int i, *reg_costs; 1444 int len; 1445 1446 if (*vec != NULL) 1447 return; 1448 *vec = reg_costs = ira_allocate_cost_vector (aclass); 1449 len = ira_class_hard_regs_num[(int) aclass]; 1450 for (i = 0; i < len; i++) 1451 reg_costs[i] = val; 1452} 1453 1454/* Allocate cost vector *VEC for hard registers of ACLASS and copy 1455 values of vector SRC into the vector if it is necessary */ 1456static inline void 1457ira_allocate_and_copy_costs (int **vec, enum reg_class aclass, int *src) 1458{ 1459 int len; 1460 1461 if (*vec != NULL || src == NULL) 1462 return; 1463 *vec = ira_allocate_cost_vector (aclass); 1464 len = ira_class_hard_regs_num[aclass]; 1465 memcpy (*vec, src, sizeof (int) * len); 1466} 1467 1468/* Allocate cost vector *VEC for hard registers of ACLASS and add 1469 values of vector SRC into the vector if it is necessary */ 1470static inline void 1471ira_allocate_and_accumulate_costs (int **vec, enum reg_class aclass, int *src) 1472{ 1473 int i, len; 1474 1475 if (src == NULL) 1476 return; 1477 len = ira_class_hard_regs_num[aclass]; 1478 if (*vec == NULL) 1479 { 1480 *vec = ira_allocate_cost_vector (aclass); 1481 memset (*vec, 0, sizeof (int) * len); 1482 } 1483 for (i = 0; i < len; i++) 1484 (*vec)[i] += src[i]; 1485} 1486 1487/* Allocate cost vector *VEC for hard registers of ACLASS and copy 1488 values of vector SRC into the vector or initialize it by VAL (if 1489 SRC is null). */ 1490static inline void 1491ira_allocate_and_set_or_copy_costs (int **vec, enum reg_class aclass, 1492 int val, int *src) 1493{ 1494 int i, *reg_costs; 1495 int len; 1496 1497 if (*vec != NULL) 1498 return; 1499 *vec = reg_costs = ira_allocate_cost_vector (aclass); 1500 len = ira_class_hard_regs_num[aclass]; 1501 if (src != NULL) 1502 memcpy (reg_costs, src, sizeof (int) * len); 1503 else 1504 { 1505 for (i = 0; i < len; i++) 1506 reg_costs[i] = val; 1507 } 1508} 1509 1510extern rtx ira_create_new_reg (rtx); 1511extern int first_moveable_pseudo, last_moveable_pseudo; 1512 1513#endif /* GCC_IRA_INT_H */ 1514