1/* Subroutines for insn-output.c for Renesas H8/300. 2 Copyright (C) 1992-2015 Free Software Foundation, Inc. 3 Contributed by Steve Chamberlain (sac@cygnus.com), 4 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com). 5 6This file is part of GCC. 7 8GCC is free software; you can redistribute it and/or modify 9it under the terms of the GNU General Public License as published by 10the Free Software Foundation; either version 3, or (at your option) 11any later version. 12 13GCC is distributed in the hope that it will be useful, 14but WITHOUT ANY WARRANTY; without even the implied warranty of 15MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16GNU General Public License for more details. 17 18You should have received a copy of the GNU General Public License 19along with GCC; see the file COPYING3. If not see 20<http://www.gnu.org/licenses/>. */ 21 22#include "config.h" 23#include "system.h" 24#include "coretypes.h" 25#include "tm.h" 26#include "rtl.h" 27#include "hash-set.h" 28#include "machmode.h" 29#include "vec.h" 30#include "double-int.h" 31#include "input.h" 32#include "alias.h" 33#include "symtab.h" 34#include "wide-int.h" 35#include "inchash.h" 36#include "tree.h" 37#include "stor-layout.h" 38#include "varasm.h" 39#include "calls.h" 40#include "stringpool.h" 41#include "regs.h" 42#include "hard-reg-set.h" 43#include "insn-config.h" 44#include "conditions.h" 45#include "output.h" 46#include "insn-attr.h" 47#include "flags.h" 48#include "recog.h" 49#include "hashtab.h" 50#include "function.h" 51#include "statistics.h" 52#include "real.h" 53#include "fixed-value.h" 54#include "expmed.h" 55#include "dojump.h" 56#include "explow.h" 57#include "emit-rtl.h" 58#include "stmt.h" 59#include "expr.h" 60#include "insn-codes.h" 61#include "optabs.h" 62#include "diagnostic-core.h" 63#include "c-family/c-pragma.h" /* ??? */ 64#include "tm_p.h" 65#include "tm-constrs.h" 66#include "ggc.h" 67#include "target.h" 68#include "target-def.h" 69#include "dominance.h" 70#include "cfg.h" 71#include "cfgrtl.h" 72#include "cfganal.h" 73#include "lcm.h" 74#include "cfgbuild.h" 75#include "cfgcleanup.h" 76#include "predict.h" 77#include "basic-block.h" 78#include "df.h" 79#include "builtins.h" 80 81/* Classifies a h8300_src_operand or h8300_dst_operand. 82 83 H8OP_IMMEDIATE 84 A constant operand of some sort. 85 86 H8OP_REGISTER 87 An ordinary register. 88 89 H8OP_MEM_ABSOLUTE 90 A memory reference with a constant address. 91 92 H8OP_MEM_BASE 93 A memory reference with a register as its address. 94 95 H8OP_MEM_COMPLEX 96 Some other kind of memory reference. */ 97enum h8300_operand_class 98{ 99 H8OP_IMMEDIATE, 100 H8OP_REGISTER, 101 H8OP_MEM_ABSOLUTE, 102 H8OP_MEM_BASE, 103 H8OP_MEM_COMPLEX, 104 NUM_H8OPS 105}; 106 107/* For a general two-operand instruction, element [X][Y] gives 108 the length of the opcode fields when the first operand has class 109 (X + 1) and the second has class Y. */ 110typedef unsigned char h8300_length_table[NUM_H8OPS - 1][NUM_H8OPS]; 111 112/* Forward declarations. */ 113static const char *byte_reg (rtx, int); 114static int h8300_interrupt_function_p (tree); 115static int h8300_saveall_function_p (tree); 116static int h8300_monitor_function_p (tree); 117static int h8300_os_task_function_p (tree); 118static void h8300_emit_stack_adjustment (int, HOST_WIDE_INT, bool); 119static HOST_WIDE_INT round_frame_size (HOST_WIDE_INT); 120static unsigned int compute_saved_regs (void); 121static const char *cond_string (enum rtx_code); 122static unsigned int h8300_asm_insn_count (const char *); 123static tree h8300_handle_fndecl_attribute (tree *, tree, tree, int, bool *); 124static tree h8300_handle_eightbit_data_attribute (tree *, tree, tree, int, bool *); 125static tree h8300_handle_tiny_data_attribute (tree *, tree, tree, int, bool *); 126static void h8300_print_operand_address (FILE *, rtx); 127static void h8300_print_operand (FILE *, rtx, int); 128static bool h8300_print_operand_punct_valid_p (unsigned char code); 129#ifndef OBJECT_FORMAT_ELF 130static void h8300_asm_named_section (const char *, unsigned int, tree); 131#endif 132static int h8300_register_move_cost (machine_mode, reg_class_t, reg_class_t); 133static int h8300_and_costs (rtx); 134static int h8300_shift_costs (rtx); 135static void h8300_push_pop (int, int, bool, bool); 136static int h8300_stack_offset_p (rtx, int); 137static int h8300_ldm_stm_regno (rtx, int, int, int); 138static void h8300_reorg (void); 139static unsigned int h8300_constant_length (rtx); 140static unsigned int h8300_displacement_length (rtx, int); 141static unsigned int h8300_classify_operand (rtx, int, enum h8300_operand_class *); 142static unsigned int h8300_length_from_table (rtx, rtx, const h8300_length_table *); 143static unsigned int h8300_unary_length (rtx); 144static unsigned int h8300_short_immediate_length (rtx); 145static unsigned int h8300_bitfield_length (rtx, rtx); 146static unsigned int h8300_binary_length (rtx_insn *, const h8300_length_table *); 147static bool h8300_short_move_mem_p (rtx, enum rtx_code); 148static unsigned int h8300_move_length (rtx *, const h8300_length_table *); 149static bool h8300_hard_regno_scratch_ok (unsigned int); 150static rtx h8300_get_index (rtx, machine_mode mode, int *); 151 152/* CPU_TYPE, says what cpu we're compiling for. */ 153int cpu_type; 154 155/* True if a #pragma interrupt has been seen for the current function. */ 156static int pragma_interrupt; 157 158/* True if a #pragma saveall has been seen for the current function. */ 159static int pragma_saveall; 160 161static const char *const names_big[] = 162{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" }; 163 164static const char *const names_extended[] = 165{ "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" }; 166 167static const char *const names_upper_extended[] = 168{ "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" }; 169 170/* Points to one of the above. */ 171/* ??? The above could be put in an array indexed by CPU_TYPE. */ 172const char * const *h8_reg_names; 173 174/* Various operations needed by the following, indexed by CPU_TYPE. */ 175 176const char *h8_push_op, *h8_pop_op, *h8_mov_op; 177 178/* Value of MOVE_RATIO. */ 179int h8300_move_ratio; 180 181/* See below where shifts are handled for explanation of this enum. */ 182 183enum shift_alg 184{ 185 SHIFT_INLINE, 186 SHIFT_ROT_AND, 187 SHIFT_SPECIAL, 188 SHIFT_LOOP 189}; 190 191/* Symbols of the various shifts which can be used as indices. */ 192 193enum shift_type 194{ 195 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT 196}; 197 198/* Macros to keep the shift algorithm tables small. */ 199#define INL SHIFT_INLINE 200#define ROT SHIFT_ROT_AND 201#define LOP SHIFT_LOOP 202#define SPC SHIFT_SPECIAL 203 204/* The shift algorithms for each machine, mode, shift type, and shift 205 count are defined below. The three tables below correspond to 206 QImode, HImode, and SImode, respectively. Each table is organized 207 by, in the order of indices, machine, shift type, and shift count. */ 208 209static enum shift_alg shift_alg_qi[3][3][8] = { 210 { 211 /* TARGET_H8300 */ 212 /* 0 1 2 3 4 5 6 7 */ 213 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */ 214 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */ 215 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */ 216 }, 217 { 218 /* TARGET_H8300H */ 219 /* 0 1 2 3 4 5 6 7 */ 220 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */ 221 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */ 222 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */ 223 }, 224 { 225 /* TARGET_H8300S */ 226 /* 0 1 2 3 4 5 6 7 */ 227 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */ 228 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */ 229 { INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */ 230 } 231}; 232 233static enum shift_alg shift_alg_hi[3][3][16] = { 234 { 235 /* TARGET_H8300 */ 236 /* 0 1 2 3 4 5 6 7 */ 237 /* 8 9 10 11 12 13 14 15 */ 238 { INL, INL, INL, INL, INL, INL, INL, SPC, 239 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */ 240 { INL, INL, INL, INL, INL, LOP, LOP, SPC, 241 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */ 242 { INL, INL, INL, INL, INL, LOP, LOP, SPC, 243 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */ 244 }, 245 { 246 /* TARGET_H8300H */ 247 /* 0 1 2 3 4 5 6 7 */ 248 /* 8 9 10 11 12 13 14 15 */ 249 { INL, INL, INL, INL, INL, INL, INL, SPC, 250 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */ 251 { INL, INL, INL, INL, INL, INL, INL, SPC, 252 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */ 253 { INL, INL, INL, INL, INL, INL, INL, SPC, 254 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */ 255 }, 256 { 257 /* TARGET_H8300S */ 258 /* 0 1 2 3 4 5 6 7 */ 259 /* 8 9 10 11 12 13 14 15 */ 260 { INL, INL, INL, INL, INL, INL, INL, INL, 261 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */ 262 { INL, INL, INL, INL, INL, INL, INL, INL, 263 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */ 264 { INL, INL, INL, INL, INL, INL, INL, INL, 265 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */ 266 } 267}; 268 269static enum shift_alg shift_alg_si[3][3][32] = { 270 { 271 /* TARGET_H8300 */ 272 /* 0 1 2 3 4 5 6 7 */ 273 /* 8 9 10 11 12 13 14 15 */ 274 /* 16 17 18 19 20 21 22 23 */ 275 /* 24 25 26 27 28 29 30 31 */ 276 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP, 277 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP, 278 SPC, SPC, SPC, SPC, SPC, LOP, LOP, LOP, 279 SPC, SPC, SPC, SPC, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFT */ 280 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP, 281 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC, 282 SPC, SPC, SPC, LOP, LOP, LOP, LOP, LOP, 283 SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_LSHIFTRT */ 284 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP, 285 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC, 286 SPC, SPC, LOP, LOP, LOP, LOP, LOP, LOP, 287 SPC, SPC, SPC, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */ 288 }, 289 { 290 /* TARGET_H8300H */ 291 /* 0 1 2 3 4 5 6 7 */ 292 /* 8 9 10 11 12 13 14 15 */ 293 /* 16 17 18 19 20 21 22 23 */ 294 /* 24 25 26 27 28 29 30 31 */ 295 { INL, INL, INL, INL, INL, LOP, LOP, LOP, 296 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC, 297 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP, 298 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */ 299 { INL, INL, INL, INL, INL, LOP, LOP, LOP, 300 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC, 301 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP, 302 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */ 303 { INL, INL, INL, INL, INL, LOP, LOP, LOP, 304 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP, 305 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP, 306 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */ 307 }, 308 { 309 /* TARGET_H8300S */ 310 /* 0 1 2 3 4 5 6 7 */ 311 /* 8 9 10 11 12 13 14 15 */ 312 /* 16 17 18 19 20 21 22 23 */ 313 /* 24 25 26 27 28 29 30 31 */ 314 { INL, INL, INL, INL, INL, INL, INL, INL, 315 INL, INL, INL, LOP, LOP, LOP, LOP, SPC, 316 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP, 317 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */ 318 { INL, INL, INL, INL, INL, INL, INL, INL, 319 INL, INL, INL, LOP, LOP, LOP, LOP, SPC, 320 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP, 321 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */ 322 { INL, INL, INL, INL, INL, INL, INL, INL, 323 INL, INL, INL, LOP, LOP, LOP, LOP, LOP, 324 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP, 325 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */ 326 } 327}; 328 329#undef INL 330#undef ROT 331#undef LOP 332#undef SPC 333 334enum h8_cpu 335{ 336 H8_300, 337 H8_300H, 338 H8_S 339}; 340 341/* Initialize various cpu specific globals at start up. */ 342 343static void 344h8300_option_override (void) 345{ 346 static const char *const h8_push_ops[2] = { "push" , "push.l" }; 347 static const char *const h8_pop_ops[2] = { "pop" , "pop.l" }; 348 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" }; 349 350#ifndef OBJECT_FORMAT_ELF 351 if (TARGET_H8300SX) 352 { 353 error ("-msx is not supported in coff"); 354 target_flags |= MASK_H8300S; 355 } 356#endif 357 358 if (TARGET_H8300) 359 { 360 cpu_type = (int) CPU_H8300; 361 h8_reg_names = names_big; 362 } 363 else 364 { 365 /* For this we treat the H8/300H and H8S the same. */ 366 cpu_type = (int) CPU_H8300H; 367 h8_reg_names = names_extended; 368 } 369 h8_push_op = h8_push_ops[cpu_type]; 370 h8_pop_op = h8_pop_ops[cpu_type]; 371 h8_mov_op = h8_mov_ops[cpu_type]; 372 373 if (!TARGET_H8300S && TARGET_MAC) 374 { 375 error ("-ms2600 is used without -ms"); 376 target_flags |= MASK_H8300S_1; 377 } 378 379 if (TARGET_H8300 && TARGET_NORMAL_MODE) 380 { 381 error ("-mn is used without -mh or -ms or -msx"); 382 target_flags ^= MASK_NORMAL_MODE; 383 } 384 385 if (! TARGET_H8300S && TARGET_EXR) 386 { 387 error ("-mexr is used without -ms"); 388 target_flags |= MASK_H8300S_1; 389 } 390 391 if (TARGET_H8300 && TARGET_INT32) 392 { 393 error ("-mint32 is not supported for H8300 and H8300L targets"); 394 target_flags ^= MASK_INT32; 395 } 396 397 if ((!TARGET_H8300S && TARGET_EXR) && (!TARGET_H8300SX && TARGET_EXR)) 398 { 399 error ("-mexr is used without -ms or -msx"); 400 target_flags |= MASK_H8300S_1; 401 } 402 403 if ((!TARGET_H8300S && TARGET_NEXR) && (!TARGET_H8300SX && TARGET_NEXR)) 404 { 405 warning (OPT_mno_exr, "-mno-exr valid only with -ms or -msx \ 406 - Option ignored!"); 407 } 408 409 /* Some of the shifts are optimized for speed by default. 410 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html 411 If optimizing for size, change shift_alg for those shift to 412 SHIFT_LOOP. */ 413 if (optimize_size) 414 { 415 /* H8/300 */ 416 shift_alg_hi[H8_300][SHIFT_ASHIFT][5] = SHIFT_LOOP; 417 shift_alg_hi[H8_300][SHIFT_ASHIFT][6] = SHIFT_LOOP; 418 shift_alg_hi[H8_300][SHIFT_ASHIFT][13] = SHIFT_LOOP; 419 shift_alg_hi[H8_300][SHIFT_ASHIFT][14] = SHIFT_LOOP; 420 421 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][13] = SHIFT_LOOP; 422 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][14] = SHIFT_LOOP; 423 424 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][13] = SHIFT_LOOP; 425 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][14] = SHIFT_LOOP; 426 427 /* H8/300H */ 428 shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP; 429 shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP; 430 431 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP; 432 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP; 433 434 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP; 435 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP; 436 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP; 437 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP; 438 439 /* H8S */ 440 shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP; 441 } 442 443 /* Work out a value for MOVE_RATIO. */ 444 if (!TARGET_H8300SX) 445 { 446 /* Memory-memory moves are quite expensive without the 447 h8sx instructions. */ 448 h8300_move_ratio = 3; 449 } 450 else if (flag_omit_frame_pointer) 451 { 452 /* movmd sequences are fairly cheap when er6 isn't fixed. They can 453 sometimes be as short as two individual memory-to-memory moves, 454 but since they use all the call-saved registers, it seems better 455 to allow up to three moves here. */ 456 h8300_move_ratio = 4; 457 } 458 else if (optimize_size) 459 { 460 /* In this case we don't use movmd sequences since they tend 461 to be longer than calls to memcpy(). Memory-to-memory 462 moves are cheaper than for !TARGET_H8300SX, so it makes 463 sense to have a slightly higher threshold. */ 464 h8300_move_ratio = 4; 465 } 466 else 467 { 468 /* We use movmd sequences for some moves since it can be quicker 469 than calling memcpy(). The sequences will need to save and 470 restore er6 though, so bump up the cost. */ 471 h8300_move_ratio = 6; 472 } 473 474 /* This target defaults to strict volatile bitfields. */ 475 if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2)) 476 flag_strict_volatile_bitfields = 1; 477} 478 479/* Return the byte register name for a register rtx X. B should be 0 480 if you want a lower byte register. B should be 1 if you want an 481 upper byte register. */ 482 483static const char * 484byte_reg (rtx x, int b) 485{ 486 static const char *const names_small[] = { 487 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h", 488 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h" 489 }; 490 491 gcc_assert (REG_P (x)); 492 493 return names_small[REGNO (x) * 2 + b]; 494} 495 496/* REGNO must be saved/restored across calls if this macro is true. */ 497 498#define WORD_REG_USED(regno) \ 499 (regno < SP_REG \ 500 /* No need to save registers if this function will not return. */ \ 501 && ! TREE_THIS_VOLATILE (current_function_decl) \ 502 && (h8300_saveall_function_p (current_function_decl) \ 503 /* Save any call saved register that was used. */ \ 504 || (df_regs_ever_live_p (regno) && !call_used_regs[regno]) \ 505 /* Save the frame pointer if it was used. */ \ 506 || (regno == HARD_FRAME_POINTER_REGNUM && df_regs_ever_live_p (regno)) \ 507 /* Save any register used in an interrupt handler. */ \ 508 || (h8300_current_function_interrupt_function_p () \ 509 && df_regs_ever_live_p (regno)) \ 510 /* Save call clobbered registers in non-leaf interrupt \ 511 handlers. */ \ 512 || (h8300_current_function_interrupt_function_p () \ 513 && call_used_regs[regno] \ 514 && !crtl->is_leaf))) 515 516/* We use this to wrap all emitted insns in the prologue. */ 517static rtx_insn * 518F (rtx_insn *x, bool set_it) 519{ 520 if (set_it) 521 RTX_FRAME_RELATED_P (x) = 1; 522 return x; 523} 524 525/* Mark all the subexpressions of the PARALLEL rtx PAR as 526 frame-related. Return PAR. 527 528 dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a 529 PARALLEL rtx other than the first if they do not have the 530 FRAME_RELATED flag set on them. */ 531static rtx 532Fpa (rtx par) 533{ 534 int len = XVECLEN (par, 0); 535 int i; 536 537 for (i = 0; i < len; i++) 538 RTX_FRAME_RELATED_P (XVECEXP (par, 0, i)) = 1; 539 540 return par; 541} 542 543/* Output assembly language to FILE for the operation OP with operand size 544 SIZE to adjust the stack pointer. */ 545 546static void 547h8300_emit_stack_adjustment (int sign, HOST_WIDE_INT size, bool in_prologue) 548{ 549 /* If the frame size is 0, we don't have anything to do. */ 550 if (size == 0) 551 return; 552 553 /* H8/300 cannot add/subtract a large constant with a single 554 instruction. If a temporary register is available, load the 555 constant to it and then do the addition. */ 556 if (TARGET_H8300 557 && size > 4 558 && !h8300_current_function_interrupt_function_p () 559 && !(cfun->static_chain_decl != NULL && sign < 0)) 560 { 561 rtx r3 = gen_rtx_REG (Pmode, 3); 562 F (emit_insn (gen_movhi (r3, GEN_INT (sign * size))), in_prologue); 563 F (emit_insn (gen_addhi3 (stack_pointer_rtx, 564 stack_pointer_rtx, r3)), in_prologue); 565 } 566 else 567 { 568 /* The stack adjustment made here is further optimized by the 569 splitter. In case of H8/300, the splitter always splits the 570 addition emitted here to make the adjustment interrupt-safe. 571 FIXME: We don't always tag those, because we don't know what 572 the splitter will do. */ 573 if (Pmode == HImode) 574 { 575 rtx_insn *x = emit_insn (gen_addhi3 (stack_pointer_rtx, 576 stack_pointer_rtx, 577 GEN_INT (sign * size))); 578 if (size < 4) 579 F (x, in_prologue); 580 } 581 else 582 F (emit_insn (gen_addsi3 (stack_pointer_rtx, 583 stack_pointer_rtx, GEN_INT (sign * size))), in_prologue); 584 } 585} 586 587/* Round up frame size SIZE. */ 588 589static HOST_WIDE_INT 590round_frame_size (HOST_WIDE_INT size) 591{ 592 return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1) 593 & -STACK_BOUNDARY / BITS_PER_UNIT); 594} 595 596/* Compute which registers to push/pop. 597 Return a bit vector of registers. */ 598 599static unsigned int 600compute_saved_regs (void) 601{ 602 unsigned int saved_regs = 0; 603 int regno; 604 605 /* Construct a bit vector of registers to be pushed/popped. */ 606 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++) 607 { 608 if (WORD_REG_USED (regno)) 609 saved_regs |= 1 << regno; 610 } 611 612 /* Don't push/pop the frame pointer as it is treated separately. */ 613 if (frame_pointer_needed) 614 saved_regs &= ~(1 << HARD_FRAME_POINTER_REGNUM); 615 616 return saved_regs; 617} 618 619/* Emit an insn to push register RN. */ 620 621static rtx 622push (int rn, bool in_prologue) 623{ 624 rtx reg = gen_rtx_REG (word_mode, rn); 625 rtx x; 626 627 if (TARGET_H8300) 628 x = gen_push_h8300 (reg); 629 else if (!TARGET_NORMAL_MODE) 630 x = gen_push_h8300hs_advanced (reg); 631 else 632 x = gen_push_h8300hs_normal (reg); 633 x = F (emit_insn (x), in_prologue); 634 add_reg_note (x, REG_INC, stack_pointer_rtx); 635 return x; 636} 637 638/* Emit an insn to pop register RN. */ 639 640static rtx 641pop (int rn) 642{ 643 rtx reg = gen_rtx_REG (word_mode, rn); 644 rtx x; 645 646 if (TARGET_H8300) 647 x = gen_pop_h8300 (reg); 648 else if (!TARGET_NORMAL_MODE) 649 x = gen_pop_h8300hs_advanced (reg); 650 else 651 x = gen_pop_h8300hs_normal (reg); 652 x = emit_insn (x); 653 add_reg_note (x, REG_INC, stack_pointer_rtx); 654 return x; 655} 656 657/* Emit an instruction to push or pop NREGS consecutive registers 658 starting at register REGNO. POP_P selects a pop rather than a 659 push and RETURN_P is true if the instruction should return. 660 661 It must be possible to do the requested operation in a single 662 instruction. If NREGS == 1 && !RETURN_P, use a normal push 663 or pop insn. Otherwise emit a parallel of the form: 664 665 (parallel 666 [(return) ;; if RETURN_P 667 (save or restore REGNO) 668 (save or restore REGNO + 1) 669 ... 670 (save or restore REGNO + NREGS - 1) 671 (set sp (plus sp (const_int adjust)))] */ 672 673static void 674h8300_push_pop (int regno, int nregs, bool pop_p, bool return_p) 675{ 676 int i, j; 677 rtvec vec; 678 rtx sp, offset, x; 679 680 /* See whether we can use a simple push or pop. */ 681 if (!return_p && nregs == 1) 682 { 683 if (pop_p) 684 pop (regno); 685 else 686 push (regno, false); 687 return; 688 } 689 690 /* We need one element for the return insn, if present, one for each 691 register, and one for stack adjustment. */ 692 vec = rtvec_alloc ((return_p ? 1 : 0) + nregs + 1); 693 sp = stack_pointer_rtx; 694 i = 0; 695 696 /* Add the return instruction. */ 697 if (return_p) 698 { 699 RTVEC_ELT (vec, i) = ret_rtx; 700 i++; 701 } 702 703 /* Add the register moves. */ 704 for (j = 0; j < nregs; j++) 705 { 706 rtx lhs, rhs; 707 708 if (pop_p) 709 { 710 /* Register REGNO + NREGS - 1 is popped first. Before the 711 stack adjustment, its slot is at address @sp. */ 712 lhs = gen_rtx_REG (SImode, regno + j); 713 rhs = gen_rtx_MEM (SImode, plus_constant (Pmode, sp, 714 (nregs - j - 1) * 4)); 715 } 716 else 717 { 718 /* Register REGNO is pushed first and will be stored at @(-4,sp). */ 719 lhs = gen_rtx_MEM (SImode, plus_constant (Pmode, sp, (j + 1) * -4)); 720 rhs = gen_rtx_REG (SImode, regno + j); 721 } 722 RTVEC_ELT (vec, i + j) = gen_rtx_SET (VOIDmode, lhs, rhs); 723 } 724 725 /* Add the stack adjustment. */ 726 offset = GEN_INT ((pop_p ? nregs : -nregs) * 4); 727 RTVEC_ELT (vec, i + j) = gen_rtx_SET (VOIDmode, sp, 728 gen_rtx_PLUS (Pmode, sp, offset)); 729 730 x = gen_rtx_PARALLEL (VOIDmode, vec); 731 if (!pop_p) 732 x = Fpa (x); 733 734 if (return_p) 735 emit_jump_insn (x); 736 else 737 emit_insn (x); 738} 739 740/* Return true if X has the value sp + OFFSET. */ 741 742static int 743h8300_stack_offset_p (rtx x, int offset) 744{ 745 if (offset == 0) 746 return x == stack_pointer_rtx; 747 748 return (GET_CODE (x) == PLUS 749 && XEXP (x, 0) == stack_pointer_rtx 750 && GET_CODE (XEXP (x, 1)) == CONST_INT 751 && INTVAL (XEXP (x, 1)) == offset); 752} 753 754/* A subroutine of h8300_ldm_stm_parallel. X is one pattern in 755 something that may be an ldm or stm instruction. If it fits 756 the required template, return the register it loads or stores, 757 otherwise return -1. 758 759 LOAD_P is true if X should be a load, false if it should be a store. 760 NREGS is the number of registers that the whole instruction is expected 761 to load or store. INDEX is the index of the register that X should 762 load or store, relative to the lowest-numbered register. */ 763 764static int 765h8300_ldm_stm_regno (rtx x, int load_p, int index, int nregs) 766{ 767 int regindex, memindex, offset; 768 769 if (load_p) 770 regindex = 0, memindex = 1, offset = (nregs - index - 1) * 4; 771 else 772 memindex = 0, regindex = 1, offset = (index + 1) * -4; 773 774 if (GET_CODE (x) == SET 775 && GET_CODE (XEXP (x, regindex)) == REG 776 && GET_CODE (XEXP (x, memindex)) == MEM 777 && h8300_stack_offset_p (XEXP (XEXP (x, memindex), 0), offset)) 778 return REGNO (XEXP (x, regindex)); 779 780 return -1; 781} 782 783/* Return true if the elements of VEC starting at FIRST describe an 784 ldm or stm instruction (LOAD_P says which). */ 785 786int 787h8300_ldm_stm_parallel (rtvec vec, int load_p, int first) 788{ 789 rtx last; 790 int nregs, i, regno, adjust; 791 792 /* There must be a stack adjustment, a register move, and at least one 793 other operation (a return or another register move). */ 794 if (GET_NUM_ELEM (vec) < 3) 795 return false; 796 797 /* Get the range of registers to be pushed or popped. */ 798 nregs = GET_NUM_ELEM (vec) - first - 1; 799 regno = h8300_ldm_stm_regno (RTVEC_ELT (vec, first), load_p, 0, nregs); 800 801 /* Check that the call to h8300_ldm_stm_regno succeeded and 802 that we're only dealing with GPRs. */ 803 if (regno < 0 || regno + nregs > 8) 804 return false; 805 806 /* 2-register h8s instructions must start with an even-numbered register. 807 3- and 4-register instructions must start with er0 or er4. */ 808 if (!TARGET_H8300SX) 809 { 810 if ((regno & 1) != 0) 811 return false; 812 if (nregs > 2 && (regno & 3) != 0) 813 return false; 814 } 815 816 /* Check the other loads or stores. */ 817 for (i = 1; i < nregs; i++) 818 if (h8300_ldm_stm_regno (RTVEC_ELT (vec, first + i), load_p, i, nregs) 819 != regno + i) 820 return false; 821 822 /* Check the stack adjustment. */ 823 last = RTVEC_ELT (vec, first + nregs); 824 adjust = (load_p ? nregs : -nregs) * 4; 825 return (GET_CODE (last) == SET 826 && SET_DEST (last) == stack_pointer_rtx 827 && h8300_stack_offset_p (SET_SRC (last), adjust)); 828} 829 830/* This is what the stack looks like after the prolog of 831 a function with a frame has been set up: 832 833 <args> 834 PC 835 FP <- fp 836 <locals> 837 <saved registers> <- sp 838 839 This is what the stack looks like after the prolog of 840 a function which doesn't have a frame: 841 842 <args> 843 PC 844 <locals> 845 <saved registers> <- sp 846*/ 847 848/* Generate RTL code for the function prologue. */ 849 850void 851h8300_expand_prologue (void) 852{ 853 int regno; 854 int saved_regs; 855 int n_regs; 856 857 /* If the current function has the OS_Task attribute set, then 858 we have a naked prologue. */ 859 if (h8300_os_task_function_p (current_function_decl)) 860 return; 861 862 if (h8300_monitor_function_p (current_function_decl)) 863 /* The monitor function act as normal functions, which means it 864 can accept parameters and return values. In addition to this, 865 interrupts are masked in prologue and return with "rte" in epilogue. */ 866 emit_insn (gen_monitor_prologue ()); 867 868 if (frame_pointer_needed) 869 { 870 /* Push fp. */ 871 push (HARD_FRAME_POINTER_REGNUM, true); 872 F (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx), true); 873 } 874 875 /* Push the rest of the registers in ascending order. */ 876 saved_regs = compute_saved_regs (); 877 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs) 878 { 879 n_regs = 1; 880 if (saved_regs & (1 << regno)) 881 { 882 if (TARGET_H8300S) 883 { 884 /* See how many registers we can push at the same time. */ 885 if ((!TARGET_H8300SX || (regno & 3) == 0) 886 && ((saved_regs >> regno) & 0x0f) == 0x0f) 887 n_regs = 4; 888 889 else if ((!TARGET_H8300SX || (regno & 3) == 0) 890 && ((saved_regs >> regno) & 0x07) == 0x07) 891 n_regs = 3; 892 893 else if ((!TARGET_H8300SX || (regno & 1) == 0) 894 && ((saved_regs >> regno) & 0x03) == 0x03) 895 n_regs = 2; 896 } 897 898 h8300_push_pop (regno, n_regs, false, false); 899 } 900 } 901 902 /* Leave room for locals. */ 903 h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()), true); 904} 905 906/* Return nonzero if we can use "rts" for the function currently being 907 compiled. */ 908 909int 910h8300_can_use_return_insn_p (void) 911{ 912 return (reload_completed 913 && !frame_pointer_needed 914 && get_frame_size () == 0 915 && compute_saved_regs () == 0); 916} 917 918/* Generate RTL code for the function epilogue. */ 919 920void 921h8300_expand_epilogue (void) 922{ 923 int regno; 924 int saved_regs; 925 int n_regs; 926 HOST_WIDE_INT frame_size; 927 bool returned_p; 928 929 if (h8300_os_task_function_p (current_function_decl)) 930 /* OS_Task epilogues are nearly naked -- they just have an 931 rts instruction. */ 932 return; 933 934 frame_size = round_frame_size (get_frame_size ()); 935 returned_p = false; 936 937 /* Deallocate locals. */ 938 h8300_emit_stack_adjustment (1, frame_size, false); 939 940 /* Pop the saved registers in descending order. */ 941 saved_regs = compute_saved_regs (); 942 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs) 943 { 944 n_regs = 1; 945 if (saved_regs & (1 << regno)) 946 { 947 if (TARGET_H8300S) 948 { 949 /* See how many registers we can pop at the same time. */ 950 if ((TARGET_H8300SX || (regno & 3) == 3) 951 && ((saved_regs << 3 >> regno) & 0x0f) == 0x0f) 952 n_regs = 4; 953 954 else if ((TARGET_H8300SX || (regno & 3) == 2) 955 && ((saved_regs << 2 >> regno) & 0x07) == 0x07) 956 n_regs = 3; 957 958 else if ((TARGET_H8300SX || (regno & 1) == 1) 959 && ((saved_regs << 1 >> regno) & 0x03) == 0x03) 960 n_regs = 2; 961 } 962 963 /* See if this pop would be the last insn before the return. 964 If so, use rte/l or rts/l instead of pop or ldm.l. */ 965 if (TARGET_H8300SX 966 && !frame_pointer_needed 967 && frame_size == 0 968 && (saved_regs & ((1 << (regno - n_regs + 1)) - 1)) == 0) 969 returned_p = true; 970 971 h8300_push_pop (regno - n_regs + 1, n_regs, true, returned_p); 972 } 973 } 974 975 /* Pop frame pointer if we had one. */ 976 if (frame_pointer_needed) 977 { 978 if (TARGET_H8300SX) 979 returned_p = true; 980 h8300_push_pop (HARD_FRAME_POINTER_REGNUM, 1, true, returned_p); 981 } 982 983 if (!returned_p) 984 emit_jump_insn (ret_rtx); 985} 986 987/* Return nonzero if the current function is an interrupt 988 function. */ 989 990int 991h8300_current_function_interrupt_function_p (void) 992{ 993 return (h8300_interrupt_function_p (current_function_decl)); 994} 995 996int 997h8300_current_function_monitor_function_p () 998{ 999 return (h8300_monitor_function_p (current_function_decl)); 1000} 1001 1002/* Output assembly code for the start of the file. */ 1003 1004static void 1005h8300_file_start (void) 1006{ 1007 default_file_start (); 1008 1009 if (TARGET_H8300H) 1010 fputs (TARGET_NORMAL_MODE ? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file); 1011 else if (TARGET_H8300SX) 1012 fputs (TARGET_NORMAL_MODE ? "\t.h8300sxn\n" : "\t.h8300sx\n", asm_out_file); 1013 else if (TARGET_H8300S) 1014 fputs (TARGET_NORMAL_MODE ? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file); 1015} 1016 1017/* Output assembly language code for the end of file. */ 1018 1019static void 1020h8300_file_end (void) 1021{ 1022 fputs ("\t.end\n", asm_out_file); 1023} 1024 1025/* Split an add of a small constant into two adds/subs insns. 1026 1027 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec 1028 instead of adds/subs. */ 1029 1030void 1031split_adds_subs (machine_mode mode, rtx *operands) 1032{ 1033 HOST_WIDE_INT val = INTVAL (operands[1]); 1034 rtx reg = operands[0]; 1035 HOST_WIDE_INT sign = 1; 1036 HOST_WIDE_INT amount; 1037 rtx (*gen_add) (rtx, rtx, rtx); 1038 1039 /* Force VAL to be positive so that we do not have to consider the 1040 sign. */ 1041 if (val < 0) 1042 { 1043 val = -val; 1044 sign = -1; 1045 } 1046 1047 switch (mode) 1048 { 1049 case HImode: 1050 gen_add = gen_addhi3; 1051 break; 1052 1053 case SImode: 1054 gen_add = gen_addsi3; 1055 break; 1056 1057 default: 1058 gcc_unreachable (); 1059 } 1060 1061 /* Try different amounts in descending order. */ 1062 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2; 1063 amount > 0; 1064 amount /= 2) 1065 { 1066 for (; val >= amount; val -= amount) 1067 emit_insn (gen_add (reg, reg, GEN_INT (sign * amount))); 1068 } 1069 1070 return; 1071} 1072 1073/* Handle machine specific pragmas for compatibility with existing 1074 compilers for the H8/300. 1075 1076 pragma saveall generates prologue/epilogue code which saves and 1077 restores all the registers on function entry. 1078 1079 pragma interrupt saves and restores all registers, and exits with 1080 an rte instruction rather than an rts. A pointer to a function 1081 with this attribute may be safely used in an interrupt vector. */ 1082 1083void 1084h8300_pr_interrupt (struct cpp_reader *pfile ATTRIBUTE_UNUSED) 1085{ 1086 pragma_interrupt = 1; 1087} 1088 1089void 1090h8300_pr_saveall (struct cpp_reader *pfile ATTRIBUTE_UNUSED) 1091{ 1092 pragma_saveall = 1; 1093} 1094 1095/* If the next function argument with MODE and TYPE is to be passed in 1096 a register, return a reg RTX for the hard register in which to pass 1097 the argument. CUM represents the state after the last argument. 1098 If the argument is to be pushed, NULL_RTX is returned. 1099 1100 On the H8/300 all normal args are pushed, unless -mquickcall in which 1101 case the first 3 arguments are passed in registers. */ 1102 1103static rtx 1104h8300_function_arg (cumulative_args_t cum_v, machine_mode mode, 1105 const_tree type, bool named) 1106{ 1107 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); 1108 1109 static const char *const hand_list[] = { 1110 "__main", 1111 "__cmpsi2", 1112 "__divhi3", 1113 "__modhi3", 1114 "__udivhi3", 1115 "__umodhi3", 1116 "__divsi3", 1117 "__modsi3", 1118 "__udivsi3", 1119 "__umodsi3", 1120 "__mulhi3", 1121 "__mulsi3", 1122 "__reg_memcpy", 1123 "__reg_memset", 1124 "__ucmpsi2", 1125 0, 1126 }; 1127 1128 rtx result = NULL_RTX; 1129 const char *fname; 1130 int regpass = 0; 1131 1132 /* Never pass unnamed arguments in registers. */ 1133 if (!named) 1134 return NULL_RTX; 1135 1136 /* Pass 3 regs worth of data in regs when user asked on the command line. */ 1137 if (TARGET_QUICKCALL) 1138 regpass = 3; 1139 1140 /* If calling hand written assembler, use 4 regs of args. */ 1141 if (cum->libcall) 1142 { 1143 const char * const *p; 1144 1145 fname = XSTR (cum->libcall, 0); 1146 1147 /* See if this libcall is one of the hand coded ones. */ 1148 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++) 1149 ; 1150 1151 if (*p) 1152 regpass = 4; 1153 } 1154 1155 if (regpass) 1156 { 1157 int size; 1158 1159 if (mode == BLKmode) 1160 size = int_size_in_bytes (type); 1161 else 1162 size = GET_MODE_SIZE (mode); 1163 1164 if (size + cum->nbytes <= regpass * UNITS_PER_WORD 1165 && cum->nbytes / UNITS_PER_WORD <= 3) 1166 result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD); 1167 } 1168 1169 return result; 1170} 1171 1172/* Update the data in CUM to advance over an argument 1173 of mode MODE and data type TYPE. 1174 (TYPE is null for libcalls where that information may not be available.) */ 1175 1176static void 1177h8300_function_arg_advance (cumulative_args_t cum_v, machine_mode mode, 1178 const_tree type, bool named ATTRIBUTE_UNUSED) 1179{ 1180 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); 1181 1182 cum->nbytes += (mode != BLKmode 1183 ? (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD 1184 : (int_size_in_bytes (type) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD); 1185} 1186 1187 1188/* Implements TARGET_REGISTER_MOVE_COST. 1189 1190 Any SI register-to-register move may need to be reloaded, 1191 so inmplement h8300_register_move_cost to return > 2 so that reload never 1192 shortcuts. */ 1193 1194static int 1195h8300_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED, 1196 reg_class_t from, reg_class_t to) 1197{ 1198 if (from == MAC_REGS || to == MAC_REG) 1199 return 6; 1200 else 1201 return 3; 1202} 1203 1204/* Compute the cost of an and insn. */ 1205 1206static int 1207h8300_and_costs (rtx x) 1208{ 1209 rtx operands[4]; 1210 1211 if (GET_MODE (x) == QImode) 1212 return 1; 1213 1214 if (GET_MODE (x) != HImode 1215 && GET_MODE (x) != SImode) 1216 return 100; 1217 1218 operands[0] = NULL; 1219 operands[1] = XEXP (x, 0); 1220 operands[2] = XEXP (x, 1); 1221 operands[3] = x; 1222 return compute_logical_op_length (GET_MODE (x), operands) / 2; 1223} 1224 1225/* Compute the cost of a shift insn. */ 1226 1227static int 1228h8300_shift_costs (rtx x) 1229{ 1230 rtx operands[4]; 1231 1232 if (GET_MODE (x) != QImode 1233 && GET_MODE (x) != HImode 1234 && GET_MODE (x) != SImode) 1235 return 100; 1236 1237 operands[0] = NULL; 1238 operands[1] = NULL; 1239 operands[2] = XEXP (x, 1); 1240 operands[3] = x; 1241 return compute_a_shift_length (NULL, operands) / 2; 1242} 1243 1244/* Worker function for TARGET_RTX_COSTS. */ 1245 1246static bool 1247h8300_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED, 1248 int *total, bool speed) 1249{ 1250 if (TARGET_H8300SX && outer_code == MEM) 1251 { 1252 /* Estimate the number of execution states needed to calculate 1253 the address. */ 1254 if (register_operand (x, VOIDmode) 1255 || GET_CODE (x) == POST_INC 1256 || GET_CODE (x) == POST_DEC 1257 || CONSTANT_P (x)) 1258 *total = 0; 1259 else 1260 *total = COSTS_N_INSNS (1); 1261 return true; 1262 } 1263 1264 switch (code) 1265 { 1266 case CONST_INT: 1267 { 1268 HOST_WIDE_INT n = INTVAL (x); 1269 1270 if (TARGET_H8300SX) 1271 { 1272 /* Constant operands need the same number of processor 1273 states as register operands. Although we could try to 1274 use a size-based cost for !speed, the lack of 1275 of a mode makes the results very unpredictable. */ 1276 *total = 0; 1277 return true; 1278 } 1279 if (-4 <= n && n <= 4) 1280 { 1281 switch ((int) n) 1282 { 1283 case 0: 1284 *total = 0; 1285 return true; 1286 case 1: 1287 case 2: 1288 case -1: 1289 case -2: 1290 *total = 0 + (outer_code == SET); 1291 return true; 1292 case 4: 1293 case -4: 1294 if (TARGET_H8300H || TARGET_H8300S) 1295 *total = 0 + (outer_code == SET); 1296 else 1297 *total = 1; 1298 return true; 1299 } 1300 } 1301 *total = 1; 1302 return true; 1303 } 1304 1305 case CONST: 1306 case LABEL_REF: 1307 case SYMBOL_REF: 1308 if (TARGET_H8300SX) 1309 { 1310 /* See comment for CONST_INT. */ 1311 *total = 0; 1312 return true; 1313 } 1314 *total = 3; 1315 return true; 1316 1317 case CONST_DOUBLE: 1318 *total = 20; 1319 return true; 1320 1321 case COMPARE: 1322 if (XEXP (x, 1) == const0_rtx) 1323 *total = 0; 1324 return false; 1325 1326 case AND: 1327 if (!h8300_dst_operand (XEXP (x, 0), VOIDmode) 1328 || !h8300_src_operand (XEXP (x, 1), VOIDmode)) 1329 return false; 1330 *total = COSTS_N_INSNS (h8300_and_costs (x)); 1331 return true; 1332 1333 /* We say that MOD and DIV are so expensive because otherwise we'll 1334 generate some really horrible code for division of a power of two. */ 1335 case MOD: 1336 case DIV: 1337 case UMOD: 1338 case UDIV: 1339 if (TARGET_H8300SX) 1340 switch (GET_MODE (x)) 1341 { 1342 case QImode: 1343 case HImode: 1344 *total = COSTS_N_INSNS (!speed ? 4 : 10); 1345 return false; 1346 1347 case SImode: 1348 *total = COSTS_N_INSNS (!speed ? 4 : 18); 1349 return false; 1350 1351 default: 1352 break; 1353 } 1354 *total = COSTS_N_INSNS (12); 1355 return true; 1356 1357 case MULT: 1358 if (TARGET_H8300SX) 1359 switch (GET_MODE (x)) 1360 { 1361 case QImode: 1362 case HImode: 1363 *total = COSTS_N_INSNS (2); 1364 return false; 1365 1366 case SImode: 1367 *total = COSTS_N_INSNS (5); 1368 return false; 1369 1370 default: 1371 break; 1372 } 1373 *total = COSTS_N_INSNS (4); 1374 return true; 1375 1376 case ASHIFT: 1377 case ASHIFTRT: 1378 case LSHIFTRT: 1379 if (h8sx_binary_shift_operator (x, VOIDmode)) 1380 { 1381 *total = COSTS_N_INSNS (2); 1382 return false; 1383 } 1384 else if (h8sx_unary_shift_operator (x, VOIDmode)) 1385 { 1386 *total = COSTS_N_INSNS (1); 1387 return false; 1388 } 1389 *total = COSTS_N_INSNS (h8300_shift_costs (x)); 1390 return true; 1391 1392 case ROTATE: 1393 case ROTATERT: 1394 if (GET_MODE (x) == HImode) 1395 *total = 2; 1396 else 1397 *total = 8; 1398 return true; 1399 1400 default: 1401 *total = COSTS_N_INSNS (1); 1402 return false; 1403 } 1404} 1405 1406/* Documentation for the machine specific operand escapes: 1407 1408 'E' like s but negative. 1409 'F' like t but negative. 1410 'G' constant just the negative 1411 'R' print operand as a byte:8 address if appropriate, else fall back to 1412 'X' handling. 1413 'S' print operand as a long word 1414 'T' print operand as a word 1415 'V' find the set bit, and print its number. 1416 'W' find the clear bit, and print its number. 1417 'X' print operand as a byte 1418 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8. 1419 If this operand isn't a register, fall back to 'R' handling. 1420 'Z' print int & 7. 1421 'c' print the opcode corresponding to rtl 1422 'e' first word of 32-bit value - if reg, then least reg. if mem 1423 then least. if const then most sig word 1424 'f' second word of 32-bit value - if reg, then biggest reg. if mem 1425 then +2. if const then least sig word 1426 'j' print operand as condition code. 1427 'k' print operand as reverse condition code. 1428 'm' convert an integer operand to a size suffix (.b, .w or .l) 1429 'o' print an integer without a leading '#' 1430 's' print as low byte of 16-bit value 1431 't' print as high byte of 16-bit value 1432 'w' print as low byte of 32-bit value 1433 'x' print as 2nd byte of 32-bit value 1434 'y' print as 3rd byte of 32-bit value 1435 'z' print as msb of 32-bit value 1436*/ 1437 1438/* Return assembly language string which identifies a comparison type. */ 1439 1440static const char * 1441cond_string (enum rtx_code code) 1442{ 1443 switch (code) 1444 { 1445 case NE: 1446 return "ne"; 1447 case EQ: 1448 return "eq"; 1449 case GE: 1450 return "ge"; 1451 case GT: 1452 return "gt"; 1453 case LE: 1454 return "le"; 1455 case LT: 1456 return "lt"; 1457 case GEU: 1458 return "hs"; 1459 case GTU: 1460 return "hi"; 1461 case LEU: 1462 return "ls"; 1463 case LTU: 1464 return "lo"; 1465 default: 1466 gcc_unreachable (); 1467 } 1468} 1469 1470/* Print operand X using operand code CODE to assembly language output file 1471 FILE. */ 1472 1473static void 1474h8300_print_operand (FILE *file, rtx x, int code) 1475{ 1476 /* This is used for communication between codes V,W,Z and Y. */ 1477 static int bitint; 1478 1479 switch (code) 1480 { 1481 case 'C': 1482 if (h8300_constant_length (x) == 2) 1483 fprintf (file, ":16"); 1484 else 1485 fprintf (file, ":32"); 1486 return; 1487 case 'E': 1488 switch (GET_CODE (x)) 1489 { 1490 case REG: 1491 fprintf (file, "%sl", names_big[REGNO (x)]); 1492 break; 1493 case CONST_INT: 1494 fprintf (file, "#%ld", (-INTVAL (x)) & 0xff); 1495 break; 1496 default: 1497 gcc_unreachable (); 1498 } 1499 break; 1500 case 'F': 1501 switch (GET_CODE (x)) 1502 { 1503 case REG: 1504 fprintf (file, "%sh", names_big[REGNO (x)]); 1505 break; 1506 case CONST_INT: 1507 fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8); 1508 break; 1509 default: 1510 gcc_unreachable (); 1511 } 1512 break; 1513 case 'G': 1514 gcc_assert (GET_CODE (x) == CONST_INT); 1515 fprintf (file, "#%ld", 0xff & (-INTVAL (x))); 1516 break; 1517 case 'S': 1518 if (GET_CODE (x) == REG) 1519 fprintf (file, "%s", names_extended[REGNO (x)]); 1520 else 1521 goto def; 1522 break; 1523 case 'T': 1524 if (GET_CODE (x) == REG) 1525 fprintf (file, "%s", names_big[REGNO (x)]); 1526 else 1527 goto def; 1528 break; 1529 case 'V': 1530 bitint = (INTVAL (x) & 0xffff); 1531 if ((exact_log2 ((bitint >> 8) & 0xff)) == -1) 1532 bitint = exact_log2 (bitint & 0xff); 1533 else 1534 bitint = exact_log2 ((bitint >> 8) & 0xff); 1535 gcc_assert (bitint >= 0); 1536 fprintf (file, "#%d", bitint); 1537 break; 1538 case 'W': 1539 bitint = ((~INTVAL (x)) & 0xffff); 1540 if ((exact_log2 ((bitint >> 8) & 0xff)) == -1 ) 1541 bitint = exact_log2 (bitint & 0xff); 1542 else 1543 bitint = (exact_log2 ((bitint >> 8) & 0xff)); 1544 gcc_assert (bitint >= 0); 1545 fprintf (file, "#%d", bitint); 1546 break; 1547 case 'R': 1548 case 'X': 1549 if (GET_CODE (x) == REG) 1550 fprintf (file, "%s", byte_reg (x, 0)); 1551 else 1552 goto def; 1553 break; 1554 case 'Y': 1555 gcc_assert (bitint >= 0); 1556 if (GET_CODE (x) == REG) 1557 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l'); 1558 else 1559 h8300_print_operand (file, x, 'R'); 1560 bitint = -1; 1561 break; 1562 case 'Z': 1563 bitint = INTVAL (x); 1564 fprintf (file, "#%d", bitint & 7); 1565 break; 1566 case 'c': 1567 switch (GET_CODE (x)) 1568 { 1569 case IOR: 1570 fprintf (file, "or"); 1571 break; 1572 case XOR: 1573 fprintf (file, "xor"); 1574 break; 1575 case AND: 1576 fprintf (file, "and"); 1577 break; 1578 default: 1579 break; 1580 } 1581 break; 1582 case 'e': 1583 switch (GET_CODE (x)) 1584 { 1585 case REG: 1586 if (TARGET_H8300) 1587 fprintf (file, "%s", names_big[REGNO (x)]); 1588 else 1589 fprintf (file, "%s", names_upper_extended[REGNO (x)]); 1590 break; 1591 case MEM: 1592 h8300_print_operand (file, x, 0); 1593 break; 1594 case CONST_INT: 1595 fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff)); 1596 break; 1597 case CONST_DOUBLE: 1598 { 1599 long val; 1600 REAL_VALUE_TYPE rv; 1601 REAL_VALUE_FROM_CONST_DOUBLE (rv, x); 1602 REAL_VALUE_TO_TARGET_SINGLE (rv, val); 1603 fprintf (file, "#%ld", ((val >> 16) & 0xffff)); 1604 break; 1605 } 1606 default: 1607 gcc_unreachable (); 1608 break; 1609 } 1610 break; 1611 case 'f': 1612 switch (GET_CODE (x)) 1613 { 1614 case REG: 1615 if (TARGET_H8300) 1616 fprintf (file, "%s", names_big[REGNO (x) + 1]); 1617 else 1618 fprintf (file, "%s", names_big[REGNO (x)]); 1619 break; 1620 case MEM: 1621 x = adjust_address (x, HImode, 2); 1622 h8300_print_operand (file, x, 0); 1623 break; 1624 case CONST_INT: 1625 fprintf (file, "#%ld", INTVAL (x) & 0xffff); 1626 break; 1627 case CONST_DOUBLE: 1628 { 1629 long val; 1630 REAL_VALUE_TYPE rv; 1631 REAL_VALUE_FROM_CONST_DOUBLE (rv, x); 1632 REAL_VALUE_TO_TARGET_SINGLE (rv, val); 1633 fprintf (file, "#%ld", (val & 0xffff)); 1634 break; 1635 } 1636 default: 1637 gcc_unreachable (); 1638 } 1639 break; 1640 case 'j': 1641 fputs (cond_string (GET_CODE (x)), file); 1642 break; 1643 case 'k': 1644 fputs (cond_string (reverse_condition (GET_CODE (x))), file); 1645 break; 1646 case 'm': 1647 gcc_assert (GET_CODE (x) == CONST_INT); 1648 switch (INTVAL (x)) 1649 { 1650 case 1: 1651 fputs (".b", file); 1652 break; 1653 1654 case 2: 1655 fputs (".w", file); 1656 break; 1657 1658 case 4: 1659 fputs (".l", file); 1660 break; 1661 1662 default: 1663 gcc_unreachable (); 1664 } 1665 break; 1666 case 'o': 1667 h8300_print_operand_address (file, x); 1668 break; 1669 case 's': 1670 if (GET_CODE (x) == CONST_INT) 1671 fprintf (file, "#%ld", (INTVAL (x)) & 0xff); 1672 else 1673 fprintf (file, "%s", byte_reg (x, 0)); 1674 break; 1675 case 't': 1676 if (GET_CODE (x) == CONST_INT) 1677 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff); 1678 else 1679 fprintf (file, "%s", byte_reg (x, 1)); 1680 break; 1681 case 'w': 1682 if (GET_CODE (x) == CONST_INT) 1683 fprintf (file, "#%ld", INTVAL (x) & 0xff); 1684 else 1685 fprintf (file, "%s", 1686 byte_reg (x, TARGET_H8300 ? 2 : 0)); 1687 break; 1688 case 'x': 1689 if (GET_CODE (x) == CONST_INT) 1690 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff); 1691 else 1692 fprintf (file, "%s", 1693 byte_reg (x, TARGET_H8300 ? 3 : 1)); 1694 break; 1695 case 'y': 1696 if (GET_CODE (x) == CONST_INT) 1697 fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff); 1698 else 1699 fprintf (file, "%s", byte_reg (x, 0)); 1700 break; 1701 case 'z': 1702 if (GET_CODE (x) == CONST_INT) 1703 fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff); 1704 else 1705 fprintf (file, "%s", byte_reg (x, 1)); 1706 break; 1707 1708 default: 1709 def: 1710 switch (GET_CODE (x)) 1711 { 1712 case REG: 1713 switch (GET_MODE (x)) 1714 { 1715 case QImode: 1716#if 0 /* Is it asm ("mov.b %0,r2l", ...) */ 1717 fprintf (file, "%s", byte_reg (x, 0)); 1718#else /* ... or is it asm ("mov.b %0l,r2l", ...) */ 1719 fprintf (file, "%s", names_big[REGNO (x)]); 1720#endif 1721 break; 1722 case HImode: 1723 fprintf (file, "%s", names_big[REGNO (x)]); 1724 break; 1725 case SImode: 1726 case SFmode: 1727 fprintf (file, "%s", names_extended[REGNO (x)]); 1728 break; 1729 default: 1730 gcc_unreachable (); 1731 } 1732 break; 1733 1734 case MEM: 1735 { 1736 rtx addr = XEXP (x, 0); 1737 1738 fprintf (file, "@"); 1739 output_address (addr); 1740 1741 /* Add a length suffix to constant addresses. Although this 1742 is often unnecessary, it helps to avoid ambiguity in the 1743 syntax of mova. If we wrote an insn like: 1744 1745 mova/w.l @(1,@foo.b),er0 1746 1747 then .b would be considered part of the symbol name. 1748 Adding a length after foo will avoid this. */ 1749 if (CONSTANT_P (addr)) 1750 switch (code) 1751 { 1752 case 'R': 1753 /* Used for mov.b and bit operations. */ 1754 if (h8300_eightbit_constant_address_p (addr)) 1755 { 1756 fprintf (file, ":8"); 1757 break; 1758 } 1759 1760 /* Fall through. We should not get here if we are 1761 processing bit operations on H8/300 or H8/300H 1762 because 'U' constraint does not allow bit 1763 operations on the tiny area on these machines. */ 1764 1765 case 'X': 1766 case 'T': 1767 case 'S': 1768 if (h8300_constant_length (addr) == 2) 1769 fprintf (file, ":16"); 1770 else 1771 fprintf (file, ":32"); 1772 break; 1773 default: 1774 break; 1775 } 1776 } 1777 break; 1778 1779 case CONST_INT: 1780 case SYMBOL_REF: 1781 case CONST: 1782 case LABEL_REF: 1783 fprintf (file, "#"); 1784 h8300_print_operand_address (file, x); 1785 break; 1786 case CONST_DOUBLE: 1787 { 1788 long val; 1789 REAL_VALUE_TYPE rv; 1790 REAL_VALUE_FROM_CONST_DOUBLE (rv, x); 1791 REAL_VALUE_TO_TARGET_SINGLE (rv, val); 1792 fprintf (file, "#%ld", val); 1793 break; 1794 } 1795 default: 1796 break; 1797 } 1798 } 1799} 1800 1801/* Implements TARGET_PRINT_OPERAND_PUNCT_VALID_P. */ 1802 1803static bool 1804h8300_print_operand_punct_valid_p (unsigned char code) 1805{ 1806 return (code == '#'); 1807} 1808 1809/* Output assembly language output for the address ADDR to FILE. */ 1810 1811static void 1812h8300_print_operand_address (FILE *file, rtx addr) 1813{ 1814 rtx index; 1815 int size; 1816 1817 switch (GET_CODE (addr)) 1818 { 1819 case REG: 1820 fprintf (file, "%s", h8_reg_names[REGNO (addr)]); 1821 break; 1822 1823 case PRE_DEC: 1824 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]); 1825 break; 1826 1827 case POST_INC: 1828 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]); 1829 break; 1830 1831 case PRE_INC: 1832 fprintf (file, "+%s", h8_reg_names[REGNO (XEXP (addr, 0))]); 1833 break; 1834 1835 case POST_DEC: 1836 fprintf (file, "%s-", h8_reg_names[REGNO (XEXP (addr, 0))]); 1837 break; 1838 1839 case PLUS: 1840 fprintf (file, "("); 1841 1842 index = h8300_get_index (XEXP (addr, 0), VOIDmode, &size); 1843 if (GET_CODE (index) == REG) 1844 { 1845 /* reg,foo */ 1846 h8300_print_operand_address (file, XEXP (addr, 1)); 1847 fprintf (file, ","); 1848 switch (size) 1849 { 1850 case 0: 1851 h8300_print_operand_address (file, index); 1852 break; 1853 1854 case 1: 1855 h8300_print_operand (file, index, 'X'); 1856 fputs (".b", file); 1857 break; 1858 1859 case 2: 1860 h8300_print_operand (file, index, 'T'); 1861 fputs (".w", file); 1862 break; 1863 1864 case 4: 1865 h8300_print_operand (file, index, 'S'); 1866 fputs (".l", file); 1867 break; 1868 } 1869 /* h8300_print_operand_address (file, XEXP (addr, 0)); */ 1870 } 1871 else 1872 { 1873 /* foo+k */ 1874 h8300_print_operand_address (file, XEXP (addr, 0)); 1875 fprintf (file, "+"); 1876 h8300_print_operand_address (file, XEXP (addr, 1)); 1877 } 1878 fprintf (file, ")"); 1879 break; 1880 1881 case CONST_INT: 1882 { 1883 /* Since the H8/300 only has 16-bit pointers, negative values are also 1884 those >= 32768. This happens for example with pointer minus a 1885 constant. We don't want to turn (char *p - 2) into 1886 (char *p + 65534) because loop unrolling can build upon this 1887 (IE: char *p + 131068). */ 1888 int n = INTVAL (addr); 1889 if (TARGET_H8300) 1890 n = (int) (short) n; 1891 fprintf (file, "%d", n); 1892 break; 1893 } 1894 1895 default: 1896 output_addr_const (file, addr); 1897 break; 1898 } 1899} 1900 1901/* Output all insn addresses and their sizes into the assembly language 1902 output file. This is helpful for debugging whether the length attributes 1903 in the md file are correct. This is not meant to be a user selectable 1904 option. */ 1905 1906void 1907final_prescan_insn (rtx_insn *insn, rtx *operand ATTRIBUTE_UNUSED, 1908 int num_operands ATTRIBUTE_UNUSED) 1909{ 1910 /* This holds the last insn address. */ 1911 static int last_insn_address = 0; 1912 1913 const int uid = INSN_UID (insn); 1914 1915 if (TARGET_ADDRESSES) 1916 { 1917 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid), 1918 INSN_ADDRESSES (uid) - last_insn_address); 1919 last_insn_address = INSN_ADDRESSES (uid); 1920 } 1921} 1922 1923/* Prepare for an SI sized move. */ 1924 1925int 1926h8300_expand_movsi (rtx operands[]) 1927{ 1928 rtx src = operands[1]; 1929 rtx dst = operands[0]; 1930 if (!reload_in_progress && !reload_completed) 1931 { 1932 if (!register_operand (dst, GET_MODE (dst))) 1933 { 1934 rtx tmp = gen_reg_rtx (GET_MODE (dst)); 1935 emit_move_insn (tmp, src); 1936 operands[1] = tmp; 1937 } 1938 } 1939 return 0; 1940} 1941 1942/* Given FROM and TO register numbers, say whether this elimination is allowed. 1943 Frame pointer elimination is automatically handled. 1944 1945 For the h8300, if frame pointer elimination is being done, we would like to 1946 convert ap and rp into sp, not fp. 1947 1948 All other eliminations are valid. */ 1949 1950static bool 1951h8300_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to) 1952{ 1953 return (to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true); 1954} 1955 1956/* Conditionally modify register usage based on target flags. */ 1957 1958static void 1959h8300_conditional_register_usage (void) 1960{ 1961 if (!TARGET_MAC) 1962 fixed_regs[MAC_REG] = call_used_regs[MAC_REG] = 1; 1963} 1964 1965/* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET). 1966 Define the offset between two registers, one to be eliminated, and 1967 the other its replacement, at the start of a routine. */ 1968 1969int 1970h8300_initial_elimination_offset (int from, int to) 1971{ 1972 /* The number of bytes that the return address takes on the stack. */ 1973 int pc_size = POINTER_SIZE / BITS_PER_UNIT; 1974 1975 /* The number of bytes that the saved frame pointer takes on the stack. */ 1976 int fp_size = frame_pointer_needed * UNITS_PER_WORD; 1977 1978 /* The number of bytes that the saved registers, excluding the frame 1979 pointer, take on the stack. */ 1980 int saved_regs_size = 0; 1981 1982 /* The number of bytes that the locals takes on the stack. */ 1983 int frame_size = round_frame_size (get_frame_size ()); 1984 1985 int regno; 1986 1987 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++) 1988 if (WORD_REG_USED (regno)) 1989 saved_regs_size += UNITS_PER_WORD; 1990 1991 /* Adjust saved_regs_size because the above loop took the frame 1992 pointer int account. */ 1993 saved_regs_size -= fp_size; 1994 1995 switch (to) 1996 { 1997 case HARD_FRAME_POINTER_REGNUM: 1998 switch (from) 1999 { 2000 case ARG_POINTER_REGNUM: 2001 return pc_size + fp_size; 2002 case RETURN_ADDRESS_POINTER_REGNUM: 2003 return fp_size; 2004 case FRAME_POINTER_REGNUM: 2005 return -saved_regs_size; 2006 default: 2007 gcc_unreachable (); 2008 } 2009 break; 2010 case STACK_POINTER_REGNUM: 2011 switch (from) 2012 { 2013 case ARG_POINTER_REGNUM: 2014 return pc_size + saved_regs_size + frame_size; 2015 case RETURN_ADDRESS_POINTER_REGNUM: 2016 return saved_regs_size + frame_size; 2017 case FRAME_POINTER_REGNUM: 2018 return frame_size; 2019 default: 2020 gcc_unreachable (); 2021 } 2022 break; 2023 default: 2024 gcc_unreachable (); 2025 } 2026 gcc_unreachable (); 2027} 2028 2029/* Worker function for RETURN_ADDR_RTX. */ 2030 2031rtx 2032h8300_return_addr_rtx (int count, rtx frame) 2033{ 2034 rtx ret; 2035 2036 if (count == 0) 2037 ret = gen_rtx_MEM (Pmode, 2038 gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM)); 2039 else if (flag_omit_frame_pointer) 2040 return (rtx) 0; 2041 else 2042 ret = gen_rtx_MEM (Pmode, 2043 memory_address (Pmode, 2044 plus_constant (Pmode, frame, 2045 UNITS_PER_WORD))); 2046 set_mem_alias_set (ret, get_frame_alias_set ()); 2047 return ret; 2048} 2049 2050/* Update the condition code from the insn. */ 2051 2052void 2053notice_update_cc (rtx body, rtx_insn *insn) 2054{ 2055 rtx set; 2056 2057 switch (get_attr_cc (insn)) 2058 { 2059 case CC_NONE: 2060 /* Insn does not affect CC at all. */ 2061 break; 2062 2063 case CC_NONE_0HIT: 2064 /* Insn does not change CC, but the 0'th operand has been changed. */ 2065 if (cc_status.value1 != 0 2066 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1)) 2067 cc_status.value1 = 0; 2068 if (cc_status.value2 != 0 2069 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value2)) 2070 cc_status.value2 = 0; 2071 break; 2072 2073 case CC_SET_ZN: 2074 /* Insn sets the Z,N flags of CC to recog_data.operand[0]. 2075 The V flag is unusable. The C flag may or may not be known but 2076 that's ok because alter_cond will change tests to use EQ/NE. */ 2077 CC_STATUS_INIT; 2078 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY; 2079 set = single_set (insn); 2080 cc_status.value1 = SET_SRC (set); 2081 if (SET_DEST (set) != cc0_rtx) 2082 cc_status.value2 = SET_DEST (set); 2083 break; 2084 2085 case CC_SET_ZNV: 2086 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0]. 2087 The C flag may or may not be known but that's ok because 2088 alter_cond will change tests to use EQ/NE. */ 2089 CC_STATUS_INIT; 2090 cc_status.flags |= CC_NO_CARRY; 2091 set = single_set (insn); 2092 cc_status.value1 = SET_SRC (set); 2093 if (SET_DEST (set) != cc0_rtx) 2094 { 2095 /* If the destination is STRICT_LOW_PART, strip off 2096 STRICT_LOW_PART. */ 2097 if (GET_CODE (SET_DEST (set)) == STRICT_LOW_PART) 2098 cc_status.value2 = XEXP (SET_DEST (set), 0); 2099 else 2100 cc_status.value2 = SET_DEST (set); 2101 } 2102 break; 2103 2104 case CC_COMPARE: 2105 /* The insn is a compare instruction. */ 2106 CC_STATUS_INIT; 2107 cc_status.value1 = SET_SRC (body); 2108 break; 2109 2110 case CC_CLOBBER: 2111 /* Insn doesn't leave CC in a usable state. */ 2112 CC_STATUS_INIT; 2113 break; 2114 } 2115} 2116 2117/* Given that X occurs in an address of the form (plus X constant), 2118 return the part of X that is expected to be a register. There are 2119 four kinds of addressing mode to recognize: 2120 2121 @(dd,Rn) 2122 @(dd,RnL.b) 2123 @(dd,Rn.w) 2124 @(dd,ERn.l) 2125 2126 If SIZE is nonnull, and the address is one of the last three forms, 2127 set *SIZE to the index multiplication factor. Set it to 0 for 2128 plain @(dd,Rn) addresses. 2129 2130 MODE is the mode of the value being accessed. It can be VOIDmode 2131 if the address is known to be valid, but its mode is unknown. */ 2132 2133static rtx 2134h8300_get_index (rtx x, machine_mode mode, int *size) 2135{ 2136 int dummy, factor; 2137 2138 if (size == 0) 2139 size = &dummy; 2140 2141 factor = (mode == VOIDmode ? 0 : GET_MODE_SIZE (mode)); 2142 if (TARGET_H8300SX 2143 && factor <= 4 2144 && (mode == VOIDmode 2145 || GET_MODE_CLASS (mode) == MODE_INT 2146 || GET_MODE_CLASS (mode) == MODE_FLOAT)) 2147 { 2148 if (factor <= 1 && GET_CODE (x) == ZERO_EXTEND) 2149 { 2150 /* When accessing byte-sized values, the index can be 2151 a zero-extended QImode or HImode register. */ 2152 *size = GET_MODE_SIZE (GET_MODE (XEXP (x, 0))); 2153 return XEXP (x, 0); 2154 } 2155 else 2156 { 2157 /* We're looking for addresses of the form: 2158 2159 (mult X I) 2160 or (mult (zero_extend X) I) 2161 2162 where I is the size of the operand being accessed. 2163 The canonical form of the second expression is: 2164 2165 (and (mult (subreg X) I) J) 2166 2167 where J == GET_MODE_MASK (GET_MODE (X)) * I. */ 2168 rtx index; 2169 2170 if (GET_CODE (x) == AND 2171 && GET_CODE (XEXP (x, 1)) == CONST_INT 2172 && (factor == 0 2173 || INTVAL (XEXP (x, 1)) == 0xff * factor 2174 || INTVAL (XEXP (x, 1)) == 0xffff * factor)) 2175 { 2176 index = XEXP (x, 0); 2177 *size = (INTVAL (XEXP (x, 1)) >= 0xffff ? 2 : 1); 2178 } 2179 else 2180 { 2181 index = x; 2182 *size = 4; 2183 } 2184 2185 if (GET_CODE (index) == MULT 2186 && GET_CODE (XEXP (index, 1)) == CONST_INT 2187 && (factor == 0 || factor == INTVAL (XEXP (index, 1)))) 2188 return XEXP (index, 0); 2189 } 2190 } 2191 *size = 0; 2192 return x; 2193} 2194 2195/* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P. 2196 2197 On the H8/300, the predecrement and postincrement address depend thus 2198 (the amount of decrement or increment being the length of the operand). */ 2199 2200static bool 2201h8300_mode_dependent_address_p (const_rtx addr, 2202 addr_space_t as ATTRIBUTE_UNUSED) 2203{ 2204 if (GET_CODE (addr) == PLUS 2205 && h8300_get_index (XEXP (addr, 0), VOIDmode, 0) != XEXP (addr, 0)) 2206 return true; 2207 2208 return false; 2209} 2210 2211static const h8300_length_table addb_length_table = 2212{ 2213 /* #xx Rs @aa @Rs @xx */ 2214 { 2, 2, 4, 4, 4 }, /* add.b xx,Rd */ 2215 { 4, 4, 4, 4, 6 }, /* add.b xx,@aa */ 2216 { 4, 4, 4, 4, 6 }, /* add.b xx,@Rd */ 2217 { 6, 4, 4, 4, 6 } /* add.b xx,@xx */ 2218}; 2219 2220static const h8300_length_table addw_length_table = 2221{ 2222 /* #xx Rs @aa @Rs @xx */ 2223 { 2, 2, 4, 4, 4 }, /* add.w xx,Rd */ 2224 { 4, 4, 4, 4, 6 }, /* add.w xx,@aa */ 2225 { 4, 4, 4, 4, 6 }, /* add.w xx,@Rd */ 2226 { 4, 4, 4, 4, 6 } /* add.w xx,@xx */ 2227}; 2228 2229static const h8300_length_table addl_length_table = 2230{ 2231 /* #xx Rs @aa @Rs @xx */ 2232 { 2, 2, 4, 4, 4 }, /* add.l xx,Rd */ 2233 { 4, 4, 6, 6, 6 }, /* add.l xx,@aa */ 2234 { 4, 4, 6, 6, 6 }, /* add.l xx,@Rd */ 2235 { 4, 4, 6, 6, 6 } /* add.l xx,@xx */ 2236}; 2237 2238#define logicb_length_table addb_length_table 2239#define logicw_length_table addw_length_table 2240 2241static const h8300_length_table logicl_length_table = 2242{ 2243 /* #xx Rs @aa @Rs @xx */ 2244 { 2, 4, 4, 4, 4 }, /* and.l xx,Rd */ 2245 { 4, 4, 6, 6, 6 }, /* and.l xx,@aa */ 2246 { 4, 4, 6, 6, 6 }, /* and.l xx,@Rd */ 2247 { 4, 4, 6, 6, 6 } /* and.l xx,@xx */ 2248}; 2249 2250static const h8300_length_table movb_length_table = 2251{ 2252 /* #xx Rs @aa @Rs @xx */ 2253 { 2, 2, 2, 2, 4 }, /* mov.b xx,Rd */ 2254 { 4, 2, 4, 4, 4 }, /* mov.b xx,@aa */ 2255 { 4, 2, 4, 4, 4 }, /* mov.b xx,@Rd */ 2256 { 4, 4, 4, 4, 4 } /* mov.b xx,@xx */ 2257}; 2258 2259#define movw_length_table movb_length_table 2260 2261static const h8300_length_table movl_length_table = 2262{ 2263 /* #xx Rs @aa @Rs @xx */ 2264 { 2, 2, 4, 4, 4 }, /* mov.l xx,Rd */ 2265 { 4, 4, 4, 4, 4 }, /* mov.l xx,@aa */ 2266 { 4, 4, 4, 4, 4 }, /* mov.l xx,@Rd */ 2267 { 4, 4, 4, 4, 4 } /* mov.l xx,@xx */ 2268}; 2269 2270/* Return the size of the given address or displacement constant. */ 2271 2272static unsigned int 2273h8300_constant_length (rtx constant) 2274{ 2275 /* Check for (@d:16,Reg). */ 2276 if (GET_CODE (constant) == CONST_INT 2277 && IN_RANGE (INTVAL (constant), -0x8000, 0x7fff)) 2278 return 2; 2279 2280 /* Check for (@d:16,Reg) in cases where the displacement is 2281 an absolute address. */ 2282 if (Pmode == HImode || h8300_tiny_constant_address_p (constant)) 2283 return 2; 2284 2285 return 4; 2286} 2287 2288/* Return the size of a displacement field in address ADDR, which should 2289 have the form (plus X constant). SIZE is the number of bytes being 2290 accessed. */ 2291 2292static unsigned int 2293h8300_displacement_length (rtx addr, int size) 2294{ 2295 rtx offset; 2296 2297 offset = XEXP (addr, 1); 2298 2299 /* Check for @(d:2,Reg). */ 2300 if (register_operand (XEXP (addr, 0), VOIDmode) 2301 && GET_CODE (offset) == CONST_INT 2302 && (INTVAL (offset) == size 2303 || INTVAL (offset) == size * 2 2304 || INTVAL (offset) == size * 3)) 2305 return 0; 2306 2307 return h8300_constant_length (offset); 2308} 2309 2310/* Store the class of operand OP in *OPCLASS and return the length of any 2311 extra operand fields. SIZE is the number of bytes in OP. OPCLASS 2312 can be null if only the length is needed. */ 2313 2314static unsigned int 2315h8300_classify_operand (rtx op, int size, enum h8300_operand_class *opclass) 2316{ 2317 enum h8300_operand_class dummy; 2318 2319 if (opclass == 0) 2320 opclass = &dummy; 2321 2322 if (CONSTANT_P (op)) 2323 { 2324 *opclass = H8OP_IMMEDIATE; 2325 2326 /* Byte-sized immediates are stored in the opcode fields. */ 2327 if (size == 1) 2328 return 0; 2329 2330 /* If this is a 32-bit instruction, see whether the constant 2331 will fit into a 16-bit immediate field. */ 2332 if (TARGET_H8300SX 2333 && size == 4 2334 && GET_CODE (op) == CONST_INT 2335 && IN_RANGE (INTVAL (op), 0, 0xffff)) 2336 return 2; 2337 2338 return size; 2339 } 2340 else if (GET_CODE (op) == MEM) 2341 { 2342 op = XEXP (op, 0); 2343 if (CONSTANT_P (op)) 2344 { 2345 *opclass = H8OP_MEM_ABSOLUTE; 2346 return h8300_constant_length (op); 2347 } 2348 else if (GET_CODE (op) == PLUS && CONSTANT_P (XEXP (op, 1))) 2349 { 2350 *opclass = H8OP_MEM_COMPLEX; 2351 return h8300_displacement_length (op, size); 2352 } 2353 else if (GET_RTX_CLASS (GET_CODE (op)) == RTX_AUTOINC) 2354 { 2355 *opclass = H8OP_MEM_COMPLEX; 2356 return 0; 2357 } 2358 else if (register_operand (op, VOIDmode)) 2359 { 2360 *opclass = H8OP_MEM_BASE; 2361 return 0; 2362 } 2363 } 2364 gcc_assert (register_operand (op, VOIDmode)); 2365 *opclass = H8OP_REGISTER; 2366 return 0; 2367} 2368 2369/* Return the length of the instruction described by TABLE given that 2370 its operands are OP1 and OP2. OP1 must be an h8300_dst_operand 2371 and OP2 must be an h8300_src_operand. */ 2372 2373static unsigned int 2374h8300_length_from_table (rtx op1, rtx op2, const h8300_length_table *table) 2375{ 2376 enum h8300_operand_class op1_class, op2_class; 2377 unsigned int size, immediate_length; 2378 2379 size = GET_MODE_SIZE (GET_MODE (op1)); 2380 immediate_length = (h8300_classify_operand (op1, size, &op1_class) 2381 + h8300_classify_operand (op2, size, &op2_class)); 2382 return immediate_length + (*table)[op1_class - 1][op2_class]; 2383} 2384 2385/* Return the length of a unary instruction such as neg or not given that 2386 its operand is OP. */ 2387 2388unsigned int 2389h8300_unary_length (rtx op) 2390{ 2391 enum h8300_operand_class opclass; 2392 unsigned int size, operand_length; 2393 2394 size = GET_MODE_SIZE (GET_MODE (op)); 2395 operand_length = h8300_classify_operand (op, size, &opclass); 2396 switch (opclass) 2397 { 2398 case H8OP_REGISTER: 2399 return 2; 2400 2401 case H8OP_MEM_BASE: 2402 return (size == 4 ? 6 : 4); 2403 2404 case H8OP_MEM_ABSOLUTE: 2405 return operand_length + (size == 4 ? 6 : 4); 2406 2407 case H8OP_MEM_COMPLEX: 2408 return operand_length + 6; 2409 2410 default: 2411 gcc_unreachable (); 2412 } 2413} 2414 2415/* Likewise short immediate instructions such as add.w #xx:3,OP. */ 2416 2417static unsigned int 2418h8300_short_immediate_length (rtx op) 2419{ 2420 enum h8300_operand_class opclass; 2421 unsigned int size, operand_length; 2422 2423 size = GET_MODE_SIZE (GET_MODE (op)); 2424 operand_length = h8300_classify_operand (op, size, &opclass); 2425 2426 switch (opclass) 2427 { 2428 case H8OP_REGISTER: 2429 return 2; 2430 2431 case H8OP_MEM_BASE: 2432 case H8OP_MEM_ABSOLUTE: 2433 case H8OP_MEM_COMPLEX: 2434 return 4 + operand_length; 2435 2436 default: 2437 gcc_unreachable (); 2438 } 2439} 2440 2441/* Likewise bitfield load and store instructions. */ 2442 2443static unsigned int 2444h8300_bitfield_length (rtx op, rtx op2) 2445{ 2446 enum h8300_operand_class opclass; 2447 unsigned int size, operand_length; 2448 2449 if (GET_CODE (op) == REG) 2450 op = op2; 2451 gcc_assert (GET_CODE (op) != REG); 2452 2453 size = GET_MODE_SIZE (GET_MODE (op)); 2454 operand_length = h8300_classify_operand (op, size, &opclass); 2455 2456 switch (opclass) 2457 { 2458 case H8OP_MEM_BASE: 2459 case H8OP_MEM_ABSOLUTE: 2460 case H8OP_MEM_COMPLEX: 2461 return 4 + operand_length; 2462 2463 default: 2464 gcc_unreachable (); 2465 } 2466} 2467 2468/* Calculate the length of general binary instruction INSN using TABLE. */ 2469 2470static unsigned int 2471h8300_binary_length (rtx_insn *insn, const h8300_length_table *table) 2472{ 2473 rtx set; 2474 2475 set = single_set (insn); 2476 gcc_assert (set); 2477 2478 if (BINARY_P (SET_SRC (set))) 2479 return h8300_length_from_table (XEXP (SET_SRC (set), 0), 2480 XEXP (SET_SRC (set), 1), table); 2481 else 2482 { 2483 gcc_assert (GET_RTX_CLASS (GET_CODE (SET_SRC (set))) == RTX_TERNARY); 2484 return h8300_length_from_table (XEXP (XEXP (SET_SRC (set), 1), 0), 2485 XEXP (XEXP (SET_SRC (set), 1), 1), 2486 table); 2487 } 2488} 2489 2490/* Subroutine of h8300_move_length. Return true if OP is 1- or 2-byte 2491 memory reference and either (1) it has the form @(d:16,Rn) or 2492 (2) its address has the code given by INC_CODE. */ 2493 2494static bool 2495h8300_short_move_mem_p (rtx op, enum rtx_code inc_code) 2496{ 2497 rtx addr; 2498 unsigned int size; 2499 2500 if (GET_CODE (op) != MEM) 2501 return false; 2502 2503 addr = XEXP (op, 0); 2504 size = GET_MODE_SIZE (GET_MODE (op)); 2505 if (size != 1 && size != 2) 2506 return false; 2507 2508 return (GET_CODE (addr) == inc_code 2509 || (GET_CODE (addr) == PLUS 2510 && GET_CODE (XEXP (addr, 0)) == REG 2511 && h8300_displacement_length (addr, size) == 2)); 2512} 2513 2514/* Calculate the length of move instruction INSN using the given length 2515 table. Although the tables are correct for most cases, there is some 2516 irregularity in the length of mov.b and mov.w. The following forms: 2517 2518 mov @ERs+, Rd 2519 mov @(d:16,ERs), Rd 2520 mov Rs, @-ERd 2521 mov Rs, @(d:16,ERd) 2522 2523 are two bytes shorter than most other "mov Rs, @complex" or 2524 "mov @complex,Rd" combinations. */ 2525 2526static unsigned int 2527h8300_move_length (rtx *operands, const h8300_length_table *table) 2528{ 2529 unsigned int size; 2530 2531 size = h8300_length_from_table (operands[0], operands[1], table); 2532 if (REG_P (operands[0]) && h8300_short_move_mem_p (operands[1], POST_INC)) 2533 size -= 2; 2534 if (REG_P (operands[1]) && h8300_short_move_mem_p (operands[0], PRE_DEC)) 2535 size -= 2; 2536 return size; 2537} 2538 2539/* Return the length of a mova instruction with the given operands. 2540 DEST is the register destination, SRC is the source address and 2541 OFFSET is the 16-bit or 32-bit displacement. */ 2542 2543static unsigned int 2544h8300_mova_length (rtx dest, rtx src, rtx offset) 2545{ 2546 unsigned int size; 2547 2548 size = (2 2549 + h8300_constant_length (offset) 2550 + h8300_classify_operand (src, GET_MODE_SIZE (GET_MODE (src)), 0)); 2551 if (!REG_P (dest) || !REG_P (src) || REGNO (src) != REGNO (dest)) 2552 size += 2; 2553 return size; 2554} 2555 2556/* Compute the length of INSN based on its length_table attribute. 2557 OPERANDS is the array of its operands. */ 2558 2559unsigned int 2560h8300_insn_length_from_table (rtx_insn *insn, rtx * operands) 2561{ 2562 switch (get_attr_length_table (insn)) 2563 { 2564 case LENGTH_TABLE_NONE: 2565 gcc_unreachable (); 2566 2567 case LENGTH_TABLE_ADDB: 2568 return h8300_binary_length (insn, &addb_length_table); 2569 2570 case LENGTH_TABLE_ADDW: 2571 return h8300_binary_length (insn, &addw_length_table); 2572 2573 case LENGTH_TABLE_ADDL: 2574 return h8300_binary_length (insn, &addl_length_table); 2575 2576 case LENGTH_TABLE_LOGICB: 2577 return h8300_binary_length (insn, &logicb_length_table); 2578 2579 case LENGTH_TABLE_MOVB: 2580 return h8300_move_length (operands, &movb_length_table); 2581 2582 case LENGTH_TABLE_MOVW: 2583 return h8300_move_length (operands, &movw_length_table); 2584 2585 case LENGTH_TABLE_MOVL: 2586 return h8300_move_length (operands, &movl_length_table); 2587 2588 case LENGTH_TABLE_MOVA: 2589 return h8300_mova_length (operands[0], operands[1], operands[2]); 2590 2591 case LENGTH_TABLE_MOVA_ZERO: 2592 return h8300_mova_length (operands[0], operands[1], const0_rtx); 2593 2594 case LENGTH_TABLE_UNARY: 2595 return h8300_unary_length (operands[0]); 2596 2597 case LENGTH_TABLE_MOV_IMM4: 2598 return 2 + h8300_classify_operand (operands[0], 0, 0); 2599 2600 case LENGTH_TABLE_SHORT_IMMEDIATE: 2601 return h8300_short_immediate_length (operands[0]); 2602 2603 case LENGTH_TABLE_BITFIELD: 2604 return h8300_bitfield_length (operands[0], operands[1]); 2605 2606 case LENGTH_TABLE_BITBRANCH: 2607 return h8300_bitfield_length (operands[1], operands[2]) - 2; 2608 2609 default: 2610 gcc_unreachable (); 2611 } 2612} 2613 2614/* Return true if LHS and RHS are memory references that can be mapped 2615 to the same h8sx assembly operand. LHS appears as the destination of 2616 an instruction and RHS appears as a source. 2617 2618 Three cases are allowed: 2619 2620 - RHS is @+Rn or @-Rn, LHS is @Rn 2621 - RHS is @Rn, LHS is @Rn+ or @Rn- 2622 - RHS and LHS have the same address and neither has side effects. */ 2623 2624bool 2625h8sx_mergeable_memrefs_p (rtx lhs, rtx rhs) 2626{ 2627 if (GET_CODE (rhs) == MEM && GET_CODE (lhs) == MEM) 2628 { 2629 rhs = XEXP (rhs, 0); 2630 lhs = XEXP (lhs, 0); 2631 2632 if (GET_CODE (rhs) == PRE_INC || GET_CODE (rhs) == PRE_DEC) 2633 return rtx_equal_p (XEXP (rhs, 0), lhs); 2634 2635 if (GET_CODE (lhs) == POST_INC || GET_CODE (lhs) == POST_DEC) 2636 return rtx_equal_p (rhs, XEXP (lhs, 0)); 2637 2638 if (rtx_equal_p (rhs, lhs)) 2639 return true; 2640 } 2641 return false; 2642} 2643 2644/* Return true if OPERANDS[1] can be mapped to the same assembly 2645 operand as OPERANDS[0]. */ 2646 2647bool 2648h8300_operands_match_p (rtx *operands) 2649{ 2650 if (register_operand (operands[0], VOIDmode) 2651 && register_operand (operands[1], VOIDmode)) 2652 return true; 2653 2654 if (h8sx_mergeable_memrefs_p (operands[0], operands[1])) 2655 return true; 2656 2657 return false; 2658} 2659 2660/* Try using movmd to move LENGTH bytes from memory region SRC to memory 2661 region DEST. The two regions do not overlap and have the common 2662 alignment given by ALIGNMENT. Return true on success. 2663 2664 Using movmd for variable-length moves seems to involve some 2665 complex trade-offs. For instance: 2666 2667 - Preparing for a movmd instruction is similar to preparing 2668 for a memcpy. The main difference is that the arguments 2669 are moved into er4, er5 and er6 rather than er0, er1 and er2. 2670 2671 - Since movmd clobbers the frame pointer, we need to save 2672 and restore it somehow when frame_pointer_needed. This can 2673 sometimes make movmd sequences longer than calls to memcpy(). 2674 2675 - The counter register is 16 bits, so the instruction is only 2676 suitable for variable-length moves when sizeof (size_t) == 2. 2677 That's only true in normal mode. 2678 2679 - We will often lack static alignment information. Falling back 2680 on movmd.b would likely be slower than calling memcpy(), at least 2681 for big moves. 2682 2683 This function therefore only uses movmd when the length is a 2684 known constant, and only then if -fomit-frame-pointer is in 2685 effect or if we're not optimizing for size. 2686 2687 At the moment the function uses movmd for all in-range constants, 2688 but it might be better to fall back on memcpy() for large moves 2689 if ALIGNMENT == 1. */ 2690 2691bool 2692h8sx_emit_movmd (rtx dest, rtx src, rtx length, 2693 HOST_WIDE_INT alignment) 2694{ 2695 if (!flag_omit_frame_pointer && optimize_size) 2696 return false; 2697 2698 if (GET_CODE (length) == CONST_INT) 2699 { 2700 rtx dest_reg, src_reg, first_dest, first_src; 2701 HOST_WIDE_INT n; 2702 int factor; 2703 2704 /* Use movmd.l if the alignment allows it, otherwise fall back 2705 on movmd.b. */ 2706 factor = (alignment >= 2 ? 4 : 1); 2707 2708 /* Make sure the length is within range. We can handle counter 2709 values up to 65536, although HImode truncation will make 2710 the count appear negative in rtl dumps. */ 2711 n = INTVAL (length); 2712 if (n <= 0 || n / factor > 65536) 2713 return false; 2714 2715 /* Create temporary registers for the source and destination 2716 pointers. Initialize them to the start of each region. */ 2717 dest_reg = copy_addr_to_reg (XEXP (dest, 0)); 2718 src_reg = copy_addr_to_reg (XEXP (src, 0)); 2719 2720 /* Create references to the movmd source and destination blocks. */ 2721 first_dest = replace_equiv_address (dest, dest_reg); 2722 first_src = replace_equiv_address (src, src_reg); 2723 2724 set_mem_size (first_dest, n & -factor); 2725 set_mem_size (first_src, n & -factor); 2726 2727 length = copy_to_mode_reg (HImode, gen_int_mode (n / factor, HImode)); 2728 emit_insn (gen_movmd (first_dest, first_src, length, GEN_INT (factor))); 2729 2730 if ((n & -factor) != n) 2731 { 2732 /* Move SRC and DEST past the region we just copied. 2733 This is done to update the memory attributes. */ 2734 dest = adjust_address (dest, BLKmode, n & -factor); 2735 src = adjust_address (src, BLKmode, n & -factor); 2736 2737 /* Replace the addresses with the source and destination 2738 registers, which movmd has left with the right values. */ 2739 dest = replace_equiv_address (dest, dest_reg); 2740 src = replace_equiv_address (src, src_reg); 2741 2742 /* Mop up the left-over bytes. */ 2743 if (n & 2) 2744 emit_move_insn (adjust_address (dest, HImode, 0), 2745 adjust_address (src, HImode, 0)); 2746 if (n & 1) 2747 emit_move_insn (adjust_address (dest, QImode, n & 2), 2748 adjust_address (src, QImode, n & 2)); 2749 } 2750 return true; 2751 } 2752 return false; 2753} 2754 2755/* Move ADDR into er6 after pushing its old value onto the stack. */ 2756 2757void 2758h8300_swap_into_er6 (rtx addr) 2759{ 2760 rtx insn = push (HARD_FRAME_POINTER_REGNUM, false); 2761 if (frame_pointer_needed) 2762 add_reg_note (insn, REG_CFA_DEF_CFA, 2763 plus_constant (Pmode, gen_rtx_MEM (Pmode, stack_pointer_rtx), 2764 2 * UNITS_PER_WORD)); 2765 else 2766 add_reg_note (insn, REG_CFA_ADJUST_CFA, 2767 gen_rtx_SET (VOIDmode, stack_pointer_rtx, 2768 plus_constant (Pmode, stack_pointer_rtx, 4))); 2769 2770 emit_move_insn (hard_frame_pointer_rtx, addr); 2771 if (REGNO (addr) == SP_REG) 2772 emit_move_insn (hard_frame_pointer_rtx, 2773 plus_constant (Pmode, hard_frame_pointer_rtx, 2774 GET_MODE_SIZE (word_mode))); 2775} 2776 2777/* Move the current value of er6 into ADDR and pop its old value 2778 from the stack. */ 2779 2780void 2781h8300_swap_out_of_er6 (rtx addr) 2782{ 2783 rtx insn; 2784 2785 if (REGNO (addr) != SP_REG) 2786 emit_move_insn (addr, hard_frame_pointer_rtx); 2787 2788 insn = pop (HARD_FRAME_POINTER_REGNUM); 2789 if (frame_pointer_needed) 2790 add_reg_note (insn, REG_CFA_DEF_CFA, 2791 plus_constant (Pmode, hard_frame_pointer_rtx, 2792 2 * UNITS_PER_WORD)); 2793 else 2794 add_reg_note (insn, REG_CFA_ADJUST_CFA, 2795 gen_rtx_SET (VOIDmode, stack_pointer_rtx, 2796 plus_constant (Pmode, stack_pointer_rtx, -4))); 2797} 2798 2799/* Return the length of mov instruction. */ 2800 2801unsigned int 2802compute_mov_length (rtx *operands) 2803{ 2804 /* If the mov instruction involves a memory operand, we compute the 2805 length, assuming the largest addressing mode is used, and then 2806 adjust later in the function. Otherwise, we compute and return 2807 the exact length in one step. */ 2808 machine_mode mode = GET_MODE (operands[0]); 2809 rtx dest = operands[0]; 2810 rtx src = operands[1]; 2811 rtx addr; 2812 2813 if (GET_CODE (src) == MEM) 2814 addr = XEXP (src, 0); 2815 else if (GET_CODE (dest) == MEM) 2816 addr = XEXP (dest, 0); 2817 else 2818 addr = NULL_RTX; 2819 2820 if (TARGET_H8300) 2821 { 2822 unsigned int base_length; 2823 2824 switch (mode) 2825 { 2826 case QImode: 2827 if (addr == NULL_RTX) 2828 return 2; 2829 2830 /* The eightbit addressing is available only in QImode, so 2831 go ahead and take care of it. */ 2832 if (h8300_eightbit_constant_address_p (addr)) 2833 return 2; 2834 2835 base_length = 4; 2836 break; 2837 2838 case HImode: 2839 if (addr == NULL_RTX) 2840 { 2841 if (REG_P (src)) 2842 return 2; 2843 2844 if (src == const0_rtx) 2845 return 2; 2846 2847 return 4; 2848 } 2849 2850 base_length = 4; 2851 break; 2852 2853 case SImode: 2854 if (addr == NULL_RTX) 2855 { 2856 if (REG_P (src)) 2857 return 4; 2858 2859 if (GET_CODE (src) == CONST_INT) 2860 { 2861 if (src == const0_rtx) 2862 return 4; 2863 2864 if ((INTVAL (src) & 0xffff) == 0) 2865 return 6; 2866 2867 if ((INTVAL (src) & 0xffff) == 0) 2868 return 6; 2869 2870 if ((INTVAL (src) & 0xffff) 2871 == ((INTVAL (src) >> 16) & 0xffff)) 2872 return 6; 2873 } 2874 return 8; 2875 } 2876 2877 base_length = 8; 2878 break; 2879 2880 case SFmode: 2881 if (addr == NULL_RTX) 2882 { 2883 if (REG_P (src)) 2884 return 4; 2885 2886 if (satisfies_constraint_G (src)) 2887 return 4; 2888 2889 return 8; 2890 } 2891 2892 base_length = 8; 2893 break; 2894 2895 default: 2896 gcc_unreachable (); 2897 } 2898 2899 /* Adjust the length based on the addressing mode used. 2900 Specifically, we subtract the difference between the actual 2901 length and the longest one, which is @(d:16,Rs). For SImode 2902 and SFmode, we double the adjustment because two mov.w are 2903 used to do the job. */ 2904 2905 /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */ 2906 if (GET_CODE (addr) == PRE_DEC 2907 || GET_CODE (addr) == POST_INC) 2908 { 2909 if (mode == QImode || mode == HImode) 2910 return base_length - 2; 2911 else 2912 /* In SImode and SFmode, we use two mov.w instructions, so 2913 double the adjustment. */ 2914 return base_length - 4; 2915 } 2916 2917 /* @Rs and @Rd are 2 bytes shorter than the longest. Note that 2918 in SImode and SFmode, the second mov.w involves an address 2919 with displacement, namely @(2,Rs) or @(2,Rd), so we subtract 2920 only 2 bytes. */ 2921 if (GET_CODE (addr) == REG) 2922 return base_length - 2; 2923 2924 return base_length; 2925 } 2926 else 2927 { 2928 unsigned int base_length; 2929 2930 switch (mode) 2931 { 2932 case QImode: 2933 if (addr == NULL_RTX) 2934 return 2; 2935 2936 /* The eightbit addressing is available only in QImode, so 2937 go ahead and take care of it. */ 2938 if (h8300_eightbit_constant_address_p (addr)) 2939 return 2; 2940 2941 base_length = 8; 2942 break; 2943 2944 case HImode: 2945 if (addr == NULL_RTX) 2946 { 2947 if (REG_P (src)) 2948 return 2; 2949 2950 if (src == const0_rtx) 2951 return 2; 2952 2953 return 4; 2954 } 2955 2956 base_length = 8; 2957 break; 2958 2959 case SImode: 2960 if (addr == NULL_RTX) 2961 { 2962 if (REG_P (src)) 2963 { 2964 if (REGNO (src) == MAC_REG || REGNO (dest) == MAC_REG) 2965 return 4; 2966 else 2967 return 2; 2968 } 2969 2970 if (GET_CODE (src) == CONST_INT) 2971 { 2972 int val = INTVAL (src); 2973 2974 if (val == 0) 2975 return 2; 2976 2977 if (val == (val & 0x00ff) || val == (val & 0xff00)) 2978 return 4; 2979 2980 switch (val & 0xffffffff) 2981 { 2982 case 0xffffffff: 2983 case 0xfffffffe: 2984 case 0xfffffffc: 2985 case 0x0000ffff: 2986 case 0x0000fffe: 2987 case 0xffff0000: 2988 case 0xfffe0000: 2989 case 0x00010000: 2990 case 0x00020000: 2991 return 4; 2992 } 2993 } 2994 return 6; 2995 } 2996 2997 base_length = 10; 2998 break; 2999 3000 case SFmode: 3001 if (addr == NULL_RTX) 3002 { 3003 if (REG_P (src)) 3004 return 2; 3005 3006 if (satisfies_constraint_G (src)) 3007 return 2; 3008 3009 return 6; 3010 } 3011 3012 base_length = 10; 3013 break; 3014 3015 default: 3016 gcc_unreachable (); 3017 } 3018 3019 /* Adjust the length based on the addressing mode used. 3020 Specifically, we subtract the difference between the actual 3021 length and the longest one, which is @(d:24,ERs). */ 3022 3023 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */ 3024 if (GET_CODE (addr) == PRE_DEC 3025 || GET_CODE (addr) == POST_INC) 3026 return base_length - 6; 3027 3028 /* @ERs and @ERd are 6 bytes shorter than the longest. */ 3029 if (GET_CODE (addr) == REG) 3030 return base_length - 6; 3031 3032 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the 3033 longest. */ 3034 if (GET_CODE (addr) == PLUS 3035 && GET_CODE (XEXP (addr, 0)) == REG 3036 && GET_CODE (XEXP (addr, 1)) == CONST_INT 3037 && INTVAL (XEXP (addr, 1)) > -32768 3038 && INTVAL (XEXP (addr, 1)) < 32767) 3039 return base_length - 4; 3040 3041 /* @aa:16 is 4 bytes shorter than the longest. */ 3042 if (h8300_tiny_constant_address_p (addr)) 3043 return base_length - 4; 3044 3045 /* @aa:24 is 2 bytes shorter than the longest. */ 3046 if (CONSTANT_P (addr)) 3047 return base_length - 2; 3048 3049 return base_length; 3050 } 3051} 3052 3053/* Output an addition insn. */ 3054 3055const char * 3056output_plussi (rtx *operands) 3057{ 3058 machine_mode mode = GET_MODE (operands[0]); 3059 3060 gcc_assert (mode == SImode); 3061 3062 if (TARGET_H8300) 3063 { 3064 if (GET_CODE (operands[2]) == REG) 3065 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0"; 3066 3067 if (GET_CODE (operands[2]) == CONST_INT) 3068 { 3069 HOST_WIDE_INT n = INTVAL (operands[2]); 3070 3071 if ((n & 0xffffff) == 0) 3072 return "add\t%z2,%z0"; 3073 if ((n & 0xffff) == 0) 3074 return "add\t%y2,%y0\n\taddx\t%z2,%z0"; 3075 if ((n & 0xff) == 0) 3076 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0"; 3077 } 3078 3079 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0"; 3080 } 3081 else 3082 { 3083 if (GET_CODE (operands[2]) == CONST_INT 3084 && register_operand (operands[1], VOIDmode)) 3085 { 3086 HOST_WIDE_INT intval = INTVAL (operands[2]); 3087 3088 if (TARGET_H8300SX && (intval >= 1 && intval <= 7)) 3089 return "add.l\t%S2,%S0"; 3090 if (TARGET_H8300SX && (intval >= -7 && intval <= -1)) 3091 return "sub.l\t%G2,%S0"; 3092 3093 /* See if we can finish with 2 bytes. */ 3094 3095 switch ((unsigned int) intval & 0xffffffff) 3096 { 3097 case 0x00000001: 3098 case 0x00000002: 3099 case 0x00000004: 3100 return "adds\t%2,%S0"; 3101 3102 case 0xffffffff: 3103 case 0xfffffffe: 3104 case 0xfffffffc: 3105 return "subs\t%G2,%S0"; 3106 3107 case 0x00010000: 3108 case 0x00020000: 3109 operands[2] = GEN_INT (intval >> 16); 3110 return "inc.w\t%2,%e0"; 3111 3112 case 0xffff0000: 3113 case 0xfffe0000: 3114 operands[2] = GEN_INT (intval >> 16); 3115 return "dec.w\t%G2,%e0"; 3116 } 3117 3118 /* See if we can finish with 4 bytes. */ 3119 if ((intval & 0xffff) == 0) 3120 { 3121 operands[2] = GEN_INT (intval >> 16); 3122 return "add.w\t%2,%e0"; 3123 } 3124 } 3125 3126 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) 3127 { 3128 operands[2] = GEN_INT (-INTVAL (operands[2])); 3129 return "sub.l\t%S2,%S0"; 3130 } 3131 return "add.l\t%S2,%S0"; 3132 } 3133} 3134 3135/* ??? It would be much easier to add the h8sx stuff if a single function 3136 classified the addition as either inc/dec, adds/subs, add.w or add.l. */ 3137/* Compute the length of an addition insn. */ 3138 3139unsigned int 3140compute_plussi_length (rtx *operands) 3141{ 3142 machine_mode mode = GET_MODE (operands[0]); 3143 3144 gcc_assert (mode == SImode); 3145 3146 if (TARGET_H8300) 3147 { 3148 if (GET_CODE (operands[2]) == REG) 3149 return 6; 3150 3151 if (GET_CODE (operands[2]) == CONST_INT) 3152 { 3153 HOST_WIDE_INT n = INTVAL (operands[2]); 3154 3155 if ((n & 0xffffff) == 0) 3156 return 2; 3157 if ((n & 0xffff) == 0) 3158 return 4; 3159 if ((n & 0xff) == 0) 3160 return 6; 3161 } 3162 3163 return 8; 3164 } 3165 else 3166 { 3167 if (GET_CODE (operands[2]) == CONST_INT 3168 && register_operand (operands[1], VOIDmode)) 3169 { 3170 HOST_WIDE_INT intval = INTVAL (operands[2]); 3171 3172 if (TARGET_H8300SX && (intval >= 1 && intval <= 7)) 3173 return 2; 3174 if (TARGET_H8300SX && (intval >= -7 && intval <= -1)) 3175 return 2; 3176 3177 /* See if we can finish with 2 bytes. */ 3178 3179 switch ((unsigned int) intval & 0xffffffff) 3180 { 3181 case 0x00000001: 3182 case 0x00000002: 3183 case 0x00000004: 3184 return 2; 3185 3186 case 0xffffffff: 3187 case 0xfffffffe: 3188 case 0xfffffffc: 3189 return 2; 3190 3191 case 0x00010000: 3192 case 0x00020000: 3193 return 2; 3194 3195 case 0xffff0000: 3196 case 0xfffe0000: 3197 return 2; 3198 } 3199 3200 /* See if we can finish with 4 bytes. */ 3201 if ((intval & 0xffff) == 0) 3202 return 4; 3203 } 3204 3205 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) 3206 return h8300_length_from_table (operands[0], 3207 GEN_INT (-INTVAL (operands[2])), 3208 &addl_length_table); 3209 else 3210 return h8300_length_from_table (operands[0], operands[2], 3211 &addl_length_table); 3212 return 6; 3213 } 3214} 3215 3216/* Compute which flag bits are valid after an addition insn. */ 3217 3218enum attr_cc 3219compute_plussi_cc (rtx *operands) 3220{ 3221 machine_mode mode = GET_MODE (operands[0]); 3222 3223 gcc_assert (mode == SImode); 3224 3225 if (TARGET_H8300) 3226 { 3227 return CC_CLOBBER; 3228 } 3229 else 3230 { 3231 if (GET_CODE (operands[2]) == CONST_INT 3232 && register_operand (operands[1], VOIDmode)) 3233 { 3234 HOST_WIDE_INT intval = INTVAL (operands[2]); 3235 3236 if (TARGET_H8300SX && (intval >= 1 && intval <= 7)) 3237 return CC_SET_ZN; 3238 if (TARGET_H8300SX && (intval >= -7 && intval <= -1)) 3239 return CC_SET_ZN; 3240 3241 /* See if we can finish with 2 bytes. */ 3242 3243 switch ((unsigned int) intval & 0xffffffff) 3244 { 3245 case 0x00000001: 3246 case 0x00000002: 3247 case 0x00000004: 3248 return CC_NONE_0HIT; 3249 3250 case 0xffffffff: 3251 case 0xfffffffe: 3252 case 0xfffffffc: 3253 return CC_NONE_0HIT; 3254 3255 case 0x00010000: 3256 case 0x00020000: 3257 return CC_CLOBBER; 3258 3259 case 0xffff0000: 3260 case 0xfffe0000: 3261 return CC_CLOBBER; 3262 } 3263 3264 /* See if we can finish with 4 bytes. */ 3265 if ((intval & 0xffff) == 0) 3266 return CC_CLOBBER; 3267 } 3268 3269 return CC_SET_ZN; 3270 } 3271} 3272 3273/* Output a logical insn. */ 3274 3275const char * 3276output_logical_op (machine_mode mode, rtx *operands) 3277{ 3278 /* Figure out the logical op that we need to perform. */ 3279 enum rtx_code code = GET_CODE (operands[3]); 3280 /* Pretend that every byte is affected if both operands are registers. */ 3281 const unsigned HOST_WIDE_INT intval = 3282 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT) 3283 /* Always use the full instruction if the 3284 first operand is in memory. It is better 3285 to use define_splits to generate the shorter 3286 sequence where valid. */ 3287 && register_operand (operands[1], VOIDmode) 3288 ? INTVAL (operands[2]) : 0x55555555); 3289 /* The determinant of the algorithm. If we perform an AND, 0 3290 affects a bit. Otherwise, 1 affects a bit. */ 3291 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval; 3292 /* Break up DET into pieces. */ 3293 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff; 3294 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff; 3295 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff; 3296 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff; 3297 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff; 3298 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff; 3299 int lower_half_easy_p = 0; 3300 int upper_half_easy_p = 0; 3301 /* The name of an insn. */ 3302 const char *opname; 3303 char insn_buf[100]; 3304 3305 switch (code) 3306 { 3307 case AND: 3308 opname = "and"; 3309 break; 3310 case IOR: 3311 opname = "or"; 3312 break; 3313 case XOR: 3314 opname = "xor"; 3315 break; 3316 default: 3317 gcc_unreachable (); 3318 } 3319 3320 switch (mode) 3321 { 3322 case HImode: 3323 /* First, see if we can finish with one insn. */ 3324 if ((TARGET_H8300H || TARGET_H8300S) 3325 && b0 != 0 3326 && b1 != 0) 3327 { 3328 sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname); 3329 output_asm_insn (insn_buf, operands); 3330 } 3331 else 3332 { 3333 /* Take care of the lower byte. */ 3334 if (b0 != 0) 3335 { 3336 sprintf (insn_buf, "%s\t%%s2,%%s0", opname); 3337 output_asm_insn (insn_buf, operands); 3338 } 3339 /* Take care of the upper byte. */ 3340 if (b1 != 0) 3341 { 3342 sprintf (insn_buf, "%s\t%%t2,%%t0", opname); 3343 output_asm_insn (insn_buf, operands); 3344 } 3345 } 3346 break; 3347 case SImode: 3348 if (TARGET_H8300H || TARGET_H8300S) 3349 { 3350 /* Determine if the lower half can be taken care of in no more 3351 than two bytes. */ 3352 lower_half_easy_p = (b0 == 0 3353 || b1 == 0 3354 || (code != IOR && w0 == 0xffff)); 3355 3356 /* Determine if the upper half can be taken care of in no more 3357 than two bytes. */ 3358 upper_half_easy_p = ((code != IOR && w1 == 0xffff) 3359 || (code == AND && w1 == 0xff00)); 3360 } 3361 3362 /* Check if doing everything with one insn is no worse than 3363 using multiple insns. */ 3364 if ((TARGET_H8300H || TARGET_H8300S) 3365 && w0 != 0 && w1 != 0 3366 && !(lower_half_easy_p && upper_half_easy_p) 3367 && !(code == IOR && w1 == 0xffff 3368 && (w0 & 0x8000) != 0 && lower_half_easy_p)) 3369 { 3370 sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname); 3371 output_asm_insn (insn_buf, operands); 3372 } 3373 else 3374 { 3375 /* Take care of the lower and upper words individually. For 3376 each word, we try different methods in the order of 3377 3378 1) the special insn (in case of AND or XOR), 3379 2) the word-wise insn, and 3380 3) The byte-wise insn. */ 3381 if (w0 == 0xffff 3382 && (TARGET_H8300 ? (code == AND) : (code != IOR))) 3383 output_asm_insn ((code == AND) 3384 ? "sub.w\t%f0,%f0" : "not.w\t%f0", 3385 operands); 3386 else if ((TARGET_H8300H || TARGET_H8300S) 3387 && (b0 != 0) 3388 && (b1 != 0)) 3389 { 3390 sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname); 3391 output_asm_insn (insn_buf, operands); 3392 } 3393 else 3394 { 3395 if (b0 != 0) 3396 { 3397 sprintf (insn_buf, "%s\t%%w2,%%w0", opname); 3398 output_asm_insn (insn_buf, operands); 3399 } 3400 if (b1 != 0) 3401 { 3402 sprintf (insn_buf, "%s\t%%x2,%%x0", opname); 3403 output_asm_insn (insn_buf, operands); 3404 } 3405 } 3406 3407 if ((w1 == 0xffff) 3408 && (TARGET_H8300 ? (code == AND) : (code != IOR))) 3409 output_asm_insn ((code == AND) 3410 ? "sub.w\t%e0,%e0" : "not.w\t%e0", 3411 operands); 3412 else if ((TARGET_H8300H || TARGET_H8300S) 3413 && code == IOR 3414 && w1 == 0xffff 3415 && (w0 & 0x8000) != 0) 3416 { 3417 output_asm_insn ("exts.l\t%S0", operands); 3418 } 3419 else if ((TARGET_H8300H || TARGET_H8300S) 3420 && code == AND 3421 && w1 == 0xff00) 3422 { 3423 output_asm_insn ("extu.w\t%e0", operands); 3424 } 3425 else if (TARGET_H8300H || TARGET_H8300S) 3426 { 3427 if (w1 != 0) 3428 { 3429 sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname); 3430 output_asm_insn (insn_buf, operands); 3431 } 3432 } 3433 else 3434 { 3435 if (b2 != 0) 3436 { 3437 sprintf (insn_buf, "%s\t%%y2,%%y0", opname); 3438 output_asm_insn (insn_buf, operands); 3439 } 3440 if (b3 != 0) 3441 { 3442 sprintf (insn_buf, "%s\t%%z2,%%z0", opname); 3443 output_asm_insn (insn_buf, operands); 3444 } 3445 } 3446 } 3447 break; 3448 default: 3449 gcc_unreachable (); 3450 } 3451 return ""; 3452} 3453 3454/* Compute the length of a logical insn. */ 3455 3456unsigned int 3457compute_logical_op_length (machine_mode mode, rtx *operands) 3458{ 3459 /* Figure out the logical op that we need to perform. */ 3460 enum rtx_code code = GET_CODE (operands[3]); 3461 /* Pretend that every byte is affected if both operands are registers. */ 3462 const unsigned HOST_WIDE_INT intval = 3463 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT) 3464 /* Always use the full instruction if the 3465 first operand is in memory. It is better 3466 to use define_splits to generate the shorter 3467 sequence where valid. */ 3468 && register_operand (operands[1], VOIDmode) 3469 ? INTVAL (operands[2]) : 0x55555555); 3470 /* The determinant of the algorithm. If we perform an AND, 0 3471 affects a bit. Otherwise, 1 affects a bit. */ 3472 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval; 3473 /* Break up DET into pieces. */ 3474 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff; 3475 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff; 3476 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff; 3477 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff; 3478 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff; 3479 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff; 3480 int lower_half_easy_p = 0; 3481 int upper_half_easy_p = 0; 3482 /* Insn length. */ 3483 unsigned int length = 0; 3484 3485 switch (mode) 3486 { 3487 case HImode: 3488 /* First, see if we can finish with one insn. */ 3489 if ((TARGET_H8300H || TARGET_H8300S) 3490 && b0 != 0 3491 && b1 != 0) 3492 { 3493 length = h8300_length_from_table (operands[1], operands[2], 3494 &logicw_length_table); 3495 } 3496 else 3497 { 3498 /* Take care of the lower byte. */ 3499 if (b0 != 0) 3500 length += 2; 3501 3502 /* Take care of the upper byte. */ 3503 if (b1 != 0) 3504 length += 2; 3505 } 3506 break; 3507 case SImode: 3508 if (TARGET_H8300H || TARGET_H8300S) 3509 { 3510 /* Determine if the lower half can be taken care of in no more 3511 than two bytes. */ 3512 lower_half_easy_p = (b0 == 0 3513 || b1 == 0 3514 || (code != IOR && w0 == 0xffff)); 3515 3516 /* Determine if the upper half can be taken care of in no more 3517 than two bytes. */ 3518 upper_half_easy_p = ((code != IOR && w1 == 0xffff) 3519 || (code == AND && w1 == 0xff00)); 3520 } 3521 3522 /* Check if doing everything with one insn is no worse than 3523 using multiple insns. */ 3524 if ((TARGET_H8300H || TARGET_H8300S) 3525 && w0 != 0 && w1 != 0 3526 && !(lower_half_easy_p && upper_half_easy_p) 3527 && !(code == IOR && w1 == 0xffff 3528 && (w0 & 0x8000) != 0 && lower_half_easy_p)) 3529 { 3530 length = h8300_length_from_table (operands[1], operands[2], 3531 &logicl_length_table); 3532 } 3533 else 3534 { 3535 /* Take care of the lower and upper words individually. For 3536 each word, we try different methods in the order of 3537 3538 1) the special insn (in case of AND or XOR), 3539 2) the word-wise insn, and 3540 3) The byte-wise insn. */ 3541 if (w0 == 0xffff 3542 && (TARGET_H8300 ? (code == AND) : (code != IOR))) 3543 { 3544 length += 2; 3545 } 3546 else if ((TARGET_H8300H || TARGET_H8300S) 3547 && (b0 != 0) 3548 && (b1 != 0)) 3549 { 3550 length += 4; 3551 } 3552 else 3553 { 3554 if (b0 != 0) 3555 length += 2; 3556 3557 if (b1 != 0) 3558 length += 2; 3559 } 3560 3561 if (w1 == 0xffff 3562 && (TARGET_H8300 ? (code == AND) : (code != IOR))) 3563 { 3564 length += 2; 3565 } 3566 else if ((TARGET_H8300H || TARGET_H8300S) 3567 && code == IOR 3568 && w1 == 0xffff 3569 && (w0 & 0x8000) != 0) 3570 { 3571 length += 2; 3572 } 3573 else if ((TARGET_H8300H || TARGET_H8300S) 3574 && code == AND 3575 && w1 == 0xff00) 3576 { 3577 length += 2; 3578 } 3579 else if (TARGET_H8300H || TARGET_H8300S) 3580 { 3581 if (w1 != 0) 3582 length += 4; 3583 } 3584 else 3585 { 3586 if (b2 != 0) 3587 length += 2; 3588 3589 if (b3 != 0) 3590 length += 2; 3591 } 3592 } 3593 break; 3594 default: 3595 gcc_unreachable (); 3596 } 3597 return length; 3598} 3599 3600/* Compute which flag bits are valid after a logical insn. */ 3601 3602enum attr_cc 3603compute_logical_op_cc (machine_mode mode, rtx *operands) 3604{ 3605 /* Figure out the logical op that we need to perform. */ 3606 enum rtx_code code = GET_CODE (operands[3]); 3607 /* Pretend that every byte is affected if both operands are registers. */ 3608 const unsigned HOST_WIDE_INT intval = 3609 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT) 3610 /* Always use the full instruction if the 3611 first operand is in memory. It is better 3612 to use define_splits to generate the shorter 3613 sequence where valid. */ 3614 && register_operand (operands[1], VOIDmode) 3615 ? INTVAL (operands[2]) : 0x55555555); 3616 /* The determinant of the algorithm. If we perform an AND, 0 3617 affects a bit. Otherwise, 1 affects a bit. */ 3618 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval; 3619 /* Break up DET into pieces. */ 3620 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff; 3621 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff; 3622 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff; 3623 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff; 3624 int lower_half_easy_p = 0; 3625 int upper_half_easy_p = 0; 3626 /* Condition code. */ 3627 enum attr_cc cc = CC_CLOBBER; 3628 3629 switch (mode) 3630 { 3631 case HImode: 3632 /* First, see if we can finish with one insn. */ 3633 if ((TARGET_H8300H || TARGET_H8300S) 3634 && b0 != 0 3635 && b1 != 0) 3636 { 3637 cc = CC_SET_ZNV; 3638 } 3639 break; 3640 case SImode: 3641 if (TARGET_H8300H || TARGET_H8300S) 3642 { 3643 /* Determine if the lower half can be taken care of in no more 3644 than two bytes. */ 3645 lower_half_easy_p = (b0 == 0 3646 || b1 == 0 3647 || (code != IOR && w0 == 0xffff)); 3648 3649 /* Determine if the upper half can be taken care of in no more 3650 than two bytes. */ 3651 upper_half_easy_p = ((code != IOR && w1 == 0xffff) 3652 || (code == AND && w1 == 0xff00)); 3653 } 3654 3655 /* Check if doing everything with one insn is no worse than 3656 using multiple insns. */ 3657 if ((TARGET_H8300H || TARGET_H8300S) 3658 && w0 != 0 && w1 != 0 3659 && !(lower_half_easy_p && upper_half_easy_p) 3660 && !(code == IOR && w1 == 0xffff 3661 && (w0 & 0x8000) != 0 && lower_half_easy_p)) 3662 { 3663 cc = CC_SET_ZNV; 3664 } 3665 else 3666 { 3667 if ((TARGET_H8300H || TARGET_H8300S) 3668 && code == IOR 3669 && w1 == 0xffff 3670 && (w0 & 0x8000) != 0) 3671 { 3672 cc = CC_SET_ZNV; 3673 } 3674 } 3675 break; 3676 default: 3677 gcc_unreachable (); 3678 } 3679 return cc; 3680} 3681 3682/* Expand a conditional branch. */ 3683 3684void 3685h8300_expand_branch (rtx operands[]) 3686{ 3687 enum rtx_code code = GET_CODE (operands[0]); 3688 rtx op0 = operands[1]; 3689 rtx op1 = operands[2]; 3690 rtx label = operands[3]; 3691 rtx tmp; 3692 3693 tmp = gen_rtx_COMPARE (VOIDmode, op0, op1); 3694 emit_insn (gen_rtx_SET (VOIDmode, cc0_rtx, tmp)); 3695 3696 tmp = gen_rtx_fmt_ee (code, VOIDmode, cc0_rtx, const0_rtx); 3697 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp, 3698 gen_rtx_LABEL_REF (VOIDmode, label), 3699 pc_rtx); 3700 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp)); 3701} 3702 3703 3704/* Expand a conditional store. */ 3705 3706void 3707h8300_expand_store (rtx operands[]) 3708{ 3709 rtx dest = operands[0]; 3710 enum rtx_code code = GET_CODE (operands[1]); 3711 rtx op0 = operands[2]; 3712 rtx op1 = operands[3]; 3713 rtx tmp; 3714 3715 tmp = gen_rtx_COMPARE (VOIDmode, op0, op1); 3716 emit_insn (gen_rtx_SET (VOIDmode, cc0_rtx, tmp)); 3717 3718 tmp = gen_rtx_fmt_ee (code, GET_MODE (dest), cc0_rtx, const0_rtx); 3719 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp)); 3720} 3721 3722/* Shifts. 3723 3724 We devote a fair bit of code to getting efficient shifts since we 3725 can only shift one bit at a time on the H8/300 and H8/300H and only 3726 one or two bits at a time on the H8S. 3727 3728 All shift code falls into one of the following ways of 3729 implementation: 3730 3731 o SHIFT_INLINE: Emit straight line code for the shift; this is used 3732 when a straight line shift is about the same size or smaller than 3733 a loop. 3734 3735 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask 3736 off the bits we don't need. This is used when only a few of the 3737 bits in the original value will survive in the shifted value. 3738 3739 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to 3740 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline 3741 shifts can be added if the shift count is slightly more than 8 or 3742 16. This case also includes other oddballs that are not worth 3743 explaining here. 3744 3745 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts. 3746 3747 For each shift count, we try to use code that has no trade-off 3748 between code size and speed whenever possible. 3749 3750 If the trade-off is unavoidable, we try to be reasonable. 3751 Specifically, the fastest version is one instruction longer than 3752 the shortest version, we take the fastest version. We also provide 3753 the use a way to switch back to the shortest version with -Os. 3754 3755 For the details of the shift algorithms for various shift counts, 3756 refer to shift_alg_[qhs]i. */ 3757 3758/* Classify a shift with the given mode and code. OP is the shift amount. */ 3759 3760enum h8sx_shift_type 3761h8sx_classify_shift (machine_mode mode, enum rtx_code code, rtx op) 3762{ 3763 if (!TARGET_H8300SX) 3764 return H8SX_SHIFT_NONE; 3765 3766 switch (code) 3767 { 3768 case ASHIFT: 3769 case LSHIFTRT: 3770 /* Check for variable shifts (shll Rs,Rd and shlr Rs,Rd). */ 3771 if (GET_CODE (op) != CONST_INT) 3772 return H8SX_SHIFT_BINARY; 3773 3774 /* Reject out-of-range shift amounts. */ 3775 if (INTVAL (op) <= 0 || INTVAL (op) >= GET_MODE_BITSIZE (mode)) 3776 return H8SX_SHIFT_NONE; 3777 3778 /* Power-of-2 shifts are effectively unary operations. */ 3779 if (exact_log2 (INTVAL (op)) >= 0) 3780 return H8SX_SHIFT_UNARY; 3781 3782 return H8SX_SHIFT_BINARY; 3783 3784 case ASHIFTRT: 3785 if (op == const1_rtx || op == const2_rtx) 3786 return H8SX_SHIFT_UNARY; 3787 return H8SX_SHIFT_NONE; 3788 3789 case ROTATE: 3790 if (GET_CODE (op) == CONST_INT 3791 && (INTVAL (op) == 1 3792 || INTVAL (op) == 2 3793 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 2 3794 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 1)) 3795 return H8SX_SHIFT_UNARY; 3796 return H8SX_SHIFT_NONE; 3797 3798 default: 3799 return H8SX_SHIFT_NONE; 3800 } 3801} 3802 3803/* Return the asm template for a single h8sx shift instruction. 3804 OPERANDS[0] and OPERANDS[1] are the destination, OPERANDS[2] 3805 is the source and OPERANDS[3] is the shift. SUFFIX is the 3806 size suffix ('b', 'w' or 'l') and OPTYPE is the h8300_print_operand 3807 prefix for the destination operand. */ 3808 3809const char * 3810output_h8sx_shift (rtx *operands, int suffix, int optype) 3811{ 3812 static char buffer[16]; 3813 const char *stem; 3814 3815 switch (GET_CODE (operands[3])) 3816 { 3817 case ASHIFT: 3818 stem = "shll"; 3819 break; 3820 3821 case ASHIFTRT: 3822 stem = "shar"; 3823 break; 3824 3825 case LSHIFTRT: 3826 stem = "shlr"; 3827 break; 3828 3829 case ROTATE: 3830 stem = "rotl"; 3831 if (INTVAL (operands[2]) > 2) 3832 { 3833 /* This is really a right rotate. */ 3834 operands[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands[0])) 3835 - INTVAL (operands[2])); 3836 stem = "rotr"; 3837 } 3838 break; 3839 3840 default: 3841 gcc_unreachable (); 3842 } 3843 if (operands[2] == const1_rtx) 3844 sprintf (buffer, "%s.%c\t%%%c0", stem, suffix, optype); 3845 else 3846 sprintf (buffer, "%s.%c\t%%X2,%%%c0", stem, suffix, optype); 3847 return buffer; 3848} 3849 3850/* Emit code to do shifts. */ 3851 3852bool 3853expand_a_shift (machine_mode mode, enum rtx_code code, rtx operands[]) 3854{ 3855 switch (h8sx_classify_shift (mode, code, operands[2])) 3856 { 3857 case H8SX_SHIFT_BINARY: 3858 operands[1] = force_reg (mode, operands[1]); 3859 return false; 3860 3861 case H8SX_SHIFT_UNARY: 3862 return false; 3863 3864 case H8SX_SHIFT_NONE: 3865 break; 3866 } 3867 3868 emit_move_insn (copy_rtx (operands[0]), operands[1]); 3869 3870 /* Need a loop to get all the bits we want - we generate the 3871 code at emit time, but need to allocate a scratch reg now. */ 3872 3873 emit_insn (gen_rtx_PARALLEL 3874 (VOIDmode, 3875 gen_rtvec (2, 3876 gen_rtx_SET (VOIDmode, copy_rtx (operands[0]), 3877 gen_rtx_fmt_ee (code, mode, 3878 copy_rtx (operands[0]), operands[2])), 3879 gen_rtx_CLOBBER (VOIDmode, 3880 gen_rtx_SCRATCH (QImode))))); 3881 return true; 3882} 3883 3884/* Symbols of the various modes which can be used as indices. */ 3885 3886enum shift_mode 3887{ 3888 QIshift, HIshift, SIshift 3889}; 3890 3891/* For single bit shift insns, record assembler and what bits of the 3892 condition code are valid afterwards (represented as various CC_FOO 3893 bits, 0 means CC isn't left in a usable state). */ 3894 3895struct shift_insn 3896{ 3897 const char *const assembler; 3898 const enum attr_cc cc_valid; 3899}; 3900 3901/* Assembler instruction shift table. 3902 3903 These tables are used to look up the basic shifts. 3904 They are indexed by cpu, shift_type, and mode. */ 3905 3906static const struct shift_insn shift_one[2][3][3] = 3907{ 3908/* H8/300 */ 3909 { 3910/* SHIFT_ASHIFT */ 3911 { 3912 { "shll\t%X0", CC_SET_ZNV }, 3913 { "add.w\t%T0,%T0", CC_SET_ZN }, 3914 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER } 3915 }, 3916/* SHIFT_LSHIFTRT */ 3917 { 3918 { "shlr\t%X0", CC_SET_ZNV }, 3919 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER }, 3920 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER } 3921 }, 3922/* SHIFT_ASHIFTRT */ 3923 { 3924 { "shar\t%X0", CC_SET_ZNV }, 3925 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER }, 3926 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER } 3927 } 3928 }, 3929/* H8/300H */ 3930 { 3931/* SHIFT_ASHIFT */ 3932 { 3933 { "shll.b\t%X0", CC_SET_ZNV }, 3934 { "shll.w\t%T0", CC_SET_ZNV }, 3935 { "shll.l\t%S0", CC_SET_ZNV } 3936 }, 3937/* SHIFT_LSHIFTRT */ 3938 { 3939 { "shlr.b\t%X0", CC_SET_ZNV }, 3940 { "shlr.w\t%T0", CC_SET_ZNV }, 3941 { "shlr.l\t%S0", CC_SET_ZNV } 3942 }, 3943/* SHIFT_ASHIFTRT */ 3944 { 3945 { "shar.b\t%X0", CC_SET_ZNV }, 3946 { "shar.w\t%T0", CC_SET_ZNV }, 3947 { "shar.l\t%S0", CC_SET_ZNV } 3948 } 3949 } 3950}; 3951 3952static const struct shift_insn shift_two[3][3] = 3953{ 3954/* SHIFT_ASHIFT */ 3955 { 3956 { "shll.b\t#2,%X0", CC_SET_ZNV }, 3957 { "shll.w\t#2,%T0", CC_SET_ZNV }, 3958 { "shll.l\t#2,%S0", CC_SET_ZNV } 3959 }, 3960/* SHIFT_LSHIFTRT */ 3961 { 3962 { "shlr.b\t#2,%X0", CC_SET_ZNV }, 3963 { "shlr.w\t#2,%T0", CC_SET_ZNV }, 3964 { "shlr.l\t#2,%S0", CC_SET_ZNV } 3965 }, 3966/* SHIFT_ASHIFTRT */ 3967 { 3968 { "shar.b\t#2,%X0", CC_SET_ZNV }, 3969 { "shar.w\t#2,%T0", CC_SET_ZNV }, 3970 { "shar.l\t#2,%S0", CC_SET_ZNV } 3971 } 3972}; 3973 3974/* Rotates are organized by which shift they'll be used in implementing. 3975 There's no need to record whether the cc is valid afterwards because 3976 it is the AND insn that will decide this. */ 3977 3978static const char *const rotate_one[2][3][3] = 3979{ 3980/* H8/300 */ 3981 { 3982/* SHIFT_ASHIFT */ 3983 { 3984 "rotr\t%X0", 3985 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0", 3986 0 3987 }, 3988/* SHIFT_LSHIFTRT */ 3989 { 3990 "rotl\t%X0", 3991 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0", 3992 0 3993 }, 3994/* SHIFT_ASHIFTRT */ 3995 { 3996 "rotl\t%X0", 3997 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0", 3998 0 3999 } 4000 }, 4001/* H8/300H */ 4002 { 4003/* SHIFT_ASHIFT */ 4004 { 4005 "rotr.b\t%X0", 4006 "rotr.w\t%T0", 4007 "rotr.l\t%S0" 4008 }, 4009/* SHIFT_LSHIFTRT */ 4010 { 4011 "rotl.b\t%X0", 4012 "rotl.w\t%T0", 4013 "rotl.l\t%S0" 4014 }, 4015/* SHIFT_ASHIFTRT */ 4016 { 4017 "rotl.b\t%X0", 4018 "rotl.w\t%T0", 4019 "rotl.l\t%S0" 4020 } 4021 } 4022}; 4023 4024static const char *const rotate_two[3][3] = 4025{ 4026/* SHIFT_ASHIFT */ 4027 { 4028 "rotr.b\t#2,%X0", 4029 "rotr.w\t#2,%T0", 4030 "rotr.l\t#2,%S0" 4031 }, 4032/* SHIFT_LSHIFTRT */ 4033 { 4034 "rotl.b\t#2,%X0", 4035 "rotl.w\t#2,%T0", 4036 "rotl.l\t#2,%S0" 4037 }, 4038/* SHIFT_ASHIFTRT */ 4039 { 4040 "rotl.b\t#2,%X0", 4041 "rotl.w\t#2,%T0", 4042 "rotl.l\t#2,%S0" 4043 } 4044}; 4045 4046struct shift_info { 4047 /* Shift algorithm. */ 4048 enum shift_alg alg; 4049 4050 /* The number of bits to be shifted by shift1 and shift2. Valid 4051 when ALG is SHIFT_SPECIAL. */ 4052 unsigned int remainder; 4053 4054 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */ 4055 const char *special; 4056 4057 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE 4058 or SHIFT_SPECIAL, and REMAINDER is nonzero. */ 4059 const char *shift1; 4060 4061 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE 4062 or SHIFT_SPECIAL, and REMAINDER is nonzero. */ 4063 const char *shift2; 4064 4065 /* CC status for SHIFT_INLINE. */ 4066 enum attr_cc cc_inline; 4067 4068 /* CC status for SHIFT_SPECIAL. */ 4069 enum attr_cc cc_special; 4070}; 4071 4072static void get_shift_alg (enum shift_type, 4073 enum shift_mode, unsigned int, 4074 struct shift_info *); 4075 4076/* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the 4077 best algorithm for doing the shift. The assembler code is stored 4078 in the pointers in INFO. We achieve the maximum efficiency in most 4079 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in 4080 SImode in particular have a lot of room to optimize. 4081 4082 We first determine the strategy of the shift algorithm by a table 4083 lookup. If that tells us to use a hand crafted assembly code, we 4084 go into the big switch statement to find what that is. Otherwise, 4085 we resort to a generic way, such as inlining. In either case, the 4086 result is returned through INFO. */ 4087 4088static void 4089get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode, 4090 unsigned int count, struct shift_info *info) 4091{ 4092 enum h8_cpu cpu; 4093 4094 /* Find the target CPU. */ 4095 if (TARGET_H8300) 4096 cpu = H8_300; 4097 else if (TARGET_H8300H) 4098 cpu = H8_300H; 4099 else 4100 cpu = H8_S; 4101 4102 /* Find the shift algorithm. */ 4103 info->alg = SHIFT_LOOP; 4104 switch (shift_mode) 4105 { 4106 case QIshift: 4107 if (count < GET_MODE_BITSIZE (QImode)) 4108 info->alg = shift_alg_qi[cpu][shift_type][count]; 4109 break; 4110 4111 case HIshift: 4112 if (count < GET_MODE_BITSIZE (HImode)) 4113 info->alg = shift_alg_hi[cpu][shift_type][count]; 4114 break; 4115 4116 case SIshift: 4117 if (count < GET_MODE_BITSIZE (SImode)) 4118 info->alg = shift_alg_si[cpu][shift_type][count]; 4119 break; 4120 4121 default: 4122 gcc_unreachable (); 4123 } 4124 4125 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */ 4126 switch (info->alg) 4127 { 4128 case SHIFT_INLINE: 4129 info->remainder = count; 4130 /* Fall through. */ 4131 4132 case SHIFT_LOOP: 4133 /* It is up to the caller to know that looping clobbers cc. */ 4134 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler; 4135 info->shift2 = shift_two[shift_type][shift_mode].assembler; 4136 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid; 4137 goto end; 4138 4139 case SHIFT_ROT_AND: 4140 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode]; 4141 info->shift2 = rotate_two[shift_type][shift_mode]; 4142 info->cc_inline = CC_CLOBBER; 4143 goto end; 4144 4145 case SHIFT_SPECIAL: 4146 /* REMAINDER is 0 for most cases, so initialize it to 0. */ 4147 info->remainder = 0; 4148 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler; 4149 info->shift2 = shift_two[shift_type][shift_mode].assembler; 4150 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid; 4151 info->cc_special = CC_CLOBBER; 4152 break; 4153 } 4154 4155 /* Here we only deal with SHIFT_SPECIAL. */ 4156 switch (shift_mode) 4157 { 4158 case QIshift: 4159 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated 4160 through the entire value. */ 4161 gcc_assert (shift_type == SHIFT_ASHIFTRT && count == 7); 4162 info->special = "shll\t%X0\n\tsubx\t%X0,%X0"; 4163 goto end; 4164 4165 case HIshift: 4166 if (count == 7) 4167 { 4168 switch (shift_type) 4169 { 4170 case SHIFT_ASHIFT: 4171 if (TARGET_H8300) 4172 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0"; 4173 else 4174 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0"; 4175 goto end; 4176 case SHIFT_LSHIFTRT: 4177 if (TARGET_H8300) 4178 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0"; 4179 else 4180 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0"; 4181 goto end; 4182 case SHIFT_ASHIFTRT: 4183 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0"; 4184 goto end; 4185 } 4186 } 4187 else if ((8 <= count && count <= 13) 4188 || (TARGET_H8300S && count == 14)) 4189 { 4190 info->remainder = count - 8; 4191 4192 switch (shift_type) 4193 { 4194 case SHIFT_ASHIFT: 4195 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0"; 4196 goto end; 4197 case SHIFT_LSHIFTRT: 4198 if (TARGET_H8300) 4199 { 4200 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0"; 4201 info->shift1 = "shlr.b\t%s0"; 4202 info->cc_inline = CC_SET_ZNV; 4203 } 4204 else 4205 { 4206 info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0"; 4207 info->cc_special = CC_SET_ZNV; 4208 } 4209 goto end; 4210 case SHIFT_ASHIFTRT: 4211 if (TARGET_H8300) 4212 { 4213 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0"; 4214 info->shift1 = "shar.b\t%s0"; 4215 } 4216 else 4217 { 4218 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0"; 4219 info->cc_special = CC_SET_ZNV; 4220 } 4221 goto end; 4222 } 4223 } 4224 else if (count == 14) 4225 { 4226 switch (shift_type) 4227 { 4228 case SHIFT_ASHIFT: 4229 if (TARGET_H8300) 4230 info->special = "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0"; 4231 goto end; 4232 case SHIFT_LSHIFTRT: 4233 if (TARGET_H8300) 4234 info->special = "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0"; 4235 goto end; 4236 case SHIFT_ASHIFTRT: 4237 if (TARGET_H8300) 4238 info->special = "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0"; 4239 else if (TARGET_H8300H) 4240 { 4241 info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0"; 4242 info->cc_special = CC_SET_ZNV; 4243 } 4244 else /* TARGET_H8300S */ 4245 gcc_unreachable (); 4246 goto end; 4247 } 4248 } 4249 else if (count == 15) 4250 { 4251 switch (shift_type) 4252 { 4253 case SHIFT_ASHIFT: 4254 info->special = "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0"; 4255 goto end; 4256 case SHIFT_LSHIFTRT: 4257 info->special = "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0"; 4258 goto end; 4259 case SHIFT_ASHIFTRT: 4260 info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0"; 4261 goto end; 4262 } 4263 } 4264 gcc_unreachable (); 4265 4266 case SIshift: 4267 if (TARGET_H8300 && 8 <= count && count <= 9) 4268 { 4269 info->remainder = count - 8; 4270 4271 switch (shift_type) 4272 { 4273 case SHIFT_ASHIFT: 4274 info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0"; 4275 goto end; 4276 case SHIFT_LSHIFTRT: 4277 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0"; 4278 info->shift1 = "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0"; 4279 goto end; 4280 case SHIFT_ASHIFTRT: 4281 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0"; 4282 goto end; 4283 } 4284 } 4285 else if (count == 8 && !TARGET_H8300) 4286 { 4287 switch (shift_type) 4288 { 4289 case SHIFT_ASHIFT: 4290 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0"; 4291 goto end; 4292 case SHIFT_LSHIFTRT: 4293 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0"; 4294 goto end; 4295 case SHIFT_ASHIFTRT: 4296 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0"; 4297 goto end; 4298 } 4299 } 4300 else if (count == 15 && TARGET_H8300) 4301 { 4302 switch (shift_type) 4303 { 4304 case SHIFT_ASHIFT: 4305 gcc_unreachable (); 4306 case SHIFT_LSHIFTRT: 4307 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0"; 4308 goto end; 4309 case SHIFT_ASHIFTRT: 4310 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0"; 4311 goto end; 4312 } 4313 } 4314 else if (count == 15 && !TARGET_H8300) 4315 { 4316 switch (shift_type) 4317 { 4318 case SHIFT_ASHIFT: 4319 info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0"; 4320 info->cc_special = CC_SET_ZNV; 4321 goto end; 4322 case SHIFT_LSHIFTRT: 4323 info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0"; 4324 info->cc_special = CC_SET_ZNV; 4325 goto end; 4326 case SHIFT_ASHIFTRT: 4327 gcc_unreachable (); 4328 } 4329 } 4330 else if ((TARGET_H8300 && 16 <= count && count <= 20) 4331 || (TARGET_H8300H && 16 <= count && count <= 19) 4332 || (TARGET_H8300S && 16 <= count && count <= 21)) 4333 { 4334 info->remainder = count - 16; 4335 4336 switch (shift_type) 4337 { 4338 case SHIFT_ASHIFT: 4339 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0"; 4340 if (TARGET_H8300) 4341 info->shift1 = "add.w\t%e0,%e0"; 4342 goto end; 4343 case SHIFT_LSHIFTRT: 4344 if (TARGET_H8300) 4345 { 4346 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0"; 4347 info->shift1 = "shlr\t%x0\n\trotxr\t%w0"; 4348 } 4349 else 4350 { 4351 info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0"; 4352 info->cc_special = CC_SET_ZNV; 4353 } 4354 goto end; 4355 case SHIFT_ASHIFTRT: 4356 if (TARGET_H8300) 4357 { 4358 info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0"; 4359 info->shift1 = "shar\t%x0\n\trotxr\t%w0"; 4360 } 4361 else 4362 { 4363 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0"; 4364 info->cc_special = CC_SET_ZNV; 4365 } 4366 goto end; 4367 } 4368 } 4369 else if (TARGET_H8300 && 24 <= count && count <= 28) 4370 { 4371 info->remainder = count - 24; 4372 4373 switch (shift_type) 4374 { 4375 case SHIFT_ASHIFT: 4376 info->special = "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0"; 4377 info->shift1 = "shll.b\t%z0"; 4378 info->cc_inline = CC_SET_ZNV; 4379 goto end; 4380 case SHIFT_LSHIFTRT: 4381 info->special = "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0"; 4382 info->shift1 = "shlr.b\t%w0"; 4383 info->cc_inline = CC_SET_ZNV; 4384 goto end; 4385 case SHIFT_ASHIFTRT: 4386 info->special = "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0"; 4387 info->shift1 = "shar.b\t%w0"; 4388 info->cc_inline = CC_SET_ZNV; 4389 goto end; 4390 } 4391 } 4392 else if ((TARGET_H8300H && count == 24) 4393 || (TARGET_H8300S && 24 <= count && count <= 25)) 4394 { 4395 info->remainder = count - 24; 4396 4397 switch (shift_type) 4398 { 4399 case SHIFT_ASHIFT: 4400 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0"; 4401 goto end; 4402 case SHIFT_LSHIFTRT: 4403 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0"; 4404 info->cc_special = CC_SET_ZNV; 4405 goto end; 4406 case SHIFT_ASHIFTRT: 4407 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0"; 4408 info->cc_special = CC_SET_ZNV; 4409 goto end; 4410 } 4411 } 4412 else if (!TARGET_H8300 && count == 28) 4413 { 4414 switch (shift_type) 4415 { 4416 case SHIFT_ASHIFT: 4417 if (TARGET_H8300H) 4418 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0"; 4419 else 4420 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0"; 4421 goto end; 4422 case SHIFT_LSHIFTRT: 4423 if (TARGET_H8300H) 4424 { 4425 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0"; 4426 info->cc_special = CC_SET_ZNV; 4427 } 4428 else 4429 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0"; 4430 goto end; 4431 case SHIFT_ASHIFTRT: 4432 gcc_unreachable (); 4433 } 4434 } 4435 else if (!TARGET_H8300 && count == 29) 4436 { 4437 switch (shift_type) 4438 { 4439 case SHIFT_ASHIFT: 4440 if (TARGET_H8300H) 4441 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0"; 4442 else 4443 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0"; 4444 goto end; 4445 case SHIFT_LSHIFTRT: 4446 if (TARGET_H8300H) 4447 { 4448 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0"; 4449 info->cc_special = CC_SET_ZNV; 4450 } 4451 else 4452 { 4453 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0"; 4454 info->cc_special = CC_SET_ZNV; 4455 } 4456 goto end; 4457 case SHIFT_ASHIFTRT: 4458 gcc_unreachable (); 4459 } 4460 } 4461 else if (!TARGET_H8300 && count == 30) 4462 { 4463 switch (shift_type) 4464 { 4465 case SHIFT_ASHIFT: 4466 if (TARGET_H8300H) 4467 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0"; 4468 else 4469 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0"; 4470 goto end; 4471 case SHIFT_LSHIFTRT: 4472 if (TARGET_H8300H) 4473 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0"; 4474 else 4475 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0"; 4476 goto end; 4477 case SHIFT_ASHIFTRT: 4478 gcc_unreachable (); 4479 } 4480 } 4481 else if (count == 31) 4482 { 4483 if (TARGET_H8300) 4484 { 4485 switch (shift_type) 4486 { 4487 case SHIFT_ASHIFT: 4488 info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0"; 4489 goto end; 4490 case SHIFT_LSHIFTRT: 4491 info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0"; 4492 goto end; 4493 case SHIFT_ASHIFTRT: 4494 info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0"; 4495 goto end; 4496 } 4497 } 4498 else 4499 { 4500 switch (shift_type) 4501 { 4502 case SHIFT_ASHIFT: 4503 info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0"; 4504 info->cc_special = CC_SET_ZNV; 4505 goto end; 4506 case SHIFT_LSHIFTRT: 4507 info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0"; 4508 info->cc_special = CC_SET_ZNV; 4509 goto end; 4510 case SHIFT_ASHIFTRT: 4511 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0"; 4512 info->cc_special = CC_SET_ZNV; 4513 goto end; 4514 } 4515 } 4516 } 4517 gcc_unreachable (); 4518 4519 default: 4520 gcc_unreachable (); 4521 } 4522 4523 end: 4524 if (!TARGET_H8300S) 4525 info->shift2 = NULL; 4526} 4527 4528/* Given COUNT and MODE of a shift, return 1 if a scratch reg may be 4529 needed for some shift with COUNT and MODE. Return 0 otherwise. */ 4530 4531int 4532h8300_shift_needs_scratch_p (int count, machine_mode mode) 4533{ 4534 enum h8_cpu cpu; 4535 int a, lr, ar; 4536 4537 if (GET_MODE_BITSIZE (mode) <= count) 4538 return 1; 4539 4540 /* Find out the target CPU. */ 4541 if (TARGET_H8300) 4542 cpu = H8_300; 4543 else if (TARGET_H8300H) 4544 cpu = H8_300H; 4545 else 4546 cpu = H8_S; 4547 4548 /* Find the shift algorithm. */ 4549 switch (mode) 4550 { 4551 case QImode: 4552 a = shift_alg_qi[cpu][SHIFT_ASHIFT][count]; 4553 lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count]; 4554 ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count]; 4555 break; 4556 4557 case HImode: 4558 a = shift_alg_hi[cpu][SHIFT_ASHIFT][count]; 4559 lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count]; 4560 ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count]; 4561 break; 4562 4563 case SImode: 4564 a = shift_alg_si[cpu][SHIFT_ASHIFT][count]; 4565 lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count]; 4566 ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count]; 4567 break; 4568 4569 default: 4570 gcc_unreachable (); 4571 } 4572 4573 /* On H8/300H, count == 8 uses a scratch register. */ 4574 return (a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP 4575 || (TARGET_H8300H && mode == SImode && count == 8)); 4576} 4577 4578/* Output the assembler code for doing shifts. */ 4579 4580const char * 4581output_a_shift (rtx *operands) 4582{ 4583 static int loopend_lab; 4584 rtx shift = operands[3]; 4585 machine_mode mode = GET_MODE (shift); 4586 enum rtx_code code = GET_CODE (shift); 4587 enum shift_type shift_type; 4588 enum shift_mode shift_mode; 4589 struct shift_info info; 4590 int n; 4591 4592 loopend_lab++; 4593 4594 switch (mode) 4595 { 4596 case QImode: 4597 shift_mode = QIshift; 4598 break; 4599 case HImode: 4600 shift_mode = HIshift; 4601 break; 4602 case SImode: 4603 shift_mode = SIshift; 4604 break; 4605 default: 4606 gcc_unreachable (); 4607 } 4608 4609 switch (code) 4610 { 4611 case ASHIFTRT: 4612 shift_type = SHIFT_ASHIFTRT; 4613 break; 4614 case LSHIFTRT: 4615 shift_type = SHIFT_LSHIFTRT; 4616 break; 4617 case ASHIFT: 4618 shift_type = SHIFT_ASHIFT; 4619 break; 4620 default: 4621 gcc_unreachable (); 4622 } 4623 4624 /* This case must be taken care of by one of the two splitters 4625 that convert a variable shift into a loop. */ 4626 gcc_assert (GET_CODE (operands[2]) == CONST_INT); 4627 4628 n = INTVAL (operands[2]); 4629 4630 /* If the count is negative, make it 0. */ 4631 if (n < 0) 4632 n = 0; 4633 /* If the count is too big, truncate it. 4634 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to 4635 do the intuitive thing. */ 4636 else if ((unsigned int) n > GET_MODE_BITSIZE (mode)) 4637 n = GET_MODE_BITSIZE (mode); 4638 4639 get_shift_alg (shift_type, shift_mode, n, &info); 4640 4641 switch (info.alg) 4642 { 4643 case SHIFT_SPECIAL: 4644 output_asm_insn (info.special, operands); 4645 /* Fall through. */ 4646 4647 case SHIFT_INLINE: 4648 n = info.remainder; 4649 4650 /* Emit two bit shifts first. */ 4651 if (info.shift2 != NULL) 4652 { 4653 for (; n > 1; n -= 2) 4654 output_asm_insn (info.shift2, operands); 4655 } 4656 4657 /* Now emit one bit shifts for any residual. */ 4658 for (; n > 0; n--) 4659 output_asm_insn (info.shift1, operands); 4660 return ""; 4661 4662 case SHIFT_ROT_AND: 4663 { 4664 int m = GET_MODE_BITSIZE (mode) - n; 4665 const int mask = (shift_type == SHIFT_ASHIFT 4666 ? ((1 << m) - 1) << n 4667 : (1 << m) - 1); 4668 char insn_buf[200]; 4669 4670 /* Not all possibilities of rotate are supported. They shouldn't 4671 be generated, but let's watch for 'em. */ 4672 gcc_assert (info.shift1); 4673 4674 /* Emit two bit rotates first. */ 4675 if (info.shift2 != NULL) 4676 { 4677 for (; m > 1; m -= 2) 4678 output_asm_insn (info.shift2, operands); 4679 } 4680 4681 /* Now single bit rotates for any residual. */ 4682 for (; m > 0; m--) 4683 output_asm_insn (info.shift1, operands); 4684 4685 /* Now mask off the high bits. */ 4686 switch (mode) 4687 { 4688 case QImode: 4689 sprintf (insn_buf, "and\t#%d,%%X0", mask); 4690 break; 4691 4692 case HImode: 4693 gcc_assert (TARGET_H8300H || TARGET_H8300S); 4694 sprintf (insn_buf, "and.w\t#%d,%%T0", mask); 4695 break; 4696 4697 default: 4698 gcc_unreachable (); 4699 } 4700 4701 output_asm_insn (insn_buf, operands); 4702 return ""; 4703 } 4704 4705 case SHIFT_LOOP: 4706 /* A loop to shift by a "large" constant value. 4707 If we have shift-by-2 insns, use them. */ 4708 if (info.shift2 != NULL) 4709 { 4710 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2, 4711 names_big[REGNO (operands[4])]); 4712 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab); 4713 output_asm_insn (info.shift2, operands); 4714 output_asm_insn ("add #0xff,%X4", operands); 4715 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab); 4716 if (n % 2) 4717 output_asm_insn (info.shift1, operands); 4718 } 4719 else 4720 { 4721 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n, 4722 names_big[REGNO (operands[4])]); 4723 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab); 4724 output_asm_insn (info.shift1, operands); 4725 output_asm_insn ("add #0xff,%X4", operands); 4726 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab); 4727 } 4728 return ""; 4729 4730 default: 4731 gcc_unreachable (); 4732 } 4733} 4734 4735/* Count the number of assembly instructions in a string TEMPL. */ 4736 4737static unsigned int 4738h8300_asm_insn_count (const char *templ) 4739{ 4740 unsigned int count = 1; 4741 4742 for (; *templ; templ++) 4743 if (*templ == '\n') 4744 count++; 4745 4746 return count; 4747} 4748 4749/* Compute the length of a shift insn. */ 4750 4751unsigned int 4752compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED, rtx *operands) 4753{ 4754 rtx shift = operands[3]; 4755 machine_mode mode = GET_MODE (shift); 4756 enum rtx_code code = GET_CODE (shift); 4757 enum shift_type shift_type; 4758 enum shift_mode shift_mode; 4759 struct shift_info info; 4760 unsigned int wlength = 0; 4761 4762 switch (mode) 4763 { 4764 case QImode: 4765 shift_mode = QIshift; 4766 break; 4767 case HImode: 4768 shift_mode = HIshift; 4769 break; 4770 case SImode: 4771 shift_mode = SIshift; 4772 break; 4773 default: 4774 gcc_unreachable (); 4775 } 4776 4777 switch (code) 4778 { 4779 case ASHIFTRT: 4780 shift_type = SHIFT_ASHIFTRT; 4781 break; 4782 case LSHIFTRT: 4783 shift_type = SHIFT_LSHIFTRT; 4784 break; 4785 case ASHIFT: 4786 shift_type = SHIFT_ASHIFT; 4787 break; 4788 default: 4789 gcc_unreachable (); 4790 } 4791 4792 if (GET_CODE (operands[2]) != CONST_INT) 4793 { 4794 /* Get the assembler code to do one shift. */ 4795 get_shift_alg (shift_type, shift_mode, 1, &info); 4796 4797 return (4 + h8300_asm_insn_count (info.shift1)) * 2; 4798 } 4799 else 4800 { 4801 int n = INTVAL (operands[2]); 4802 4803 /* If the count is negative, make it 0. */ 4804 if (n < 0) 4805 n = 0; 4806 /* If the count is too big, truncate it. 4807 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to 4808 do the intuitive thing. */ 4809 else if ((unsigned int) n > GET_MODE_BITSIZE (mode)) 4810 n = GET_MODE_BITSIZE (mode); 4811 4812 get_shift_alg (shift_type, shift_mode, n, &info); 4813 4814 switch (info.alg) 4815 { 4816 case SHIFT_SPECIAL: 4817 wlength += h8300_asm_insn_count (info.special); 4818 4819 /* Every assembly instruction used in SHIFT_SPECIAL case 4820 takes 2 bytes except xor.l, which takes 4 bytes, so if we 4821 see xor.l, we just pretend that xor.l counts as two insns 4822 so that the insn length will be computed correctly. */ 4823 if (strstr (info.special, "xor.l") != NULL) 4824 wlength++; 4825 4826 /* Fall through. */ 4827 4828 case SHIFT_INLINE: 4829 n = info.remainder; 4830 4831 if (info.shift2 != NULL) 4832 { 4833 wlength += h8300_asm_insn_count (info.shift2) * (n / 2); 4834 n = n % 2; 4835 } 4836 4837 wlength += h8300_asm_insn_count (info.shift1) * n; 4838 4839 return 2 * wlength; 4840 4841 case SHIFT_ROT_AND: 4842 { 4843 int m = GET_MODE_BITSIZE (mode) - n; 4844 4845 /* Not all possibilities of rotate are supported. They shouldn't 4846 be generated, but let's watch for 'em. */ 4847 gcc_assert (info.shift1); 4848 4849 if (info.shift2 != NULL) 4850 { 4851 wlength += h8300_asm_insn_count (info.shift2) * (m / 2); 4852 m = m % 2; 4853 } 4854 4855 wlength += h8300_asm_insn_count (info.shift1) * m; 4856 4857 /* Now mask off the high bits. */ 4858 switch (mode) 4859 { 4860 case QImode: 4861 wlength += 1; 4862 break; 4863 case HImode: 4864 wlength += 2; 4865 break; 4866 case SImode: 4867 gcc_assert (!TARGET_H8300); 4868 wlength += 3; 4869 break; 4870 default: 4871 gcc_unreachable (); 4872 } 4873 return 2 * wlength; 4874 } 4875 4876 case SHIFT_LOOP: 4877 /* A loop to shift by a "large" constant value. 4878 If we have shift-by-2 insns, use them. */ 4879 if (info.shift2 != NULL) 4880 { 4881 wlength += 3 + h8300_asm_insn_count (info.shift2); 4882 if (n % 2) 4883 wlength += h8300_asm_insn_count (info.shift1); 4884 } 4885 else 4886 { 4887 wlength += 3 + h8300_asm_insn_count (info.shift1); 4888 } 4889 return 2 * wlength; 4890 4891 default: 4892 gcc_unreachable (); 4893 } 4894 } 4895} 4896 4897/* Compute which flag bits are valid after a shift insn. */ 4898 4899enum attr_cc 4900compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED, rtx *operands) 4901{ 4902 rtx shift = operands[3]; 4903 machine_mode mode = GET_MODE (shift); 4904 enum rtx_code code = GET_CODE (shift); 4905 enum shift_type shift_type; 4906 enum shift_mode shift_mode; 4907 struct shift_info info; 4908 int n; 4909 4910 switch (mode) 4911 { 4912 case QImode: 4913 shift_mode = QIshift; 4914 break; 4915 case HImode: 4916 shift_mode = HIshift; 4917 break; 4918 case SImode: 4919 shift_mode = SIshift; 4920 break; 4921 default: 4922 gcc_unreachable (); 4923 } 4924 4925 switch (code) 4926 { 4927 case ASHIFTRT: 4928 shift_type = SHIFT_ASHIFTRT; 4929 break; 4930 case LSHIFTRT: 4931 shift_type = SHIFT_LSHIFTRT; 4932 break; 4933 case ASHIFT: 4934 shift_type = SHIFT_ASHIFT; 4935 break; 4936 default: 4937 gcc_unreachable (); 4938 } 4939 4940 /* This case must be taken care of by one of the two splitters 4941 that convert a variable shift into a loop. */ 4942 gcc_assert (GET_CODE (operands[2]) == CONST_INT); 4943 4944 n = INTVAL (operands[2]); 4945 4946 /* If the count is negative, make it 0. */ 4947 if (n < 0) 4948 n = 0; 4949 /* If the count is too big, truncate it. 4950 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to 4951 do the intuitive thing. */ 4952 else if ((unsigned int) n > GET_MODE_BITSIZE (mode)) 4953 n = GET_MODE_BITSIZE (mode); 4954 4955 get_shift_alg (shift_type, shift_mode, n, &info); 4956 4957 switch (info.alg) 4958 { 4959 case SHIFT_SPECIAL: 4960 if (info.remainder == 0) 4961 return info.cc_special; 4962 4963 /* Fall through. */ 4964 4965 case SHIFT_INLINE: 4966 return info.cc_inline; 4967 4968 case SHIFT_ROT_AND: 4969 /* This case always ends with an and instruction. */ 4970 return CC_SET_ZNV; 4971 4972 case SHIFT_LOOP: 4973 /* A loop to shift by a "large" constant value. 4974 If we have shift-by-2 insns, use them. */ 4975 if (info.shift2 != NULL) 4976 { 4977 if (n % 2) 4978 return info.cc_inline; 4979 } 4980 return CC_CLOBBER; 4981 4982 default: 4983 gcc_unreachable (); 4984 } 4985} 4986 4987/* A rotation by a non-constant will cause a loop to be generated, in 4988 which a rotation by one bit is used. A rotation by a constant, 4989 including the one in the loop, will be taken care of by 4990 output_a_rotate () at the insn emit time. */ 4991 4992int 4993expand_a_rotate (rtx operands[]) 4994{ 4995 rtx dst = operands[0]; 4996 rtx src = operands[1]; 4997 rtx rotate_amount = operands[2]; 4998 machine_mode mode = GET_MODE (dst); 4999 5000 if (h8sx_classify_shift (mode, ROTATE, rotate_amount) == H8SX_SHIFT_UNARY) 5001 return false; 5002 5003 /* We rotate in place. */ 5004 emit_move_insn (dst, src); 5005 5006 if (GET_CODE (rotate_amount) != CONST_INT) 5007 { 5008 rtx counter = gen_reg_rtx (QImode); 5009 rtx_code_label *start_label = gen_label_rtx (); 5010 rtx_code_label *end_label = gen_label_rtx (); 5011 5012 /* If the rotate amount is less than or equal to 0, 5013 we go out of the loop. */ 5014 emit_cmp_and_jump_insns (rotate_amount, const0_rtx, LE, NULL_RTX, 5015 QImode, 0, end_label); 5016 5017 /* Initialize the loop counter. */ 5018 emit_move_insn (counter, rotate_amount); 5019 5020 emit_label (start_label); 5021 5022 /* Rotate by one bit. */ 5023 switch (mode) 5024 { 5025 case QImode: 5026 emit_insn (gen_rotlqi3_1 (dst, dst, const1_rtx)); 5027 break; 5028 case HImode: 5029 emit_insn (gen_rotlhi3_1 (dst, dst, const1_rtx)); 5030 break; 5031 case SImode: 5032 emit_insn (gen_rotlsi3_1 (dst, dst, const1_rtx)); 5033 break; 5034 default: 5035 gcc_unreachable (); 5036 } 5037 5038 /* Decrement the counter by 1. */ 5039 emit_insn (gen_addqi3 (counter, counter, constm1_rtx)); 5040 5041 /* If the loop counter is nonzero, we go back to the beginning 5042 of the loop. */ 5043 emit_cmp_and_jump_insns (counter, const0_rtx, NE, NULL_RTX, QImode, 1, 5044 start_label); 5045 5046 emit_label (end_label); 5047 } 5048 else 5049 { 5050 /* Rotate by AMOUNT bits. */ 5051 switch (mode) 5052 { 5053 case QImode: 5054 emit_insn (gen_rotlqi3_1 (dst, dst, rotate_amount)); 5055 break; 5056 case HImode: 5057 emit_insn (gen_rotlhi3_1 (dst, dst, rotate_amount)); 5058 break; 5059 case SImode: 5060 emit_insn (gen_rotlsi3_1 (dst, dst, rotate_amount)); 5061 break; 5062 default: 5063 gcc_unreachable (); 5064 } 5065 } 5066 5067 return 1; 5068} 5069 5070/* Output a rotate insn. */ 5071 5072const char * 5073output_a_rotate (enum rtx_code code, rtx *operands) 5074{ 5075 rtx dst = operands[0]; 5076 rtx rotate_amount = operands[2]; 5077 enum shift_mode rotate_mode; 5078 enum shift_type rotate_type; 5079 const char *insn_buf; 5080 int bits; 5081 int amount; 5082 machine_mode mode = GET_MODE (dst); 5083 5084 gcc_assert (GET_CODE (rotate_amount) == CONST_INT); 5085 5086 switch (mode) 5087 { 5088 case QImode: 5089 rotate_mode = QIshift; 5090 break; 5091 case HImode: 5092 rotate_mode = HIshift; 5093 break; 5094 case SImode: 5095 rotate_mode = SIshift; 5096 break; 5097 default: 5098 gcc_unreachable (); 5099 } 5100 5101 switch (code) 5102 { 5103 case ROTATERT: 5104 rotate_type = SHIFT_ASHIFT; 5105 break; 5106 case ROTATE: 5107 rotate_type = SHIFT_LSHIFTRT; 5108 break; 5109 default: 5110 gcc_unreachable (); 5111 } 5112 5113 amount = INTVAL (rotate_amount); 5114 5115 /* Clean up AMOUNT. */ 5116 if (amount < 0) 5117 amount = 0; 5118 if ((unsigned int) amount > GET_MODE_BITSIZE (mode)) 5119 amount = GET_MODE_BITSIZE (mode); 5120 5121 /* Determine the faster direction. After this phase, amount will be 5122 at most a half of GET_MODE_BITSIZE (mode). */ 5123 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2) 5124 { 5125 /* Flip the direction. */ 5126 amount = GET_MODE_BITSIZE (mode) - amount; 5127 rotate_type = 5128 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT; 5129 } 5130 5131 /* See if a byte swap (in HImode) or a word swap (in SImode) can 5132 boost up the rotation. */ 5133 if ((mode == HImode && TARGET_H8300 && amount >= 5) 5134 || (mode == HImode && TARGET_H8300H && amount >= 6) 5135 || (mode == HImode && TARGET_H8300S && amount == 8) 5136 || (mode == SImode && TARGET_H8300H && amount >= 10) 5137 || (mode == SImode && TARGET_H8300S && amount >= 13)) 5138 { 5139 switch (mode) 5140 { 5141 case HImode: 5142 /* This code works on any family. */ 5143 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0"; 5144 output_asm_insn (insn_buf, operands); 5145 break; 5146 5147 case SImode: 5148 /* This code works on the H8/300H and H8S. */ 5149 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0"; 5150 output_asm_insn (insn_buf, operands); 5151 break; 5152 5153 default: 5154 gcc_unreachable (); 5155 } 5156 5157 /* Adjust AMOUNT and flip the direction. */ 5158 amount = GET_MODE_BITSIZE (mode) / 2 - amount; 5159 rotate_type = 5160 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT; 5161 } 5162 5163 /* Output rotate insns. */ 5164 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2) 5165 { 5166 if (bits == 2) 5167 insn_buf = rotate_two[rotate_type][rotate_mode]; 5168 else 5169 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode]; 5170 5171 for (; amount >= bits; amount -= bits) 5172 output_asm_insn (insn_buf, operands); 5173 } 5174 5175 return ""; 5176} 5177 5178/* Compute the length of a rotate insn. */ 5179 5180unsigned int 5181compute_a_rotate_length (rtx *operands) 5182{ 5183 rtx src = operands[1]; 5184 rtx amount_rtx = operands[2]; 5185 machine_mode mode = GET_MODE (src); 5186 int amount; 5187 unsigned int length = 0; 5188 5189 gcc_assert (GET_CODE (amount_rtx) == CONST_INT); 5190 5191 amount = INTVAL (amount_rtx); 5192 5193 /* Clean up AMOUNT. */ 5194 if (amount < 0) 5195 amount = 0; 5196 if ((unsigned int) amount > GET_MODE_BITSIZE (mode)) 5197 amount = GET_MODE_BITSIZE (mode); 5198 5199 /* Determine the faster direction. After this phase, amount 5200 will be at most a half of GET_MODE_BITSIZE (mode). */ 5201 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2) 5202 /* Flip the direction. */ 5203 amount = GET_MODE_BITSIZE (mode) - amount; 5204 5205 /* See if a byte swap (in HImode) or a word swap (in SImode) can 5206 boost up the rotation. */ 5207 if ((mode == HImode && TARGET_H8300 && amount >= 5) 5208 || (mode == HImode && TARGET_H8300H && amount >= 6) 5209 || (mode == HImode && TARGET_H8300S && amount == 8) 5210 || (mode == SImode && TARGET_H8300H && amount >= 10) 5211 || (mode == SImode && TARGET_H8300S && amount >= 13)) 5212 { 5213 /* Adjust AMOUNT and flip the direction. */ 5214 amount = GET_MODE_BITSIZE (mode) / 2 - amount; 5215 length += 6; 5216 } 5217 5218 /* We use 2-bit rotations on the H8S. */ 5219 if (TARGET_H8300S) 5220 amount = amount / 2 + amount % 2; 5221 5222 /* The H8/300 uses three insns to rotate one bit, taking 6 5223 length. */ 5224 length += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2); 5225 5226 return length; 5227} 5228 5229/* Fix the operands of a gen_xxx so that it could become a bit 5230 operating insn. */ 5231 5232int 5233fix_bit_operand (rtx *operands, enum rtx_code code) 5234{ 5235 /* The bit_operand predicate accepts any memory during RTL generation, but 5236 only 'U' memory afterwards, so if this is a MEM operand, we must force 5237 it to be valid for 'U' by reloading the address. */ 5238 5239 if (code == AND 5240 ? single_zero_operand (operands[2], QImode) 5241 : single_one_operand (operands[2], QImode)) 5242 { 5243 /* OK to have a memory dest. */ 5244 if (GET_CODE (operands[0]) == MEM 5245 && !satisfies_constraint_U (operands[0])) 5246 { 5247 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]), 5248 copy_to_mode_reg (Pmode, 5249 XEXP (operands[0], 0))); 5250 MEM_COPY_ATTRIBUTES (mem, operands[0]); 5251 operands[0] = mem; 5252 } 5253 5254 if (GET_CODE (operands[1]) == MEM 5255 && !satisfies_constraint_U (operands[1])) 5256 { 5257 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]), 5258 copy_to_mode_reg (Pmode, 5259 XEXP (operands[1], 0))); 5260 MEM_COPY_ATTRIBUTES (mem, operands[0]); 5261 operands[1] = mem; 5262 } 5263 return 0; 5264 } 5265 5266 /* Dest and src op must be register. */ 5267 5268 operands[1] = force_reg (QImode, operands[1]); 5269 { 5270 rtx res = gen_reg_rtx (QImode); 5271 switch (code) 5272 { 5273 case AND: 5274 emit_insn (gen_andqi3_1 (res, operands[1], operands[2])); 5275 break; 5276 case IOR: 5277 emit_insn (gen_iorqi3_1 (res, operands[1], operands[2])); 5278 break; 5279 case XOR: 5280 emit_insn (gen_xorqi3_1 (res, operands[1], operands[2])); 5281 break; 5282 default: 5283 gcc_unreachable (); 5284 } 5285 emit_insn (gen_movqi (operands[0], res)); 5286 } 5287 return 1; 5288} 5289 5290/* Return nonzero if FUNC is an interrupt function as specified 5291 by the "interrupt" attribute. */ 5292 5293static int 5294h8300_interrupt_function_p (tree func) 5295{ 5296 tree a; 5297 5298 if (TREE_CODE (func) != FUNCTION_DECL) 5299 return 0; 5300 5301 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func)); 5302 return a != NULL_TREE; 5303} 5304 5305/* Return nonzero if FUNC is a saveall function as specified by the 5306 "saveall" attribute. */ 5307 5308static int 5309h8300_saveall_function_p (tree func) 5310{ 5311 tree a; 5312 5313 if (TREE_CODE (func) != FUNCTION_DECL) 5314 return 0; 5315 5316 a = lookup_attribute ("saveall", DECL_ATTRIBUTES (func)); 5317 return a != NULL_TREE; 5318} 5319 5320/* Return nonzero if FUNC is an OS_Task function as specified 5321 by the "OS_Task" attribute. */ 5322 5323static int 5324h8300_os_task_function_p (tree func) 5325{ 5326 tree a; 5327 5328 if (TREE_CODE (func) != FUNCTION_DECL) 5329 return 0; 5330 5331 a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func)); 5332 return a != NULL_TREE; 5333} 5334 5335/* Return nonzero if FUNC is a monitor function as specified 5336 by the "monitor" attribute. */ 5337 5338static int 5339h8300_monitor_function_p (tree func) 5340{ 5341 tree a; 5342 5343 if (TREE_CODE (func) != FUNCTION_DECL) 5344 return 0; 5345 5346 a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func)); 5347 return a != NULL_TREE; 5348} 5349 5350/* Return nonzero if FUNC is a function that should be called 5351 through the function vector. */ 5352 5353int 5354h8300_funcvec_function_p (tree func) 5355{ 5356 tree a; 5357 5358 if (TREE_CODE (func) != FUNCTION_DECL) 5359 return 0; 5360 5361 a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func)); 5362 return a != NULL_TREE; 5363} 5364 5365/* Return nonzero if DECL is a variable that's in the eight bit 5366 data area. */ 5367 5368int 5369h8300_eightbit_data_p (tree decl) 5370{ 5371 tree a; 5372 5373 if (TREE_CODE (decl) != VAR_DECL) 5374 return 0; 5375 5376 a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl)); 5377 return a != NULL_TREE; 5378} 5379 5380/* Return nonzero if DECL is a variable that's in the tiny 5381 data area. */ 5382 5383int 5384h8300_tiny_data_p (tree decl) 5385{ 5386 tree a; 5387 5388 if (TREE_CODE (decl) != VAR_DECL) 5389 return 0; 5390 5391 a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl)); 5392 return a != NULL_TREE; 5393} 5394 5395/* Generate an 'interrupt_handler' attribute for decls. We convert 5396 all the pragmas to corresponding attributes. */ 5397 5398static void 5399h8300_insert_attributes (tree node, tree *attributes) 5400{ 5401 if (TREE_CODE (node) == FUNCTION_DECL) 5402 { 5403 if (pragma_interrupt) 5404 { 5405 pragma_interrupt = 0; 5406 5407 /* Add an 'interrupt_handler' attribute. */ 5408 *attributes = tree_cons (get_identifier ("interrupt_handler"), 5409 NULL, *attributes); 5410 } 5411 5412 if (pragma_saveall) 5413 { 5414 pragma_saveall = 0; 5415 5416 /* Add an 'saveall' attribute. */ 5417 *attributes = tree_cons (get_identifier ("saveall"), 5418 NULL, *attributes); 5419 } 5420 } 5421} 5422 5423/* Supported attributes: 5424 5425 interrupt_handler: output a prologue and epilogue suitable for an 5426 interrupt handler. 5427 5428 saveall: output a prologue and epilogue that saves and restores 5429 all registers except the stack pointer. 5430 5431 function_vector: This function should be called through the 5432 function vector. 5433 5434 eightbit_data: This variable lives in the 8-bit data area and can 5435 be referenced with 8-bit absolute memory addresses. 5436 5437 tiny_data: This variable lives in the tiny data area and can be 5438 referenced with 16-bit absolute memory references. */ 5439 5440static const struct attribute_spec h8300_attribute_table[] = 5441{ 5442 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler, 5443 affects_type_identity } */ 5444 { "interrupt_handler", 0, 0, true, false, false, 5445 h8300_handle_fndecl_attribute, false }, 5446 { "saveall", 0, 0, true, false, false, 5447 h8300_handle_fndecl_attribute, false }, 5448 { "OS_Task", 0, 0, true, false, false, 5449 h8300_handle_fndecl_attribute, false }, 5450 { "monitor", 0, 0, true, false, false, 5451 h8300_handle_fndecl_attribute, false }, 5452 { "function_vector", 0, 0, true, false, false, 5453 h8300_handle_fndecl_attribute, false }, 5454 { "eightbit_data", 0, 0, true, false, false, 5455 h8300_handle_eightbit_data_attribute, false }, 5456 { "tiny_data", 0, 0, true, false, false, 5457 h8300_handle_tiny_data_attribute, false }, 5458 { NULL, 0, 0, false, false, false, NULL, false } 5459}; 5460 5461 5462/* Handle an attribute requiring a FUNCTION_DECL; arguments as in 5463 struct attribute_spec.handler. */ 5464static tree 5465h8300_handle_fndecl_attribute (tree *node, tree name, 5466 tree args ATTRIBUTE_UNUSED, 5467 int flags ATTRIBUTE_UNUSED, 5468 bool *no_add_attrs) 5469{ 5470 if (TREE_CODE (*node) != FUNCTION_DECL) 5471 { 5472 warning (OPT_Wattributes, "%qE attribute only applies to functions", 5473 name); 5474 *no_add_attrs = true; 5475 } 5476 5477 return NULL_TREE; 5478} 5479 5480/* Handle an "eightbit_data" attribute; arguments as in 5481 struct attribute_spec.handler. */ 5482static tree 5483h8300_handle_eightbit_data_attribute (tree *node, tree name, 5484 tree args ATTRIBUTE_UNUSED, 5485 int flags ATTRIBUTE_UNUSED, 5486 bool *no_add_attrs) 5487{ 5488 tree decl = *node; 5489 5490 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl)) 5491 { 5492 set_decl_section_name (decl, ".eight"); 5493 } 5494 else 5495 { 5496 warning (OPT_Wattributes, "%qE attribute ignored", 5497 name); 5498 *no_add_attrs = true; 5499 } 5500 5501 return NULL_TREE; 5502} 5503 5504/* Handle an "tiny_data" attribute; arguments as in 5505 struct attribute_spec.handler. */ 5506static tree 5507h8300_handle_tiny_data_attribute (tree *node, tree name, 5508 tree args ATTRIBUTE_UNUSED, 5509 int flags ATTRIBUTE_UNUSED, 5510 bool *no_add_attrs) 5511{ 5512 tree decl = *node; 5513 5514 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl)) 5515 { 5516 set_decl_section_name (decl, ".tiny"); 5517 } 5518 else 5519 { 5520 warning (OPT_Wattributes, "%qE attribute ignored", 5521 name); 5522 *no_add_attrs = true; 5523 } 5524 5525 return NULL_TREE; 5526} 5527 5528/* Mark function vectors, and various small data objects. */ 5529 5530static void 5531h8300_encode_section_info (tree decl, rtx rtl, int first) 5532{ 5533 int extra_flags = 0; 5534 5535 default_encode_section_info (decl, rtl, first); 5536 5537 if (TREE_CODE (decl) == FUNCTION_DECL 5538 && h8300_funcvec_function_p (decl)) 5539 extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION; 5540 else if (TREE_CODE (decl) == VAR_DECL 5541 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))) 5542 { 5543 if (h8300_eightbit_data_p (decl)) 5544 extra_flags = SYMBOL_FLAG_EIGHTBIT_DATA; 5545 else if (first && h8300_tiny_data_p (decl)) 5546 extra_flags = SYMBOL_FLAG_TINY_DATA; 5547 } 5548 5549 if (extra_flags) 5550 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags; 5551} 5552 5553/* Output a single-bit extraction. */ 5554 5555const char * 5556output_simode_bld (int bild, rtx operands[]) 5557{ 5558 if (TARGET_H8300) 5559 { 5560 /* Clear the destination register. */ 5561 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands); 5562 5563 /* Now output the bit load or bit inverse load, and store it in 5564 the destination. */ 5565 if (bild) 5566 output_asm_insn ("bild\t%Z2,%Y1", operands); 5567 else 5568 output_asm_insn ("bld\t%Z2,%Y1", operands); 5569 5570 output_asm_insn ("bst\t#0,%w0", operands); 5571 } 5572 else 5573 { 5574 /* Determine if we can clear the destination first. */ 5575 int clear_first = (REG_P (operands[0]) && REG_P (operands[1]) 5576 && REGNO (operands[0]) != REGNO (operands[1])); 5577 5578 if (clear_first) 5579 output_asm_insn ("sub.l\t%S0,%S0", operands); 5580 5581 /* Output the bit load or bit inverse load. */ 5582 if (bild) 5583 output_asm_insn ("bild\t%Z2,%Y1", operands); 5584 else 5585 output_asm_insn ("bld\t%Z2,%Y1", operands); 5586 5587 if (!clear_first) 5588 output_asm_insn ("xor.l\t%S0,%S0", operands); 5589 5590 /* Perform the bit store. */ 5591 output_asm_insn ("rotxl.l\t%S0", operands); 5592 } 5593 5594 /* All done. */ 5595 return ""; 5596} 5597 5598/* Delayed-branch scheduling is more effective if we have some idea 5599 how long each instruction will be. Use a shorten_branches pass 5600 to get an initial estimate. */ 5601 5602static void 5603h8300_reorg (void) 5604{ 5605 if (flag_delayed_branch) 5606 shorten_branches (get_insns ()); 5607} 5608 5609#ifndef OBJECT_FORMAT_ELF 5610static void 5611h8300_asm_named_section (const char *name, unsigned int flags ATTRIBUTE_UNUSED, 5612 tree decl) 5613{ 5614 /* ??? Perhaps we should be using default_coff_asm_named_section. */ 5615 fprintf (asm_out_file, "\t.section %s\n", name); 5616} 5617#endif /* ! OBJECT_FORMAT_ELF */ 5618 5619/* Nonzero if X is a constant address suitable as an 8-bit absolute, 5620 which is a special case of the 'R' operand. */ 5621 5622int 5623h8300_eightbit_constant_address_p (rtx x) 5624{ 5625 /* The ranges of the 8-bit area. */ 5626 const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode); 5627 const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode); 5628 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode); 5629 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00ffffff, SImode); 5630 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0xffffff00, SImode); 5631 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0xffffffff, SImode); 5632 5633 unsigned HOST_WIDE_INT addr; 5634 5635 /* We accept symbols declared with eightbit_data. */ 5636 if (GET_CODE (x) == SYMBOL_REF) 5637 return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0; 5638 5639 if (GET_CODE (x) == CONST 5640 && GET_CODE (XEXP (x, 0)) == PLUS 5641 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF 5642 && (SYMBOL_REF_FLAGS (XEXP (XEXP (x, 0), 0)) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0) 5643 return 1; 5644 5645 if (GET_CODE (x) != CONST_INT) 5646 return 0; 5647 5648 addr = INTVAL (x); 5649 5650 return (0 5651 || ((TARGET_H8300 || TARGET_NORMAL_MODE) && IN_RANGE (addr, n1, n2)) 5652 || (TARGET_H8300H && IN_RANGE (addr, h1, h2)) 5653 || (TARGET_H8300S && IN_RANGE (addr, s1, s2))); 5654} 5655 5656/* Nonzero if X is a constant address suitable as an 16-bit absolute 5657 on H8/300H and H8S. */ 5658 5659int 5660h8300_tiny_constant_address_p (rtx x) 5661{ 5662 /* The ranges of the 16-bit area. */ 5663 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00000000, SImode); 5664 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00007fff, SImode); 5665 const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode (0x00ff8000, SImode); 5666 const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode (0x00ffffff, SImode); 5667 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0x00000000, SImode); 5668 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0x00007fff, SImode); 5669 const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode (0xffff8000, SImode); 5670 const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode (0xffffffff, SImode); 5671 5672 unsigned HOST_WIDE_INT addr; 5673 5674 switch (GET_CODE (x)) 5675 { 5676 case SYMBOL_REF: 5677 /* In the normal mode, any symbol fits in the 16-bit absolute 5678 address range. We also accept symbols declared with 5679 tiny_data. */ 5680 return (TARGET_NORMAL_MODE 5681 || (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_TINY_DATA) != 0); 5682 5683 case CONST_INT: 5684 addr = INTVAL (x); 5685 return (TARGET_NORMAL_MODE 5686 || (TARGET_H8300H 5687 && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4))) 5688 || (TARGET_H8300S 5689 && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4)))); 5690 5691 case CONST: 5692 return TARGET_NORMAL_MODE; 5693 5694 default: 5695 return 0; 5696 } 5697 5698} 5699 5700/* Return nonzero if ADDR1 and ADDR2 point to consecutive memory 5701 locations that can be accessed as a 16-bit word. */ 5702 5703int 5704byte_accesses_mergeable_p (rtx addr1, rtx addr2) 5705{ 5706 HOST_WIDE_INT offset1, offset2; 5707 rtx reg1, reg2; 5708 5709 if (REG_P (addr1)) 5710 { 5711 reg1 = addr1; 5712 offset1 = 0; 5713 } 5714 else if (GET_CODE (addr1) == PLUS 5715 && REG_P (XEXP (addr1, 0)) 5716 && GET_CODE (XEXP (addr1, 1)) == CONST_INT) 5717 { 5718 reg1 = XEXP (addr1, 0); 5719 offset1 = INTVAL (XEXP (addr1, 1)); 5720 } 5721 else 5722 return 0; 5723 5724 if (REG_P (addr2)) 5725 { 5726 reg2 = addr2; 5727 offset2 = 0; 5728 } 5729 else if (GET_CODE (addr2) == PLUS 5730 && REG_P (XEXP (addr2, 0)) 5731 && GET_CODE (XEXP (addr2, 1)) == CONST_INT) 5732 { 5733 reg2 = XEXP (addr2, 0); 5734 offset2 = INTVAL (XEXP (addr2, 1)); 5735 } 5736 else 5737 return 0; 5738 5739 if (((reg1 == stack_pointer_rtx && reg2 == stack_pointer_rtx) 5740 || (reg1 == frame_pointer_rtx && reg2 == frame_pointer_rtx)) 5741 && offset1 % 2 == 0 5742 && offset1 + 1 == offset2) 5743 return 1; 5744 5745 return 0; 5746} 5747 5748/* Return nonzero if we have the same comparison insn as I3 two insns 5749 before I3. I3 is assumed to be a comparison insn. */ 5750 5751int 5752same_cmp_preceding_p (rtx i3) 5753{ 5754 rtx_insn *i1, *i2; 5755 5756 /* Make sure we have a sequence of three insns. */ 5757 i2 = prev_nonnote_insn (i3); 5758 if (i2 == NULL) 5759 return 0; 5760 i1 = prev_nonnote_insn (i2); 5761 if (i1 == NULL) 5762 return 0; 5763 5764 return (INSN_P (i1) && rtx_equal_p (PATTERN (i1), PATTERN (i3)) 5765 && any_condjump_p (i2) && onlyjump_p (i2)); 5766} 5767 5768/* Return nonzero if we have the same comparison insn as I1 two insns 5769 after I1. I1 is assumed to be a comparison insn. */ 5770 5771int 5772same_cmp_following_p (rtx i1) 5773{ 5774 rtx_insn *i2, *i3; 5775 5776 /* Make sure we have a sequence of three insns. */ 5777 i2 = next_nonnote_insn (i1); 5778 if (i2 == NULL) 5779 return 0; 5780 i3 = next_nonnote_insn (i2); 5781 if (i3 == NULL) 5782 return 0; 5783 5784 return (INSN_P (i3) && rtx_equal_p (PATTERN (i1), PATTERN (i3)) 5785 && any_condjump_p (i2) && onlyjump_p (i2)); 5786} 5787 5788/* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes 5789 (or pops) N registers. OPERANDS are assumed to be an array of 5790 registers. */ 5791 5792int 5793h8300_regs_ok_for_stm (int n, rtx operands[]) 5794{ 5795 switch (n) 5796 { 5797 case 2: 5798 return ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1) 5799 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3) 5800 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5)); 5801 case 3: 5802 return ((REGNO (operands[0]) == 0 5803 && REGNO (operands[1]) == 1 5804 && REGNO (operands[2]) == 2) 5805 || (REGNO (operands[0]) == 4 5806 && REGNO (operands[1]) == 5 5807 && REGNO (operands[2]) == 6)); 5808 5809 case 4: 5810 return (REGNO (operands[0]) == 0 5811 && REGNO (operands[1]) == 1 5812 && REGNO (operands[2]) == 2 5813 && REGNO (operands[3]) == 3); 5814 default: 5815 gcc_unreachable (); 5816 } 5817} 5818 5819/* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */ 5820 5821int 5822h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED, 5823 unsigned int new_reg) 5824{ 5825 /* Interrupt functions can only use registers that have already been 5826 saved by the prologue, even if they would normally be 5827 call-clobbered. */ 5828 5829 if (h8300_current_function_interrupt_function_p () 5830 && !df_regs_ever_live_p (new_reg)) 5831 return 0; 5832 5833 return 1; 5834} 5835 5836/* Returns true if register REGNO is safe to be allocated as a scratch 5837 register in the current function. */ 5838 5839static bool 5840h8300_hard_regno_scratch_ok (unsigned int regno) 5841{ 5842 if (h8300_current_function_interrupt_function_p () 5843 && ! WORD_REG_USED (regno)) 5844 return false; 5845 5846 return true; 5847} 5848 5849 5850/* Return nonzero if X is a REG or SUBREG suitable as a base register. */ 5851 5852static int 5853h8300_rtx_ok_for_base_p (rtx x, int strict) 5854{ 5855 /* Strip off SUBREG if any. */ 5856 if (GET_CODE (x) == SUBREG) 5857 x = SUBREG_REG (x); 5858 5859 return (REG_P (x) 5860 && (strict 5861 ? REG_OK_FOR_BASE_STRICT_P (x) 5862 : REG_OK_FOR_BASE_NONSTRICT_P (x))); 5863} 5864 5865/* Return nozero if X is a legitimate address. On the H8/300, a 5866 legitimate address has the form REG, REG+CONSTANT_ADDRESS or 5867 CONSTANT_ADDRESS. */ 5868 5869static bool 5870h8300_legitimate_address_p (machine_mode mode, rtx x, bool strict) 5871{ 5872 /* The register indirect addresses like @er0 is always valid. */ 5873 if (h8300_rtx_ok_for_base_p (x, strict)) 5874 return 1; 5875 5876 if (CONSTANT_ADDRESS_P (x)) 5877 return 1; 5878 5879 if (TARGET_H8300SX 5880 && ( GET_CODE (x) == PRE_INC 5881 || GET_CODE (x) == PRE_DEC 5882 || GET_CODE (x) == POST_INC 5883 || GET_CODE (x) == POST_DEC) 5884 && h8300_rtx_ok_for_base_p (XEXP (x, 0), strict)) 5885 return 1; 5886 5887 if (GET_CODE (x) == PLUS 5888 && CONSTANT_ADDRESS_P (XEXP (x, 1)) 5889 && h8300_rtx_ok_for_base_p (h8300_get_index (XEXP (x, 0), 5890 mode, 0), strict)) 5891 return 1; 5892 5893 return 0; 5894} 5895 5896/* Worker function for HARD_REGNO_NREGS. 5897 5898 We pretend the MAC register is 32bits -- we don't have any data 5899 types on the H8 series to handle more than 32bits. */ 5900 5901int 5902h8300_hard_regno_nregs (int regno ATTRIBUTE_UNUSED, machine_mode mode) 5903{ 5904 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; 5905} 5906 5907/* Worker function for HARD_REGNO_MODE_OK. */ 5908 5909int 5910h8300_hard_regno_mode_ok (int regno, machine_mode mode) 5911{ 5912 if (TARGET_H8300) 5913 /* If an even reg, then anything goes. Otherwise the mode must be 5914 QI or HI. */ 5915 return ((regno & 1) == 0) || (mode == HImode) || (mode == QImode); 5916 else 5917 /* MAC register can only be of SImode. Otherwise, anything 5918 goes. */ 5919 return regno == MAC_REG ? mode == SImode : 1; 5920} 5921 5922/* Helper function for the move patterns. Make sure a move is legitimate. */ 5923 5924bool 5925h8300_move_ok (rtx dest, rtx src) 5926{ 5927 rtx addr, other; 5928 5929 /* Validate that at least one operand is a register. */ 5930 if (MEM_P (dest)) 5931 { 5932 if (MEM_P (src) || CONSTANT_P (src)) 5933 return false; 5934 addr = XEXP (dest, 0); 5935 other = src; 5936 } 5937 else if (MEM_P (src)) 5938 { 5939 addr = XEXP (src, 0); 5940 other = dest; 5941 } 5942 else 5943 return true; 5944 5945 /* Validate that auto-inc doesn't affect OTHER. */ 5946 if (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC) 5947 return true; 5948 addr = XEXP (addr, 0); 5949 5950 if (addr == stack_pointer_rtx) 5951 return register_no_sp_elim_operand (other, VOIDmode); 5952 else 5953 return !reg_overlap_mentioned_p(other, addr); 5954} 5955 5956/* Perform target dependent optabs initialization. */ 5957static void 5958h8300_init_libfuncs (void) 5959{ 5960 set_optab_libfunc (smul_optab, HImode, "__mulhi3"); 5961 set_optab_libfunc (sdiv_optab, HImode, "__divhi3"); 5962 set_optab_libfunc (udiv_optab, HImode, "__udivhi3"); 5963 set_optab_libfunc (smod_optab, HImode, "__modhi3"); 5964 set_optab_libfunc (umod_optab, HImode, "__umodhi3"); 5965} 5966 5967/* Worker function for TARGET_FUNCTION_VALUE. 5968 5969 On the H8 the return value is in R0/R1. */ 5970 5971static rtx 5972h8300_function_value (const_tree ret_type, 5973 const_tree fn_decl_or_type ATTRIBUTE_UNUSED, 5974 bool outgoing ATTRIBUTE_UNUSED) 5975{ 5976 return gen_rtx_REG (TYPE_MODE (ret_type), R0_REG); 5977} 5978 5979/* Worker function for TARGET_LIBCALL_VALUE. 5980 5981 On the H8 the return value is in R0/R1. */ 5982 5983static rtx 5984h8300_libcall_value (machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED) 5985{ 5986 return gen_rtx_REG (mode, R0_REG); 5987} 5988 5989/* Worker function for TARGET_FUNCTION_VALUE_REGNO_P. 5990 5991 On the H8, R0 is the only register thus used. */ 5992 5993static bool 5994h8300_function_value_regno_p (const unsigned int regno) 5995{ 5996 return (regno == R0_REG); 5997} 5998 5999/* Worker function for TARGET_RETURN_IN_MEMORY. */ 6000 6001static bool 6002h8300_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) 6003{ 6004 return (TYPE_MODE (type) == BLKmode 6005 || GET_MODE_SIZE (TYPE_MODE (type)) > (TARGET_H8300 ? 4 : 8)); 6006} 6007 6008/* We emit the entire trampoline here. Depending on the pointer size, 6009 we use a different trampoline. 6010 6011 Pmode == HImode 6012 vvvv context 6013 1 0000 7903xxxx mov.w #0x1234,r3 6014 2 0004 5A00xxxx jmp @0x1234 6015 ^^^^ function 6016 6017 Pmode == SImode 6018 vvvvvvvv context 6019 2 0000 7A03xxxxxxxx mov.l #0x12345678,er3 6020 3 0006 5Axxxxxx jmp @0x123456 6021 ^^^^^^ function 6022*/ 6023 6024static void 6025h8300_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt) 6026{ 6027 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0); 6028 rtx mem; 6029 6030 if (Pmode == HImode) 6031 { 6032 mem = adjust_address (m_tramp, HImode, 0); 6033 emit_move_insn (mem, GEN_INT (0x7903)); 6034 mem = adjust_address (m_tramp, Pmode, 2); 6035 emit_move_insn (mem, cxt); 6036 mem = adjust_address (m_tramp, HImode, 4); 6037 emit_move_insn (mem, GEN_INT (0x5a00)); 6038 mem = adjust_address (m_tramp, Pmode, 6); 6039 emit_move_insn (mem, fnaddr); 6040 } 6041 else 6042 { 6043 rtx tem; 6044 6045 mem = adjust_address (m_tramp, HImode, 0); 6046 emit_move_insn (mem, GEN_INT (0x7a03)); 6047 mem = adjust_address (m_tramp, Pmode, 2); 6048 emit_move_insn (mem, cxt); 6049 6050 tem = copy_to_reg (fnaddr); 6051 emit_insn (gen_andsi3 (tem, tem, GEN_INT (0x00ffffff))); 6052 emit_insn (gen_iorsi3 (tem, tem, GEN_INT (0x5a000000))); 6053 mem = adjust_address (m_tramp, SImode, 6); 6054 emit_move_insn (mem, tem); 6055 } 6056} 6057 6058/* Initialize the GCC target structure. */ 6059#undef TARGET_ATTRIBUTE_TABLE 6060#define TARGET_ATTRIBUTE_TABLE h8300_attribute_table 6061 6062#undef TARGET_ASM_ALIGNED_HI_OP 6063#define TARGET_ASM_ALIGNED_HI_OP "\t.word\t" 6064 6065#undef TARGET_ASM_FILE_START 6066#define TARGET_ASM_FILE_START h8300_file_start 6067#undef TARGET_ASM_FILE_START_FILE_DIRECTIVE 6068#define TARGET_ASM_FILE_START_FILE_DIRECTIVE true 6069 6070#undef TARGET_ASM_FILE_END 6071#define TARGET_ASM_FILE_END h8300_file_end 6072 6073#undef TARGET_PRINT_OPERAND 6074#define TARGET_PRINT_OPERAND h8300_print_operand 6075#undef TARGET_PRINT_OPERAND_ADDRESS 6076#define TARGET_PRINT_OPERAND_ADDRESS h8300_print_operand_address 6077#undef TARGET_PRINT_OPERAND_PUNCT_VALID_P 6078#define TARGET_PRINT_OPERAND_PUNCT_VALID_P h8300_print_operand_punct_valid_p 6079 6080#undef TARGET_ENCODE_SECTION_INFO 6081#define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info 6082 6083#undef TARGET_INSERT_ATTRIBUTES 6084#define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes 6085 6086#undef TARGET_REGISTER_MOVE_COST 6087#define TARGET_REGISTER_MOVE_COST h8300_register_move_cost 6088 6089#undef TARGET_RTX_COSTS 6090#define TARGET_RTX_COSTS h8300_rtx_costs 6091 6092#undef TARGET_INIT_LIBFUNCS 6093#define TARGET_INIT_LIBFUNCS h8300_init_libfuncs 6094 6095#undef TARGET_FUNCTION_VALUE 6096#define TARGET_FUNCTION_VALUE h8300_function_value 6097 6098#undef TARGET_LIBCALL_VALUE 6099#define TARGET_LIBCALL_VALUE h8300_libcall_value 6100 6101#undef TARGET_FUNCTION_VALUE_REGNO_P 6102#define TARGET_FUNCTION_VALUE_REGNO_P h8300_function_value_regno_p 6103 6104#undef TARGET_RETURN_IN_MEMORY 6105#define TARGET_RETURN_IN_MEMORY h8300_return_in_memory 6106 6107#undef TARGET_FUNCTION_ARG 6108#define TARGET_FUNCTION_ARG h8300_function_arg 6109 6110#undef TARGET_FUNCTION_ARG_ADVANCE 6111#define TARGET_FUNCTION_ARG_ADVANCE h8300_function_arg_advance 6112 6113#undef TARGET_MACHINE_DEPENDENT_REORG 6114#define TARGET_MACHINE_DEPENDENT_REORG h8300_reorg 6115 6116#undef TARGET_HARD_REGNO_SCRATCH_OK 6117#define TARGET_HARD_REGNO_SCRATCH_OK h8300_hard_regno_scratch_ok 6118 6119#undef TARGET_LEGITIMATE_ADDRESS_P 6120#define TARGET_LEGITIMATE_ADDRESS_P h8300_legitimate_address_p 6121 6122#undef TARGET_CAN_ELIMINATE 6123#define TARGET_CAN_ELIMINATE h8300_can_eliminate 6124 6125#undef TARGET_CONDITIONAL_REGISTER_USAGE 6126#define TARGET_CONDITIONAL_REGISTER_USAGE h8300_conditional_register_usage 6127 6128#undef TARGET_TRAMPOLINE_INIT 6129#define TARGET_TRAMPOLINE_INIT h8300_trampoline_init 6130 6131#undef TARGET_OPTION_OVERRIDE 6132#define TARGET_OPTION_OVERRIDE h8300_option_override 6133 6134#undef TARGET_MODE_DEPENDENT_ADDRESS_P 6135#define TARGET_MODE_DEPENDENT_ADDRESS_P h8300_mode_dependent_address_p 6136 6137struct gcc_target targetm = TARGET_INITIALIZER; 6138