1/* Instruction printing code for the ARM 2 Copyright (C) 1994-2017 Free Software Foundation, Inc. 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) 4 Modification by James G. Smith (jsmith@cygnus.co.uk) 5 6 This file is part of libopcodes. 7 8 This library is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the License, or 11 (at your option) any later version. 12 13 It is distributed in the hope that it will be useful, but WITHOUT 14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16 License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; if not, write to the Free Software 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 21 MA 02110-1301, USA. */ 22 23#include "sysdep.h" 24 25#include "dis-asm.h" 26#include "opcode/arm.h" 27#include "opintl.h" 28#include "safe-ctype.h" 29#include "floatformat.h" 30 31/* FIXME: This shouldn't be done here. */ 32#include "coff/internal.h" 33#include "libcoff.h" 34#include "elf-bfd.h" 35#include "elf/internal.h" 36#include "elf/arm.h" 37#include "mach-o.h" 38 39/* FIXME: Belongs in global header. */ 40#ifndef strneq 41#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0) 42#endif 43 44#ifndef NUM_ELEM 45#define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0]) 46#endif 47 48/* Cached mapping symbol state. */ 49enum map_type 50{ 51 MAP_ARM, 52 MAP_THUMB, 53 MAP_DATA 54}; 55 56struct arm_private_data 57{ 58 /* The features to use when disassembling optional instructions. */ 59 arm_feature_set features; 60 61 /* Whether any mapping symbols are present in the provided symbol 62 table. -1 if we do not know yet, otherwise 0 or 1. */ 63 int has_mapping_symbols; 64 65 /* Track the last type (although this doesn't seem to be useful) */ 66 enum map_type last_type; 67 68 /* Tracking symbol table information */ 69 int last_mapping_sym; 70 bfd_vma last_mapping_addr; 71}; 72 73struct opcode32 74{ 75 arm_feature_set arch; /* Architecture defining this insn. */ 76 unsigned long value; /* If arch is 0 then value is a sentinel. */ 77 unsigned long mask; /* Recognise insn if (op & mask) == value. */ 78 const char * assembler; /* How to disassemble this insn. */ 79}; 80 81struct opcode16 82{ 83 arm_feature_set arch; /* Architecture defining this insn. */ 84 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */ 85 const char *assembler; /* How to disassemble this insn. */ 86}; 87 88/* print_insn_coprocessor recognizes the following format control codes: 89 90 %% % 91 92 %c print condition code (always bits 28-31 in ARM mode) 93 %q print shifter argument 94 %u print condition code (unconditional in ARM mode, 95 UNPREDICTABLE if not AL in Thumb) 96 %A print address for ldc/stc/ldf/stf instruction 97 %B print vstm/vldm register list 98 %I print cirrus signed shift immediate: bits 0..3|4..6 99 %F print the COUNT field of a LFM/SFM instruction. 100 %P print floating point precision in arithmetic insn 101 %Q print floating point precision in ldf/stf insn 102 %R print floating point rounding mode 103 104 %<bitfield>c print as a condition code (for vsel) 105 %<bitfield>r print as an ARM register 106 %<bitfield>R as %<>r but r15 is UNPREDICTABLE 107 %<bitfield>ru as %<>r but each u register must be unique. 108 %<bitfield>d print the bitfield in decimal 109 %<bitfield>k print immediate for VFPv3 conversion instruction 110 %<bitfield>x print the bitfield in hex 111 %<bitfield>X print the bitfield as 1 hex digit without leading "0x" 112 %<bitfield>f print a floating point constant if >7 else a 113 floating point register 114 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us 115 %<bitfield>g print as an iWMMXt 64-bit register 116 %<bitfield>G print as an iWMMXt general purpose or control register 117 %<bitfield>D print as a NEON D register 118 %<bitfield>Q print as a NEON Q register 119 %<bitfield>V print as a NEON D or Q register 120 %<bitfield>E print a quarter-float immediate value 121 122 %y<code> print a single precision VFP reg. 123 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair 124 %z<code> print a double precision VFP reg 125 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list 126 127 %<bitfield>'c print specified char iff bitfield is all ones 128 %<bitfield>`c print specified char iff bitfield is all zeroes 129 %<bitfield>?ab... select from array of values in big endian order 130 131 %L print as an iWMMXt N/M width field. 132 %Z print the Immediate of a WSHUFH instruction. 133 %l like 'A' except use byte offsets for 'B' & 'H' 134 versions. 135 %i print 5-bit immediate in bits 8,3..0 136 (print "32" when 0) 137 %r print register offset address for wldt/wstr instruction. */ 138 139enum opcode_sentinel_enum 140{ 141 SENTINEL_IWMMXT_START = 1, 142 SENTINEL_IWMMXT_END, 143 SENTINEL_GENERIC_START 144} opcode_sentinels; 145 146#define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x" 147#define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>" 148 149/* Common coprocessor opcodes shared between Arm and Thumb-2. */ 150 151static const struct opcode32 coprocessor_opcodes[] = 152{ 153 /* XScale instructions. */ 154 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 155 0x0e200010, 0x0fff0ff0, 156 "mia%c\tacc0, %0-3r, %12-15r"}, 157 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 158 0x0e280010, 0x0fff0ff0, 159 "miaph%c\tacc0, %0-3r, %12-15r"}, 160 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 161 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"}, 162 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 163 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"}, 164 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 165 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"}, 166 167 /* Intel Wireless MMX technology instructions. */ 168 {ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" }, 169 {ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT), 170 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"}, 171 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 172 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"}, 173 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 174 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"}, 175 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 176 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"}, 177 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 178 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"}, 179 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 180 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"}, 181 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 182 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"}, 183 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 184 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"}, 185 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 186 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"}, 187 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 188 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"}, 189 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 190 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"}, 191 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 192 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"}, 193 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 194 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"}, 195 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 196 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"}, 197 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 198 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"}, 199 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 200 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"}, 201 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 202 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"}, 203 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 204 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"}, 205 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 206 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"}, 207 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 208 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"}, 209 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 210 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"}, 211 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 212 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"}, 213 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 214 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"}, 215 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 216 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"}, 217 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 218 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"}, 219 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 220 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 221 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 222 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 223 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 224 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"}, 225 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 226 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"}, 227 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 228 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"}, 229 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 230 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"}, 231 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 232 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"}, 233 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 234 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"}, 235 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 236 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 237 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 238 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"}, 239 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 240 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, 241 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 242 0x0e800120, 0x0f800ff0, 243 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, 244 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 245 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 246 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 247 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"}, 248 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 249 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"}, 250 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 251 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"}, 252 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 253 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"}, 254 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 255 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"}, 256 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 257 0x0e8000a0, 0x0f800ff0, 258 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, 259 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 260 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"}, 261 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 262 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"}, 263 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 264 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"}, 265 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 266 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"}, 267 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 268 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"}, 269 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 270 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 271 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 272 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"}, 273 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 274 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"}, 275 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 276 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"}, 277 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 278 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"}, 279 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 280 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, 281 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 282 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, 283 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 284 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"}, 285 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 286 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, 287 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 288 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, 289 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 290 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"}, 291 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 292 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, 293 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 294 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, 295 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 296 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"}, 297 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 298 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"}, 299 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 300 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"}, 301 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 302 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"}, 303 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 304 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"}, 305 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 306 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 307 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 308 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"}, 309 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 310 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"}, 311 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 312 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"}, 313 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 314 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"}, 315 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 316 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 317 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 318 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 319 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 320 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"}, 321 {ARM_FEATURE_CORE_LOW (0), 322 SENTINEL_IWMMXT_END, 0, "" }, 323 324 /* Floating point coprocessor (FPA) instructions. */ 325 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 326 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 327 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 328 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 329 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 330 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 331 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 332 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 333 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 334 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 335 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 336 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 337 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 338 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"}, 339 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 340 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"}, 341 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 342 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 343 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 344 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"}, 345 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 346 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"}, 347 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 348 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"}, 349 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 350 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"}, 351 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 352 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"}, 353 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 354 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"}, 355 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 356 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"}, 357 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 358 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"}, 359 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 360 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"}, 361 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 362 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"}, 363 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 364 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"}, 365 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 366 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"}, 367 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 368 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"}, 369 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 370 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"}, 371 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 372 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"}, 373 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 374 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"}, 375 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 376 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"}, 377 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 378 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"}, 379 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 380 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"}, 381 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 382 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"}, 383 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 384 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"}, 385 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 386 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"}, 387 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 388 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"}, 389 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 390 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"}, 391 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 392 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"}, 393 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 394 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"}, 395 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 396 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"}, 397 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 398 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"}, 399 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 400 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"}, 401 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 402 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"}, 403 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 404 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"}, 405 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 406 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"}, 407 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2), 408 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"}, 409 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2), 410 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"}, 411 412 /* ARMv8-M Mainline Security Extensions instructions. */ 413 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN), 414 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"}, 415 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN), 416 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"}, 417 418 /* Register load/store. */ 419 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 420 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"}, 421 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 422 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"}, 423 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 424 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"}, 425 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 426 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"}, 427 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 428 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"}, 429 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 430 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"}, 431 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 432 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"}, 433 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 434 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"}, 435 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 436 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"}, 437 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 438 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"}, 439 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 440 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"}, 441 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 442 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"}, 443 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 444 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"}, 445 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 446 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"}, 447 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 448 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"}, 449 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 450 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"}, 451 452 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 453 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"}, 454 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 455 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"}, 456 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 457 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"}, 458 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 459 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"}, 460 461 /* Data transfer between ARM and NEON registers. */ 462 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 463 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"}, 464 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 465 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"}, 466 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 467 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"}, 468 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 469 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"}, 470 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 471 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"}, 472 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 473 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"}, 474 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 475 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"}, 476 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 477 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"}, 478 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 479 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"}, 480 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 481 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"}, 482 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 483 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"}, 484 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 485 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"}, 486 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 487 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"}, 488 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 489 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"}, 490 /* Half-precision conversion instructions. */ 491 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 492 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"}, 493 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 494 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"}, 495 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), 496 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"}, 497 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), 498 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"}, 499 500 /* Floating point coprocessor (VFP) instructions. */ 501 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 502 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"}, 503 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 504 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"}, 505 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 506 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"}, 507 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 508 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"}, 509 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 510 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"}, 511 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 512 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"}, 513 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 514 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"}, 515 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 516 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"}, 517 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 518 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"}, 519 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 520 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"}, 521 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 522 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"}, 523 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 524 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"}, 525 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 526 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"}, 527 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 528 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"}, 529 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 530 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"}, 531 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 532 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"}, 533 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 534 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"}, 535 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 536 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"}, 537 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 538 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"}, 539 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 540 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"}, 541 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 542 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"}, 543 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 544 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"}, 545 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 546 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"}, 547 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 548 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"}, 549 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 550 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"}, 551 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 552 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"}, 553 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 554 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"}, 555 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 556 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"}, 557 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 558 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"}, 559 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 560 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"}, 561 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 562 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"}, 563 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 564 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"}, 565 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 566 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"}, 567 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 568 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"}, 569 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 570 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"}, 571 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 572 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"}, 573 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 574 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"}, 575 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 576 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"}, 577 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 578 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"}, 579 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD), 580 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"}, 581 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3), 582 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"}, 583 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 584 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"}, 585 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 586 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"}, 587 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD), 588 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"}, 589 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3), 590 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"}, 591 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 592 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"}, 593 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD), 594 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"}, 595 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3), 596 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"}, 597 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2), 598 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"}, 599 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2), 600 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"}, 601 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2), 602 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"}, 603 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 604 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"}, 605 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 606 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"}, 607 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 608 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"}, 609 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 610 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"}, 611 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 612 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"}, 613 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 614 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"}, 615 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 616 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"}, 617 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 618 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"}, 619 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 620 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"}, 621 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 622 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"}, 623 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 624 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"}, 625 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 626 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"}, 627 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 628 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"}, 629 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 630 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"}, 631 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 632 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"}, 633 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 634 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"}, 635 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 636 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"}, 637 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 638 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"}, 639 640 /* Cirrus coprocessor instructions. */ 641 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 642 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"}, 643 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 644 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"}, 645 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 646 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"}, 647 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 648 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"}, 649 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 650 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"}, 651 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 652 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"}, 653 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 654 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"}, 655 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 656 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"}, 657 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 658 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"}, 659 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 660 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"}, 661 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 662 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"}, 663 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 664 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"}, 665 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 666 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"}, 667 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 668 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"}, 669 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 670 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"}, 671 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 672 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"}, 673 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 674 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"}, 675 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 676 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"}, 677 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 678 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"}, 679 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 680 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"}, 681 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 682 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"}, 683 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 684 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"}, 685 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 686 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"}, 687 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 688 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"}, 689 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 690 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"}, 691 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 692 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"}, 693 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 694 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"}, 695 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 696 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"}, 697 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 698 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"}, 699 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 700 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"}, 701 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 702 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"}, 703 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 704 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"}, 705 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 706 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"}, 707 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 708 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"}, 709 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 710 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"}, 711 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 712 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"}, 713 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 714 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"}, 715 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 716 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"}, 717 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 718 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"}, 719 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 720 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"}, 721 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 722 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"}, 723 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 724 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"}, 725 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 726 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"}, 727 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 728 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"}, 729 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 730 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"}, 731 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 732 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"}, 733 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 734 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"}, 735 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 736 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"}, 737 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 738 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"}, 739 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 740 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"}, 741 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 742 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"}, 743 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 744 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"}, 745 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 746 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"}, 747 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 748 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"}, 749 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 750 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"}, 751 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 752 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"}, 753 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 754 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"}, 755 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 756 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"}, 757 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 758 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"}, 759 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 760 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"}, 761 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 762 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"}, 763 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 764 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"}, 765 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 766 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, 767 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 768 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, 769 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 770 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, 771 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 772 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, 773 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 774 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, 775 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 776 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, 777 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 778 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"}, 779 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 780 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"}, 781 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 782 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"}, 783 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 784 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"}, 785 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 786 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 787 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 788 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, 789 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 790 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 791 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 792 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, 793 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 794 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 795 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 796 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, 797 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 798 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 799 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 800 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 801 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 802 0x0e000600, 0x0ff00f10, 803 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 804 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 805 0x0e100600, 0x0ff00f10, 806 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 807 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 808 0x0e200600, 0x0ff00f10, 809 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"}, 810 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 811 0x0e300600, 0x0ff00f10, 812 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"}, 813 814 /* VFP Fused multiply add instructions. */ 815 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 816 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"}, 817 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 818 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"}, 819 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 820 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"}, 821 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 822 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"}, 823 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 824 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"}, 825 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 826 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"}, 827 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 828 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"}, 829 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 830 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"}, 831 832 /* FP v5. */ 833 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 834 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"}, 835 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 836 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"}, 837 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 838 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"}, 839 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 840 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"}, 841 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 842 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"}, 843 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 844 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"}, 845 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 846 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"}, 847 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 848 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"}, 849 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 850 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"}, 851 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 852 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"}, 853 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 854 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"}, 855 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 856 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"}, 857 858 /* Generic coprocessor instructions. */ 859 {ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" }, 860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), 861 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"}, 862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), 863 0x0c500000, 0x0ff00000, 864 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"}, 865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 866 0x0e000000, 0x0f000010, 867 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, 868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 869 0x0e10f010, 0x0f10f010, 870 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"}, 871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 872 0x0e100010, 0x0f100010, 873 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, 874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 875 0x0e000010, 0x0f100010, 876 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"}, 877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 878 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"}, 879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 880 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"}, 881 882 /* V6 coprocessor instructions. */ 883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 884 0xfc500000, 0xfff00000, 885 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"}, 886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 887 0xfc400000, 0xfff00000, 888 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"}, 889 890 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */ 891 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 892 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"}, 893 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 894 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"}, 895 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 896 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"}, 897 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 898 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"}, 899 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 900 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"}, 901 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 902 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"}, 903 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 904 0xfe000800, 0xfea00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"}, 905 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 906 0xfe200800, 0xfea00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%23?780"}, 907 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 908 0xfe800800, 0xfea00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"}, 909 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 910 0xfea00800, 0xfea00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%23?780"}, 911 912 /* V5 coprocessor instructions. */ 913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 914 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"}, 915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 916 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"}, 917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 918 0xfe000000, 0xff000010, 919 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, 920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 921 0xfe000010, 0xff100010, 922 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"}, 923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 924 0xfe100010, 0xff100010, 925 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, 926 927 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions. 928 cp_num: bit <11:8> == 0b1001. 929 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */ 930 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 931 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"}, 932 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 933 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"}, 934 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 935 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"}, 936 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 937 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"}, 938 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 939 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"}, 940 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 941 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"}, 942 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 943 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"}, 944 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 945 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"}, 946 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 947 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"}, 948 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 949 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"}, 950 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 951 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"}, 952 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 953 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"}, 954 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 955 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"}, 956 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 957 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"}, 958 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 959 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"}, 960 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 961 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"}, 962 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 963 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"}, 964 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 965 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"}, 966 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 967 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"}, 968 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 969 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"}, 970 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 971 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"}, 972 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 973 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"}, 974 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 975 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"}, 976 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 977 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"}, 978 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 979 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"}, 980 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 981 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"}, 982 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 983 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"}, 984 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 985 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"}, 986 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 987 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"}, 988 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 989 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"}, 990 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 991 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"}, 992 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 993 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"}, 994 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 995 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"}, 996 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 997 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"}, 998 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 999 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"}, 1000 1001 /* ARMv8.3 javascript conversion instruction. */ 1002 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 1003 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"}, 1004 1005 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0} 1006}; 1007 1008/* Neon opcode table: This does not encode the top byte -- that is 1009 checked by the print_insn_neon routine, as it depends on whether we are 1010 doing thumb32 or arm32 disassembly. */ 1011 1012/* print_insn_neon recognizes the following format control codes: 1013 1014 %% % 1015 1016 %c print condition code 1017 %u print condition code (unconditional in ARM mode, 1018 UNPREDICTABLE if not AL in Thumb) 1019 %A print v{st,ld}[1234] operands 1020 %B print v{st,ld}[1234] any one operands 1021 %C print v{st,ld}[1234] single->all operands 1022 %D print scalar 1023 %E print vmov, vmvn, vorr, vbic encoded constant 1024 %F print vtbl,vtbx register list 1025 1026 %<bitfield>r print as an ARM register 1027 %<bitfield>d print the bitfield in decimal 1028 %<bitfield>e print the 2^N - bitfield in decimal 1029 %<bitfield>D print as a NEON D register 1030 %<bitfield>Q print as a NEON Q register 1031 %<bitfield>R print as a NEON D or Q register 1032 %<bitfield>Sn print byte scaled width limited by n 1033 %<bitfield>Tn print short scaled width limited by n 1034 %<bitfield>Un print long scaled width limited by n 1035 1036 %<bitfield>'c print specified char iff bitfield is all ones 1037 %<bitfield>`c print specified char iff bitfield is all zeroes 1038 %<bitfield>?ab... select from array of values in big endian order. */ 1039 1040static const struct opcode32 neon_opcodes[] = 1041{ 1042 /* Extract. */ 1043 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1044 0xf2b00840, 0xffb00850, 1045 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"}, 1046 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1047 0xf2b00000, 0xffb00810, 1048 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"}, 1049 1050 /* Move data element to all lanes. */ 1051 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1052 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"}, 1053 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1054 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"}, 1055 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1056 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"}, 1057 1058 /* Table lookup. */ 1059 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1060 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"}, 1061 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1062 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"}, 1063 1064 /* Half-precision conversions. */ 1065 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), 1066 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"}, 1067 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), 1068 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"}, 1069 1070 /* NEON fused multiply add instructions. */ 1071 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA), 1072 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1073 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1074 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1075 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA), 1076 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1077 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1078 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1079 1080 /* Two registers, miscellaneous. */ 1081 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), 1082 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"}, 1083 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1084 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"}, 1085 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), 1086 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"}, 1087 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1088 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"}, 1089 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1090 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"}, 1091 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1092 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"}, 1093 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1094 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"}, 1095 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1096 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"}, 1097 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1098 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"}, 1099 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1100 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"}, 1101 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1102 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"}, 1103 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1104 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"}, 1105 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1106 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"}, 1107 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1108 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"}, 1109 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1110 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"}, 1111 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1112 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"}, 1113 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1114 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"}, 1115 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1116 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"}, 1117 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1118 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"}, 1119 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1120 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"}, 1121 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1122 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"}, 1123 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1124 0xf3b20300, 0xffb30fd0, 1125 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"}, 1126 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1127 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"}, 1128 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1129 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"}, 1130 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1131 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"}, 1132 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1133 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"}, 1134 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1135 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1136 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1137 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1138 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1139 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1140 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1141 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, 1142 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1143 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"}, 1144 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1145 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, 1146 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1147 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, 1148 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1149 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1150 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1151 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1152 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1153 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1154 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1155 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, 1156 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1157 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, 1158 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1159 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"}, 1160 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1161 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, 1162 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1163 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, 1164 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1165 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"}, 1166 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1167 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"}, 1168 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1169 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"}, 1170 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1171 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"}, 1172 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1173 0xf3bb0600, 0xffbf0e10, 1174 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"}, 1175 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1176 0xf3b70600, 0xffbf0e10, 1177 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"}, 1178 1179 /* Three registers of the same length. */ 1180 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1181 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1182 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1183 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1184 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1185 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1186 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1187 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1188 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1189 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1190 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1191 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1192 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1193 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1194 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), 1195 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1196 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1197 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1198 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), 1199 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1200 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1201 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1202 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1203 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1204 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1205 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1206 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1207 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1208 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1209 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1210 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1211 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1212 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1213 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1214 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1215 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1216 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1217 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1218 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1219 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1220 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1221 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1222 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1223 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1224 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1225 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1226 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1227 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1228 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1229 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1230 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1231 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1232 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1233 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1234 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1235 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1236 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1237 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1238 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1239 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1240 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1241 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1242 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1243 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1244 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1245 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1246 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1247 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1248 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1249 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1250 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1251 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1252 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1253 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1254 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1255 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1256 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1257 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1258 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1259 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1260 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1261 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1262 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1263 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1264 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1265 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1266 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1267 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1268 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1269 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1270 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1271 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1272 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1273 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1274 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1275 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1276 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1277 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1278 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1279 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1280 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1281 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1282 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1283 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1284 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1285 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1286 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1287 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1288 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1289 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1290 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1291 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1292 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1293 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1294 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1295 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1296 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1297 0xf2000b00, 0xff800f10, 1298 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1299 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1300 0xf2000b10, 0xff800f10, 1301 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1302 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1303 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1304 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1305 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1306 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1307 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1308 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1309 0xf3000b00, 0xff800f10, 1310 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1311 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1312 0xf2000000, 0xfe800f10, 1313 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1314 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1315 0xf2000010, 0xfe800f10, 1316 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1317 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1318 0xf2000100, 0xfe800f10, 1319 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1320 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1321 0xf2000200, 0xfe800f10, 1322 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1323 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1324 0xf2000210, 0xfe800f10, 1325 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1326 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1327 0xf2000300, 0xfe800f10, 1328 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1329 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1330 0xf2000310, 0xfe800f10, 1331 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1332 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1333 0xf2000400, 0xfe800f10, 1334 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, 1335 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1336 0xf2000410, 0xfe800f10, 1337 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, 1338 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1339 0xf2000500, 0xfe800f10, 1340 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, 1341 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1342 0xf2000510, 0xfe800f10, 1343 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, 1344 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1345 0xf2000600, 0xfe800f10, 1346 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1347 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1348 0xf2000610, 0xfe800f10, 1349 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1350 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1351 0xf2000700, 0xfe800f10, 1352 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1353 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1354 0xf2000710, 0xfe800f10, 1355 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1356 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1357 0xf2000910, 0xfe800f10, 1358 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1359 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1360 0xf2000a00, 0xfe800f10, 1361 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1362 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1363 0xf2000a10, 0xfe800f10, 1364 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1365 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 1366 0xf3000b10, 0xff800f10, 1367 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1368 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 1369 0xf3000c10, 0xff800f10, 1370 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1371 1372 /* One register and an immediate value. */ 1373 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1374 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"}, 1375 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1376 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"}, 1377 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1378 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"}, 1379 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1380 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"}, 1381 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1382 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"}, 1383 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1384 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"}, 1385 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1386 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"}, 1387 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1388 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"}, 1389 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1390 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"}, 1391 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1392 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"}, 1393 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1394 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"}, 1395 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1396 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"}, 1397 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1398 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"}, 1399 1400 /* Two registers and a shift amount. */ 1401 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1402 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 1403 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1404 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 1405 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1406 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 1407 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1408 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 1409 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1410 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 1411 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1412 0xf2880950, 0xfeb80fd0, 1413 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 1414 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1415 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"}, 1416 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1417 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 1418 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1419 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 1420 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1421 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"}, 1422 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1423 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"}, 1424 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1425 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"}, 1426 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1427 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"}, 1428 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1429 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 1430 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1431 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 1432 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1433 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 1434 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1435 0xf2900950, 0xfeb00fd0, 1436 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 1437 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1438 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"}, 1439 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1440 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, 1441 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1442 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, 1443 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1444 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, 1445 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1446 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, 1447 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1448 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"}, 1449 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1450 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 1451 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1452 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 1453 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1454 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"}, 1455 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1456 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"}, 1457 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1458 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"}, 1459 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1460 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"}, 1461 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1462 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"}, 1463 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1464 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, 1465 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1466 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, 1467 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1468 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, 1469 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1470 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, 1471 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1472 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"}, 1473 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1474 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 1475 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1476 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 1477 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1478 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 1479 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1480 0xf2a00950, 0xfea00fd0, 1481 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 1482 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1483 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"}, 1484 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1485 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"}, 1486 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1487 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"}, 1488 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1489 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"}, 1490 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1491 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, 1492 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1493 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, 1494 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1495 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, 1496 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1497 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, 1498 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1499 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"}, 1500 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1501 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"}, 1502 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1503 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"}, 1504 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1505 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"}, 1506 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1507 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"}, 1508 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1509 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, 1510 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1511 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, 1512 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1513 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, 1514 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1515 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, 1516 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1517 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"}, 1518 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1519 0xf2a00e10, 0xfea00e90, 1520 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"}, 1521 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1522 0xf2a00c10, 0xfea00e90, 1523 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"}, 1524 1525 /* Three registers of different lengths. */ 1526 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1527 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1528 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1529 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1530 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1531 0xf2800400, 0xff800f50, 1532 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, 1533 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1534 0xf2800600, 0xff800f50, 1535 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, 1536 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1537 0xf2800900, 0xff800f50, 1538 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1539 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1540 0xf2800b00, 0xff800f50, 1541 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1542 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1543 0xf2800d00, 0xff800f50, 1544 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1545 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1546 0xf3800400, 0xff800f50, 1547 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, 1548 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1549 0xf3800600, 0xff800f50, 1550 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, 1551 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1552 0xf2800000, 0xfe800f50, 1553 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1554 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1555 0xf2800100, 0xfe800f50, 1556 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"}, 1557 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1558 0xf2800200, 0xfe800f50, 1559 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1560 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1561 0xf2800300, 0xfe800f50, 1562 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"}, 1563 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1564 0xf2800500, 0xfe800f50, 1565 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1566 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1567 0xf2800700, 0xfe800f50, 1568 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1569 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1570 0xf2800800, 0xfe800f50, 1571 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1572 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1573 0xf2800a00, 0xfe800f50, 1574 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1575 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1576 0xf2800c00, 0xfe800f50, 1577 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1578 1579 /* Two registers and a scalar. */ 1580 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1581 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1582 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1583 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"}, 1584 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 1585 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"}, 1586 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1587 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 1588 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1589 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1590 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1591 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1592 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 1593 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"}, 1594 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1595 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 1596 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1597 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1598 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1599 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"}, 1600 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 1601 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"}, 1602 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1603 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 1604 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1605 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1606 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1607 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1608 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1609 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 1610 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1611 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, 1612 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 1613 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"}, 1614 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1615 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 1616 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1617 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, 1618 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 1619 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"}, 1620 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1621 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 1622 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1623 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, 1624 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 1625 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"}, 1626 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1627 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 1628 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1629 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 1630 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1631 0xf2800240, 0xfe800f50, 1632 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 1633 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1634 0xf2800640, 0xfe800f50, 1635 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 1636 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1637 0xf2800a40, 0xfe800f50, 1638 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 1639 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 1640 0xf2800e40, 0xff800f50, 1641 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1642 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 1643 0xf2800f40, 0xff800f50, 1644 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1645 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 1646 0xf3800e40, 0xff800f50, 1647 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 1648 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 1649 0xf3800f40, 0xff800f50, 1650 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D" 1651 }, 1652 1653 /* Element and structure load/store. */ 1654 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1655 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"}, 1656 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1657 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"}, 1658 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1659 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"}, 1660 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1661 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"}, 1662 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1663 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"}, 1664 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1665 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, 1666 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1667 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, 1668 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1669 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"}, 1670 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1671 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"}, 1672 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1673 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, 1674 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1675 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, 1676 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1677 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, 1678 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1679 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, 1680 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1681 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, 1682 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1683 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"}, 1684 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1685 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"}, 1686 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1687 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"}, 1688 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1689 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"}, 1690 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1691 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"}, 1692 1693 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0} 1694}; 1695 1696/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially 1697 ordered: they must be searched linearly from the top to obtain a correct 1698 match. */ 1699 1700/* print_insn_arm recognizes the following format control codes: 1701 1702 %% % 1703 1704 %a print address for ldr/str instruction 1705 %s print address for ldr/str halfword/signextend instruction 1706 %S like %s but allow UNPREDICTABLE addressing 1707 %b print branch destination 1708 %c print condition code (always bits 28-31) 1709 %m print register mask for ldm/stm instruction 1710 %o print operand2 (immediate or register + shift) 1711 %p print 'p' iff bits 12-15 are 15 1712 %t print 't' iff bit 21 set and bit 24 clear 1713 %B print arm BLX(1) destination 1714 %C print the PSR sub type. 1715 %U print barrier type. 1716 %P print address for pli instruction. 1717 1718 %<bitfield>r print as an ARM register 1719 %<bitfield>T print as an ARM register + 1 1720 %<bitfield>R as %r but r15 is UNPREDICTABLE 1721 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE 1722 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE 1723 %<bitfield>d print the bitfield in decimal 1724 %<bitfield>W print the bitfield plus one in decimal 1725 %<bitfield>x print the bitfield in hex 1726 %<bitfield>X print the bitfield as 1 hex digit without leading "0x" 1727 1728 %<bitfield>'c print specified char iff bitfield is all ones 1729 %<bitfield>`c print specified char iff bitfield is all zeroes 1730 %<bitfield>?ab... select from array of values in big endian order 1731 1732 %e print arm SMI operand (bits 0..7,8..19). 1733 %E print the LSB and WIDTH fields of a BFI or BFC instruction. 1734 %V print the 16-bit immediate field of a MOVT or MOVW instruction. 1735 %R print the SPSR/CPSR or banked register of an MRS. */ 1736 1737static const struct opcode32 arm_opcodes[] = 1738{ 1739 /* ARM instructions. */ 1740 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 1741 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"}, 1742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 1743 0xe7f000f0, 0xfff000f0, "udf\t#%e"}, 1744 1745 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5), 1746 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"}, 1747 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 1748 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"}, 1749 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 1750 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 1751 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S), 1752 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"}, 1753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M), 1754 0x00800090, 0x0fa000f0, 1755 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 1756 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M), 1757 0x00a00090, 0x0fa000f0, 1758 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 1759 1760 /* V8.2 RAS extension instructions. */ 1761 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS), 1762 0xe320f010, 0xffffffff, "esb"}, 1763 1764 /* V8 instructions. */ 1765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 1766 0x0320f005, 0x0fffffff, "sevl"}, 1767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 1768 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"}, 1769 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS), 1770 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"}, 1771 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1772 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"}, 1773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 1774 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"}, 1775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 1776 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"}, 1777 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1778 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"}, 1779 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1780 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"}, 1781 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1782 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"}, 1783 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1784 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"}, 1785 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1786 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"}, 1787 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1788 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"}, 1789 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1790 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"}, 1791 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1792 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"}, 1793 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1794 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"}, 1795 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1796 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"}, 1797 /* CRC32 instructions. */ 1798 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 1799 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"}, 1800 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 1801 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"}, 1802 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 1803 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"}, 1804 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 1805 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"}, 1806 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 1807 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"}, 1808 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 1809 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"}, 1810 1811 /* Privileged Access Never extension instructions. */ 1812 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 1813 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"}, 1814 1815 /* Virtualization Extension instructions. */ 1816 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"}, 1817 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"}, 1818 1819 /* Integer Divide Extension instructions. */ 1820 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV), 1821 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"}, 1822 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV), 1823 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"}, 1824 1825 /* MP Extension instructions. */ 1826 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"}, 1827 1828 /* V7 instructions. */ 1829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"}, 1830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"}, 1831 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"}, 1832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"}, 1833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"}, 1834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"}, 1835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"}, 1836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 1837 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"}, 1838 1839 /* ARM V6T2 instructions. */ 1840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 1841 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"}, 1842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 1843 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"}, 1844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 1845 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 1846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 1847 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"}, 1848 1849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 1850 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION }, 1851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 1852 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"}, 1853 1854 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 1855 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"}, 1856 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 1857 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"}, 1858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 1859 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"}, 1860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 1861 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"}, 1862 1863 /* ARM Security extension instructions. */ 1864 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 1865 0x01600070, 0x0ff000f0, "smc%c\t%e"}, 1866 1867 /* ARM V6K instructions. */ 1868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1869 0xf57ff01f, 0xffffffff, "clrex"}, 1870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1871 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"}, 1872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1873 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"}, 1874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1875 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"}, 1876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1877 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"}, 1878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1879 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"}, 1880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1881 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"}, 1882 1883 /* ARM V6K NOP hints. */ 1884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1885 0x0320f001, 0x0fffffff, "yield%c"}, 1886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1887 0x0320f002, 0x0fffffff, "wfe%c"}, 1888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1889 0x0320f003, 0x0fffffff, "wfi%c"}, 1890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1891 0x0320f004, 0x0fffffff, "sev%c"}, 1892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1893 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"}, 1894 1895 /* ARM V6 instructions. */ 1896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1897 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"}, 1898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1899 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"}, 1900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1901 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"}, 1902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1903 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"}, 1904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1905 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"}, 1906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1907 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"}, 1908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1909 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"}, 1910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1911 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"}, 1912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1913 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"}, 1914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1915 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"}, 1916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1917 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"}, 1918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1919 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"}, 1920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1921 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"}, 1922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1923 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"}, 1924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1925 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"}, 1926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1927 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"}, 1928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1929 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"}, 1930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1931 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"}, 1932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1933 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"}, 1934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1935 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"}, 1936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1937 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"}, 1938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1939 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"}, 1940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1941 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"}, 1942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1943 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"}, 1944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1945 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"}, 1946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1947 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"}, 1948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1949 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"}, 1950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1951 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"}, 1952 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1953 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"}, 1954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1955 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"}, 1956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1957 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"}, 1958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1959 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"}, 1960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1961 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"}, 1962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1963 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"}, 1964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1965 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"}, 1966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1967 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"}, 1968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1969 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"}, 1970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1971 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"}, 1972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1973 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"}, 1974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1975 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"}, 1976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1977 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"}, 1978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1979 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"}, 1980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1981 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"}, 1982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1983 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"}, 1984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1985 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"}, 1986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1987 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"}, 1988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1989 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"}, 1990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1991 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"}, 1992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1993 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"}, 1994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1995 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"}, 1996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1997 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"}, 1998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1999 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"}, 2000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2001 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"}, 2002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2003 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"}, 2004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2005 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"}, 2006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2007 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"}, 2008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2009 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"}, 2010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2011 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"}, 2012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2013 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"}, 2014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2015 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"}, 2016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2017 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"}, 2018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2019 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"}, 2020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2021 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"}, 2022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2023 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"}, 2024 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2025 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"}, 2026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2027 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"}, 2028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2029 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"}, 2030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2031 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"}, 2032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2033 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"}, 2034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2035 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"}, 2036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2037 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"}, 2038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2039 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"}, 2040 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2041 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"}, 2042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2043 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"}, 2044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2045 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"}, 2046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2047 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"}, 2048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2049 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"}, 2050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2051 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"}, 2052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2053 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"}, 2054 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2055 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"}, 2056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2057 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"}, 2058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2059 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"}, 2060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2061 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"}, 2062 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2063 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"}, 2064 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2065 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"}, 2066 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2067 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"}, 2068 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2069 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"}, 2070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2071 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"}, 2072 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2073 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"}, 2074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2075 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"}, 2076 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2077 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"}, 2078 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2079 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"}, 2080 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2081 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"}, 2082 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2083 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"}, 2084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2085 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"}, 2086 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2087 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"}, 2088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2089 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"}, 2090 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2091 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"}, 2092 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2093 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"}, 2094 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2095 0xf1010000, 0xfffffc00, "setend\t%9?ble"}, 2096 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2097 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"}, 2098 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2099 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"}, 2100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2101 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 2102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2103 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 2104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2105 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 2106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2107 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 2108 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2109 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"}, 2110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2111 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 2112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2113 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 2114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2115 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"}, 2116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2117 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"}, 2118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2119 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"}, 2120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2121 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"}, 2122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2123 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"}, 2124 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2125 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"}, 2126 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2127 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"}, 2128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2129 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"}, 2130 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2131 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 2132 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2133 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"}, 2134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2135 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"}, 2136 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2137 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"}, 2138 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2139 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"}, 2140 2141 /* V5J instruction. */ 2142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J), 2143 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"}, 2144 2145 /* V5 Instructions. */ 2146 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 2147 0xe1200070, 0xfff000f0, 2148 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"}, 2149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 2150 0xfa000000, 0xfe000000, "blx\t%B"}, 2151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 2152 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"}, 2153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 2154 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"}, 2155 2156 /* V5E "El Segundo" Instructions. */ 2157 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), 2158 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"}, 2159 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), 2160 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"}, 2161 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), 2162 0xf450f000, 0xfc70f000, "pld\t%a"}, 2163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2164 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 2165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2166 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 2167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2168 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 2169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2170 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"}, 2171 2172 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2173 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 2174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2175 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"}, 2176 2177 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2178 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 2179 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2180 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 2181 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2182 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 2183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2184 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 2185 2186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2187 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"}, 2188 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2189 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"}, 2190 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2191 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"}, 2192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2193 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"}, 2194 2195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2196 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"}, 2197 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2198 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"}, 2199 2200 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2201 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"}, 2202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2203 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"}, 2204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2205 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"}, 2206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2207 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"}, 2208 2209 /* ARM Instructions. */ 2210 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2211 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"}, 2212 2213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2214 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"}, 2215 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2216 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"}, 2217 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2218 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"}, 2219 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2220 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"}, 2221 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2222 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"}, 2223 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2224 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"}, 2225 2226 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2227 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"}, 2228 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2229 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"}, 2230 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2231 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"}, 2232 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2233 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"}, 2234 2235 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2236 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION}, 2237 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2238 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"}, 2239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2240 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION}, 2241 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2242 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"}, 2243 2244 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2245 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"}, 2246 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2247 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"}, 2248 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2249 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"}, 2250 2251 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2252 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"}, 2253 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2254 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"}, 2255 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2256 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"}, 2257 2258 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2259 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"}, 2260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2261 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"}, 2262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2263 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"}, 2264 2265 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2266 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"}, 2267 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2268 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"}, 2269 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2270 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"}, 2271 2272 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2273 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"}, 2274 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2275 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"}, 2276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2277 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"}, 2278 2279 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2280 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"}, 2281 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2282 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"}, 2283 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2284 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"}, 2285 2286 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2287 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"}, 2288 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2289 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"}, 2290 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2291 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"}, 2292 2293 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2294 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"}, 2295 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2296 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"}, 2297 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2298 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"}, 2299 2300 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 2301 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"}, 2302 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 2303 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"}, 2304 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 2305 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"}, 2306 2307 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2308 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"}, 2309 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2310 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"}, 2311 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2312 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"}, 2313 2314 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2315 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"}, 2316 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2317 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"}, 2318 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2319 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"}, 2320 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 2321 0x0130f000, 0x0ff0f010, "bx%c\t%0-3r"}, 2322 2323 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2324 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"}, 2325 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2326 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"}, 2327 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2328 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"}, 2329 2330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2331 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"}, 2332 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2333 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"}, 2334 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2335 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"}, 2336 2337 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2338 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"}, 2339 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2340 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"}, 2341 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2342 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"}, 2343 2344 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2345 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"}, 2346 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2347 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"}, 2348 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2349 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"}, 2350 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2351 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"}, 2352 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2353 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"}, 2354 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2355 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"}, 2356 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2357 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"}, 2358 2359 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2360 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"}, 2361 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2362 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"}, 2363 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2364 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"}, 2365 2366 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2367 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"}, 2368 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2369 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"}, 2370 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2371 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"}, 2372 2373 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2374 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION}, 2375 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2376 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"}, 2377 2378 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2379 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"}, 2380 2381 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2382 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"}, 2383 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2384 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"}, 2385 2386 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2387 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2388 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2389 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2390 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2391 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2392 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2393 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2394 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2395 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2396 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2397 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2398 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2399 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2400 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2401 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2402 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2403 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2404 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2405 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2406 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2407 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2408 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2409 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2410 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2411 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2412 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2413 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2414 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2415 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2416 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2417 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2418 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2419 0x092d0000, 0x0fff0000, "push%c\t%m"}, 2420 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2421 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"}, 2422 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2423 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"}, 2424 2425 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2426 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2427 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2428 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2429 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2430 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2431 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2432 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2433 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2434 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2435 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2436 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2437 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2438 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2439 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2440 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2441 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2442 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2443 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2444 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2445 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2446 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2447 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2448 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2449 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2450 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2451 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2452 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2453 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2454 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2455 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2456 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2457 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2458 0x08bd0000, 0x0fff0000, "pop%c\t%m"}, 2459 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2460 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"}, 2461 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2462 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"}, 2463 2464 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2465 0x0a000000, 0x0e000000, "b%24'l%c\t%b"}, 2466 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2467 0x0f000000, 0x0f000000, "svc%c\t%0-23x"}, 2468 2469 /* The rest. */ 2470 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 2471 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION}, 2472 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2473 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION}, 2474 {ARM_FEATURE_CORE_LOW (0), 2475 0x00000000, 0x00000000, 0} 2476}; 2477 2478/* print_insn_thumb16 recognizes the following format control codes: 2479 2480 %S print Thumb register (bits 3..5 as high number if bit 6 set) 2481 %D print Thumb register (bits 0..2 as high number if bit 7 set) 2482 %<bitfield>I print bitfield as a signed decimal 2483 (top bit of range being the sign bit) 2484 %N print Thumb register mask (with LR) 2485 %O print Thumb register mask (with PC) 2486 %M print Thumb register mask 2487 %b print CZB's 6-bit unsigned branch destination 2488 %s print Thumb right-shift immediate (6..10; 0 == 32). 2489 %c print the condition code 2490 %C print the condition code, or "s" if not conditional 2491 %x print warning if conditional an not at end of IT block" 2492 %X print "\t; unpredictable <IT:code>" if conditional 2493 %I print IT instruction suffix and operands 2494 %W print Thumb Writeback indicator for LDMIA 2495 %<bitfield>r print bitfield as an ARM register 2496 %<bitfield>d print bitfield as a decimal 2497 %<bitfield>H print (bitfield * 2) as a decimal 2498 %<bitfield>W print (bitfield * 4) as a decimal 2499 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol 2500 %<bitfield>B print Thumb branch destination (signed displacement) 2501 %<bitfield>c print bitfield as a condition code 2502 %<bitnum>'c print specified char iff bit is one 2503 %<bitnum>?ab print a if bit is one else print b. */ 2504 2505static const struct opcode16 thumb_opcodes[] = 2506{ 2507 /* Thumb instructions. */ 2508 2509 /* ARMv8-M Security Extensions instructions. */ 2510 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"}, 2511 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff07, "bxns\t%3-6r"}, 2512 2513 /* ARM V8 instructions. */ 2514 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"}, 2515 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"}, 2516 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"}, 2517 2518 /* ARM V6K no-argument instructions. */ 2519 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"}, 2520 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"}, 2521 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"}, 2522 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"}, 2523 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"}, 2524 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"}, 2525 2526 /* ARM V6T2 instructions. */ 2527 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 2528 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"}, 2529 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 2530 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"}, 2531 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"}, 2532 2533 /* ARM V6. */ 2534 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"}, 2535 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"}, 2536 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"}, 2537 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"}, 2538 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"}, 2539 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"}, 2540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"}, 2541 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"}, 2542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"}, 2543 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"}, 2544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"}, 2545 2546 /* ARM V5 ISA extends Thumb. */ 2547 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T), 2548 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */ 2549 /* This is BLX(2). BLX(1) is a 32-bit instruction. */ 2550 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T), 2551 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */ 2552 /* ARM V4T ISA (Thumb v1). */ 2553 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2554 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"}, 2555 /* Format 4. */ 2556 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"}, 2557 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"}, 2558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"}, 2559 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"}, 2560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"}, 2561 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"}, 2562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"}, 2563 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"}, 2564 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"}, 2565 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"}, 2566 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"}, 2567 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"}, 2568 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"}, 2569 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"}, 2570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"}, 2571 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"}, 2572 /* format 13 */ 2573 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"}, 2574 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"}, 2575 /* format 5 */ 2576 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"}, 2577 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"}, 2578 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"}, 2579 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"}, 2580 /* format 14 */ 2581 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"}, 2582 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"}, 2583 /* format 2 */ 2584 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2585 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"}, 2586 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2587 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"}, 2588 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2589 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"}, 2590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2591 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"}, 2592 /* format 8 */ 2593 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2594 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"}, 2595 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2596 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"}, 2597 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2598 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"}, 2599 /* format 7 */ 2600 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2601 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"}, 2602 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2603 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"}, 2604 /* format 1 */ 2605 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"}, 2606 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2607 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"}, 2608 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"}, 2609 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"}, 2610 /* format 3 */ 2611 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"}, 2612 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"}, 2613 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"}, 2614 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"}, 2615 /* format 6 */ 2616 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */ 2617 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2618 0x4800, 0xF800, 2619 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"}, 2620 /* format 9 */ 2621 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2622 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"}, 2623 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2624 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"}, 2625 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2626 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"}, 2627 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2628 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"}, 2629 /* format 10 */ 2630 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2631 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"}, 2632 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2633 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"}, 2634 /* format 11 */ 2635 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2636 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"}, 2637 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2638 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"}, 2639 /* format 12 */ 2640 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2641 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"}, 2642 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2643 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"}, 2644 /* format 15 */ 2645 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"}, 2646 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"}, 2647 /* format 17 */ 2648 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"}, 2649 /* format 16 */ 2650 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"}, 2651 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION}, 2652 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"}, 2653 /* format 18 */ 2654 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"}, 2655 2656 /* The E800 .. FFFF range is unconditionally redirected to the 2657 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs 2658 are processed via that table. Thus, we can never encounter a 2659 bare "second half of BL/BLX(1)" instruction here. */ 2660 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION}, 2661 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0} 2662}; 2663 2664/* Thumb32 opcodes use the same table structure as the ARM opcodes. 2665 We adopt the convention that hw1 is the high 16 bits of .value and 2666 .mask, hw2 the low 16 bits. 2667 2668 print_insn_thumb32 recognizes the following format control codes: 2669 2670 %% % 2671 2672 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0] 2673 %M print a modified 12-bit immediate (same location) 2674 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0] 2675 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4] 2676 %H print a 16-bit immediate from hw2[3:0],hw1[11:0] 2677 %S print a possibly-shifted Rm 2678 2679 %L print address for a ldrd/strd instruction 2680 %a print the address of a plain load/store 2681 %w print the width and signedness of a core load/store 2682 %m print register mask for ldm/stm 2683 2684 %E print the lsb and width fields of a bfc/bfi instruction 2685 %F print the lsb and width fields of a sbfx/ubfx instruction 2686 %b print a conditional branch offset 2687 %B print an unconditional branch offset 2688 %s print the shift field of an SSAT instruction 2689 %R print the rotation field of an SXT instruction 2690 %U print barrier type. 2691 %P print address for pli instruction. 2692 %c print the condition code 2693 %x print warning if conditional an not at end of IT block" 2694 %X print "\t; unpredictable <IT:code>" if conditional 2695 2696 %<bitfield>d print bitfield in decimal 2697 %<bitfield>D print bitfield plus one in decimal 2698 %<bitfield>W print bitfield*4 in decimal 2699 %<bitfield>r print bitfield as an ARM register 2700 %<bitfield>R as %<>r but r15 is UNPREDICTABLE 2701 %<bitfield>S as %<>R but r13 is UNPREDICTABLE 2702 %<bitfield>c print bitfield as a condition code 2703 2704 %<bitfield>'c print specified char iff bitfield is all ones 2705 %<bitfield>`c print specified char iff bitfield is all zeroes 2706 %<bitfield>?ab... select from array of values in big endian order 2707 2708 With one exception at the bottom (done because BL and BLX(1) need 2709 to come dead last), this table was machine-sorted first in 2710 decreasing order of number of bits set in the mask, then in 2711 increasing numeric order of mask, then in increasing numeric order 2712 of opcode. This order is not the clearest for a human reader, but 2713 is guaranteed never to catch a special-case bit pattern with a more 2714 general mask, which is important, because this instruction encoding 2715 makes heavy use of special-case bit patterns. */ 2716static const struct opcode32 thumb32_opcodes[] = 2717{ 2718 /* ARMv8-M and ARMv8-M Security Extensions instructions. */ 2719 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"}, 2720 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 2721 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"}, 2722 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 2723 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"}, 2724 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 2725 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"}, 2726 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 2727 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"}, 2728 2729 /* ARM V8.2 RAS extension instructions. */ 2730 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS), 2731 0xf3af8010, 0xffffffff, "esb"}, 2732 2733 /* V8 instructions. */ 2734 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2735 0xf3af8005, 0xffffffff, "sevl%c.w"}, 2736 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2737 0xf78f8000, 0xfffffffc, "dcps%0-1d"}, 2738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2739 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"}, 2740 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2741 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"}, 2742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2743 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"}, 2744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2745 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"}, 2746 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2747 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"}, 2748 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2749 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"}, 2750 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2751 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"}, 2752 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2753 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"}, 2754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2755 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"}, 2756 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2757 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"}, 2758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2759 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"}, 2760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2761 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"}, 2762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2763 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"}, 2764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2765 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"}, 2766 2767 /* CRC32 instructions. */ 2768 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 2769 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11S, %16-19S, %0-3S"}, 2770 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 2771 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11S, %16-19S, %0-3S"}, 2772 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 2773 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11S, %16-19S, %0-3S"}, 2774 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 2775 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11S, %16-19S, %0-3S"}, 2776 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 2777 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11S, %16-19S, %0-3S"}, 2778 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 2779 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11S, %16-19S, %0-3S"}, 2780 2781 /* V7 instructions. */ 2782 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"}, 2783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"}, 2784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"}, 2785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"}, 2786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"}, 2787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"}, 2788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"}, 2789 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV), 2790 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"}, 2791 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV), 2792 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"}, 2793 2794 /* Virtualization Extension instructions. */ 2795 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"}, 2796 /* We skip ERET as that is SUBS pc, lr, #0. */ 2797 2798 /* MP Extension instructions. */ 2799 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"}, 2800 2801 /* Security extension instructions. */ 2802 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"}, 2803 2804 /* Instructions defined in the basic V6T2 set. */ 2805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"}, 2806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"}, 2807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"}, 2808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"}, 2809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"}, 2810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2811 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"}, 2812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"}, 2813 2814 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 2815 0xf3bf8f2f, 0xffffffff, "clrex%c"}, 2816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2817 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"}, 2818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2819 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"}, 2820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2821 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"}, 2822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2823 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"}, 2824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2825 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"}, 2826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2827 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"}, 2828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2829 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"}, 2830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2831 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"}, 2832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2833 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"}, 2834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2835 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"}, 2836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2837 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"}, 2838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2839 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"}, 2840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2841 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"}, 2842 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 2843 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"}, 2844 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 2845 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"}, 2846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2847 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"}, 2848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2849 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"}, 2850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2851 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"}, 2852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2853 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"}, 2854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2855 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"}, 2856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2857 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"}, 2858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2859 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"}, 2860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2861 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"}, 2862 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 2863 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"}, 2864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2865 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"}, 2866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2867 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"}, 2868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2869 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"}, 2870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2871 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"}, 2872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2873 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"}, 2874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2875 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"}, 2876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2877 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"}, 2878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2879 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"}, 2880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2881 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"}, 2882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2883 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"}, 2884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2885 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"}, 2886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2887 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"}, 2888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2889 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"}, 2890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2891 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"}, 2892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2893 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"}, 2894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2895 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"}, 2896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2897 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"}, 2898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2899 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"}, 2900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2901 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"}, 2902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2903 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"}, 2904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2905 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"}, 2906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2907 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"}, 2908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2909 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"}, 2910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2911 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"}, 2912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2913 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"}, 2914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2915 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"}, 2916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2917 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"}, 2918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2919 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"}, 2920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2921 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"}, 2922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2923 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"}, 2924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2925 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"}, 2926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2927 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"}, 2928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2929 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"}, 2930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2931 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"}, 2932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2933 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"}, 2934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2935 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"}, 2936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2937 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"}, 2938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2939 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"}, 2940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2941 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"}, 2942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2943 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"}, 2944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2945 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"}, 2946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2947 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"}, 2948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2949 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"}, 2950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2951 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"}, 2952 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2953 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"}, 2954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2955 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"}, 2956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2957 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"}, 2958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2959 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"}, 2960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2961 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"}, 2962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2963 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"}, 2964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2965 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"}, 2966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2967 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"}, 2968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2969 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"}, 2970 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 2971 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"}, 2972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2973 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"}, 2974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2975 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"}, 2976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2977 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"}, 2978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2979 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"}, 2980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2981 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"}, 2982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2983 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"}, 2984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2985 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"}, 2986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2987 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"}, 2988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2989 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"}, 2990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2991 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"}, 2992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2993 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"}, 2994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2995 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"}, 2996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2997 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"}, 2998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2999 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"}, 3000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3001 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"}, 3002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3003 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"}, 3004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3005 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"}, 3006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3007 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"}, 3008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3009 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"}, 3010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3011 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"}, 3012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3013 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"}, 3014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3015 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"}, 3016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3017 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"}, 3018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3019 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"}, 3020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3021 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"}, 3022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3023 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, 3024 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3025 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, 3026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3027 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 3028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3029 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 3030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3031 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 3032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3033 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 3034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3035 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 3036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3037 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 3038 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 3039 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"}, 3040 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3041 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"}, 3042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3043 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"}, 3044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3045 0xf810f000, 0xff70f000, "pld%c\t%a"}, 3046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3047 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 3048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3049 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 3050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3051 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 3052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3053 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 3054 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3055 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 3056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3057 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 3058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3059 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 3060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3061 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"}, 3062 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3063 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"}, 3064 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3065 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"}, 3066 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3067 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"}, 3068 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3069 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"}, 3070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3071 0xfb100000, 0xfff000c0, 3072 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, 3073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3074 0xfbc00080, 0xfff000c0, 3075 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, 3076 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3077 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"}, 3078 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3079 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"}, 3080 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3081 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"}, 3082 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3083 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"}, 3084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3085 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"}, 3086 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 3087 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"}, 3088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3089 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"}, 3090 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 3091 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"}, 3092 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3093 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"}, 3094 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3095 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"}, 3096 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3097 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"}, 3098 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3099 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"}, 3100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3101 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"}, 3102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3103 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"}, 3104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3105 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"}, 3106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3107 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"}, 3108 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3109 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"}, 3110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3111 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"}, 3112 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 3113 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"}, 3114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3115 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"}, 3116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3117 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"}, 3118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3119 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"}, 3120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3121 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"}, 3122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3123 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"}, 3124 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3125 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"}, 3126 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3127 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"}, 3128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3129 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"}, 3130 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3131 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"}, 3132 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3133 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"}, 3134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3135 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"}, 3136 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3137 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"}, 3138 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3139 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"}, 3140 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3141 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"}, 3142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3143 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"}, 3144 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3145 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"}, 3146 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3147 0xe9400000, 0xff500000, 3148 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"}, 3149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3150 0xe9500000, 0xff500000, 3151 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"}, 3152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3153 0xe8600000, 0xff700000, 3154 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"}, 3155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3156 0xe8700000, 0xff700000, 3157 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"}, 3158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3159 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"}, 3160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3161 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"}, 3162 3163 /* Filter out Bcc with cond=E or F, which are used for other instructions. */ 3164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3165 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"}, 3166 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3167 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"}, 3168 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3169 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"}, 3170 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3171 0xf0009000, 0xf800d000, "b%c.w\t%B%x"}, 3172 3173 /* These have been 32-bit since the invention of Thumb. */ 3174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 3175 0xf000c000, 0xf800d001, "blx%c\t%B%x"}, 3176 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 3177 0xf000d000, 0xf800d000, "bl%c\t%B%x"}, 3178 3179 /* Fallback. */ 3180 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3181 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION}, 3182 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0} 3183}; 3184 3185static const char *const arm_conditional[] = 3186{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", 3187 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""}; 3188 3189static const char *const arm_fp_const[] = 3190{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"}; 3191 3192static const char *const arm_shift[] = 3193{"lsl", "lsr", "asr", "ror"}; 3194 3195typedef struct 3196{ 3197 const char *name; 3198 const char *description; 3199 const char *reg_names[16]; 3200} 3201arm_regname; 3202 3203static const arm_regname regnames[] = 3204{ 3205 { "raw" , "Select raw register names", 3206 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}}, 3207 { "gcc", "Select register names used by GCC", 3208 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }}, 3209 { "std", "Select register names used in ARM's ISA documentation", 3210 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }}, 3211 { "apcs", "Select register names used in the APCS", 3212 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }}, 3213 { "atpcs", "Select register names used in the ATPCS", 3214 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }}, 3215 { "special-atpcs", "Select special register names used in the ATPCS", 3216 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}, 3217}; 3218 3219static const char *const iwmmxt_wwnames[] = 3220{"b", "h", "w", "d"}; 3221 3222static const char *const iwmmxt_wwssnames[] = 3223{"b", "bus", "bc", "bss", 3224 "h", "hus", "hc", "hss", 3225 "w", "wus", "wc", "wss", 3226 "d", "dus", "dc", "dss" 3227}; 3228 3229static const char *const iwmmxt_regnames[] = 3230{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7", 3231 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15" 3232}; 3233 3234static const char *const iwmmxt_cregnames[] = 3235{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved", 3236 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved" 3237}; 3238 3239/* Default to GCC register name set. */ 3240static unsigned int regname_selected = 1; 3241 3242#define NUM_ARM_REGNAMES NUM_ELEM (regnames) 3243#define arm_regnames regnames[regname_selected].reg_names 3244 3245static bfd_boolean force_thumb = FALSE; 3246 3247/* Current IT instruction state. This contains the same state as the IT 3248 bits in the CPSR. */ 3249static unsigned int ifthen_state; 3250/* IT state for the next instruction. */ 3251static unsigned int ifthen_next_state; 3252/* The address of the insn for which the IT state is valid. */ 3253static bfd_vma ifthen_address; 3254#define IFTHEN_COND ((ifthen_state >> 4) & 0xf) 3255/* Indicates that the current Conditional state is unconditional or outside 3256 an IT block. */ 3257#define COND_UNCOND 16 3258 3259 3260/* Functions. */ 3261int 3262get_arm_regname_num_options (void) 3263{ 3264 return NUM_ARM_REGNAMES; 3265} 3266 3267int 3268set_arm_regname_option (int option) 3269{ 3270 int old = regname_selected; 3271 regname_selected = option; 3272 return old; 3273} 3274 3275int 3276get_arm_regnames (int option, 3277 const char **setname, 3278 const char **setdescription, 3279 const char *const **register_names) 3280{ 3281 *setname = regnames[option].name; 3282 *setdescription = regnames[option].description; 3283 *register_names = regnames[option].reg_names; 3284 return 16; 3285} 3286 3287/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?. 3288 Returns pointer to following character of the format string and 3289 fills in *VALUEP and *WIDTHP with the extracted value and number of 3290 bits extracted. WIDTHP can be NULL. */ 3291 3292static const char * 3293arm_decode_bitfield (const char *ptr, 3294 unsigned long insn, 3295 unsigned long *valuep, 3296 int *widthp) 3297{ 3298 unsigned long value = 0; 3299 int width = 0; 3300 3301 do 3302 { 3303 int start, end; 3304 int bits; 3305 3306 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++) 3307 start = start * 10 + *ptr - '0'; 3308 if (*ptr == '-') 3309 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++) 3310 end = end * 10 + *ptr - '0'; 3311 else 3312 end = start; 3313 bits = end - start; 3314 if (bits < 0) 3315 abort (); 3316 value |= ((insn >> start) & ((2ul << bits) - 1)) << width; 3317 width += bits + 1; 3318 } 3319 while (*ptr++ == ','); 3320 *valuep = value; 3321 if (widthp) 3322 *widthp = width; 3323 return ptr - 1; 3324} 3325 3326static void 3327arm_decode_shift (long given, fprintf_ftype func, void *stream, 3328 bfd_boolean print_shift) 3329{ 3330 func (stream, "%s", arm_regnames[given & 0xf]); 3331 3332 if ((given & 0xff0) != 0) 3333 { 3334 if ((given & 0x10) == 0) 3335 { 3336 int amount = (given & 0xf80) >> 7; 3337 int shift = (given & 0x60) >> 5; 3338 3339 if (amount == 0) 3340 { 3341 if (shift == 3) 3342 { 3343 func (stream, ", rrx"); 3344 return; 3345 } 3346 3347 amount = 32; 3348 } 3349 3350 if (print_shift) 3351 func (stream, ", %s #%d", arm_shift[shift], amount); 3352 else 3353 func (stream, ", #%d", amount); 3354 } 3355 else if ((given & 0x80) == 0x80) 3356 func (stream, "\t; <illegal shifter operand>"); 3357 else if (print_shift) 3358 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5], 3359 arm_regnames[(given & 0xf00) >> 8]); 3360 else 3361 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]); 3362 } 3363} 3364 3365#define W_BIT 21 3366#define I_BIT 22 3367#define U_BIT 23 3368#define P_BIT 24 3369 3370#define WRITEBACK_BIT_SET (given & (1 << W_BIT)) 3371#define IMMEDIATE_BIT_SET (given & (1 << I_BIT)) 3372#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0) 3373#define PRE_BIT_SET (given & (1 << P_BIT)) 3374 3375/* Print one coprocessor instruction on INFO->STREAM. 3376 Return TRUE if the instuction matched, FALSE if this is not a 3377 recognised coprocessor instruction. */ 3378 3379static bfd_boolean 3380print_insn_coprocessor (bfd_vma pc, 3381 struct disassemble_info *info, 3382 long given, 3383 bfd_boolean thumb) 3384{ 3385 const struct opcode32 *insn; 3386 void *stream = info->stream; 3387 fprintf_ftype func = info->fprintf_func; 3388 unsigned long mask; 3389 unsigned long value = 0; 3390 int cond; 3391 int cp_num; 3392 struct arm_private_data *private_data = info->private_data; 3393 arm_feature_set allowed_arches = ARM_ARCH_NONE; 3394 3395 ARM_FEATURE_COPY (allowed_arches, private_data->features); 3396 3397 for (insn = coprocessor_opcodes; insn->assembler; insn++) 3398 { 3399 unsigned long u_reg = 16; 3400 bfd_boolean is_unpredictable = FALSE; 3401 signed long value_in_comment = 0; 3402 const char *c; 3403 3404 if (ARM_FEATURE_ZERO (insn->arch)) 3405 switch (insn->value) 3406 { 3407 case SENTINEL_IWMMXT_START: 3408 if (info->mach != bfd_mach_arm_XScale 3409 && info->mach != bfd_mach_arm_iWMMXt 3410 && info->mach != bfd_mach_arm_iWMMXt2) 3411 do 3412 insn++; 3413 while ((! ARM_FEATURE_ZERO (insn->arch)) 3414 && insn->value != SENTINEL_IWMMXT_END); 3415 continue; 3416 3417 case SENTINEL_IWMMXT_END: 3418 continue; 3419 3420 case SENTINEL_GENERIC_START: 3421 ARM_FEATURE_COPY (allowed_arches, private_data->features); 3422 continue; 3423 3424 default: 3425 abort (); 3426 } 3427 3428 mask = insn->mask; 3429 value = insn->value; 3430 cp_num = (given >> 8) & 0xf; 3431 3432 if (thumb) 3433 { 3434 /* The high 4 bits are 0xe for Arm conditional instructions, and 3435 0xe for arm unconditional instructions. The rest of the 3436 encoding is the same. */ 3437 mask |= 0xf0000000; 3438 value |= 0xe0000000; 3439 if (ifthen_state) 3440 cond = IFTHEN_COND; 3441 else 3442 cond = COND_UNCOND; 3443 } 3444 else 3445 { 3446 /* Only match unconditional instuctions against unconditional 3447 patterns. */ 3448 if ((given & 0xf0000000) == 0xf0000000) 3449 { 3450 mask |= 0xf0000000; 3451 cond = COND_UNCOND; 3452 } 3453 else 3454 { 3455 cond = (given >> 28) & 0xf; 3456 if (cond == 0xe) 3457 cond = COND_UNCOND; 3458 } 3459 } 3460 3461 if ((given & mask) != value) 3462 continue; 3463 3464 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches)) 3465 continue; 3466 3467 if (insn->value == 0xfe000010 /* mcr2 */ 3468 || insn->value == 0xfe100010 /* mrc2 */ 3469 || insn->value == 0xfc100000 /* ldc2 */ 3470 || insn->value == 0xfc000000) /* stc2 */ 3471 { 3472 if (cp_num == 9 || cp_num == 10 || cp_num == 11) 3473 is_unpredictable = TRUE; 3474 } 3475 else if (insn->value == 0x0e000000 /* cdp */ 3476 || insn->value == 0xfe000000 /* cdp2 */ 3477 || insn->value == 0x0e000010 /* mcr */ 3478 || insn->value == 0x0e100010 /* mrc */ 3479 || insn->value == 0x0c100000 /* ldc */ 3480 || insn->value == 0x0c000000) /* stc */ 3481 { 3482 /* Floating-point instructions. */ 3483 if (cp_num == 9 || cp_num == 10 || cp_num == 11) 3484 continue; 3485 } 3486 3487 for (c = insn->assembler; *c; c++) 3488 { 3489 if (*c == '%') 3490 { 3491 switch (*++c) 3492 { 3493 case '%': 3494 func (stream, "%%"); 3495 break; 3496 3497 case 'A': 3498 { 3499 int rn = (given >> 16) & 0xf; 3500 bfd_vma offset = given & 0xff; 3501 3502 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); 3503 3504 if (PRE_BIT_SET || WRITEBACK_BIT_SET) 3505 { 3506 /* Not unindexed. The offset is scaled. */ 3507 if (cp_num == 9) 3508 /* vldr.16/vstr.16 will shift the address 3509 left by 1 bit only. */ 3510 offset = offset * 2; 3511 else 3512 offset = offset * 4; 3513 3514 if (NEGATIVE_BIT_SET) 3515 offset = - offset; 3516 if (rn != 15) 3517 value_in_comment = offset; 3518 } 3519 3520 if (PRE_BIT_SET) 3521 { 3522 if (offset) 3523 func (stream, ", #%d]%s", 3524 (int) offset, 3525 WRITEBACK_BIT_SET ? "!" : ""); 3526 else if (NEGATIVE_BIT_SET) 3527 func (stream, ", #-0]"); 3528 else 3529 func (stream, "]"); 3530 } 3531 else 3532 { 3533 func (stream, "]"); 3534 3535 if (WRITEBACK_BIT_SET) 3536 { 3537 if (offset) 3538 func (stream, ", #%d", (int) offset); 3539 else if (NEGATIVE_BIT_SET) 3540 func (stream, ", #-0"); 3541 } 3542 else 3543 { 3544 func (stream, ", {%s%d}", 3545 (NEGATIVE_BIT_SET && !offset) ? "-" : "", 3546 (int) offset); 3547 value_in_comment = offset; 3548 } 3549 } 3550 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET)) 3551 { 3552 func (stream, "\t; "); 3553 /* For unaligned PCs, apply off-by-alignment 3554 correction. */ 3555 info->print_address_func (offset + pc 3556 + info->bytes_per_chunk * 2 3557 - (pc & 3), 3558 info); 3559 } 3560 } 3561 break; 3562 3563 case 'B': 3564 { 3565 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10); 3566 int offset = (given >> 1) & 0x3f; 3567 3568 if (offset == 1) 3569 func (stream, "{d%d}", regno); 3570 else if (regno + offset > 32) 3571 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1); 3572 else 3573 func (stream, "{d%d-d%d}", regno, regno + offset - 1); 3574 } 3575 break; 3576 3577 case 'u': 3578 if (cond != COND_UNCOND) 3579 is_unpredictable = TRUE; 3580 3581 /* Fall through. */ 3582 case 'c': 3583 if (cond != COND_UNCOND && cp_num == 9) 3584 is_unpredictable = TRUE; 3585 3586 func (stream, "%s", arm_conditional[cond]); 3587 break; 3588 3589 case 'I': 3590 /* Print a Cirrus/DSP shift immediate. */ 3591 /* Immediates are 7bit signed ints with bits 0..3 in 3592 bits 0..3 of opcode and bits 4..6 in bits 5..7 3593 of opcode. */ 3594 { 3595 int imm; 3596 3597 imm = (given & 0xf) | ((given & 0xe0) >> 1); 3598 3599 /* Is ``imm'' a negative number? */ 3600 if (imm & 0x40) 3601 imm -= 0x80; 3602 3603 func (stream, "%d", imm); 3604 } 3605 3606 break; 3607 3608 case 'F': 3609 switch (given & 0x00408000) 3610 { 3611 case 0: 3612 func (stream, "4"); 3613 break; 3614 case 0x8000: 3615 func (stream, "1"); 3616 break; 3617 case 0x00400000: 3618 func (stream, "2"); 3619 break; 3620 default: 3621 func (stream, "3"); 3622 } 3623 break; 3624 3625 case 'P': 3626 switch (given & 0x00080080) 3627 { 3628 case 0: 3629 func (stream, "s"); 3630 break; 3631 case 0x80: 3632 func (stream, "d"); 3633 break; 3634 case 0x00080000: 3635 func (stream, "e"); 3636 break; 3637 default: 3638 func (stream, _("<illegal precision>")); 3639 break; 3640 } 3641 break; 3642 3643 case 'Q': 3644 switch (given & 0x00408000) 3645 { 3646 case 0: 3647 func (stream, "s"); 3648 break; 3649 case 0x8000: 3650 func (stream, "d"); 3651 break; 3652 case 0x00400000: 3653 func (stream, "e"); 3654 break; 3655 default: 3656 func (stream, "p"); 3657 break; 3658 } 3659 break; 3660 3661 case 'R': 3662 switch (given & 0x60) 3663 { 3664 case 0: 3665 break; 3666 case 0x20: 3667 func (stream, "p"); 3668 break; 3669 case 0x40: 3670 func (stream, "m"); 3671 break; 3672 default: 3673 func (stream, "z"); 3674 break; 3675 } 3676 break; 3677 3678 case '0': case '1': case '2': case '3': case '4': 3679 case '5': case '6': case '7': case '8': case '9': 3680 { 3681 int width; 3682 3683 c = arm_decode_bitfield (c, given, &value, &width); 3684 3685 switch (*c) 3686 { 3687 case 'R': 3688 if (value == 15) 3689 is_unpredictable = TRUE; 3690 /* Fall through. */ 3691 case 'r': 3692 if (c[1] == 'u') 3693 { 3694 /* Eat the 'u' character. */ 3695 ++ c; 3696 3697 if (u_reg == value) 3698 is_unpredictable = TRUE; 3699 u_reg = value; 3700 } 3701 func (stream, "%s", arm_regnames[value]); 3702 break; 3703 case 'V': 3704 if (given & (1 << 6)) 3705 goto Q; 3706 /* FALLTHROUGH */ 3707 case 'D': 3708 func (stream, "d%ld", value); 3709 break; 3710 case 'Q': 3711 Q: 3712 if (value & 1) 3713 func (stream, "<illegal reg q%ld.5>", value >> 1); 3714 else 3715 func (stream, "q%ld", value >> 1); 3716 break; 3717 case 'd': 3718 func (stream, "%ld", value); 3719 value_in_comment = value; 3720 break; 3721 case 'E': 3722 { 3723 /* Converts immediate 8 bit back to float value. */ 3724 unsigned floatVal = (value & 0x80) << 24 3725 | (value & 0x3F) << 19 3726 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30)); 3727 3728 /* Quarter float have a maximum value of 31.0. 3729 Get floating point value multiplied by 1e7. 3730 The maximum value stays in limit of a 32-bit int. */ 3731 unsigned decVal = 3732 (78125 << (((floatVal >> 23) & 0xFF) - 124)) * 3733 (16 + (value & 0xF)); 3734 3735 if (!(decVal % 1000000)) 3736 func (stream, "%ld\t; 0x%08x %c%u.%01u", value, 3737 floatVal, value & 0x80 ? '-' : ' ', 3738 decVal / 10000000, 3739 decVal % 10000000 / 1000000); 3740 else if (!(decVal % 10000)) 3741 func (stream, "%ld\t; 0x%08x %c%u.%03u", value, 3742 floatVal, value & 0x80 ? '-' : ' ', 3743 decVal / 10000000, 3744 decVal % 10000000 / 10000); 3745 else 3746 func (stream, "%ld\t; 0x%08x %c%u.%07u", value, 3747 floatVal, value & 0x80 ? '-' : ' ', 3748 decVal / 10000000, decVal % 10000000); 3749 break; 3750 } 3751 case 'k': 3752 { 3753 int from = (given & (1 << 7)) ? 32 : 16; 3754 func (stream, "%ld", from - value); 3755 } 3756 break; 3757 3758 case 'f': 3759 if (value > 7) 3760 func (stream, "#%s", arm_fp_const[value & 7]); 3761 else 3762 func (stream, "f%ld", value); 3763 break; 3764 3765 case 'w': 3766 if (width == 2) 3767 func (stream, "%s", iwmmxt_wwnames[value]); 3768 else 3769 func (stream, "%s", iwmmxt_wwssnames[value]); 3770 break; 3771 3772 case 'g': 3773 func (stream, "%s", iwmmxt_regnames[value]); 3774 break; 3775 case 'G': 3776 func (stream, "%s", iwmmxt_cregnames[value]); 3777 break; 3778 3779 case 'x': 3780 func (stream, "0x%lx", (value & 0xffffffffUL)); 3781 break; 3782 3783 case 'c': 3784 switch (value) 3785 { 3786 case 0: 3787 func (stream, "eq"); 3788 break; 3789 3790 case 1: 3791 func (stream, "vs"); 3792 break; 3793 3794 case 2: 3795 func (stream, "ge"); 3796 break; 3797 3798 case 3: 3799 func (stream, "gt"); 3800 break; 3801 3802 default: 3803 func (stream, "??"); 3804 break; 3805 } 3806 break; 3807 3808 case '`': 3809 c++; 3810 if (value == 0) 3811 func (stream, "%c", *c); 3812 break; 3813 case '\'': 3814 c++; 3815 if (value == ((1ul << width) - 1)) 3816 func (stream, "%c", *c); 3817 break; 3818 case '?': 3819 func (stream, "%c", c[(1 << width) - (int) value]); 3820 c += 1 << width; 3821 break; 3822 default: 3823 abort (); 3824 } 3825 break; 3826 3827 case 'y': 3828 case 'z': 3829 { 3830 int single = *c++ == 'y'; 3831 int regno; 3832 3833 switch (*c) 3834 { 3835 case '4': /* Sm pair */ 3836 case '0': /* Sm, Dm */ 3837 regno = given & 0x0000000f; 3838 if (single) 3839 { 3840 regno <<= 1; 3841 regno += (given >> 5) & 1; 3842 } 3843 else 3844 regno += ((given >> 5) & 1) << 4; 3845 break; 3846 3847 case '1': /* Sd, Dd */ 3848 regno = (given >> 12) & 0x0000000f; 3849 if (single) 3850 { 3851 regno <<= 1; 3852 regno += (given >> 22) & 1; 3853 } 3854 else 3855 regno += ((given >> 22) & 1) << 4; 3856 break; 3857 3858 case '2': /* Sn, Dn */ 3859 regno = (given >> 16) & 0x0000000f; 3860 if (single) 3861 { 3862 regno <<= 1; 3863 regno += (given >> 7) & 1; 3864 } 3865 else 3866 regno += ((given >> 7) & 1) << 4; 3867 break; 3868 3869 case '3': /* List */ 3870 func (stream, "{"); 3871 regno = (given >> 12) & 0x0000000f; 3872 if (single) 3873 { 3874 regno <<= 1; 3875 regno += (given >> 22) & 1; 3876 } 3877 else 3878 regno += ((given >> 22) & 1) << 4; 3879 break; 3880 3881 default: 3882 abort (); 3883 } 3884 3885 func (stream, "%c%d", single ? 's' : 'd', regno); 3886 3887 if (*c == '3') 3888 { 3889 int count = given & 0xff; 3890 3891 if (single == 0) 3892 count >>= 1; 3893 3894 if (--count) 3895 { 3896 func (stream, "-%c%d", 3897 single ? 's' : 'd', 3898 regno + count); 3899 } 3900 3901 func (stream, "}"); 3902 } 3903 else if (*c == '4') 3904 func (stream, ", %c%d", single ? 's' : 'd', 3905 regno + 1); 3906 } 3907 break; 3908 3909 case 'L': 3910 switch (given & 0x00400100) 3911 { 3912 case 0x00000000: func (stream, "b"); break; 3913 case 0x00400000: func (stream, "h"); break; 3914 case 0x00000100: func (stream, "w"); break; 3915 case 0x00400100: func (stream, "d"); break; 3916 default: 3917 break; 3918 } 3919 break; 3920 3921 case 'Z': 3922 { 3923 /* given (20, 23) | given (0, 3) */ 3924 value = ((given >> 16) & 0xf0) | (given & 0xf); 3925 func (stream, "%d", (int) value); 3926 } 3927 break; 3928 3929 case 'l': 3930 /* This is like the 'A' operator, except that if 3931 the width field "M" is zero, then the offset is 3932 *not* multiplied by four. */ 3933 { 3934 int offset = given & 0xff; 3935 int multiplier = (given & 0x00000100) ? 4 : 1; 3936 3937 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); 3938 3939 if (multiplier > 1) 3940 { 3941 value_in_comment = offset * multiplier; 3942 if (NEGATIVE_BIT_SET) 3943 value_in_comment = - value_in_comment; 3944 } 3945 3946 if (offset) 3947 { 3948 if (PRE_BIT_SET) 3949 func (stream, ", #%s%d]%s", 3950 NEGATIVE_BIT_SET ? "-" : "", 3951 offset * multiplier, 3952 WRITEBACK_BIT_SET ? "!" : ""); 3953 else 3954 func (stream, "], #%s%d", 3955 NEGATIVE_BIT_SET ? "-" : "", 3956 offset * multiplier); 3957 } 3958 else 3959 func (stream, "]"); 3960 } 3961 break; 3962 3963 case 'r': 3964 { 3965 int imm4 = (given >> 4) & 0xf; 3966 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1); 3967 int ubit = ! NEGATIVE_BIT_SET; 3968 const char *rm = arm_regnames [given & 0xf]; 3969 const char *rn = arm_regnames [(given >> 16) & 0xf]; 3970 3971 switch (puw_bits) 3972 { 3973 case 1: 3974 case 3: 3975 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm); 3976 if (imm4) 3977 func (stream, ", lsl #%d", imm4); 3978 break; 3979 3980 case 4: 3981 case 5: 3982 case 6: 3983 case 7: 3984 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm); 3985 if (imm4 > 0) 3986 func (stream, ", lsl #%d", imm4); 3987 func (stream, "]"); 3988 if (puw_bits == 5 || puw_bits == 7) 3989 func (stream, "!"); 3990 break; 3991 3992 default: 3993 func (stream, "INVALID"); 3994 } 3995 } 3996 break; 3997 3998 case 'i': 3999 { 4000 long imm5; 4001 imm5 = ((given & 0x100) >> 4) | (given & 0xf); 4002 func (stream, "%ld", (imm5 == 0) ? 32 : imm5); 4003 } 4004 break; 4005 4006 default: 4007 abort (); 4008 } 4009 } 4010 } 4011 else 4012 func (stream, "%c", *c); 4013 } 4014 4015 if (value_in_comment > 32 || value_in_comment < -16) 4016 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL)); 4017 4018 if (is_unpredictable) 4019 func (stream, UNPREDICTABLE_INSTRUCTION); 4020 4021 return TRUE; 4022 } 4023 return FALSE; 4024} 4025 4026/* Decodes and prints ARM addressing modes. Returns the offset 4027 used in the address, if any, if it is worthwhile printing the 4028 offset as a hexadecimal value in a comment at the end of the 4029 line of disassembly. */ 4030 4031static signed long 4032print_arm_address (bfd_vma pc, struct disassemble_info *info, long given) 4033{ 4034 void *stream = info->stream; 4035 fprintf_ftype func = info->fprintf_func; 4036 bfd_vma offset = 0; 4037 4038 if (((given & 0x000f0000) == 0x000f0000) 4039 && ((given & 0x02000000) == 0)) 4040 { 4041 offset = given & 0xfff; 4042 4043 func (stream, "[pc"); 4044 4045 if (PRE_BIT_SET) 4046 { 4047 /* Pre-indexed. Elide offset of positive zero when 4048 non-writeback. */ 4049 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset) 4050 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset); 4051 4052 if (NEGATIVE_BIT_SET) 4053 offset = -offset; 4054 4055 offset += pc + 8; 4056 4057 /* Cope with the possibility of write-back 4058 being used. Probably a very dangerous thing 4059 for the programmer to do, but who are we to 4060 argue ? */ 4061 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : ""); 4062 } 4063 else /* Post indexed. */ 4064 { 4065 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset); 4066 4067 /* Ie ignore the offset. */ 4068 offset = pc + 8; 4069 } 4070 4071 func (stream, "\t; "); 4072 info->print_address_func (offset, info); 4073 offset = 0; 4074 } 4075 else 4076 { 4077 func (stream, "[%s", 4078 arm_regnames[(given >> 16) & 0xf]); 4079 4080 if (PRE_BIT_SET) 4081 { 4082 if ((given & 0x02000000) == 0) 4083 { 4084 /* Elide offset of positive zero when non-writeback. */ 4085 offset = given & 0xfff; 4086 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset) 4087 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset); 4088 } 4089 else 4090 { 4091 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : ""); 4092 arm_decode_shift (given, func, stream, TRUE); 4093 } 4094 4095 func (stream, "]%s", 4096 WRITEBACK_BIT_SET ? "!" : ""); 4097 } 4098 else 4099 { 4100 if ((given & 0x02000000) == 0) 4101 { 4102 /* Always show offset. */ 4103 offset = given & 0xfff; 4104 func (stream, "], #%s%d", 4105 NEGATIVE_BIT_SET ? "-" : "", (int) offset); 4106 } 4107 else 4108 { 4109 func (stream, "], %s", 4110 NEGATIVE_BIT_SET ? "-" : ""); 4111 arm_decode_shift (given, func, stream, TRUE); 4112 } 4113 } 4114 if (NEGATIVE_BIT_SET) 4115 offset = -offset; 4116 } 4117 4118 return (signed long) offset; 4119} 4120 4121/* Print one neon instruction on INFO->STREAM. 4122 Return TRUE if the instuction matched, FALSE if this is not a 4123 recognised neon instruction. */ 4124 4125static bfd_boolean 4126print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) 4127{ 4128 const struct opcode32 *insn; 4129 void *stream = info->stream; 4130 fprintf_ftype func = info->fprintf_func; 4131 4132 if (thumb) 4133 { 4134 if ((given & 0xef000000) == 0xef000000) 4135 { 4136 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */ 4137 unsigned long bit28 = given & (1 << 28); 4138 4139 given &= 0x00ffffff; 4140 if (bit28) 4141 given |= 0xf3000000; 4142 else 4143 given |= 0xf2000000; 4144 } 4145 else if ((given & 0xff000000) == 0xf9000000) 4146 given ^= 0xf9000000 ^ 0xf4000000; 4147 else 4148 return FALSE; 4149 } 4150 4151 for (insn = neon_opcodes; insn->assembler; insn++) 4152 { 4153 if ((given & insn->mask) == insn->value) 4154 { 4155 signed long value_in_comment = 0; 4156 bfd_boolean is_unpredictable = FALSE; 4157 const char *c; 4158 4159 for (c = insn->assembler; *c; c++) 4160 { 4161 if (*c == '%') 4162 { 4163 switch (*++c) 4164 { 4165 case '%': 4166 func (stream, "%%"); 4167 break; 4168 4169 case 'u': 4170 if (thumb && ifthen_state) 4171 is_unpredictable = TRUE; 4172 4173 /* Fall through. */ 4174 case 'c': 4175 if (thumb && ifthen_state) 4176 func (stream, "%s", arm_conditional[IFTHEN_COND]); 4177 break; 4178 4179 case 'A': 4180 { 4181 static const unsigned char enc[16] = 4182 { 4183 0x4, 0x14, /* st4 0,1 */ 4184 0x4, /* st1 2 */ 4185 0x4, /* st2 3 */ 4186 0x3, /* st3 4 */ 4187 0x13, /* st3 5 */ 4188 0x3, /* st1 6 */ 4189 0x1, /* st1 7 */ 4190 0x2, /* st2 8 */ 4191 0x12, /* st2 9 */ 4192 0x2, /* st1 10 */ 4193 0, 0, 0, 0, 0 4194 }; 4195 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4); 4196 int rn = ((given >> 16) & 0xf); 4197 int rm = ((given >> 0) & 0xf); 4198 int align = ((given >> 4) & 0x3); 4199 int type = ((given >> 8) & 0xf); 4200 int n = enc[type] & 0xf; 4201 int stride = (enc[type] >> 4) + 1; 4202 int ix; 4203 4204 func (stream, "{"); 4205 if (stride > 1) 4206 for (ix = 0; ix != n; ix++) 4207 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride); 4208 else if (n == 1) 4209 func (stream, "d%d", rd); 4210 else 4211 func (stream, "d%d-d%d", rd, rd + n - 1); 4212 func (stream, "}, [%s", arm_regnames[rn]); 4213 if (align) 4214 func (stream, " :%d", 32 << align); 4215 func (stream, "]"); 4216 if (rm == 0xd) 4217 func (stream, "!"); 4218 else if (rm != 0xf) 4219 func (stream, ", %s", arm_regnames[rm]); 4220 } 4221 break; 4222 4223 case 'B': 4224 { 4225 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4); 4226 int rn = ((given >> 16) & 0xf); 4227 int rm = ((given >> 0) & 0xf); 4228 int idx_align = ((given >> 4) & 0xf); 4229 int align = 0; 4230 int size = ((given >> 10) & 0x3); 4231 int idx = idx_align >> (size + 1); 4232 int length = ((given >> 8) & 3) + 1; 4233 int stride = 1; 4234 int i; 4235 4236 if (length > 1 && size > 0) 4237 stride = (idx_align & (1 << size)) ? 2 : 1; 4238 4239 switch (length) 4240 { 4241 case 1: 4242 { 4243 int amask = (1 << size) - 1; 4244 if ((idx_align & (1 << size)) != 0) 4245 return FALSE; 4246 if (size > 0) 4247 { 4248 if ((idx_align & amask) == amask) 4249 align = 8 << size; 4250 else if ((idx_align & amask) != 0) 4251 return FALSE; 4252 } 4253 } 4254 break; 4255 4256 case 2: 4257 if (size == 2 && (idx_align & 2) != 0) 4258 return FALSE; 4259 align = (idx_align & 1) ? 16 << size : 0; 4260 break; 4261 4262 case 3: 4263 if ((size == 2 && (idx_align & 3) != 0) 4264 || (idx_align & 1) != 0) 4265 return FALSE; 4266 break; 4267 4268 case 4: 4269 if (size == 2) 4270 { 4271 if ((idx_align & 3) == 3) 4272 return FALSE; 4273 align = (idx_align & 3) * 64; 4274 } 4275 else 4276 align = (idx_align & 1) ? 32 << size : 0; 4277 break; 4278 4279 default: 4280 abort (); 4281 } 4282 4283 func (stream, "{"); 4284 for (i = 0; i < length; i++) 4285 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",", 4286 rd + i * stride, idx); 4287 func (stream, "}, [%s", arm_regnames[rn]); 4288 if (align) 4289 func (stream, " :%d", align); 4290 func (stream, "]"); 4291 if (rm == 0xd) 4292 func (stream, "!"); 4293 else if (rm != 0xf) 4294 func (stream, ", %s", arm_regnames[rm]); 4295 } 4296 break; 4297 4298 case 'C': 4299 { 4300 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4); 4301 int rn = ((given >> 16) & 0xf); 4302 int rm = ((given >> 0) & 0xf); 4303 int align = ((given >> 4) & 0x1); 4304 int size = ((given >> 6) & 0x3); 4305 int type = ((given >> 8) & 0x3); 4306 int n = type + 1; 4307 int stride = ((given >> 5) & 0x1); 4308 int ix; 4309 4310 if (stride && (n == 1)) 4311 n++; 4312 else 4313 stride++; 4314 4315 func (stream, "{"); 4316 if (stride > 1) 4317 for (ix = 0; ix != n; ix++) 4318 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride); 4319 else if (n == 1) 4320 func (stream, "d%d[]", rd); 4321 else 4322 func (stream, "d%d[]-d%d[]", rd, rd + n - 1); 4323 func (stream, "}, [%s", arm_regnames[rn]); 4324 if (align) 4325 { 4326 align = (8 * (type + 1)) << size; 4327 if (type == 3) 4328 align = (size > 1) ? align >> 1 : align; 4329 if (type == 2 || (type == 0 && !size)) 4330 func (stream, " :<bad align %d>", align); 4331 else 4332 func (stream, " :%d", align); 4333 } 4334 func (stream, "]"); 4335 if (rm == 0xd) 4336 func (stream, "!"); 4337 else if (rm != 0xf) 4338 func (stream, ", %s", arm_regnames[rm]); 4339 } 4340 break; 4341 4342 case 'D': 4343 { 4344 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10); 4345 int size = (given >> 20) & 3; 4346 int reg = raw_reg & ((4 << size) - 1); 4347 int ix = raw_reg >> size >> 2; 4348 4349 func (stream, "d%d[%d]", reg, ix); 4350 } 4351 break; 4352 4353 case 'E': 4354 /* Neon encoded constant for mov, mvn, vorr, vbic. */ 4355 { 4356 int bits = 0; 4357 int cmode = (given >> 8) & 0xf; 4358 int op = (given >> 5) & 0x1; 4359 unsigned long value = 0, hival = 0; 4360 unsigned shift; 4361 int size = 0; 4362 int isfloat = 0; 4363 4364 bits |= ((given >> 24) & 1) << 7; 4365 bits |= ((given >> 16) & 7) << 4; 4366 bits |= ((given >> 0) & 15) << 0; 4367 4368 if (cmode < 8) 4369 { 4370 shift = (cmode >> 1) & 3; 4371 value = (unsigned long) bits << (8 * shift); 4372 size = 32; 4373 } 4374 else if (cmode < 12) 4375 { 4376 shift = (cmode >> 1) & 1; 4377 value = (unsigned long) bits << (8 * shift); 4378 size = 16; 4379 } 4380 else if (cmode < 14) 4381 { 4382 shift = (cmode & 1) + 1; 4383 value = (unsigned long) bits << (8 * shift); 4384 value |= (1ul << (8 * shift)) - 1; 4385 size = 32; 4386 } 4387 else if (cmode == 14) 4388 { 4389 if (op) 4390 { 4391 /* Bit replication into bytes. */ 4392 int ix; 4393 unsigned long mask; 4394 4395 value = 0; 4396 hival = 0; 4397 for (ix = 7; ix >= 0; ix--) 4398 { 4399 mask = ((bits >> ix) & 1) ? 0xff : 0; 4400 if (ix <= 3) 4401 value = (value << 8) | mask; 4402 else 4403 hival = (hival << 8) | mask; 4404 } 4405 size = 64; 4406 } 4407 else 4408 { 4409 /* Byte replication. */ 4410 value = (unsigned long) bits; 4411 size = 8; 4412 } 4413 } 4414 else if (!op) 4415 { 4416 /* Floating point encoding. */ 4417 int tmp; 4418 4419 value = (unsigned long) (bits & 0x7f) << 19; 4420 value |= (unsigned long) (bits & 0x80) << 24; 4421 tmp = bits & 0x40 ? 0x3c : 0x40; 4422 value |= (unsigned long) tmp << 24; 4423 size = 32; 4424 isfloat = 1; 4425 } 4426 else 4427 { 4428 func (stream, "<illegal constant %.8x:%x:%x>", 4429 bits, cmode, op); 4430 size = 32; 4431 break; 4432 } 4433 switch (size) 4434 { 4435 case 8: 4436 func (stream, "#%ld\t; 0x%.2lx", value, value); 4437 break; 4438 4439 case 16: 4440 func (stream, "#%ld\t; 0x%.4lx", value, value); 4441 break; 4442 4443 case 32: 4444 if (isfloat) 4445 { 4446 unsigned char valbytes[4]; 4447 double fvalue; 4448 4449 /* Do this a byte at a time so we don't have to 4450 worry about the host's endianness. */ 4451 valbytes[0] = value & 0xff; 4452 valbytes[1] = (value >> 8) & 0xff; 4453 valbytes[2] = (value >> 16) & 0xff; 4454 valbytes[3] = (value >> 24) & 0xff; 4455 4456 floatformat_to_double 4457 (& floatformat_ieee_single_little, valbytes, 4458 & fvalue); 4459 4460 func (stream, "#%.7g\t; 0x%.8lx", fvalue, 4461 value); 4462 } 4463 else 4464 func (stream, "#%ld\t; 0x%.8lx", 4465 (long) (((value & 0x80000000L) != 0) 4466 ? value | ~0xffffffffL : value), 4467 value); 4468 break; 4469 4470 case 64: 4471 func (stream, "#0x%.8lx%.8lx", hival, value); 4472 break; 4473 4474 default: 4475 abort (); 4476 } 4477 } 4478 break; 4479 4480 case 'F': 4481 { 4482 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10); 4483 int num = (given >> 8) & 0x3; 4484 4485 if (!num) 4486 func (stream, "{d%d}", regno); 4487 else if (num + regno >= 32) 4488 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num); 4489 else 4490 func (stream, "{d%d-d%d}", regno, regno + num); 4491 } 4492 break; 4493 4494 4495 case '0': case '1': case '2': case '3': case '4': 4496 case '5': case '6': case '7': case '8': case '9': 4497 { 4498 int width; 4499 unsigned long value; 4500 4501 c = arm_decode_bitfield (c, given, &value, &width); 4502 4503 switch (*c) 4504 { 4505 case 'r': 4506 func (stream, "%s", arm_regnames[value]); 4507 break; 4508 case 'd': 4509 func (stream, "%ld", value); 4510 value_in_comment = value; 4511 break; 4512 case 'e': 4513 func (stream, "%ld", (1ul << width) - value); 4514 break; 4515 4516 case 'S': 4517 case 'T': 4518 case 'U': 4519 /* Various width encodings. */ 4520 { 4521 int base = 8 << (*c - 'S'); /* 8,16 or 32 */ 4522 int limit; 4523 unsigned low, high; 4524 4525 c++; 4526 if (*c >= '0' && *c <= '9') 4527 limit = *c - '0'; 4528 else if (*c >= 'a' && *c <= 'f') 4529 limit = *c - 'a' + 10; 4530 else 4531 abort (); 4532 low = limit >> 2; 4533 high = limit & 3; 4534 4535 if (value < low || value > high) 4536 func (stream, "<illegal width %d>", base << value); 4537 else 4538 func (stream, "%d", base << value); 4539 } 4540 break; 4541 case 'R': 4542 if (given & (1 << 6)) 4543 goto Q; 4544 /* FALLTHROUGH */ 4545 case 'D': 4546 func (stream, "d%ld", value); 4547 break; 4548 case 'Q': 4549 Q: 4550 if (value & 1) 4551 func (stream, "<illegal reg q%ld.5>", value >> 1); 4552 else 4553 func (stream, "q%ld", value >> 1); 4554 break; 4555 4556 case '`': 4557 c++; 4558 if (value == 0) 4559 func (stream, "%c", *c); 4560 break; 4561 case '\'': 4562 c++; 4563 if (value == ((1ul << width) - 1)) 4564 func (stream, "%c", *c); 4565 break; 4566 case '?': 4567 func (stream, "%c", c[(1 << width) - (int) value]); 4568 c += 1 << width; 4569 break; 4570 default: 4571 abort (); 4572 } 4573 break; 4574 4575 default: 4576 abort (); 4577 } 4578 } 4579 } 4580 else 4581 func (stream, "%c", *c); 4582 } 4583 4584 if (value_in_comment > 32 || value_in_comment < -16) 4585 func (stream, "\t; 0x%lx", value_in_comment); 4586 4587 if (is_unpredictable) 4588 func (stream, UNPREDICTABLE_INSTRUCTION); 4589 4590 return TRUE; 4591 } 4592 } 4593 return FALSE; 4594} 4595 4596/* Return the name of a v7A special register. */ 4597 4598static const char * 4599banked_regname (unsigned reg) 4600{ 4601 switch (reg) 4602 { 4603 case 15: return "CPSR"; 4604 case 32: return "R8_usr"; 4605 case 33: return "R9_usr"; 4606 case 34: return "R10_usr"; 4607 case 35: return "R11_usr"; 4608 case 36: return "R12_usr"; 4609 case 37: return "SP_usr"; 4610 case 38: return "LR_usr"; 4611 case 40: return "R8_fiq"; 4612 case 41: return "R9_fiq"; 4613 case 42: return "R10_fiq"; 4614 case 43: return "R11_fiq"; 4615 case 44: return "R12_fiq"; 4616 case 45: return "SP_fiq"; 4617 case 46: return "LR_fiq"; 4618 case 48: return "LR_irq"; 4619 case 49: return "SP_irq"; 4620 case 50: return "LR_svc"; 4621 case 51: return "SP_svc"; 4622 case 52: return "LR_abt"; 4623 case 53: return "SP_abt"; 4624 case 54: return "LR_und"; 4625 case 55: return "SP_und"; 4626 case 60: return "LR_mon"; 4627 case 61: return "SP_mon"; 4628 case 62: return "ELR_hyp"; 4629 case 63: return "SP_hyp"; 4630 case 79: return "SPSR"; 4631 case 110: return "SPSR_fiq"; 4632 case 112: return "SPSR_irq"; 4633 case 114: return "SPSR_svc"; 4634 case 116: return "SPSR_abt"; 4635 case 118: return "SPSR_und"; 4636 case 124: return "SPSR_mon"; 4637 case 126: return "SPSR_hyp"; 4638 default: return NULL; 4639 } 4640} 4641 4642/* Return the name of the DMB/DSB option. */ 4643static const char * 4644data_barrier_option (unsigned option) 4645{ 4646 switch (option & 0xf) 4647 { 4648 case 0xf: return "sy"; 4649 case 0xe: return "st"; 4650 case 0xd: return "ld"; 4651 case 0xb: return "ish"; 4652 case 0xa: return "ishst"; 4653 case 0x9: return "ishld"; 4654 case 0x7: return "un"; 4655 case 0x6: return "unst"; 4656 case 0x5: return "nshld"; 4657 case 0x3: return "osh"; 4658 case 0x2: return "oshst"; 4659 case 0x1: return "oshld"; 4660 default: return NULL; 4661 } 4662} 4663 4664/* Print one ARM instruction from PC on INFO->STREAM. */ 4665 4666static void 4667print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) 4668{ 4669 const struct opcode32 *insn; 4670 void *stream = info->stream; 4671 fprintf_ftype func = info->fprintf_func; 4672 struct arm_private_data *private_data = info->private_data; 4673 4674 if (print_insn_coprocessor (pc, info, given, FALSE)) 4675 return; 4676 4677 if (print_insn_neon (info, given, FALSE)) 4678 return; 4679 4680 for (insn = arm_opcodes; insn->assembler; insn++) 4681 { 4682 if ((given & insn->mask) != insn->value) 4683 continue; 4684 4685 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features)) 4686 continue; 4687 4688 /* Special case: an instruction with all bits set in the condition field 4689 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask, 4690 or by the catchall at the end of the table. */ 4691 if ((given & 0xF0000000) != 0xF0000000 4692 || (insn->mask & 0xF0000000) == 0xF0000000 4693 || (insn->mask == 0 && insn->value == 0)) 4694 { 4695 unsigned long u_reg = 16; 4696 unsigned long U_reg = 16; 4697 bfd_boolean is_unpredictable = FALSE; 4698 signed long value_in_comment = 0; 4699 const char *c; 4700 4701 for (c = insn->assembler; *c; c++) 4702 { 4703 if (*c == '%') 4704 { 4705 bfd_boolean allow_unpredictable = FALSE; 4706 4707 switch (*++c) 4708 { 4709 case '%': 4710 func (stream, "%%"); 4711 break; 4712 4713 case 'a': 4714 value_in_comment = print_arm_address (pc, info, given); 4715 break; 4716 4717 case 'P': 4718 /* Set P address bit and use normal address 4719 printing routine. */ 4720 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT)); 4721 break; 4722 4723 case 'S': 4724 allow_unpredictable = TRUE; 4725 /* Fall through. */ 4726 case 's': 4727 if ((given & 0x004f0000) == 0x004f0000) 4728 { 4729 /* PC relative with immediate offset. */ 4730 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf); 4731 4732 if (PRE_BIT_SET) 4733 { 4734 /* Elide positive zero offset. */ 4735 if (offset || NEGATIVE_BIT_SET) 4736 func (stream, "[pc, #%s%d]\t; ", 4737 NEGATIVE_BIT_SET ? "-" : "", (int) offset); 4738 else 4739 func (stream, "[pc]\t; "); 4740 if (NEGATIVE_BIT_SET) 4741 offset = -offset; 4742 info->print_address_func (offset + pc + 8, info); 4743 } 4744 else 4745 { 4746 /* Always show the offset. */ 4747 func (stream, "[pc], #%s%d", 4748 NEGATIVE_BIT_SET ? "-" : "", (int) offset); 4749 if (! allow_unpredictable) 4750 is_unpredictable = TRUE; 4751 } 4752 } 4753 else 4754 { 4755 int offset = ((given & 0xf00) >> 4) | (given & 0xf); 4756 4757 func (stream, "[%s", 4758 arm_regnames[(given >> 16) & 0xf]); 4759 4760 if (PRE_BIT_SET) 4761 { 4762 if (IMMEDIATE_BIT_SET) 4763 { 4764 /* Elide offset for non-writeback 4765 positive zero. */ 4766 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET 4767 || offset) 4768 func (stream, ", #%s%d", 4769 NEGATIVE_BIT_SET ? "-" : "", offset); 4770 4771 if (NEGATIVE_BIT_SET) 4772 offset = -offset; 4773 4774 value_in_comment = offset; 4775 } 4776 else 4777 { 4778 /* Register Offset or Register Pre-Indexed. */ 4779 func (stream, ", %s%s", 4780 NEGATIVE_BIT_SET ? "-" : "", 4781 arm_regnames[given & 0xf]); 4782 4783 /* Writing back to the register that is the source/ 4784 destination of the load/store is unpredictable. */ 4785 if (! allow_unpredictable 4786 && WRITEBACK_BIT_SET 4787 && ((given & 0xf) == ((given >> 12) & 0xf))) 4788 is_unpredictable = TRUE; 4789 } 4790 4791 func (stream, "]%s", 4792 WRITEBACK_BIT_SET ? "!" : ""); 4793 } 4794 else 4795 { 4796 if (IMMEDIATE_BIT_SET) 4797 { 4798 /* Immediate Post-indexed. */ 4799 /* PR 10924: Offset must be printed, even if it is zero. */ 4800 func (stream, "], #%s%d", 4801 NEGATIVE_BIT_SET ? "-" : "", offset); 4802 if (NEGATIVE_BIT_SET) 4803 offset = -offset; 4804 value_in_comment = offset; 4805 } 4806 else 4807 { 4808 /* Register Post-indexed. */ 4809 func (stream, "], %s%s", 4810 NEGATIVE_BIT_SET ? "-" : "", 4811 arm_regnames[given & 0xf]); 4812 4813 /* Writing back to the register that is the source/ 4814 destination of the load/store is unpredictable. */ 4815 if (! allow_unpredictable 4816 && (given & 0xf) == ((given >> 12) & 0xf)) 4817 is_unpredictable = TRUE; 4818 } 4819 4820 if (! allow_unpredictable) 4821 { 4822 /* Writeback is automatically implied by post- addressing. 4823 Setting the W bit is unnecessary and ARM specify it as 4824 being unpredictable. */ 4825 if (WRITEBACK_BIT_SET 4826 /* Specifying the PC register as the post-indexed 4827 registers is also unpredictable. */ 4828 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf))) 4829 is_unpredictable = TRUE; 4830 } 4831 } 4832 } 4833 break; 4834 4835 case 'b': 4836 { 4837 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000); 4838 info->print_address_func (disp * 4 + pc + 8, info); 4839 } 4840 break; 4841 4842 case 'c': 4843 if (((given >> 28) & 0xf) != 0xe) 4844 func (stream, "%s", 4845 arm_conditional [(given >> 28) & 0xf]); 4846 break; 4847 4848 case 'm': 4849 { 4850 int started = 0; 4851 int reg; 4852 4853 func (stream, "{"); 4854 for (reg = 0; reg < 16; reg++) 4855 if ((given & (1 << reg)) != 0) 4856 { 4857 if (started) 4858 func (stream, ", "); 4859 started = 1; 4860 func (stream, "%s", arm_regnames[reg]); 4861 } 4862 func (stream, "}"); 4863 if (! started) 4864 is_unpredictable = TRUE; 4865 } 4866 break; 4867 4868 case 'q': 4869 arm_decode_shift (given, func, stream, FALSE); 4870 break; 4871 4872 case 'o': 4873 if ((given & 0x02000000) != 0) 4874 { 4875 unsigned int rotate = (given & 0xf00) >> 7; 4876 unsigned int immed = (given & 0xff); 4877 unsigned int a, i; 4878 4879 a = (((immed << (32 - rotate)) 4880 | (immed >> rotate)) & 0xffffffff); 4881 /* If there is another encoding with smaller rotate, 4882 the rotate should be specified directly. */ 4883 for (i = 0; i < 32; i += 2) 4884 if ((a << i | a >> (32 - i)) <= 0xff) 4885 break; 4886 4887 if (i != rotate) 4888 func (stream, "#%d, %d", immed, rotate); 4889 else 4890 func (stream, "#%d", a); 4891 value_in_comment = a; 4892 } 4893 else 4894 arm_decode_shift (given, func, stream, TRUE); 4895 break; 4896 4897 case 'p': 4898 if ((given & 0x0000f000) == 0x0000f000) 4899 { 4900 arm_feature_set arm_ext_v6 = 4901 ARM_FEATURE_CORE_LOW (ARM_EXT_V6); 4902 4903 /* The p-variants of tst/cmp/cmn/teq are the pre-V6 4904 mechanism for setting PSR flag bits. They are 4905 obsolete in V6 onwards. */ 4906 if (! ARM_CPU_HAS_FEATURE (private_data->features, \ 4907 arm_ext_v6)) 4908 func (stream, "p"); 4909 else 4910 is_unpredictable = TRUE; 4911 } 4912 break; 4913 4914 case 't': 4915 if ((given & 0x01200000) == 0x00200000) 4916 func (stream, "t"); 4917 break; 4918 4919 case 'A': 4920 { 4921 int offset = given & 0xff; 4922 4923 value_in_comment = offset * 4; 4924 if (NEGATIVE_BIT_SET) 4925 value_in_comment = - value_in_comment; 4926 4927 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); 4928 4929 if (PRE_BIT_SET) 4930 { 4931 if (offset) 4932 func (stream, ", #%d]%s", 4933 (int) value_in_comment, 4934 WRITEBACK_BIT_SET ? "!" : ""); 4935 else 4936 func (stream, "]"); 4937 } 4938 else 4939 { 4940 func (stream, "]"); 4941 4942 if (WRITEBACK_BIT_SET) 4943 { 4944 if (offset) 4945 func (stream, ", #%d", (int) value_in_comment); 4946 } 4947 else 4948 { 4949 func (stream, ", {%d}", (int) offset); 4950 value_in_comment = offset; 4951 } 4952 } 4953 } 4954 break; 4955 4956 case 'B': 4957 /* Print ARM V5 BLX(1) address: pc+25 bits. */ 4958 { 4959 bfd_vma address; 4960 bfd_vma offset = 0; 4961 4962 if (! NEGATIVE_BIT_SET) 4963 /* Is signed, hi bits should be ones. */ 4964 offset = (-1) ^ 0x00ffffff; 4965 4966 /* Offset is (SignExtend(offset field)<<2). */ 4967 offset += given & 0x00ffffff; 4968 offset <<= 2; 4969 address = offset + pc + 8; 4970 4971 if (given & 0x01000000) 4972 /* H bit allows addressing to 2-byte boundaries. */ 4973 address += 2; 4974 4975 info->print_address_func (address, info); 4976 } 4977 break; 4978 4979 case 'C': 4980 if ((given & 0x02000200) == 0x200) 4981 { 4982 const char * name; 4983 unsigned sysm = (given & 0x004f0000) >> 16; 4984 4985 sysm |= (given & 0x300) >> 4; 4986 name = banked_regname (sysm); 4987 4988 if (name != NULL) 4989 func (stream, "%s", name); 4990 else 4991 func (stream, "(UNDEF: %lu)", (unsigned long) sysm); 4992 } 4993 else 4994 { 4995 func (stream, "%cPSR_", 4996 (given & 0x00400000) ? 'S' : 'C'); 4997 if (given & 0x80000) 4998 func (stream, "f"); 4999 if (given & 0x40000) 5000 func (stream, "s"); 5001 if (given & 0x20000) 5002 func (stream, "x"); 5003 if (given & 0x10000) 5004 func (stream, "c"); 5005 } 5006 break; 5007 5008 case 'U': 5009 if ((given & 0xf0) == 0x60) 5010 { 5011 switch (given & 0xf) 5012 { 5013 case 0xf: func (stream, "sy"); break; 5014 default: 5015 func (stream, "#%d", (int) given & 0xf); 5016 break; 5017 } 5018 } 5019 else 5020 { 5021 const char * opt = data_barrier_option (given & 0xf); 5022 if (opt != NULL) 5023 func (stream, "%s", opt); 5024 else 5025 func (stream, "#%d", (int) given & 0xf); 5026 } 5027 break; 5028 5029 case '0': case '1': case '2': case '3': case '4': 5030 case '5': case '6': case '7': case '8': case '9': 5031 { 5032 int width; 5033 unsigned long value; 5034 5035 c = arm_decode_bitfield (c, given, &value, &width); 5036 5037 switch (*c) 5038 { 5039 case 'R': 5040 if (value == 15) 5041 is_unpredictable = TRUE; 5042 /* Fall through. */ 5043 case 'r': 5044 case 'T': 5045 /* We want register + 1 when decoding T. */ 5046 if (*c == 'T') 5047 ++value; 5048 5049 if (c[1] == 'u') 5050 { 5051 /* Eat the 'u' character. */ 5052 ++ c; 5053 5054 if (u_reg == value) 5055 is_unpredictable = TRUE; 5056 u_reg = value; 5057 } 5058 if (c[1] == 'U') 5059 { 5060 /* Eat the 'U' character. */ 5061 ++ c; 5062 5063 if (U_reg == value) 5064 is_unpredictable = TRUE; 5065 U_reg = value; 5066 } 5067 func (stream, "%s", arm_regnames[value]); 5068 break; 5069 case 'd': 5070 func (stream, "%ld", value); 5071 value_in_comment = value; 5072 break; 5073 case 'b': 5074 func (stream, "%ld", value * 8); 5075 value_in_comment = value * 8; 5076 break; 5077 case 'W': 5078 func (stream, "%ld", value + 1); 5079 value_in_comment = value + 1; 5080 break; 5081 case 'x': 5082 func (stream, "0x%08lx", value); 5083 5084 /* Some SWI instructions have special 5085 meanings. */ 5086 if ((given & 0x0fffffff) == 0x0FF00000) 5087 func (stream, "\t; IMB"); 5088 else if ((given & 0x0fffffff) == 0x0FF00001) 5089 func (stream, "\t; IMBRange"); 5090 break; 5091 case 'X': 5092 func (stream, "%01lx", value & 0xf); 5093 value_in_comment = value; 5094 break; 5095 case '`': 5096 c++; 5097 if (value == 0) 5098 func (stream, "%c", *c); 5099 break; 5100 case '\'': 5101 c++; 5102 if (value == ((1ul << width) - 1)) 5103 func (stream, "%c", *c); 5104 break; 5105 case '?': 5106 func (stream, "%c", c[(1 << width) - (int) value]); 5107 c += 1 << width; 5108 break; 5109 default: 5110 abort (); 5111 } 5112 break; 5113 5114 case 'e': 5115 { 5116 int imm; 5117 5118 imm = (given & 0xf) | ((given & 0xfff00) >> 4); 5119 func (stream, "%d", imm); 5120 value_in_comment = imm; 5121 } 5122 break; 5123 5124 case 'E': 5125 /* LSB and WIDTH fields of BFI or BFC. The machine- 5126 language instruction encodes LSB and MSB. */ 5127 { 5128 long msb = (given & 0x001f0000) >> 16; 5129 long lsb = (given & 0x00000f80) >> 7; 5130 long w = msb - lsb + 1; 5131 5132 if (w > 0) 5133 func (stream, "#%lu, #%lu", lsb, w); 5134 else 5135 func (stream, "(invalid: %lu:%lu)", lsb, msb); 5136 } 5137 break; 5138 5139 case 'R': 5140 /* Get the PSR/banked register name. */ 5141 { 5142 const char * name; 5143 unsigned sysm = (given & 0x004f0000) >> 16; 5144 5145 sysm |= (given & 0x300) >> 4; 5146 name = banked_regname (sysm); 5147 5148 if (name != NULL) 5149 func (stream, "%s", name); 5150 else 5151 func (stream, "(UNDEF: %lu)", (unsigned long) sysm); 5152 } 5153 break; 5154 5155 case 'V': 5156 /* 16-bit unsigned immediate from a MOVT or MOVW 5157 instruction, encoded in bits 0:11 and 15:19. */ 5158 { 5159 long hi = (given & 0x000f0000) >> 4; 5160 long lo = (given & 0x00000fff); 5161 long imm16 = hi | lo; 5162 5163 func (stream, "#%lu", imm16); 5164 value_in_comment = imm16; 5165 } 5166 break; 5167 5168 default: 5169 abort (); 5170 } 5171 } 5172 } 5173 else 5174 func (stream, "%c", *c); 5175 } 5176 5177 if (value_in_comment > 32 || value_in_comment < -16) 5178 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL)); 5179 5180 if (is_unpredictable) 5181 func (stream, UNPREDICTABLE_INSTRUCTION); 5182 5183 return; 5184 } 5185 } 5186 abort (); 5187} 5188 5189/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */ 5190 5191static void 5192print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given) 5193{ 5194 const struct opcode16 *insn; 5195 void *stream = info->stream; 5196 fprintf_ftype func = info->fprintf_func; 5197 5198 for (insn = thumb_opcodes; insn->assembler; insn++) 5199 if ((given & insn->mask) == insn->value) 5200 { 5201 signed long value_in_comment = 0; 5202 const char *c = insn->assembler; 5203 5204 for (; *c; c++) 5205 { 5206 int domaskpc = 0; 5207 int domasklr = 0; 5208 5209 if (*c != '%') 5210 { 5211 func (stream, "%c", *c); 5212 continue; 5213 } 5214 5215 switch (*++c) 5216 { 5217 case '%': 5218 func (stream, "%%"); 5219 break; 5220 5221 case 'c': 5222 if (ifthen_state) 5223 func (stream, "%s", arm_conditional[IFTHEN_COND]); 5224 break; 5225 5226 case 'C': 5227 if (ifthen_state) 5228 func (stream, "%s", arm_conditional[IFTHEN_COND]); 5229 else 5230 func (stream, "s"); 5231 break; 5232 5233 case 'I': 5234 { 5235 unsigned int tmp; 5236 5237 ifthen_next_state = given & 0xff; 5238 for (tmp = given << 1; tmp & 0xf; tmp <<= 1) 5239 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t"); 5240 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]); 5241 } 5242 break; 5243 5244 case 'x': 5245 if (ifthen_next_state) 5246 func (stream, "\t; unpredictable branch in IT block\n"); 5247 break; 5248 5249 case 'X': 5250 if (ifthen_state) 5251 func (stream, "\t; unpredictable <IT:%s>", 5252 arm_conditional[IFTHEN_COND]); 5253 break; 5254 5255 case 'S': 5256 { 5257 long reg; 5258 5259 reg = (given >> 3) & 0x7; 5260 if (given & (1 << 6)) 5261 reg += 8; 5262 5263 func (stream, "%s", arm_regnames[reg]); 5264 } 5265 break; 5266 5267 case 'D': 5268 { 5269 long reg; 5270 5271 reg = given & 0x7; 5272 if (given & (1 << 7)) 5273 reg += 8; 5274 5275 func (stream, "%s", arm_regnames[reg]); 5276 } 5277 break; 5278 5279 case 'N': 5280 if (given & (1 << 8)) 5281 domasklr = 1; 5282 /* Fall through. */ 5283 case 'O': 5284 if (*c == 'O' && (given & (1 << 8))) 5285 domaskpc = 1; 5286 /* Fall through. */ 5287 case 'M': 5288 { 5289 int started = 0; 5290 int reg; 5291 5292 func (stream, "{"); 5293 5294 /* It would be nice if we could spot 5295 ranges, and generate the rS-rE format: */ 5296 for (reg = 0; (reg < 8); reg++) 5297 if ((given & (1 << reg)) != 0) 5298 { 5299 if (started) 5300 func (stream, ", "); 5301 started = 1; 5302 func (stream, "%s", arm_regnames[reg]); 5303 } 5304 5305 if (domasklr) 5306 { 5307 if (started) 5308 func (stream, ", "); 5309 started = 1; 5310 func (stream, "%s", arm_regnames[14] /* "lr" */); 5311 } 5312 5313 if (domaskpc) 5314 { 5315 if (started) 5316 func (stream, ", "); 5317 func (stream, "%s", arm_regnames[15] /* "pc" */); 5318 } 5319 5320 func (stream, "}"); 5321 } 5322 break; 5323 5324 case 'W': 5325 /* Print writeback indicator for a LDMIA. We are doing a 5326 writeback if the base register is not in the register 5327 mask. */ 5328 if ((given & (1 << ((given & 0x0700) >> 8))) == 0) 5329 func (stream, "!"); 5330 break; 5331 5332 case 'b': 5333 /* Print ARM V6T2 CZB address: pc+4+6 bits. */ 5334 { 5335 bfd_vma address = (pc + 4 5336 + ((given & 0x00f8) >> 2) 5337 + ((given & 0x0200) >> 3)); 5338 info->print_address_func (address, info); 5339 } 5340 break; 5341 5342 case 's': 5343 /* Right shift immediate -- bits 6..10; 1-31 print 5344 as themselves, 0 prints as 32. */ 5345 { 5346 long imm = (given & 0x07c0) >> 6; 5347 if (imm == 0) 5348 imm = 32; 5349 func (stream, "#%ld", imm); 5350 } 5351 break; 5352 5353 case '0': case '1': case '2': case '3': case '4': 5354 case '5': case '6': case '7': case '8': case '9': 5355 { 5356 int bitstart = *c++ - '0'; 5357 int bitend = 0; 5358 5359 while (*c >= '0' && *c <= '9') 5360 bitstart = (bitstart * 10) + *c++ - '0'; 5361 5362 switch (*c) 5363 { 5364 case '-': 5365 { 5366 bfd_vma reg; 5367 5368 c++; 5369 while (*c >= '0' && *c <= '9') 5370 bitend = (bitend * 10) + *c++ - '0'; 5371 if (!bitend) 5372 abort (); 5373 reg = given >> bitstart; 5374 reg &= (2 << (bitend - bitstart)) - 1; 5375 5376 switch (*c) 5377 { 5378 case 'r': 5379 func (stream, "%s", arm_regnames[reg]); 5380 break; 5381 5382 case 'd': 5383 func (stream, "%ld", (long) reg); 5384 value_in_comment = reg; 5385 break; 5386 5387 case 'H': 5388 func (stream, "%ld", (long) (reg << 1)); 5389 value_in_comment = reg << 1; 5390 break; 5391 5392 case 'W': 5393 func (stream, "%ld", (long) (reg << 2)); 5394 value_in_comment = reg << 2; 5395 break; 5396 5397 case 'a': 5398 /* PC-relative address -- the bottom two 5399 bits of the address are dropped 5400 before the calculation. */ 5401 info->print_address_func 5402 (((pc + 4) & ~3) + (reg << 2), info); 5403 value_in_comment = 0; 5404 break; 5405 5406 case 'x': 5407 func (stream, "0x%04lx", (long) reg); 5408 break; 5409 5410 case 'B': 5411 reg = ((reg ^ (1 << bitend)) - (1 << bitend)); 5412 info->print_address_func (reg * 2 + pc + 4, info); 5413 value_in_comment = 0; 5414 break; 5415 5416 case 'c': 5417 func (stream, "%s", arm_conditional [reg]); 5418 break; 5419 5420 default: 5421 abort (); 5422 } 5423 } 5424 break; 5425 5426 case '\'': 5427 c++; 5428 if ((given & (1 << bitstart)) != 0) 5429 func (stream, "%c", *c); 5430 break; 5431 5432 case '?': 5433 ++c; 5434 if ((given & (1 << bitstart)) != 0) 5435 func (stream, "%c", *c++); 5436 else 5437 func (stream, "%c", *++c); 5438 break; 5439 5440 default: 5441 abort (); 5442 } 5443 } 5444 break; 5445 5446 default: 5447 abort (); 5448 } 5449 } 5450 5451 if (value_in_comment > 32 || value_in_comment < -16) 5452 func (stream, "\t; 0x%lx", value_in_comment); 5453 return; 5454 } 5455 5456 /* No match. */ 5457 abort (); 5458} 5459 5460/* Return the name of an V7M special register. */ 5461 5462static const char * 5463psr_name (int regno) 5464{ 5465 switch (regno) 5466 { 5467 case 0x0: return "APSR"; 5468 case 0x1: return "IAPSR"; 5469 case 0x2: return "EAPSR"; 5470 case 0x3: return "PSR"; 5471 case 0x5: return "IPSR"; 5472 case 0x6: return "EPSR"; 5473 case 0x7: return "IEPSR"; 5474 case 0x8: return "MSP"; 5475 case 0x9: return "PSP"; 5476 case 0xa: return "MSPLIM"; 5477 case 0xb: return "PSPLIM"; 5478 case 0x10: return "PRIMASK"; 5479 case 0x11: return "BASEPRI"; 5480 case 0x12: return "BASEPRI_MAX"; 5481 case 0x13: return "FAULTMASK"; 5482 case 0x14: return "CONTROL"; 5483 case 0x88: return "MSP_NS"; 5484 case 0x89: return "PSP_NS"; 5485 case 0x8a: return "MSPLIM_NS"; 5486 case 0x8b: return "PSPLIM_NS"; 5487 case 0x90: return "PRIMASK_NS"; 5488 case 0x91: return "BASEPRI_NS"; 5489 case 0x93: return "FAULTMASK_NS"; 5490 case 0x94: return "CONTROL_NS"; 5491 case 0x98: return "SP_NS"; 5492 default: return "<unknown>"; 5493 } 5494} 5495 5496/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */ 5497 5498static void 5499print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) 5500{ 5501 const struct opcode32 *insn; 5502 void *stream = info->stream; 5503 fprintf_ftype func = info->fprintf_func; 5504 5505 if (print_insn_coprocessor (pc, info, given, TRUE)) 5506 return; 5507 5508 if (print_insn_neon (info, given, TRUE)) 5509 return; 5510 5511 for (insn = thumb32_opcodes; insn->assembler; insn++) 5512 if ((given & insn->mask) == insn->value) 5513 { 5514 bfd_boolean is_unpredictable = FALSE; 5515 signed long value_in_comment = 0; 5516 const char *c = insn->assembler; 5517 5518 for (; *c; c++) 5519 { 5520 if (*c != '%') 5521 { 5522 func (stream, "%c", *c); 5523 continue; 5524 } 5525 5526 switch (*++c) 5527 { 5528 case '%': 5529 func (stream, "%%"); 5530 break; 5531 5532 case 'c': 5533 if (ifthen_state) 5534 func (stream, "%s", arm_conditional[IFTHEN_COND]); 5535 break; 5536 5537 case 'x': 5538 if (ifthen_next_state) 5539 func (stream, "\t; unpredictable branch in IT block\n"); 5540 break; 5541 5542 case 'X': 5543 if (ifthen_state) 5544 func (stream, "\t; unpredictable <IT:%s>", 5545 arm_conditional[IFTHEN_COND]); 5546 break; 5547 5548 case 'I': 5549 { 5550 unsigned int imm12 = 0; 5551 5552 imm12 |= (given & 0x000000ffu); 5553 imm12 |= (given & 0x00007000u) >> 4; 5554 imm12 |= (given & 0x04000000u) >> 15; 5555 func (stream, "#%u", imm12); 5556 value_in_comment = imm12; 5557 } 5558 break; 5559 5560 case 'M': 5561 { 5562 unsigned int bits = 0, imm, imm8, mod; 5563 5564 bits |= (given & 0x000000ffu); 5565 bits |= (given & 0x00007000u) >> 4; 5566 bits |= (given & 0x04000000u) >> 15; 5567 imm8 = (bits & 0x0ff); 5568 mod = (bits & 0xf00) >> 8; 5569 switch (mod) 5570 { 5571 case 0: imm = imm8; break; 5572 case 1: imm = ((imm8 << 16) | imm8); break; 5573 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break; 5574 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break; 5575 default: 5576 mod = (bits & 0xf80) >> 7; 5577 imm8 = (bits & 0x07f) | 0x80; 5578 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff); 5579 } 5580 func (stream, "#%u", imm); 5581 value_in_comment = imm; 5582 } 5583 break; 5584 5585 case 'J': 5586 { 5587 unsigned int imm = 0; 5588 5589 imm |= (given & 0x000000ffu); 5590 imm |= (given & 0x00007000u) >> 4; 5591 imm |= (given & 0x04000000u) >> 15; 5592 imm |= (given & 0x000f0000u) >> 4; 5593 func (stream, "#%u", imm); 5594 value_in_comment = imm; 5595 } 5596 break; 5597 5598 case 'K': 5599 { 5600 unsigned int imm = 0; 5601 5602 imm |= (given & 0x000f0000u) >> 16; 5603 imm |= (given & 0x00000ff0u) >> 0; 5604 imm |= (given & 0x0000000fu) << 12; 5605 func (stream, "#%u", imm); 5606 value_in_comment = imm; 5607 } 5608 break; 5609 5610 case 'H': 5611 { 5612 unsigned int imm = 0; 5613 5614 imm |= (given & 0x000f0000u) >> 4; 5615 imm |= (given & 0x00000fffu) >> 0; 5616 func (stream, "#%u", imm); 5617 value_in_comment = imm; 5618 } 5619 break; 5620 5621 case 'V': 5622 { 5623 unsigned int imm = 0; 5624 5625 imm |= (given & 0x00000fffu); 5626 imm |= (given & 0x000f0000u) >> 4; 5627 func (stream, "#%u", imm); 5628 value_in_comment = imm; 5629 } 5630 break; 5631 5632 case 'S': 5633 { 5634 unsigned int reg = (given & 0x0000000fu); 5635 unsigned int stp = (given & 0x00000030u) >> 4; 5636 unsigned int imm = 0; 5637 imm |= (given & 0x000000c0u) >> 6; 5638 imm |= (given & 0x00007000u) >> 10; 5639 5640 func (stream, "%s", arm_regnames[reg]); 5641 switch (stp) 5642 { 5643 case 0: 5644 if (imm > 0) 5645 func (stream, ", lsl #%u", imm); 5646 break; 5647 5648 case 1: 5649 if (imm == 0) 5650 imm = 32; 5651 func (stream, ", lsr #%u", imm); 5652 break; 5653 5654 case 2: 5655 if (imm == 0) 5656 imm = 32; 5657 func (stream, ", asr #%u", imm); 5658 break; 5659 5660 case 3: 5661 if (imm == 0) 5662 func (stream, ", rrx"); 5663 else 5664 func (stream, ", ror #%u", imm); 5665 } 5666 } 5667 break; 5668 5669 case 'a': 5670 { 5671 unsigned int Rn = (given & 0x000f0000) >> 16; 5672 unsigned int U = ! NEGATIVE_BIT_SET; 5673 unsigned int op = (given & 0x00000f00) >> 8; 5674 unsigned int i12 = (given & 0x00000fff); 5675 unsigned int i8 = (given & 0x000000ff); 5676 bfd_boolean writeback = FALSE, postind = FALSE; 5677 bfd_vma offset = 0; 5678 5679 func (stream, "[%s", arm_regnames[Rn]); 5680 if (U) /* 12-bit positive immediate offset. */ 5681 { 5682 offset = i12; 5683 if (Rn != 15) 5684 value_in_comment = offset; 5685 } 5686 else if (Rn == 15) /* 12-bit negative immediate offset. */ 5687 offset = - (int) i12; 5688 else if (op == 0x0) /* Shifted register offset. */ 5689 { 5690 unsigned int Rm = (i8 & 0x0f); 5691 unsigned int sh = (i8 & 0x30) >> 4; 5692 5693 func (stream, ", %s", arm_regnames[Rm]); 5694 if (sh) 5695 func (stream, ", lsl #%u", sh); 5696 func (stream, "]"); 5697 break; 5698 } 5699 else switch (op) 5700 { 5701 case 0xE: /* 8-bit positive immediate offset. */ 5702 offset = i8; 5703 break; 5704 5705 case 0xC: /* 8-bit negative immediate offset. */ 5706 offset = -i8; 5707 break; 5708 5709 case 0xF: /* 8-bit + preindex with wb. */ 5710 offset = i8; 5711 writeback = TRUE; 5712 break; 5713 5714 case 0xD: /* 8-bit - preindex with wb. */ 5715 offset = -i8; 5716 writeback = TRUE; 5717 break; 5718 5719 case 0xB: /* 8-bit + postindex. */ 5720 offset = i8; 5721 postind = TRUE; 5722 break; 5723 5724 case 0x9: /* 8-bit - postindex. */ 5725 offset = -i8; 5726 postind = TRUE; 5727 break; 5728 5729 default: 5730 func (stream, ", <undefined>]"); 5731 goto skip; 5732 } 5733 5734 if (postind) 5735 func (stream, "], #%d", (int) offset); 5736 else 5737 { 5738 if (offset) 5739 func (stream, ", #%d", (int) offset); 5740 func (stream, writeback ? "]!" : "]"); 5741 } 5742 5743 if (Rn == 15) 5744 { 5745 func (stream, "\t; "); 5746 info->print_address_func (((pc + 4) & ~3) + offset, info); 5747 } 5748 } 5749 skip: 5750 break; 5751 5752 case 'A': 5753 { 5754 unsigned int U = ! NEGATIVE_BIT_SET; 5755 unsigned int W = WRITEBACK_BIT_SET; 5756 unsigned int Rn = (given & 0x000f0000) >> 16; 5757 unsigned int off = (given & 0x000000ff); 5758 5759 func (stream, "[%s", arm_regnames[Rn]); 5760 5761 if (PRE_BIT_SET) 5762 { 5763 if (off || !U) 5764 { 5765 func (stream, ", #%c%u", U ? '+' : '-', off * 4); 5766 value_in_comment = (off && U) ? 1 : -1; 5767 } 5768 func (stream, "]"); 5769 if (W) 5770 func (stream, "!"); 5771 } 5772 else 5773 { 5774 func (stream, "], "); 5775 if (W) 5776 { 5777 func (stream, "#%c%u", U ? '+' : '-', off * 4); 5778 value_in_comment = (off && U) ? 1 : -1; 5779 } 5780 else 5781 { 5782 func (stream, "{%u}", off); 5783 value_in_comment = off; 5784 } 5785 } 5786 } 5787 break; 5788 5789 case 'w': 5790 { 5791 unsigned int Sbit = (given & 0x01000000) >> 24; 5792 unsigned int type = (given & 0x00600000) >> 21; 5793 5794 switch (type) 5795 { 5796 case 0: func (stream, Sbit ? "sb" : "b"); break; 5797 case 1: func (stream, Sbit ? "sh" : "h"); break; 5798 case 2: 5799 if (Sbit) 5800 func (stream, "??"); 5801 break; 5802 case 3: 5803 func (stream, "??"); 5804 break; 5805 } 5806 } 5807 break; 5808 5809 case 'm': 5810 { 5811 int started = 0; 5812 int reg; 5813 5814 func (stream, "{"); 5815 for (reg = 0; reg < 16; reg++) 5816 if ((given & (1 << reg)) != 0) 5817 { 5818 if (started) 5819 func (stream, ", "); 5820 started = 1; 5821 func (stream, "%s", arm_regnames[reg]); 5822 } 5823 func (stream, "}"); 5824 } 5825 break; 5826 5827 case 'E': 5828 { 5829 unsigned int msb = (given & 0x0000001f); 5830 unsigned int lsb = 0; 5831 5832 lsb |= (given & 0x000000c0u) >> 6; 5833 lsb |= (given & 0x00007000u) >> 10; 5834 func (stream, "#%u, #%u", lsb, msb - lsb + 1); 5835 } 5836 break; 5837 5838 case 'F': 5839 { 5840 unsigned int width = (given & 0x0000001f) + 1; 5841 unsigned int lsb = 0; 5842 5843 lsb |= (given & 0x000000c0u) >> 6; 5844 lsb |= (given & 0x00007000u) >> 10; 5845 func (stream, "#%u, #%u", lsb, width); 5846 } 5847 break; 5848 5849 case 'b': 5850 { 5851 unsigned int S = (given & 0x04000000u) >> 26; 5852 unsigned int J1 = (given & 0x00002000u) >> 13; 5853 unsigned int J2 = (given & 0x00000800u) >> 11; 5854 bfd_vma offset = 0; 5855 5856 offset |= !S << 20; 5857 offset |= J2 << 19; 5858 offset |= J1 << 18; 5859 offset |= (given & 0x003f0000) >> 4; 5860 offset |= (given & 0x000007ff) << 1; 5861 offset -= (1 << 20); 5862 5863 info->print_address_func (pc + 4 + offset, info); 5864 } 5865 break; 5866 5867 case 'B': 5868 { 5869 unsigned int S = (given & 0x04000000u) >> 26; 5870 unsigned int I1 = (given & 0x00002000u) >> 13; 5871 unsigned int I2 = (given & 0x00000800u) >> 11; 5872 bfd_vma offset = 0; 5873 5874 offset |= !S << 24; 5875 offset |= !(I1 ^ S) << 23; 5876 offset |= !(I2 ^ S) << 22; 5877 offset |= (given & 0x03ff0000u) >> 4; 5878 offset |= (given & 0x000007ffu) << 1; 5879 offset -= (1 << 24); 5880 offset += pc + 4; 5881 5882 /* BLX target addresses are always word aligned. */ 5883 if ((given & 0x00001000u) == 0) 5884 offset &= ~2u; 5885 5886 info->print_address_func (offset, info); 5887 } 5888 break; 5889 5890 case 's': 5891 { 5892 unsigned int shift = 0; 5893 5894 shift |= (given & 0x000000c0u) >> 6; 5895 shift |= (given & 0x00007000u) >> 10; 5896 if (WRITEBACK_BIT_SET) 5897 func (stream, ", asr #%u", shift); 5898 else if (shift) 5899 func (stream, ", lsl #%u", shift); 5900 /* else print nothing - lsl #0 */ 5901 } 5902 break; 5903 5904 case 'R': 5905 { 5906 unsigned int rot = (given & 0x00000030) >> 4; 5907 5908 if (rot) 5909 func (stream, ", ror #%u", rot * 8); 5910 } 5911 break; 5912 5913 case 'U': 5914 if ((given & 0xf0) == 0x60) 5915 { 5916 switch (given & 0xf) 5917 { 5918 case 0xf: func (stream, "sy"); break; 5919 default: 5920 func (stream, "#%d", (int) given & 0xf); 5921 break; 5922 } 5923 } 5924 else 5925 { 5926 const char * opt = data_barrier_option (given & 0xf); 5927 if (opt != NULL) 5928 func (stream, "%s", opt); 5929 else 5930 func (stream, "#%d", (int) given & 0xf); 5931 } 5932 break; 5933 5934 case 'C': 5935 if ((given & 0xff) == 0) 5936 { 5937 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C'); 5938 if (given & 0x800) 5939 func (stream, "f"); 5940 if (given & 0x400) 5941 func (stream, "s"); 5942 if (given & 0x200) 5943 func (stream, "x"); 5944 if (given & 0x100) 5945 func (stream, "c"); 5946 } 5947 else if ((given & 0x20) == 0x20) 5948 { 5949 char const* name; 5950 unsigned sysm = (given & 0xf00) >> 8; 5951 5952 sysm |= (given & 0x30); 5953 sysm |= (given & 0x00100000) >> 14; 5954 name = banked_regname (sysm); 5955 5956 if (name != NULL) 5957 func (stream, "%s", name); 5958 else 5959 func (stream, "(UNDEF: %lu)", (unsigned long) sysm); 5960 } 5961 else 5962 { 5963 func (stream, "%s", psr_name (given & 0xff)); 5964 } 5965 break; 5966 5967 case 'D': 5968 if (((given & 0xff) == 0) 5969 || ((given & 0x20) == 0x20)) 5970 { 5971 char const* name; 5972 unsigned sm = (given & 0xf0000) >> 16; 5973 5974 sm |= (given & 0x30); 5975 sm |= (given & 0x00100000) >> 14; 5976 name = banked_regname (sm); 5977 5978 if (name != NULL) 5979 func (stream, "%s", name); 5980 else 5981 func (stream, "(UNDEF: %lu)", (unsigned long) sm); 5982 } 5983 else 5984 func (stream, "%s", psr_name (given & 0xff)); 5985 break; 5986 5987 case '0': case '1': case '2': case '3': case '4': 5988 case '5': case '6': case '7': case '8': case '9': 5989 { 5990 int width; 5991 unsigned long val; 5992 5993 c = arm_decode_bitfield (c, given, &val, &width); 5994 5995 switch (*c) 5996 { 5997 case 'd': 5998 func (stream, "%lu", val); 5999 value_in_comment = val; 6000 break; 6001 6002 case 'D': 6003 func (stream, "%lu", val + 1); 6004 value_in_comment = val + 1; 6005 break; 6006 6007 case 'W': 6008 func (stream, "%lu", val * 4); 6009 value_in_comment = val * 4; 6010 break; 6011 6012 case 'S': 6013 if (val == 13) 6014 is_unpredictable = TRUE; 6015 /* Fall through. */ 6016 case 'R': 6017 if (val == 15) 6018 is_unpredictable = TRUE; 6019 /* Fall through. */ 6020 case 'r': 6021 func (stream, "%s", arm_regnames[val]); 6022 break; 6023 6024 case 'c': 6025 func (stream, "%s", arm_conditional[val]); 6026 break; 6027 6028 case '\'': 6029 c++; 6030 if (val == ((1ul << width) - 1)) 6031 func (stream, "%c", *c); 6032 break; 6033 6034 case '`': 6035 c++; 6036 if (val == 0) 6037 func (stream, "%c", *c); 6038 break; 6039 6040 case '?': 6041 func (stream, "%c", c[(1 << width) - (int) val]); 6042 c += 1 << width; 6043 break; 6044 6045 case 'x': 6046 func (stream, "0x%lx", val & 0xffffffffUL); 6047 break; 6048 6049 default: 6050 abort (); 6051 } 6052 } 6053 break; 6054 6055 case 'L': 6056 /* PR binutils/12534 6057 If we have a PC relative offset in an LDRD or STRD 6058 instructions then display the decoded address. */ 6059 if (((given >> 16) & 0xf) == 0xf) 6060 { 6061 bfd_vma offset = (given & 0xff) * 4; 6062 6063 if ((given & (1 << 23)) == 0) 6064 offset = - offset; 6065 func (stream, "\t; "); 6066 info->print_address_func ((pc & ~3) + 4 + offset, info); 6067 } 6068 break; 6069 6070 default: 6071 abort (); 6072 } 6073 } 6074 6075 if (value_in_comment > 32 || value_in_comment < -16) 6076 func (stream, "\t; 0x%lx", value_in_comment); 6077 6078 if (is_unpredictable) 6079 func (stream, UNPREDICTABLE_INSTRUCTION); 6080 6081 return; 6082 } 6083 6084 /* No match. */ 6085 abort (); 6086} 6087 6088/* Print data bytes on INFO->STREAM. */ 6089 6090static void 6091print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED, 6092 struct disassemble_info *info, 6093 long given) 6094{ 6095 switch (info->bytes_per_chunk) 6096 { 6097 case 1: 6098 info->fprintf_func (info->stream, ".byte\t0x%02lx", given); 6099 break; 6100 case 2: 6101 info->fprintf_func (info->stream, ".short\t0x%04lx", given); 6102 break; 6103 case 4: 6104 info->fprintf_func (info->stream, ".word\t0x%08lx", given); 6105 break; 6106 default: 6107 abort (); 6108 } 6109} 6110 6111/* Disallow mapping symbols ($a, $b, $d, $t etc) from 6112 being displayed in symbol relative addresses. 6113 6114 Also disallow private symbol, with __tagsym$$ prefix, 6115 from ARM RVCT toolchain being displayed. */ 6116 6117bfd_boolean 6118arm_symbol_is_valid (asymbol * sym, 6119 struct disassemble_info * info ATTRIBUTE_UNUSED) 6120{ 6121 const char * name; 6122 6123 if (sym == NULL) 6124 return FALSE; 6125 6126 name = bfd_asymbol_name (sym); 6127 6128 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10)); 6129} 6130 6131/* Parse an individual disassembler option. */ 6132 6133void 6134parse_arm_disassembler_option (char *option) 6135{ 6136 if (option == NULL) 6137 return; 6138 6139 if (CONST_STRNEQ (option, "reg-names-")) 6140 { 6141 int i; 6142 6143 option += 10; 6144 6145 for (i = NUM_ARM_REGNAMES; i--;) 6146 if (strneq (option, regnames[i].name, strlen (regnames[i].name))) 6147 { 6148 regname_selected = i; 6149 break; 6150 } 6151 6152 if (i < 0) 6153 /* XXX - should break 'option' at following delimiter. */ 6154 fprintf (stderr, _("Unrecognised register name set: %s\n"), option); 6155 } 6156 else if (CONST_STRNEQ (option, "force-thumb")) 6157 force_thumb = 1; 6158 else if (CONST_STRNEQ (option, "no-force-thumb")) 6159 force_thumb = 0; 6160 else 6161 /* XXX - should break 'option' at following delimiter. */ 6162 fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option); 6163 6164 return; 6165} 6166 6167/* Parse the string of disassembler options, spliting it at whitespaces 6168 or commas. (Whitespace separators supported for backwards compatibility). */ 6169 6170static void 6171parse_disassembler_options (char *options) 6172{ 6173 if (options == NULL) 6174 return; 6175 6176 while (*options) 6177 { 6178 parse_arm_disassembler_option (options); 6179 6180 /* Skip forward to next seperator. */ 6181 while ((*options) && (! ISSPACE (*options)) && (*options != ',')) 6182 ++ options; 6183 /* Skip forward past seperators. */ 6184 while (ISSPACE (*options) || (*options == ',')) 6185 ++ options; 6186 } 6187} 6188 6189static bfd_boolean 6190mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info, 6191 enum map_type *map_symbol); 6192 6193/* Search back through the insn stream to determine if this instruction is 6194 conditionally executed. */ 6195 6196static void 6197find_ifthen_state (bfd_vma pc, 6198 struct disassemble_info *info, 6199 bfd_boolean little) 6200{ 6201 unsigned char b[2]; 6202 unsigned int insn; 6203 int status; 6204 /* COUNT is twice the number of instructions seen. It will be odd if we 6205 just crossed an instruction boundary. */ 6206 int count; 6207 int it_count; 6208 unsigned int seen_it; 6209 bfd_vma addr; 6210 6211 ifthen_address = pc; 6212 ifthen_state = 0; 6213 6214 addr = pc; 6215 count = 1; 6216 it_count = 0; 6217 seen_it = 0; 6218 /* Scan backwards looking for IT instructions, keeping track of where 6219 instruction boundaries are. We don't know if something is actually an 6220 IT instruction until we find a definite instruction boundary. */ 6221 for (;;) 6222 { 6223 if (addr == 0 || info->symbol_at_address_func (addr, info)) 6224 { 6225 /* A symbol must be on an instruction boundary, and will not 6226 be within an IT block. */ 6227 if (seen_it && (count & 1)) 6228 break; 6229 6230 return; 6231 } 6232 addr -= 2; 6233 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info); 6234 if (status) 6235 return; 6236 6237 if (little) 6238 insn = (b[0]) | (b[1] << 8); 6239 else 6240 insn = (b[1]) | (b[0] << 8); 6241 if (seen_it) 6242 { 6243 if ((insn & 0xf800) < 0xe800) 6244 { 6245 /* Addr + 2 is an instruction boundary. See if this matches 6246 the expected boundary based on the position of the last 6247 IT candidate. */ 6248 if (count & 1) 6249 break; 6250 seen_it = 0; 6251 } 6252 } 6253 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0) 6254 { 6255 enum map_type type = MAP_ARM; 6256 bfd_boolean found = mapping_symbol_for_insn (addr, info, &type); 6257 6258 if (!found || (found && type == MAP_THUMB)) 6259 { 6260 /* This could be an IT instruction. */ 6261 seen_it = insn; 6262 it_count = count >> 1; 6263 } 6264 } 6265 if ((insn & 0xf800) >= 0xe800) 6266 count++; 6267 else 6268 count = (count + 2) | 1; 6269 /* IT blocks contain at most 4 instructions. */ 6270 if (count >= 8 && !seen_it) 6271 return; 6272 } 6273 /* We found an IT instruction. */ 6274 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f); 6275 if ((ifthen_state & 0xf) == 0) 6276 ifthen_state = 0; 6277} 6278 6279/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a 6280 mapping symbol. */ 6281 6282static int 6283is_mapping_symbol (struct disassemble_info *info, int n, 6284 enum map_type *map_type) 6285{ 6286 const char *name; 6287 6288 name = bfd_asymbol_name (info->symtab[n]); 6289 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd') 6290 && (name[2] == 0 || name[2] == '.')) 6291 { 6292 *map_type = ((name[1] == 'a') ? MAP_ARM 6293 : (name[1] == 't') ? MAP_THUMB 6294 : MAP_DATA); 6295 return TRUE; 6296 } 6297 6298 return FALSE; 6299} 6300 6301/* Try to infer the code type (ARM or Thumb) from a mapping symbol. 6302 Returns nonzero if *MAP_TYPE was set. */ 6303 6304static int 6305get_map_sym_type (struct disassemble_info *info, 6306 int n, 6307 enum map_type *map_type) 6308{ 6309 /* If the symbol is in a different section, ignore it. */ 6310 if (info->section != NULL && info->section != info->symtab[n]->section) 6311 return FALSE; 6312 6313 return is_mapping_symbol (info, n, map_type); 6314} 6315 6316/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol. 6317 Returns nonzero if *MAP_TYPE was set. */ 6318 6319static int 6320get_sym_code_type (struct disassemble_info *info, 6321 int n, 6322 enum map_type *map_type) 6323{ 6324 elf_symbol_type *es; 6325 unsigned int type; 6326 6327 /* If the symbol is in a different section, ignore it. */ 6328 if (info->section != NULL && info->section != info->symtab[n]->section) 6329 return FALSE; 6330 6331 es = *(elf_symbol_type **)(info->symtab + n); 6332 type = ELF_ST_TYPE (es->internal_elf_sym.st_info); 6333 6334 /* If the symbol has function type then use that. */ 6335 if (type == STT_FUNC || type == STT_GNU_IFUNC) 6336 { 6337 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal) 6338 == ST_BRANCH_TO_THUMB) 6339 *map_type = MAP_THUMB; 6340 else 6341 *map_type = MAP_ARM; 6342 return TRUE; 6343 } 6344 6345 return FALSE; 6346} 6347 6348/* Search the mapping symbol state for instruction at pc. This is only 6349 applicable for elf target. 6350 6351 There is an assumption Here, info->private_data contains the correct AND 6352 up-to-date information about current scan process. The information will be 6353 used to speed this search process. 6354 6355 Return TRUE if the mapping state can be determined, and map_symbol 6356 will be updated accordingly. Otherwise, return FALSE. */ 6357 6358static bfd_boolean 6359mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info, 6360 enum map_type *map_symbol) 6361{ 6362 bfd_vma addr; 6363 int n, start = 0; 6364 bfd_boolean found = FALSE; 6365 enum map_type type = MAP_ARM; 6366 struct arm_private_data *private_data; 6367 6368 if (info->private_data == NULL || info->symtab_size == 0 6369 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour) 6370 return FALSE; 6371 6372 private_data = info->private_data; 6373 if (pc == 0) 6374 start = 0; 6375 else 6376 start = private_data->last_mapping_sym; 6377 6378 start = (start == -1)? 0 : start; 6379 addr = bfd_asymbol_value (info->symtab[start]); 6380 6381 if (pc >= addr) 6382 { 6383 if (get_map_sym_type (info, start, &type)) 6384 found = TRUE; 6385 } 6386 else 6387 { 6388 for (n = start - 1; n >= 0; n--) 6389 { 6390 if (get_map_sym_type (info, n, &type)) 6391 { 6392 found = TRUE; 6393 break; 6394 } 6395 } 6396 } 6397 6398 /* No mapping symbols were found. A leading $d may be 6399 omitted for sections which start with data; but for 6400 compatibility with legacy and stripped binaries, only 6401 assume the leading $d if there is at least one mapping 6402 symbol in the file. */ 6403 if (!found && private_data->has_mapping_symbols == 1) 6404 { 6405 type = MAP_DATA; 6406 found = TRUE; 6407 } 6408 6409 *map_symbol = type; 6410 return found; 6411} 6412 6413/* Given a bfd_mach_arm_XXX value, this function fills in the fields 6414 of the supplied arm_feature_set structure with bitmasks indicating 6415 the support base architectures and coprocessor extensions. 6416 6417 FIXME: This could more efficiently implemented as a constant array, 6418 although it would also be less robust. */ 6419 6420static void 6421select_arm_features (unsigned long mach, 6422 arm_feature_set * features) 6423{ 6424#undef ARM_SET_FEATURES 6425#define ARM_SET_FEATURES(FSET) \ 6426 { \ 6427 const arm_feature_set fset = FSET; \ 6428 arm_feature_set tmp = ARM_FEATURE (0, 0, FPU_FPA) ; \ 6429 ARM_MERGE_FEATURE_SETS (*features, tmp, fset); \ 6430 } 6431 6432 switch (mach) 6433 { 6434 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break; 6435 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break; 6436 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break; 6437 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break; 6438 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break; 6439 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break; 6440 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break; 6441 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break; 6442 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break; 6443 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break; 6444 case bfd_mach_arm_ep9312: 6445 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T, 6446 ARM_CEXT_MAVERICK | FPU_MAVERICK)); 6447 break; 6448 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break; 6449 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break; 6450 /* If the machine type is unknown allow all 6451 architecture types and all extensions. */ 6452 case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break; 6453 default: 6454 abort (); 6455 } 6456 6457#undef ARM_SET_FEATURES 6458} 6459 6460 6461/* NOTE: There are no checks in these routines that 6462 the relevant number of data bytes exist. */ 6463 6464static int 6465print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little) 6466{ 6467 unsigned char b[4]; 6468 long given; 6469 int status; 6470 int is_thumb = FALSE; 6471 int is_data = FALSE; 6472 int little_code; 6473 unsigned int size = 4; 6474 void (*printer) (bfd_vma, struct disassemble_info *, long); 6475 bfd_boolean found = FALSE; 6476 struct arm_private_data *private_data; 6477 6478 if (info->disassembler_options) 6479 { 6480 parse_disassembler_options (info->disassembler_options); 6481 6482 /* To avoid repeated parsing of these options, we remove them here. */ 6483 info->disassembler_options = NULL; 6484 } 6485 6486 /* PR 10288: Control which instructions will be disassembled. */ 6487 if (info->private_data == NULL) 6488 { 6489 static struct arm_private_data private; 6490 6491 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0) 6492 /* If the user did not use the -m command line switch then default to 6493 disassembling all types of ARM instruction. 6494 6495 The info->mach value has to be ignored as this will be based on 6496 the default archictecture for the target and/or hints in the notes 6497 section, but it will never be greater than the current largest arm 6498 machine value (iWMMXt2), which is only equivalent to the V5TE 6499 architecture. ARM architectures have advanced beyond the machine 6500 value encoding, and these newer architectures would be ignored if 6501 the machine value was used. 6502 6503 Ie the -m switch is used to restrict which instructions will be 6504 disassembled. If it is necessary to use the -m switch to tell 6505 objdump that an ARM binary is being disassembled, eg because the 6506 input is a raw binary file, but it is also desired to disassemble 6507 all ARM instructions then use "-marm". This will select the 6508 "unknown" arm architecture which is compatible with any ARM 6509 instruction. */ 6510 info->mach = bfd_mach_arm_unknown; 6511 6512 /* Compute the architecture bitmask from the machine number. 6513 Note: This assumes that the machine number will not change 6514 during disassembly.... */ 6515 select_arm_features (info->mach, & private.features); 6516 6517 private.has_mapping_symbols = -1; 6518 private.last_mapping_sym = -1; 6519 private.last_mapping_addr = 0; 6520 6521 info->private_data = & private; 6522 } 6523 6524 private_data = info->private_data; 6525 6526 /* Decide if our code is going to be little-endian, despite what the 6527 function argument might say. */ 6528 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little); 6529 6530 /* For ELF, consult the symbol table to determine what kind of code 6531 or data we have. */ 6532 if (info->symtab_size != 0 6533 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour) 6534 { 6535 bfd_vma addr; 6536 int n, start; 6537 int last_sym = -1; 6538 enum map_type type = MAP_ARM; 6539 6540 /* Start scanning at the start of the function, or wherever 6541 we finished last time. */ 6542 /* PR 14006. When the address is 0 we are either at the start of the 6543 very first function, or else the first function in a new, unlinked 6544 executable section (eg because of -ffunction-sections). Either way 6545 start scanning from the beginning of the symbol table, not where we 6546 left off last time. */ 6547 if (pc == 0) 6548 start = 0; 6549 else 6550 { 6551 start = info->symtab_pos + 1; 6552 if (start < private_data->last_mapping_sym) 6553 start = private_data->last_mapping_sym; 6554 } 6555 found = FALSE; 6556 6557 /* First, look for mapping symbols. */ 6558 if (private_data->has_mapping_symbols != 0) 6559 { 6560 /* Scan up to the location being disassembled. */ 6561 for (n = start; n < info->symtab_size; n++) 6562 { 6563 addr = bfd_asymbol_value (info->symtab[n]); 6564 if (addr > pc) 6565 break; 6566 if (get_map_sym_type (info, n, &type)) 6567 { 6568 last_sym = n; 6569 found = TRUE; 6570 } 6571 } 6572 6573 if (!found) 6574 { 6575 /* No mapping symbol found at this address. Look backwards 6576 for a preceding one. */ 6577 for (n = start - 1; n >= 0; n--) 6578 { 6579 if (get_map_sym_type (info, n, &type)) 6580 { 6581 last_sym = n; 6582 found = TRUE; 6583 break; 6584 } 6585 } 6586 } 6587 6588 if (found) 6589 private_data->has_mapping_symbols = 1; 6590 6591 /* No mapping symbols were found. A leading $d may be 6592 omitted for sections which start with data; but for 6593 compatibility with legacy and stripped binaries, only 6594 assume the leading $d if there is at least one mapping 6595 symbol in the file. */ 6596 if (!found && private_data->has_mapping_symbols == -1) 6597 { 6598 /* Look for mapping symbols, in any section. */ 6599 for (n = 0; n < info->symtab_size; n++) 6600 if (is_mapping_symbol (info, n, &type)) 6601 { 6602 private_data->has_mapping_symbols = 1; 6603 break; 6604 } 6605 if (private_data->has_mapping_symbols == -1) 6606 private_data->has_mapping_symbols = 0; 6607 } 6608 6609 if (!found && private_data->has_mapping_symbols == 1) 6610 { 6611 type = MAP_DATA; 6612 found = TRUE; 6613 } 6614 } 6615 6616 /* Next search for function symbols to separate ARM from Thumb 6617 in binaries without mapping symbols. */ 6618 if (!found) 6619 { 6620 /* Scan up to the location being disassembled. */ 6621 for (n = start; n < info->symtab_size; n++) 6622 { 6623 addr = bfd_asymbol_value (info->symtab[n]); 6624 if (addr > pc) 6625 break; 6626 if (get_sym_code_type (info, n, &type)) 6627 { 6628 last_sym = n; 6629 found = TRUE; 6630 } 6631 } 6632 6633 if (!found) 6634 { 6635 /* No mapping symbol found at this address. Look backwards 6636 for a preceding one. */ 6637 for (n = start - 1; n >= 0; n--) 6638 { 6639 if (get_sym_code_type (info, n, &type)) 6640 { 6641 last_sym = n; 6642 found = TRUE; 6643 break; 6644 } 6645 } 6646 } 6647 } 6648 6649 private_data->last_mapping_sym = last_sym; 6650 private_data->last_type = type; 6651 is_thumb = (private_data->last_type == MAP_THUMB); 6652 is_data = (private_data->last_type == MAP_DATA); 6653 6654 /* Look a little bit ahead to see if we should print out 6655 two or four bytes of data. If there's a symbol, 6656 mapping or otherwise, after two bytes then don't 6657 print more. */ 6658 if (is_data) 6659 { 6660 size = 4 - (pc & 3); 6661 for (n = last_sym + 1; n < info->symtab_size; n++) 6662 { 6663 addr = bfd_asymbol_value (info->symtab[n]); 6664 if (addr > pc 6665 && (info->section == NULL 6666 || info->section == info->symtab[n]->section)) 6667 { 6668 if (addr - pc < size) 6669 size = addr - pc; 6670 break; 6671 } 6672 } 6673 /* If the next symbol is after three bytes, we need to 6674 print only part of the data, so that we can use either 6675 .byte or .short. */ 6676 if (size == 3) 6677 size = (pc & 1) ? 1 : 2; 6678 } 6679 } 6680 6681 if (info->symbols != NULL) 6682 { 6683 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour) 6684 { 6685 coff_symbol_type * cs; 6686 6687 cs = coffsymbol (*info->symbols); 6688 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT 6689 || cs->native->u.syment.n_sclass == C_THUMBSTAT 6690 || cs->native->u.syment.n_sclass == C_THUMBLABEL 6691 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC 6692 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC); 6693 } 6694 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour 6695 && !found) 6696 { 6697 /* If no mapping symbol has been found then fall back to the type 6698 of the function symbol. */ 6699 elf_symbol_type * es; 6700 unsigned int type; 6701 6702 es = *(elf_symbol_type **)(info->symbols); 6703 type = ELF_ST_TYPE (es->internal_elf_sym.st_info); 6704 6705 is_thumb = 6706 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal) 6707 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT); 6708 } 6709 else if (bfd_asymbol_flavour (*info->symbols) 6710 == bfd_target_mach_o_flavour) 6711 { 6712 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols; 6713 6714 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF); 6715 } 6716 } 6717 6718 if (force_thumb) 6719 is_thumb = TRUE; 6720 6721 if (is_data) 6722 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; 6723 else 6724 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; 6725 6726 info->bytes_per_line = 4; 6727 6728 /* PR 10263: Disassemble data if requested to do so by the user. */ 6729 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0)) 6730 { 6731 int i; 6732 6733 /* Size was already set above. */ 6734 info->bytes_per_chunk = size; 6735 printer = print_insn_data; 6736 6737 status = info->read_memory_func (pc, (bfd_byte *) b, size, info); 6738 given = 0; 6739 if (little) 6740 for (i = size - 1; i >= 0; i--) 6741 given = b[i] | (given << 8); 6742 else 6743 for (i = 0; i < (int) size; i++) 6744 given = b[i] | (given << 8); 6745 } 6746 else if (!is_thumb) 6747 { 6748 /* In ARM mode endianness is a straightforward issue: the instruction 6749 is four bytes long and is either ordered 0123 or 3210. */ 6750 printer = print_insn_arm; 6751 info->bytes_per_chunk = 4; 6752 size = 4; 6753 6754 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info); 6755 if (little_code) 6756 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24); 6757 else 6758 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24); 6759 } 6760 else 6761 { 6762 /* In Thumb mode we have the additional wrinkle of two 6763 instruction lengths. Fortunately, the bits that determine 6764 the length of the current instruction are always to be found 6765 in the first two bytes. */ 6766 printer = print_insn_thumb16; 6767 info->bytes_per_chunk = 2; 6768 size = 2; 6769 6770 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info); 6771 if (little_code) 6772 given = (b[0]) | (b[1] << 8); 6773 else 6774 given = (b[1]) | (b[0] << 8); 6775 6776 if (!status) 6777 { 6778 /* These bit patterns signal a four-byte Thumb 6779 instruction. */ 6780 if ((given & 0xF800) == 0xF800 6781 || (given & 0xF800) == 0xF000 6782 || (given & 0xF800) == 0xE800) 6783 { 6784 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info); 6785 if (little_code) 6786 given = (b[0]) | (b[1] << 8) | (given << 16); 6787 else 6788 given = (b[1]) | (b[0] << 8) | (given << 16); 6789 6790 printer = print_insn_thumb32; 6791 size = 4; 6792 } 6793 } 6794 6795 if (ifthen_address != pc) 6796 find_ifthen_state (pc, info, little_code); 6797 6798 if (ifthen_state) 6799 { 6800 if ((ifthen_state & 0xf) == 0x8) 6801 ifthen_next_state = 0; 6802 else 6803 ifthen_next_state = (ifthen_state & 0xe0) 6804 | ((ifthen_state & 0xf) << 1); 6805 } 6806 } 6807 6808 if (status) 6809 { 6810 info->memory_error_func (status, pc, info); 6811 return -1; 6812 } 6813 if (info->flags & INSN_HAS_RELOC) 6814 /* If the instruction has a reloc associated with it, then 6815 the offset field in the instruction will actually be the 6816 addend for the reloc. (We are using REL type relocs). 6817 In such cases, we can ignore the pc when computing 6818 addresses, since the addend is not currently pc-relative. */ 6819 pc = 0; 6820 6821 printer (pc, info, given); 6822 6823 if (is_thumb) 6824 { 6825 ifthen_state = ifthen_next_state; 6826 ifthen_address += size; 6827 } 6828 return size; 6829} 6830 6831int 6832print_insn_big_arm (bfd_vma pc, struct disassemble_info *info) 6833{ 6834 /* Detect BE8-ness and record it in the disassembler info. */ 6835 if (info->flavour == bfd_target_elf_flavour 6836 && info->section != NULL 6837 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8)) 6838 info->endian_code = BFD_ENDIAN_LITTLE; 6839 6840 return print_insn (pc, info, FALSE); 6841} 6842 6843int 6844print_insn_little_arm (bfd_vma pc, struct disassemble_info *info) 6845{ 6846 return print_insn (pc, info, TRUE); 6847} 6848 6849void 6850print_arm_disassembler_options (FILE *stream) 6851{ 6852 int i; 6853 6854 fprintf (stream, _("\n\ 6855The following ARM specific disassembler options are supported for use with\n\ 6856the -M switch:\n")); 6857 6858 for (i = NUM_ARM_REGNAMES; i--;) 6859 fprintf (stream, " reg-names-%s %*c%s\n", 6860 regnames[i].name, 6861 (int)(14 - strlen (regnames[i].name)), ' ', 6862 regnames[i].description); 6863 6864 fprintf (stream, " force-thumb Assume all insns are Thumb insns\n"); 6865 fprintf (stream, " no-force-thumb Examine preceding label to determine an insn's type\n\n"); 6866} 6867