1This is as.info, produced by makeinfo version 6.1 from as.texinfo. 2 3This file documents the GNU Assembler "as". 4 5 Copyright (C) 1991-2017 Free Software Foundation, Inc. 6 7 Permission is granted to copy, distribute and/or modify this document 8under the terms of the GNU Free Documentation License, Version 1.3 or 9any later version published by the Free Software Foundation; with no 10Invariant Sections, with no Front-Cover Texts, and with no Back-Cover 11Texts. A copy of the license is included in the section entitled "GNU 12Free Documentation License". 13 14INFO-DIR-SECTION Software development 15START-INFO-DIR-ENTRY 16* As: (as). The GNU assembler. 17* Gas: (as). The GNU assembler. 18END-INFO-DIR-ENTRY 19 20 21File: as.info, Node: Top, Next: Overview, Up: (dir) 22 23Using as 24******** 25 26This file is a user guide to the GNU assembler 'as' (GNU Binutils) 27version 2.28. 28 29 This document is distributed under the terms of the GNU Free 30Documentation License. A copy of the license is included in the section 31entitled "GNU Free Documentation License". 32 33* Menu: 34 35* Overview:: Overview 36* Invoking:: Command-Line Options 37* Syntax:: Syntax 38* Sections:: Sections and Relocation 39* Symbols:: Symbols 40* Expressions:: Expressions 41* Pseudo Ops:: Assembler Directives 42* Object Attributes:: Object Attributes 43* Machine Dependencies:: Machine Dependent Features 44* Reporting Bugs:: Reporting Bugs 45* Acknowledgements:: Who Did What 46* GNU Free Documentation License:: GNU Free Documentation License 47* AS Index:: AS Index 48 49 50File: as.info, Node: Overview, Next: Invoking, Prev: Top, Up: Top 51 521 Overview 53********** 54 55Here is a brief summary of how to invoke 'as'. For details, see *note 56Command-Line Options: Invoking. 57 58 as [-a[cdghlns][=FILE]] [-alternate] [-D] 59 [-compress-debug-sections] [-nocompress-debug-sections] 60 [-debug-prefix-map OLD=NEW] 61 [-defsym SYM=VAL] [-f] [-g] [-gstabs] 62 [-gstabs+] [-gdwarf-2] [-gdwarf-sections] 63 [-help] [-I DIR] [-J] 64 [-K] [-L] [-listing-lhs-width=NUM] 65 [-listing-lhs-width2=NUM] [-listing-rhs-width=NUM] 66 [-listing-cont-lines=NUM] [-keep-locals] 67 [-no-pad-sections] 68 [-o OBJFILE] [-R] 69 [-hash-size=NUM] [-reduce-memory-overheads] 70 [-statistics] 71 [-v] [-version] [-version] 72 [-W] [-warn] [-fatal-warnings] [-w] [-x] 73 [-Z] [@FILE] 74 [-sectname-subst] [-size-check=[error|warning]] 75 [-elf-stt-common=[no|yes]] 76 [-target-help] [TARGET-OPTIONS] 77 [-|FILES ...] 78 79 _Target AArch64 options:_ 80 [-EB|-EL] 81 [-mabi=ABI] 82 83 _Target Alpha options:_ 84 [-mCPU] 85 [-mdebug | -no-mdebug] 86 [-replace | -noreplace] 87 [-relax] [-g] [-GSIZE] 88 [-F] [-32addr] 89 90 _Target ARC options:_ 91 [-mcpu=CPU] 92 [-mA6|-mARC600|-mARC601|-mA7|-mARC700|-mEM|-mHS] 93 [-mcode-density] 94 [-mrelax] 95 [-EB|-EL] 96 97 _Target ARM options:_ 98 [-mcpu=PROCESSOR[+EXTENSION...]] 99 [-march=ARCHITECTURE[+EXTENSION...]] 100 [-mfpu=FLOATING-POINT-FORMAT] 101 [-mfloat-abi=ABI] 102 [-meabi=VER] 103 [-mthumb] 104 [-EB|-EL] 105 [-mapcs-32|-mapcs-26|-mapcs-float| 106 -mapcs-reentrant] 107 [-mthumb-interwork] [-k] 108 109 _Target Blackfin options:_ 110 [-mcpu=PROCESSOR[-SIREVISION]] 111 [-mfdpic] 112 [-mno-fdpic] 113 [-mnopic] 114 115 _Target CRIS options:_ 116 [-underscore | -no-underscore] 117 [-pic] [-N] 118 [-emulation=criself | -emulation=crisaout] 119 [-march=v0_v10 | -march=v10 | -march=v32 | -march=common_v10_v32] 120 121 _Target D10V options:_ 122 [-O] 123 124 _Target D30V options:_ 125 [-O|-n|-N] 126 127 _Target EPIPHANY options:_ 128 [-mepiphany|-mepiphany16] 129 130 _Target H8/300 options:_ 131 [-h-tick-hex] 132 133 _Target i386 options:_ 134 [-32|-x32|-64] [-n] 135 [-march=CPU[+EXTENSION...]] [-mtune=CPU] 136 137 _Target i960 options:_ 138 [-ACA|-ACA_A|-ACB|-ACC|-AKA|-AKB| 139 -AKC|-AMC] 140 [-b] [-no-relax] 141 142 _Target IA-64 options:_ 143 [-mconstant-gp|-mauto-pic] 144 [-milp32|-milp64|-mlp64|-mp64] 145 [-mle|mbe] 146 [-mtune=itanium1|-mtune=itanium2] 147 [-munwind-check=warning|-munwind-check=error] 148 [-mhint.b=ok|-mhint.b=warning|-mhint.b=error] 149 [-x|-xexplicit] [-xauto] [-xdebug] 150 151 _Target IP2K options:_ 152 [-mip2022|-mip2022ext] 153 154 _Target M32C options:_ 155 [-m32c|-m16c] [-relax] [-h-tick-hex] 156 157 _Target M32R options:_ 158 [-m32rx|-[no-]warn-explicit-parallel-conflicts| 159 -W[n]p] 160 161 _Target M680X0 options:_ 162 [-l] [-m68000|-m68010|-m68020|...] 163 164 _Target M68HC11 options:_ 165 [-m68hc11|-m68hc12|-m68hcs12|-mm9s12x|-mm9s12xg] 166 [-mshort|-mlong] 167 [-mshort-double|-mlong-double] 168 [-force-long-branches] [-short-branches] 169 [-strict-direct-mode] [-print-insn-syntax] 170 [-print-opcodes] [-generate-example] 171 172 _Target MCORE options:_ 173 [-jsri2bsr] [-sifilter] [-relax] 174 [-mcpu=[210|340]] 175 176 _Target Meta options:_ 177 [-mcpu=CPU] [-mfpu=CPU] [-mdsp=CPU] 178 _Target MICROBLAZE options:_ 179 180 _Target MIPS options:_ 181 [-nocpp] [-EL] [-EB] [-O[OPTIMIZATION LEVEL]] 182 [-g[DEBUG LEVEL]] [-G NUM] [-KPIC] [-call_shared] 183 [-non_shared] [-xgot [-mvxworks-pic] 184 [-mabi=ABI] [-32] [-n32] [-64] [-mfp32] [-mgp32] 185 [-mfp64] [-mgp64] [-mfpxx] 186 [-modd-spreg] [-mno-odd-spreg] 187 [-march=CPU] [-mtune=CPU] [-mips1] [-mips2] 188 [-mips3] [-mips4] [-mips5] [-mips32] [-mips32r2] 189 [-mips32r3] [-mips32r5] [-mips32r6] [-mips64] [-mips64r2] 190 [-mips64r3] [-mips64r5] [-mips64r6] 191 [-construct-floats] [-no-construct-floats] 192 [-mignore-branch-isa] [-mno-ignore-branch-isa] 193 [-mnan=ENCODING] 194 [-trap] [-no-break] [-break] [-no-trap] 195 [-mips16] [-no-mips16] 196 [-mmicromips] [-mno-micromips] 197 [-msmartmips] [-mno-smartmips] 198 [-mips3d] [-no-mips3d] 199 [-mdmx] [-no-mdmx] 200 [-mdsp] [-mno-dsp] 201 [-mdspr2] [-mno-dspr2] 202 [-mdspr3] [-mno-dspr3] 203 [-mmsa] [-mno-msa] 204 [-mxpa] [-mno-xpa] 205 [-mmt] [-mno-mt] 206 [-mmcu] [-mno-mcu] 207 [-minsn32] [-mno-insn32] 208 [-mfix7000] [-mno-fix7000] 209 [-mfix-rm7000] [-mno-fix-rm7000] 210 [-mfix-vr4120] [-mno-fix-vr4120] 211 [-mfix-vr4130] [-mno-fix-vr4130] 212 [-mdebug] [-no-mdebug] 213 [-mpdr] [-mno-pdr] 214 215 _Target MMIX options:_ 216 [-fixed-special-register-names] [-globalize-symbols] 217 [-gnu-syntax] [-relax] [-no-predefined-symbols] 218 [-no-expand] [-no-merge-gregs] [-x] 219 [-linker-allocated-gregs] 220 221 _Target Nios II options:_ 222 [-relax-all] [-relax-section] [-no-relax] 223 [-EB] [-EL] 224 225 _Target NDS32 options:_ 226 [-EL] [-EB] [-O] [-Os] [-mcpu=CPU] 227 [-misa=ISA] [-mabi=ABI] [-mall-ext] 228 [-m[no-]16-bit] [-m[no-]perf-ext] [-m[no-]perf2-ext] 229 [-m[no-]string-ext] [-m[no-]dsp-ext] [-m[no-]mac] [-m[no-]div] 230 [-m[no-]audio-isa-ext] [-m[no-]fpu-sp-ext] [-m[no-]fpu-dp-ext] 231 [-m[no-]fpu-fma] [-mfpu-freg=FREG] [-mreduced-regs] 232 [-mfull-regs] [-m[no-]dx-regs] [-mpic] [-mno-relax] 233 [-mb2bb] 234 235 _Target PDP11 options:_ 236 [-mpic|-mno-pic] [-mall] [-mno-extensions] 237 [-mEXTENSION|-mno-EXTENSION] 238 [-mCPU] [-mMACHINE] 239 240 _Target picoJava options:_ 241 [-mb|-me] 242 243 _Target PowerPC options:_ 244 [-a32|-a64] 245 [-mpwrx|-mpwr2|-mpwr|-m601|-mppc|-mppc32|-m603|-m604|-m403|-m405| 246 -m440|-m464|-m476|-m7400|-m7410|-m7450|-m7455|-m750cl|-mppc64| 247 -m620|-me500|-e500x2|-me500mc|-me500mc64|-me5500|-me6500|-mppc64bridge| 248 -mbooke|-mpower4|-mpwr4|-mpower5|-mpwr5|-mpwr5x|-mpower6|-mpwr6| 249 -mpower7|-mpwr7|-mpower8|-mpwr8|-mpower9|-mpwr9-ma2| 250 -mcell|-mspe|-mtitan|-me300|-mcom] 251 [-many] [-maltivec|-mvsx|-mhtm|-mvle] 252 [-mregnames|-mno-regnames] 253 [-mrelocatable|-mrelocatable-lib|-K PIC] [-memb] 254 [-mlittle|-mlittle-endian|-le|-mbig|-mbig-endian|-be] 255 [-msolaris|-mno-solaris] 256 [-nops=COUNT] 257 258 _Target RL78 options:_ 259 [-mg10] 260 [-m32bit-doubles|-m64bit-doubles] 261 262 _Target RX options:_ 263 [-mlittle-endian|-mbig-endian] 264 [-m32bit-doubles|-m64bit-doubles] 265 [-muse-conventional-section-names] 266 [-msmall-data-limit] 267 [-mpid] 268 [-mrelax] 269 [-mint-register=NUMBER] 270 [-mgcc-abi|-mrx-abi] 271 272 _Target RISC-V options:_ 273 [-march=ISA] 274 [-mabi=ABI] 275 276 _Target s390 options:_ 277 [-m31|-m64] [-mesa|-mzarch] [-march=CPU] 278 [-mregnames|-mno-regnames] 279 [-mwarn-areg-zero] 280 281 _Target SCORE options:_ 282 [-EB][-EL][-FIXDD][-NWARN] 283 [-SCORE5][-SCORE5U][-SCORE7][-SCORE3] 284 [-march=score7][-march=score3] 285 [-USE_R1][-KPIC][-O0][-G NUM][-V] 286 287 _Target SPARC options:_ 288 [-Av6|-Av7|-Av8|-Aleon|-Asparclet|-Asparclite 289 -Av8plus|-Av8plusa|-Av8plusb|-Av8plusc|-Av8plusd 290 -Av8plusv|-Av8plusm|-Av9|-Av9a|-Av9b|-Av9c 291 -Av9d|-Av9e|-Av9v|-Av9m|-Asparc|-Asparcvis 292 -Asparcvis2|-Asparcfmaf|-Asparcima|-Asparcvis3 293 -Asparcvisr|-Asparc5] 294 [-xarch=v8plus|-xarch=v8plusa]|-xarch=v8plusb|-xarch=v8plusc 295 -xarch=v8plusd|-xarch=v8plusv|-xarch=v8plusm|-xarch=v9 296 -xarch=v9a|-xarch=v9b|-xarch=v9c|-xarch=v9d|-xarch=v9e 297 -xarch=v9v|-xarch=v9m|-xarch=sparc|-xarch=sparcvis 298 -xarch=sparcvis2|-xarch=sparcfmaf|-xarch=sparcima 299 -xarch=sparcvis3|-xarch=sparcvisr|-xarch=sparc5 300 -bump] 301 [-32|-64] 302 [-enforce-aligned-data][-dcti-couples-detect] 303 304 _Target TIC54X options:_ 305 [-mcpu=54[123589]|-mcpu=54[56]lp] [-mfar-mode|-mf] 306 [-merrors-to-file <FILENAME>|-me <FILENAME>] 307 308 _Target TIC6X options:_ 309 [-march=ARCH] [-mbig-endian|-mlittle-endian] 310 [-mdsbt|-mno-dsbt] [-mpid=no|-mpid=near|-mpid=far] 311 [-mpic|-mno-pic] 312 313 _Target TILE-Gx options:_ 314 [-m32|-m64][-EB][-EL] 315 316 _Target Visium options:_ 317 [-mtune=ARCH] 318 319 _Target Xtensa options:_ 320 [-[no-]text-section-literals] [-[no-]auto-litpools] 321 [-[no-]absolute-literals] 322 [-[no-]target-align] [-[no-]longcalls] 323 [-[no-]transform] 324 [-rename-section OLDNAME=NEWNAME] 325 [-[no-]trampolines] 326 327 _Target Z80 options:_ 328 [-z80] [-r800] 329 [ -ignore-undocumented-instructions] [-Wnud] 330 [ -ignore-unportable-instructions] [-Wnup] 331 [ -warn-undocumented-instructions] [-Wud] 332 [ -warn-unportable-instructions] [-Wup] 333 [ -forbid-undocumented-instructions] [-Fud] 334 [ -forbid-unportable-instructions] [-Fup] 335 336 337 338'@FILE' 339 Read command-line options from FILE. The options read are inserted 340 in place of the original @FILE option. If FILE does not exist, or 341 cannot be read, then the option will be treated literally, and not 342 removed. 343 344 Options in FILE are separated by whitespace. A whitespace 345 character may be included in an option by surrounding the entire 346 option in either single or double quotes. Any character (including 347 a backslash) may be included by prefixing the character to be 348 included with a backslash. The FILE may itself contain additional 349 @FILE options; any such options will be processed recursively. 350 351'-a[cdghlmns]' 352 Turn on listings, in any of a variety of ways: 353 354 '-ac' 355 omit false conditionals 356 357 '-ad' 358 omit debugging directives 359 360 '-ag' 361 include general information, like as version and options 362 passed 363 364 '-ah' 365 include high-level source 366 367 '-al' 368 include assembly 369 370 '-am' 371 include macro expansions 372 373 '-an' 374 omit forms processing 375 376 '-as' 377 include symbols 378 379 '=file' 380 set the name of the listing file 381 382 You may combine these options; for example, use '-aln' for assembly 383 listing without forms processing. The '=file' option, if used, 384 must be the last one. By itself, '-a' defaults to '-ahls'. 385 386'--alternate' 387 Begin in alternate macro mode. *Note '.altmacro': Altmacro. 388 389'--compress-debug-sections' 390 Compress DWARF debug sections using zlib with SHF_COMPRESSED from 391 the ELF ABI. The resulting object file may not be compatible with 392 older linkers and object file utilities. Note if compression would 393 make a given section _larger_ then it is not compressed. 394 395'--compress-debug-sections=none' 396'--compress-debug-sections=zlib' 397'--compress-debug-sections=zlib-gnu' 398'--compress-debug-sections=zlib-gabi' 399 These options control how DWARF debug sections are compressed. 400 '--compress-debug-sections=none' is equivalent to 401 '--nocompress-debug-sections'. '--compress-debug-sections=zlib' 402 and '--compress-debug-sections=zlib-gabi' are equivalent to 403 '--compress-debug-sections'. '--compress-debug-sections=zlib-gnu' 404 compresses DWARF debug sections using zlib. The debug sections are 405 renamed to begin with '.zdebug'. Note if compression would make a 406 given section _larger_ then it is not compressed nor renamed. 407 408'--nocompress-debug-sections' 409 Do not compress DWARF debug sections. This is usually the default 410 for all targets except the x86/x86_64, but a configure time option 411 can be used to override this. 412 413'-D' 414 Ignored. This option is accepted for script compatibility with 415 calls to other assemblers. 416 417'--debug-prefix-map OLD=NEW' 418 When assembling files in directory 'OLD', record debugging 419 information describing them as in 'NEW' instead. 420 421'--defsym SYM=VALUE' 422 Define the symbol SYM to be VALUE before assembling the input file. 423 VALUE must be an integer constant. As in C, a leading '0x' 424 indicates a hexadecimal value, and a leading '0' indicates an octal 425 value. The value of the symbol can be overridden inside a source 426 file via the use of a '.set' pseudo-op. 427 428'-f' 429 "fast"--skip whitespace and comment preprocessing (assume source is 430 compiler output). 431 432'-g' 433'--gen-debug' 434 Generate debugging information for each assembler source line using 435 whichever debug format is preferred by the target. This currently 436 means either STABS, ECOFF or DWARF2. 437 438'--gstabs' 439 Generate stabs debugging information for each assembler line. This 440 may help debugging assembler code, if the debugger can handle it. 441 442'--gstabs+' 443 Generate stabs debugging information for each assembler line, with 444 GNU extensions that probably only gdb can handle, and that could 445 make other debuggers crash or refuse to read your program. This 446 may help debugging assembler code. Currently the only GNU 447 extension is the location of the current working directory at 448 assembling time. 449 450'--gdwarf-2' 451 Generate DWARF2 debugging information for each assembler line. 452 This may help debugging assembler code, if the debugger can handle 453 it. Note--this option is only supported by some targets, not all 454 of them. 455 456'--gdwarf-sections' 457 Instead of creating a .debug_line section, create a series of 458 .debug_line.FOO sections where FOO is the name of the corresponding 459 code section. For example a code section called .TEXT.FUNC will 460 have its dwarf line number information placed into a section called 461 .DEBUG_LINE.TEXT.FUNC. If the code section is just called .TEXT 462 then debug line section will still be called just .DEBUG_LINE 463 without any suffix. 464 465'--size-check=error' 466'--size-check=warning' 467 Issue an error or warning for invalid ELF .size directive. 468 469'--elf-stt-common=no' 470'--elf-stt-common=yes' 471 These options control whether the ELF assembler should generate 472 common symbols with the 'STT_COMMON' type. The default can be 473 controlled by a configure option '--enable-elf-stt-common'. 474 475'--help' 476 Print a summary of the command line options and exit. 477 478'--target-help' 479 Print a summary of all target specific options and exit. 480 481'-I DIR' 482 Add directory DIR to the search list for '.include' directives. 483 484'-J' 485 Don't warn about signed overflow. 486 487'-K' 488 Issue warnings when difference tables altered for long 489 displacements. 490 491'-L' 492'--keep-locals' 493 Keep (in the symbol table) local symbols. These symbols start with 494 system-specific local label prefixes, typically '.L' for ELF 495 systems or 'L' for traditional a.out systems. *Note Symbol 496 Names::. 497 498'--listing-lhs-width=NUMBER' 499 Set the maximum width, in words, of the output data column for an 500 assembler listing to NUMBER. 501 502'--listing-lhs-width2=NUMBER' 503 Set the maximum width, in words, of the output data column for 504 continuation lines in an assembler listing to NUMBER. 505 506'--listing-rhs-width=NUMBER' 507 Set the maximum width of an input source line, as displayed in a 508 listing, to NUMBER bytes. 509 510'--listing-cont-lines=NUMBER' 511 Set the maximum number of lines printed in a listing for a single 512 line of input to NUMBER + 1. 513 514'--no-pad-sections' 515 Stop the assembler for padding the ends of output sections to the 516 alignment of that section. The default is to pad the sections, but 517 this can waste space which might be needed on targets which have 518 tight memory constraints. 519 520'-o OBJFILE' 521 Name the object-file output from 'as' OBJFILE. 522 523'-R' 524 Fold the data section into the text section. 525 526'--hash-size=NUMBER' 527 Set the default size of GAS's hash tables to a prime number close 528 to NUMBER. Increasing this value can reduce the length of time it 529 takes the assembler to perform its tasks, at the expense of 530 increasing the assembler's memory requirements. Similarly reducing 531 this value can reduce the memory requirements at the expense of 532 speed. 533 534'--reduce-memory-overheads' 535 This option reduces GAS's memory requirements, at the expense of 536 making the assembly processes slower. Currently this switch is a 537 synonym for '--hash-size=4051', but in the future it may have other 538 effects as well. 539 540'--sectname-subst' 541 Honor substitution sequences in section names. *Note '.section 542 NAME': Section Name Substitutions. 543 544'--statistics' 545 Print the maximum space (in bytes) and total time (in seconds) used 546 by assembly. 547 548'--strip-local-absolute' 549 Remove local absolute symbols from the outgoing symbol table. 550 551'-v' 552'-version' 553 Print the 'as' version. 554 555'--version' 556 Print the 'as' version and exit. 557 558'-W' 559'--no-warn' 560 Suppress warning messages. 561 562'--fatal-warnings' 563 Treat warnings as errors. 564 565'--warn' 566 Don't suppress warning messages or treat them as errors. 567 568'-w' 569 Ignored. 570 571'-x' 572 Ignored. 573 574'-Z' 575 Generate an object file even after errors. 576 577'-- | FILES ...' 578 Standard input, or source files to assemble. 579 580 *Note AArch64 Options::, for the options available when as is 581configured for the 64-bit mode of the ARM Architecture (AArch64). 582 583 *Note Alpha Options::, for the options available when as is 584configured for an Alpha processor. 585 586 The following options are available when as is configured for an ARC 587processor. 588 589'-mcpu=CPU' 590 This option selects the core processor variant. 591'-EB | -EL' 592 Select either big-endian (-EB) or little-endian (-EL) output. 593'-mcode-density' 594 Enable Code Density extenssion instructions. 595 596 The following options are available when as is configured for the ARM 597processor family. 598 599'-mcpu=PROCESSOR[+EXTENSION...]' 600 Specify which ARM processor variant is the target. 601'-march=ARCHITECTURE[+EXTENSION...]' 602 Specify which ARM architecture variant is used by the target. 603'-mfpu=FLOATING-POINT-FORMAT' 604 Select which Floating Point architecture is the target. 605'-mfloat-abi=ABI' 606 Select which floating point ABI is in use. 607'-mthumb' 608 Enable Thumb only instruction decoding. 609'-mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant' 610 Select which procedure calling convention is in use. 611'-EB | -EL' 612 Select either big-endian (-EB) or little-endian (-EL) output. 613'-mthumb-interwork' 614 Specify that the code has been generated with interworking between 615 Thumb and ARM code in mind. 616'-mccs' 617 Turns on CodeComposer Studio assembly syntax compatibility mode. 618'-k' 619 Specify that PIC code has been generated. 620 621 *Note Blackfin Options::, for the options available when as is 622configured for the Blackfin processor family. 623 624 See the info pages for documentation of the CRIS-specific options. 625 626 The following options are available when as is configured for a D10V 627processor. 628'-O' 629 Optimize output by parallelizing instructions. 630 631 The following options are available when as is configured for a D30V 632processor. 633'-O' 634 Optimize output by parallelizing instructions. 635 636'-n' 637 Warn when nops are generated. 638 639'-N' 640 Warn when a nop after a 32-bit multiply instruction is generated. 641 642 The following options are available when as is configured for the 643Adapteva EPIPHANY series. 644 645 *Note Epiphany Options::, for the options available when as is 646configured for an Epiphany processor. 647 648 *Note i386-Options::, for the options available when as is configured 649for an i386 processor. 650 651 The following options are available when as is configured for the 652Intel 80960 processor. 653 654'-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC' 655 Specify which variant of the 960 architecture is the target. 656 657'-b' 658 Add code to collect statistics about branches taken. 659 660'-no-relax' 661 Do not alter compare-and-branch instructions for long 662 displacements; error if necessary. 663 664 The following options are available when as is configured for the 665Ubicom IP2K series. 666 667'-mip2022ext' 668 Specifies that the extended IP2022 instructions are allowed. 669 670'-mip2022' 671 Restores the default behaviour, which restricts the permitted 672 instructions to just the basic IP2022 ones. 673 674 The following options are available when as is configured for the 675Renesas M32C and M16C processors. 676 677'-m32c' 678 Assemble M32C instructions. 679 680'-m16c' 681 Assemble M16C instructions (the default). 682 683'-relax' 684 Enable support for link-time relaxations. 685 686'-h-tick-hex' 687 Support H'00 style hex constants in addition to 0x00 style. 688 689 The following options are available when as is configured for the 690Renesas M32R (formerly Mitsubishi M32R) series. 691 692'--m32rx' 693 Specify which processor in the M32R family is the target. The 694 default is normally the M32R, but this option changes it to the 695 M32RX. 696 697'--warn-explicit-parallel-conflicts or --Wp' 698 Produce warning messages when questionable parallel constructs are 699 encountered. 700 701'--no-warn-explicit-parallel-conflicts or --Wnp' 702 Do not produce warning messages when questionable parallel 703 constructs are encountered. 704 705 The following options are available when as is configured for the 706Motorola 68000 series. 707 708'-l' 709 Shorten references to undefined symbols, to one word instead of 710 two. 711 712'-m68000 | -m68008 | -m68010 | -m68020 | -m68030' 713'| -m68040 | -m68060 | -m68302 | -m68331 | -m68332' 714'| -m68333 | -m68340 | -mcpu32 | -m5200' 715 Specify what processor in the 68000 family is the target. The 716 default is normally the 68020, but this can be changed at 717 configuration time. 718 719'-m68881 | -m68882 | -mno-68881 | -mno-68882' 720 The target machine does (or does not) have a floating-point 721 coprocessor. The default is to assume a coprocessor for 68020, 722 68030, and cpu32. Although the basic 68000 is not compatible with 723 the 68881, a combination of the two can be specified, since it's 724 possible to do emulation of the coprocessor instructions with the 725 main processor. 726 727'-m68851 | -mno-68851' 728 The target machine does (or does not) have a memory-management unit 729 coprocessor. The default is to assume an MMU for 68020 and up. 730 731 *Note Nios II Options::, for the options available when as is 732configured for an Altera Nios II processor. 733 734 For details about the PDP-11 machine dependent features options, see 735*note PDP-11-Options::. 736 737'-mpic | -mno-pic' 738 Generate position-independent (or position-dependent) code. The 739 default is '-mpic'. 740 741'-mall' 742'-mall-extensions' 743 Enable all instruction set extensions. This is the default. 744 745'-mno-extensions' 746 Disable all instruction set extensions. 747 748'-mEXTENSION | -mno-EXTENSION' 749 Enable (or disable) a particular instruction set extension. 750 751'-mCPU' 752 Enable the instruction set extensions supported by a particular 753 CPU, and disable all other extensions. 754 755'-mMACHINE' 756 Enable the instruction set extensions supported by a particular 757 machine model, and disable all other extensions. 758 759 The following options are available when as is configured for a 760picoJava processor. 761 762'-mb' 763 Generate "big endian" format output. 764 765'-ml' 766 Generate "little endian" format output. 767 768 The following options are available when as is configured for the 769Motorola 68HC11 or 68HC12 series. 770 771'-m68hc11 | -m68hc12 | -m68hcs12 | -mm9s12x | -mm9s12xg' 772 Specify what processor is the target. The default is defined by 773 the configuration option when building the assembler. 774 775'--xgate-ramoffset' 776 Instruct the linker to offset RAM addresses from S12X address space 777 into XGATE address space. 778 779'-mshort' 780 Specify to use the 16-bit integer ABI. 781 782'-mlong' 783 Specify to use the 32-bit integer ABI. 784 785'-mshort-double' 786 Specify to use the 32-bit double ABI. 787 788'-mlong-double' 789 Specify to use the 64-bit double ABI. 790 791'--force-long-branches' 792 Relative branches are turned into absolute ones. This concerns 793 conditional branches, unconditional branches and branches to a sub 794 routine. 795 796'-S | --short-branches' 797 Do not turn relative branches into absolute ones when the offset is 798 out of range. 799 800'--strict-direct-mode' 801 Do not turn the direct addressing mode into extended addressing 802 mode when the instruction does not support direct addressing mode. 803 804'--print-insn-syntax' 805 Print the syntax of instruction in case of error. 806 807'--print-opcodes' 808 Print the list of instructions with syntax and then exit. 809 810'--generate-example' 811 Print an example of instruction for each possible instruction and 812 then exit. This option is only useful for testing 'as'. 813 814 The following options are available when 'as' is configured for the 815SPARC architecture: 816 817'-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite' 818'-Av8plus | -Av8plusa | -Av9 | -Av9a' 819 Explicitly select a variant of the SPARC architecture. 820 821 '-Av8plus' and '-Av8plusa' select a 32 bit environment. '-Av9' and 822 '-Av9a' select a 64 bit environment. 823 824 '-Av8plusa' and '-Av9a' enable the SPARC V9 instruction set with 825 UltraSPARC extensions. 826 827'-xarch=v8plus | -xarch=v8plusa' 828 For compatibility with the Solaris v9 assembler. These options are 829 equivalent to -Av8plus and -Av8plusa, respectively. 830 831'-bump' 832 Warn when the assembler switches to another architecture. 833 834 The following options are available when as is configured for the 835'c54x architecture. 836 837'-mfar-mode' 838 Enable extended addressing mode. All addresses and relocations 839 will assume extended addressing (usually 23 bits). 840'-mcpu=CPU_VERSION' 841 Sets the CPU version being compiled for. 842'-merrors-to-file FILENAME' 843 Redirect error output to a file, for broken systems which don't 844 support such behaviour in the shell. 845 846 The following options are available when as is configured for a MIPS 847processor. 848 849'-G NUM' 850 This option sets the largest size of an object that can be 851 referenced implicitly with the 'gp' register. It is only accepted 852 for targets that use ECOFF format, such as a DECstation running 853 Ultrix. The default value is 8. 854 855'-EB' 856 Generate "big endian" format output. 857 858'-EL' 859 Generate "little endian" format output. 860 861'-mips1' 862'-mips2' 863'-mips3' 864'-mips4' 865'-mips5' 866'-mips32' 867'-mips32r2' 868'-mips32r3' 869'-mips32r5' 870'-mips32r6' 871'-mips64' 872'-mips64r2' 873'-mips64r3' 874'-mips64r5' 875'-mips64r6' 876 Generate code for a particular MIPS Instruction Set Architecture 877 level. '-mips1' is an alias for '-march=r3000', '-mips2' is an 878 alias for '-march=r6000', '-mips3' is an alias for '-march=r4000' 879 and '-mips4' is an alias for '-march=r8000'. '-mips5', '-mips32', 880 '-mips32r2', '-mips32r3', '-mips32r5', '-mips32r6', '-mips64', 881 '-mips64r2', '-mips64r3', '-mips64r5', and '-mips64r6' correspond 882 to generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3, 883 MIPS32 Release 5, MIPS32 Release 6, MIPS64, MIPS64 Release 2, 884 MIPS64 Release 3, MIPS64 Release 5, and MIPS64 Release 6 ISA 885 processors, respectively. 886 887'-march=CPU' 888 Generate code for a particular MIPS CPU. 889 890'-mtune=CPU' 891 Schedule and tune for a particular MIPS CPU. 892 893'-mfix7000' 894'-mno-fix7000' 895 Cause nops to be inserted if the read of the destination register 896 of an mfhi or mflo instruction occurs in the following two 897 instructions. 898 899'-mfix-rm7000' 900'-mno-fix-rm7000' 901 Cause nops to be inserted if a dmult or dmultu instruction is 902 followed by a load instruction. 903 904'-mdebug' 905'-no-mdebug' 906 Cause stabs-style debugging output to go into an ECOFF-style 907 .mdebug section instead of the standard ELF .stabs sections. 908 909'-mpdr' 910'-mno-pdr' 911 Control generation of '.pdr' sections. 912 913'-mgp32' 914'-mfp32' 915 The register sizes are normally inferred from the ISA and ABI, but 916 these flags force a certain group of registers to be treated as 32 917 bits wide at all times. '-mgp32' controls the size of 918 general-purpose registers and '-mfp32' controls the size of 919 floating-point registers. 920 921'-mgp64' 922'-mfp64' 923 The register sizes are normally inferred from the ISA and ABI, but 924 these flags force a certain group of registers to be treated as 64 925 bits wide at all times. '-mgp64' controls the size of 926 general-purpose registers and '-mfp64' controls the size of 927 floating-point registers. 928 929'-mfpxx' 930 The register sizes are normally inferred from the ISA and ABI, but 931 using this flag in combination with '-mabi=32' enables an ABI 932 variant which will operate correctly with floating-point registers 933 which are 32 or 64 bits wide. 934 935'-modd-spreg' 936'-mno-odd-spreg' 937 Enable use of floating-point operations on odd-numbered 938 single-precision registers when supported by the ISA. '-mfpxx' 939 implies '-mno-odd-spreg', otherwise the default is '-modd-spreg'. 940 941'-mips16' 942'-no-mips16' 943 Generate code for the MIPS 16 processor. This is equivalent to 944 putting '.set mips16' at the start of the assembly file. 945 '-no-mips16' turns off this option. 946 947'-mmicromips' 948'-mno-micromips' 949 Generate code for the microMIPS processor. This is equivalent to 950 putting '.set micromips' at the start of the assembly file. 951 '-mno-micromips' turns off this option. This is equivalent to 952 putting '.set nomicromips' at the start of the assembly file. 953 954'-msmartmips' 955'-mno-smartmips' 956 Enables the SmartMIPS extension to the MIPS32 instruction set. 957 This is equivalent to putting '.set smartmips' at the start of the 958 assembly file. '-mno-smartmips' turns off this option. 959 960'-mips3d' 961'-no-mips3d' 962 Generate code for the MIPS-3D Application Specific Extension. This 963 tells the assembler to accept MIPS-3D instructions. '-no-mips3d' 964 turns off this option. 965 966'-mdmx' 967'-no-mdmx' 968 Generate code for the MDMX Application Specific Extension. This 969 tells the assembler to accept MDMX instructions. '-no-mdmx' turns 970 off this option. 971 972'-mdsp' 973'-mno-dsp' 974 Generate code for the DSP Release 1 Application Specific Extension. 975 This tells the assembler to accept DSP Release 1 instructions. 976 '-mno-dsp' turns off this option. 977 978'-mdspr2' 979'-mno-dspr2' 980 Generate code for the DSP Release 2 Application Specific Extension. 981 This option implies '-mdsp'. This tells the assembler to accept 982 DSP Release 2 instructions. '-mno-dspr2' turns off this option. 983 984'-mdspr3' 985'-mno-dspr3' 986 Generate code for the DSP Release 3 Application Specific Extension. 987 This option implies '-mdsp' and '-mdspr2'. This tells the 988 assembler to accept DSP Release 3 instructions. '-mno-dspr3' turns 989 off this option. 990 991'-mmsa' 992'-mno-msa' 993 Generate code for the MIPS SIMD Architecture Extension. This tells 994 the assembler to accept MSA instructions. '-mno-msa' turns off 995 this option. 996 997'-mxpa' 998'-mno-xpa' 999 Generate code for the MIPS eXtended Physical Address (XPA) 1000 Extension. This tells the assembler to accept XPA instructions. 1001 '-mno-xpa' turns off this option. 1002 1003'-mmt' 1004'-mno-mt' 1005 Generate code for the MT Application Specific Extension. This 1006 tells the assembler to accept MT instructions. '-mno-mt' turns off 1007 this option. 1008 1009'-mmcu' 1010'-mno-mcu' 1011 Generate code for the MCU Application Specific Extension. This 1012 tells the assembler to accept MCU instructions. '-mno-mcu' turns 1013 off this option. 1014 1015'-minsn32' 1016'-mno-insn32' 1017 Only use 32-bit instruction encodings when generating code for the 1018 microMIPS processor. This option inhibits the use of any 16-bit 1019 instructions. This is equivalent to putting '.set insn32' at the 1020 start of the assembly file. '-mno-insn32' turns off this option. 1021 This is equivalent to putting '.set noinsn32' at the start of the 1022 assembly file. By default '-mno-insn32' is selected, allowing all 1023 instructions to be used. 1024 1025'--construct-floats' 1026'--no-construct-floats' 1027 The '--no-construct-floats' option disables the construction of 1028 double width floating point constants by loading the two halves of 1029 the value into the two single width floating point registers that 1030 make up the double width register. By default '--construct-floats' 1031 is selected, allowing construction of these floating point 1032 constants. 1033 1034'--relax-branch' 1035'--no-relax-branch' 1036 The '--relax-branch' option enables the relaxation of out-of-range 1037 branches. By default '--no-relax-branch' is selected, causing any 1038 out-of-range branches to produce an error. 1039 1040'-mignore-branch-isa' 1041'-mno-ignore-branch-isa' 1042 Ignore branch checks for invalid transitions between ISA modes. 1043 The semantics of branches does not provide for an ISA mode switch, 1044 so in most cases the ISA mode a branch has been encoded for has to 1045 be the same as the ISA mode of the branch's target label. 1046 Therefore GAS has checks implemented that verify in branch assembly 1047 that the two ISA modes match. '-mignore-branch-isa' disables these 1048 checks. By default '-mno-ignore-branch-isa' is selected, causing 1049 any invalid branch requiring a transition between ISA modes to 1050 produce an error. 1051 1052'-mnan=ENCODING' 1053 Select between the IEEE 754-2008 ('-mnan=2008') or the legacy 1054 ('-mnan=legacy') NaN encoding format. The latter is the default. 1055 1056'--emulation=NAME' 1057 This option was formerly used to switch between ELF and ECOFF 1058 output on targets like IRIX 5 that supported both. MIPS ECOFF 1059 support was removed in GAS 2.24, so the option now serves little 1060 purpose. It is retained for backwards compatibility. 1061 1062 The available configuration names are: 'mipself', 'mipslelf' and 1063 'mipsbelf'. Choosing 'mipself' now has no effect, since the output 1064 is always ELF. 'mipslelf' and 'mipsbelf' select little- and 1065 big-endian output respectively, but '-EL' and '-EB' are now the 1066 preferred options instead. 1067 1068'-nocpp' 1069 'as' ignores this option. It is accepted for compatibility with 1070 the native tools. 1071 1072'--trap' 1073'--no-trap' 1074'--break' 1075'--no-break' 1076 Control how to deal with multiplication overflow and division by 1077 zero. '--trap' or '--no-break' (which are synonyms) take a trap 1078 exception (and only work for Instruction Set Architecture level 2 1079 and higher); '--break' or '--no-trap' (also synonyms, and the 1080 default) take a break exception. 1081 1082'-n' 1083 When this option is used, 'as' will issue a warning every time it 1084 generates a nop instruction from a macro. 1085 1086 The following options are available when as is configured for an 1087MCore processor. 1088 1089'-jsri2bsr' 1090'-nojsri2bsr' 1091 Enable or disable the JSRI to BSR transformation. By default this 1092 is enabled. The command line option '-nojsri2bsr' can be used to 1093 disable it. 1094 1095'-sifilter' 1096'-nosifilter' 1097 Enable or disable the silicon filter behaviour. By default this is 1098 disabled. The default can be overridden by the '-sifilter' command 1099 line option. 1100 1101'-relax' 1102 Alter jump instructions for long displacements. 1103 1104'-mcpu=[210|340]' 1105 Select the cpu type on the target hardware. This controls which 1106 instructions can be assembled. 1107 1108'-EB' 1109 Assemble for a big endian target. 1110 1111'-EL' 1112 Assemble for a little endian target. 1113 1114 *Note Meta Options::, for the options available when as is configured 1115for a Meta processor. 1116 1117 See the info pages for documentation of the MMIX-specific options. 1118 1119 *Note NDS32 Options::, for the options available when as is 1120configured for a NDS32 processor. 1121 1122 *Note PowerPC-Opts::, for the options available when as is configured 1123for a PowerPC processor. 1124 1125 *Note RISC-V-Opts::, for the options available when as is configured 1126for a RISC-V processor. 1127 1128 See the info pages for documentation of the RX-specific options. 1129 1130 The following options are available when as is configured for the 1131s390 processor family. 1132 1133'-m31' 1134'-m64' 1135 Select the word size, either 31/32 bits or 64 bits. 1136'-mesa' 1137'-mzarch' 1138 Select the architecture mode, either the Enterprise System 1139 Architecture (esa) or the z/Architecture mode (zarch). 1140'-march=PROCESSOR' 1141 Specify which s390 processor variant is the target, 'g5' (or 1142 'arch3'), 'g6', 'z900' (or 'arch5'), 'z990' (or 'arch6'), 'z9-109', 1143 'z9-ec' (or 'arch7'), 'z10' (or 'arch8'), 'z196' (or 'arch9'), 1144 'zEC12' (or 'arch10'), 'z13' (or 'arch11'), or 'arch12'. 1145'-mregnames' 1146'-mno-regnames' 1147 Allow or disallow symbolic names for registers. 1148'-mwarn-areg-zero' 1149 Warn whenever the operand for a base or index register has been 1150 specified but evaluates to zero. 1151 1152 *Note TIC6X Options::, for the options available when as is 1153configured for a TMS320C6000 processor. 1154 1155 *Note TILE-Gx Options::, for the options available when as is 1156configured for a TILE-Gx processor. 1157 1158 *Note Visium Options::, for the options available when as is 1159configured for a Visium processor. 1160 1161 *Note Xtensa Options::, for the options available when as is 1162configured for an Xtensa processor. 1163 1164 The following options are available when as is configured for a Z80 1165family processor. 1166'-z80' 1167 Assemble for Z80 processor. 1168'-r800' 1169 Assemble for R800 processor. 1170'-ignore-undocumented-instructions' 1171'-Wnud' 1172 Assemble undocumented Z80 instructions that also work on R800 1173 without warning. 1174'-ignore-unportable-instructions' 1175'-Wnup' 1176 Assemble all undocumented Z80 instructions without warning. 1177'-warn-undocumented-instructions' 1178'-Wud' 1179 Issue a warning for undocumented Z80 instructions that also work on 1180 R800. 1181'-warn-unportable-instructions' 1182'-Wup' 1183 Issue a warning for undocumented Z80 instructions that do not work 1184 on R800. 1185'-forbid-undocumented-instructions' 1186'-Fud' 1187 Treat all undocumented instructions as errors. 1188'-forbid-unportable-instructions' 1189'-Fup' 1190 Treat undocumented Z80 instructions that do not work on R800 as 1191 errors. 1192 1193* Menu: 1194 1195* Manual:: Structure of this Manual 1196* GNU Assembler:: The GNU Assembler 1197* Object Formats:: Object File Formats 1198* Command Line:: Command Line 1199* Input Files:: Input Files 1200* Object:: Output (Object) File 1201* Errors:: Error and Warning Messages 1202 1203 1204File: as.info, Node: Manual, Next: GNU Assembler, Up: Overview 1205 12061.1 Structure of this Manual 1207============================ 1208 1209This manual is intended to describe what you need to know to use GNU 1210'as'. We cover the syntax expected in source files, including notation 1211for symbols, constants, and expressions; the directives that 'as' 1212understands; and of course how to invoke 'as'. 1213 1214 This manual also describes some of the machine-dependent features of 1215various flavors of the assembler. 1216 1217 On the other hand, this manual is _not_ intended as an introduction 1218to programming in assembly language--let alone programming in general! 1219In a similar vein, we make no attempt to introduce the machine 1220architecture; we do _not_ describe the instruction set, standard 1221mnemonics, registers or addressing modes that are standard to a 1222particular architecture. You may want to consult the manufacturer's 1223machine architecture manual for this information. 1224 1225 1226File: as.info, Node: GNU Assembler, Next: Object Formats, Prev: Manual, Up: Overview 1227 12281.2 The GNU Assembler 1229===================== 1230 1231GNU 'as' is really a family of assemblers. If you use (or have used) 1232the GNU assembler on one architecture, you should find a fairly similar 1233environment when you use it on another architecture. Each version has 1234much in common with the others, including object file formats, most 1235assembler directives (often called "pseudo-ops") and assembler syntax. 1236 1237 'as' is primarily intended to assemble the output of the GNU C 1238compiler 'gcc' for use by the linker 'ld'. Nevertheless, we've tried to 1239make 'as' assemble correctly everything that other assemblers for the 1240same machine would assemble. Any exceptions are documented explicitly 1241(*note Machine Dependencies::). This doesn't mean 'as' always uses the 1242same syntax as another assembler for the same architecture; for example, 1243we know of several incompatible versions of 680x0 assembly language 1244syntax. 1245 1246 Unlike older assemblers, 'as' is designed to assemble a source 1247program in one pass of the source file. This has a subtle impact on the 1248'.org' directive (*note '.org': Org.). 1249 1250 1251File: as.info, Node: Object Formats, Next: Command Line, Prev: GNU Assembler, Up: Overview 1252 12531.3 Object File Formats 1254======================= 1255 1256The GNU assembler can be configured to produce several alternative 1257object file formats. For the most part, this does not affect how you 1258write assembly language programs; but directives for debugging symbols 1259are typically different in different file formats. *Note Symbol 1260Attributes: Symbol Attributes. 1261 1262 1263File: as.info, Node: Command Line, Next: Input Files, Prev: Object Formats, Up: Overview 1264 12651.4 Command Line 1266================ 1267 1268After the program name 'as', the command line may contain options and 1269file names. Options may appear in any order, and may be before, after, 1270or between file names. The order of file names is significant. 1271 1272 '--' (two hyphens) by itself names the standard input file 1273explicitly, as one of the files for 'as' to assemble. 1274 1275 Except for '--' any command line argument that begins with a hyphen 1276('-') is an option. Each option changes the behavior of 'as'. No 1277option changes the way another option works. An option is a '-' 1278followed by one or more letters; the case of the letter is important. 1279All options are optional. 1280 1281 Some options expect exactly one file name to follow them. The file 1282name may either immediately follow the option's letter (compatible with 1283older assemblers) or it may be the next command argument (GNU standard). 1284These two command lines are equivalent: 1285 1286 as -o my-object-file.o mumble.s 1287 as -omy-object-file.o mumble.s 1288 1289 1290File: as.info, Node: Input Files, Next: Object, Prev: Command Line, Up: Overview 1291 12921.5 Input Files 1293=============== 1294 1295We use the phrase "source program", abbreviated "source", to describe 1296the program input to one run of 'as'. The program may be in one or more 1297files; how the source is partitioned into files doesn't change the 1298meaning of the source. 1299 1300 The source program is a concatenation of the text in all the files, 1301in the order specified. 1302 1303 Each time you run 'as' it assembles exactly one source program. The 1304source program is made up of one or more files. (The standard input is 1305also a file.) 1306 1307 You give 'as' a command line that has zero or more input file names. 1308The input files are read (from left file name to right). A command line 1309argument (in any position) that has no special meaning is taken to be an 1310input file name. 1311 1312 If you give 'as' no file names it attempts to read one input file 1313from the 'as' standard input, which is normally your terminal. You may 1314have to type <ctl-D> to tell 'as' there is no more program to assemble. 1315 1316 Use '--' if you need to explicitly name the standard input file in 1317your command line. 1318 1319 If the source is empty, 'as' produces a small, empty object file. 1320 1321Filenames and Line-numbers 1322-------------------------- 1323 1324There are two ways of locating a line in the input file (or files) and 1325either may be used in reporting error messages. One way refers to a 1326line number in a physical file; the other refers to a line number in a 1327"logical" file. *Note Error and Warning Messages: Errors. 1328 1329 "Physical files" are those files named in the command line given to 1330'as'. 1331 1332 "Logical files" are simply names declared explicitly by assembler 1333directives; they bear no relation to physical files. Logical file names 1334help error messages reflect the original source file, when 'as' source 1335is itself synthesized from other files. 'as' understands the '#' 1336directives emitted by the 'gcc' preprocessor. See also *note '.file': 1337File. 1338 1339 1340File: as.info, Node: Object, Next: Errors, Prev: Input Files, Up: Overview 1341 13421.6 Output (Object) File 1343======================== 1344 1345Every time you run 'as' it produces an output file, which is your 1346assembly language program translated into numbers. This file is the 1347object file. Its default name is 'a.out'. You can give it another name 1348by using the '-o' option. Conventionally, object file names end with 1349'.o'. The default name is used for historical reasons: older assemblers 1350were capable of assembling self-contained programs directly into a 1351runnable program. (For some formats, this isn't currently possible, but 1352it can be done for the 'a.out' format.) 1353 1354 The object file is meant for input to the linker 'ld'. It contains 1355assembled program code, information to help 'ld' integrate the assembled 1356program into a runnable file, and (optionally) symbolic information for 1357the debugger. 1358 1359 1360File: as.info, Node: Errors, Prev: Object, Up: Overview 1361 13621.7 Error and Warning Messages 1363============================== 1364 1365'as' may write warnings and error messages to the standard error file 1366(usually your terminal). This should not happen when a compiler runs 1367'as' automatically. Warnings report an assumption made so that 'as' 1368could keep assembling a flawed program; errors report a grave problem 1369that stops the assembly. 1370 1371 Warning messages have the format 1372 1373 file_name:NNN:Warning Message Text 1374 1375(where NNN is a line number). If both a logical file name (*note 1376'.file': File.) and a logical line number (*note '.line': Line.) have 1377been given then they will be used, otherwise the file name and line 1378number in the current assembler source file will be used. The message 1379text is intended to be self explanatory (in the grand Unix tradition). 1380 1381 Note the file name must be set via the logical version of the '.file' 1382directive, not the DWARF2 version of the '.file' directive. For 1383example: 1384 1385 .file 2 "bar.c" 1386 error_assembler_source 1387 .file "foo.c" 1388 .line 30 1389 error_c_source 1390 1391 produces this output: 1392 1393 Assembler messages: 1394 asm.s:2: Error: no such instruction: `error_assembler_source' 1395 foo.c:31: Error: no such instruction: `error_c_source' 1396 1397 Error messages have the format 1398 1399 file_name:NNN:FATAL:Error Message Text 1400 1401 The file name and line number are derived as for warning messages. 1402The actual message text may be rather less explanatory because many of 1403them aren't supposed to happen. 1404 1405 1406File: as.info, Node: Invoking, Next: Syntax, Prev: Overview, Up: Top 1407 14082 Command-Line Options 1409********************** 1410 1411This chapter describes command-line options available in _all_ versions 1412of the GNU assembler; see *note Machine Dependencies::, for options 1413specific to particular machine architectures. 1414 1415 If you are invoking 'as' via the GNU C compiler, you can use the 1416'-Wa' option to pass arguments through to the assembler. The assembler 1417arguments must be separated from each other (and the '-Wa') by commas. 1418For example: 1419 1420 gcc -c -g -O -Wa,-alh,-L file.c 1421 1422This passes two options to the assembler: '-alh' (emit a listing to 1423standard output with high-level and assembly source) and '-L' (retain 1424local symbols in the symbol table). 1425 1426 Usually you do not need to use this '-Wa' mechanism, since many 1427compiler command-line options are automatically passed to the assembler 1428by the compiler. (You can call the GNU compiler driver with the '-v' 1429option to see precisely what options it passes to each compilation pass, 1430including the assembler.) 1431 1432* Menu: 1433 1434* a:: -a[cdghlns] enable listings 1435* alternate:: -alternate enable alternate macro syntax 1436* D:: -D for compatibility 1437* f:: -f to work faster 1438* I:: -I for .include search path 1439* K:: -K for difference tables 1440 1441* L:: -L to retain local symbols 1442* listing:: -listing-XXX to configure listing output 1443* M:: -M or -mri to assemble in MRI compatibility mode 1444* MD:: -MD for dependency tracking 1445* no-pad-sections:: -no-pad-sections to stop section padding 1446* o:: -o to name the object file 1447* R:: -R to join data and text sections 1448* statistics:: -statistics to see statistics about assembly 1449* traditional-format:: -traditional-format for compatible output 1450* v:: -v to announce version 1451* W:: -W, -no-warn, -warn, -fatal-warnings to control warnings 1452* Z:: -Z to make object file even after errors 1453 1454 1455File: as.info, Node: a, Next: alternate, Up: Invoking 1456 14572.1 Enable Listings: '-a[cdghlns]' 1458================================== 1459 1460These options enable listing output from the assembler. By itself, '-a' 1461requests high-level, assembly, and symbols listing. You can use other 1462letters to select specific options for the list: '-ah' requests a 1463high-level language listing, '-al' requests an output-program assembly 1464listing, and '-as' requests a symbol table listing. High-level listings 1465require that a compiler debugging option like '-g' be used, and that 1466assembly listings ('-al') be requested also. 1467 1468 Use the '-ag' option to print a first section with general assembly 1469information, like as version, switches passed, or time stamp. 1470 1471 Use the '-ac' option to omit false conditionals from a listing. Any 1472lines which are not assembled because of a false '.if' (or '.ifdef', or 1473any other conditional), or a true '.if' followed by an '.else', will be 1474omitted from the listing. 1475 1476 Use the '-ad' option to omit debugging directives from the listing. 1477 1478 Once you have specified one of these options, you can further control 1479listing output and its appearance using the directives '.list', 1480'.nolist', '.psize', '.eject', '.title', and '.sbttl'. The '-an' option 1481turns off all forms processing. If you do not request listing output 1482with one of the '-a' options, the listing-control directives have no 1483effect. 1484 1485 The letters after '-a' may be combined into one option, _e.g._, 1486'-aln'. 1487 1488 Note if the assembler source is coming from the standard input (e.g., 1489because it is being created by 'gcc' and the '-pipe' command line switch 1490is being used) then the listing will not contain any comments or 1491preprocessor directives. This is because the listing code buffers input 1492source lines from stdin only after they have been preprocessed by the 1493assembler. This reduces memory usage and makes the code more efficient. 1494 1495 1496File: as.info, Node: alternate, Next: D, Prev: a, Up: Invoking 1497 14982.2 '--alternate' 1499================= 1500 1501Begin in alternate macro mode, see *note '.altmacro': Altmacro. 1502 1503 1504File: as.info, Node: D, Next: f, Prev: alternate, Up: Invoking 1505 15062.3 '-D' 1507======== 1508 1509This option has no effect whatsoever, but it is accepted to make it more 1510likely that scripts written for other assemblers also work with 'as'. 1511 1512 1513File: as.info, Node: f, Next: I, Prev: D, Up: Invoking 1514 15152.4 Work Faster: '-f' 1516===================== 1517 1518'-f' should only be used when assembling programs written by a (trusted) 1519compiler. '-f' stops the assembler from doing whitespace and comment 1520preprocessing on the input file(s) before assembling them. *Note 1521Preprocessing: Preprocessing. 1522 1523 _Warning:_ if you use '-f' when the files actually need to be 1524 preprocessed (if they contain comments, for example), 'as' does not 1525 work correctly. 1526 1527 1528File: as.info, Node: I, Next: K, Prev: f, Up: Invoking 1529 15302.5 '.include' Search Path: '-I' PATH 1531===================================== 1532 1533Use this option to add a PATH to the list of directories 'as' searches 1534for files specified in '.include' directives (*note '.include': 1535Include.). You may use '-I' as many times as necessary to include a 1536variety of paths. The current working directory is always searched 1537first; after that, 'as' searches any '-I' directories in the same order 1538as they were specified (left to right) on the command line. 1539 1540 1541File: as.info, Node: K, Next: L, Prev: I, Up: Invoking 1542 15432.6 Difference Tables: '-K' 1544=========================== 1545 1546'as' sometimes alters the code emitted for directives of the form '.word 1547SYM1-SYM2'. *Note '.word': Word. You can use the '-K' option if you 1548want a warning issued when this is done. 1549 1550 1551File: as.info, Node: L, Next: listing, Prev: K, Up: Invoking 1552 15532.7 Include Local Symbols: '-L' 1554=============================== 1555 1556Symbols beginning with system-specific local label prefixes, typically 1557'.L' for ELF systems or 'L' for traditional a.out systems, are called 1558"local symbols". *Note Symbol Names::. Normally you do not see such 1559symbols when debugging, because they are intended for the use of 1560programs (like compilers) that compose assembler programs, not for your 1561notice. Normally both 'as' and 'ld' discard such symbols, so you do not 1562normally debug with them. 1563 1564 This option tells 'as' to retain those local symbols in the object 1565file. Usually if you do this you also tell the linker 'ld' to preserve 1566those symbols. 1567 1568 1569File: as.info, Node: listing, Next: M, Prev: L, Up: Invoking 1570 15712.8 Configuring listing output: '--listing' 1572=========================================== 1573 1574The listing feature of the assembler can be enabled via the command line 1575switch '-a' (*note a::). This feature combines the input source file(s) 1576with a hex dump of the corresponding locations in the output object 1577file, and displays them as a listing file. The format of this listing 1578can be controlled by directives inside the assembler source (i.e., 1579'.list' (*note List::), '.title' (*note Title::), '.sbttl' (*note 1580Sbttl::), '.psize' (*note Psize::), and '.eject' (*note Eject::) and 1581also by the following switches: 1582 1583'--listing-lhs-width='number'' 1584 Sets the maximum width, in words, of the first line of the hex byte 1585 dump. This dump appears on the left hand side of the listing 1586 output. 1587 1588'--listing-lhs-width2='number'' 1589 Sets the maximum width, in words, of any further lines of the hex 1590 byte dump for a given input source line. If this value is not 1591 specified, it defaults to being the same as the value specified for 1592 '--listing-lhs-width'. If neither switch is used the default is to 1593 one. 1594 1595'--listing-rhs-width='number'' 1596 Sets the maximum width, in characters, of the source line that is 1597 displayed alongside the hex dump. The default value for this 1598 parameter is 100. The source line is displayed on the right hand 1599 side of the listing output. 1600 1601'--listing-cont-lines='number'' 1602 Sets the maximum number of continuation lines of hex dump that will 1603 be displayed for a given single line of source input. The default 1604 value is 4. 1605 1606 1607File: as.info, Node: M, Next: MD, Prev: listing, Up: Invoking 1608 16092.9 Assemble in MRI Compatibility Mode: '-M' 1610============================================ 1611 1612The '-M' or '--mri' option selects MRI compatibility mode. This changes 1613the syntax and pseudo-op handling of 'as' to make it compatible with the 1614'ASM68K' or the 'ASM960' (depending upon the configured target) 1615assembler from Microtec Research. The exact nature of the MRI syntax 1616will not be documented here; see the MRI manuals for more information. 1617Note in particular that the handling of macros and macro arguments is 1618somewhat different. The purpose of this option is to permit assembling 1619existing MRI assembler code using 'as'. 1620 1621 The MRI compatibility is not complete. Certain operations of the MRI 1622assembler depend upon its object file format, and can not be supported 1623using other object file formats. Supporting these would require 1624enhancing each object file format individually. These are: 1625 1626 * global symbols in common section 1627 1628 The m68k MRI assembler supports common sections which are merged by 1629 the linker. Other object file formats do not support this. 'as' 1630 handles common sections by treating them as a single common symbol. 1631 It permits local symbols to be defined within a common section, but 1632 it can not support global symbols, since it has no way to describe 1633 them. 1634 1635 * complex relocations 1636 1637 The MRI assemblers support relocations against a negated section 1638 address, and relocations which combine the start addresses of two 1639 or more sections. These are not support by other object file 1640 formats. 1641 1642 * 'END' pseudo-op specifying start address 1643 1644 The MRI 'END' pseudo-op permits the specification of a start 1645 address. This is not supported by other object file formats. The 1646 start address may instead be specified using the '-e' option to the 1647 linker, or in a linker script. 1648 1649 * 'IDNT', '.ident' and 'NAME' pseudo-ops 1650 1651 The MRI 'IDNT', '.ident' and 'NAME' pseudo-ops assign a module name 1652 to the output file. This is not supported by other object file 1653 formats. 1654 1655 * 'ORG' pseudo-op 1656 1657 The m68k MRI 'ORG' pseudo-op begins an absolute section at a given 1658 address. This differs from the usual 'as' '.org' pseudo-op, which 1659 changes the location within the current section. Absolute sections 1660 are not supported by other object file formats. The address of a 1661 section may be assigned within a linker script. 1662 1663 There are some other features of the MRI assembler which are not 1664supported by 'as', typically either because they are difficult or 1665because they seem of little consequence. Some of these may be supported 1666in future releases. 1667 1668 * EBCDIC strings 1669 1670 EBCDIC strings are not supported. 1671 1672 * packed binary coded decimal 1673 1674 Packed binary coded decimal is not supported. This means that the 1675 'DC.P' and 'DCB.P' pseudo-ops are not supported. 1676 1677 * 'FEQU' pseudo-op 1678 1679 The m68k 'FEQU' pseudo-op is not supported. 1680 1681 * 'NOOBJ' pseudo-op 1682 1683 The m68k 'NOOBJ' pseudo-op is not supported. 1684 1685 * 'OPT' branch control options 1686 1687 The m68k 'OPT' branch control options--'B', 'BRS', 'BRB', 'BRL', 1688 and 'BRW'--are ignored. 'as' automatically relaxes all branches, 1689 whether forward or backward, to an appropriate size, so these 1690 options serve no purpose. 1691 1692 * 'OPT' list control options 1693 1694 The following m68k 'OPT' list control options are ignored: 'C', 1695 'CEX', 'CL', 'CRE', 'E', 'G', 'I', 'M', 'MEX', 'MC', 'MD', 'X'. 1696 1697 * other 'OPT' options 1698 1699 The following m68k 'OPT' options are ignored: 'NEST', 'O', 'OLD', 1700 'OP', 'P', 'PCO', 'PCR', 'PCS', 'R'. 1701 1702 * 'OPT' 'D' option is default 1703 1704 The m68k 'OPT' 'D' option is the default, unlike the MRI assembler. 1705 'OPT NOD' may be used to turn it off. 1706 1707 * 'XREF' pseudo-op. 1708 1709 The m68k 'XREF' pseudo-op is ignored. 1710 1711 * '.debug' pseudo-op 1712 1713 The i960 '.debug' pseudo-op is not supported. 1714 1715 * '.extended' pseudo-op 1716 1717 The i960 '.extended' pseudo-op is not supported. 1718 1719 * '.list' pseudo-op. 1720 1721 The various options of the i960 '.list' pseudo-op are not 1722 supported. 1723 1724 * '.optimize' pseudo-op 1725 1726 The i960 '.optimize' pseudo-op is not supported. 1727 1728 * '.output' pseudo-op 1729 1730 The i960 '.output' pseudo-op is not supported. 1731 1732 * '.setreal' pseudo-op 1733 1734 The i960 '.setreal' pseudo-op is not supported. 1735 1736 1737File: as.info, Node: MD, Next: no-pad-sections, Prev: M, Up: Invoking 1738 17392.10 Dependency Tracking: '--MD' 1740================================ 1741 1742'as' can generate a dependency file for the file it creates. This file 1743consists of a single rule suitable for 'make' describing the 1744dependencies of the main source file. 1745 1746 The rule is written to the file named in its argument. 1747 1748 This feature is used in the automatic updating of makefiles. 1749 1750 1751File: as.info, Node: no-pad-sections, Next: o, Prev: MD, Up: Invoking 1752 17532.11 Output Section Padding 1754=========================== 1755 1756Normally the assembler will pad the end of each output section up to its 1757alignment boundary. But this can waste space, which can be significant 1758on memory constrained targets. So the '--no-pad-sections' option will 1759disable this behaviour. 1760 1761 1762File: as.info, Node: o, Next: R, Prev: no-pad-sections, Up: Invoking 1763 17642.12 Name the Object File: '-o' 1765=============================== 1766 1767There is always one object file output when you run 'as'. By default it 1768has the name 'a.out' (or 'b.out', for Intel 960 targets only). You use 1769this option (which takes exactly one filename) to give the object file a 1770different name. 1771 1772 Whatever the object file is called, 'as' overwrites any existing file 1773of the same name. 1774 1775 1776File: as.info, Node: R, Next: statistics, Prev: o, Up: Invoking 1777 17782.13 Join Data and Text Sections: '-R' 1779====================================== 1780 1781'-R' tells 'as' to write the object file as if all data-section data 1782lives in the text section. This is only done at the very last moment: 1783your binary data are the same, but data section parts are relocated 1784differently. The data section part of your object file is zero bytes 1785long because all its bytes are appended to the text section. (*Note 1786Sections and Relocation: Sections.) 1787 1788 When you specify '-R' it would be possible to generate shorter 1789address displacements (because we do not have to cross between text and 1790data section). We refrain from doing this simply for compatibility with 1791older versions of 'as'. In future, '-R' may work this way. 1792 1793 When 'as' is configured for COFF or ELF output, this option is only 1794useful if you use sections named '.text' and '.data'. 1795 1796 '-R' is not supported for any of the HPPA targets. Using '-R' 1797generates a warning from 'as'. 1798 1799 1800File: as.info, Node: statistics, Next: traditional-format, Prev: R, Up: Invoking 1801 18022.14 Display Assembly Statistics: '--statistics' 1803================================================ 1804 1805Use '--statistics' to display two statistics about the resources used by 1806'as': the maximum amount of space allocated during the assembly (in 1807bytes), and the total execution time taken for the assembly (in CPU 1808seconds). 1809 1810 1811File: as.info, Node: traditional-format, Next: v, Prev: statistics, Up: Invoking 1812 18132.15 Compatible Output: '--traditional-format' 1814============================================== 1815 1816For some targets, the output of 'as' is different in some ways from the 1817output of some existing assembler. This switch requests 'as' to use the 1818traditional format instead. 1819 1820 For example, it disables the exception frame optimizations which 'as' 1821normally does by default on 'gcc' output. 1822 1823 1824File: as.info, Node: v, Next: W, Prev: traditional-format, Up: Invoking 1825 18262.16 Announce Version: '-v' 1827=========================== 1828 1829You can find out what version of as is running by including the option 1830'-v' (which you can also spell as '-version') on the command line. 1831 1832 1833File: as.info, Node: W, Next: Z, Prev: v, Up: Invoking 1834 18352.17 Control Warnings: '-W', '--warn', '--no-warn', '--fatal-warnings' 1836====================================================================== 1837 1838'as' should never give a warning or error message when assembling 1839compiler output. But programs written by people often cause 'as' to 1840give a warning that a particular assumption was made. All such warnings 1841are directed to the standard error file. 1842 1843 If you use the '-W' and '--no-warn' options, no warnings are issued. 1844This only affects the warning messages: it does not change any 1845particular of how 'as' assembles your file. Errors, which stop the 1846assembly, are still reported. 1847 1848 If you use the '--fatal-warnings' option, 'as' considers files that 1849generate warnings to be in error. 1850 1851 You can switch these options off again by specifying '--warn', which 1852causes warnings to be output as usual. 1853 1854 1855File: as.info, Node: Z, Prev: W, Up: Invoking 1856 18572.18 Generate Object File in Spite of Errors: '-Z' 1858================================================== 1859 1860After an error message, 'as' normally produces no output. If for some 1861reason you are interested in object file output even after 'as' gives an 1862error message on your program, use the '-Z' option. If there are any 1863errors, 'as' continues anyways, and writes an object file after a final 1864warning message of the form 'N errors, M warnings, generating bad object 1865file.' 1866 1867 1868File: as.info, Node: Syntax, Next: Sections, Prev: Invoking, Up: Top 1869 18703 Syntax 1871******** 1872 1873This chapter describes the machine-independent syntax allowed in a 1874source file. 'as' syntax is similar to what many other assemblers use; 1875it is inspired by the BSD 4.2 assembler, except that 'as' does not 1876assemble Vax bit-fields. 1877 1878* Menu: 1879 1880* Preprocessing:: Preprocessing 1881* Whitespace:: Whitespace 1882* Comments:: Comments 1883* Symbol Intro:: Symbols 1884* Statements:: Statements 1885* Constants:: Constants 1886 1887 1888File: as.info, Node: Preprocessing, Next: Whitespace, Up: Syntax 1889 18903.1 Preprocessing 1891================= 1892 1893The 'as' internal preprocessor: 1894 * adjusts and removes extra whitespace. It leaves one space or tab 1895 before the keywords on a line, and turns any other whitespace on 1896 the line into a single space. 1897 1898 * removes all comments, replacing them with a single space, or an 1899 appropriate number of newlines. 1900 1901 * converts character constants into the appropriate numeric values. 1902 1903 It does not do macro processing, include file handling, or anything 1904else you may get from your C compiler's preprocessor. You can do 1905include file processing with the '.include' directive (*note '.include': 1906Include.). You can use the GNU C compiler driver to get other "CPP" 1907style preprocessing by giving the input file a '.S' suffix. *Note 1908Options Controlling the Kind of Output: (gcc info)Overall Options. 1909 1910 Excess whitespace, comments, and character constants cannot be used 1911in the portions of the input text that are not preprocessed. 1912 1913 If the first line of an input file is '#NO_APP' or if you use the 1914'-f' option, whitespace and comments are not removed from the input 1915file. Within an input file, you can ask for whitespace and comment 1916removal in specific portions of the by putting a line that says '#APP' 1917before the text that may contain whitespace or comments, and putting a 1918line that says '#NO_APP' after this text. This feature is mainly intend 1919to support 'asm' statements in compilers whose output is otherwise free 1920of comments and whitespace. 1921 1922 1923File: as.info, Node: Whitespace, Next: Comments, Prev: Preprocessing, Up: Syntax 1924 19253.2 Whitespace 1926============== 1927 1928"Whitespace" is one or more blanks or tabs, in any order. Whitespace is 1929used to separate symbols, and to make programs neater for people to 1930read. Unless within character constants (*note Character Constants: 1931Characters.), any whitespace means the same as exactly one space. 1932 1933 1934File: as.info, Node: Comments, Next: Symbol Intro, Prev: Whitespace, Up: Syntax 1935 19363.3 Comments 1937============ 1938 1939There are two ways of rendering comments to 'as'. In both cases the 1940comment is equivalent to one space. 1941 1942 Anything from '/*' through the next '*/' is a comment. This means 1943you may not nest these comments. 1944 1945 /* 1946 The only way to include a newline ('\n') in a comment 1947 is to use this sort of comment. 1948 */ 1949 1950 /* This sort of comment does not nest. */ 1951 1952 Anything from a "line comment" character up to the next newline is 1953considered a comment and is ignored. The line comment character is 1954target specific, and some targets multiple comment characters. Some 1955targets also have line comment characters that only work if they are the 1956first character on a line. Some targets use a sequence of two 1957characters to introduce a line comment. Some targets can also change 1958their line comment characters depending upon command line options that 1959have been used. For more details see the _Syntax_ section in the 1960documentation for individual targets. 1961 1962 If the line comment character is the hash sign ('#') then it still 1963has the special ability to enable and disable preprocessing (*note 1964Preprocessing::) and to specify logical line numbers: 1965 1966 To be compatible with past assemblers, lines that begin with '#' have 1967a special interpretation. Following the '#' should be an absolute 1968expression (*note Expressions::): the logical line number of the _next_ 1969line. Then a string (*note Strings: Strings.) is allowed: if present it 1970is a new logical file name. The rest of the line, if any, should be 1971whitespace. 1972 1973 If the first non-whitespace characters on the line are not numeric, 1974the line is ignored. (Just like a comment.) 1975 1976 # This is an ordinary comment. 1977 # 42-6 "new_file_name" # New logical file name 1978 # This is logical line # 36. 1979 This feature is deprecated, and may disappear from future versions of 1980'as'. 1981 1982 1983File: as.info, Node: Symbol Intro, Next: Statements, Prev: Comments, Up: Syntax 1984 19853.4 Symbols 1986=========== 1987 1988A "symbol" is one or more characters chosen from the set of all letters 1989(both upper and lower case), digits and the three characters '_.$'. On 1990most machines, you can also use '$' in symbol names; exceptions are 1991noted in *note Machine Dependencies::. No symbol may begin with a 1992digit. Case is significant. There is no length limit; all characters 1993are significant. Multibyte characters are supported. Symbols are 1994delimited by characters not in that set, or by the beginning of a file 1995(since the source program must end with a newline, the end of a file is 1996not a possible symbol delimiter). *Note Symbols::. 1997 1998 Symbol names may also be enclosed in double quote '"' characters. In 1999such cases any characters are allowed, except for the NUL character. If 2000a double quote character is to be included in the symbol name it must be 2001preceeded by a backslash '\' character. 2002 2003 2004File: as.info, Node: Statements, Next: Constants, Prev: Symbol Intro, Up: Syntax 2005 20063.5 Statements 2007============== 2008 2009A "statement" ends at a newline character ('\n') or a "line separator 2010character". The line separator character is target specific and 2011described in the _Syntax_ section of each target's documentation. Not 2012all targets support a line separator character. The newline or line 2013separator character is considered to be part of the preceding statement. 2014Newlines and separators within character constants are an exception: 2015they do not end statements. 2016 2017 It is an error to end any statement with end-of-file: the last 2018character of any input file should be a newline. 2019 2020 An empty statement is allowed, and may include whitespace. It is 2021ignored. 2022 2023 A statement begins with zero or more labels, optionally followed by a 2024key symbol which determines what kind of statement it is. The key 2025symbol determines the syntax of the rest of the statement. If the 2026symbol begins with a dot '.' then the statement is an assembler 2027directive: typically valid for any computer. If the symbol begins with 2028a letter the statement is an assembly language "instruction": it 2029assembles into a machine language instruction. Different versions of 2030'as' for different computers recognize different instructions. In fact, 2031the same symbol may represent a different instruction in a different 2032computer's assembly language. 2033 2034 A label is a symbol immediately followed by a colon (':'). 2035Whitespace before a label or after a colon is permitted, but you may not 2036have whitespace between a label's symbol and its colon. *Note Labels::. 2037 2038 For HPPA targets, labels need not be immediately followed by a colon, 2039but the definition of a label must begin in column zero. This also 2040implies that only one label may be defined on each line. 2041 2042 label: .directive followed by something 2043 another_label: # This is an empty statement. 2044 instruction operand_1, operand_2, ... 2045 2046 2047File: as.info, Node: Constants, Prev: Statements, Up: Syntax 2048 20493.6 Constants 2050============= 2051 2052A constant is a number, written so that its value is known by 2053inspection, without knowing any context. Like this: 2054 .byte 74, 0112, 092, 0x4A, 0X4a, 'J, '\J # All the same value. 2055 .ascii "Ring the bell\7" # A string constant. 2056 .octa 0x123456789abcdef0123456789ABCDEF0 # A bignum. 2057 .float 0f-314159265358979323846264338327\ 2058 95028841971.693993751E-40 # - pi, a flonum. 2059 2060* Menu: 2061 2062* Characters:: Character Constants 2063* Numbers:: Number Constants 2064 2065 2066File: as.info, Node: Characters, Next: Numbers, Up: Constants 2067 20683.6.1 Character Constants 2069------------------------- 2070 2071There are two kinds of character constants. A "character" stands for 2072one character in one byte and its value may be used in numeric 2073expressions. String constants (properly called string _literals_) are 2074potentially many bytes and their values may not be used in arithmetic 2075expressions. 2076 2077* Menu: 2078 2079* Strings:: Strings 2080* Chars:: Characters 2081 2082 2083File: as.info, Node: Strings, Next: Chars, Up: Characters 2084 20853.6.1.1 Strings 2086............... 2087 2088A "string" is written between double-quotes. It may contain 2089double-quotes or null characters. The way to get special characters 2090into a string is to "escape" these characters: precede them with a 2091backslash '\' character. For example '\\' represents one backslash: the 2092first '\' is an escape which tells 'as' to interpret the second 2093character literally as a backslash (which prevents 'as' from recognizing 2094the second '\' as an escape character). The complete list of escapes 2095follows. 2096 2097'\b' 2098 Mnemonic for backspace; for ASCII this is octal code 010. 2099 2100'backslash-f' 2101 Mnemonic for FormFeed; for ASCII this is octal code 014. 2102 2103'\n' 2104 Mnemonic for newline; for ASCII this is octal code 012. 2105 2106'\r' 2107 Mnemonic for carriage-Return; for ASCII this is octal code 015. 2108 2109'\t' 2110 Mnemonic for horizontal Tab; for ASCII this is octal code 011. 2111 2112'\ DIGIT DIGIT DIGIT' 2113 An octal character code. The numeric code is 3 octal digits. For 2114 compatibility with other Unix systems, 8 and 9 are accepted as 2115 digits: for example, '\008' has the value 010, and '\009' the value 2116 011. 2117 2118'\x HEX-DIGITS...' 2119 A hex character code. All trailing hex digits are combined. 2120 Either upper or lower case 'x' works. 2121 2122'\\' 2123 Represents one '\' character. 2124 2125'\"' 2126 Represents one '"' character. Needed in strings to represent this 2127 character, because an unescaped '"' would end the string. 2128 2129'\ ANYTHING-ELSE' 2130 Any other character when escaped by '\' gives a warning, but 2131 assembles as if the '\' was not present. The idea is that if you 2132 used an escape sequence you clearly didn't want the literal 2133 interpretation of the following character. However 'as' has no 2134 other interpretation, so 'as' knows it is giving you the wrong code 2135 and warns you of the fact. 2136 2137 Which characters are escapable, and what those escapes represent, 2138varies widely among assemblers. The current set is what we think the 2139BSD 4.2 assembler recognizes, and is a subset of what most C compilers 2140recognize. If you are in doubt, do not use an escape sequence. 2141 2142 2143File: as.info, Node: Chars, Prev: Strings, Up: Characters 2144 21453.6.1.2 Characters 2146.................. 2147 2148A single character may be written as a single quote immediately followed 2149by that character. Some backslash escapes apply to characters, '\b', 2150'\f', '\n', '\r', '\t', and '\"' with the same meaning as for strings, 2151plus '\'' for a single quote. So if you want to write the character 2152backslash, you must write ''\\' where the first '\' escapes the second 2153'\'. As you can see, the quote is an acute accent, not a grave accent. 2154A newline immediately following an acute accent is taken as a literal 2155character and does not count as the end of a statement. The value of a 2156character constant in a numeric expression is the machine's byte-wide 2157code for that character. 'as' assumes your character code is ASCII: 2158''A' means 65, ''B' means 66, and so on. 2159 2160 2161File: as.info, Node: Numbers, Prev: Characters, Up: Constants 2162 21633.6.2 Number Constants 2164---------------------- 2165 2166'as' distinguishes three kinds of numbers according to how they are 2167stored in the target machine. _Integers_ are numbers that would fit 2168into an 'int' in the C language. _Bignums_ are integers, but they are 2169stored in more than 32 bits. _Flonums_ are floating point numbers, 2170described below. 2171 2172* Menu: 2173 2174* Integers:: Integers 2175* Bignums:: Bignums 2176* Flonums:: Flonums 2177 2178 2179File: as.info, Node: Integers, Next: Bignums, Up: Numbers 2180 21813.6.2.1 Integers 2182................ 2183 2184A binary integer is '0b' or '0B' followed by zero or more of the binary 2185digits '01'. 2186 2187 An octal integer is '0' followed by zero or more of the octal digits 2188('01234567'). 2189 2190 A decimal integer starts with a non-zero digit followed by zero or 2191more digits ('0123456789'). 2192 2193 A hexadecimal integer is '0x' or '0X' followed by one or more 2194hexadecimal digits chosen from '0123456789abcdefABCDEF'. 2195 2196 Integers have the usual values. To denote a negative integer, use 2197the prefix operator '-' discussed under expressions (*note Prefix 2198Operators: Prefix Ops.). 2199 2200 2201File: as.info, Node: Bignums, Next: Flonums, Prev: Integers, Up: Numbers 2202 22033.6.2.2 Bignums 2204............... 2205 2206A "bignum" has the same syntax and semantics as an integer except that 2207the number (or its negative) takes more than 32 bits to represent in 2208binary. The distinction is made because in some places integers are 2209permitted while bignums are not. 2210 2211 2212File: as.info, Node: Flonums, Prev: Bignums, Up: Numbers 2213 22143.6.2.3 Flonums 2215............... 2216 2217A "flonum" represents a floating point number. The translation is 2218indirect: a decimal floating point number from the text is converted by 2219'as' to a generic binary floating point number of more than sufficient 2220precision. This generic floating point number is converted to a 2221particular computer's floating point format (or formats) by a portion of 2222'as' specialized to that computer. 2223 2224 A flonum is written by writing (in order) 2225 * The digit '0'. ('0' is optional on the HPPA.) 2226 2227 * A letter, to tell 'as' the rest of the number is a flonum. 'e' is 2228 recommended. Case is not important. 2229 2230 On the H8/300, Renesas / SuperH SH, and AMD 29K architectures, the 2231 letter must be one of the letters 'DFPRSX' (in upper or lower 2232 case). 2233 2234 On the ARC, the letter must be one of the letters 'DFRS' (in upper 2235 or lower case). 2236 2237 On the Intel 960 architecture, the letter must be one of the 2238 letters 'DFT' (in upper or lower case). 2239 2240 On the HPPA architecture, the letter must be 'E' (upper case only). 2241 2242 * An optional sign: either '+' or '-'. 2243 2244 * An optional "integer part": zero or more decimal digits. 2245 2246 * An optional "fractional part": '.' followed by zero or more decimal 2247 digits. 2248 2249 * An optional exponent, consisting of: 2250 2251 * An 'E' or 'e'. 2252 * Optional sign: either '+' or '-'. 2253 * One or more decimal digits. 2254 2255 At least one of the integer part or the fractional part must be 2256present. The floating point number has the usual base-10 value. 2257 2258 'as' does all processing using integers. Flonums are computed 2259independently of any floating point hardware in the computer running 2260'as'. 2261 2262 2263File: as.info, Node: Sections, Next: Symbols, Prev: Syntax, Up: Top 2264 22654 Sections and Relocation 2266************************* 2267 2268* Menu: 2269 2270* Secs Background:: Background 2271* Ld Sections:: Linker Sections 2272* As Sections:: Assembler Internal Sections 2273* Sub-Sections:: Sub-Sections 2274* bss:: bss Section 2275 2276 2277File: as.info, Node: Secs Background, Next: Ld Sections, Up: Sections 2278 22794.1 Background 2280============== 2281 2282Roughly, a section is a range of addresses, with no gaps; all data "in" 2283those addresses is treated the same for some particular purpose. For 2284example there may be a "read only" section. 2285 2286 The linker 'ld' reads many object files (partial programs) and 2287combines their contents to form a runnable program. When 'as' emits an 2288object file, the partial program is assumed to start at address 0. 'ld' 2289assigns the final addresses for the partial program, so that different 2290partial programs do not overlap. This is actually an 2291oversimplification, but it suffices to explain how 'as' uses sections. 2292 2293 'ld' moves blocks of bytes of your program to their run-time 2294addresses. These blocks slide to their run-time addresses as rigid 2295units; their length does not change and neither does the order of bytes 2296within them. Such a rigid unit is called a _section_. Assigning 2297run-time addresses to sections is called "relocation". It includes the 2298task of adjusting mentions of object-file addresses so they refer to the 2299proper run-time addresses. For the H8/300, and for the Renesas / SuperH 2300SH, 'as' pads sections if needed to ensure they end on a word (sixteen 2301bit) boundary. 2302 2303 An object file written by 'as' has at least three sections, any of 2304which may be empty. These are named "text", "data" and "bss" sections. 2305 2306 When it generates COFF or ELF output, 'as' can also generate whatever 2307other named sections you specify using the '.section' directive (*note 2308'.section': Section.). If you do not use any directives that place 2309output in the '.text' or '.data' sections, these sections still exist, 2310but are empty. 2311 2312 When 'as' generates SOM or ELF output for the HPPA, 'as' can also 2313generate whatever other named sections you specify using the '.space' 2314and '.subspace' directives. See 'HP9000 Series 800 Assembly Language 2315Reference Manual' (HP 92432-90001) for details on the '.space' and 2316'.subspace' assembler directives. 2317 2318 Additionally, 'as' uses different names for the standard text, data, 2319and bss sections when generating SOM output. Program text is placed 2320into the '$CODE$' section, data into '$DATA$', and BSS into '$BSS$'. 2321 2322 Within the object file, the text section starts at address '0', the 2323data section follows, and the bss section follows the data section. 2324 2325 When generating either SOM or ELF output files on the HPPA, the text 2326section starts at address '0', the data section at address '0x4000000', 2327and the bss section follows the data section. 2328 2329 To let 'ld' know which data changes when the sections are relocated, 2330and how to change that data, 'as' also writes to the object file details 2331of the relocation needed. To perform relocation 'ld' must know, each 2332time an address in the object file is mentioned: 2333 * Where in the object file is the beginning of this reference to an 2334 address? 2335 * How long (in bytes) is this reference? 2336 * Which section does the address refer to? What is the numeric value 2337 of 2338 (ADDRESS) - (START-ADDRESS OF SECTION)? 2339 * Is the reference to an address "Program-Counter relative"? 2340 2341 In fact, every address 'as' ever uses is expressed as 2342 (SECTION) + (OFFSET INTO SECTION) 2343Further, most expressions 'as' computes have this section-relative 2344nature. (For some object formats, such as SOM for the HPPA, some 2345expressions are symbol-relative instead.) 2346 2347 In this manual we use the notation {SECNAME N} to mean "offset N into 2348section SECNAME." 2349 2350 Apart from text, data and bss sections you need to know about the 2351"absolute" section. When 'ld' mixes partial programs, addresses in the 2352absolute section remain unchanged. For example, address '{absolute 0}' 2353is "relocated" to run-time address 0 by 'ld'. Although the linker never 2354arranges two partial programs' data sections with overlapping addresses 2355after linking, _by definition_ their absolute sections must overlap. 2356Address '{absolute 239}' in one part of a program is always the same 2357address when the program is running as address '{absolute 239}' in any 2358other part of the program. 2359 2360 The idea of sections is extended to the "undefined" section. Any 2361address whose section is unknown at assembly time is by definition 2362rendered {undefined U}--where U is filled in later. Since numbers are 2363always defined, the only way to generate an undefined address is to 2364mention an undefined symbol. A reference to a named common block would 2365be such a symbol: its value is unknown at assembly time so it has 2366section _undefined_. 2367 2368 By analogy the word _section_ is used to describe groups of sections 2369in the linked program. 'ld' puts all partial programs' text sections in 2370contiguous addresses in the linked program. It is customary to refer to 2371the _text section_ of a program, meaning all the addresses of all 2372partial programs' text sections. Likewise for data and bss sections. 2373 2374 Some sections are manipulated by 'ld'; others are invented for use of 2375'as' and have no meaning except during assembly. 2376 2377 2378File: as.info, Node: Ld Sections, Next: As Sections, Prev: Secs Background, Up: Sections 2379 23804.2 Linker Sections 2381=================== 2382 2383'ld' deals with just four kinds of sections, summarized below. 2384 2385*named sections* 2386*text section* 2387*data section* 2388 These sections hold your program. 'as' and 'ld' treat them as 2389 separate but equal sections. Anything you can say of one section 2390 is true of another. When the program is running, however, it is 2391 customary for the text section to be unalterable. The text section 2392 is often shared among processes: it contains instructions, 2393 constants and the like. The data section of a running program is 2394 usually alterable: for example, C variables would be stored in the 2395 data section. 2396 2397*bss section* 2398 This section contains zeroed bytes when your program begins 2399 running. It is used to hold uninitialized variables or common 2400 storage. The length of each partial program's bss section is 2401 important, but because it starts out containing zeroed bytes there 2402 is no need to store explicit zero bytes in the object file. The 2403 bss section was invented to eliminate those explicit zeros from 2404 object files. 2405 2406*absolute section* 2407 Address 0 of this section is always "relocated" to runtime address 2408 0. This is useful if you want to refer to an address that 'ld' 2409 must not change when relocating. In this sense we speak of 2410 absolute addresses being "unrelocatable": they do not change during 2411 relocation. 2412 2413*undefined section* 2414 This "section" is a catch-all for address references to objects not 2415 in the preceding sections. 2416 2417 An idealized example of three relocatable sections follows. The 2418example uses the traditional section names '.text' and '.data'. Memory 2419addresses are on the horizontal axis. 2420 2421 +-----+----+--+ 2422 partial program # 1: |ttttt|dddd|00| 2423 +-----+----+--+ 2424 2425 text data bss 2426 seg. seg. seg. 2427 2428 +---+---+---+ 2429 partial program # 2: |TTT|DDD|000| 2430 +---+---+---+ 2431 2432 +--+---+-----+--+----+---+-----+~~ 2433 linked program: | |TTT|ttttt| |dddd|DDD|00000| 2434 +--+---+-----+--+----+---+-----+~~ 2435 2436 addresses: 0 ... 2437 2438 2439File: as.info, Node: As Sections, Next: Sub-Sections, Prev: Ld Sections, Up: Sections 2440 24414.3 Assembler Internal Sections 2442=============================== 2443 2444These sections are meant only for the internal use of 'as'. They have 2445no meaning at run-time. You do not really need to know about these 2446sections for most purposes; but they can be mentioned in 'as' warning 2447messages, so it might be helpful to have an idea of their meanings to 2448'as'. These sections are used to permit the value of every expression 2449in your assembly language program to be a section-relative address. 2450 2451ASSEMBLER-INTERNAL-LOGIC-ERROR! 2452 An internal assembler logic error has been found. This means there 2453 is a bug in the assembler. 2454 2455expr section 2456 The assembler stores complex expression internally as combinations 2457 of symbols. When it needs to represent an expression as a symbol, 2458 it puts it in the expr section. 2459 2460 2461File: as.info, Node: Sub-Sections, Next: bss, Prev: As Sections, Up: Sections 2462 24634.4 Sub-Sections 2464================ 2465 2466Assembled bytes conventionally fall into two sections: text and data. 2467You may have separate groups of data in named sections that you want to 2468end up near to each other in the object file, even though they are not 2469contiguous in the assembler source. 'as' allows you to use 2470"subsections" for this purpose. Within each section, there can be 2471numbered subsections with values from 0 to 8192. Objects assembled into 2472the same subsection go into the object file together with other objects 2473in the same subsection. For example, a compiler might want to store 2474constants in the text section, but might not want to have them 2475interspersed with the program being assembled. In this case, the 2476compiler could issue a '.text 0' before each section of code being 2477output, and a '.text 1' before each group of constants being output. 2478 2479 Subsections are optional. If you do not use subsections, everything 2480goes in subsection number zero. 2481 2482 Each subsection is zero-padded up to a multiple of four bytes. 2483(Subsections may be padded a different amount on different flavors of 2484'as'.) 2485 2486 Subsections appear in your object file in numeric order, lowest 2487numbered to highest. (All this to be compatible with other people's 2488assemblers.) The object file contains no representation of subsections; 2489'ld' and other programs that manipulate object files see no trace of 2490them. They just see all your text subsections as a text section, and 2491all your data subsections as a data section. 2492 2493 To specify which subsection you want subsequent statements assembled 2494into, use a numeric argument to specify it, in a '.text EXPRESSION' or a 2495'.data EXPRESSION' statement. When generating COFF output, you can also 2496use an extra subsection argument with arbitrary named sections: 2497'.section NAME, EXPRESSION'. When generating ELF output, you can also 2498use the '.subsection' directive (*note SubSection::) to specify a 2499subsection: '.subsection EXPRESSION'. EXPRESSION should be an absolute 2500expression (*note Expressions::). If you just say '.text' then '.text 25010' is assumed. Likewise '.data' means '.data 0'. Assembly begins in 2502'text 0'. For instance: 2503 .text 0 # The default subsection is text 0 anyway. 2504 .ascii "This lives in the first text subsection. *" 2505 .text 1 2506 .ascii "But this lives in the second text subsection." 2507 .data 0 2508 .ascii "This lives in the data section," 2509 .ascii "in the first data subsection." 2510 .text 0 2511 .ascii "This lives in the first text section," 2512 .ascii "immediately following the asterisk (*)." 2513 2514 Each section has a "location counter" incremented by one for every 2515byte assembled into that section. Because subsections are merely a 2516convenience restricted to 'as' there is no concept of a subsection 2517location counter. There is no way to directly manipulate a location 2518counter--but the '.align' directive changes it, and any label definition 2519captures its current value. The location counter of the section where 2520statements are being assembled is said to be the "active" location 2521counter. 2522 2523 2524File: as.info, Node: bss, Prev: Sub-Sections, Up: Sections 2525 25264.5 bss Section 2527=============== 2528 2529The bss section is used for local common variable storage. You may 2530allocate address space in the bss section, but you may not dictate data 2531to load into it before your program executes. When your program starts 2532running, all the contents of the bss section are zeroed bytes. 2533 2534 The '.lcomm' pseudo-op defines a symbol in the bss section; see *note 2535'.lcomm': Lcomm. 2536 2537 The '.comm' pseudo-op may be used to declare a common symbol, which 2538is another form of uninitialized symbol; see *note '.comm': Comm. 2539 2540 When assembling for a target which supports multiple sections, such 2541as ELF or COFF, you may switch into the '.bss' section and define 2542symbols as usual; see *note '.section': Section. You may only assemble 2543zero values into the section. Typically the section will only contain 2544symbol definitions and '.skip' directives (*note '.skip': Skip.). 2545 2546 2547File: as.info, Node: Symbols, Next: Expressions, Prev: Sections, Up: Top 2548 25495 Symbols 2550********* 2551 2552Symbols are a central concept: the programmer uses symbols to name 2553things, the linker uses symbols to link, and the debugger uses symbols 2554to debug. 2555 2556 _Warning:_ 'as' does not place symbols in the object file in the 2557 same order they were declared. This may break some debuggers. 2558 2559* Menu: 2560 2561* Labels:: Labels 2562* Setting Symbols:: Giving Symbols Other Values 2563* Symbol Names:: Symbol Names 2564* Dot:: The Special Dot Symbol 2565* Symbol Attributes:: Symbol Attributes 2566 2567 2568File: as.info, Node: Labels, Next: Setting Symbols, Up: Symbols 2569 25705.1 Labels 2571========== 2572 2573A "label" is written as a symbol immediately followed by a colon ':'. 2574The symbol then represents the current value of the active location 2575counter, and is, for example, a suitable instruction operand. You are 2576warned if you use the same symbol to represent two different locations: 2577the first definition overrides any other definitions. 2578 2579 On the HPPA, the usual form for a label need not be immediately 2580followed by a colon, but instead must start in column zero. Only one 2581label may be defined on a single line. To work around this, the HPPA 2582version of 'as' also provides a special directive '.label' for defining 2583labels more flexibly. 2584 2585 2586File: as.info, Node: Setting Symbols, Next: Symbol Names, Prev: Labels, Up: Symbols 2587 25885.2 Giving Symbols Other Values 2589=============================== 2590 2591A symbol can be given an arbitrary value by writing a symbol, followed 2592by an equals sign '=', followed by an expression (*note Expressions::). 2593This is equivalent to using the '.set' directive. *Note '.set': Set. 2594In the same way, using a double equals sign '=''=' here represents an 2595equivalent of the '.eqv' directive. *Note '.eqv': Eqv. 2596 2597 Blackfin does not support symbol assignment with '='. 2598 2599 2600File: as.info, Node: Symbol Names, Next: Dot, Prev: Setting Symbols, Up: Symbols 2601 26025.3 Symbol Names 2603================ 2604 2605Symbol names begin with a letter or with one of '._'. On most machines, 2606you can also use '$' in symbol names; exceptions are noted in *note 2607Machine Dependencies::. That character may be followed by any string of 2608digits, letters, dollar signs (unless otherwise noted for a particular 2609target machine), and underscores. 2610 2611 Case of letters is significant: 'foo' is a different symbol name than 2612'Foo'. 2613 2614 Symbol names do not start with a digit. An exception to this rule is 2615made for Local Labels. See below. 2616 2617 Multibyte characters are supported. To generate a symbol name 2618containing multibyte characters enclose it within double quotes and use 2619escape codes. cf *Note Strings::. Generating a multibyte symbol name 2620from a label is not currently supported. 2621 2622 Each symbol has exactly one name. Each name in an assembly language 2623program refers to exactly one symbol. You may use that symbol name any 2624number of times in a program. 2625 2626Local Symbol Names 2627------------------ 2628 2629A local symbol is any symbol beginning with certain local label 2630prefixes. By default, the local label prefix is '.L' for ELF systems or 2631'L' for traditional a.out systems, but each target may have its own set 2632of local label prefixes. On the HPPA local symbols begin with 'L$'. 2633 2634 Local symbols are defined and used within the assembler, but they are 2635normally not saved in object files. Thus, they are not visible when 2636debugging. You may use the '-L' option (*note Include Local Symbols: 2637L.) to retain the local symbols in the object files. 2638 2639Local Labels 2640------------ 2641 2642Local labels are different from local symbols. Local labels help 2643compilers and programmers use names temporarily. They create symbols 2644which are guaranteed to be unique over the entire scope of the input 2645source code and which can be referred to by a simple notation. To 2646define a local label, write a label of the form 'N:' (where N represents 2647any non-negative integer). To refer to the most recent previous 2648definition of that label write 'Nb', using the same number as when you 2649defined the label. To refer to the next definition of a local label, 2650write 'Nf'. The 'b' stands for "backwards" and the 'f' stands for 2651"forwards". 2652 2653 There is no restriction on how you can use these labels, and you can 2654reuse them too. So that it is possible to repeatedly define the same 2655local label (using the same number 'N'), although you can only refer to 2656the most recently defined local label of that number (for a backwards 2657reference) or the next definition of a specific local label for a 2658forward reference. It is also worth noting that the first 10 local 2659labels ('0:'...'9:') are implemented in a slightly more efficient manner 2660than the others. 2661 2662 Here is an example: 2663 2664 1: branch 1f 2665 2: branch 1b 2666 1: branch 2f 2667 2: branch 1b 2668 2669 Which is the equivalent of: 2670 2671 label_1: branch label_3 2672 label_2: branch label_1 2673 label_3: branch label_4 2674 label_4: branch label_3 2675 2676 Local label names are only a notational device. They are immediately 2677transformed into more conventional symbol names before the assembler 2678uses them. The symbol names are stored in the symbol table, appear in 2679error messages, and are optionally emitted to the object file. The 2680names are constructed using these parts: 2681 2682'_local label prefix_' 2683 All local symbols begin with the system-specific local label 2684 prefix. Normally both 'as' and 'ld' forget symbols that start with 2685 the local label prefix. These labels are used for symbols you are 2686 never intended to see. If you use the '-L' option then 'as' 2687 retains these symbols in the object file. If you also instruct 2688 'ld' to retain these symbols, you may use them in debugging. 2689 2690'NUMBER' 2691 This is the number that was used in the local label definition. So 2692 if the label is written '55:' then the number is '55'. 2693 2694'C-B' 2695 This unusual character is included so you do not accidentally 2696 invent a symbol of the same name. The character has ASCII value of 2697 '\002' (control-B). 2698 2699'_ordinal number_' 2700 This is a serial number to keep the labels distinct. The first 2701 definition of '0:' gets the number '1'. The 15th definition of 2702 '0:' gets the number '15', and so on. Likewise the first 2703 definition of '1:' gets the number '1' and its 15th definition gets 2704 '15' as well. 2705 2706 So for example, the first '1:' may be named '.L1C-B1', and the 44th 2707'3:' may be named '.L3C-B44'. 2708 2709Dollar Local Labels 2710------------------- 2711 2712On some targets 'as' also supports an even more local form of local 2713labels called dollar labels. These labels go out of scope (i.e., they 2714become undefined) as soon as a non-local label is defined. Thus they 2715remain valid for only a small region of the input source code. Normal 2716local labels, by contrast, remain in scope for the entire file, or until 2717they are redefined by another occurrence of the same local label. 2718 2719 Dollar labels are defined in exactly the same way as ordinary local 2720labels, except that they have a dollar sign suffix to their numeric 2721value, e.g., '55$:'. 2722 2723 They can also be distinguished from ordinary local labels by their 2724transformed names which use ASCII character '\001' (control-A) as the 2725magic character to distinguish them from ordinary labels. For example, 2726the fifth definition of '6$' may be named '.L6'C-A'5'. 2727 2728 2729File: as.info, Node: Dot, Next: Symbol Attributes, Prev: Symbol Names, Up: Symbols 2730 27315.4 The Special Dot Symbol 2732========================== 2733 2734The special symbol '.' refers to the current address that 'as' is 2735assembling into. Thus, the expression 'melvin: .long .' defines 2736'melvin' to contain its own address. Assigning a value to '.' is 2737treated the same as a '.org' directive. Thus, the expression '.=.+4' is 2738the same as saying '.space 4'. 2739 2740 2741File: as.info, Node: Symbol Attributes, Prev: Dot, Up: Symbols 2742 27435.5 Symbol Attributes 2744===================== 2745 2746Every symbol has, as well as its name, the attributes "Value" and 2747"Type". Depending on output format, symbols can also have auxiliary 2748attributes. 2749 2750 If you use a symbol without defining it, 'as' assumes zero for all 2751these attributes, and probably won't warn you. This makes the symbol an 2752externally defined symbol, which is generally what you would want. 2753 2754* Menu: 2755 2756* Symbol Value:: Value 2757* Symbol Type:: Type 2758* a.out Symbols:: Symbol Attributes: 'a.out' 2759* COFF Symbols:: Symbol Attributes for COFF 2760* SOM Symbols:: Symbol Attributes for SOM 2761 2762 2763File: as.info, Node: Symbol Value, Next: Symbol Type, Up: Symbol Attributes 2764 27655.5.1 Value 2766----------- 2767 2768The value of a symbol is (usually) 32 bits. For a symbol which labels a 2769location in the text, data, bss or absolute sections the value is the 2770number of addresses from the start of that section to the label. 2771Naturally for text, data and bss sections the value of a symbol changes 2772as 'ld' changes section base addresses during linking. Absolute 2773symbols' values do not change during linking: that is why they are 2774called absolute. 2775 2776 The value of an undefined symbol is treated in a special way. If it 2777is 0 then the symbol is not defined in this assembler source file, and 2778'ld' tries to determine its value from other files linked into the same 2779program. You make this kind of symbol simply by mentioning a symbol 2780name without defining it. A non-zero value represents a '.comm' common 2781declaration. The value is how much common storage to reserve, in bytes 2782(addresses). The symbol refers to the first address of the allocated 2783storage. 2784 2785 2786File: as.info, Node: Symbol Type, Next: a.out Symbols, Prev: Symbol Value, Up: Symbol Attributes 2787 27885.5.2 Type 2789---------- 2790 2791The type attribute of a symbol contains relocation (section) 2792information, any flag settings indicating that a symbol is external, and 2793(optionally), other information for linkers and debuggers. The exact 2794format depends on the object-code output format in use. 2795 2796 2797File: as.info, Node: a.out Symbols, Next: COFF Symbols, Prev: Symbol Type, Up: Symbol Attributes 2798 27995.5.3 Symbol Attributes: 'a.out' 2800-------------------------------- 2801 2802* Menu: 2803 2804* Symbol Desc:: Descriptor 2805* Symbol Other:: Other 2806 2807 2808File: as.info, Node: Symbol Desc, Next: Symbol Other, Up: a.out Symbols 2809 28105.5.3.1 Descriptor 2811.................. 2812 2813This is an arbitrary 16-bit value. You may establish a symbol's 2814descriptor value by using a '.desc' statement (*note '.desc': Desc.). A 2815descriptor value means nothing to 'as'. 2816 2817 2818File: as.info, Node: Symbol Other, Prev: Symbol Desc, Up: a.out Symbols 2819 28205.5.3.2 Other 2821............. 2822 2823This is an arbitrary 8-bit value. It means nothing to 'as'. 2824 2825 2826File: as.info, Node: COFF Symbols, Next: SOM Symbols, Prev: a.out Symbols, Up: Symbol Attributes 2827 28285.5.4 Symbol Attributes for COFF 2829-------------------------------- 2830 2831The COFF format supports a multitude of auxiliary symbol attributes; 2832like the primary symbol attributes, they are set between '.def' and 2833'.endef' directives. 2834 28355.5.4.1 Primary Attributes 2836.......................... 2837 2838The symbol name is set with '.def'; the value and type, respectively, 2839with '.val' and '.type'. 2840 28415.5.4.2 Auxiliary Attributes 2842............................ 2843 2844The 'as' directives '.dim', '.line', '.scl', '.size', '.tag', and 2845'.weak' can generate auxiliary symbol table information for COFF. 2846 2847 2848File: as.info, Node: SOM Symbols, Prev: COFF Symbols, Up: Symbol Attributes 2849 28505.5.5 Symbol Attributes for SOM 2851------------------------------- 2852 2853The SOM format for the HPPA supports a multitude of symbol attributes 2854set with the '.EXPORT' and '.IMPORT' directives. 2855 2856 The attributes are described in 'HP9000 Series 800 Assembly Language 2857Reference Manual' (HP 92432-90001) under the 'IMPORT' and 'EXPORT' 2858assembler directive documentation. 2859 2860 2861File: as.info, Node: Expressions, Next: Pseudo Ops, Prev: Symbols, Up: Top 2862 28636 Expressions 2864************* 2865 2866An "expression" specifies an address or numeric value. Whitespace may 2867precede and/or follow an expression. 2868 2869 The result of an expression must be an absolute number, or else an 2870offset into a particular section. If an expression is not absolute, and 2871there is not enough information when 'as' sees the expression to know 2872its section, a second pass over the source program might be necessary to 2873interpret the expression--but the second pass is currently not 2874implemented. 'as' aborts with an error message in this situation. 2875 2876* Menu: 2877 2878* Empty Exprs:: Empty Expressions 2879* Integer Exprs:: Integer Expressions 2880 2881 2882File: as.info, Node: Empty Exprs, Next: Integer Exprs, Up: Expressions 2883 28846.1 Empty Expressions 2885===================== 2886 2887An empty expression has no value: it is just whitespace or null. 2888Wherever an absolute expression is required, you may omit the 2889expression, and 'as' assumes a value of (absolute) 0. This is 2890compatible with other assemblers. 2891 2892 2893File: as.info, Node: Integer Exprs, Prev: Empty Exprs, Up: Expressions 2894 28956.2 Integer Expressions 2896======================= 2897 2898An "integer expression" is one or more _arguments_ delimited by 2899_operators_. 2900 2901* Menu: 2902 2903* Arguments:: Arguments 2904* Operators:: Operators 2905* Prefix Ops:: Prefix Operators 2906* Infix Ops:: Infix Operators 2907 2908 2909File: as.info, Node: Arguments, Next: Operators, Up: Integer Exprs 2910 29116.2.1 Arguments 2912--------------- 2913 2914"Arguments" are symbols, numbers or subexpressions. In other contexts 2915arguments are sometimes called "arithmetic operands". In this manual, 2916to avoid confusing them with the "instruction operands" of the machine 2917language, we use the term "argument" to refer to parts of expressions 2918only, reserving the word "operand" to refer only to machine instruction 2919operands. 2920 2921 Symbols are evaluated to yield {SECTION NNN} where SECTION is one of 2922text, data, bss, absolute, or undefined. NNN is a signed, 2's 2923complement 32 bit integer. 2924 2925 Numbers are usually integers. 2926 2927 A number can be a flonum or bignum. In this case, you are warned 2928that only the low order 32 bits are used, and 'as' pretends these 32 2929bits are an integer. You may write integer-manipulating instructions 2930that act on exotic constants, compatible with other assemblers. 2931 2932 Subexpressions are a left parenthesis '(' followed by an integer 2933expression, followed by a right parenthesis ')'; or a prefix operator 2934followed by an argument. 2935 2936 2937File: as.info, Node: Operators, Next: Prefix Ops, Prev: Arguments, Up: Integer Exprs 2938 29396.2.2 Operators 2940--------------- 2941 2942"Operators" are arithmetic functions, like '+' or '%'. Prefix operators 2943are followed by an argument. Infix operators appear between their 2944arguments. Operators may be preceded and/or followed by whitespace. 2945 2946 2947File: as.info, Node: Prefix Ops, Next: Infix Ops, Prev: Operators, Up: Integer Exprs 2948 29496.2.3 Prefix Operator 2950--------------------- 2951 2952'as' has the following "prefix operators". They each take one argument, 2953which must be absolute. 2954 2955'-' 2956 "Negation". Two's complement negation. 2957'~' 2958 "Complementation". Bitwise not. 2959 2960 2961File: as.info, Node: Infix Ops, Prev: Prefix Ops, Up: Integer Exprs 2962 29636.2.4 Infix Operators 2964--------------------- 2965 2966"Infix operators" take two arguments, one on either side. Operators 2967have precedence, but operations with equal precedence are performed left 2968to right. Apart from '+' or '-', both arguments must be absolute, and 2969the result is absolute. 2970 2971 1. Highest Precedence 2972 2973 '*' 2974 "Multiplication". 2975 2976 '/' 2977 "Division". Truncation is the same as the C operator '/' 2978 2979 '%' 2980 "Remainder". 2981 2982 '<<' 2983 "Shift Left". Same as the C operator '<<'. 2984 2985 '>>' 2986 "Shift Right". Same as the C operator '>>'. 2987 2988 2. Intermediate precedence 2989 2990 '|' 2991 2992 "Bitwise Inclusive Or". 2993 2994 '&' 2995 "Bitwise And". 2996 2997 '^' 2998 "Bitwise Exclusive Or". 2999 3000 '!' 3001 "Bitwise Or Not". 3002 3003 3. Low Precedence 3004 3005 '+' 3006 "Addition". If either argument is absolute, the result has 3007 the section of the other argument. You may not add together 3008 arguments from different sections. 3009 3010 '-' 3011 "Subtraction". If the right argument is absolute, the result 3012 has the section of the left argument. If both arguments are 3013 in the same section, the result is absolute. You may not 3014 subtract arguments from different sections. 3015 3016 '==' 3017 "Is Equal To" 3018 '<>' 3019 '!=' 3020 "Is Not Equal To" 3021 '<' 3022 "Is Less Than" 3023 '>' 3024 "Is Greater Than" 3025 '>=' 3026 "Is Greater Than Or Equal To" 3027 '<=' 3028 "Is Less Than Or Equal To" 3029 3030 The comparison operators can be used as infix operators. A 3031 true results has a value of -1 whereas a false result has a 3032 value of 0. Note, these operators perform signed comparisons. 3033 3034 4. Lowest Precedence 3035 3036 '&&' 3037 "Logical And". 3038 3039 '||' 3040 "Logical Or". 3041 3042 These two logical operations can be used to combine the 3043 results of sub expressions. Note, unlike the comparison 3044 operators a true result returns a value of 1 but a false 3045 results does still return 0. Also note that the logical or 3046 operator has a slightly lower precedence than logical and. 3047 3048 In short, it's only meaningful to add or subtract the _offsets_ in an 3049address; you can only have a defined section in one of the two 3050arguments. 3051 3052 3053File: as.info, Node: Pseudo Ops, Next: Object Attributes, Prev: Expressions, Up: Top 3054 30557 Assembler Directives 3056********************** 3057 3058All assembler directives have names that begin with a period ('.'). The 3059names are case insensitive for most targets, and usually written in 3060lower case. 3061 3062 This chapter discusses directives that are available regardless of 3063the target machine configuration for the GNU assembler. Some machine 3064configurations provide additional directives. *Note Machine 3065Dependencies::. 3066 3067* Menu: 3068 3069* Abort:: '.abort' 3070* ABORT (COFF):: '.ABORT' 3071 3072* Align:: '.align ABS-EXPR , ABS-EXPR' 3073* Altmacro:: '.altmacro' 3074* Ascii:: '.ascii "STRING"'... 3075* Asciz:: '.asciz "STRING"'... 3076* Balign:: '.balign ABS-EXPR , ABS-EXPR' 3077* Bundle directives:: '.bundle_align_mode ABS-EXPR', etc 3078* Byte:: '.byte EXPRESSIONS' 3079* CFI directives:: '.cfi_startproc [simple]', '.cfi_endproc', etc. 3080* Comm:: '.comm SYMBOL , LENGTH ' 3081* Data:: '.data SUBSECTION' 3082* Def:: '.def NAME' 3083* Desc:: '.desc SYMBOL, ABS-EXPRESSION' 3084* Dim:: '.dim' 3085 3086* Double:: '.double FLONUMS' 3087* Eject:: '.eject' 3088* Else:: '.else' 3089* Elseif:: '.elseif' 3090* End:: '.end' 3091* Endef:: '.endef' 3092 3093* Endfunc:: '.endfunc' 3094* Endif:: '.endif' 3095* Equ:: '.equ SYMBOL, EXPRESSION' 3096* Equiv:: '.equiv SYMBOL, EXPRESSION' 3097* Eqv:: '.eqv SYMBOL, EXPRESSION' 3098* Err:: '.err' 3099* Error:: '.error STRING' 3100* Exitm:: '.exitm' 3101* Extern:: '.extern' 3102* Fail:: '.fail' 3103* File:: '.file' 3104* Fill:: '.fill REPEAT , SIZE , VALUE' 3105* Float:: '.float FLONUMS' 3106* Func:: '.func' 3107* Global:: '.global SYMBOL', '.globl SYMBOL' 3108* Gnu_attribute:: '.gnu_attribute TAG,VALUE' 3109* Hidden:: '.hidden NAMES' 3110 3111* hword:: '.hword EXPRESSIONS' 3112* Ident:: '.ident' 3113* If:: '.if ABSOLUTE EXPRESSION' 3114* Incbin:: '.incbin "FILE"[,SKIP[,COUNT]]' 3115* Include:: '.include "FILE"' 3116* Int:: '.int EXPRESSIONS' 3117* Internal:: '.internal NAMES' 3118 3119* Irp:: '.irp SYMBOL,VALUES'... 3120* Irpc:: '.irpc SYMBOL,VALUES'... 3121* Lcomm:: '.lcomm SYMBOL , LENGTH' 3122* Lflags:: '.lflags' 3123* Line:: '.line LINE-NUMBER' 3124 3125* Linkonce:: '.linkonce [TYPE]' 3126* List:: '.list' 3127* Ln:: '.ln LINE-NUMBER' 3128* Loc:: '.loc FILENO LINENO' 3129* Loc_mark_labels:: '.loc_mark_labels ENABLE' 3130* Local:: '.local NAMES' 3131 3132* Long:: '.long EXPRESSIONS' 3133 3134* Macro:: '.macro NAME ARGS'... 3135* MRI:: '.mri VAL' 3136* Noaltmacro:: '.noaltmacro' 3137* Nolist:: '.nolist' 3138* Octa:: '.octa BIGNUMS' 3139* Offset:: '.offset LOC' 3140* Org:: '.org NEW-LC, FILL' 3141* P2align:: '.p2align ABS-EXPR, ABS-EXPR, ABS-EXPR' 3142* PopSection:: '.popsection' 3143* Previous:: '.previous' 3144 3145* Print:: '.print STRING' 3146* Protected:: '.protected NAMES' 3147 3148* Psize:: '.psize LINES, COLUMNS' 3149* Purgem:: '.purgem NAME' 3150* PushSection:: '.pushsection NAME' 3151 3152* Quad:: '.quad BIGNUMS' 3153* Reloc:: '.reloc OFFSET, RELOC_NAME[, EXPRESSION]' 3154* Rept:: '.rept COUNT' 3155* Sbttl:: '.sbttl "SUBHEADING"' 3156* Scl:: '.scl CLASS' 3157* Section:: '.section NAME[, FLAGS]' 3158 3159* Set:: '.set SYMBOL, EXPRESSION' 3160* Short:: '.short EXPRESSIONS' 3161* Single:: '.single FLONUMS' 3162* Size:: '.size [NAME , EXPRESSION]' 3163* Skip:: '.skip SIZE , FILL' 3164 3165* Sleb128:: '.sleb128 EXPRESSIONS' 3166* Space:: '.space SIZE , FILL' 3167* Stab:: '.stabd, .stabn, .stabs' 3168 3169* String:: '.string "STR"', '.string8 "STR"', '.string16 "STR"', '.string32 "STR"', '.string64 "STR"' 3170* Struct:: '.struct EXPRESSION' 3171* SubSection:: '.subsection' 3172* Symver:: '.symver NAME,NAME2@NODENAME' 3173 3174* Tag:: '.tag STRUCTNAME' 3175 3176* Text:: '.text SUBSECTION' 3177* Title:: '.title "HEADING"' 3178* Type:: '.type <INT | NAME , TYPE DESCRIPTION>' 3179 3180* Uleb128:: '.uleb128 EXPRESSIONS' 3181* Val:: '.val ADDR' 3182 3183* Version:: '.version "STRING"' 3184* VTableEntry:: '.vtable_entry TABLE, OFFSET' 3185* VTableInherit:: '.vtable_inherit CHILD, PARENT' 3186 3187* Warning:: '.warning STRING' 3188* Weak:: '.weak NAMES' 3189* Weakref:: '.weakref ALIAS, SYMBOL' 3190* Word:: '.word EXPRESSIONS' 3191* Zero:: '.zero SIZE' 3192* Deprecated:: Deprecated Directives 3193 3194 3195File: as.info, Node: Abort, Next: ABORT (COFF), Up: Pseudo Ops 3196 31977.1 '.abort' 3198============ 3199 3200This directive stops the assembly immediately. It is for compatibility 3201with other assemblers. The original idea was that the assembly language 3202source would be piped into the assembler. If the sender of the source 3203quit, it could use this directive tells 'as' to quit also. One day 3204'.abort' will not be supported. 3205 3206 3207File: as.info, Node: ABORT (COFF), Next: Align, Prev: Abort, Up: Pseudo Ops 3208 32097.2 '.ABORT' (COFF) 3210=================== 3211 3212When producing COFF output, 'as' accepts this directive as a synonym for 3213'.abort'. 3214 3215 3216File: as.info, Node: Align, Next: Altmacro, Prev: ABORT (COFF), Up: Pseudo Ops 3217 32187.3 '.align ABS-EXPR, ABS-EXPR, ABS-EXPR' 3219========================================= 3220 3221Pad the location counter (in the current subsection) to a particular 3222storage boundary. The first expression (which must be absolute) is the 3223alignment required, as described below. 3224 3225 The second expression (also absolute) gives the fill value to be 3226stored in the padding bytes. It (and the comma) may be omitted. If it 3227is omitted, the padding bytes are normally zero. However, on some 3228systems, if the section is marked as containing code and the fill value 3229is omitted, the space is filled with no-op instructions. 3230 3231 The third expression is also absolute, and is also optional. If it 3232is present, it is the maximum number of bytes that should be skipped by 3233this alignment directive. If doing the alignment would require skipping 3234more bytes than the specified maximum, then the alignment is not done at 3235all. You can omit the fill value (the second argument) entirely by 3236simply using two commas after the required alignment; this can be useful 3237if you want the alignment to be filled with no-op instructions when 3238appropriate. 3239 3240 The way the required alignment is specified varies from system to 3241system. For the arc, hppa, i386 using ELF, i860, iq2000, m68k, or1k, 3242s390, sparc, tic4x, tic80 and xtensa, the first expression is the 3243alignment request in bytes. For example '.align 8' advances the 3244location counter until it is a multiple of 8. If the location counter 3245is already a multiple of 8, no change is needed. For the tic54x, the 3246first expression is the alignment request in words. 3247 3248 For other systems, including ppc, i386 using a.out format, arm and 3249strongarm, it is the number of low-order zero bits the location counter 3250must have after advancement. For example '.align 3' advances the 3251location counter until it a multiple of 8. If the location counter is 3252already a multiple of 8, no change is needed. 3253 3254 This inconsistency is due to the different behaviors of the various 3255native assemblers for these systems which GAS must emulate. GAS also 3256provides '.balign' and '.p2align' directives, described later, which 3257have a consistent behavior across all architectures (but are specific to 3258GAS). 3259 3260 3261File: as.info, Node: Altmacro, Next: Ascii, Prev: Align, Up: Pseudo Ops 3262 32637.4 '.altmacro' 3264=============== 3265 3266Enable alternate macro mode, enabling: 3267 3268'LOCAL NAME [ , ... ]' 3269 One additional directive, 'LOCAL', is available. It is used to 3270 generate a string replacement for each of the NAME arguments, and 3271 replace any instances of NAME in each macro expansion. The 3272 replacement string is unique in the assembly, and different for 3273 each separate macro expansion. 'LOCAL' allows you to write macros 3274 that define symbols, without fear of conflict between separate 3275 macro expansions. 3276 3277'String delimiters' 3278 You can write strings delimited in these other ways besides 3279 '"STRING"': 3280 3281 ''STRING'' 3282 You can delimit strings with single-quote characters. 3283 3284 '<STRING>' 3285 You can delimit strings with matching angle brackets. 3286 3287'single-character string escape' 3288 To include any single character literally in a string (even if the 3289 character would otherwise have some special meaning), you can 3290 prefix the character with '!' (an exclamation mark). For example, 3291 you can write '<4.3 !> 5.4!!>' to get the literal text '4.3 > 3292 5.4!'. 3293 3294'Expression results as strings' 3295 You can write '%EXPR' to evaluate the expression EXPR and use the 3296 result as a string. 3297 3298 3299File: as.info, Node: Ascii, Next: Asciz, Prev: Altmacro, Up: Pseudo Ops 3300 33017.5 '.ascii "STRING"'... 3302======================== 3303 3304'.ascii' expects zero or more string literals (*note Strings::) 3305separated by commas. It assembles each string (with no automatic 3306trailing zero byte) into consecutive addresses. 3307 3308 3309File: as.info, Node: Asciz, Next: Balign, Prev: Ascii, Up: Pseudo Ops 3310 33117.6 '.asciz "STRING"'... 3312======================== 3313 3314'.asciz' is just like '.ascii', but each string is followed by a zero 3315byte. The "z" in '.asciz' stands for "zero". 3316 3317 3318File: as.info, Node: Balign, Next: Bundle directives, Prev: Asciz, Up: Pseudo Ops 3319 33207.7 '.balign[wl] ABS-EXPR, ABS-EXPR, ABS-EXPR' 3321============================================== 3322 3323Pad the location counter (in the current subsection) to a particular 3324storage boundary. The first expression (which must be absolute) is the 3325alignment request in bytes. For example '.balign 8' advances the 3326location counter until it is a multiple of 8. If the location counter 3327is already a multiple of 8, no change is needed. 3328 3329 The second expression (also absolute) gives the fill value to be 3330stored in the padding bytes. It (and the comma) may be omitted. If it 3331is omitted, the padding bytes are normally zero. However, on some 3332systems, if the section is marked as containing code and the fill value 3333is omitted, the space is filled with no-op instructions. 3334 3335 The third expression is also absolute, and is also optional. If it 3336is present, it is the maximum number of bytes that should be skipped by 3337this alignment directive. If doing the alignment would require skipping 3338more bytes than the specified maximum, then the alignment is not done at 3339all. You can omit the fill value (the second argument) entirely by 3340simply using two commas after the required alignment; this can be useful 3341if you want the alignment to be filled with no-op instructions when 3342appropriate. 3343 3344 The '.balignw' and '.balignl' directives are variants of the 3345'.balign' directive. The '.balignw' directive treats the fill pattern 3346as a two byte word value. The '.balignl' directives treats the fill 3347pattern as a four byte longword value. For example, '.balignw 4,0x368d' 3348will align to a multiple of 4. If it skips two bytes, they will be 3349filled in with the value 0x368d (the exact placement of the bytes 3350depends upon the endianness of the processor). If it skips 1 or 3 3351bytes, the fill value is undefined. 3352 3353 3354File: as.info, Node: Bundle directives, Next: Byte, Prev: Balign, Up: Pseudo Ops 3355 33567.8 Bundle directives 3357===================== 3358 33597.8.1 '.bundle_align_mode ABS-EXPR' 3360----------------------------------- 3361 3362'.bundle_align_mode' enables or disables "aligned instruction bundle" 3363mode. In this mode, sequences of adjacent instructions are grouped into 3364fixed-sized "bundles". If the argument is zero, this mode is disabled 3365(which is the default state). If the argument it not zero, it gives the 3366size of an instruction bundle as a power of two (as for the '.p2align' 3367directive, *note P2align::). 3368 3369 For some targets, it's an ABI requirement that no instruction may 3370span a certain aligned boundary. A "bundle" is simply a sequence of 3371instructions that starts on an aligned boundary. For example, if 3372ABS-EXPR is '5' then the bundle size is 32, so each aligned chunk of 32 3373bytes is a bundle. When aligned instruction bundle mode is in effect, 3374no single instruction may span a boundary between bundles. If an 3375instruction would start too close to the end of a bundle for the length 3376of that particular instruction to fit within the bundle, then the space 3377at the end of that bundle is filled with no-op instructions so the 3378instruction starts in the next bundle. As a corollary, it's an error if 3379any single instruction's encoding is longer than the bundle size. 3380 33817.8.2 '.bundle_lock' and '.bundle_unlock' 3382----------------------------------------- 3383 3384The '.bundle_lock' and directive '.bundle_unlock' directives allow 3385explicit control over instruction bundle padding. These directives are 3386only valid when '.bundle_align_mode' has been used to enable aligned 3387instruction bundle mode. It's an error if they appear when 3388'.bundle_align_mode' has not been used at all, or when the last 3389directive was '.bundle_align_mode 0'. 3390 3391 For some targets, it's an ABI requirement that certain instructions 3392may appear only as part of specified permissible sequences of multiple 3393instructions, all within the same bundle. A pair of '.bundle_lock' and 3394'.bundle_unlock' directives define a "bundle-locked" instruction 3395sequence. For purposes of aligned instruction bundle mode, a sequence 3396starting with '.bundle_lock' and ending with '.bundle_unlock' is treated 3397as a single instruction. That is, the entire sequence must fit into a 3398single bundle and may not span a bundle boundary. If necessary, no-op 3399instructions will be inserted before the first instruction of the 3400sequence so that the whole sequence starts on an aligned bundle 3401boundary. It's an error if the sequence is longer than the bundle size. 3402 3403 For convenience when using '.bundle_lock' and '.bundle_unlock' inside 3404assembler macros (*note Macro::), bundle-locked sequences may be nested. 3405That is, a second '.bundle_lock' directive before the next 3406'.bundle_unlock' directive has no effect except that it must be matched 3407by another closing '.bundle_unlock' so that there is the same number of 3408'.bundle_lock' and '.bundle_unlock' directives. 3409 3410 3411File: as.info, Node: Byte, Next: CFI directives, Prev: Bundle directives, Up: Pseudo Ops 3412 34137.9 '.byte EXPRESSIONS' 3414======================= 3415 3416'.byte' expects zero or more expressions, separated by commas. Each 3417expression is assembled into the next byte. 3418 3419 3420File: as.info, Node: CFI directives, Next: Comm, Prev: Byte, Up: Pseudo Ops 3421 34227.10 CFI directives 3423=================== 3424 34257.10.1 '.cfi_sections SECTION_LIST' 3426----------------------------------- 3427 3428'.cfi_sections' may be used to specify whether CFI directives should 3429emit '.eh_frame' section and/or '.debug_frame' section. If SECTION_LIST 3430is '.eh_frame', '.eh_frame' is emitted, if SECTION_LIST is 3431'.debug_frame', '.debug_frame' is emitted. To emit both use '.eh_frame, 3432.debug_frame'. The default if this directive is not used is 3433'.cfi_sections .eh_frame'. 3434 3435 On targets that support compact unwinding tables these can be 3436generated by specifying '.eh_frame_entry' instead of '.eh_frame'. 3437 3438 Some targets may support an additional name, such as '.c6xabi.exidx' 3439which is used by the target. 3440 3441 The '.cfi_sections' directive can be repeated, with the same or 3442different arguments, provided that CFI generation has not yet started. 3443Once CFI generation has started however the section list is fixed and 3444any attempts to redefine it will result in an error. 3445 34467.10.2 '.cfi_startproc [simple]' 3447-------------------------------- 3448 3449'.cfi_startproc' is used at the beginning of each function that should 3450have an entry in '.eh_frame'. It initializes some internal data 3451structures. Don't forget to close the function by '.cfi_endproc'. 3452 3453 Unless '.cfi_startproc' is used along with parameter 'simple' it also 3454emits some architecture dependent initial CFI instructions. 3455 34567.10.3 '.cfi_endproc' 3457--------------------- 3458 3459'.cfi_endproc' is used at the end of a function where it closes its 3460unwind entry previously opened by '.cfi_startproc', and emits it to 3461'.eh_frame'. 3462 34637.10.4 '.cfi_personality ENCODING [, EXP]' 3464------------------------------------------ 3465 3466'.cfi_personality' defines personality routine and its encoding. 3467ENCODING must be a constant determining how the personality should be 3468encoded. If it is 255 ('DW_EH_PE_omit'), second argument is not 3469present, otherwise second argument should be a constant or a symbol 3470name. When using indirect encodings, the symbol provided should be the 3471location where personality can be loaded from, not the personality 3472routine itself. The default after '.cfi_startproc' is '.cfi_personality 34730xff', no personality routine. 3474 34757.10.5 '.cfi_personality_id ID' 3476------------------------------- 3477 3478'cfi_personality_id' defines a personality routine by its index as 3479defined in a compact unwinding format. Only valid when generating 3480compact EH frames (i.e. with '.cfi_sections eh_frame_entry'. 3481 34827.10.6 '.cfi_fde_data [OPCODE1 [, ...]]' 3483---------------------------------------- 3484 3485'cfi_fde_data' is used to describe the compact unwind opcodes to be used 3486for the current function. These are emitted inline in the 3487'.eh_frame_entry' section if small enough and there is no LSDA, or in 3488the '.gnu.extab' section otherwise. Only valid when generating compact 3489EH frames (i.e. with '.cfi_sections eh_frame_entry'. 3490 34917.10.7 '.cfi_lsda ENCODING [, EXP]' 3492----------------------------------- 3493 3494'.cfi_lsda' defines LSDA and its encoding. ENCODING must be a constant 3495determining how the LSDA should be encoded. If it is 255 3496('DW_EH_PE_omit'), the second argument is not present, otherwise the 3497second argument should be a constant or a symbol name. The default 3498after '.cfi_startproc' is '.cfi_lsda 0xff', meaning that no LSDA is 3499present. 3500 35017.10.8 '.cfi_inline_lsda' [ALIGN] 3502--------------------------------- 3503 3504'.cfi_inline_lsda' marks the start of a LSDA data section and switches 3505to the corresponding '.gnu.extab' section. Must be preceded by a CFI 3506block containing a '.cfi_lsda' directive. Only valid when generating 3507compact EH frames (i.e. with '.cfi_sections eh_frame_entry'. 3508 3509 The table header and unwinding opcodes will be generated at this 3510point, so that they are immediately followed by the LSDA data. The 3511symbol referenced by the '.cfi_lsda' directive should still be defined 3512in case a fallback FDE based encoding is used. The LSDA data is 3513terminated by a section directive. 3514 3515 The optional ALIGN argument specifies the alignment required. The 3516alignment is specified as a power of two, as with the '.p2align' 3517directive. 3518 35197.10.9 '.cfi_def_cfa REGISTER, OFFSET' 3520-------------------------------------- 3521 3522'.cfi_def_cfa' defines a rule for computing CFA as: take address from 3523REGISTER and add OFFSET to it. 3524 35257.10.10 '.cfi_def_cfa_register REGISTER' 3526---------------------------------------- 3527 3528'.cfi_def_cfa_register' modifies a rule for computing CFA. From now on 3529REGISTER will be used instead of the old one. Offset remains the same. 3530 35317.10.11 '.cfi_def_cfa_offset OFFSET' 3532------------------------------------ 3533 3534'.cfi_def_cfa_offset' modifies a rule for computing CFA. Register 3535remains the same, but OFFSET is new. Note that it is the absolute 3536offset that will be added to a defined register to compute CFA address. 3537 35387.10.12 '.cfi_adjust_cfa_offset OFFSET' 3539--------------------------------------- 3540 3541Same as '.cfi_def_cfa_offset' but OFFSET is a relative value that is 3542added/substracted from the previous offset. 3543 35447.10.13 '.cfi_offset REGISTER, OFFSET' 3545-------------------------------------- 3546 3547Previous value of REGISTER is saved at offset OFFSET from CFA. 3548 35497.10.14 '.cfi_val_offset REGISTER, OFFSET' 3550------------------------------------------ 3551 3552Previous value of REGISTER is CFA + OFFSET. 3553 35547.10.15 '.cfi_rel_offset REGISTER, OFFSET' 3555------------------------------------------ 3556 3557Previous value of REGISTER is saved at offset OFFSET from the current 3558CFA register. This is transformed to '.cfi_offset' using the known 3559displacement of the CFA register from the CFA. This is often easier to 3560use, because the number will match the code it's annotating. 3561 35627.10.16 '.cfi_register REGISTER1, REGISTER2' 3563-------------------------------------------- 3564 3565Previous value of REGISTER1 is saved in register REGISTER2. 3566 35677.10.17 '.cfi_restore REGISTER' 3568------------------------------- 3569 3570'.cfi_restore' says that the rule for REGISTER is now the same as it was 3571at the beginning of the function, after all initial instruction added by 3572'.cfi_startproc' were executed. 3573 35747.10.18 '.cfi_undefined REGISTER' 3575--------------------------------- 3576 3577From now on the previous value of REGISTER can't be restored anymore. 3578 35797.10.19 '.cfi_same_value REGISTER' 3580---------------------------------- 3581 3582Current value of REGISTER is the same like in the previous frame, i.e. 3583no restoration needed. 3584 35857.10.20 '.cfi_remember_state' and '.cfi_restore_state' 3586------------------------------------------------------ 3587 3588'.cfi_remember_state' pushes the set of rules for every register onto an 3589implicit stack, while '.cfi_restore_state' pops them off the stack and 3590places them in the current row. This is useful for situations where you 3591have multiple '.cfi_*' directives that need to be undone due to the 3592control flow of the program. For example, we could have something like 3593this (assuming the CFA is the value of 'rbp'): 3594 3595 je label 3596 popq %rbx 3597 .cfi_restore %rbx 3598 popq %r12 3599 .cfi_restore %r12 3600 popq %rbp 3601 .cfi_restore %rbp 3602 .cfi_def_cfa %rsp, 8 3603 ret 3604 label: 3605 /* Do something else */ 3606 3607 Here, we want the '.cfi' directives to affect only the rows 3608corresponding to the instructions before 'label'. This means we'd have 3609to add multiple '.cfi' directives after 'label' to recreate the original 3610save locations of the registers, as well as setting the CFA back to the 3611value of 'rbp'. This would be clumsy, and result in a larger binary 3612size. Instead, we can write: 3613 3614 je label 3615 popq %rbx 3616 .cfi_remember_state 3617 .cfi_restore %rbx 3618 popq %r12 3619 .cfi_restore %r12 3620 popq %rbp 3621 .cfi_restore %rbp 3622 .cfi_def_cfa %rsp, 8 3623 ret 3624 label: 3625 .cfi_restore_state 3626 /* Do something else */ 3627 3628 That way, the rules for the instructions after 'label' will be the 3629same as before the first '.cfi_restore' without having to use multiple 3630'.cfi' directives. 3631 36327.10.21 '.cfi_return_column REGISTER' 3633------------------------------------- 3634 3635Change return column REGISTER, i.e. the return address is either 3636directly in REGISTER or can be accessed by rules for REGISTER. 3637 36387.10.22 '.cfi_signal_frame' 3639--------------------------- 3640 3641Mark current function as signal trampoline. 3642 36437.10.23 '.cfi_window_save' 3644-------------------------- 3645 3646SPARC register window has been saved. 3647 36487.10.24 '.cfi_escape' EXPRESSION[, ...] 3649--------------------------------------- 3650 3651Allows the user to add arbitrary bytes to the unwind info. One might 3652use this to add OS-specific CFI opcodes, or generic CFI opcodes that GAS 3653does not yet support. 3654 36557.10.25 '.cfi_val_encoded_addr REGISTER, ENCODING, LABEL' 3656--------------------------------------------------------- 3657 3658The current value of REGISTER is LABEL. The value of LABEL will be 3659encoded in the output file according to ENCODING; see the description of 3660'.cfi_personality' for details on this encoding. 3661 3662 The usefulness of equating a register to a fixed label is probably 3663limited to the return address register. Here, it can be useful to mark 3664a code segment that has only one return address which is reached by a 3665direct branch and no copy of the return address exists in memory or 3666another register. 3667 3668 3669File: as.info, Node: Comm, Next: Data, Prev: CFI directives, Up: Pseudo Ops 3670 36717.11 '.comm SYMBOL , LENGTH ' 3672============================= 3673 3674'.comm' declares a common symbol named SYMBOL. When linking, a common 3675symbol in one object file may be merged with a defined or common symbol 3676of the same name in another object file. If 'ld' does not see a 3677definition for the symbol-just one or more common symbols-then it will 3678allocate LENGTH bytes of uninitialized memory. LENGTH must be an 3679absolute expression. If 'ld' sees multiple common symbols with the same 3680name, and they do not all have the same size, it will allocate space 3681using the largest size. 3682 3683 When using ELF or (as a GNU extension) PE, the '.comm' directive 3684takes an optional third argument. This is the desired alignment of the 3685symbol, specified for ELF as a byte boundary (for example, an alignment 3686of 16 means that the least significant 4 bits of the address should be 3687zero), and for PE as a power of two (for example, an alignment of 5 3688means aligned to a 32-byte boundary). The alignment must be an absolute 3689expression, and it must be a power of two. If 'ld' allocates 3690uninitialized memory for the common symbol, it will use the alignment 3691when placing the symbol. If no alignment is specified, 'as' will set 3692the alignment to the largest power of two less than or equal to the size 3693of the symbol, up to a maximum of 16 on ELF, or the default section 3694alignment of 4 on PE(1). 3695 3696 The syntax for '.comm' differs slightly on the HPPA. The syntax is 3697'SYMBOL .comm, LENGTH'; SYMBOL is optional. 3698 3699 ---------- Footnotes ---------- 3700 3701 (1) This is not the same as the executable image file alignment 3702controlled by 'ld''s '--section-alignment' option; image file sections 3703in PE are aligned to multiples of 4096, which is far too large an 3704alignment for ordinary variables. It is rather the default alignment 3705for (non-debug) sections within object ('*.o') files, which are less 3706strictly aligned. 3707 3708 3709File: as.info, Node: Data, Next: Def, Prev: Comm, Up: Pseudo Ops 3710 37117.12 '.data SUBSECTION' 3712======================= 3713 3714'.data' tells 'as' to assemble the following statements onto the end of 3715the data subsection numbered SUBSECTION (which is an absolute 3716expression). If SUBSECTION is omitted, it defaults to zero. 3717 3718 3719File: as.info, Node: Def, Next: Desc, Prev: Data, Up: Pseudo Ops 3720 37217.13 '.def NAME' 3722================ 3723 3724Begin defining debugging information for a symbol NAME; the definition 3725extends until the '.endef' directive is encountered. 3726 3727 3728File: as.info, Node: Desc, Next: Dim, Prev: Def, Up: Pseudo Ops 3729 37307.14 '.desc SYMBOL, ABS-EXPRESSION' 3731=================================== 3732 3733This directive sets the descriptor of the symbol (*note Symbol 3734Attributes::) to the low 16 bits of an absolute expression. 3735 3736 The '.desc' directive is not available when 'as' is configured for 3737COFF output; it is only for 'a.out' or 'b.out' object format. For the 3738sake of compatibility, 'as' accepts it, but produces no output, when 3739configured for COFF. 3740 3741 3742File: as.info, Node: Dim, Next: Double, Prev: Desc, Up: Pseudo Ops 3743 37447.15 '.dim' 3745=========== 3746 3747This directive is generated by compilers to include auxiliary debugging 3748information in the symbol table. It is only permitted inside 3749'.def'/'.endef' pairs. 3750 3751 3752File: as.info, Node: Double, Next: Eject, Prev: Dim, Up: Pseudo Ops 3753 37547.16 '.double FLONUMS' 3755====================== 3756 3757'.double' expects zero or more flonums, separated by commas. It 3758assembles floating point numbers. The exact kind of floating point 3759numbers emitted depends on how 'as' is configured. *Note Machine 3760Dependencies::. 3761 3762 3763File: as.info, Node: Eject, Next: Else, Prev: Double, Up: Pseudo Ops 3764 37657.17 '.eject' 3766============= 3767 3768Force a page break at this point, when generating assembly listings. 3769 3770 3771File: as.info, Node: Else, Next: Elseif, Prev: Eject, Up: Pseudo Ops 3772 37737.18 '.else' 3774============ 3775 3776'.else' is part of the 'as' support for conditional assembly; see *note 3777'.if': If. It marks the beginning of a section of code to be assembled 3778if the condition for the preceding '.if' was false. 3779 3780 3781File: as.info, Node: Elseif, Next: End, Prev: Else, Up: Pseudo Ops 3782 37837.19 '.elseif' 3784============== 3785 3786'.elseif' is part of the 'as' support for conditional assembly; see 3787*note '.if': If. It is shorthand for beginning a new '.if' block that 3788would otherwise fill the entire '.else' section. 3789 3790 3791File: as.info, Node: End, Next: Endef, Prev: Elseif, Up: Pseudo Ops 3792 37937.20 '.end' 3794=========== 3795 3796'.end' marks the end of the assembly file. 'as' does not process 3797anything in the file past the '.end' directive. 3798 3799 3800File: as.info, Node: Endef, Next: Endfunc, Prev: End, Up: Pseudo Ops 3801 38027.21 '.endef' 3803============= 3804 3805This directive flags the end of a symbol definition begun with '.def'. 3806 3807 3808File: as.info, Node: Endfunc, Next: Endif, Prev: Endef, Up: Pseudo Ops 3809 38107.22 '.endfunc' 3811=============== 3812 3813'.endfunc' marks the end of a function specified with '.func'. 3814 3815 3816File: as.info, Node: Endif, Next: Equ, Prev: Endfunc, Up: Pseudo Ops 3817 38187.23 '.endif' 3819============= 3820 3821'.endif' is part of the 'as' support for conditional assembly; it marks 3822the end of a block of code that is only assembled conditionally. *Note 3823'.if': If. 3824 3825 3826File: as.info, Node: Equ, Next: Equiv, Prev: Endif, Up: Pseudo Ops 3827 38287.24 '.equ SYMBOL, EXPRESSION' 3829============================== 3830 3831This directive sets the value of SYMBOL to EXPRESSION. It is synonymous 3832with '.set'; see *note '.set': Set. 3833 3834 The syntax for 'equ' on the HPPA is 'SYMBOL .equ EXPRESSION'. 3835 3836 The syntax for 'equ' on the Z80 is 'SYMBOL equ EXPRESSION'. On the 3837Z80 it is an eror if SYMBOL is already defined, but the symbol is not 3838protected from later redefinition. Compare *note Equiv::. 3839 3840 3841File: as.info, Node: Equiv, Next: Eqv, Prev: Equ, Up: Pseudo Ops 3842 38437.25 '.equiv SYMBOL, EXPRESSION' 3844================================ 3845 3846The '.equiv' directive is like '.equ' and '.set', except that the 3847assembler will signal an error if SYMBOL is already defined. Note a 3848symbol which has been referenced but not actually defined is considered 3849to be undefined. 3850 3851 Except for the contents of the error message, this is roughly 3852equivalent to 3853 .ifdef SYM 3854 .err 3855 .endif 3856 .equ SYM,VAL 3857 plus it protects the symbol from later redefinition. 3858 3859 3860File: as.info, Node: Eqv, Next: Err, Prev: Equiv, Up: Pseudo Ops 3861 38627.26 '.eqv SYMBOL, EXPRESSION' 3863============================== 3864 3865The '.eqv' directive is like '.equiv', but no attempt is made to 3866evaluate the expression or any part of it immediately. Instead each 3867time the resulting symbol is used in an expression, a snapshot of its 3868current value is taken. 3869 3870 3871File: as.info, Node: Err, Next: Error, Prev: Eqv, Up: Pseudo Ops 3872 38737.27 '.err' 3874=========== 3875 3876If 'as' assembles a '.err' directive, it will print an error message 3877and, unless the '-Z' option was used, it will not generate an object 3878file. This can be used to signal an error in conditionally compiled 3879code. 3880 3881 3882File: as.info, Node: Error, Next: Exitm, Prev: Err, Up: Pseudo Ops 3883 38847.28 '.error "STRING"' 3885====================== 3886 3887Similarly to '.err', this directive emits an error, but you can specify 3888a string that will be emitted as the error message. If you don't 3889specify the message, it defaults to '".error directive invoked in source 3890file"'. *Note Error and Warning Messages: Errors. 3891 3892 .error "This code has not been assembled and tested." 3893 3894 3895File: as.info, Node: Exitm, Next: Extern, Prev: Error, Up: Pseudo Ops 3896 38977.29 '.exitm' 3898============= 3899 3900Exit early from the current macro definition. *Note Macro::. 3901 3902 3903File: as.info, Node: Extern, Next: Fail, Prev: Exitm, Up: Pseudo Ops 3904 39057.30 '.extern' 3906============== 3907 3908'.extern' is accepted in the source program--for compatibility with 3909other assemblers--but it is ignored. 'as' treats all undefined symbols 3910as external. 3911 3912 3913File: as.info, Node: Fail, Next: File, Prev: Extern, Up: Pseudo Ops 3914 39157.31 '.fail EXPRESSION' 3916======================= 3917 3918Generates an error or a warning. If the value of the EXPRESSION is 500 3919or more, 'as' will print a warning message. If the value is less than 3920500, 'as' will print an error message. The message will include the 3921value of EXPRESSION. This can occasionally be useful inside complex 3922nested macros or conditional assembly. 3923 3924 3925File: as.info, Node: File, Next: Fill, Prev: Fail, Up: Pseudo Ops 3926 39277.32 '.file' 3928============ 3929 3930There are two different versions of the '.file' directive. Targets that 3931support DWARF2 line number information use the DWARF2 version of 3932'.file'. Other targets use the default version. 3933 3934Default Version 3935--------------- 3936 3937This version of the '.file' directive tells 'as' that we are about to 3938start a new logical file. The syntax is: 3939 3940 .file STRING 3941 3942 STRING is the new file name. In general, the filename is recognized 3943whether or not it is surrounded by quotes '"'; but if you wish to 3944specify an empty file name, you must give the quotes-'""'. This 3945statement may go away in future: it is only recognized to be compatible 3946with old 'as' programs. 3947 3948DWARF2 Version 3949-------------- 3950 3951When emitting DWARF2 line number information, '.file' assigns filenames 3952to the '.debug_line' file name table. The syntax is: 3953 3954 .file FILENO FILENAME 3955 3956 The FILENO operand should be a unique positive integer to use as the 3957index of the entry in the table. The FILENAME operand is a C string 3958literal. 3959 3960 The detail of filename indices is exposed to the user because the 3961filename table is shared with the '.debug_info' section of the DWARF2 3962debugging information, and thus the user must know the exact indices 3963that table entries will have. 3964 3965 3966File: as.info, Node: Fill, Next: Float, Prev: File, Up: Pseudo Ops 3967 39687.33 '.fill REPEAT , SIZE , VALUE' 3969================================== 3970 3971REPEAT, SIZE and VALUE are absolute expressions. This emits REPEAT 3972copies of SIZE bytes. REPEAT may be zero or more. SIZE may be zero or 3973more, but if it is more than 8, then it is deemed to have the value 8, 3974compatible with other people's assemblers. The contents of each REPEAT 3975bytes is taken from an 8-byte number. The highest order 4 bytes are 3976zero. The lowest order 4 bytes are VALUE rendered in the byte-order of 3977an integer on the computer 'as' is assembling for. Each SIZE bytes in a 3978repetition is taken from the lowest order SIZE bytes of this number. 3979Again, this bizarre behavior is compatible with other people's 3980assemblers. 3981 3982 SIZE and VALUE are optional. If the second comma and VALUE are 3983absent, VALUE is assumed zero. If the first comma and following tokens 3984are absent, SIZE is assumed to be 1. 3985 3986 3987File: as.info, Node: Float, Next: Func, Prev: Fill, Up: Pseudo Ops 3988 39897.34 '.float FLONUMS' 3990===================== 3991 3992This directive assembles zero or more flonums, separated by commas. It 3993has the same effect as '.single'. The exact kind of floating point 3994numbers emitted depends on how 'as' is configured. *Note Machine 3995Dependencies::. 3996 3997 3998File: as.info, Node: Func, Next: Global, Prev: Float, Up: Pseudo Ops 3999 40007.35 '.func NAME[,LABEL]' 4001========================= 4002 4003'.func' emits debugging information to denote function NAME, and is 4004ignored unless the file is assembled with debugging enabled. Only 4005'--gstabs[+]' is currently supported. LABEL is the entry point of the 4006function and if omitted NAME prepended with the 'leading char' is used. 4007'leading char' is usually '_' or nothing, depending on the target. All 4008functions are currently defined to have 'void' return type. The 4009function must be terminated with '.endfunc'. 4010 4011 4012File: as.info, Node: Global, Next: Gnu_attribute, Prev: Func, Up: Pseudo Ops 4013 40147.36 '.global SYMBOL', '.globl SYMBOL' 4015====================================== 4016 4017'.global' makes the symbol visible to 'ld'. If you define SYMBOL in 4018your partial program, its value is made available to other partial 4019programs that are linked with it. Otherwise, SYMBOL takes its 4020attributes from a symbol of the same name from another file linked into 4021the same program. 4022 4023 Both spellings ('.globl' and '.global') are accepted, for 4024compatibility with other assemblers. 4025 4026 On the HPPA, '.global' is not always enough to make it accessible to 4027other partial programs. You may need the HPPA-only '.EXPORT' directive 4028as well. *Note HPPA Assembler Directives: HPPA Directives. 4029 4030 4031File: as.info, Node: Gnu_attribute, Next: Hidden, Prev: Global, Up: Pseudo Ops 4032 40337.37 '.gnu_attribute TAG,VALUE' 4034=============================== 4035 4036Record a GNU object attribute for this file. *Note Object Attributes::. 4037 4038 4039File: as.info, Node: Hidden, Next: hword, Prev: Gnu_attribute, Up: Pseudo Ops 4040 40417.38 '.hidden NAMES' 4042==================== 4043 4044This is one of the ELF visibility directives. The other two are 4045'.internal' (*note '.internal': Internal.) and '.protected' (*note 4046'.protected': Protected.). 4047 4048 This directive overrides the named symbols default visibility (which 4049is set by their binding: local, global or weak). The directive sets the 4050visibility to 'hidden' which means that the symbols are not visible to 4051other components. Such symbols are always considered to be 'protected' 4052as well. 4053 4054 4055File: as.info, Node: hword, Next: Ident, Prev: Hidden, Up: Pseudo Ops 4056 40577.39 '.hword EXPRESSIONS' 4058========================= 4059 4060This expects zero or more EXPRESSIONS, and emits a 16 bit number for 4061each. 4062 4063 This directive is a synonym for '.short'; depending on the target 4064architecture, it may also be a synonym for '.word'. 4065 4066 4067File: as.info, Node: Ident, Next: If, Prev: hword, Up: Pseudo Ops 4068 40697.40 '.ident' 4070============= 4071 4072This directive is used by some assemblers to place tags in object files. 4073The behavior of this directive varies depending on the target. When 4074using the a.out object file format, 'as' simply accepts the directive 4075for source-file compatibility with existing assemblers, but does not 4076emit anything for it. When using COFF, comments are emitted to the 4077'.comment' or '.rdata' section, depending on the target. When using 4078ELF, comments are emitted to the '.comment' section. 4079 4080 4081File: as.info, Node: If, Next: Incbin, Prev: Ident, Up: Pseudo Ops 4082 40837.41 '.if ABSOLUTE EXPRESSION' 4084============================== 4085 4086'.if' marks the beginning of a section of code which is only considered 4087part of the source program being assembled if the argument (which must 4088be an ABSOLUTE EXPRESSION) is non-zero. The end of the conditional 4089section of code must be marked by '.endif' (*note '.endif': Endif.); 4090optionally, you may include code for the alternative condition, flagged 4091by '.else' (*note '.else': Else.). If you have several conditions to 4092check, '.elseif' may be used to avoid nesting blocks if/else within each 4093subsequent '.else' block. 4094 4095 The following variants of '.if' are also supported: 4096'.ifdef SYMBOL' 4097 Assembles the following section of code if the specified SYMBOL has 4098 been defined. Note a symbol which has been referenced but not yet 4099 defined is considered to be undefined. 4100 4101'.ifb TEXT' 4102 Assembles the following section of code if the operand is blank 4103 (empty). 4104 4105'.ifc STRING1,STRING2' 4106 Assembles the following section of code if the two strings are the 4107 same. The strings may be optionally quoted with single quotes. If 4108 they are not quoted, the first string stops at the first comma, and 4109 the second string stops at the end of the line. Strings which 4110 contain whitespace should be quoted. The string comparison is case 4111 sensitive. 4112 4113'.ifeq ABSOLUTE EXPRESSION' 4114 Assembles the following section of code if the argument is zero. 4115 4116'.ifeqs STRING1,STRING2' 4117 Another form of '.ifc'. The strings must be quoted using double 4118 quotes. 4119 4120'.ifge ABSOLUTE EXPRESSION' 4121 Assembles the following section of code if the argument is greater 4122 than or equal to zero. 4123 4124'.ifgt ABSOLUTE EXPRESSION' 4125 Assembles the following section of code if the argument is greater 4126 than zero. 4127 4128'.ifle ABSOLUTE EXPRESSION' 4129 Assembles the following section of code if the argument is less 4130 than or equal to zero. 4131 4132'.iflt ABSOLUTE EXPRESSION' 4133 Assembles the following section of code if the argument is less 4134 than zero. 4135 4136'.ifnb TEXT' 4137 Like '.ifb', but the sense of the test is reversed: this assembles 4138 the following section of code if the operand is non-blank 4139 (non-empty). 4140 4141'.ifnc STRING1,STRING2.' 4142 Like '.ifc', but the sense of the test is reversed: this assembles 4143 the following section of code if the two strings are not the same. 4144 4145'.ifndef SYMBOL' 4146'.ifnotdef SYMBOL' 4147 Assembles the following section of code if the specified SYMBOL has 4148 not been defined. Both spelling variants are equivalent. Note a 4149 symbol which has been referenced but not yet defined is considered 4150 to be undefined. 4151 4152'.ifne ABSOLUTE EXPRESSION' 4153 Assembles the following section of code if the argument is not 4154 equal to zero (in other words, this is equivalent to '.if'). 4155 4156'.ifnes STRING1,STRING2' 4157 Like '.ifeqs', but the sense of the test is reversed: this 4158 assembles the following section of code if the two strings are not 4159 the same. 4160 4161 4162File: as.info, Node: Incbin, Next: Include, Prev: If, Up: Pseudo Ops 4163 41647.42 '.incbin "FILE"[,SKIP[,COUNT]]' 4165==================================== 4166 4167The 'incbin' directive includes FILE verbatim at the current location. 4168You can control the search paths used with the '-I' command-line option 4169(*note Command-Line Options: Invoking.). Quotation marks are required 4170around FILE. 4171 4172 The SKIP argument skips a number of bytes from the start of the FILE. 4173The COUNT argument indicates the maximum number of bytes to read. Note 4174that the data is not aligned in any way, so it is the user's 4175responsibility to make sure that proper alignment is provided both 4176before and after the 'incbin' directive. 4177 4178 4179File: as.info, Node: Include, Next: Int, Prev: Incbin, Up: Pseudo Ops 4180 41817.43 '.include "FILE"' 4182====================== 4183 4184This directive provides a way to include supporting files at specified 4185points in your source program. The code from FILE is assembled as if it 4186followed the point of the '.include'; when the end of the included file 4187is reached, assembly of the original file continues. You can control 4188the search paths used with the '-I' command-line option (*note 4189Command-Line Options: Invoking.). Quotation marks are required around 4190FILE. 4191 4192 4193File: as.info, Node: Int, Next: Internal, Prev: Include, Up: Pseudo Ops 4194 41957.44 '.int EXPRESSIONS' 4196======================= 4197 4198Expect zero or more EXPRESSIONS, of any section, separated by commas. 4199For each expression, emit a number that, at run time, is the value of 4200that expression. The byte order and bit size of the number depends on 4201what kind of target the assembly is for. 4202 4203 4204File: as.info, Node: Internal, Next: Irp, Prev: Int, Up: Pseudo Ops 4205 42067.45 '.internal NAMES' 4207====================== 4208 4209This is one of the ELF visibility directives. The other two are 4210'.hidden' (*note '.hidden': Hidden.) and '.protected' (*note 4211'.protected': Protected.). 4212 4213 This directive overrides the named symbols default visibility (which 4214is set by their binding: local, global or weak). The directive sets the 4215visibility to 'internal' which means that the symbols are considered to 4216be 'hidden' (i.e., not visible to other components), and that some 4217extra, processor specific processing must also be performed upon the 4218symbols as well. 4219 4220 4221File: as.info, Node: Irp, Next: Irpc, Prev: Internal, Up: Pseudo Ops 4222 42237.46 '.irp SYMBOL,VALUES'... 4224============================ 4225 4226Evaluate a sequence of statements assigning different values to SYMBOL. 4227The sequence of statements starts at the '.irp' directive, and is 4228terminated by an '.endr' directive. For each VALUE, SYMBOL is set to 4229VALUE, and the sequence of statements is assembled. If no VALUE is 4230listed, the sequence of statements is assembled once, with SYMBOL set to 4231the null string. To refer to SYMBOL within the sequence of statements, 4232use \SYMBOL. 4233 4234 For example, assembling 4235 4236 .irp param,1,2,3 4237 move d\param,sp@- 4238 .endr 4239 4240 is equivalent to assembling 4241 4242 move d1,sp@- 4243 move d2,sp@- 4244 move d3,sp@- 4245 4246 For some caveats with the spelling of SYMBOL, see also *note Macro::. 4247 4248 4249File: as.info, Node: Irpc, Next: Lcomm, Prev: Irp, Up: Pseudo Ops 4250 42517.47 '.irpc SYMBOL,VALUES'... 4252============================= 4253 4254Evaluate a sequence of statements assigning different values to SYMBOL. 4255The sequence of statements starts at the '.irpc' directive, and is 4256terminated by an '.endr' directive. For each character in VALUE, SYMBOL 4257is set to the character, and the sequence of statements is assembled. 4258If no VALUE is listed, the sequence of statements is assembled once, 4259with SYMBOL set to the null string. To refer to SYMBOL within the 4260sequence of statements, use \SYMBOL. 4261 4262 For example, assembling 4263 4264 .irpc param,123 4265 move d\param,sp@- 4266 .endr 4267 4268 is equivalent to assembling 4269 4270 move d1,sp@- 4271 move d2,sp@- 4272 move d3,sp@- 4273 4274 For some caveats with the spelling of SYMBOL, see also the discussion 4275at *Note Macro::. 4276 4277 4278File: as.info, Node: Lcomm, Next: Lflags, Prev: Irpc, Up: Pseudo Ops 4279 42807.48 '.lcomm SYMBOL , LENGTH' 4281============================= 4282 4283Reserve LENGTH (an absolute expression) bytes for a local common denoted 4284by SYMBOL. The section and value of SYMBOL are those of the new local 4285common. The addresses are allocated in the bss section, so that at 4286run-time the bytes start off zeroed. SYMBOL is not declared global 4287(*note '.global': Global.), so is normally not visible to 'ld'. 4288 4289 Some targets permit a third argument to be used with '.lcomm'. This 4290argument specifies the desired alignment of the symbol in the bss 4291section. 4292 4293 The syntax for '.lcomm' differs slightly on the HPPA. The syntax is 4294'SYMBOL .lcomm, LENGTH'; SYMBOL is optional. 4295 4296 4297File: as.info, Node: Lflags, Next: Line, Prev: Lcomm, Up: Pseudo Ops 4298 42997.49 '.lflags' 4300============== 4301 4302'as' accepts this directive, for compatibility with other assemblers, 4303but ignores it. 4304 4305 4306File: as.info, Node: Line, Next: Linkonce, Prev: Lflags, Up: Pseudo Ops 4307 43087.50 '.line LINE-NUMBER' 4309======================== 4310 4311Change the logical line number. LINE-NUMBER must be an absolute 4312expression. The next line has that logical line number. Therefore any 4313other statements on the current line (after a statement separator 4314character) are reported as on logical line number LINE-NUMBER - 1. One 4315day 'as' will no longer support this directive: it is recognized only 4316for compatibility with existing assembler programs. 4317 4318 Even though this is a directive associated with the 'a.out' or 4319'b.out' object-code formats, 'as' still recognizes it when producing 4320COFF output, and treats '.line' as though it were the COFF '.ln' _if_ it 4321is found outside a '.def'/'.endef' pair. 4322 4323 Inside a '.def', '.line' is, instead, one of the directives used by 4324compilers to generate auxiliary symbol information for debugging. 4325 4326 4327File: as.info, Node: Linkonce, Next: List, Prev: Line, Up: Pseudo Ops 4328 43297.51 '.linkonce [TYPE]' 4330======================= 4331 4332Mark the current section so that the linker only includes a single copy 4333of it. This may be used to include the same section in several 4334different object files, but ensure that the linker will only include it 4335once in the final output file. The '.linkonce' pseudo-op must be used 4336for each instance of the section. Duplicate sections are detected based 4337on the section name, so it should be unique. 4338 4339 This directive is only supported by a few object file formats; as of 4340this writing, the only object file format which supports it is the 4341Portable Executable format used on Windows NT. 4342 4343 The TYPE argument is optional. If specified, it must be one of the 4344following strings. For example: 4345 .linkonce same_size 4346 Not all types may be supported on all object file formats. 4347 4348'discard' 4349 Silently discard duplicate sections. This is the default. 4350 4351'one_only' 4352 Warn if there are duplicate sections, but still keep only one copy. 4353 4354'same_size' 4355 Warn if any of the duplicates have different sizes. 4356 4357'same_contents' 4358 Warn if any of the duplicates do not have exactly the same 4359 contents. 4360 4361 4362File: as.info, Node: List, Next: Ln, Prev: Linkonce, Up: Pseudo Ops 4363 43647.52 '.list' 4365============ 4366 4367Control (in conjunction with the '.nolist' directive) whether or not 4368assembly listings are generated. These two directives maintain an 4369internal counter (which is zero initially). '.list' increments the 4370counter, and '.nolist' decrements it. Assembly listings are generated 4371whenever the counter is greater than zero. 4372 4373 By default, listings are disabled. When you enable them (with the 4374'-a' command line option; *note Command-Line Options: Invoking.), the 4375initial value of the listing counter is one. 4376 4377 4378File: as.info, Node: Ln, Next: Loc, Prev: List, Up: Pseudo Ops 4379 43807.53 '.ln LINE-NUMBER' 4381====================== 4382 4383'.ln' is a synonym for '.line'. 4384 4385 4386File: as.info, Node: Loc, Next: Loc_mark_labels, Prev: Ln, Up: Pseudo Ops 4387 43887.54 '.loc FILENO LINENO [COLUMN] [OPTIONS]' 4389============================================ 4390 4391When emitting DWARF2 line number information, the '.loc' directive will 4392add a row to the '.debug_line' line number matrix corresponding to the 4393immediately following assembly instruction. The FILENO, LINENO, and 4394optional COLUMN arguments will be applied to the '.debug_line' state 4395machine before the row is added. 4396 4397 The OPTIONS are a sequence of the following tokens in any order: 4398 4399'basic_block' 4400 This option will set the 'basic_block' register in the 4401 '.debug_line' state machine to 'true'. 4402 4403'prologue_end' 4404 This option will set the 'prologue_end' register in the 4405 '.debug_line' state machine to 'true'. 4406 4407'epilogue_begin' 4408 This option will set the 'epilogue_begin' register in the 4409 '.debug_line' state machine to 'true'. 4410 4411'is_stmt VALUE' 4412 This option will set the 'is_stmt' register in the '.debug_line' 4413 state machine to 'value', which must be either 0 or 1. 4414 4415'isa VALUE' 4416 This directive will set the 'isa' register in the '.debug_line' 4417 state machine to VALUE, which must be an unsigned integer. 4418 4419'discriminator VALUE' 4420 This directive will set the 'discriminator' register in the 4421 '.debug_line' state machine to VALUE, which must be an unsigned 4422 integer. 4423 4424 4425File: as.info, Node: Loc_mark_labels, Next: Local, Prev: Loc, Up: Pseudo Ops 4426 44277.55 '.loc_mark_labels ENABLE' 4428============================== 4429 4430When emitting DWARF2 line number information, the '.loc_mark_labels' 4431directive makes the assembler emit an entry to the '.debug_line' line 4432number matrix with the 'basic_block' register in the state machine set 4433whenever a code label is seen. The ENABLE argument should be either 1 4434or 0, to enable or disable this function respectively. 4435 4436 4437File: as.info, Node: Local, Next: Long, Prev: Loc_mark_labels, Up: Pseudo Ops 4438 44397.56 '.local NAMES' 4440=================== 4441 4442This directive, which is available for ELF targets, marks each symbol in 4443the comma-separated list of 'names' as a local symbol so that it will 4444not be externally visible. If the symbols do not already exist, they 4445will be created. 4446 4447 For targets where the '.lcomm' directive (*note Lcomm::) does not 4448accept an alignment argument, which is the case for most ELF targets, 4449the '.local' directive can be used in combination with '.comm' (*note 4450Comm::) to define aligned local common data. 4451 4452 4453File: as.info, Node: Long, Next: Macro, Prev: Local, Up: Pseudo Ops 4454 44557.57 '.long EXPRESSIONS' 4456======================== 4457 4458'.long' is the same as '.int'. *Note '.int': Int. 4459 4460 4461File: as.info, Node: Macro, Next: MRI, Prev: Long, Up: Pseudo Ops 4462 44637.58 '.macro' 4464============= 4465 4466The commands '.macro' and '.endm' allow you to define macros that 4467generate assembly output. For example, this definition specifies a 4468macro 'sum' that puts a sequence of numbers into memory: 4469 4470 .macro sum from=0, to=5 4471 .long \from 4472 .if \to-\from 4473 sum "(\from+1)",\to 4474 .endif 4475 .endm 4476 4477With that definition, 'SUM 0,5' is equivalent to this assembly input: 4478 4479 .long 0 4480 .long 1 4481 .long 2 4482 .long 3 4483 .long 4 4484 .long 5 4485 4486'.macro MACNAME' 4487'.macro MACNAME MACARGS ...' 4488 Begin the definition of a macro called MACNAME. If your macro 4489 definition requires arguments, specify their names after the macro 4490 name, separated by commas or spaces. You can qualify the macro 4491 argument to indicate whether all invocations must specify a 4492 non-blank value (through ':'req''), or whether it takes all of the 4493 remaining arguments (through ':'vararg''). You can supply a 4494 default value for any macro argument by following the name with 4495 '=DEFLT'. You cannot define two macros with the same MACNAME 4496 unless it has been subject to the '.purgem' directive (*note 4497 Purgem::) between the two definitions. For example, these are all 4498 valid '.macro' statements: 4499 4500 '.macro comm' 4501 Begin the definition of a macro called 'comm', which takes no 4502 arguments. 4503 4504 '.macro plus1 p, p1' 4505 '.macro plus1 p p1' 4506 Either statement begins the definition of a macro called 4507 'plus1', which takes two arguments; within the macro 4508 definition, write '\p' or '\p1' to evaluate the arguments. 4509 4510 '.macro reserve_str p1=0 p2' 4511 Begin the definition of a macro called 'reserve_str', with two 4512 arguments. The first argument has a default value, but not 4513 the second. After the definition is complete, you can call 4514 the macro either as 'reserve_str A,B' (with '\p1' evaluating 4515 to A and '\p2' evaluating to B), or as 'reserve_str ,B' (with 4516 '\p1' evaluating as the default, in this case '0', and '\p2' 4517 evaluating to B). 4518 4519 '.macro m p1:req, p2=0, p3:vararg' 4520 Begin the definition of a macro called 'm', with at least 4521 three arguments. The first argument must always have a value 4522 specified, but not the second, which instead has a default 4523 value. The third formal will get assigned all remaining 4524 arguments specified at invocation time. 4525 4526 When you call a macro, you can specify the argument values 4527 either by position, or by keyword. For example, 'sum 9,17' is 4528 equivalent to 'sum to=17, from=9'. 4529 4530 Note that since each of the MACARGS can be an identifier exactly as 4531 any other one permitted by the target architecture, there may be 4532 occasional problems if the target hand-crafts special meanings to 4533 certain characters when they occur in a special position. For 4534 example, if the colon (':') is generally permitted to be part of a 4535 symbol name, but the architecture specific code special-cases it 4536 when occurring as the final character of a symbol (to denote a 4537 label), then the macro parameter replacement code will have no way 4538 of knowing that and consider the whole construct (including the 4539 colon) an identifier, and check only this identifier for being the 4540 subject to parameter substitution. So for example this macro 4541 definition: 4542 4543 .macro label l 4544 \l: 4545 .endm 4546 4547 might not work as expected. Invoking 'label foo' might not create 4548 a label called 'foo' but instead just insert the text '\l:' into 4549 the assembler source, probably generating an error about an 4550 unrecognised identifier. 4551 4552 Similarly problems might occur with the period character ('.') 4553 which is often allowed inside opcode names (and hence identifier 4554 names). So for example constructing a macro to build an opcode 4555 from a base name and a length specifier like this: 4556 4557 .macro opcode base length 4558 \base.\length 4559 .endm 4560 4561 and invoking it as 'opcode store l' will not create a 'store.l' 4562 instruction but instead generate some kind of error as the 4563 assembler tries to interpret the text '\base.\length'. 4564 4565 There are several possible ways around this problem: 4566 4567 'Insert white space' 4568 If it is possible to use white space characters then this is 4569 the simplest solution. eg: 4570 4571 .macro label l 4572 \l : 4573 .endm 4574 4575 'Use '\()'' 4576 The string '\()' can be used to separate the end of a macro 4577 argument from the following text. eg: 4578 4579 .macro opcode base length 4580 \base\().\length 4581 .endm 4582 4583 'Use the alternate macro syntax mode' 4584 In the alternative macro syntax mode the ampersand character 4585 ('&') can be used as a separator. eg: 4586 4587 .altmacro 4588 .macro label l 4589 l&: 4590 .endm 4591 4592 Note: this problem of correctly identifying string parameters to 4593 pseudo ops also applies to the identifiers used in '.irp' (*note 4594 Irp::) and '.irpc' (*note Irpc::) as well. 4595 4596'.endm' 4597 Mark the end of a macro definition. 4598 4599'.exitm' 4600 Exit early from the current macro definition. 4601 4602'\@' 4603 'as' maintains a counter of how many macros it has executed in this 4604 pseudo-variable; you can copy that number to your output with '\@', 4605 but _only within a macro definition_. 4606 4607'LOCAL NAME [ , ... ]' 4608 _Warning: 'LOCAL' is only available if you select "alternate macro 4609 syntax" with '--alternate' or '.altmacro'._ *Note '.altmacro': 4610 Altmacro. 4611 4612 4613File: as.info, Node: MRI, Next: Noaltmacro, Prev: Macro, Up: Pseudo Ops 4614 46157.59 '.mri VAL' 4616=============== 4617 4618If VAL is non-zero, this tells 'as' to enter MRI mode. If VAL is zero, 4619this tells 'as' to exit MRI mode. This change affects code assembled 4620until the next '.mri' directive, or until the end of the file. *Note 4621MRI mode: M. 4622 4623 4624File: as.info, Node: Noaltmacro, Next: Nolist, Prev: MRI, Up: Pseudo Ops 4625 46267.60 '.noaltmacro' 4627================== 4628 4629Disable alternate macro mode. *Note Altmacro::. 4630 4631 4632File: as.info, Node: Nolist, Next: Octa, Prev: Noaltmacro, Up: Pseudo Ops 4633 46347.61 '.nolist' 4635============== 4636 4637Control (in conjunction with the '.list' directive) whether or not 4638assembly listings are generated. These two directives maintain an 4639internal counter (which is zero initially). '.list' increments the 4640counter, and '.nolist' decrements it. Assembly listings are generated 4641whenever the counter is greater than zero. 4642 4643 4644File: as.info, Node: Octa, Next: Offset, Prev: Nolist, Up: Pseudo Ops 4645 46467.62 '.octa BIGNUMS' 4647==================== 4648 4649This directive expects zero or more bignums, separated by commas. For 4650each bignum, it emits a 16-byte integer. 4651 4652 The term "octa" comes from contexts in which a "word" is two bytes; 4653hence _octa_-word for 16 bytes. 4654 4655 4656File: as.info, Node: Offset, Next: Org, Prev: Octa, Up: Pseudo Ops 4657 46587.63 '.offset LOC' 4659================== 4660 4661Set the location counter to LOC in the absolute section. LOC must be an 4662absolute expression. This directive may be useful for defining symbols 4663with absolute values. Do not confuse it with the '.org' directive. 4664 4665 4666File: as.info, Node: Org, Next: P2align, Prev: Offset, Up: Pseudo Ops 4667 46687.64 '.org NEW-LC , FILL' 4669========================= 4670 4671Advance the location counter of the current section to NEW-LC. NEW-LC 4672is either an absolute expression or an expression with the same section 4673as the current subsection. That is, you can't use '.org' to cross 4674sections: if NEW-LC has the wrong section, the '.org' directive is 4675ignored. To be compatible with former assemblers, if the section of 4676NEW-LC is absolute, 'as' issues a warning, then pretends the section of 4677NEW-LC is the same as the current subsection. 4678 4679 '.org' may only increase the location counter, or leave it unchanged; 4680you cannot use '.org' to move the location counter backwards. 4681 4682 Because 'as' tries to assemble programs in one pass, NEW-LC may not 4683be undefined. If you really detest this restriction we eagerly await a 4684chance to share your improved assembler. 4685 4686 Beware that the origin is relative to the start of the section, not 4687to the start of the subsection. This is compatible with other people's 4688assemblers. 4689 4690 When the location counter (of the current subsection) is advanced, 4691the intervening bytes are filled with FILL which should be an absolute 4692expression. If the comma and FILL are omitted, FILL defaults to zero. 4693 4694 4695File: as.info, Node: P2align, Next: PopSection, Prev: Org, Up: Pseudo Ops 4696 46977.65 '.p2align[wl] ABS-EXPR, ABS-EXPR, ABS-EXPR' 4698================================================ 4699 4700Pad the location counter (in the current subsection) to a particular 4701storage boundary. The first expression (which must be absolute) is the 4702number of low-order zero bits the location counter must have after 4703advancement. For example '.p2align 3' advances the location counter 4704until it a multiple of 8. If the location counter is already a multiple 4705of 8, no change is needed. 4706 4707 The second expression (also absolute) gives the fill value to be 4708stored in the padding bytes. It (and the comma) may be omitted. If it 4709is omitted, the padding bytes are normally zero. However, on some 4710systems, if the section is marked as containing code and the fill value 4711is omitted, the space is filled with no-op instructions. 4712 4713 The third expression is also absolute, and is also optional. If it 4714is present, it is the maximum number of bytes that should be skipped by 4715this alignment directive. If doing the alignment would require skipping 4716more bytes than the specified maximum, then the alignment is not done at 4717all. You can omit the fill value (the second argument) entirely by 4718simply using two commas after the required alignment; this can be useful 4719if you want the alignment to be filled with no-op instructions when 4720appropriate. 4721 4722 The '.p2alignw' and '.p2alignl' directives are variants of the 4723'.p2align' directive. The '.p2alignw' directive treats the fill pattern 4724as a two byte word value. The '.p2alignl' directives treats the fill 4725pattern as a four byte longword value. For example, '.p2alignw 47262,0x368d' will align to a multiple of 4. If it skips two bytes, they 4727will be filled in with the value 0x368d (the exact placement of the 4728bytes depends upon the endianness of the processor). If it skips 1 or 3 4729bytes, the fill value is undefined. 4730 4731 4732File: as.info, Node: PopSection, Next: Previous, Prev: P2align, Up: Pseudo Ops 4733 47347.66 '.popsection' 4735================== 4736 4737This is one of the ELF section stack manipulation directives. The 4738others are '.section' (*note Section::), '.subsection' (*note 4739SubSection::), '.pushsection' (*note PushSection::), and '.previous' 4740(*note Previous::). 4741 4742 This directive replaces the current section (and subsection) with the 4743top section (and subsection) on the section stack. This section is 4744popped off the stack. 4745 4746 4747File: as.info, Node: Previous, Next: Print, Prev: PopSection, Up: Pseudo Ops 4748 47497.67 '.previous' 4750================ 4751 4752This is one of the ELF section stack manipulation directives. The 4753others are '.section' (*note Section::), '.subsection' (*note 4754SubSection::), '.pushsection' (*note PushSection::), and '.popsection' 4755(*note PopSection::). 4756 4757 This directive swaps the current section (and subsection) with most 4758recently referenced section/subsection pair prior to this one. Multiple 4759'.previous' directives in a row will flip between two sections (and 4760their subsections). For example: 4761 4762 .section A 4763 .subsection 1 4764 .word 0x1234 4765 .subsection 2 4766 .word 0x5678 4767 .previous 4768 .word 0x9abc 4769 4770 Will place 0x1234 and 0x9abc into subsection 1 and 0x5678 into 4771subsection 2 of section A. Whilst: 4772 4773 .section A 4774 .subsection 1 4775 # Now in section A subsection 1 4776 .word 0x1234 4777 .section B 4778 .subsection 0 4779 # Now in section B subsection 0 4780 .word 0x5678 4781 .subsection 1 4782 # Now in section B subsection 1 4783 .word 0x9abc 4784 .previous 4785 # Now in section B subsection 0 4786 .word 0xdef0 4787 4788 Will place 0x1234 into section A, 0x5678 and 0xdef0 into subsection 0 4789of section B and 0x9abc into subsection 1 of section B. 4790 4791 In terms of the section stack, this directive swaps the current 4792section with the top section on the section stack. 4793 4794 4795File: as.info, Node: Print, Next: Protected, Prev: Previous, Up: Pseudo Ops 4796 47977.68 '.print STRING' 4798==================== 4799 4800'as' will print STRING on the standard output during assembly. You must 4801put STRING in double quotes. 4802 4803 4804File: as.info, Node: Protected, Next: Psize, Prev: Print, Up: Pseudo Ops 4805 48067.69 '.protected NAMES' 4807======================= 4808 4809This is one of the ELF visibility directives. The other two are 4810'.hidden' (*note Hidden::) and '.internal' (*note Internal::). 4811 4812 This directive overrides the named symbols default visibility (which 4813is set by their binding: local, global or weak). The directive sets the 4814visibility to 'protected' which means that any references to the symbols 4815from within the components that defines them must be resolved to the 4816definition in that component, even if a definition in another component 4817would normally preempt this. 4818 4819 4820File: as.info, Node: Psize, Next: Purgem, Prev: Protected, Up: Pseudo Ops 4821 48227.70 '.psize LINES , COLUMNS' 4823============================= 4824 4825Use this directive to declare the number of lines--and, optionally, the 4826number of columns--to use for each page, when generating listings. 4827 4828 If you do not use '.psize', listings use a default line-count of 60. 4829You may omit the comma and COLUMNS specification; the default width is 4830200 columns. 4831 4832 'as' generates formfeeds whenever the specified number of lines is 4833exceeded (or whenever you explicitly request one, using '.eject'). 4834 4835 If you specify LINES as '0', no formfeeds are generated save those 4836explicitly specified with '.eject'. 4837 4838 4839File: as.info, Node: Purgem, Next: PushSection, Prev: Psize, Up: Pseudo Ops 4840 48417.71 '.purgem NAME' 4842=================== 4843 4844Undefine the macro NAME, so that later uses of the string will not be 4845expanded. *Note Macro::. 4846 4847 4848File: as.info, Node: PushSection, Next: Quad, Prev: Purgem, Up: Pseudo Ops 4849 48507.72 '.pushsection NAME [, SUBSECTION] [, "FLAGS"[, @TYPE[,ARGUMENTS]]]' 4851======================================================================== 4852 4853This is one of the ELF section stack manipulation directives. The 4854others are '.section' (*note Section::), '.subsection' (*note 4855SubSection::), '.popsection' (*note PopSection::), and '.previous' 4856(*note Previous::). 4857 4858 This directive pushes the current section (and subsection) onto the 4859top of the section stack, and then replaces the current section and 4860subsection with 'name' and 'subsection'. The optional 'flags', 'type' 4861and 'arguments' are treated the same as in the '.section' (*note 4862Section::) directive. 4863 4864 4865File: as.info, Node: Quad, Next: Reloc, Prev: PushSection, Up: Pseudo Ops 4866 48677.73 '.quad BIGNUMS' 4868==================== 4869 4870'.quad' expects zero or more bignums, separated by commas. For each 4871bignum, it emits an 8-byte integer. If the bignum won't fit in 8 bytes, 4872it prints a warning message; and just takes the lowest order 8 bytes of 4873the bignum. 4874 4875 The term "quad" comes from contexts in which a "word" is two bytes; 4876hence _quad_-word for 8 bytes. 4877 4878 4879File: as.info, Node: Reloc, Next: Rept, Prev: Quad, Up: Pseudo Ops 4880 48817.74 '.reloc OFFSET, RELOC_NAME[, EXPRESSION]' 4882============================================== 4883 4884Generate a relocation at OFFSET of type RELOC_NAME with value 4885EXPRESSION. If OFFSET is a number, the relocation is generated in the 4886current section. If OFFSET is an expression that resolves to a symbol 4887plus offset, the relocation is generated in the given symbol's section. 4888EXPRESSION, if present, must resolve to a symbol plus addend or to an 4889absolute value, but note that not all targets support an addend. e.g. 4890ELF REL targets such as i386 store an addend in the section contents 4891rather than in the relocation. This low level interface does not 4892support addends stored in the section. 4893 4894 4895File: as.info, Node: Rept, Next: Sbttl, Prev: Reloc, Up: Pseudo Ops 4896 48977.75 '.rept COUNT' 4898================== 4899 4900Repeat the sequence of lines between the '.rept' directive and the next 4901'.endr' directive COUNT times. 4902 4903 For example, assembling 4904 4905 .rept 3 4906 .long 0 4907 .endr 4908 4909 is equivalent to assembling 4910 4911 .long 0 4912 .long 0 4913 .long 0 4914 4915 4916File: as.info, Node: Sbttl, Next: Scl, Prev: Rept, Up: Pseudo Ops 4917 49187.76 '.sbttl "SUBHEADING"' 4919========================== 4920 4921Use SUBHEADING as the title (third line, immediately after the title 4922line) when generating assembly listings. 4923 4924 This directive affects subsequent pages, as well as the current page 4925if it appears within ten lines of the top of a page. 4926 4927 4928File: as.info, Node: Scl, Next: Section, Prev: Sbttl, Up: Pseudo Ops 4929 49307.77 '.scl CLASS' 4931================= 4932 4933Set the storage-class value for a symbol. This directive may only be 4934used inside a '.def'/'.endef' pair. Storage class may flag whether a 4935symbol is static or external, or it may record further symbolic 4936debugging information. 4937 4938 4939File: as.info, Node: Section, Next: Set, Prev: Scl, Up: Pseudo Ops 4940 49417.78 '.section NAME' 4942==================== 4943 4944Use the '.section' directive to assemble the following code into a 4945section named NAME. 4946 4947 This directive is only supported for targets that actually support 4948arbitrarily named sections; on 'a.out' targets, for example, it is not 4949accepted, even with a standard 'a.out' section name. 4950 4951COFF Version 4952------------ 4953 4954For COFF targets, the '.section' directive is used in one of the 4955following ways: 4956 4957 .section NAME[, "FLAGS"] 4958 .section NAME[, SUBSECTION] 4959 4960 If the optional argument is quoted, it is taken as flags to use for 4961the section. Each flag is a single character. The following flags are 4962recognized: 4963 4964'b' 4965 bss section (uninitialized data) 4966'n' 4967 section is not loaded 4968'w' 4969 writable section 4970'd' 4971 data section 4972'e' 4973 exclude section from linking 4974'r' 4975 read-only section 4976'x' 4977 executable section 4978's' 4979 shared section (meaningful for PE targets) 4980'a' 4981 ignored. (For compatibility with the ELF version) 4982'y' 4983 section is not readable (meaningful for PE targets) 4984'0-9' 4985 single-digit power-of-two section alignment (GNU extension) 4986 4987 If no flags are specified, the default flags depend upon the section 4988name. If the section name is not recognized, the default will be for 4989the section to be loaded and writable. Note the 'n' and 'w' flags 4990remove attributes from the section, rather than adding them, so if they 4991are used on their own it will be as if no flags had been specified at 4992all. 4993 4994 If the optional argument to the '.section' directive is not quoted, 4995it is taken as a subsection number (*note Sub-Sections::). 4996 4997ELF Version 4998----------- 4999 5000This is one of the ELF section stack manipulation directives. The 5001others are '.subsection' (*note SubSection::), '.pushsection' (*note 5002PushSection::), '.popsection' (*note PopSection::), and '.previous' 5003(*note Previous::). 5004 5005 For ELF targets, the '.section' directive is used like this: 5006 5007 .section NAME [, "FLAGS"[, @TYPE[,FLAG_SPECIFIC_ARGUMENTS]]] 5008 5009 If the '--sectname-subst' command-line option is provided, the NAME 5010argument may contain a substitution sequence. Only '%S' is supported at 5011the moment, and substitutes the current section name. For example: 5012 5013 .macro exception_code 5014 .section %S.exception 5015 [exception code here] 5016 .previous 5017 .endm 5018 5019 .text 5020 [code] 5021 exception_code 5022 [...] 5023 5024 .section .init 5025 [init code] 5026 exception_code 5027 [...] 5028 5029 The two 'exception_code' invocations above would create the 5030'.text.exception' and '.init.exception' sections respectively. This is 5031useful e.g. to discriminate between anciliary sections that are tied to 5032setup code to be discarded after use from anciliary sections that need 5033to stay resident without having to define multiple 'exception_code' 5034macros just for that purpose. 5035 5036 The optional FLAGS argument is a quoted string which may contain any 5037combination of the following characters: 5038 5039'a' 5040 section is allocatable 5041'e' 5042 section is excluded from executable and shared library. 5043'w' 5044 section is writable 5045'x' 5046 section is executable 5047'M' 5048 section is mergeable 5049'S' 5050 section contains zero terminated strings 5051'G' 5052 section is a member of a section group 5053'T' 5054 section is used for thread-local-storage 5055'?' 5056 section is a member of the previously-current section's group, if 5057 any 5058'<number>' 5059 a numeric value indicating the bits to be set in the ELF section 5060 header's flags field. Note - if one or more of the alphabetic 5061 characters described above is also included in the flags field, 5062 their bit values will be ORed into the resulting value. 5063'<target specific>' 5064 some targets extend this list with their own flag characters 5065 5066 Note - once a section's flags have been set they cannot be changed. 5067There are a few exceptions to this rule however. Processor and 5068application specific flags can be added to an already defined section. 5069The '.interp', '.strtab' and '.symtab' sections can have the allocate 5070flag ('a') set after they are initially defined, and the 5071'.note-GNU-stack' section may have the executable ('x') flag added. 5072 5073 The optional TYPE argument may contain one of the following 5074constants: 5075 5076'@progbits' 5077 section contains data 5078'@nobits' 5079 section does not contain data (i.e., section only occupies space) 5080'@note' 5081 section contains data which is used by things other than the 5082 program 5083'@init_array' 5084 section contains an array of pointers to init functions 5085'@fini_array' 5086 section contains an array of pointers to finish functions 5087'@preinit_array' 5088 section contains an array of pointers to pre-init functions 5089'@<number>' 5090 a numeric value to be set as the ELF section header's type field. 5091'@<target specific>' 5092 some targets extend this list with their own types 5093 5094 Many targets only support the first three section types. The type 5095may be enclosed in double quotes if necessary. 5096 5097 Note on targets where the '@' character is the start of a comment (eg 5098ARM) then another character is used instead. For example the ARM port 5099uses the '%' character. 5100 5101 Note - some sections, eg '.text' and '.data' are considered to be 5102special and have fixed types. Any attempt to declare them with a 5103different type will generate an error from the assembler. 5104 5105 If FLAGS contains the 'M' symbol then the TYPE argument must be 5106specified as well as an extra argument--ENTSIZE--like this: 5107 5108 .section NAME , "FLAGS"M, @TYPE, ENTSIZE 5109 5110 Sections with the 'M' flag but not 'S' flag must contain fixed size 5111constants, each ENTSIZE octets long. Sections with both 'M' and 'S' 5112must contain zero terminated strings where each character is ENTSIZE 5113bytes long. The linker may remove duplicates within sections with the 5114same name, same entity size and same flags. ENTSIZE must be an absolute 5115expression. For sections with both 'M' and 'S', a string which is a 5116suffix of a larger string is considered a duplicate. Thus '"def"' will 5117be merged with '"abcdef"'; A reference to the first '"def"' will be 5118changed to a reference to '"abcdef"+3'. 5119 5120 If FLAGS contains the 'G' symbol then the TYPE argument must be 5121present along with an additional field like this: 5122 5123 .section NAME , "FLAGS"G, @TYPE, GROUPNAME[, LINKAGE] 5124 5125 The GROUPNAME field specifies the name of the section group to which 5126this particular section belongs. The optional linkage field can 5127contain: 5128 5129'comdat' 5130 indicates that only one copy of this section should be retained 5131'.gnu.linkonce' 5132 an alias for comdat 5133 5134 Note: if both the M and G flags are present then the fields for the 5135Merge flag should come first, like this: 5136 5137 .section NAME , "FLAGS"MG, @TYPE, ENTSIZE, GROUPNAME[, LINKAGE] 5138 5139 If FLAGS contains the '?' symbol then it may not also contain the 'G' 5140symbol and the GROUPNAME or LINKAGE fields should not be present. 5141Instead, '?' says to consider the section that's current before this 5142directive. If that section used 'G', then the new section will use 'G' 5143with those same GROUPNAME and LINKAGE fields implicitly. If not, then 5144the '?' symbol has no effect. 5145 5146 If no flags are specified, the default flags depend upon the section 5147name. If the section name is not recognized, the default will be for 5148the section to have none of the above flags: it will not be allocated in 5149memory, nor writable, nor executable. The section will contain data. 5150 5151 For ELF targets, the assembler supports another type of '.section' 5152directive for compatibility with the Solaris assembler: 5153 5154 .section "NAME"[, FLAGS...] 5155 5156 Note that the section name is quoted. There may be a sequence of 5157comma separated flags: 5158 5159'#alloc' 5160 section is allocatable 5161'#write' 5162 section is writable 5163'#execinstr' 5164 section is executable 5165'#exclude' 5166 section is excluded from executable and shared library. 5167'#tls' 5168 section is used for thread local storage 5169 5170 This directive replaces the current section and subsection. See the 5171contents of the gas testsuite directory 'gas/testsuite/gas/elf' for some 5172examples of how this directive and the other section stack directives 5173work. 5174 5175 5176File: as.info, Node: Set, Next: Short, Prev: Section, Up: Pseudo Ops 5177 51787.79 '.set SYMBOL, EXPRESSION' 5179============================== 5180 5181Set the value of SYMBOL to EXPRESSION. This changes SYMBOL's value and 5182type to conform to EXPRESSION. If SYMBOL was flagged as external, it 5183remains flagged (*note Symbol Attributes::). 5184 5185 You may '.set' a symbol many times in the same assembly provided that 5186the values given to the symbol are constants. Values that are based on 5187expressions involving other symbols are allowed, but some targets may 5188restrict this to only being done once per assembly. This is because 5189those targets do not set the addresses of symbols at assembly time, but 5190rather delay the assignment until a final link is performed. This 5191allows the linker a chance to change the code in the files, changing the 5192location of, and the relative distance between, various different 5193symbols. 5194 5195 If you '.set' a global symbol, the value stored in the object file is 5196the last value stored into it. 5197 5198 On Z80 'set' is a real instruction, use 'SYMBOL defl EXPRESSION' 5199instead. 5200 5201 5202File: as.info, Node: Short, Next: Single, Prev: Set, Up: Pseudo Ops 5203 52047.80 '.short EXPRESSIONS' 5205========================= 5206 5207'.short' is normally the same as '.word'. *Note '.word': Word. 5208 5209 In some configurations, however, '.short' and '.word' generate 5210numbers of different lengths. *Note Machine Dependencies::. 5211 5212 5213File: as.info, Node: Single, Next: Size, Prev: Short, Up: Pseudo Ops 5214 52157.81 '.single FLONUMS' 5216====================== 5217 5218This directive assembles zero or more flonums, separated by commas. It 5219has the same effect as '.float'. The exact kind of floating point 5220numbers emitted depends on how 'as' is configured. *Note Machine 5221Dependencies::. 5222 5223 5224File: as.info, Node: Size, Next: Skip, Prev: Single, Up: Pseudo Ops 5225 52267.82 '.size' 5227============ 5228 5229This directive is used to set the size associated with a symbol. 5230 5231COFF Version 5232------------ 5233 5234For COFF targets, the '.size' directive is only permitted inside 5235'.def'/'.endef' pairs. It is used like this: 5236 5237 .size EXPRESSION 5238 5239ELF Version 5240----------- 5241 5242For ELF targets, the '.size' directive is used like this: 5243 5244 .size NAME , EXPRESSION 5245 5246 This directive sets the size associated with a symbol NAME. The size 5247in bytes is computed from EXPRESSION which can make use of label 5248arithmetic. This directive is typically used to set the size of 5249function symbols. 5250 5251 5252File: as.info, Node: Skip, Next: Sleb128, Prev: Size, Up: Pseudo Ops 5253 52547.83 '.skip SIZE , FILL' 5255======================== 5256 5257This directive emits SIZE bytes, each of value FILL. Both SIZE and FILL 5258are absolute expressions. If the comma and FILL are omitted, FILL is 5259assumed to be zero. This is the same as '.space'. 5260 5261 5262File: as.info, Node: Sleb128, Next: Space, Prev: Skip, Up: Pseudo Ops 5263 52647.84 '.sleb128 EXPRESSIONS' 5265=========================== 5266 5267SLEB128 stands for "signed little endian base 128." This is a compact, 5268variable length representation of numbers used by the DWARF symbolic 5269debugging format. *Note '.uleb128': Uleb128. 5270 5271 5272File: as.info, Node: Space, Next: Stab, Prev: Sleb128, Up: Pseudo Ops 5273 52747.85 '.space SIZE , FILL' 5275========================= 5276 5277This directive emits SIZE bytes, each of value FILL. Both SIZE and FILL 5278are absolute expressions. If the comma and FILL are omitted, FILL is 5279assumed to be zero. This is the same as '.skip'. 5280 5281 _Warning:_ '.space' has a completely different meaning for HPPA 5282 targets; use '.block' as a substitute. See 'HP9000 Series 800 5283 Assembly Language Reference Manual' (HP 92432-90001) for the 5284 meaning of the '.space' directive. *Note HPPA Assembler 5285 Directives: HPPA Directives, for a summary. 5286 5287 5288File: as.info, Node: Stab, Next: String, Prev: Space, Up: Pseudo Ops 5289 52907.86 '.stabd, .stabn, .stabs' 5291============================= 5292 5293There are three directives that begin '.stab'. All emit symbols (*note 5294Symbols::), for use by symbolic debuggers. The symbols are not entered 5295in the 'as' hash table: they cannot be referenced elsewhere in the 5296source file. Up to five fields are required: 5297 5298STRING 5299 This is the symbol's name. It may contain any character except 5300 '\000', so is more general than ordinary symbol names. Some 5301 debuggers used to code arbitrarily complex structures into symbol 5302 names using this field. 5303 5304TYPE 5305 An absolute expression. The symbol's type is set to the low 8 bits 5306 of this expression. Any bit pattern is permitted, but 'ld' and 5307 debuggers choke on silly bit patterns. 5308 5309OTHER 5310 An absolute expression. The symbol's "other" attribute is set to 5311 the low 8 bits of this expression. 5312 5313DESC 5314 An absolute expression. The symbol's descriptor is set to the low 5315 16 bits of this expression. 5316 5317VALUE 5318 An absolute expression which becomes the symbol's value. 5319 5320 If a warning is detected while reading a '.stabd', '.stabn', or 5321'.stabs' statement, the symbol has probably already been created; you 5322get a half-formed symbol in your object file. This is compatible with 5323earlier assemblers! 5324 5325'.stabd TYPE , OTHER , DESC' 5326 5327 The "name" of the symbol generated is not even an empty string. It 5328 is a null pointer, for compatibility. Older assemblers used a null 5329 pointer so they didn't waste space in object files with empty 5330 strings. 5331 5332 The symbol's value is set to the location counter, relocatably. 5333 When your program is linked, the value of this symbol is the 5334 address of the location counter when the '.stabd' was assembled. 5335 5336'.stabn TYPE , OTHER , DESC , VALUE' 5337 The name of the symbol is set to the empty string '""'. 5338 5339'.stabs STRING , TYPE , OTHER , DESC , VALUE' 5340 All five fields are specified. 5341 5342 5343File: as.info, Node: String, Next: Struct, Prev: Stab, Up: Pseudo Ops 5344 53457.87 '.string' "STR", '.string8' "STR", '.string16' 5346=================================================== 5347 5348"STR", '.string32' "STR", '.string64' "STR" 5349 5350 Copy the characters in STR to the object file. You may specify more 5351than one string to copy, separated by commas. Unless otherwise 5352specified for a particular machine, the assembler marks the end of each 5353string with a 0 byte. You can use any of the escape sequences described 5354in *note Strings: Strings. 5355 5356 The variants 'string16', 'string32' and 'string64' differ from the 5357'string' pseudo opcode in that each 8-bit character from STR is copied 5358and expanded to 16, 32 or 64 bits respectively. The expanded characters 5359are stored in target endianness byte order. 5360 5361 Example: 5362 .string32 "BYE" 5363 expands to: 5364 .string "B\0\0\0Y\0\0\0E\0\0\0" /* On little endian targets. */ 5365 .string "\0\0\0B\0\0\0Y\0\0\0E" /* On big endian targets. */ 5366 5367 5368File: as.info, Node: Struct, Next: SubSection, Prev: String, Up: Pseudo Ops 5369 53707.88 '.struct EXPRESSION' 5371========================= 5372 5373Switch to the absolute section, and set the section offset to 5374EXPRESSION, which must be an absolute expression. You might use this as 5375follows: 5376 .struct 0 5377 field1: 5378 .struct field1 + 4 5379 field2: 5380 .struct field2 + 4 5381 field3: 5382 This would define the symbol 'field1' to have the value 0, the symbol 5383'field2' to have the value 4, and the symbol 'field3' to have the value 53848. Assembly would be left in the absolute section, and you would need 5385to use a '.section' directive of some sort to change to some other 5386section before further assembly. 5387 5388 5389File: as.info, Node: SubSection, Next: Symver, Prev: Struct, Up: Pseudo Ops 5390 53917.89 '.subsection NAME' 5392======================= 5393 5394This is one of the ELF section stack manipulation directives. The 5395others are '.section' (*note Section::), '.pushsection' (*note 5396PushSection::), '.popsection' (*note PopSection::), and '.previous' 5397(*note Previous::). 5398 5399 This directive replaces the current subsection with 'name'. The 5400current section is not changed. The replaced subsection is put onto the 5401section stack in place of the then current top of stack subsection. 5402 5403 5404File: as.info, Node: Symver, Next: Tag, Prev: SubSection, Up: Pseudo Ops 5405 54067.90 '.symver' 5407============== 5408 5409Use the '.symver' directive to bind symbols to specific version nodes 5410within a source file. This is only supported on ELF platforms, and is 5411typically used when assembling files to be linked into a shared library. 5412There are cases where it may make sense to use this in objects to be 5413bound into an application itself so as to override a versioned symbol 5414from a shared library. 5415 5416 For ELF targets, the '.symver' directive can be used like this: 5417 .symver NAME, NAME2@NODENAME 5418 If the symbol NAME is defined within the file being assembled, the 5419'.symver' directive effectively creates a symbol alias with the name 5420NAME2@NODENAME, and in fact the main reason that we just don't try and 5421create a regular alias is that the @ character isn't permitted in symbol 5422names. The NAME2 part of the name is the actual name of the symbol by 5423which it will be externally referenced. The name NAME itself is merely 5424a name of convenience that is used so that it is possible to have 5425definitions for multiple versions of a function within a single source 5426file, and so that the compiler can unambiguously know which version of a 5427function is being mentioned. The NODENAME portion of the alias should 5428be the name of a node specified in the version script supplied to the 5429linker when building a shared library. If you are attempting to 5430override a versioned symbol from a shared library, then NODENAME should 5431correspond to the nodename of the symbol you are trying to override. 5432 5433 If the symbol NAME is not defined within the file being assembled, 5434all references to NAME will be changed to NAME2@NODENAME. If no 5435reference to NAME is made, NAME2@NODENAME will be removed from the 5436symbol table. 5437 5438 Another usage of the '.symver' directive is: 5439 .symver NAME, NAME2@@NODENAME 5440 In this case, the symbol NAME must exist and be defined within the 5441file being assembled. It is similar to NAME2@NODENAME. The difference 5442is NAME2@@NODENAME will also be used to resolve references to NAME2 by 5443the linker. 5444 5445 The third usage of the '.symver' directive is: 5446 .symver NAME, NAME2@@@NODENAME 5447 When NAME is not defined within the file being assembled, it is 5448treated as NAME2@NODENAME. When NAME is defined within the file being 5449assembled, the symbol name, NAME, will be changed to NAME2@@NODENAME. 5450 5451 5452File: as.info, Node: Tag, Next: Text, Prev: Symver, Up: Pseudo Ops 5453 54547.91 '.tag STRUCTNAME' 5455====================== 5456 5457This directive is generated by compilers to include auxiliary debugging 5458information in the symbol table. It is only permitted inside 5459'.def'/'.endef' pairs. Tags are used to link structure definitions in 5460the symbol table with instances of those structures. 5461 5462 5463File: as.info, Node: Text, Next: Title, Prev: Tag, Up: Pseudo Ops 5464 54657.92 '.text SUBSECTION' 5466======================= 5467 5468Tells 'as' to assemble the following statements onto the end of the text 5469subsection numbered SUBSECTION, which is an absolute expression. If 5470SUBSECTION is omitted, subsection number zero is used. 5471 5472 5473File: as.info, Node: Title, Next: Type, Prev: Text, Up: Pseudo Ops 5474 54757.93 '.title "HEADING"' 5476======================= 5477 5478Use HEADING as the title (second line, immediately after the source file 5479name and pagenumber) when generating assembly listings. 5480 5481 This directive affects subsequent pages, as well as the current page 5482if it appears within ten lines of the top of a page. 5483 5484 5485File: as.info, Node: Type, Next: Uleb128, Prev: Title, Up: Pseudo Ops 5486 54877.94 '.type' 5488============ 5489 5490This directive is used to set the type of a symbol. 5491 5492COFF Version 5493------------ 5494 5495For COFF targets, this directive is permitted only within 5496'.def'/'.endef' pairs. It is used like this: 5497 5498 .type INT 5499 5500 This records the integer INT as the type attribute of a symbol table 5501entry. 5502 5503ELF Version 5504----------- 5505 5506For ELF targets, the '.type' directive is used like this: 5507 5508 .type NAME , TYPE DESCRIPTION 5509 5510 This sets the type of symbol NAME to be either a function symbol or 5511an object symbol. There are five different syntaxes supported for the 5512TYPE DESCRIPTION field, in order to provide compatibility with various 5513other assemblers. 5514 5515 Because some of the characters used in these syntaxes (such as '@' 5516and '#') are comment characters for some architectures, some of the 5517syntaxes below do not work on all architectures. The first variant will 5518be accepted by the GNU assembler on all architectures so that variant 5519should be used for maximum portability, if you do not need to assemble 5520your code with other assemblers. 5521 5522 The syntaxes supported are: 5523 5524 .type <name> STT_<TYPE_IN_UPPER_CASE> 5525 .type <name>,#<type> 5526 .type <name>,@<type> 5527 .type <name>,%<type> 5528 .type <name>,"<type>" 5529 5530 The types supported are: 5531 5532'STT_FUNC' 5533'function' 5534 Mark the symbol as being a function name. 5535 5536'STT_GNU_IFUNC' 5537'gnu_indirect_function' 5538 Mark the symbol as an indirect function when evaluated during reloc 5539 processing. (This is only supported on assemblers targeting GNU 5540 systems). 5541 5542'STT_OBJECT' 5543'object' 5544 Mark the symbol as being a data object. 5545 5546'STT_TLS' 5547'tls_object' 5548 Mark the symbol as being a thead-local data object. 5549 5550'STT_COMMON' 5551'common' 5552 Mark the symbol as being a common data object. 5553 5554'STT_NOTYPE' 5555'notype' 5556 Does not mark the symbol in any way. It is supported just for 5557 completeness. 5558 5559'gnu_unique_object' 5560 Marks the symbol as being a globally unique data object. The 5561 dynamic linker will make sure that in the entire process there is 5562 just one symbol with this name and type in use. (This is only 5563 supported on assemblers targeting GNU systems). 5564 5565 Note: Some targets support extra types in addition to those listed 5566above. 5567 5568 5569File: as.info, Node: Uleb128, Next: Val, Prev: Type, Up: Pseudo Ops 5570 55717.95 '.uleb128 EXPRESSIONS' 5572=========================== 5573 5574ULEB128 stands for "unsigned little endian base 128." This is a 5575compact, variable length representation of numbers used by the DWARF 5576symbolic debugging format. *Note '.sleb128': Sleb128. 5577 5578 5579File: as.info, Node: Val, Next: Version, Prev: Uleb128, Up: Pseudo Ops 5580 55817.96 '.val ADDR' 5582================ 5583 5584This directive, permitted only within '.def'/'.endef' pairs, records the 5585address ADDR as the value attribute of a symbol table entry. 5586 5587 5588File: as.info, Node: Version, Next: VTableEntry, Prev: Val, Up: Pseudo Ops 5589 55907.97 '.version "STRING"' 5591======================== 5592 5593This directive creates a '.note' section and places into it an ELF 5594formatted note of type NT_VERSION. The note's name is set to 'string'. 5595 5596 5597File: as.info, Node: VTableEntry, Next: VTableInherit, Prev: Version, Up: Pseudo Ops 5598 55997.98 '.vtable_entry TABLE, OFFSET' 5600================================== 5601 5602This directive finds or creates a symbol 'table' and creates a 5603'VTABLE_ENTRY' relocation for it with an addend of 'offset'. 5604 5605 5606File: as.info, Node: VTableInherit, Next: Warning, Prev: VTableEntry, Up: Pseudo Ops 5607 56087.99 '.vtable_inherit CHILD, PARENT' 5609==================================== 5610 5611This directive finds the symbol 'child' and finds or creates the symbol 5612'parent' and then creates a 'VTABLE_INHERIT' relocation for the parent 5613whose addend is the value of the child symbol. As a special case the 5614parent name of '0' is treated as referring to the '*ABS*' section. 5615 5616 5617File: as.info, Node: Warning, Next: Weak, Prev: VTableInherit, Up: Pseudo Ops 5618 56197.100 '.warning "STRING"' 5620========================= 5621 5622Similar to the directive '.error' (*note '.error "STRING"': Error.), but 5623just emits a warning. 5624 5625 5626File: as.info, Node: Weak, Next: Weakref, Prev: Warning, Up: Pseudo Ops 5627 56287.101 '.weak NAMES' 5629=================== 5630 5631This directive sets the weak attribute on the comma separated list of 5632symbol 'names'. If the symbols do not already exist, they will be 5633created. 5634 5635 On COFF targets other than PE, weak symbols are a GNU extension. 5636This directive sets the weak attribute on the comma separated list of 5637symbol 'names'. If the symbols do not already exist, they will be 5638created. 5639 5640 On the PE target, weak symbols are supported natively as weak 5641aliases. When a weak symbol is created that is not an alias, GAS 5642creates an alternate symbol to hold the default value. 5643 5644 5645File: as.info, Node: Weakref, Next: Word, Prev: Weak, Up: Pseudo Ops 5646 56477.102 '.weakref ALIAS, TARGET' 5648============================== 5649 5650This directive creates an alias to the target symbol that enables the 5651symbol to be referenced with weak-symbol semantics, but without actually 5652making it weak. If direct references or definitions of the symbol are 5653present, then the symbol will not be weak, but if all references to it 5654are through weak references, the symbol will be marked as weak in the 5655symbol table. 5656 5657 The effect is equivalent to moving all references to the alias to a 5658separate assembly source file, renaming the alias to the symbol in it, 5659declaring the symbol as weak there, and running a reloadable link to 5660merge the object files resulting from the assembly of the new source 5661file and the old source file that had the references to the alias 5662removed. 5663 5664 The alias itself never makes to the symbol table, and is entirely 5665handled within the assembler. 5666 5667 5668File: as.info, Node: Word, Next: Zero, Prev: Weakref, Up: Pseudo Ops 5669 56707.103 '.word EXPRESSIONS' 5671========================= 5672 5673This directive expects zero or more EXPRESSIONS, of any section, 5674separated by commas. 5675 5676 The size of the number emitted, and its byte order, depend on what 5677target computer the assembly is for. 5678 5679 _Warning: Special Treatment to support Compilers_ 5680 5681 Machines with a 32-bit address space, but that do less than 32-bit 5682addressing, require the following special treatment. If the machine of 5683interest to you does 32-bit addressing (or doesn't require it; *note 5684Machine Dependencies::), you can ignore this issue. 5685 5686 In order to assemble compiler output into something that works, 'as' 5687occasionally does strange things to '.word' directives. Directives of 5688the form '.word sym1-sym2' are often emitted by compilers as part of 5689jump tables. Therefore, when 'as' assembles a directive of the form 5690'.word sym1-sym2', and the difference between 'sym1' and 'sym2' does not 5691fit in 16 bits, 'as' creates a "secondary jump table", immediately 5692before the next label. This secondary jump table is preceded by a 5693short-jump to the first byte after the secondary table. This short-jump 5694prevents the flow of control from accidentally falling into the new 5695table. Inside the table is a long-jump to 'sym2'. The original '.word' 5696contains 'sym1' minus the address of the long-jump to 'sym2'. 5697 5698 If there were several occurrences of '.word sym1-sym2' before the 5699secondary jump table, all of them are adjusted. If there was a '.word 5700sym3-sym4', that also did not fit in sixteen bits, a long-jump to 'sym4' 5701is included in the secondary jump table, and the '.word' directives are 5702adjusted to contain 'sym3' minus the address of the long-jump to 'sym4'; 5703and so on, for as many entries in the original jump table as necessary. 5704 5705 5706File: as.info, Node: Zero, Next: Deprecated, Prev: Word, Up: Pseudo Ops 5707 57087.104 '.zero SIZE' 5709================== 5710 5711This directive emits SIZE 0-valued bytes. SIZE must be an absolute 5712expression. This directive is actually an alias for the '.skip' 5713directive so in can take an optional second argument of the value to 5714store in the bytes instead of zero. Using '.zero' in this way would be 5715confusing however. 5716 5717 5718File: as.info, Node: Deprecated, Prev: Zero, Up: Pseudo Ops 5719 57207.105 Deprecated Directives 5721=========================== 5722 5723One day these directives won't work. They are included for 5724compatibility with older assemblers. 5725.abort 5726.line 5727 5728 5729File: as.info, Node: Object Attributes, Next: Machine Dependencies, Prev: Pseudo Ops, Up: Top 5730 57318 Object Attributes 5732******************* 5733 5734'as' assembles source files written for a specific architecture into 5735object files for that architecture. But not all object files are alike. 5736Many architectures support incompatible variations. For instance, 5737floating point arguments might be passed in floating point registers if 5738the object file requires hardware floating point support--or floating 5739point arguments might be passed in integer registers if the object file 5740supports processors with no hardware floating point unit. Or, if two 5741objects are built for different generations of the same architecture, 5742the combination may require the newer generation at run-time. 5743 5744 This information is useful during and after linking. At link time, 5745'ld' can warn about incompatible object files. After link time, tools 5746like 'gdb' can use it to process the linked file correctly. 5747 5748 Compatibility information is recorded as a series of object 5749attributes. Each attribute has a "vendor", "tag", and "value". The 5750vendor is a string, and indicates who sets the meaning of the tag. The 5751tag is an integer, and indicates what property the attribute describes. 5752The value may be a string or an integer, and indicates how the property 5753affects this object. Missing attributes are the same as attributes with 5754a zero value or empty string value. 5755 5756 Object attributes were developed as part of the ABI for the ARM 5757Architecture. The file format is documented in 'ELF for the ARM 5758Architecture'. 5759 5760* Menu: 5761 5762* GNU Object Attributes:: GNU Object Attributes 5763* Defining New Object Attributes:: Defining New Object Attributes 5764 5765 5766File: as.info, Node: GNU Object Attributes, Next: Defining New Object Attributes, Up: Object Attributes 5767 57688.1 GNU Object Attributes 5769========================= 5770 5771The '.gnu_attribute' directive records an object attribute with vendor 5772'gnu'. 5773 5774 Except for 'Tag_compatibility', which has both an integer and a 5775string for its value, GNU attributes have a string value if the tag 5776number is odd and an integer value if the tag number is even. The 5777second bit ('TAG & 2' is set for architecture-independent attributes and 5778clear for architecture-dependent ones. 5779 57808.1.1 Common GNU attributes 5781--------------------------- 5782 5783These attributes are valid on all architectures. 5784 5785Tag_compatibility (32) 5786 The compatibility attribute takes an integer flag value and a 5787 vendor name. If the flag value is 0, the file is compatible with 5788 other toolchains. If it is 1, then the file is only compatible 5789 with the named toolchain. If it is greater than 1, the file can 5790 only be processed by other toolchains under some private 5791 arrangement indicated by the flag value and the vendor name. 5792 57938.1.2 MIPS Attributes 5794--------------------- 5795 5796Tag_GNU_MIPS_ABI_FP (4) 5797 The floating-point ABI used by this object file. The value will 5798 be: 5799 5800 * 0 for files not affected by the floating-point ABI. 5801 * 1 for files using the hardware floating-point ABI with a 5802 standard double-precision FPU. 5803 * 2 for files using the hardware floating-point ABI with a 5804 single-precision FPU. 5805 * 3 for files using the software floating-point ABI. 5806 * 4 for files using the deprecated hardware floating-point ABI 5807 which used 64-bit floating-point registers, 32-bit 5808 general-purpose registers and increased the number of 5809 callee-saved floating-point registers. 5810 * 5 for files using the hardware floating-point ABI with a 5811 double-precision FPU with either 32-bit or 64-bit 5812 floating-point registers and 32-bit general-purpose registers. 5813 * 6 for files using the hardware floating-point ABI with 64-bit 5814 floating-point registers and 32-bit general-purpose registers. 5815 * 7 for files using the hardware floating-point ABI with 64-bit 5816 floating-point registers, 32-bit general-purpose registers and 5817 a rule that forbids the direct use of odd-numbered 5818 single-precision floating-point registers. 5819 58208.1.3 PowerPC Attributes 5821------------------------ 5822 5823Tag_GNU_Power_ABI_FP (4) 5824 The floating-point ABI used by this object file. The value will 5825 be: 5826 5827 * 0 for files not affected by the floating-point ABI. 5828 * 1 for files using double-precision hardware floating-point 5829 ABI. 5830 * 2 for files using the software floating-point ABI. 5831 * 3 for files using single-precision hardware floating-point 5832 ABI. 5833 5834Tag_GNU_Power_ABI_Vector (8) 5835 The vector ABI used by this object file. The value will be: 5836 5837 * 0 for files not affected by the vector ABI. 5838 * 1 for files using general purpose registers to pass vectors. 5839 * 2 for files using AltiVec registers to pass vectors. 5840 * 3 for files using SPE registers to pass vectors. 5841 58428.1.4 IBM z Systems Attributes 5843------------------------------ 5844 5845Tag_GNU_S390_ABI_Vector (8) 5846 The vector ABI used by this object file. The value will be: 5847 5848 * 0 for files not affected by the vector ABI. 5849 * 1 for files using software vector ABI. 5850 * 2 for files using hardware vector ABI. 5851 5852 5853File: as.info, Node: Defining New Object Attributes, Prev: GNU Object Attributes, Up: Object Attributes 5854 58558.2 Defining New Object Attributes 5856================================== 5857 5858If you want to define a new GNU object attribute, here are the places 5859you will need to modify. New attributes should be discussed on the 5860'binutils' mailing list. 5861 5862 * This manual, which is the official register of attributes. 5863 * The header for your architecture 'include/elf', to define the tag. 5864 * The 'bfd' support file for your architecture, to merge the 5865 attribute and issue any appropriate link warnings. 5866 * Test cases in 'ld/testsuite' for merging and link warnings. 5867 * 'binutils/readelf.c' to display your attribute. 5868 * GCC, if you want the compiler to mark the attribute automatically. 5869 5870 5871File: as.info, Node: Machine Dependencies, Next: Reporting Bugs, Prev: Object Attributes, Up: Top 5872 58739 Machine Dependent Features 5874**************************** 5875 5876The machine instruction sets are (almost by definition) different on 5877each machine where 'as' runs. Floating point representations vary as 5878well, and 'as' often supports a few additional directives or 5879command-line options for compatibility with other assemblers on a 5880particular platform. Finally, some versions of 'as' support special 5881pseudo-instructions for branch optimization. 5882 5883 This chapter discusses most of these differences, though it does not 5884include details on any machine's instruction set. For details on that 5885subject, see the hardware manufacturer's manual. 5886 5887* Menu: 5888 5889* AArch64-Dependent:: AArch64 Dependent Features 5890* Alpha-Dependent:: Alpha Dependent Features 5891* ARC-Dependent:: ARC Dependent Features 5892* ARM-Dependent:: ARM Dependent Features 5893* AVR-Dependent:: AVR Dependent Features 5894* Blackfin-Dependent:: Blackfin Dependent Features 5895* CR16-Dependent:: CR16 Dependent Features 5896* CRIS-Dependent:: CRIS Dependent Features 5897* D10V-Dependent:: D10V Dependent Features 5898* D30V-Dependent:: D30V Dependent Features 5899* Epiphany-Dependent:: EPIPHANY Dependent Features 5900* H8/300-Dependent:: Renesas H8/300 Dependent Features 5901* HPPA-Dependent:: HPPA Dependent Features 5902* ESA/390-Dependent:: IBM ESA/390 Dependent Features 5903* i386-Dependent:: Intel 80386 and AMD x86-64 Dependent Features 5904* i860-Dependent:: Intel 80860 Dependent Features 5905* i960-Dependent:: Intel 80960 Dependent Features 5906* IA-64-Dependent:: Intel IA-64 Dependent Features 5907* IP2K-Dependent:: IP2K Dependent Features 5908* LM32-Dependent:: LM32 Dependent Features 5909* M32C-Dependent:: M32C Dependent Features 5910* M32R-Dependent:: M32R Dependent Features 5911* M68K-Dependent:: M680x0 Dependent Features 5912* M68HC11-Dependent:: M68HC11 and 68HC12 Dependent Features 5913* Meta-Dependent :: Meta Dependent Features 5914* MicroBlaze-Dependent:: MICROBLAZE Dependent Features 5915* MIPS-Dependent:: MIPS Dependent Features 5916* MMIX-Dependent:: MMIX Dependent Features 5917* MSP430-Dependent:: MSP430 Dependent Features 5918* NDS32-Dependent:: Andes NDS32 Dependent Features 5919* NiosII-Dependent:: Altera Nios II Dependent Features 5920* NS32K-Dependent:: NS32K Dependent Features 5921* PDP-11-Dependent:: PDP-11 Dependent Features 5922* PJ-Dependent:: picoJava Dependent Features 5923* PPC-Dependent:: PowerPC Dependent Features 5924* RL78-Dependent:: RL78 Dependent Features 5925* RISC-V-Dependent:: RISC-V Dependent Features 5926* RX-Dependent:: RX Dependent Features 5927* S/390-Dependent:: IBM S/390 Dependent Features 5928* SCORE-Dependent:: SCORE Dependent Features 5929* SH-Dependent:: Renesas / SuperH SH Dependent Features 5930* SH64-Dependent:: SuperH SH64 Dependent Features 5931* Sparc-Dependent:: SPARC Dependent Features 5932* TIC54X-Dependent:: TI TMS320C54x Dependent Features 5933* TIC6X-Dependent :: TI TMS320C6x Dependent Features 5934* TILE-Gx-Dependent :: Tilera TILE-Gx Dependent Features 5935* TILEPro-Dependent :: Tilera TILEPro Dependent Features 5936* V850-Dependent:: V850 Dependent Features 5937* Vax-Dependent:: VAX Dependent Features 5938* Visium-Dependent:: Visium Dependent Features 5939* XGATE-Dependent:: XGATE Features 5940* XSTORMY16-Dependent:: XStormy16 Dependent Features 5941* Xtensa-Dependent:: Xtensa Dependent Features 5942* Z80-Dependent:: Z80 Dependent Features 5943* Z8000-Dependent:: Z8000 Dependent Features 5944 5945 5946File: as.info, Node: AArch64-Dependent, Next: Alpha-Dependent, Up: Machine Dependencies 5947 59489.1 AArch64 Dependent Features 5949============================== 5950 5951* Menu: 5952 5953* AArch64 Options:: Options 5954* AArch64 Extensions:: Extensions 5955* AArch64 Syntax:: Syntax 5956* AArch64 Floating Point:: Floating Point 5957* AArch64 Directives:: AArch64 Machine Directives 5958* AArch64 Opcodes:: Opcodes 5959* AArch64 Mapping Symbols:: Mapping Symbols 5960 5961 5962File: as.info, Node: AArch64 Options, Next: AArch64 Extensions, Up: AArch64-Dependent 5963 59649.1.1 Options 5965------------- 5966 5967'-EB' 5968 This option specifies that the output generated by the assembler 5969 should be marked as being encoded for a big-endian processor. 5970 5971'-EL' 5972 This option specifies that the output generated by the assembler 5973 should be marked as being encoded for a little-endian processor. 5974 5975'-mabi=ABI' 5976 Specify which ABI the source code uses. The recognized arguments 5977 are: 'ilp32' and 'lp64', which decides the generated object file in 5978 ELF32 and ELF64 format respectively. The default is 'lp64'. 5979 5980'-mcpu=PROCESSOR[+EXTENSION...]' 5981 This option specifies the target processor. The assembler will 5982 issue an error message if an attempt is made to assemble an 5983 instruction which will not execute on the target processor. The 5984 following processor names are recognized: 'cortex-a35', 5985 'cortex-a53', 'cortex-a57', 'cortex-a72', 'cortex-a73', 5986 'exynos-m1', 'falkor', 'qdf24xx', 'thunderx', 'vulcan', 'xgene1' 5987 and 'xgene2'. The special name 'all' may be used to allow the 5988 assembler to accept instructions valid for any supported processor, 5989 including all optional extensions. 5990 5991 In addition to the basic instruction set, the assembler can be told 5992 to accept, or restrict, various extension mnemonics that extend the 5993 processor. *Note AArch64 Extensions::. 5994 5995 If some implementations of a particular processor can have an 5996 extension, then then those extensions are automatically enabled. 5997 Consequently, you will not normally have to specify any additional 5998 extensions. 5999 6000'-march=ARCHITECTURE[+EXTENSION...]' 6001 This option specifies the target architecture. The assembler will 6002 issue an error message if an attempt is made to assemble an 6003 instruction which will not execute on the target architecture. The 6004 following architecture names are recognized: 'armv8-a', 6005 'armv8.1-a', 'armv8.2-a' and 'armv8.3-a'. 6006 6007 If both '-mcpu' and '-march' are specified, the assembler will use 6008 the setting for '-mcpu'. If neither are specified, the assembler 6009 will default to '-mcpu=all'. 6010 6011 The architecture option can be extended with the same instruction 6012 set extension options as the '-mcpu' option. Unlike '-mcpu', 6013 extensions are not always enabled by default, *Note AArch64 6014 Extensions::. 6015 6016'-mverbose-error' 6017 This option enables verbose error messages for AArch64 gas. This 6018 option is enabled by default. 6019 6020'-mno-verbose-error' 6021 This option disables verbose error messages in AArch64 gas. 6022 6023 6024File: as.info, Node: AArch64 Extensions, Next: AArch64 Syntax, Prev: AArch64 Options, Up: AArch64-Dependent 6025 60269.1.2 Architecture Extensions 6027----------------------------- 6028 6029The table below lists the permitted architecture extensions that are 6030supported by the assembler and the conditions under which they are 6031automatically enabled. 6032 6033 Multiple extensions may be specified, separated by a '+'. Extension 6034mnemonics may also be removed from those the assembler accepts. This is 6035done by prepending 'no' to the option that adds the extension. 6036Extensions that are removed must be listed after all extensions that 6037have been added. 6038 6039 Enabling an extension that requires other extensions will 6040automatically cause those extensions to be enabled. Similarly, 6041disabling an extension that is required by other extensions will 6042automatically cause those extensions to be disabled. 6043 6044Extension Minimum Enabled by Description 6045 Architecture default 6046---------------------------------------------------------------------------- 6047'compnum' ARMv8.2-A ARMv8.3-A Enable the complex number SIMD 6048 or later extensions. This implies 'fp16' and 6049 'simd'. 6050'crc' ARMv8-A ARMv8.1-A Enable CRC instructions. 6051 or later 6052'crypto' ARMv8-A No Enable cryptographic extensions. 6053 This implies 'fp' and 'simd'. 6054'fp' ARMv8-A ARMv8-A or Enable floating-point extensions. 6055 later 6056'fp16' ARMv8.2-A ARMv8.2-A Enable ARMv8.2 16-bit floating-point 6057 or later support. This implies 'fp'. 6058'lor' ARMv8-A ARMv8.1-A Enable Limited Ordering Regions 6059 or later extensions. 6060'lse' ARMv8-A ARMv8.1-A Enable Large System extensions. 6061 or later 6062'pan' ARMv8-A ARMv8.1-A Enable Privileged Access Never 6063 or later support. 6064'profile' ARMv8.2-A No Enable statistical profiling 6065 extensions. 6066'ras' ARMv8-A ARMv8.2-A Enable the Reliability, Availability 6067 or later and Serviceability extension. 6068'rdma' ARMv8-A ARMv8.1-A Enable ARMv8.1 Advanced SIMD 6069 or later extensions. This implies 'simd'. 6070'simd' ARMv8-A ARMv8-A or Enable Advanced SIMD extensions. 6071 later This implies 'fp'. 6072'sve' ARMv8.2-A No Enable the Scalable Vector 6073 Extensions. This implies 'fp16', 6074 'simd' and 'compnum'. 6075 6076 6077File: as.info, Node: AArch64 Syntax, Next: AArch64 Floating Point, Prev: AArch64 Extensions, Up: AArch64-Dependent 6078 60799.1.3 Syntax 6080------------ 6081 6082* Menu: 6083 6084* AArch64-Chars:: Special Characters 6085* AArch64-Regs:: Register Names 6086* AArch64-Relocations:: Relocations 6087 6088 6089File: as.info, Node: AArch64-Chars, Next: AArch64-Regs, Up: AArch64 Syntax 6090 60919.1.3.1 Special Characters 6092.......................... 6093 6094The presence of a '//' on a line indicates the start of a comment that 6095extends to the end of the current line. If a '#' appears as the first 6096character of a line, the whole line is treated as a comment. 6097 6098 The ';' character can be used instead of a newline to separate 6099statements. 6100 6101 The '#' can be optionally used to indicate immediate operands. 6102 6103 6104File: as.info, Node: AArch64-Regs, Next: AArch64-Relocations, Prev: AArch64-Chars, Up: AArch64 Syntax 6105 61069.1.3.2 Register Names 6107...................... 6108 6109Please refer to the section '4.4 Register Names' of 'ARMv8 Instruction 6110Set Overview', which is available at <http://infocenter.arm.com>. 6111 6112 6113File: as.info, Node: AArch64-Relocations, Prev: AArch64-Regs, Up: AArch64 Syntax 6114 61159.1.3.3 Relocations 6116................... 6117 6118Relocations for 'MOVZ' and 'MOVK' instructions can be generated by 6119prefixing the label with '#:abs_g2:' etc. For example to load the 612048-bit absolute address of FOO into x0: 6121 6122 movz x0, #:abs_g2:foo // bits 32-47, overflow check 6123 movk x0, #:abs_g1_nc:foo // bits 16-31, no overflow check 6124 movk x0, #:abs_g0_nc:foo // bits 0-15, no overflow check 6125 6126 Relocations for 'ADRP', and 'ADD', 'LDR' or 'STR' instructions can be 6127generated by prefixing the label with ':pg_hi21:' and '#:lo12:' 6128respectively. 6129 6130 For example to use 33-bit (+/-4GB) pc-relative addressing to load the 6131address of FOO into x0: 6132 6133 adrp x0, :pg_hi21:foo 6134 add x0, x0, #:lo12:foo 6135 6136 Or to load the value of FOO into x0: 6137 6138 adrp x0, :pg_hi21:foo 6139 ldr x0, [x0, #:lo12:foo] 6140 6141 Note that ':pg_hi21:' is optional. 6142 6143 adrp x0, foo 6144 6145 is equivalent to 6146 6147 adrp x0, :pg_hi21:foo 6148 6149 6150File: as.info, Node: AArch64 Floating Point, Next: AArch64 Directives, Prev: AArch64 Syntax, Up: AArch64-Dependent 6151 61529.1.4 Floating Point 6153-------------------- 6154 6155The AArch64 architecture uses IEEE floating-point numbers. 6156 6157 6158File: as.info, Node: AArch64 Directives, Next: AArch64 Opcodes, Prev: AArch64 Floating Point, Up: AArch64-Dependent 6159 61609.1.5 AArch64 Machine Directives 6161-------------------------------- 6162 6163'.arch NAME' 6164 Select the target architecture. Valid values for NAME are the same 6165 as for the '-march' commandline option. 6166 6167 Specifying '.arch' clears any previously selected architecture 6168 extensions. 6169 6170'.arch_extension NAME' 6171 Add or remove an architecture extension to the target architecture. 6172 Valid values for NAME are the same as those accepted as 6173 architectural extensions by the '-mcpu' commandline option. 6174 6175 '.arch_extension' may be used multiple times to add or remove 6176 extensions incrementally to the architecture being compiled for. 6177 6178'.bss' 6179 This directive switches to the '.bss' section. 6180 6181'.cpu NAME' 6182 Set the target processor. Valid values for NAME are the same as 6183 those accepted by the '-mcpu=' command line option. 6184 6185'.dword EXPRESSIONS' 6186 The '.dword' directive produces 64 bit values. 6187 6188'.even' 6189 The '.even' directive aligns the output on the next even byte 6190 boundary. 6191 6192'.inst EXPRESSIONS' 6193 Inserts the expressions into the output as if they were 6194 instructions, rather than data. 6195 6196'.ltorg' 6197 This directive causes the current contents of the literal pool to 6198 be dumped into the current section (which is assumed to be the 6199 .text section) at the current location (aligned to a word 6200 boundary). GAS maintains a separate literal pool for each section 6201 and each sub-section. The '.ltorg' directive will only affect the 6202 literal pool of the current section and sub-section. At the end of 6203 assembly all remaining, un-empty literal pools will automatically 6204 be dumped. 6205 6206 Note - older versions of GAS would dump the current literal pool 6207 any time a section change occurred. This is no longer done, since 6208 it prevents accurate control of the placement of literal pools. 6209 6210'.pool' 6211 This is a synonym for .ltorg. 6212 6213'NAME .req REGISTER NAME' 6214 This creates an alias for REGISTER NAME called NAME. For example: 6215 6216 foo .req w0 6217 6218'.tlsdescadd' 6219 Emits a TLSDESC_ADD reloc on the next instruction. 6220 6221'.tlsdesccall' 6222 Emits a TLSDESC_CALL reloc on the next instruction. 6223 6224'.tlsdescldr' 6225 Emits a TLSDESC_LDR reloc on the next instruction. 6226 6227'.unreq ALIAS-NAME' 6228 This undefines a register alias which was previously defined using 6229 the 'req' directive. For example: 6230 6231 foo .req w0 6232 .unreq foo 6233 6234 An error occurs if the name is undefined. Note - this pseudo op 6235 can be used to delete builtin in register name aliases (eg 'w0'). 6236 This should only be done if it is really necessary. 6237 6238'.xword EXPRESSIONS' 6239 The '.xword' directive produces 64 bit values. This is the same as 6240 the '.dword' directive. 6241 6242 6243File: as.info, Node: AArch64 Opcodes, Next: AArch64 Mapping Symbols, Prev: AArch64 Directives, Up: AArch64-Dependent 6244 62459.1.6 Opcodes 6246------------- 6247 6248GAS implements all the standard AArch64 opcodes. It also implements 6249several pseudo opcodes, including several synthetic load instructions. 6250 6251'LDR =' 6252 ldr <register> , =<expression> 6253 6254 The constant expression will be placed into the nearest literal 6255 pool (if it not already there) and a PC-relative LDR instruction 6256 will be generated. 6257 6258 For more information on the AArch64 instruction set and assembly 6259language notation, see 'ARMv8 Instruction Set Overview' available at 6260<http://infocenter.arm.com>. 6261 6262 6263File: as.info, Node: AArch64 Mapping Symbols, Prev: AArch64 Opcodes, Up: AArch64-Dependent 6264 62659.1.7 Mapping Symbols 6266--------------------- 6267 6268The AArch64 ELF specification requires that special symbols be inserted 6269into object files to mark certain features: 6270 6271'$x' 6272 At the start of a region of code containing AArch64 instructions. 6273 6274'$d' 6275 At the start of a region of data. 6276 6277 6278File: as.info, Node: Alpha-Dependent, Next: ARC-Dependent, Prev: AArch64-Dependent, Up: Machine Dependencies 6279 62809.2 Alpha Dependent Features 6281============================ 6282 6283* Menu: 6284 6285* Alpha Notes:: Notes 6286* Alpha Options:: Options 6287* Alpha Syntax:: Syntax 6288* Alpha Floating Point:: Floating Point 6289* Alpha Directives:: Alpha Machine Directives 6290* Alpha Opcodes:: Opcodes 6291 6292 6293File: as.info, Node: Alpha Notes, Next: Alpha Options, Up: Alpha-Dependent 6294 62959.2.1 Notes 6296----------- 6297 6298The documentation here is primarily for the ELF object format. 'as' 6299also supports the ECOFF and EVAX formats, but features specific to these 6300formats are not yet documented. 6301 6302 6303File: as.info, Node: Alpha Options, Next: Alpha Syntax, Prev: Alpha Notes, Up: Alpha-Dependent 6304 63059.2.2 Options 6306------------- 6307 6308'-mCPU' 6309 This option specifies the target processor. If an attempt is made 6310 to assemble an instruction which will not execute on the target 6311 processor, the assembler may either expand the instruction as a 6312 macro or issue an error message. This option is equivalent to the 6313 '.arch' directive. 6314 6315 The following processor names are recognized: '21064', '21064a', 6316 '21066', '21068', '21164', '21164a', '21164pc', '21264', '21264a', 6317 '21264b', 'ev4', 'ev5', 'lca45', 'ev5', 'ev56', 'pca56', 'ev6', 6318 'ev67', 'ev68'. The special name 'all' may be used to allow the 6319 assembler to accept instructions valid for any Alpha processor. 6320 6321 In order to support existing practice in OSF/1 with respect to 6322 '.arch', and existing practice within 'MILO' (the Linux ARC 6323 bootloader), the numbered processor names (e.g. 21064) enable the 6324 processor-specific PALcode instructions, while the "electro-vlasic" 6325 names (e.g. 'ev4') do not. 6326 6327'-mdebug' 6328'-no-mdebug' 6329 Enables or disables the generation of '.mdebug' encapsulation for 6330 stabs directives and procedure descriptors. The default is to 6331 automatically enable '.mdebug' when the first stabs directive is 6332 seen. 6333 6334'-relax' 6335 This option forces all relocations to be put into the object file, 6336 instead of saving space and resolving some relocations at assembly 6337 time. Note that this option does not propagate all symbol 6338 arithmetic into the object file, because not all symbol arithmetic 6339 can be represented. However, the option can still be useful in 6340 specific applications. 6341 6342'-replace' 6343'-noreplace' 6344 Enables or disables the optimization of procedure calls, both at 6345 assemblage and at link time. These options are only available for 6346 VMS targets and '-replace' is the default. See section 1.4.1 of 6347 the OpenVMS Linker Utility Manual. 6348 6349'-g' 6350 This option is used when the compiler generates debug information. 6351 When 'gcc' is using 'mips-tfile' to generate debug information for 6352 ECOFF, local labels must be passed through to the object file. 6353 Otherwise this option has no effect. 6354 6355'-GSIZE' 6356 A local common symbol larger than SIZE is placed in '.bss', while 6357 smaller symbols are placed in '.sbss'. 6358 6359'-F' 6360'-32addr' 6361 These options are ignored for backward compatibility. 6362 6363 6364File: as.info, Node: Alpha Syntax, Next: Alpha Floating Point, Prev: Alpha Options, Up: Alpha-Dependent 6365 63669.2.3 Syntax 6367------------ 6368 6369The assembler syntax closely follow the Alpha Reference Manual; 6370assembler directives and general syntax closely follow the OSF/1 and 6371OpenVMS syntax, with a few differences for ELF. 6372 6373* Menu: 6374 6375* Alpha-Chars:: Special Characters 6376* Alpha-Regs:: Register Names 6377* Alpha-Relocs:: Relocations 6378 6379 6380File: as.info, Node: Alpha-Chars, Next: Alpha-Regs, Up: Alpha Syntax 6381 63829.2.3.1 Special Characters 6383.......................... 6384 6385'#' is the line comment character. Note that if '#' is the first 6386character on a line then it can also be a logical line number directive 6387(*note Comments::) or a preprocessor control command (*note 6388Preprocessing::). 6389 6390 ';' can be used instead of a newline to separate statements. 6391 6392 6393File: as.info, Node: Alpha-Regs, Next: Alpha-Relocs, Prev: Alpha-Chars, Up: Alpha Syntax 6394 63959.2.3.2 Register Names 6396...................... 6397 6398The 32 integer registers are referred to as '$N' or '$rN'. In addition, 6399registers 15, 28, 29, and 30 may be referred to by the symbols '$fp', 6400'$at', '$gp', and '$sp' respectively. 6401 6402 The 32 floating-point registers are referred to as '$fN'. 6403 6404 6405File: as.info, Node: Alpha-Relocs, Prev: Alpha-Regs, Up: Alpha Syntax 6406 64079.2.3.3 Relocations 6408................... 6409 6410Some of these relocations are available for ECOFF, but mostly only for 6411ELF. They are modeled after the relocation format introduced in Digital 6412Unix 4.0, but there are additions. 6413 6414 The format is '!TAG' or '!TAG!NUMBER' where TAG is the name of the 6415relocation. In some cases NUMBER is used to relate specific 6416instructions. 6417 6418 The relocation is placed at the end of the instruction like so: 6419 6420 ldah $0,a($29) !gprelhigh 6421 lda $0,a($0) !gprellow 6422 ldq $1,b($29) !literal!100 6423 ldl $2,0($1) !lituse_base!100 6424 6425'!literal' 6426'!literal!N' 6427 Used with an 'ldq' instruction to load the address of a symbol from 6428 the GOT. 6429 6430 A sequence number N is optional, and if present is used to pair 6431 'lituse' relocations with this 'literal' relocation. The 'lituse' 6432 relocations are used by the linker to optimize the code based on 6433 the final location of the symbol. 6434 6435 Note that these optimizations are dependent on the data flow of the 6436 program. Therefore, if _any_ 'lituse' is paired with a 'literal' 6437 relocation, then _all_ uses of the register set by the 'literal' 6438 instruction must also be marked with 'lituse' relocations. This is 6439 because the original 'literal' instruction may be deleted or 6440 transformed into another instruction. 6441 6442 Also note that there may be a one-to-many relationship between 6443 'literal' and 'lituse', but not a many-to-one. That is, if there 6444 are two code paths that load up the same address and feed the value 6445 to a single use, then the use may not use a 'lituse' relocation. 6446 6447'!lituse_base!N' 6448 Used with any memory format instruction (e.g. 'ldl') to indicate 6449 that the literal is used for an address load. The offset field of 6450 the instruction must be zero. During relaxation, the code may be 6451 altered to use a gp-relative load. 6452 6453'!lituse_jsr!N' 6454 Used with a register branch format instruction (e.g. 'jsr') to 6455 indicate that the literal is used for a call. During relaxation, 6456 the code may be altered to use a direct branch (e.g. 'bsr'). 6457 6458'!lituse_jsrdirect!N' 6459 Similar to 'lituse_jsr', but also that this call cannot be vectored 6460 through a PLT entry. This is useful for functions with special 6461 calling conventions which do not allow the normal call-clobbered 6462 registers to be clobbered. 6463 6464'!lituse_bytoff!N' 6465 Used with a byte mask instruction (e.g. 'extbl') to indicate that 6466 only the low 3 bits of the address are relevant. During 6467 relaxation, the code may be altered to use an immediate instead of 6468 a register shift. 6469 6470'!lituse_addr!N' 6471 Used with any other instruction to indicate that the original 6472 address is in fact used, and the original 'ldq' instruction may not 6473 be altered or deleted. This is useful in conjunction with 6474 'lituse_jsr' to test whether a weak symbol is defined. 6475 6476 ldq $27,foo($29) !literal!1 6477 beq $27,is_undef !lituse_addr!1 6478 jsr $26,($27),foo !lituse_jsr!1 6479 6480'!lituse_tlsgd!N' 6481 Used with a register branch format instruction to indicate that the 6482 literal is the call to '__tls_get_addr' used to compute the address 6483 of the thread-local storage variable whose descriptor was loaded 6484 with '!tlsgd!N'. 6485 6486'!lituse_tlsldm!N' 6487 Used with a register branch format instruction to indicate that the 6488 literal is the call to '__tls_get_addr' used to compute the address 6489 of the base of the thread-local storage block for the current 6490 module. The descriptor for the module must have been loaded with 6491 '!tlsldm!N'. 6492 6493'!gpdisp!N' 6494 Used with 'ldah' and 'lda' to load the GP from the current address, 6495 a-la the 'ldgp' macro. The source register for the 'ldah' 6496 instruction must contain the address of the 'ldah' instruction. 6497 There must be exactly one 'lda' instruction paired with the 'ldah' 6498 instruction, though it may appear anywhere in the instruction 6499 stream. The immediate operands must be zero. 6500 6501 bsr $26,foo 6502 ldah $29,0($26) !gpdisp!1 6503 lda $29,0($29) !gpdisp!1 6504 6505'!gprelhigh' 6506 Used with an 'ldah' instruction to add the high 16 bits of a 32-bit 6507 displacement from the GP. 6508 6509'!gprellow' 6510 Used with any memory format instruction to add the low 16 bits of a 6511 32-bit displacement from the GP. 6512 6513'!gprel' 6514 Used with any memory format instruction to add a 16-bit 6515 displacement from the GP. 6516 6517'!samegp' 6518 Used with any branch format instruction to skip the GP load at the 6519 target address. The referenced symbol must have the same GP as the 6520 source object file, and it must be declared to either not use '$27' 6521 or perform a standard GP load in the first two instructions via the 6522 '.prologue' directive. 6523 6524'!tlsgd' 6525'!tlsgd!N' 6526 Used with an 'lda' instruction to load the address of a TLS 6527 descriptor for a symbol in the GOT. 6528 6529 The sequence number N is optional, and if present it used to pair 6530 the descriptor load with both the 'literal' loading the address of 6531 the '__tls_get_addr' function and the 'lituse_tlsgd' marking the 6532 call to that function. 6533 6534 For proper relaxation, both the 'tlsgd', 'literal' and 'lituse' 6535 relocations must be in the same extended basic block. That is, the 6536 relocation with the lowest address must be executed first at 6537 runtime. 6538 6539'!tlsldm' 6540'!tlsldm!N' 6541 Used with an 'lda' instruction to load the address of a TLS 6542 descriptor for the current module in the GOT. 6543 6544 Similar in other respects to 'tlsgd'. 6545 6546'!gotdtprel' 6547 Used with an 'ldq' instruction to load the offset of the TLS symbol 6548 within its module's thread-local storage block. Also known as the 6549 dynamic thread pointer offset or dtp-relative offset. 6550 6551'!dtprelhi' 6552'!dtprello' 6553'!dtprel' 6554 Like 'gprel' relocations except they compute dtp-relative offsets. 6555 6556'!gottprel' 6557 Used with an 'ldq' instruction to load the offset of the TLS symbol 6558 from the thread pointer. Also known as the tp-relative offset. 6559 6560'!tprelhi' 6561'!tprello' 6562'!tprel' 6563 Like 'gprel' relocations except they compute tp-relative offsets. 6564 6565 6566File: as.info, Node: Alpha Floating Point, Next: Alpha Directives, Prev: Alpha Syntax, Up: Alpha-Dependent 6567 65689.2.4 Floating Point 6569-------------------- 6570 6571The Alpha family uses both IEEE and VAX floating-point numbers. 6572 6573 6574File: as.info, Node: Alpha Directives, Next: Alpha Opcodes, Prev: Alpha Floating Point, Up: Alpha-Dependent 6575 65769.2.5 Alpha Assembler Directives 6577-------------------------------- 6578 6579'as' for the Alpha supports many additional directives for compatibility 6580with the native assembler. This section describes them only briefly. 6581 6582 These are the additional directives in 'as' for the Alpha: 6583 6584'.arch CPU' 6585 Specifies the target processor. This is equivalent to the '-mCPU' 6586 command-line option. *Note Options: Alpha Options, for a list of 6587 values for CPU. 6588 6589'.ent FUNCTION[, N]' 6590 Mark the beginning of FUNCTION. An optional number may follow for 6591 compatibility with the OSF/1 assembler, but is ignored. When 6592 generating '.mdebug' information, this will create a procedure 6593 descriptor for the function. In ELF, it will mark the symbol as a 6594 function a-la the generic '.type' directive. 6595 6596'.end FUNCTION' 6597 Mark the end of FUNCTION. In ELF, it will set the size of the 6598 symbol a-la the generic '.size' directive. 6599 6600'.mask MASK, OFFSET' 6601 Indicate which of the integer registers are saved in the current 6602 function's stack frame. MASK is interpreted a bit mask in which 6603 bit N set indicates that register N is saved. The registers are 6604 saved in a block located OFFSET bytes from the "canonical frame 6605 address" (CFA) which is the value of the stack pointer on entry to 6606 the function. The registers are saved sequentially, except that 6607 the return address register (normally '$26') is saved first. 6608 6609 This and the other directives that describe the stack frame are 6610 currently only used when generating '.mdebug' information. They 6611 may in the future be used to generate DWARF2 '.debug_frame' unwind 6612 information for hand written assembly. 6613 6614'.fmask MASK, OFFSET' 6615 Indicate which of the floating-point registers are saved in the 6616 current stack frame. The MASK and OFFSET parameters are 6617 interpreted as with '.mask'. 6618 6619'.frame FRAMEREG, FRAMEOFFSET, RETREG[, ARGOFFSET]' 6620 Describes the shape of the stack frame. The frame pointer in use 6621 is FRAMEREG; normally this is either '$fp' or '$sp'. The frame 6622 pointer is FRAMEOFFSET bytes below the CFA. The return address is 6623 initially located in RETREG until it is saved as indicated in 6624 '.mask'. For compatibility with OSF/1 an optional ARGOFFSET 6625 parameter is accepted and ignored. It is believed to indicate the 6626 offset from the CFA to the saved argument registers. 6627 6628'.prologue N' 6629 Indicate that the stack frame is set up and all registers have been 6630 spilled. The argument N indicates whether and how the function 6631 uses the incoming "procedure vector" (the address of the called 6632 function) in '$27'. 0 indicates that '$27' is not used; 1 6633 indicates that the first two instructions of the function use '$27' 6634 to perform a load of the GP register; 2 indicates that '$27' is 6635 used in some non-standard way and so the linker cannot elide the 6636 load of the procedure vector during relaxation. 6637 6638'.usepv FUNCTION, WHICH' 6639 Used to indicate the use of the '$27' register, similar to 6640 '.prologue', but without the other semantics of needing to be 6641 inside an open '.ent'/'.end' block. 6642 6643 The WHICH argument should be either 'no', indicating that '$27' is 6644 not used, or 'std', indicating that the first two instructions of 6645 the function perform a GP load. 6646 6647 One might use this directive instead of '.prologue' if you are also 6648 using dwarf2 CFI directives. 6649 6650'.gprel32 EXPRESSION' 6651 Computes the difference between the address in EXPRESSION and the 6652 GP for the current object file, and stores it in 4 bytes. In 6653 addition to being smaller than a full 8 byte address, this also 6654 does not require a dynamic relocation when used in a shared 6655 library. 6656 6657'.t_floating EXPRESSION' 6658 Stores EXPRESSION as an IEEE double precision value. 6659 6660'.s_floating EXPRESSION' 6661 Stores EXPRESSION as an IEEE single precision value. 6662 6663'.f_floating EXPRESSION' 6664 Stores EXPRESSION as a VAX F format value. 6665 6666'.g_floating EXPRESSION' 6667 Stores EXPRESSION as a VAX G format value. 6668 6669'.d_floating EXPRESSION' 6670 Stores EXPRESSION as a VAX D format value. 6671 6672'.set FEATURE' 6673 Enables or disables various assembler features. Using the positive 6674 name of the feature enables while using 'noFEATURE' disables. 6675 6676 'at' 6677 Indicates that macro expansions may clobber the "assembler 6678 temporary" ('$at' or '$28') register. Some macros may not be 6679 expanded without this and will generate an error message if 6680 'noat' is in effect. When 'at' is in effect, a warning will 6681 be generated if '$at' is used by the programmer. 6682 6683 'macro' 6684 Enables the expansion of macro instructions. Note that 6685 variants of real instructions, such as 'br label' vs 'br 6686 $31,label' are considered alternate forms and not macros. 6687 6688 'move' 6689 'reorder' 6690 'volatile' 6691 These control whether and how the assembler may re-order 6692 instructions. Accepted for compatibility with the OSF/1 6693 assembler, but 'as' does not do instruction scheduling, so 6694 these features are ignored. 6695 6696 The following directives are recognized for compatibility with the 6697OSF/1 assembler but are ignored. 6698 6699 .proc .aproc 6700 .reguse .livereg 6701 .option .aent 6702 .ugen .eflag 6703 .alias .noalias 6704 6705 6706File: as.info, Node: Alpha Opcodes, Prev: Alpha Directives, Up: Alpha-Dependent 6707 67089.2.6 Opcodes 6709------------- 6710 6711For detailed information on the Alpha machine instruction set, see the 6712Alpha Architecture Handbook 6713(ftp://ftp.digital.com/pub/Digital/info/semiconductor/literature/alphaahb.pdf). 6714 6715 6716File: as.info, Node: ARC-Dependent, Next: ARM-Dependent, Prev: Alpha-Dependent, Up: Machine Dependencies 6717 67189.3 ARC Dependent Features 6719========================== 6720 6721* Menu: 6722 6723* ARC Options:: Options 6724* ARC Syntax:: Syntax 6725* ARC Directives:: ARC Machine Directives 6726* ARC Modifiers:: ARC Assembler Modifiers 6727* ARC Symbols:: ARC Pre-defined Symbols 6728* ARC Opcodes:: Opcodes 6729 6730 6731File: as.info, Node: ARC Options, Next: ARC Syntax, Up: ARC-Dependent 6732 67339.3.1 Options 6734------------- 6735 6736The following options control the type of CPU for which code is 6737assembled, and generic constraints on the code generated: 6738 6739'-mcpu=CPU' 6740 Set architecture type and register usage for CPU. There are also 6741 shortcut alias options available for backward compatibility and 6742 convenience. Supported values for CPU are 6743 6744 'arc600' 6745 Assemble for ARC 600. Aliases: '-mA6', '-mARC600'. 6746 6747 'arc600_norm' 6748 Assemble for ARC 600 with norm instructions. 6749 6750 'arc600_mul64' 6751 Assemble for ARC 600 with mul64 instructions. 6752 6753 'arc600_mul32x16' 6754 Assemble for ARC 600 with mul32x16 instructions. 6755 6756 'arc601' 6757 Assemble for ARC 601. Alias: '-mARC601'. 6758 6759 'arc601_norm' 6760 Assemble for ARC 601 with norm instructions. 6761 6762 'arc601_mul64' 6763 Assemble for ARC 601 with mul64 instructions. 6764 6765 'arc601_mul32x16' 6766 Assemble for ARC 601 with mul32x16 instructions. 6767 6768 'arc700' 6769 Assemble for ARC 700. Aliases: '-mA7', '-mARC700'. 6770 6771 'arcem' 6772 Assemble for ARC EM. Aliases: '-mEM' 6773 6774 'em' 6775 Assemble for ARC EM, identical as arcem variant. 6776 6777 'em4' 6778 Assemble for ARC EM with code-density instructions. 6779 6780 'em4_dmips' 6781 Assemble for ARC EM with code-density instructions. 6782 6783 'em4_fpus' 6784 Assemble for ARC EM with code-density instructions. 6785 6786 'em4_fpuda' 6787 Assemble for ARC EM with code-density, and double-precision 6788 assist instructions. 6789 6790 'quarkse_em' 6791 Assemble for QuarkSE-EM cpu. 6792 6793 'archs' 6794 Assemble for ARC HS. Aliases: '-mHS', '-mav2hs'. 6795 6796 'hs' 6797 Assemble for ARC HS. 6798 6799 'hs34' 6800 Assemble for ARC HS34. 6801 6802 'hs38' 6803 Assemble for ARC HS38. 6804 6805 'hs38_linux' 6806 Assemble for ARC HS38 with floating point support on. 6807 6808 'nps400' 6809 Assemble for ARC 700 with NPS-400 extended instructions. 6810 6811 Note: the '.cpu' directive (*note ARC Directives::) can to be used 6812 to select a core variant from within assembly code. 6813 6814'-EB' 6815 This option specifies that the output generated by the assembler 6816 should be marked as being encoded for a big-endian processor. 6817 6818'-EL' 6819 This option specifies that the output generated by the assembler 6820 should be marked as being encoded for a little-endian processor - 6821 this is the default. 6822 6823'-mcode-density' 6824 This option turns on Code Density instructions. Only valid for ARC 6825 EM processors. 6826 6827'-mrelax' 6828 Enable support for assembly-time relaxation. The assembler will 6829 replace a longer version of an instruction with a shorter one, 6830 whenever it is possible. 6831 6832'-mnps400' 6833 Enable support for NPS-400 extended instructions. 6834 6835'-mspfp' 6836 Enable support for single-precision floating point instructions. 6837 6838'-mdpfp' 6839 Enable support for double-precision floating point instructions. 6840 6841'-mfpuda' 6842 Enable support for double-precision assist floating point 6843 instructions. Only valid for ARC EM processors. 6844 6845 6846File: as.info, Node: ARC Syntax, Next: ARC Directives, Prev: ARC Options, Up: ARC-Dependent 6847 68489.3.2 Syntax 6849------------ 6850 6851* Menu: 6852 6853* ARC-Chars:: Special Characters 6854* ARC-Regs:: Register Names 6855 6856 6857File: as.info, Node: ARC-Chars, Next: ARC-Regs, Up: ARC Syntax 6858 68599.3.2.1 Special Characters 6860.......................... 6861 6862'%' 6863 A register name can optionally be prefixed by a '%' character. So 6864 register '%r0' is equivalent to 'r0' in the assembly code. 6865 6866'#' 6867 The presence of a '#' character within a line (but not at the start 6868 of a line) indicates the start of a comment that extends to the end 6869 of the current line. 6870 6871 _Note:_ if a line starts with a '#' character then it can also be a 6872 logical line number directive (*note Comments::) or a preprocessor 6873 control command (*note Preprocessing::). 6874 6875'@' 6876 Prefixing an operand with an '@' specifies that the operand is a 6877 symbol and not a register. This is how the assembler disambiguates 6878 the use of an ARC register name as a symbol. So the instruction 6879 mov r0, @r0 6880 moves the address of symbol 'r0' into register 'r0'. 6881 6882'`' 6883 The '`' (backtick) character is used to separate statements on a 6884 single line. 6885 6886'-' 6887 Used as a separator to obtain a sequence of commands from a C 6888 preprocessor macro. 6889 6890 6891File: as.info, Node: ARC-Regs, Prev: ARC-Chars, Up: ARC Syntax 6892 68939.3.2.2 Register Names 6894...................... 6895 6896The ARC assembler uses the following register names for its core 6897registers: 6898 6899'r0-r31' 6900 The core general registers. Registers 'r26' through 'r31' have 6901 special functions, and are usually referred to by those synonyms. 6902 6903'gp' 6904 The global pointer and a synonym for 'r26'. 6905 6906'fp' 6907 The frame pointer and a synonym for 'r27'. 6908 6909'sp' 6910 The stack pointer and a synonym for 'r28'. 6911 6912'ilink1' 6913 For ARC 600 and ARC 700, the level 1 interrupt link register and a 6914 synonym for 'r29'. Not supported for ARCv2. 6915 6916'ilink' 6917 For ARCv2, the interrupt link register and a synonym for 'r29'. 6918 Not supported for ARC 600 and ARC 700. 6919 6920'ilink2' 6921 For ARC 600 and ARC 700, the level 2 interrupt link register and a 6922 synonym for 'r30'. Not supported for ARC v2. 6923 6924'blink' 6925 The link register and a synonym for 'r31'. 6926 6927'r32-r59' 6928 The extension core registers. 6929 6930'lp_count' 6931 The loop count register. 6932 6933'pcl' 6934 The word aligned program counter. 6935 6936 In addition the ARC processor has a large number of _auxiliary 6937registers_. The precise set depends on the extensions being supported, 6938but the following baseline set are always defined: 6939 6940'identity' 6941 Processor Identification register. Auxiliary register address 0x4. 6942 6943'pc' 6944 Program Counter. Auxiliary register address 0x6. 6945 6946'status32' 6947 Status register. Auxiliary register address 0x0a. 6948 6949'bta' 6950 Branch Target Address. Auxiliary register address 0x412. 6951 6952'ecr' 6953 Exception Cause Register. Auxiliary register address 0x403. 6954 6955'int_vector_base' 6956 Interrupt Vector Base address. Auxiliary register address 0x25. 6957 6958'status32_p0' 6959 Stored STATUS32 register on entry to level P0 interrupts. 6960 Auxiliary register address 0xb. 6961 6962'aux_user_sp' 6963 Saved User Stack Pointer. Auxiliary register address 0xd. 6964 6965'eret' 6966 Exception Return Address. Auxiliary register address 0x400. 6967 6968'erbta' 6969 BTA saved on exception entry. Auxiliary register address 0x401. 6970 6971'erstatus' 6972 STATUS32 saved on exception. Auxiliary register address 0x402. 6973 6974'bcr_ver' 6975 Build Configuration Registers Version. Auxiliary register address 6976 0x60. 6977 6978'bta_link_build' 6979 Build configuration for: BTA Registers. Auxiliary register address 6980 0x63. 6981 6982'vecbase_ac_build' 6983 Build configuration for: Interrupts. Auxiliary register address 6984 0x68. 6985 6986'rf_build' 6987 Build configuration for: Core Registers. Auxiliary register 6988 address 0x6e. 6989 6990'dccm_build' 6991 DCCM RAM Configuration Register. Auxiliary register address 0xc1. 6992 6993 Additional auxiliary register names are defined according to the 6994processor architecture version and extensions selected by the options. 6995 6996 6997File: as.info, Node: ARC Directives, Next: ARC Modifiers, Prev: ARC Syntax, Up: ARC-Dependent 6998 69999.3.3 ARC Machine Directives 7000---------------------------- 7001 7002The ARC version of 'as' supports the following additional machine 7003directives: 7004 7005'.lcomm SYMBOL, LENGTH[, ALIGNMENT]' 7006 Reserve LENGTH (an absolute expression) bytes for a local common 7007 denoted by SYMBOL. The section and value of SYMBOL are those of 7008 the new local common. The addresses are allocated in the bss 7009 section, so that at run-time the bytes start off zeroed. Since 7010 SYMBOL is not declared global, it is normally not visible to 'ld'. 7011 The optional third parameter, ALIGNMENT, specifies the desired 7012 alignment of the symbol in the bss section, specified as a byte 7013 boundary (for example, an alignment of 16 means that the least 7014 significant 4 bits of the address should be zero). The alignment 7015 must be an absolute expression, and it must be a power of two. If 7016 no alignment is specified, as will set the alignment to the largest 7017 power of two less than or equal to the size of the symbol, up to a 7018 maximum of 16. 7019 7020'.lcommon SYMBOL, LENGTH[, ALIGNMENT]' 7021 The same as 'lcomm' directive. 7022 7023'.cpu CPU' 7024 The '.cpu' directive must be followed by the desired core version. 7025 Permitted values for CPU are: 7026 'ARC600' 7027 Assemble for the ARC600 instruction set. 7028 7029 'arc600_norm' 7030 Assemble for ARC 600 with norm instructions. 7031 7032 'arc600_mul64' 7033 Assemble for ARC 600 with mul64 instructions. 7034 7035 'arc600_mul32x16' 7036 Assemble for ARC 600 with mul32x16 instructions. 7037 7038 'arc601' 7039 Assemble for ARC 601 instruction set. 7040 7041 'arc601_norm' 7042 Assemble for ARC 601 with norm instructions. 7043 7044 'arc601_mul64' 7045 Assemble for ARC 601 with mul64 instructions. 7046 7047 'arc601_mul32x16' 7048 Assemble for ARC 601 with mul32x16 instructions. 7049 7050 'ARC700' 7051 Assemble for the ARC700 instruction set. 7052 7053 'NPS400' 7054 Assemble for the NPS400 instruction set. 7055 7056 'EM' 7057 Assemble for the ARC EM instruction set. 7058 7059 'arcem' 7060 Assemble for ARC EM instruction set 7061 7062 'em4' 7063 Assemble for ARC EM with code-density instructions. 7064 7065 'em4_dmips' 7066 Assemble for ARC EM with code-density instructions. 7067 7068 'em4_fpus' 7069 Assemble for ARC EM with code-density instructions. 7070 7071 'em4_fpuda' 7072 Assemble for ARC EM with code-density, and double-precision 7073 assist instructions. 7074 7075 'quarkse_em' 7076 Assemble for QuarkSE-EM instruction set. 7077 7078 'HS' 7079 Assemble for the ARC HS instruction set. 7080 7081 'archs' 7082 Assemble for ARC HS instruction set. 7083 7084 'hs' 7085 Assemble for ARC HS instruction set. 7086 7087 'hs34' 7088 Assemble for ARC HS34 instruction set. 7089 7090 'hs38' 7091 Assemble for ARC HS38 instruction set. 7092 7093 'hs38_linux' 7094 Assemble for ARC HS38 with floating point support on. 7095 7096 Note: the '.cpu' directive overrides the command line option 7097 '-mcpu=CPU'; a warning is emitted when the version is not 7098 consistent between the two. 7099 7100'.extAuxRegister NAME, ADDR, MODE' 7101 Auxiliary registers can be defined in the assembler source code by 7102 using this directive. The first parameter, NAME, is the name of 7103 the new auxiliary register. The second parameter, ADDR, is address 7104 the of the auxiliary register. The third parameter, MODE, 7105 specifies whether the register is readable and/or writable and is 7106 one of: 7107 'r' 7108 Read only; 7109 7110 'w' 7111 Write only; 7112 7113 'r|w' 7114 Read and write. 7115 7116 For example: 7117 .extAuxRegister mulhi, 0x12, w 7118 specifies a write only extension auxiliary register, MULHI at 7119 address 0x12. 7120 7121'.extCondCode SUFFIX, VAL' 7122 ARC supports extensible condition codes. This directive defines a 7123 new condition code, to be known by the suffix, SUFFIX and will 7124 depend on the value, VAL in the condition code. 7125 7126 For example: 7127 .extCondCode is_busy,0x14 7128 add.is_busy r1,r2,r3 7129 will only execute the 'add' instruction if the condition code value 7130 is 0x14. 7131 7132'.extCoreRegister NAME, REGNUM, MODE, SHORTCUT' 7133 Specifies an extension core register named NAME as a synonym for 7134 the register numbered REGNUM. The register number must be between 7135 32 and 59. The third argument, MODE, indicates whether the 7136 register is readable and/or writable and is one of: 7137 'r' 7138 Read only; 7139 7140 'w' 7141 Write only; 7142 7143 'r|w' 7144 Read and write. 7145 7146 The final parameter, SHORTCUT indicates whether the register has a 7147 short cut in the pipeline. The valid values are: 7148 'can_shortcut' 7149 The register has a short cut in the pipeline; 7150 7151 'cannot_shortcut' 7152 The register does not have a short cut in the pipeline. 7153 7154 For example: 7155 .extCoreRegister mlo, 57, r , can_shortcut 7156 defines a read only extension core register, 'mlo', which is 7157 register 57, and can short cut the pipeline. 7158 7159'.extInstruction NAME, OPCODE, SUBOPCODE, SUFFIXCLASS, SYNTAXCLASS' 7160 ARC allows the user to specify extension instructions. These 7161 extension instructions are not macros; the assembler creates 7162 encodings for use of these instructions according to the 7163 specification by the user. 7164 7165 The first argument, NAME, gives the name of the instruction. 7166 7167 The second argument, OPCODE, is the opcode to be used (bits 31:27 7168 in the encoding). 7169 7170 The third argument, SUBOPCODE, is the sub-opcode to be used, but 7171 the correct value also depends on the fifth argument, SYNTAXCLASS 7172 7173 The fourth argument, SUFFIXCLASS, determines the kinds of suffixes 7174 to be allowed. Valid values are: 7175 'SUFFIX_NONE' 7176 No suffixes are permitted; 7177 7178 'SUFFIX_COND' 7179 Conditional suffixes are permitted; 7180 7181 'SUFFIX_FLAG' 7182 Flag setting suffixes are permitted. 7183 7184 'SUFFIX_COND|SUFFIX_FLAG' 7185 Both conditional and flag setting suffices are permitted. 7186 7187 The fifth and final argument, SYNTAXCLASS, determines the syntax 7188 class for the instruction. It can have the following values: 7189 'SYNTAX_2OP' 7190 Two Operand Instruction; 7191 7192 'SYNTAX_3OP' 7193 Three Operand Instruction. 7194 7195 'SYNTAX_1OP' 7196 One Operand Instruction. 7197 7198 'SYNTAX_NOP' 7199 No Operand Instruction. 7200 7201 The syntax class may be followed by '|' and one of the following 7202 modifiers. 7203 7204 'OP1_MUST_BE_IMM' 7205 Modifies syntax class 'SYNTAX_3OP', specifying that the first 7206 operand of a three-operand instruction must be an immediate 7207 (i.e., the result is discarded). This is usually used to set 7208 the flags using specific instructions and not retain results. 7209 7210 'OP1_IMM_IMPLIED' 7211 Modifies syntax class 'SYNTAX_20P', specifying that there is 7212 an implied immediate destination operand which does not appear 7213 in the syntax. 7214 7215 For example, if the source code contains an instruction like: 7216 inst r1,r2 7217 the first argument is an implied immediate (that is, the 7218 result is discarded). This is the same as though the source 7219 code were: inst 0,r1,r2. 7220 7221 For example, defining a 64-bit multiplier with immediate operands: 7222 .extInstruction mp64, 0x07, 0x2d, SUFFIX_COND|SUFFIX_FLAG, 7223 SYNTAX_3OP|OP1_MUST_BE_IMM 7224 which specifies an extension instruction named 'mp64' with 3 7225 operands. It sets the flags and can be used with a condition code, 7226 for which the first operand is an immediate, i.e. equivalent to 7227 discarding the result of the operation. 7228 7229 A two operands instruction variant would be: 7230 .extInstruction mul64, 0x07, 0x2d, SUFFIX_COND, 7231 SYNTAX_2OP|OP1_IMM_IMPLIED 7232 which describes a two operand instruction with an implicit first 7233 immediate operand. The result of this operation would be 7234 discarded. 7235 7236 7237File: as.info, Node: ARC Modifiers, Next: ARC Symbols, Prev: ARC Directives, Up: ARC-Dependent 7238 72399.3.4 ARC Assembler Modifiers 7240----------------------------- 7241 7242The following additional assembler modifiers have been added for 7243position-independent code. These modifiers are available only with the 7244ARC 700 and above processors and generate relocation entries, which are 7245interpreted by the linker as follows: 7246 7247'@pcl(SYMBOL)' 7248 Relative distance of SYMBOL's from the current program counter 7249 location. 7250 7251'@gotpc(SYMBOL)' 7252 Relative distance of SYMBOL's Global Offset Table entry from the 7253 current program counter location. 7254 7255'@gotoff(SYMBOL)' 7256 Distance of SYMBOL from the base of the Global Offset Table. 7257 7258'@plt(SYMBOL)' 7259 Distance of SYMBOL's Procedure Linkage Table entry from the current 7260 program counter. This is valid only with branch and link 7261 instructions and PC-relative calls. 7262 7263'@sda(SYMBOL)' 7264 Relative distance of SYMBOL from the base of the Small Data 7265 Pointer. 7266 7267 7268File: as.info, Node: ARC Symbols, Next: ARC Opcodes, Prev: ARC Modifiers, Up: ARC-Dependent 7269 72709.3.5 ARC Pre-defined Symbols 7271----------------------------- 7272 7273The following assembler symbols will prove useful when developing 7274position-independent code. These symbols are available only with the 7275ARC 700 and above processors. 7276 7277'__GLOBAL_OFFSET_TABLE__' 7278 Symbol referring to the base of the Global Offset Table. 7279 7280'__DYNAMIC__' 7281 An alias for the Global Offset Table 'Base__GLOBAL_OFFSET_TABLE__'. 7282 It can be used only with '@gotpc' modifiers. 7283 7284 7285File: as.info, Node: ARC Opcodes, Prev: ARC Symbols, Up: ARC-Dependent 7286 72879.3.6 Opcodes 7288------------- 7289 7290For information on the ARC instruction set, see 'ARC Programmers 7291Reference Manual', available where you download the processor IP 7292library. 7293 7294 7295File: as.info, Node: ARM-Dependent, Next: AVR-Dependent, Prev: ARC-Dependent, Up: Machine Dependencies 7296 72979.4 ARM Dependent Features 7298========================== 7299 7300* Menu: 7301 7302* ARM Options:: Options 7303* ARM Syntax:: Syntax 7304* ARM Floating Point:: Floating Point 7305* ARM Directives:: ARM Machine Directives 7306* ARM Opcodes:: Opcodes 7307* ARM Mapping Symbols:: Mapping Symbols 7308* ARM Unwinding Tutorial:: Unwinding 7309 7310 7311File: as.info, Node: ARM Options, Next: ARM Syntax, Up: ARM-Dependent 7312 73139.4.1 Options 7314------------- 7315 7316'-mcpu=PROCESSOR[+EXTENSION...]' 7317 This option specifies the target processor. The assembler will 7318 issue an error message if an attempt is made to assemble an 7319 instruction which will not execute on the target processor. The 7320 following processor names are recognized: 'arm1', 'arm2', 'arm250', 7321 'arm3', 'arm6', 'arm60', 'arm600', 'arm610', 'arm620', 'arm7', 7322 'arm7m', 'arm7d', 'arm7dm', 'arm7di', 'arm7dmi', 'arm70', 'arm700', 7323 'arm700i', 'arm710', 'arm710t', 'arm720', 'arm720t', 'arm740t', 7324 'arm710c', 'arm7100', 'arm7500', 'arm7500fe', 'arm7t', 'arm7tdmi', 7325 'arm7tdmi-s', 'arm8', 'arm810', 'strongarm', 'strongarm1', 7326 'strongarm110', 'strongarm1100', 'strongarm1110', 'arm9', 'arm920', 7327 'arm920t', 'arm922t', 'arm940t', 'arm9tdmi', 'fa526' (Faraday FA526 7328 processor), 'fa626' (Faraday FA626 processor), 'arm9e', 'arm926e', 7329 'arm926ej-s', 'arm946e-r0', 'arm946e', 'arm946e-s', 'arm966e-r0', 7330 'arm966e', 'arm966e-s', 'arm968e-s', 'arm10t', 'arm10tdmi', 7331 'arm10e', 'arm1020', 'arm1020t', 'arm1020e', 'arm1022e', 7332 'arm1026ej-s', 'fa606te' (Faraday FA606TE processor), 'fa616te' 7333 (Faraday FA616TE processor), 'fa626te' (Faraday FA626TE processor), 7334 'fmp626' (Faraday FMP626 processor), 'fa726te' (Faraday FA726TE 7335 processor), 'arm1136j-s', 'arm1136jf-s', 'arm1156t2-s', 7336 'arm1156t2f-s', 'arm1176jz-s', 'arm1176jzf-s', 'mpcore', 7337 'mpcorenovfp', 'cortex-a5', 'cortex-a7', 'cortex-a8', 'cortex-a9', 7338 'cortex-a15', 'cortex-a17', 'cortex-a32', 'cortex-a35', 7339 'cortex-a53', 'cortex-a57', 'cortex-a72', 'cortex-a73', 7340 'cortex-r4', 'cortex-r4f', 'cortex-r5', 'cortex-r7', 'cortex-r8', 7341 'cortex-m33', 'cortex-m23', 'cortex-m7', 'cortex-m4', 'cortex-m3', 7342 'cortex-m1', 'cortex-m0', 'cortex-m0plus', 'exynos-m1', 7343 'marvell-pj4', 'marvell-whitney', 'falkor', 'qdf24xx', 'xgene1', 7344 'xgene2', 'ep9312' (ARM920 with Cirrus Maverick coprocessor), 7345 'i80200' (Intel XScale processor) 'iwmmxt' (Intel(r) XScale 7346 processor with Wireless MMX(tm) technology coprocessor) and 7347 'xscale'. The special name 'all' may be used to allow the 7348 assembler to accept instructions valid for any ARM processor. 7349 7350 In addition to the basic instruction set, the assembler can be told 7351 to accept various extension mnemonics that extend the processor 7352 using the co-processor instruction space. For example, 7353 '-mcpu=arm920+maverick' is equivalent to specifying '-mcpu=ep9312'. 7354 7355 Multiple extensions may be specified, separated by a '+'. The 7356 extensions should be specified in ascending alphabetical order. 7357 7358 Some extensions may be restricted to particular architectures; this 7359 is documented in the list of extensions below. 7360 7361 Extension mnemonics may also be removed from those the assembler 7362 accepts. This is done be prepending 'no' to the option that adds 7363 the extension. Extensions that are removed should be listed after 7364 all extensions which have been added, again in ascending 7365 alphabetical order. For example, '-mcpu=ep9312+nomaverick' is 7366 equivalent to specifying '-mcpu=arm920'. 7367 7368 The following extensions are currently supported: 'crc' 'crypto' 7369 (Cryptography Extensions for v8-A architecture, implies 'fp+simd'), 7370 'fp' (Floating Point Extensions for v8-A architecture), 'idiv' 7371 (Integer Divide Extensions for v7-A and v7-R architectures), 7372 'iwmmxt', 'iwmmxt2', 'xscale', 'maverick', 'mp' (Multiprocessing 7373 Extensions for v7-A and v7-R architectures), 'os' (Operating System 7374 for v6M architecture), 'sec' (Security Extensions for v6K and v7-A 7375 architectures), 'simd' (Advanced SIMD Extensions for v8-A 7376 architecture, implies 'fp'), 'virt' (Virtualization Extensions for 7377 v7-A architecture, implies 'idiv'), 'pan' (Priviliged Access Never 7378 Extensions for v8-A architecture), 'ras' (Reliability, Availability 7379 and Serviceability extensions for v8-A architecture), 'rdma' 7380 (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies 7381 'simd') and 'xscale'. 7382 7383'-march=ARCHITECTURE[+EXTENSION...]' 7384 This option specifies the target architecture. The assembler will 7385 issue an error message if an attempt is made to assemble an 7386 instruction which will not execute on the target architecture. The 7387 following architecture names are recognized: 'armv1', 'armv2', 7388 'armv2a', 'armv2s', 'armv3', 'armv3m', 'armv4', 'armv4xm', 7389 'armv4t', 'armv4txm', 'armv5', 'armv5t', 'armv5txm', 'armv5te', 7390 'armv5texp', 'armv6', 'armv6j', 'armv6k', 'armv6z', 'armv6kz', 7391 'armv6-m', 'armv6s-m', 'armv7', 'armv7-a', 'armv7ve', 'armv7-r', 7392 'armv7-m', 'armv7e-m', 'armv8-a', 'armv8.1-a', 'armv8.2-a', 7393 'armv8.3-a', 'iwmmxt' 'iwmmxt2' and 'xscale'. If both '-mcpu' and 7394 '-march' are specified, the assembler will use the setting for 7395 '-mcpu'. 7396 7397 The architecture option can be extended with the same instruction 7398 set extension options as the '-mcpu' option. 7399 7400'-mfpu=FLOATING-POINT-FORMAT' 7401 7402 This option specifies the floating point format to assemble for. 7403 The assembler will issue an error message if an attempt is made to 7404 assemble an instruction which will not execute on the target 7405 floating point unit. The following format options are recognized: 7406 'softfpa', 'fpe', 'fpe2', 'fpe3', 'fpa', 'fpa10', 'fpa11', 7407 'arm7500fe', 'softvfp', 'softvfp+vfp', 'vfp', 'vfp10', 'vfp10-r0', 7408 'vfp9', 'vfpxd', 'vfpv2', 'vfpv3', 'vfpv3-fp16', 'vfpv3-d16', 7409 'vfpv3-d16-fp16', 'vfpv3xd', 'vfpv3xd-d16', 'vfpv4', 'vfpv4-d16', 7410 'fpv4-sp-d16', 'fpv5-sp-d16', 'fpv5-d16', 'fp-armv8', 'arm1020t', 7411 'arm1020e', 'arm1136jf-s', 'maverick', 'neon', 'neon-vfpv4', 7412 'neon-fp-armv8', 'crypto-neon-fp-armv8', 'neon-fp-armv8.1' and 7413 'crypto-neon-fp-armv8.1'. 7414 7415 In addition to determining which instructions are assembled, this 7416 option also affects the way in which the '.double' assembler 7417 directive behaves when assembling little-endian code. 7418 7419 The default is dependent on the processor selected. For 7420 Architecture 5 or later, the default is to assembler for VFP 7421 instructions; for earlier architectures the default is to assemble 7422 for FPA instructions. 7423 7424'-mthumb' 7425 This option specifies that the assembler should start assembling 7426 Thumb instructions; that is, it should behave as though the file 7427 starts with a '.code 16' directive. 7428 7429'-mthumb-interwork' 7430 This option specifies that the output generated by the assembler 7431 should be marked as supporting interworking. 7432 7433'-mimplicit-it=never' 7434'-mimplicit-it=always' 7435'-mimplicit-it=arm' 7436'-mimplicit-it=thumb' 7437 The '-mimplicit-it' option controls the behavior of the assembler 7438 when conditional instructions are not enclosed in IT blocks. There 7439 are four possible behaviors. If 'never' is specified, such 7440 constructs cause a warning in ARM code and an error in Thumb-2 7441 code. If 'always' is specified, such constructs are accepted in 7442 both ARM and Thumb-2 code, where the IT instruction is added 7443 implicitly. If 'arm' is specified, such constructs are accepted in 7444 ARM code and cause an error in Thumb-2 code. If 'thumb' is 7445 specified, such constructs cause a warning in ARM code and are 7446 accepted in Thumb-2 code. If you omit this option, the behavior is 7447 equivalent to '-mimplicit-it=arm'. 7448 7449'-mapcs-26' 7450'-mapcs-32' 7451 These options specify that the output generated by the assembler 7452 should be marked as supporting the indicated version of the Arm 7453 Procedure. Calling Standard. 7454 7455'-matpcs' 7456 This option specifies that the output generated by the assembler 7457 should be marked as supporting the Arm/Thumb Procedure Calling 7458 Standard. If enabled this option will cause the assembler to 7459 create an empty debugging section in the object file called 7460 .arm.atpcs. Debuggers can use this to determine the ABI being used 7461 by. 7462 7463'-mapcs-float' 7464 This indicates the floating point variant of the APCS should be 7465 used. In this variant floating point arguments are passed in FP 7466 registers rather than integer registers. 7467 7468'-mapcs-reentrant' 7469 This indicates that the reentrant variant of the APCS should be 7470 used. This variant supports position independent code. 7471 7472'-mfloat-abi=ABI' 7473 This option specifies that the output generated by the assembler 7474 should be marked as using specified floating point ABI. The 7475 following values are recognized: 'soft', 'softfp' and 'hard'. 7476 7477'-meabi=VER' 7478 This option specifies which EABI version the produced object files 7479 should conform to. The following values are recognized: 'gnu', '4' 7480 and '5'. 7481 7482'-EB' 7483 This option specifies that the output generated by the assembler 7484 should be marked as being encoded for a big-endian processor. 7485 7486 Note: If a program is being built for a system with big-endian data 7487 and little-endian instructions then it should be assembled with the 7488 '-EB' option, (all of it, code and data) and then linked with the 7489 '--be8' option. This will reverse the endianness of the 7490 instructions back to little-endian, but leave the data as 7491 big-endian. 7492 7493'-EL' 7494 This option specifies that the output generated by the assembler 7495 should be marked as being encoded for a little-endian processor. 7496 7497'-k' 7498 This option specifies that the output of the assembler should be 7499 marked as position-independent code (PIC). 7500 7501'--fix-v4bx' 7502 Allow 'BX' instructions in ARMv4 code. This is intended for use 7503 with the linker option of the same name. 7504 7505'-mwarn-deprecated' 7506'-mno-warn-deprecated' 7507 Enable or disable warnings about using deprecated options or 7508 features. The default is to warn. 7509 7510'-mccs' 7511 Turns on CodeComposer Studio assembly syntax compatibility mode. 7512 7513'-mwarn-syms' 7514'-mno-warn-syms' 7515 Enable or disable warnings about symbols that match the names of 7516 ARM instructions. The default is to warn. 7517 7518 7519File: as.info, Node: ARM Syntax, Next: ARM Floating Point, Prev: ARM Options, Up: ARM-Dependent 7520 75219.4.2 Syntax 7522------------ 7523 7524* Menu: 7525 7526* ARM-Instruction-Set:: Instruction Set 7527* ARM-Chars:: Special Characters 7528* ARM-Regs:: Register Names 7529* ARM-Relocations:: Relocations 7530* ARM-Neon-Alignment:: NEON Alignment Specifiers 7531 7532 7533File: as.info, Node: ARM-Instruction-Set, Next: ARM-Chars, Up: ARM Syntax 7534 75359.4.2.1 Instruction Set Syntax 7536.............................. 7537 7538Two slightly different syntaxes are support for ARM and THUMB 7539instructions. The default, 'divided', uses the old style where ARM and 7540THUMB instructions had their own, separate syntaxes. The new, 'unified' 7541syntax, which can be selected via the '.syntax' directive, and has the 7542following main features: 7543 7544 * Immediate operands do not require a '#' prefix. 7545 7546 * The 'IT' instruction may appear, and if it does it is validated 7547 against subsequent conditional affixes. In ARM mode it does not 7548 generate machine code, in THUMB mode it does. 7549 7550 * For ARM instructions the conditional affixes always appear at the 7551 end of the instruction. For THUMB instructions conditional affixes 7552 can be used, but only inside the scope of an 'IT' instruction. 7553 7554 * All of the instructions new to the V6T2 architecture (and later) 7555 are available. (Only a few such instructions can be written in the 7556 'divided' syntax). 7557 7558 * The '.N' and '.W' suffixes are recognized and honored. 7559 7560 * All instructions set the flags if and only if they have an 's' 7561 affix. 7562 7563 7564File: as.info, Node: ARM-Chars, Next: ARM-Regs, Prev: ARM-Instruction-Set, Up: ARM Syntax 7565 75669.4.2.2 Special Characters 7567.......................... 7568 7569The presence of a '@' anywhere on a line indicates the start of a 7570comment that extends to the end of that line. 7571 7572 If a '#' appears as the first character of a line then the whole line 7573is treated as a comment, but in this case the line could also be a 7574logical line number directive (*note Comments::) or a preprocessor 7575control command (*note Preprocessing::). 7576 7577 The ';' character can be used instead of a newline to separate 7578statements. 7579 7580 Either '#' or '$' can be used to indicate immediate operands. 7581 7582 *TODO* Explain about /data modifier on symbols. 7583 7584 7585File: as.info, Node: ARM-Regs, Next: ARM-Relocations, Prev: ARM-Chars, Up: ARM Syntax 7586 75879.4.2.3 Register Names 7588...................... 7589 7590*TODO* Explain about ARM register naming, and the predefined names. 7591 7592 7593File: as.info, Node: ARM-Relocations, Next: ARM-Neon-Alignment, Prev: ARM-Regs, Up: ARM Syntax 7594 75959.4.2.4 ARM relocation generation 7596................................. 7597 7598Specific data relocations can be generated by putting the relocation 7599name in parentheses after the symbol name. For example: 7600 7601 .word foo(TARGET1) 7602 7603 This will generate an 'R_ARM_TARGET1' relocation against the symbol 7604FOO. The following relocations are supported: 'GOT', 'GOTOFF', 7605'TARGET1', 'TARGET2', 'SBREL', 'TLSGD', 'TLSLDM', 'TLSLDO', 'TLSDESC', 7606'TLSCALL', 'GOTTPOFF', 'GOT_PREL' and 'TPOFF'. 7607 7608 For compatibility with older toolchains the assembler also accepts 7609'(PLT)' after branch targets. On legacy targets this will generate the 7610deprecated 'R_ARM_PLT32' relocation. On EABI targets it will encode 7611either the 'R_ARM_CALL' or 'R_ARM_JUMP24' relocation, as appropriate. 7612 7613 Relocations for 'MOVW' and 'MOVT' instructions can be generated by 7614prefixing the value with '#:lower16:' and '#:upper16' respectively. For 7615example to load the 32-bit address of foo into r0: 7616 7617 MOVW r0, #:lower16:foo 7618 MOVT r0, #:upper16:foo 7619 7620 Relocations 'R_ARM_THM_ALU_ABS_G0_NC', 'R_ARM_THM_ALU_ABS_G1_NC', 7621'R_ARM_THM_ALU_ABS_G2_NC' and 'R_ARM_THM_ALU_ABS_G3_NC' can be generated 7622by prefixing the value with '#:lower0_7:#', '#:lower8_15:#', 7623'#:upper0_7:#' and '#:upper8_15:#' respectively. For example to load 7624the 32-bit address of foo into r0: 7625 7626 MOVS r0, #:upper8_15:#foo 7627 LSLS r0, r0, #8 7628 ADDS r0, #:upper0_7:#foo 7629 LSLS r0, r0, #8 7630 ADDS r0, #:lower8_15:#foo 7631 LSLS r0, r0, #8 7632 ADDS r0, #:lower0_7:#foo 7633 7634 7635File: as.info, Node: ARM-Neon-Alignment, Prev: ARM-Relocations, Up: ARM Syntax 7636 76379.4.2.5 NEON Alignment Specifiers 7638................................. 7639 7640Some NEON load/store instructions allow an optional address alignment 7641qualifier. The ARM documentation specifies that this is indicated by '@ 7642ALIGN'. However GAS already interprets the '@' character as a "line 7643comment" start, so ': ALIGN' is used instead. For example: 7644 7645 vld1.8 {q0}, [r0, :128] 7646 7647 7648File: as.info, Node: ARM Floating Point, Next: ARM Directives, Prev: ARM Syntax, Up: ARM-Dependent 7649 76509.4.3 Floating Point 7651-------------------- 7652 7653The ARM family uses IEEE floating-point numbers. 7654 7655 7656File: as.info, Node: ARM Directives, Next: ARM Opcodes, Prev: ARM Floating Point, Up: ARM-Dependent 7657 76589.4.4 ARM Machine Directives 7659---------------------------- 7660 7661'.2byte EXPRESSION [, EXPRESSION]*' 7662'.4byte EXPRESSION [, EXPRESSION]*' 7663'.8byte EXPRESSION [, EXPRESSION]*' 7664 These directives write 2, 4 or 8 byte values to the output section. 7665 7666'.align EXPRESSION [, EXPRESSION]' 7667 This is the generic .ALIGN directive. For the ARM however if the 7668 first argument is zero (ie no alignment is needed) the assembler 7669 will behave as if the argument had been 2 (ie pad to the next four 7670 byte boundary). This is for compatibility with ARM's own 7671 assembler. 7672 7673'.arch NAME' 7674 Select the target architecture. Valid values for NAME are the same 7675 as for the '-march' commandline option. 7676 7677 Specifying '.arch' clears any previously selected architecture 7678 extensions. 7679 7680'.arch_extension NAME' 7681 Add or remove an architecture extension to the target architecture. 7682 Valid values for NAME are the same as those accepted as 7683 architectural extensions by the '-mcpu' commandline option. 7684 7685 '.arch_extension' may be used multiple times to add or remove 7686 extensions incrementally to the architecture being compiled for. 7687 7688'.arm' 7689 This performs the same action as .CODE 32. 7690 7691'.bss' 7692 This directive switches to the '.bss' section. 7693 7694'.cantunwind' 7695 Prevents unwinding through the current function. No personality 7696 routine or exception table data is required or permitted. 7697 7698'.code [16|32]' 7699 This directive selects the instruction set being generated. The 7700 value 16 selects Thumb, with the value 32 selecting ARM. 7701 7702'.cpu NAME' 7703 Select the target processor. Valid values for NAME are the same as 7704 for the '-mcpu' commandline option. 7705 7706 Specifying '.cpu' clears any previously selected architecture 7707 extensions. 7708 7709'NAME .dn REGISTER NAME [.TYPE] [[INDEX]]' 7710'NAME .qn REGISTER NAME [.TYPE] [[INDEX]]' 7711 7712 The 'dn' and 'qn' directives are used to create typed and/or 7713 indexed register aliases for use in Advanced SIMD Extension (Neon) 7714 instructions. The former should be used to create aliases of 7715 double-precision registers, and the latter to create aliases of 7716 quad-precision registers. 7717 7718 If these directives are used to create typed aliases, those aliases 7719 can be used in Neon instructions instead of writing types after the 7720 mnemonic or after each operand. For example: 7721 7722 x .dn d2.f32 7723 y .dn d3.f32 7724 z .dn d4.f32[1] 7725 vmul x,y,z 7726 7727 This is equivalent to writing the following: 7728 7729 vmul.f32 d2,d3,d4[1] 7730 7731 Aliases created using 'dn' or 'qn' can be destroyed using 'unreq'. 7732 7733'.eabi_attribute TAG, VALUE' 7734 Set the EABI object attribute TAG to VALUE. 7735 7736 The TAG is either an attribute number, or one of the following: 7737 'Tag_CPU_raw_name', 'Tag_CPU_name', 'Tag_CPU_arch', 7738 'Tag_CPU_arch_profile', 'Tag_ARM_ISA_use', 'Tag_THUMB_ISA_use', 7739 'Tag_FP_arch', 'Tag_WMMX_arch', 'Tag_Advanced_SIMD_arch', 7740 'Tag_PCS_config', 'Tag_ABI_PCS_R9_use', 'Tag_ABI_PCS_RW_data', 7741 'Tag_ABI_PCS_RO_data', 'Tag_ABI_PCS_GOT_use', 7742 'Tag_ABI_PCS_wchar_t', 'Tag_ABI_FP_rounding', 7743 'Tag_ABI_FP_denormal', 'Tag_ABI_FP_exceptions', 7744 'Tag_ABI_FP_user_exceptions', 'Tag_ABI_FP_number_model', 7745 'Tag_ABI_align_needed', 'Tag_ABI_align_preserved', 7746 'Tag_ABI_enum_size', 'Tag_ABI_HardFP_use', 'Tag_ABI_VFP_args', 7747 'Tag_ABI_WMMX_args', 'Tag_ABI_optimization_goals', 7748 'Tag_ABI_FP_optimization_goals', 'Tag_compatibility', 7749 'Tag_CPU_unaligned_access', 'Tag_FP_HP_extension', 7750 'Tag_ABI_FP_16bit_format', 'Tag_MPextension_use', 'Tag_DIV_use', 7751 'Tag_nodefaults', 'Tag_also_compatible_with', 'Tag_conformance', 7752 'Tag_T2EE_use', 'Tag_Virtualization_use' 7753 7754 The VALUE is either a 'number', '"string"', or 'number, "string"' 7755 depending on the tag. 7756 7757 Note - the following legacy values are also accepted by TAG: 7758 'Tag_VFP_arch', 'Tag_ABI_align8_needed', 7759 'Tag_ABI_align8_preserved', 'Tag_VFP_HP_extension', 7760 7761'.even' 7762 This directive aligns to an even-numbered address. 7763 7764'.extend EXPRESSION [, EXPRESSION]*' 7765'.ldouble EXPRESSION [, EXPRESSION]*' 7766 These directives write 12byte long double floating-point values to 7767 the output section. These are not compatible with current ARM 7768 processors or ABIs. 7769 7770'.fnend' 7771 Marks the end of a function with an unwind table entry. The unwind 7772 index table entry is created when this directive is processed. 7773 7774 If no personality routine has been specified then standard 7775 personality routine 0 or 1 will be used, depending on the number of 7776 unwind opcodes required. 7777 7778'.fnstart' 7779 Marks the start of a function with an unwind table entry. 7780 7781'.force_thumb' 7782 This directive forces the selection of Thumb instructions, even if 7783 the target processor does not support those instructions 7784 7785'.fpu NAME' 7786 Select the floating-point unit to assemble for. Valid values for 7787 NAME are the same as for the '-mfpu' commandline option. 7788 7789'.handlerdata' 7790 Marks the end of the current function, and the start of the 7791 exception table entry for that function. Anything between this 7792 directive and the '.fnend' directive will be added to the exception 7793 table entry. 7794 7795 Must be preceded by a '.personality' or '.personalityindex' 7796 directive. 7797 7798'.inst OPCODE [ , ... ]' 7799'.inst.n OPCODE [ , ... ]' 7800'.inst.w OPCODE [ , ... ]' 7801 Generates the instruction corresponding to the numerical value 7802 OPCODE. '.inst.n' and '.inst.w' allow the Thumb instruction size 7803 to be specified explicitly, overriding the normal encoding rules. 7804 7805'.ldouble EXPRESSION [, EXPRESSION]*' 7806 See '.extend'. 7807 7808'.ltorg' 7809 This directive causes the current contents of the literal pool to 7810 be dumped into the current section (which is assumed to be the 7811 .text section) at the current location (aligned to a word 7812 boundary). 'GAS' maintains a separate literal pool for each 7813 section and each sub-section. The '.ltorg' directive will only 7814 affect the literal pool of the current section and sub-section. At 7815 the end of assembly all remaining, un-empty literal pools will 7816 automatically be dumped. 7817 7818 Note - older versions of 'GAS' would dump the current literal pool 7819 any time a section change occurred. This is no longer done, since 7820 it prevents accurate control of the placement of literal pools. 7821 7822'.movsp REG [, #OFFSET]' 7823 Tell the unwinder that REG contains an offset from the current 7824 stack pointer. If OFFSET is not specified then it is assumed to be 7825 zero. 7826 7827'.object_arch NAME' 7828 Override the architecture recorded in the EABI object attribute 7829 section. Valid values for NAME are the same as for the '.arch' 7830 directive. Typically this is useful when code uses runtime 7831 detection of CPU features. 7832 7833'.packed EXPRESSION [, EXPRESSION]*' 7834 This directive writes 12-byte packed floating-point values to the 7835 output section. These are not compatible with current ARM 7836 processors or ABIs. 7837 7838'.pad #COUNT' 7839 Generate unwinder annotations for a stack adjustment of COUNT 7840 bytes. A positive value indicates the function prologue allocated 7841 stack space by decrementing the stack pointer. 7842 7843'.personality NAME' 7844 Sets the personality routine for the current function to NAME. 7845 7846'.personalityindex INDEX' 7847 Sets the personality routine for the current function to the EABI 7848 standard routine number INDEX 7849 7850'.pool' 7851 This is a synonym for .ltorg. 7852 7853'NAME .req REGISTER NAME' 7854 This creates an alias for REGISTER NAME called NAME. For example: 7855 7856 foo .req r0 7857 7858'.save REGLIST' 7859 Generate unwinder annotations to restore the registers in REGLIST. 7860 The format of REGLIST is the same as the corresponding 7861 store-multiple instruction. 7862 7863 _core registers_ 7864 .save {r4, r5, r6, lr} 7865 stmfd sp!, {r4, r5, r6, lr} 7866 _FPA registers_ 7867 .save f4, 2 7868 sfmfd f4, 2, [sp]! 7869 _VFP registers_ 7870 .save {d8, d9, d10} 7871 fstmdx sp!, {d8, d9, d10} 7872 _iWMMXt registers_ 7873 .save {wr10, wr11} 7874 wstrd wr11, [sp, #-8]! 7875 wstrd wr10, [sp, #-8]! 7876 or 7877 .save wr11 7878 wstrd wr11, [sp, #-8]! 7879 .save wr10 7880 wstrd wr10, [sp, #-8]! 7881 7882'.setfp FPREG, SPREG [, #OFFSET]' 7883 Make all unwinder annotations relative to a frame pointer. Without 7884 this the unwinder will use offsets from the stack pointer. 7885 7886 The syntax of this directive is the same as the 'add' or 'mov' 7887 instruction used to set the frame pointer. SPREG must be either 7888 'sp' or mentioned in a previous '.movsp' directive. 7889 7890 .movsp ip 7891 mov ip, sp 7892 ... 7893 .setfp fp, ip, #4 7894 add fp, ip, #4 7895 7896'.secrel32 EXPRESSION [, EXPRESSION]*' 7897 This directive emits relocations that evaluate to the 7898 section-relative offset of each expression's symbol. This 7899 directive is only supported for PE targets. 7900 7901'.syntax [unified | divided]' 7902 This directive sets the Instruction Set Syntax as described in the 7903 *note ARM-Instruction-Set:: section. 7904 7905'.thumb' 7906 This performs the same action as .CODE 16. 7907 7908'.thumb_func' 7909 This directive specifies that the following symbol is the name of a 7910 Thumb encoded function. This information is necessary in order to 7911 allow the assembler and linker to generate correct code for 7912 interworking between Arm and Thumb instructions and should be used 7913 even if interworking is not going to be performed. The presence of 7914 this directive also implies '.thumb' 7915 7916 This directive is not neccessary when generating EABI objects. On 7917 these targets the encoding is implicit when generating Thumb code. 7918 7919'.thumb_set' 7920 This performs the equivalent of a '.set' directive in that it 7921 creates a symbol which is an alias for another symbol (possibly not 7922 yet defined). This directive also has the added property in that 7923 it marks the aliased symbol as being a thumb function entry point, 7924 in the same way that the '.thumb_func' directive does. 7925 7926'.tlsdescseq TLS-VARIABLE' 7927 This directive is used to annotate parts of an inlined TLS 7928 descriptor trampoline. Normally the trampoline is provided by the 7929 linker, and this directive is not needed. 7930 7931'.unreq ALIAS-NAME' 7932 This undefines a register alias which was previously defined using 7933 the 'req', 'dn' or 'qn' directives. For example: 7934 7935 foo .req r0 7936 .unreq foo 7937 7938 An error occurs if the name is undefined. Note - this pseudo op 7939 can be used to delete builtin in register name aliases (eg 'r0'). 7940 This should only be done if it is really necessary. 7941 7942'.unwind_raw OFFSET, BYTE1, ...' 7943 Insert one of more arbitary unwind opcode bytes, which are known to 7944 adjust the stack pointer by OFFSET bytes. 7945 7946 For example '.unwind_raw 4, 0xb1, 0x01' is equivalent to '.save 7947 {r0}' 7948 7949'.vsave VFP-REGLIST' 7950 Generate unwinder annotations to restore the VFP registers in 7951 VFP-REGLIST using FLDMD. Also works for VFPv3 registers that are to 7952 be restored using VLDM. The format of VFP-REGLIST is the same as 7953 the corresponding store-multiple instruction. 7954 7955 _VFP registers_ 7956 .vsave {d8, d9, d10} 7957 fstmdd sp!, {d8, d9, d10} 7958 _VFPv3 registers_ 7959 .vsave {d15, d16, d17} 7960 vstm sp!, {d15, d16, d17} 7961 7962 Since FLDMX and FSTMX are now deprecated, this directive should be 7963 used in favour of '.save' for saving VFP registers for ARMv6 and 7964 above. 7965 7966 7967File: as.info, Node: ARM Opcodes, Next: ARM Mapping Symbols, Prev: ARM Directives, Up: ARM-Dependent 7968 79699.4.5 Opcodes 7970------------- 7971 7972'as' implements all the standard ARM opcodes. It also implements 7973several pseudo opcodes, including several synthetic load instructions. 7974 7975'NOP' 7976 nop 7977 7978 This pseudo op will always evaluate to a legal ARM instruction that 7979 does nothing. Currently it will evaluate to MOV r0, r0. 7980 7981'LDR' 7982 ldr <register> , = <expression> 7983 7984 If expression evaluates to a numeric constant then a MOV or MVN 7985 instruction will be used in place of the LDR instruction, if the 7986 constant can be generated by either of these instructions. 7987 Otherwise the constant will be placed into the nearest literal pool 7988 (if it not already there) and a PC relative LDR instruction will be 7989 generated. 7990 7991'ADR' 7992 adr <register> <label> 7993 7994 This instruction will load the address of LABEL into the indicated 7995 register. The instruction will evaluate to a PC relative ADD or 7996 SUB instruction depending upon where the label is located. If the 7997 label is out of range, or if it is not defined in the same file 7998 (and section) as the ADR instruction, then an error will be 7999 generated. This instruction will not make use of the literal pool. 8000 8001'ADRL' 8002 adrl <register> <label> 8003 8004 This instruction will load the address of LABEL into the indicated 8005 register. The instruction will evaluate to one or two PC relative 8006 ADD or SUB instructions depending upon where the label is located. 8007 If a second instruction is not needed a NOP instruction will be 8008 generated in its place, so that this instruction is always 8 bytes 8009 long. 8010 8011 If the label is out of range, or if it is not defined in the same 8012 file (and section) as the ADRL instruction, then an error will be 8013 generated. This instruction will not make use of the literal pool. 8014 8015 For information on the ARM or Thumb instruction sets, see 'ARM 8016Software Development Toolkit Reference Manual', Advanced RISC Machines 8017Ltd. 8018 8019 8020File: as.info, Node: ARM Mapping Symbols, Next: ARM Unwinding Tutorial, Prev: ARM Opcodes, Up: ARM-Dependent 8021 80229.4.6 Mapping Symbols 8023--------------------- 8024 8025The ARM ELF specification requires that special symbols be inserted into 8026object files to mark certain features: 8027 8028'$a' 8029 At the start of a region of code containing ARM instructions. 8030 8031'$t' 8032 At the start of a region of code containing THUMB instructions. 8033 8034'$d' 8035 At the start of a region of data. 8036 8037 The assembler will automatically insert these symbols for you - there 8038is no need to code them yourself. Support for tagging symbols ($b, $f, 8039$p and $m) which is also mentioned in the current ARM ELF specification 8040is not implemented. This is because they have been dropped from the new 8041EABI and so tools cannot rely upon their presence. 8042 8043 8044File: as.info, Node: ARM Unwinding Tutorial, Prev: ARM Mapping Symbols, Up: ARM-Dependent 8045 80469.4.7 Unwinding 8047--------------- 8048 8049The ABI for the ARM Architecture specifies a standard format for 8050exception unwind information. This information is used when an 8051exception is thrown to determine where control should be transferred. 8052In particular, the unwind information is used to determine which 8053function called the function that threw the exception, and which 8054function called that one, and so forth. This information is also used 8055to restore the values of callee-saved registers in the function catching 8056the exception. 8057 8058 If you are writing functions in assembly code, and those functions 8059call other functions that throw exceptions, you must use assembly pseudo 8060ops to ensure that appropriate exception unwind information is 8061generated. Otherwise, if one of the functions called by your assembly 8062code throws an exception, the run-time library will be unable to unwind 8063the stack through your assembly code and your program will not behave 8064correctly. 8065 8066 To illustrate the use of these pseudo ops, we will examine the code 8067that G++ generates for the following C++ input: 8068 8069void callee (int *); 8070 8071int 8072caller () 8073{ 8074 int i; 8075 callee (&i); 8076 return i; 8077} 8078 8079 This example does not show how to throw or catch an exception from 8080assembly code. That is a much more complex operation and should always 8081be done in a high-level language, such as C++, that directly supports 8082exceptions. 8083 8084 The code generated by one particular version of G++ when compiling 8085the example above is: 8086 8087_Z6callerv: 8088 .fnstart 8089.LFB2: 8090 @ Function supports interworking. 8091 @ args = 0, pretend = 0, frame = 8 8092 @ frame_needed = 1, uses_anonymous_args = 0 8093 stmfd sp!, {fp, lr} 8094 .save {fp, lr} 8095.LCFI0: 8096 .setfp fp, sp, #4 8097 add fp, sp, #4 8098.LCFI1: 8099 .pad #8 8100 sub sp, sp, #8 8101.LCFI2: 8102 sub r3, fp, #8 8103 mov r0, r3 8104 bl _Z6calleePi 8105 ldr r3, [fp, #-8] 8106 mov r0, r3 8107 sub sp, fp, #4 8108 ldmfd sp!, {fp, lr} 8109 bx lr 8110.LFE2: 8111 .fnend 8112 8113 Of course, the sequence of instructions varies based on the options 8114you pass to GCC and on the version of GCC in use. The exact 8115instructions are not important since we are focusing on the pseudo ops 8116that are used to generate unwind information. 8117 8118 An important assumption made by the unwinder is that the stack frame 8119does not change during the body of the function. In particular, since 8120we assume that the assembly code does not itself throw an exception, the 8121only point where an exception can be thrown is from a call, such as the 8122'bl' instruction above. At each call site, the same saved registers 8123(including 'lr', which indicates the return address) must be located in 8124the same locations relative to the frame pointer. 8125 8126 The '.fnstart' (*note .fnstart pseudo op: arm_fnstart.) pseudo op 8127appears immediately before the first instruction of the function while 8128the '.fnend' (*note .fnend pseudo op: arm_fnend.) pseudo op appears 8129immediately after the last instruction of the function. These pseudo 8130ops specify the range of the function. 8131 8132 Only the order of the other pseudos ops (e.g., '.setfp' or '.pad') 8133matters; their exact locations are irrelevant. In the example above, 8134the compiler emits the pseudo ops with particular instructions. That 8135makes it easier to understand the code, but it is not required for 8136correctness. It would work just as well to emit all of the pseudo ops 8137other than '.fnend' in the same order, but immediately after '.fnstart'. 8138 8139 The '.save' (*note .save pseudo op: arm_save.) pseudo op indicates 8140registers that have been saved to the stack so that they can be restored 8141before the function returns. The argument to the '.save' pseudo op is a 8142list of registers to save. If a register is "callee-saved" (as 8143specified by the ABI) and is modified by the function you are writing, 8144then your code must save the value before it is modified and restore the 8145original value before the function returns. If an exception is thrown, 8146the run-time library restores the values of these registers from their 8147locations on the stack before returning control to the exception 8148handler. (Of course, if an exception is not thrown, the function that 8149contains the '.save' pseudo op restores these registers in the function 8150epilogue, as is done with the 'ldmfd' instruction above.) 8151 8152 You do not have to save callee-saved registers at the very beginning 8153of the function and you do not need to use the '.save' pseudo op 8154immediately following the point at which the registers are saved. 8155However, if you modify a callee-saved register, you must save it on the 8156stack before modifying it and before calling any functions which might 8157throw an exception. And, you must use the '.save' pseudo op to indicate 8158that you have done so. 8159 8160 The '.pad' (*note .pad: arm_pad.) pseudo op indicates a modification 8161of the stack pointer that does not save any registers. The argument is 8162the number of bytes (in decimal) that are subtracted from the stack 8163pointer. (On ARM CPUs, the stack grows downwards, so subtracting from 8164the stack pointer increases the size of the stack.) 8165 8166 The '.setfp' (*note .setfp pseudo op: arm_setfp.) pseudo op indicates 8167the register that contains the frame pointer. The first argument is the 8168register that is set, which is typically 'fp'. The second argument 8169indicates the register from which the frame pointer takes its value. 8170The third argument, if present, is the value (in decimal) added to the 8171register specified by the second argument to compute the value of the 8172frame pointer. You should not modify the frame pointer in the body of 8173the function. 8174 8175 If you do not use a frame pointer, then you should not use the 8176'.setfp' pseudo op. If you do not use a frame pointer, then you should 8177avoid modifying the stack pointer outside of the function prologue. 8178Otherwise, the run-time library will be unable to find saved registers 8179when it is unwinding the stack. 8180 8181 The pseudo ops described above are sufficient for writing assembly 8182code that calls functions which may throw exceptions. If you need to 8183know more about the object-file format used to represent unwind 8184information, you may consult the 'Exception Handling ABI for the ARM 8185Architecture' available from <http://infocenter.arm.com>. 8186 8187 8188File: as.info, Node: AVR-Dependent, Next: Blackfin-Dependent, Prev: ARM-Dependent, Up: Machine Dependencies 8189 81909.5 AVR Dependent Features 8191========================== 8192 8193* Menu: 8194 8195* AVR Options:: Options 8196* AVR Syntax:: Syntax 8197* AVR Opcodes:: Opcodes 8198 8199 8200File: as.info, Node: AVR Options, Next: AVR Syntax, Up: AVR-Dependent 8201 82029.5.1 Options 8203------------- 8204 8205'-mmcu=MCU' 8206 Specify ATMEL AVR instruction set or MCU type. 8207 8208 Instruction set avr1 is for the minimal AVR core, not supported by 8209 the C compiler, only for assembler programs (MCU types: at90s1200, 8210 attiny11, attiny12, attiny15, attiny28). 8211 8212 Instruction set avr2 (default) is for the classic AVR core with up 8213 to 8K program memory space (MCU types: at90s2313, at90s2323, 8214 at90s2333, at90s2343, attiny22, attiny26, at90s4414, at90s4433, 8215 at90s4434, at90s8515, at90c8534, at90s8535). 8216 8217 Instruction set avr25 is for the classic AVR core with up to 8K 8218 program memory space plus the MOVW instruction (MCU types: 8219 attiny13, attiny13a, attiny2313, attiny2313a, attiny24, attiny24a, 8220 attiny4313, attiny44, attiny44a, attiny84, attiny84a, attiny25, 8221 attiny45, attiny85, attiny261, attiny261a, attiny461, attiny461a, 8222 attiny861, attiny861a, attiny87, attiny43u, attiny48, attiny88, 8223 attiny828, at86rf401, ata6289, ata5272). 8224 8225 Instruction set avr3 is for the classic AVR core with up to 128K 8226 program memory space (MCU types: at43usb355, at76c711). 8227 8228 Instruction set avr31 is for the classic AVR core with exactly 128K 8229 program memory space (MCU types: atmega103, at43usb320). 8230 8231 Instruction set avr35 is for classic AVR core plus MOVW, CALL, and 8232 JMP instructions (MCU types: attiny167, attiny1634, at90usb82, 8233 at90usb162, atmega8u2, atmega16u2, atmega32u2, ata5505). 8234 8235 Instruction set avr4 is for the enhanced AVR core with up to 8K 8236 program memory space (MCU types: atmega48, atmega48a, atmega48pa, 8237 atmega48p, atmega8, atmega8a, atmega88, atmega88a, atmega88p, 8238 atmega88pa, atmega8515, atmega8535, atmega8hva, at90pwm1, at90pwm2, 8239 at90pwm2b, at90pwm3, at90pwm3b, at90pwm81, ata6285, ata6286). 8240 8241 Instruction set avr5 is for the enhanced AVR core with up to 128K 8242 program memory space (MCU types: at90pwm161, atmega16, atmega16a, 8243 atmega161, atmega162, atmega163, atmega164a, atmega164p, 8244 atmega164pa, atmega165, atmega165a, atmega165p, atmega165pa, 8245 atmega168, atmega168a, atmega168p, atmega168pa, atmega169, 8246 atmega169a, atmega169p, atmega169pa, atmega32, atmega323, 8247 atmega324a, atmega324p, atmega324pa, atmega325, atmega325a, 8248 atmega32, atmega32a, atmega323, atmega324a, atmega324p, 8249 atmega324pa, atmega325, atmega325a, atmega325p, atmega325p, 8250 atmega325pa, atmega3250, atmega3250a, atmega3250p, atmega3250pa, 8251 atmega328, atmega328p, atmega329, atmega329a, atmega329p, 8252 atmega329pa, atmega3290a, atmega3290p, atmega3290pa, atmega406, 8253 atmega64, atmega64a, atmega64rfr2, atmega644rfr2, atmega640, 8254 atmega644, atmega644a, atmega644p, atmega644pa, atmega645, 8255 atmega645a, atmega645p, atmega6450, atmega6450a, atmega6450p, 8256 atmega649, atmega649a, atmega649p, atmega6490, atmega6490a, 8257 atmega6490p, atmega16hva, atmega16hva2, atmega16hvb, 8258 atmega16hvbrevb, atmega32hvb, atmega32hvbrevb, atmega64hve, 8259 at90can32, at90can64, at90pwm161, at90pwm216, at90pwm316, 8260 atmega32c1, atmega64c1, atmega16m1, atmega32m1, atmega64m1, 8261 atmega16u4, atmega32u4, atmega32u6, at90usb646, at90usb647, at94k, 8262 at90scr100, ata5790, ata5795). 8263 8264 Instruction set avr51 is for the enhanced AVR core with exactly 8265 128K program memory space (MCU types: atmega128, atmega128a, 8266 atmega1280, atmega1281, atmega1284, atmega1284p, atmega128rfa1, 8267 atmega128rfr2, atmega1284rfr2, at90can128, at90usb1286, 8268 at90usb1287, m3000). 8269 8270 Instruction set avr6 is for the enhanced AVR core with a 3-byte PC 8271 (MCU types: atmega2560, atmega2561, atmega256rfr2, atmega2564rfr2). 8272 8273 Instruction set avrxmega2 is for the XMEGA AVR core with 8K to 64K 8274 program memory space and less than 64K data space (MCU types: 8275 atxmega16a4, atxmega16a4u, atxmega16c4, atxmega16d4, atxmega16x1, 8276 atxmega32a4, atxmega32a4u, atxmega32c4, atxmega32d4, atxmega16e5, 8277 atxmega8e5, atxmega32e5, atxmega32x1). 8278 8279 Instruction set avrxmega3 is for the XMEGA AVR core with 8K to 64K 8280 program memory space and greater than 64K data space (MCU types: 8281 none). 8282 8283 Instruction set avrxmega4 is for the XMEGA AVR core with up to 64K 8284 program memory space and less than 64K data space (MCU types: 8285 atxmega64a3, atxmega64a3u, atxmega64a4u, atxmega64b1, atxmega64b3, 8286 atxmega64c3, atxmega64d3, atxmega64d4). 8287 8288 Instruction set avrxmega5 is for the XMEGA AVR core with up to 64K 8289 program memory space and greater than 64K data space (MCU types: 8290 atxmega64a1, atxmega64a1u). 8291 8292 Instruction set avrxmega6 is for the XMEGA AVR core with larger 8293 than 64K program memory space and less than 64K data space (MCU 8294 types: atxmega128a3, atxmega128a3u, atxmega128c3, atxmega128d3, 8295 atxmega128d4, atxmega192a3, atxmega192a3u, atxmega128b1, 8296 atxmega128b3, atxmega192c3, atxmega192d3, atxmega256a3, 8297 atxmega256a3u, atxmega256a3b, atxmega256a3bu, atxmega256c3, 8298 atxmega256d3, atxmega384c3, atxmega256d3). 8299 8300 Instruction set avrxmega7 is for the XMEGA AVR core with larger 8301 than 64K program memory space and greater than 64K data space (MCU 8302 types: atxmega128a1, atxmega128a1u, atxmega128a4u). 8303 8304 Instruction set avrtiny is for the ATtiny4/5/9/10/20/40 8305 microcontrollers. 8306 8307'-mall-opcodes' 8308 Accept all AVR opcodes, even if not supported by '-mmcu'. 8309 8310'-mno-skip-bug' 8311 This option disable warnings for skipping two-word instructions. 8312 8313'-mno-wrap' 8314 This option reject 'rjmp/rcall' instructions with 8K wrap-around. 8315 8316'-mrmw' 8317 Accept Read-Modify-Write ('XCH,LAC,LAS,LAT') instructions. 8318 8319'-mlink-relax' 8320 Enable support for link-time relaxation. This is now on by default 8321 and this flag no longer has any effect. 8322 8323'-mno-link-relax' 8324 Disable support for link-time relaxation. The assembler will 8325 resolve relocations when it can, and may be able to better compress 8326 some debug information. 8327 8328 8329File: as.info, Node: AVR Syntax, Next: AVR Opcodes, Prev: AVR Options, Up: AVR-Dependent 8330 83319.5.2 Syntax 8332------------ 8333 8334* Menu: 8335 8336* AVR-Chars:: Special Characters 8337* AVR-Regs:: Register Names 8338* AVR-Modifiers:: Relocatable Expression Modifiers 8339 8340 8341File: as.info, Node: AVR-Chars, Next: AVR-Regs, Up: AVR Syntax 8342 83439.5.2.1 Special Characters 8344.......................... 8345 8346The presence of a ';' anywhere on a line indicates the start of a 8347comment that extends to the end of that line. 8348 8349 If a '#' appears as the first character of a line, the whole line is 8350treated as a comment, but in this case the line can also be a logical 8351line number directive (*note Comments::) or a preprocessor control 8352command (*note Preprocessing::). 8353 8354 The '$' character can be used instead of a newline to separate 8355statements. 8356 8357 8358File: as.info, Node: AVR-Regs, Next: AVR-Modifiers, Prev: AVR-Chars, Up: AVR Syntax 8359 83609.5.2.2 Register Names 8361...................... 8362 8363The AVR has 32 x 8-bit general purpose working registers 'r0', 'r1', ... 8364'r31'. Six of the 32 registers can be used as three 16-bit indirect 8365address register pointers for Data Space addressing. One of the these 8366address pointers can also be used as an address pointer for look up 8367tables in Flash program memory. These added function registers are the 836816-bit 'X', 'Y' and 'Z' - registers. 8369 8370 X = r26:r27 8371 Y = r28:r29 8372 Z = r30:r31 8373 8374 8375File: as.info, Node: AVR-Modifiers, Prev: AVR-Regs, Up: AVR Syntax 8376 83779.5.2.3 Relocatable Expression Modifiers 8378........................................ 8379 8380The assembler supports several modifiers when using relocatable 8381addresses in AVR instruction operands. The general syntax is the 8382following: 8383 8384 modifier(relocatable-expression) 8385 8386'lo8' 8387 8388 This modifier allows you to use bits 0 through 7 of an address 8389 expression as 8 bit relocatable expression. 8390 8391'hi8' 8392 8393 This modifier allows you to use bits 7 through 15 of an address 8394 expression as 8 bit relocatable expression. This is useful with, 8395 for example, the AVR 'ldi' instruction and 'lo8' modifier. 8396 8397 For example 8398 8399 ldi r26, lo8(sym+10) 8400 ldi r27, hi8(sym+10) 8401 8402'hh8' 8403 8404 This modifier allows you to use bits 16 through 23 of an address 8405 expression as 8 bit relocatable expression. Also, can be useful 8406 for loading 32 bit constants. 8407 8408'hlo8' 8409 8410 Synonym of 'hh8'. 8411 8412'hhi8' 8413 8414 This modifier allows you to use bits 24 through 31 of an expression 8415 as 8 bit expression. This is useful with, for example, the AVR 8416 'ldi' instruction and 'lo8', 'hi8', 'hlo8', 'hhi8', modifier. 8417 8418 For example 8419 8420 ldi r26, lo8(285774925) 8421 ldi r27, hi8(285774925) 8422 ldi r28, hlo8(285774925) 8423 ldi r29, hhi8(285774925) 8424 ; r29,r28,r27,r26 = 285774925 8425 8426'pm_lo8' 8427 8428 This modifier allows you to use bits 0 through 7 of an address 8429 expression as 8 bit relocatable expression. This modifier useful 8430 for addressing data or code from Flash/Program memory. The using 8431 of 'pm_lo8' similar to 'lo8'. 8432 8433'pm_hi8' 8434 8435 This modifier allows you to use bits 8 through 15 of an address 8436 expression as 8 bit relocatable expression. This modifier useful 8437 for addressing data or code from Flash/Program memory. 8438 8439'pm_hh8' 8440 8441 This modifier allows you to use bits 15 through 23 of an address 8442 expression as 8 bit relocatable expression. This modifier useful 8443 for addressing data or code from Flash/Program memory. 8444 8445 8446File: as.info, Node: AVR Opcodes, Prev: AVR Syntax, Up: AVR-Dependent 8447 84489.5.3 Opcodes 8449------------- 8450 8451For detailed information on the AVR machine instruction set, see 8452<www.atmel.com/products/AVR>. 8453 8454 'as' implements all the standard AVR opcodes. The following table 8455summarizes the AVR opcodes, and their arguments. 8456 8457 Legend: 8458 r any register 8459 d 'ldi' register (r16-r31) 8460 v 'movw' even register (r0, r2, ..., r28, r30) 8461 a 'fmul' register (r16-r23) 8462 w 'adiw' register (r24,r26,r28,r30) 8463 e pointer registers (X,Y,Z) 8464 b base pointer register and displacement ([YZ]+disp) 8465 z Z pointer register (for [e]lpm Rd,Z[+]) 8466 M immediate value from 0 to 255 8467 n immediate value from 0 to 255 ( n = ~M ). Relocation impossible 8468 s immediate value from 0 to 7 8469 P Port address value from 0 to 63. (in, out) 8470 p Port address value from 0 to 31. (cbi, sbi, sbic, sbis) 8471 K immediate value from 0 to 63 (used in 'adiw', 'sbiw') 8472 i immediate value 8473 l signed pc relative offset from -64 to 63 8474 L signed pc relative offset from -2048 to 2047 8475 h absolute code address (call, jmp) 8476 S immediate value from 0 to 7 (S = s << 4) 8477 ? use this opcode entry if no parameters, else use next opcode entry 8478 8479 1001010010001000 clc 8480 1001010011011000 clh 8481 1001010011111000 cli 8482 1001010010101000 cln 8483 1001010011001000 cls 8484 1001010011101000 clt 8485 1001010010111000 clv 8486 1001010010011000 clz 8487 1001010000001000 sec 8488 1001010001011000 seh 8489 1001010001111000 sei 8490 1001010000101000 sen 8491 1001010001001000 ses 8492 1001010001101000 set 8493 1001010000111000 sev 8494 1001010000011000 sez 8495 100101001SSS1000 bclr S 8496 100101000SSS1000 bset S 8497 1001010100001001 icall 8498 1001010000001001 ijmp 8499 1001010111001000 lpm ? 8500 1001000ddddd010+ lpm r,z 8501 1001010111011000 elpm ? 8502 1001000ddddd011+ elpm r,z 8503 0000000000000000 nop 8504 1001010100001000 ret 8505 1001010100011000 reti 8506 1001010110001000 sleep 8507 1001010110011000 break 8508 1001010110101000 wdr 8509 1001010111101000 spm 8510 000111rdddddrrrr adc r,r 8511 000011rdddddrrrr add r,r 8512 001000rdddddrrrr and r,r 8513 000101rdddddrrrr cp r,r 8514 000001rdddddrrrr cpc r,r 8515 000100rdddddrrrr cpse r,r 8516 001001rdddddrrrr eor r,r 8517 001011rdddddrrrr mov r,r 8518 100111rdddddrrrr mul r,r 8519 001010rdddddrrrr or r,r 8520 000010rdddddrrrr sbc r,r 8521 000110rdddddrrrr sub r,r 8522 001001rdddddrrrr clr r 8523 000011rdddddrrrr lsl r 8524 000111rdddddrrrr rol r 8525 001000rdddddrrrr tst r 8526 0111KKKKddddKKKK andi d,M 8527 0111KKKKddddKKKK cbr d,n 8528 1110KKKKddddKKKK ldi d,M 8529 11101111dddd1111 ser d 8530 0110KKKKddddKKKK ori d,M 8531 0110KKKKddddKKKK sbr d,M 8532 0011KKKKddddKKKK cpi d,M 8533 0100KKKKddddKKKK sbci d,M 8534 0101KKKKddddKKKK subi d,M 8535 1111110rrrrr0sss sbrc r,s 8536 1111111rrrrr0sss sbrs r,s 8537 1111100ddddd0sss bld r,s 8538 1111101ddddd0sss bst r,s 8539 10110PPdddddPPPP in r,P 8540 10111PPrrrrrPPPP out P,r 8541 10010110KKddKKKK adiw w,K 8542 10010111KKddKKKK sbiw w,K 8543 10011000pppppsss cbi p,s 8544 10011010pppppsss sbi p,s 8545 10011001pppppsss sbic p,s 8546 10011011pppppsss sbis p,s 8547 111101lllllll000 brcc l 8548 111100lllllll000 brcs l 8549 111100lllllll001 breq l 8550 111101lllllll100 brge l 8551 111101lllllll101 brhc l 8552 111100lllllll101 brhs l 8553 111101lllllll111 brid l 8554 111100lllllll111 brie l 8555 111100lllllll000 brlo l 8556 111100lllllll100 brlt l 8557 111100lllllll010 brmi l 8558 111101lllllll001 brne l 8559 111101lllllll010 brpl l 8560 111101lllllll000 brsh l 8561 111101lllllll110 brtc l 8562 111100lllllll110 brts l 8563 111101lllllll011 brvc l 8564 111100lllllll011 brvs l 8565 111101lllllllsss brbc s,l 8566 111100lllllllsss brbs s,l 8567 1101LLLLLLLLLLLL rcall L 8568 1100LLLLLLLLLLLL rjmp L 8569 1001010hhhhh111h call h 8570 1001010hhhhh110h jmp h 8571 1001010rrrrr0101 asr r 8572 1001010rrrrr0000 com r 8573 1001010rrrrr1010 dec r 8574 1001010rrrrr0011 inc r 8575 1001010rrrrr0110 lsr r 8576 1001010rrrrr0001 neg r 8577 1001000rrrrr1111 pop r 8578 1001001rrrrr1111 push r 8579 1001010rrrrr0111 ror r 8580 1001010rrrrr0010 swap r 8581 00000001ddddrrrr movw v,v 8582 00000010ddddrrrr muls d,d 8583 000000110ddd0rrr mulsu a,a 8584 000000110ddd1rrr fmul a,a 8585 000000111ddd0rrr fmuls a,a 8586 000000111ddd1rrr fmulsu a,a 8587 1001001ddddd0000 sts i,r 8588 1001000ddddd0000 lds r,i 8589 10o0oo0dddddbooo ldd r,b 8590 100!000dddddee-+ ld r,e 8591 10o0oo1rrrrrbooo std b,r 8592 100!001rrrrree-+ st e,r 8593 1001010100011001 eicall 8594 1001010000011001 eijmp 8595 8596 8597File: as.info, Node: Blackfin-Dependent, Next: CR16-Dependent, Prev: AVR-Dependent, Up: Machine Dependencies 8598 85999.6 Blackfin Dependent Features 8600=============================== 8601 8602* Menu: 8603 8604* Blackfin Options:: Blackfin Options 8605* Blackfin Syntax:: Blackfin Syntax 8606* Blackfin Directives:: Blackfin Directives 8607 8608 8609File: as.info, Node: Blackfin Options, Next: Blackfin Syntax, Up: Blackfin-Dependent 8610 86119.6.1 Options 8612------------- 8613 8614'-mcpu=PROCESSOR[-SIREVISION]' 8615 This option specifies the target processor. The optional 8616 SIREVISION is not used in assembler. It's here such that GCC can 8617 easily pass down its '-mcpu=' option. The assembler will issue an 8618 error message if an attempt is made to assemble an instruction 8619 which will not execute on the target processor. The following 8620 processor names are recognized: 'bf504', 'bf506', 'bf512', 'bf514', 8621 'bf516', 'bf518', 'bf522', 'bf523', 'bf524', 'bf525', 'bf526', 8622 'bf527', 'bf531', 'bf532', 'bf533', 'bf534', 'bf535' (not 8623 implemented yet), 'bf536', 'bf537', 'bf538', 'bf539', 'bf542', 8624 'bf542m', 'bf544', 'bf544m', 'bf547', 'bf547m', 'bf548', 'bf548m', 8625 'bf549', 'bf549m', 'bf561', and 'bf592'. 8626 8627'-mfdpic' 8628 Assemble for the FDPIC ABI. 8629 8630'-mno-fdpic' 8631'-mnopic' 8632 Disable -mfdpic. 8633 8634 8635File: as.info, Node: Blackfin Syntax, Next: Blackfin Directives, Prev: Blackfin Options, Up: Blackfin-Dependent 8636 86379.6.2 Syntax 8638------------ 8639 8640'Special Characters' 8641 Assembler input is free format and may appear anywhere on the line. 8642 One instruction may extend across multiple lines or more than one 8643 instruction may appear on the same line. White space (space, tab, 8644 comments or newline) may appear anywhere between tokens. A token 8645 must not have embedded spaces. Tokens include numbers, register 8646 names, keywords, user identifiers, and also some multicharacter 8647 special symbols like "+=", "/*" or "||". 8648 8649 Comments are introduced by the '#' character and extend to the end 8650 of the current line. If the '#' appears as the first character of 8651 a line, the whole line is treated as a comment, but in this case 8652 the line can also be a logical line number directive (*note 8653 Comments::) or a preprocessor control command (*note 8654 Preprocessing::). 8655 8656'Instruction Delimiting' 8657 A semicolon must terminate every instruction. Sometimes a complete 8658 instruction will consist of more than one operation. There are two 8659 cases where this occurs. The first is when two general operations 8660 are combined. Normally a comma separates the different parts, as 8661 in 8662 8663 a0= r3.h * r2.l, a1 = r3.l * r2.h ; 8664 8665 The second case occurs when a general instruction is combined with 8666 one or two memory references for joint issue. The latter portions 8667 are set off by a "||" token. 8668 8669 a0 = r3.h * r2.l || r1 = [p3++] || r4 = [i2++]; 8670 8671 Multiple instructions can occur on the same line. Each must be 8672 terminated by a semicolon character. 8673 8674'Register Names' 8675 8676 The assembler treats register names and instruction keywords in a 8677 case insensitive manner. User identifiers are case sensitive. 8678 Thus, R3.l, R3.L, r3.l and r3.L are all equivalent input to the 8679 assembler. 8680 8681 Register names are reserved and may not be used as program 8682 identifiers. 8683 8684 Some operations (such as "Move Register") require a register pair. 8685 Register pairs are always data registers and are denoted using a 8686 colon, eg., R3:2. The larger number must be written firsts. Note 8687 that the hardware only supports odd-even pairs, eg., R7:6, R5:4, 8688 R3:2, and R1:0. 8689 8690 Some instructions (such as -SP (Push Multiple)) require a group of 8691 adjacent registers. Adjacent registers are denoted in the syntax 8692 by the range enclosed in parentheses and separated by a colon, eg., 8693 (R7:3). Again, the larger number appears first. 8694 8695 Portions of a particular register may be individually specified. 8696 This is written with a dot (".") following the register name and 8697 then a letter denoting the desired portion. For 32-bit registers, 8698 ".H" denotes the most significant ("High") portion. ".L" denotes 8699 the least-significant portion. The subdivisions of the 40-bit 8700 registers are described later. 8701 8702'Accumulators' 8703 The set of 40-bit registers A1 and A0 that normally contain data 8704 that is being manipulated. Each accumulator can be accessed in 8705 four ways. 8706 8707 'one 40-bit register' 8708 The register will be referred to as A1 or A0. 8709 'one 32-bit register' 8710 The registers are designated as A1.W or A0.W. 8711 'two 16-bit registers' 8712 The registers are designated as A1.H, A1.L, A0.H or A0.L. 8713 'one 8-bit register' 8714 The registers are designated as A1.X or A0.X for the bits that 8715 extend beyond bit 31. 8716 8717'Data Registers' 8718 The set of 32-bit registers (R0, R1, R2, R3, R4, R5, R6 and R7) 8719 that normally contain data for manipulation. These are abbreviated 8720 as D-register or Dreg. Data registers can be accessed as 32-bit 8721 registers or as two independent 16-bit registers. The least 8722 significant 16 bits of each register is called the "low" half and 8723 is designated with ".L" following the register name. The most 8724 significant 16 bits are called the "high" half and is designated 8725 with ".H" following the name. 8726 8727 R7.L, r2.h, r4.L, R0.H 8728 8729'Pointer Registers' 8730 The set of 32-bit registers (P0, P1, P2, P3, P4, P5, SP and FP) 8731 that normally contain byte addresses of data structures. These are 8732 abbreviated as P-register or Preg. 8733 8734 p2, p5, fp, sp 8735 8736'Stack Pointer SP' 8737 The stack pointer contains the 32-bit address of the last occupied 8738 byte location in the stack. The stack grows by decrementing the 8739 stack pointer. 8740 8741'Frame Pointer FP' 8742 The frame pointer contains the 32-bit address of the previous frame 8743 pointer in the stack. It is located at the top of a frame. 8744 8745'Loop Top' 8746 LT0 and LT1. These registers contain the 32-bit address of the top 8747 of a zero overhead loop. 8748 8749'Loop Count' 8750 LC0 and LC1. These registers contain the 32-bit counter of the 8751 zero overhead loop executions. 8752 8753'Loop Bottom' 8754 LB0 and LB1. These registers contain the 32-bit address of the 8755 bottom of a zero overhead loop. 8756 8757'Index Registers' 8758 The set of 32-bit registers (I0, I1, I2, I3) that normally contain 8759 byte addresses of data structures. Abbreviated I-register or Ireg. 8760 8761'Modify Registers' 8762 The set of 32-bit registers (M0, M1, M2, M3) that normally contain 8763 offset values that are added and subtracted to one of the index 8764 registers. Abbreviated as Mreg. 8765 8766'Length Registers' 8767 The set of 32-bit registers (L0, L1, L2, L3) that normally contain 8768 the length in bytes of the circular buffer. Abbreviated as Lreg. 8769 Clear the Lreg to disable circular addressing for the corresponding 8770 Ireg. 8771 8772'Base Registers' 8773 The set of 32-bit registers (B0, B1, B2, B3) that normally contain 8774 the base address in bytes of the circular buffer. Abbreviated as 8775 Breg. 8776 8777'Floating Point' 8778 The Blackfin family has no hardware floating point but the .float 8779 directive generates ieee floating point numbers for use with 8780 software floating point libraries. 8781 8782'Blackfin Opcodes' 8783 For detailed information on the Blackfin machine instruction set, 8784 see the Blackfin(r) Processor Instruction Set Reference. 8785 8786 8787File: as.info, Node: Blackfin Directives, Prev: Blackfin Syntax, Up: Blackfin-Dependent 8788 87899.6.3 Directives 8790---------------- 8791 8792The following directives are provided for compatibility with the VDSP 8793assembler. 8794 8795'.byte2' 8796 Initializes a two byte data object. 8797 8798 This maps to the '.short' directive. 8799'.byte4' 8800 Initializes a four byte data object. 8801 8802 This maps to the '.int' directive. 8803'.db' 8804 Initializes a single byte data object. 8805 8806 This directive is a synonym for '.byte'. 8807'.dw' 8808 Initializes a two byte data object. 8809 8810 This directive is a synonym for '.byte2'. 8811'.dd' 8812 Initializes a four byte data object. 8813 8814 This directive is a synonym for '.byte4'. 8815'.var' 8816 Define and initialize a 32 bit data object. 8817 8818 8819File: as.info, Node: CR16-Dependent, Next: CRIS-Dependent, Prev: Blackfin-Dependent, Up: Machine Dependencies 8820 88219.7 CR16 Dependent Features 8822=========================== 8823 8824* Menu: 8825 8826* CR16 Operand Qualifiers:: CR16 Machine Operand Qualifiers 8827* CR16 Syntax:: Syntax for the CR16 8828 8829 8830File: as.info, Node: CR16 Operand Qualifiers, Next: CR16 Syntax, Up: CR16-Dependent 8831 88329.7.1 CR16 Operand Qualifiers 8833----------------------------- 8834 8835The National Semiconductor CR16 target of 'as' has a few machine 8836dependent operand qualifiers. 8837 8838 Operand expression type qualifier is an optional field in the 8839instruction operand, to determines the type of the expression field of 8840an operand. The '@' is required. CR16 architecture uses one of the 8841following expression qualifiers: 8842 8843's' 8844 - 'Specifies expression operand type as small' 8845'm' 8846 - 'Specifies expression operand type as medium' 8847'l' 8848 - 'Specifies expression operand type as large' 8849'c' 8850 - 'Specifies the CR16 Assembler generates a relocation entry for 8851 the operand, where pc has implied bit, the expression is adjusted 8852 accordingly. The linker uses the relocation entry to update the 8853 operand address at link time.' 8854'got/GOT' 8855 - 'Specifies the CR16 Assembler generates a relocation entry for 8856 the operand, offset from Global Offset Table. The linker uses this 8857 relocation entry to update the operand address at link time' 8858'cgot/cGOT' 8859 - 'Specifies the CompactRISC Assembler generates a relocation entry 8860 for the operand, where pc has implied bit, the expression is 8861 adjusted accordingly. The linker uses the relocation entry to 8862 update the operand address at link time.' 8863 8864 CR16 target operand qualifiers and its size (in bits): 8865 8866'Immediate Operand: s' 8867 4 bits. 8868 8869'Immediate Operand: m' 8870 16 bits, for movb and movw instructions. 8871 8872'Immediate Operand: m' 8873 20 bits, movd instructions. 8874 8875'Immediate Operand: l' 8876 32 bits. 8877 8878'Absolute Operand: s' 8879 Illegal specifier for this operand. 8880 8881'Absolute Operand: m' 8882 20 bits, movd instructions. 8883 8884'Displacement Operand: s' 8885 8 bits. 8886 8887'Displacement Operand: m' 8888 16 bits. 8889 8890'Displacement Operand: l' 8891 24 bits. 8892 8893 For example: 8894 1 movw $_myfun@c,r1 8895 8896 This loads the address of _myfun, shifted right by 1, into r1. 8897 8898 2 movd $_myfun@c,(r2,r1) 8899 8900 This loads the address of _myfun, shifted right by 1, into register-pair r2-r1. 8901 8902 3 _myfun_ptr: 8903 .long _myfun@c 8904 loadd _myfun_ptr, (r1,r0) 8905 jal (r1,r0) 8906 8907 This .long directive, the address of _myfunc, shifted right by 1 at link time. 8908 8909 4 loadd _data1@GOT(r12), (r1,r0) 8910 8911 This loads the address of _data1, into global offset table (ie GOT) and its offset value from GOT loads into register-pair r2-r1. 8912 8913 5 loadd _myfunc@cGOT(r12), (r1,r0) 8914 8915 This loads the address of _myfun, shifted right by 1, into global offset table (ie GOT) and its offset value from GOT loads into register-pair r1-r0. 8916 8917 8918File: as.info, Node: CR16 Syntax, Prev: CR16 Operand Qualifiers, Up: CR16-Dependent 8919 89209.7.2 CR16 Syntax 8921----------------- 8922 8923* Menu: 8924 8925* CR16-Chars:: Special Characters 8926 8927 8928File: as.info, Node: CR16-Chars, Up: CR16 Syntax 8929 89309.7.2.1 Special Characters 8931.......................... 8932 8933The presence of a '#' on a line indicates the start of a comment that 8934extends to the end of the current line. If the '#' appears as the first 8935character of a line, the whole line is treated as a comment, but in this 8936case the line can also be a logical line number directive (*note 8937Comments::) or a preprocessor control command (*note Preprocessing::). 8938 8939 The ';' character can be used to separate statements on the same 8940line. 8941 8942 8943File: as.info, Node: CRIS-Dependent, Next: D10V-Dependent, Prev: CR16-Dependent, Up: Machine Dependencies 8944 89459.8 CRIS Dependent Features 8946=========================== 8947 8948* Menu: 8949 8950* CRIS-Opts:: Command-line Options 8951* CRIS-Expand:: Instruction expansion 8952* CRIS-Symbols:: Symbols 8953* CRIS-Syntax:: Syntax 8954 8955 8956File: as.info, Node: CRIS-Opts, Next: CRIS-Expand, Up: CRIS-Dependent 8957 89589.8.1 Command-line Options 8959-------------------------- 8960 8961The CRIS version of 'as' has these machine-dependent command-line 8962options. 8963 8964 The format of the generated object files can be either ELF or a.out, 8965specified by the command-line options '--emulation=crisaout' and 8966'--emulation=criself'. The default is ELF (criself), unless 'as' has 8967been configured specifically for a.out by using the configuration name 8968'cris-axis-aout'. 8969 8970 There are two different link-incompatible ELF object file variants 8971for CRIS, for use in environments where symbols are expected to be 8972prefixed by a leading '_' character and for environments without such a 8973symbol prefix. The variant used for GNU/Linux port has no symbol 8974prefix. Which variant to produce is specified by either of the options 8975'--underscore' and '--no-underscore'. The default is '--underscore'. 8976Since symbols in CRIS a.out objects are expected to have a '_' prefix, 8977specifying '--no-underscore' when generating a.out objects is an error. 8978Besides the object format difference, the effect of this option is to 8979parse register names differently (*note crisnous::). The 8980'--no-underscore' option makes a '$' register prefix mandatory. 8981 8982 The option '--pic' must be passed to 'as' in order to recognize the 8983symbol syntax used for ELF (SVR4 PIC) position-independent-code (*note 8984crispic::). This will also affect expansion of instructions. The 8985expansion with '--pic' will use PC-relative rather than (slightly 8986faster) absolute addresses in those expansions. This option is only 8987valid when generating ELF format object files. 8988 8989 The option '--march=ARCHITECTURE' specifies the recognized 8990instruction set and recognized register names. It also controls the 8991architecture type of the object file. Valid values for ARCHITECTURE 8992are: 8993 8994'v0_v10' 8995 All instructions and register names for any architecture variant in 8996 the set v0...v10 are recognized. This is the default if the target 8997 is configured as cris-*. 8998 8999'v10' 9000 Only instructions and register names for CRIS v10 (as found in 9001 ETRAX 100 LX) are recognized. This is the default if the target is 9002 configured as crisv10-*. 9003 9004'v32' 9005 Only instructions and register names for CRIS v32 (code name 9006 Guinness) are recognized. This is the default if the target is 9007 configured as crisv32-*. This value implies '--no-mul-bug-abort'. 9008 (A subsequent '--mul-bug-abort' will turn it back on.) 9009 9010'common_v10_v32' 9011 Only instructions with register names and addressing modes with 9012 opcodes common to the v10 and v32 are recognized. 9013 9014 When '-N' is specified, 'as' will emit a warning when a 16-bit branch 9015instruction is expanded into a 32-bit multiple-instruction construct 9016(*note CRIS-Expand::). 9017 9018 Some versions of the CRIS v10, for example in the Etrax 100 LX, 9019contain a bug that causes destabilizing memory accesses when a multiply 9020instruction is executed with certain values in the first operand just 9021before a cache-miss. When the '--mul-bug-abort' command line option is 9022active (the default value), 'as' will refuse to assemble a file 9023containing a multiply instruction at a dangerous offset, one that could 9024be the last on a cache-line, or is in a section with insufficient 9025alignment. This placement checking does not catch any case where the 9026multiply instruction is dangerously placed because it is located in a 9027delay-slot. The '--mul-bug-abort' command line option turns off the 9028checking. 9029 9030 9031File: as.info, Node: CRIS-Expand, Next: CRIS-Symbols, Prev: CRIS-Opts, Up: CRIS-Dependent 9032 90339.8.2 Instruction expansion 9034--------------------------- 9035 9036'as' will silently choose an instruction that fits the operand size for 9037'[register+constant]' operands. For example, the offset '127' in 9038'move.d [r3+127],r4' fits in an instruction using a signed-byte offset. 9039Similarly, 'move.d [r2+32767],r1' will generate an instruction using a 904016-bit offset. For symbolic expressions and constants that do not fit 9041in 16 bits including the sign bit, a 32-bit offset is generated. 9042 9043 For branches, 'as' will expand from a 16-bit branch instruction into 9044a sequence of instructions that can reach a full 32-bit address. Since 9045this does not correspond to a single instruction, such expansions can 9046optionally be warned about. *Note CRIS-Opts::. 9047 9048 If the operand is found to fit the range, a 'lapc' mnemonic will 9049translate to a 'lapcq' instruction. Use 'lapc.d' to force the 32-bit 9050'lapc' instruction. 9051 9052 Similarly, the 'addo' mnemonic will translate to the shortest fitting 9053instruction of 'addoq', 'addo.w' and 'addo.d', when used with a operand 9054that is a constant known at assembly time. 9055 9056 9057File: as.info, Node: CRIS-Symbols, Next: CRIS-Syntax, Prev: CRIS-Expand, Up: CRIS-Dependent 9058 90599.8.3 Symbols 9060------------- 9061 9062Some symbols are defined by the assembler. They're intended to be used 9063in conditional assembly, for example: 9064 .if ..asm.arch.cris.v32 9065 CODE FOR CRIS V32 9066 .elseif ..asm.arch.cris.common_v10_v32 9067 CODE COMMON TO CRIS V32 AND CRIS V10 9068 .elseif ..asm.arch.cris.v10 | ..asm.arch.cris.any_v0_v10 9069 CODE FOR V10 9070 .else 9071 .error "Code needs to be added here." 9072 .endif 9073 9074 These symbols are defined in the assembler, reflecting command-line 9075options, either when specified or the default. They are always defined, 9076to 0 or 1. 9077 9078'..asm.arch.cris.any_v0_v10' 9079 This symbol is non-zero when '--march=v0_v10' is specified or the 9080 default. 9081 9082'..asm.arch.cris.common_v10_v32' 9083 Set according to the option '--march=common_v10_v32'. 9084 9085'..asm.arch.cris.v10' 9086 Reflects the option '--march=v10'. 9087 9088'..asm.arch.cris.v32' 9089 Corresponds to '--march=v10'. 9090 9091 Speaking of symbols, when a symbol is used in code, it can have a 9092suffix modifying its value for use in position-independent code. *Note 9093CRIS-Pic::. 9094 9095 9096File: as.info, Node: CRIS-Syntax, Prev: CRIS-Symbols, Up: CRIS-Dependent 9097 90989.8.4 Syntax 9099------------ 9100 9101There are different aspects of the CRIS assembly syntax. 9102 9103* Menu: 9104 9105* CRIS-Chars:: Special Characters 9106* CRIS-Pic:: Position-Independent Code Symbols 9107* CRIS-Regs:: Register Names 9108* CRIS-Pseudos:: Assembler Directives 9109 9110 9111File: as.info, Node: CRIS-Chars, Next: CRIS-Pic, Up: CRIS-Syntax 9112 91139.8.4.1 Special Characters 9114.......................... 9115 9116The character '#' is a line comment character. It starts a comment if 9117and only if it is placed at the beginning of a line. 9118 9119 A ';' character starts a comment anywhere on the line, causing all 9120characters up to the end of the line to be ignored. 9121 9122 A '@' character is handled as a line separator equivalent to a 9123logical new-line character (except in a comment), so separate 9124instructions can be specified on a single line. 9125 9126 9127File: as.info, Node: CRIS-Pic, Next: CRIS-Regs, Prev: CRIS-Chars, Up: CRIS-Syntax 9128 91299.8.4.2 Symbols in position-independent code 9130............................................ 9131 9132When generating position-independent code (SVR4 PIC) for use in 9133cris-axis-linux-gnu or crisv32-axis-linux-gnu shared libraries, symbol 9134suffixes are used to specify what kind of run-time symbol lookup will be 9135used, expressed in the object as different _relocation types_. Usually, 9136all absolute symbol values must be located in a table, the _global 9137offset table_, leaving the code position-independent; independent of 9138values of global symbols and independent of the address of the code. 9139The suffix modifies the value of the symbol, into for example an index 9140into the global offset table where the real symbol value is entered, or 9141a PC-relative value, or a value relative to the start of the global 9142offset table. All symbol suffixes start with the character ':' (omitted 9143in the list below). Every symbol use in code or a read-only section 9144must therefore have a PIC suffix to enable a useful shared library to be 9145created. Usually, these constructs must not be used with an additive 9146constant offset as is usually allowed, i.e. no 4 as in 'symbol + 4' is 9147allowed. This restriction is checked at link-time, not at 9148assembly-time. 9149 9150'GOT' 9151 9152 Attaching this suffix to a symbol in an instruction causes the 9153 symbol to be entered into the global offset table. The value is a 9154 32-bit index for that symbol into the global offset table. The 9155 name of the corresponding relocation is 'R_CRIS_32_GOT'. Example: 9156 'move.d [$r0+extsym:GOT],$r9' 9157 9158'GOT16' 9159 9160 Same as for 'GOT', but the value is a 16-bit index into the global 9161 offset table. The corresponding relocation is 'R_CRIS_16_GOT'. 9162 Example: 'move.d [$r0+asymbol:GOT16],$r10' 9163 9164'PLT' 9165 9166 This suffix is used for function symbols. It causes a _procedure 9167 linkage table_, an array of code stubs, to be created at the time 9168 the shared object is created or linked against, together with a 9169 global offset table entry. The value is a pc-relative offset to 9170 the corresponding stub code in the procedure linkage table. This 9171 arrangement causes the run-time symbol resolver to be called to 9172 look up and set the value of the symbol the first time the function 9173 is called (at latest; depending environment variables). It is only 9174 safe to leave the symbol unresolved this way if all references are 9175 function calls. The name of the relocation is 9176 'R_CRIS_32_PLT_PCREL'. Example: 'add.d fnname:PLT,$pc' 9177 9178'PLTG' 9179 9180 Like PLT, but the value is relative to the beginning of the global 9181 offset table. The relocation is 'R_CRIS_32_PLT_GOTREL'. Example: 9182 'move.d fnname:PLTG,$r3' 9183 9184'GOTPLT' 9185 9186 Similar to 'PLT', but the value of the symbol is a 32-bit index 9187 into the global offset table. This is somewhat of a mix between 9188 the effect of the 'GOT' and the 'PLT' suffix; the difference to 9189 'GOT' is that there will be a procedure linkage table entry 9190 created, and that the symbol is assumed to be a function entry and 9191 will be resolved by the run-time resolver as with 'PLT'. The 9192 relocation is 'R_CRIS_32_GOTPLT'. Example: 'jsr 9193 [$r0+fnname:GOTPLT]' 9194 9195'GOTPLT16' 9196 9197 A variant of 'GOTPLT' giving a 16-bit value. Its relocation name 9198 is 'R_CRIS_16_GOTPLT'. Example: 'jsr [$r0+fnname:GOTPLT16]' 9199 9200'GOTOFF' 9201 9202 This suffix must only be attached to a local symbol, but may be 9203 used in an expression adding an offset. The value is the address 9204 of the symbol relative to the start of the global offset table. 9205 The relocation name is 'R_CRIS_32_GOTREL'. Example: 'move.d 9206 [$r0+localsym:GOTOFF],r3' 9207 9208 9209File: as.info, Node: CRIS-Regs, Next: CRIS-Pseudos, Prev: CRIS-Pic, Up: CRIS-Syntax 9210 92119.8.4.3 Register names 9212...................... 9213 9214A '$' character may always prefix a general or special register name in 9215an instruction operand but is mandatory when the option 9216'--no-underscore' is specified or when the '.syntax register_prefix' 9217directive is in effect (*note crisnous::). Register names are 9218case-insensitive. 9219 9220 9221File: as.info, Node: CRIS-Pseudos, Prev: CRIS-Regs, Up: CRIS-Syntax 9222 92239.8.4.4 Assembler Directives 9224............................ 9225 9226There are a few CRIS-specific pseudo-directives in addition to the 9227generic ones. *Note Pseudo Ops::. Constants emitted by 9228pseudo-directives are in little-endian order for CRIS. There is no 9229support for floating-point-specific directives for CRIS. 9230 9231'.dword EXPRESSIONS' 9232 9233 The '.dword' directive is a synonym for '.int', expecting zero or 9234 more EXPRESSIONS, separated by commas. For each expression, a 9235 32-bit little-endian constant is emitted. 9236 9237'.syntax ARGUMENT' 9238 The '.syntax' directive takes as ARGUMENT one of the following 9239 case-sensitive choices. 9240 9241 'no_register_prefix' 9242 9243 The '.syntax no_register_prefix' directive makes a '$' 9244 character prefix on all registers optional. It overrides a 9245 previous setting, including the corresponding effect of the 9246 option '--no-underscore'. If this directive is used when 9247 ordinary symbols do not have a '_' character prefix, care must 9248 be taken to avoid ambiguities whether an operand is a register 9249 or a symbol; using symbols with names the same as general or 9250 special registers then invoke undefined behavior. 9251 9252 'register_prefix' 9253 9254 This directive makes a '$' character prefix on all registers 9255 mandatory. It overrides a previous setting, including the 9256 corresponding effect of the option '--underscore'. 9257 9258 'leading_underscore' 9259 9260 This is an assertion directive, emitting an error if the 9261 '--no-underscore' option is in effect. 9262 9263 'no_leading_underscore' 9264 9265 This is the opposite of the '.syntax leading_underscore' 9266 directive and emits an error if the option '--underscore' is 9267 in effect. 9268 9269'.arch ARGUMENT' 9270 This is an assertion directive, giving an error if the specified 9271 ARGUMENT is not the same as the specified or default value for the 9272 '--march=ARCHITECTURE' option (*note march-option::). 9273 9274 9275File: as.info, Node: D10V-Dependent, Next: D30V-Dependent, Prev: CRIS-Dependent, Up: Machine Dependencies 9276 92779.9 D10V Dependent Features 9278=========================== 9279 9280* Menu: 9281 9282* D10V-Opts:: D10V Options 9283* D10V-Syntax:: Syntax 9284* D10V-Float:: Floating Point 9285* D10V-Opcodes:: Opcodes 9286 9287 9288File: as.info, Node: D10V-Opts, Next: D10V-Syntax, Up: D10V-Dependent 9289 92909.9.1 D10V Options 9291------------------ 9292 9293The Mitsubishi D10V version of 'as' has a few machine dependent options. 9294 9295'-O' 9296 The D10V can often execute two sub-instructions in parallel. When 9297 this option is used, 'as' will attempt to optimize its output by 9298 detecting when instructions can be executed in parallel. 9299'--nowarnswap' 9300 To optimize execution performance, 'as' will sometimes swap the 9301 order of instructions. Normally this generates a warning. When 9302 this option is used, no warning will be generated when instructions 9303 are swapped. 9304'--gstabs-packing' 9305'--no-gstabs-packing' 9306 'as' packs adjacent short instructions into a single packed 9307 instruction. '--no-gstabs-packing' turns instruction packing off 9308 if '--gstabs' is specified as well; '--gstabs-packing' (the 9309 default) turns instruction packing on even when '--gstabs' is 9310 specified. 9311 9312 9313File: as.info, Node: D10V-Syntax, Next: D10V-Float, Prev: D10V-Opts, Up: D10V-Dependent 9314 93159.9.2 Syntax 9316------------ 9317 9318The D10V syntax is based on the syntax in Mitsubishi's D10V architecture 9319manual. The differences are detailed below. 9320 9321* Menu: 9322 9323* D10V-Size:: Size Modifiers 9324* D10V-Subs:: Sub-Instructions 9325* D10V-Chars:: Special Characters 9326* D10V-Regs:: Register Names 9327* D10V-Addressing:: Addressing Modes 9328* D10V-Word:: @WORD Modifier 9329 9330 9331File: as.info, Node: D10V-Size, Next: D10V-Subs, Up: D10V-Syntax 9332 93339.9.2.1 Size Modifiers 9334...................... 9335 9336The D10V version of 'as' uses the instruction names in the D10V 9337Architecture Manual. However, the names in the manual are sometimes 9338ambiguous. There are instruction names that can assemble to a short or 9339long form opcode. How does the assembler pick the correct form? 'as' 9340will always pick the smallest form if it can. When dealing with a 9341symbol that is not defined yet when a line is being assembled, it will 9342always use the long form. If you need to force the assembler to use 9343either the short or long form of the instruction, you can append either 9344'.s' (short) or '.l' (long) to it. For example, if you are writing an 9345assembly program and you want to do a branch to a symbol that is defined 9346later in your program, you can write 'bra.s foo'. Objdump and GDB will 9347always append '.s' or '.l' to instructions which have both short and 9348long forms. 9349 9350 9351File: as.info, Node: D10V-Subs, Next: D10V-Chars, Prev: D10V-Size, Up: D10V-Syntax 9352 93539.9.2.2 Sub-Instructions 9354........................ 9355 9356The D10V assembler takes as input a series of instructions, either 9357one-per-line, or in the special two-per-line format described in the 9358next section. Some of these instructions will be short-form or 9359sub-instructions. These sub-instructions can be packed into a single 9360instruction. The assembler will do this automatically. It will also 9361detect when it should not pack instructions. For example, when a label 9362is defined, the next instruction will never be packaged with the 9363previous one. Whenever a branch and link instruction is called, it will 9364not be packaged with the next instruction so the return address will be 9365valid. Nops are automatically inserted when necessary. 9366 9367 If you do not want the assembler automatically making these 9368decisions, you can control the packaging and execution type (parallel or 9369sequential) with the special execution symbols described in the next 9370section. 9371 9372 9373File: as.info, Node: D10V-Chars, Next: D10V-Regs, Prev: D10V-Subs, Up: D10V-Syntax 9374 93759.9.2.3 Special Characters 9376.......................... 9377 9378A semicolon (';') can be used anywhere on a line to start a comment that 9379extends to the end of the line. 9380 9381 If a '#' appears as the first character of a line, the whole line is 9382treated as a comment, but in this case the line could also be a logical 9383line number directive (*note Comments::) or a preprocessor control 9384command (*note Preprocessing::). 9385 9386 Sub-instructions may be executed in order, in reverse-order, or in 9387parallel. Instructions listed in the standard one-per-line format will 9388be executed sequentially. To specify the executing order, use the 9389following symbols: 9390'->' 9391 Sequential with instruction on the left first. 9392'<-' 9393 Sequential with instruction on the right first. 9394'||' 9395 Parallel 9396 The D10V syntax allows either one instruction per line, one 9397instruction per line with the execution symbol, or two instructions per 9398line. For example 9399'abs a1 -> abs r0' 9400 Execute these sequentially. The instruction on the right is in the 9401 right container and is executed second. 9402'abs r0 <- abs a1' 9403 Execute these reverse-sequentially. The instruction on the right 9404 is in the right container, and is executed first. 9405'ld2w r2,@r8+ || mac a0,r0,r7' 9406 Execute these in parallel. 9407'ld2w r2,@r8+ ||' 9408'mac a0,r0,r7' 9409 Two-line format. Execute these in parallel. 9410'ld2w r2,@r8+' 9411'mac a0,r0,r7' 9412 Two-line format. Execute these sequentially. Assembler will put 9413 them in the proper containers. 9414'ld2w r2,@r8+ ->' 9415'mac a0,r0,r7' 9416 Two-line format. Execute these sequentially. Same as above but 9417 second instruction will always go into right container. 9418 Since '$' has no special meaning, you may use it in symbol names. 9419 9420 9421File: as.info, Node: D10V-Regs, Next: D10V-Addressing, Prev: D10V-Chars, Up: D10V-Syntax 9422 94239.9.2.4 Register Names 9424...................... 9425 9426You can use the predefined symbols 'r0' through 'r15' to refer to the 9427D10V registers. You can also use 'sp' as an alias for 'r15'. The 9428accumulators are 'a0' and 'a1'. There are special register-pair names 9429that may optionally be used in opcodes that require even-numbered 9430registers. Register names are not case sensitive. 9431 9432 Register Pairs 9433'r0-r1' 9434'r2-r3' 9435'r4-r5' 9436'r6-r7' 9437'r8-r9' 9438'r10-r11' 9439'r12-r13' 9440'r14-r15' 9441 9442 The D10V also has predefined symbols for these control registers and 9443status bits: 9444'psw' 9445 Processor Status Word 9446'bpsw' 9447 Backup Processor Status Word 9448'pc' 9449 Program Counter 9450'bpc' 9451 Backup Program Counter 9452'rpt_c' 9453 Repeat Count 9454'rpt_s' 9455 Repeat Start address 9456'rpt_e' 9457 Repeat End address 9458'mod_s' 9459 Modulo Start address 9460'mod_e' 9461 Modulo End address 9462'iba' 9463 Instruction Break Address 9464'f0' 9465 Flag 0 9466'f1' 9467 Flag 1 9468'c' 9469 Carry flag 9470 9471 9472File: as.info, Node: D10V-Addressing, Next: D10V-Word, Prev: D10V-Regs, Up: D10V-Syntax 9473 94749.9.2.5 Addressing Modes 9475........................ 9476 9477'as' understands the following addressing modes for the D10V. 'RN' in 9478the following refers to any of the numbered registers, but _not_ the 9479control registers. 9480'RN' 9481 Register direct 9482'@RN' 9483 Register indirect 9484'@RN+' 9485 Register indirect with post-increment 9486'@RN-' 9487 Register indirect with post-decrement 9488'@-SP' 9489 Register indirect with pre-decrement 9490'@(DISP, RN)' 9491 Register indirect with displacement 9492'ADDR' 9493 PC relative address (for branch or rep). 9494'#IMM' 9495 Immediate data (the '#' is optional and ignored) 9496 9497 9498File: as.info, Node: D10V-Word, Prev: D10V-Addressing, Up: D10V-Syntax 9499 95009.9.2.6 @WORD Modifier 9501...................... 9502 9503Any symbol followed by '@word' will be replaced by the symbol's value 9504shifted right by 2. This is used in situations such as loading a 9505register with the address of a function (or any other code fragment). 9506For example, if you want to load a register with the location of the 9507function 'main' then jump to that function, you could do it as follows: 9508 ldi r2, main@word 9509 jmp r2 9510 9511 9512File: as.info, Node: D10V-Float, Next: D10V-Opcodes, Prev: D10V-Syntax, Up: D10V-Dependent 9513 95149.9.3 Floating Point 9515-------------------- 9516 9517The D10V has no hardware floating point, but the '.float' and '.double' 9518directives generates IEEE floating-point numbers for compatibility with 9519other development tools. 9520 9521 9522File: as.info, Node: D10V-Opcodes, Prev: D10V-Float, Up: D10V-Dependent 9523 95249.9.4 Opcodes 9525------------- 9526 9527For detailed information on the D10V machine instruction set, see 'D10V 9528Architecture: A VLIW Microprocessor for Multimedia Applications' 9529(Mitsubishi Electric Corp.). 'as' implements all the standard D10V 9530opcodes. The only changes are those described in the section on size 9531modifiers 9532 9533 9534File: as.info, Node: D30V-Dependent, Next: Epiphany-Dependent, Prev: D10V-Dependent, Up: Machine Dependencies 9535 95369.10 D30V Dependent Features 9537============================ 9538 9539* Menu: 9540 9541* D30V-Opts:: D30V Options 9542* D30V-Syntax:: Syntax 9543* D30V-Float:: Floating Point 9544* D30V-Opcodes:: Opcodes 9545 9546 9547File: as.info, Node: D30V-Opts, Next: D30V-Syntax, Up: D30V-Dependent 9548 95499.10.1 D30V Options 9550------------------- 9551 9552The Mitsubishi D30V version of 'as' has a few machine dependent options. 9553 9554'-O' 9555 The D30V can often execute two sub-instructions in parallel. When 9556 this option is used, 'as' will attempt to optimize its output by 9557 detecting when instructions can be executed in parallel. 9558 9559'-n' 9560 When this option is used, 'as' will issue a warning every time it 9561 adds a nop instruction. 9562 9563'-N' 9564 When this option is used, 'as' will issue a warning if it needs to 9565 insert a nop after a 32-bit multiply before a load or 16-bit 9566 multiply instruction. 9567 9568 9569File: as.info, Node: D30V-Syntax, Next: D30V-Float, Prev: D30V-Opts, Up: D30V-Dependent 9570 95719.10.2 Syntax 9572------------- 9573 9574The D30V syntax is based on the syntax in Mitsubishi's D30V architecture 9575manual. The differences are detailed below. 9576 9577* Menu: 9578 9579* D30V-Size:: Size Modifiers 9580* D30V-Subs:: Sub-Instructions 9581* D30V-Chars:: Special Characters 9582* D30V-Guarded:: Guarded Execution 9583* D30V-Regs:: Register Names 9584* D30V-Addressing:: Addressing Modes 9585 9586 9587File: as.info, Node: D30V-Size, Next: D30V-Subs, Up: D30V-Syntax 9588 95899.10.2.1 Size Modifiers 9590....................... 9591 9592The D30V version of 'as' uses the instruction names in the D30V 9593Architecture Manual. However, the names in the manual are sometimes 9594ambiguous. There are instruction names that can assemble to a short or 9595long form opcode. How does the assembler pick the correct form? 'as' 9596will always pick the smallest form if it can. When dealing with a 9597symbol that is not defined yet when a line is being assembled, it will 9598always use the long form. If you need to force the assembler to use 9599either the short or long form of the instruction, you can append either 9600'.s' (short) or '.l' (long) to it. For example, if you are writing an 9601assembly program and you want to do a branch to a symbol that is defined 9602later in your program, you can write 'bra.s foo'. Objdump and GDB will 9603always append '.s' or '.l' to instructions which have both short and 9604long forms. 9605 9606 9607File: as.info, Node: D30V-Subs, Next: D30V-Chars, Prev: D30V-Size, Up: D30V-Syntax 9608 96099.10.2.2 Sub-Instructions 9610......................... 9611 9612The D30V assembler takes as input a series of instructions, either 9613one-per-line, or in the special two-per-line format described in the 9614next section. Some of these instructions will be short-form or 9615sub-instructions. These sub-instructions can be packed into a single 9616instruction. The assembler will do this automatically. It will also 9617detect when it should not pack instructions. For example, when a label 9618is defined, the next instruction will never be packaged with the 9619previous one. Whenever a branch and link instruction is called, it will 9620not be packaged with the next instruction so the return address will be 9621valid. Nops are automatically inserted when necessary. 9622 9623 If you do not want the assembler automatically making these 9624decisions, you can control the packaging and execution type (parallel or 9625sequential) with the special execution symbols described in the next 9626section. 9627 9628 9629File: as.info, Node: D30V-Chars, Next: D30V-Guarded, Prev: D30V-Subs, Up: D30V-Syntax 9630 96319.10.2.3 Special Characters 9632........................... 9633 9634A semicolon (';') can be used anywhere on a line to start a comment that 9635extends to the end of the line. 9636 9637 If a '#' appears as the first character of a line, the whole line is 9638treated as a comment, but in this case the line could also be a logical 9639line number directive (*note Comments::) or a preprocessor control 9640command (*note Preprocessing::). 9641 9642 Sub-instructions may be executed in order, in reverse-order, or in 9643parallel. Instructions listed in the standard one-per-line format will 9644be executed sequentially unless you use the '-O' option. 9645 9646 To specify the executing order, use the following symbols: 9647'->' 9648 Sequential with instruction on the left first. 9649 9650'<-' 9651 Sequential with instruction on the right first. 9652 9653'||' 9654 Parallel 9655 9656 The D30V syntax allows either one instruction per line, one 9657instruction per line with the execution symbol, or two instructions per 9658line. For example 9659'abs r2,r3 -> abs r4,r5' 9660 Execute these sequentially. The instruction on the right is in the 9661 right container and is executed second. 9662 9663'abs r2,r3 <- abs r4,r5' 9664 Execute these reverse-sequentially. The instruction on the right 9665 is in the right container, and is executed first. 9666 9667'abs r2,r3 || abs r4,r5' 9668 Execute these in parallel. 9669 9670'ldw r2,@(r3,r4) ||' 9671'mulx r6,r8,r9' 9672 Two-line format. Execute these in parallel. 9673 9674'mulx a0,r8,r9' 9675'stw r2,@(r3,r4)' 9676 Two-line format. Execute these sequentially unless '-O' option is 9677 used. If the '-O' option is used, the assembler will determine if 9678 the instructions could be done in parallel (the above two 9679 instructions can be done in parallel), and if so, emit them as 9680 parallel instructions. The assembler will put them in the proper 9681 containers. In the above example, the assembler will put the 'stw' 9682 instruction in left container and the 'mulx' instruction in the 9683 right container. 9684 9685'stw r2,@(r3,r4) ->' 9686'mulx a0,r8,r9' 9687 Two-line format. Execute the 'stw' instruction followed by the 9688 'mulx' instruction sequentially. The first instruction goes in the 9689 left container and the second instruction goes into right 9690 container. The assembler will give an error if the machine 9691 ordering constraints are violated. 9692 9693'stw r2,@(r3,r4) <-' 9694'mulx a0,r8,r9' 9695 Same as previous example, except that the 'mulx' instruction is 9696 executed before the 'stw' instruction. 9697 9698 Since '$' has no special meaning, you may use it in symbol names. 9699 9700 9701File: as.info, Node: D30V-Guarded, Next: D30V-Regs, Prev: D30V-Chars, Up: D30V-Syntax 9702 97039.10.2.4 Guarded Execution 9704.......................... 9705 9706'as' supports the full range of guarded execution directives for each 9707instruction. Just append the directive after the instruction proper. 9708The directives are: 9709 9710'/tx' 9711 Execute the instruction if flag f0 is true. 9712'/fx' 9713 Execute the instruction if flag f0 is false. 9714'/xt' 9715 Execute the instruction if flag f1 is true. 9716'/xf' 9717 Execute the instruction if flag f1 is false. 9718'/tt' 9719 Execute the instruction if both flags f0 and f1 are true. 9720'/tf' 9721 Execute the instruction if flag f0 is true and flag f1 is false. 9722 9723 9724File: as.info, Node: D30V-Regs, Next: D30V-Addressing, Prev: D30V-Guarded, Up: D30V-Syntax 9725 97269.10.2.5 Register Names 9727....................... 9728 9729You can use the predefined symbols 'r0' through 'r63' to refer to the 9730D30V registers. You can also use 'sp' as an alias for 'r63' and 'link' 9731as an alias for 'r62'. The accumulators are 'a0' and 'a1'. 9732 9733 The D30V also has predefined symbols for these control registers and 9734status bits: 9735'psw' 9736 Processor Status Word 9737'bpsw' 9738 Backup Processor Status Word 9739'pc' 9740 Program Counter 9741'bpc' 9742 Backup Program Counter 9743'rpt_c' 9744 Repeat Count 9745'rpt_s' 9746 Repeat Start address 9747'rpt_e' 9748 Repeat End address 9749'mod_s' 9750 Modulo Start address 9751'mod_e' 9752 Modulo End address 9753'iba' 9754 Instruction Break Address 9755'f0' 9756 Flag 0 9757'f1' 9758 Flag 1 9759'f2' 9760 Flag 2 9761'f3' 9762 Flag 3 9763'f4' 9764 Flag 4 9765'f5' 9766 Flag 5 9767'f6' 9768 Flag 6 9769'f7' 9770 Flag 7 9771's' 9772 Same as flag 4 (saturation flag) 9773'v' 9774 Same as flag 5 (overflow flag) 9775'va' 9776 Same as flag 6 (sticky overflow flag) 9777'c' 9778 Same as flag 7 (carry/borrow flag) 9779'b' 9780 Same as flag 7 (carry/borrow flag) 9781 9782 9783File: as.info, Node: D30V-Addressing, Prev: D30V-Regs, Up: D30V-Syntax 9784 97859.10.2.6 Addressing Modes 9786......................... 9787 9788'as' understands the following addressing modes for the D30V. 'RN' in 9789the following refers to any of the numbered registers, but _not_ the 9790control registers. 9791'RN' 9792 Register direct 9793'@RN' 9794 Register indirect 9795'@RN+' 9796 Register indirect with post-increment 9797'@RN-' 9798 Register indirect with post-decrement 9799'@-SP' 9800 Register indirect with pre-decrement 9801'@(DISP, RN)' 9802 Register indirect with displacement 9803'ADDR' 9804 PC relative address (for branch or rep). 9805'#IMM' 9806 Immediate data (the '#' is optional and ignored) 9807 9808 9809File: as.info, Node: D30V-Float, Next: D30V-Opcodes, Prev: D30V-Syntax, Up: D30V-Dependent 9810 98119.10.3 Floating Point 9812--------------------- 9813 9814The D30V has no hardware floating point, but the '.float' and '.double' 9815directives generates IEEE floating-point numbers for compatibility with 9816other development tools. 9817 9818 9819File: as.info, Node: D30V-Opcodes, Prev: D30V-Float, Up: D30V-Dependent 9820 98219.10.4 Opcodes 9822-------------- 9823 9824For detailed information on the D30V machine instruction set, see 'D30V 9825Architecture: A VLIW Microprocessor for Multimedia Applications' 9826(Mitsubishi Electric Corp.). 'as' implements all the standard D30V 9827opcodes. The only changes are those described in the section on size 9828modifiers 9829 9830 9831File: as.info, Node: Epiphany-Dependent, Next: H8/300-Dependent, Prev: D30V-Dependent, Up: Machine Dependencies 9832 98339.11 Epiphany Dependent Features 9834================================ 9835 9836* Menu: 9837 9838* Epiphany Options:: Options 9839* Epiphany Syntax:: Epiphany Syntax 9840 9841 9842File: as.info, Node: Epiphany Options, Next: Epiphany Syntax, Up: Epiphany-Dependent 9843 98449.11.1 Options 9845-------------- 9846 9847'as' has two additional command-line options for the Epiphany 9848architecture. 9849 9850'-mepiphany' 9851 Specifies that the both 32 and 16 bit instructions are allowed. 9852 This is the default behavior. 9853 9854'-mepiphany16' 9855 Restricts the permitted instructions to just the 16 bit set. 9856 9857 9858File: as.info, Node: Epiphany Syntax, Prev: Epiphany Options, Up: Epiphany-Dependent 9859 98609.11.2 Epiphany Syntax 9861---------------------- 9862 9863* Menu: 9864 9865* Epiphany-Chars:: Special Characters 9866 9867 9868File: as.info, Node: Epiphany-Chars, Up: Epiphany Syntax 9869 98709.11.2.1 Special Characters 9871........................... 9872 9873The presence of a ';' on a line indicates the start of a comment that 9874extends to the end of the current line. 9875 9876 If a '#' appears as the first character of a line then the whole line 9877is treated as a comment, but in this case the line could also be a 9878logical line number directive (*note Comments::) or a preprocessor 9879control command (*note Preprocessing::). 9880 9881 The '`' character can be used to separate statements on the same 9882line. 9883 9884 9885File: as.info, Node: H8/300-Dependent, Next: HPPA-Dependent, Prev: Epiphany-Dependent, Up: Machine Dependencies 9886 98879.12 H8/300 Dependent Features 9888============================== 9889 9890* Menu: 9891 9892* H8/300 Options:: Options 9893* H8/300 Syntax:: Syntax 9894* H8/300 Floating Point:: Floating Point 9895* H8/300 Directives:: H8/300 Machine Directives 9896* H8/300 Opcodes:: Opcodes 9897 9898 9899File: as.info, Node: H8/300 Options, Next: H8/300 Syntax, Up: H8/300-Dependent 9900 99019.12.1 Options 9902-------------- 9903 9904The Renesas H8/300 version of 'as' has one machine-dependent option: 9905 9906'-h-tick-hex' 9907 Support H'00 style hex constants in addition to 0x00 style. 9908 9909'-mach=NAME' 9910 Sets the H8300 machine variant. The following machine names are 9911 recognised: 'h8300h', 'h8300hn', 'h8300s', 'h8300sn', 'h8300sx' and 9912 'h8300sxn'. 9913 9914 9915File: as.info, Node: H8/300 Syntax, Next: H8/300 Floating Point, Prev: H8/300 Options, Up: H8/300-Dependent 9916 99179.12.2 Syntax 9918------------- 9919 9920* Menu: 9921 9922* H8/300-Chars:: Special Characters 9923* H8/300-Regs:: Register Names 9924* H8/300-Addressing:: Addressing Modes 9925 9926 9927File: as.info, Node: H8/300-Chars, Next: H8/300-Regs, Up: H8/300 Syntax 9928 99299.12.2.1 Special Characters 9930........................... 9931 9932';' is the line comment character. 9933 9934 '$' can be used instead of a newline to separate statements. 9935Therefore _you may not use '$' in symbol names_ on the H8/300. 9936 9937 9938File: as.info, Node: H8/300-Regs, Next: H8/300-Addressing, Prev: H8/300-Chars, Up: H8/300 Syntax 9939 99409.12.2.2 Register Names 9941....................... 9942 9943You can use predefined symbols of the form 'rNh' and 'rNl' to refer to 9944the H8/300 registers as sixteen 8-bit general-purpose registers. N is a 9945digit from '0' to '7'); for instance, both 'r0h' and 'r7l' are valid 9946register names. 9947 9948 You can also use the eight predefined symbols 'rN' to refer to the 9949H8/300 registers as 16-bit registers (you must use this form for 9950addressing). 9951 9952 On the H8/300H, you can also use the eight predefined symbols 'erN' 9953('er0' ... 'er7') to refer to the 32-bit general purpose registers. 9954 9955 The two control registers are called 'pc' (program counter; a 16-bit 9956register, except on the H8/300H where it is 24 bits) and 'ccr' 9957(condition code register; an 8-bit register). 'r7' is used as the stack 9958pointer, and can also be called 'sp'. 9959 9960 9961File: as.info, Node: H8/300-Addressing, Prev: H8/300-Regs, Up: H8/300 Syntax 9962 99639.12.2.3 Addressing Modes 9964......................... 9965 9966as understands the following addressing modes for the H8/300: 9967'rN' 9968 Register direct 9969 9970'@rN' 9971 Register indirect 9972 9973'@(D, rN)' 9974'@(D:16, rN)' 9975'@(D:24, rN)' 9976 Register indirect: 16-bit or 24-bit displacement D from register N. 9977 (24-bit displacements are only meaningful on the H8/300H.) 9978 9979'@rN+' 9980 Register indirect with post-increment 9981 9982'@-rN' 9983 Register indirect with pre-decrement 9984 9985'@AA' 9986'@AA:8' 9987'@AA:16' 9988'@AA:24' 9989 Absolute address 'aa'. (The address size ':24' only makes sense on 9990 the H8/300H.) 9991 9992'#XX' 9993'#XX:8' 9994'#XX:16' 9995'#XX:32' 9996 Immediate data XX. You may specify the ':8', ':16', or ':32' for 9997 clarity, if you wish; but 'as' neither requires this nor uses 9998 it--the data size required is taken from context. 9999 10000'@@AA' 10001'@@AA:8' 10002 Memory indirect. You may specify the ':8' for clarity, if you 10003 wish; but 'as' neither requires this nor uses it. 10004 10005 10006File: as.info, Node: H8/300 Floating Point, Next: H8/300 Directives, Prev: H8/300 Syntax, Up: H8/300-Dependent 10007 100089.12.3 Floating Point 10009--------------------- 10010 10011The H8/300 family has no hardware floating point, but the '.float' 10012directive generates IEEE floating-point numbers for compatibility with 10013other development tools. 10014 10015 10016File: as.info, Node: H8/300 Directives, Next: H8/300 Opcodes, Prev: H8/300 Floating Point, Up: H8/300-Dependent 10017 100189.12.4 H8/300 Machine Directives 10019-------------------------------- 10020 10021'as' has the following machine-dependent directives for the H8/300: 10022 10023'.h8300h' 10024 Recognize and emit additional instructions for the H8/300H variant, 10025 and also make '.int' emit 32-bit numbers rather than the usual 10026 (16-bit) for the H8/300 family. 10027 10028'.h8300s' 10029 Recognize and emit additional instructions for the H8S variant, and 10030 also make '.int' emit 32-bit numbers rather than the usual (16-bit) 10031 for the H8/300 family. 10032 10033'.h8300hn' 10034 Recognize and emit additional instructions for the H8/300H variant 10035 in normal mode, and also make '.int' emit 32-bit numbers rather 10036 than the usual (16-bit) for the H8/300 family. 10037 10038'.h8300sn' 10039 Recognize and emit additional instructions for the H8S variant in 10040 normal mode, and also make '.int' emit 32-bit numbers rather than 10041 the usual (16-bit) for the H8/300 family. 10042 10043 On the H8/300 family (including the H8/300H) '.word' directives 10044generate 16-bit numbers. 10045 10046 10047File: as.info, Node: H8/300 Opcodes, Prev: H8/300 Directives, Up: H8/300-Dependent 10048 100499.12.5 Opcodes 10050-------------- 10051 10052For detailed information on the H8/300 machine instruction set, see 10053'H8/300 Series Programming Manual'. For information specific to the 10054H8/300H, see 'H8/300H Series Programming Manual' (Renesas). 10055 10056 'as' implements all the standard H8/300 opcodes. No additional 10057pseudo-instructions are needed on this family. 10058 10059 The following table summarizes the H8/300 opcodes, and their 10060arguments. Entries marked '*' are opcodes used only on the H8/300H. 10061 10062 Legend: 10063 Rs source register 10064 Rd destination register 10065 abs absolute address 10066 imm immediate data 10067 disp:N N-bit displacement from a register 10068 pcrel:N N-bit displacement relative to program counter 10069 10070 add.b #imm,rd * andc #imm,ccr 10071 add.b rs,rd band #imm,rd 10072 add.w rs,rd band #imm,@rd 10073 * add.w #imm,rd band #imm,@abs:8 10074 * add.l rs,rd bra pcrel:8 10075 * add.l #imm,rd * bra pcrel:16 10076 adds #imm,rd bt pcrel:8 10077 addx #imm,rd * bt pcrel:16 10078 addx rs,rd brn pcrel:8 10079 and.b #imm,rd * brn pcrel:16 10080 and.b rs,rd bf pcrel:8 10081 * and.w rs,rd * bf pcrel:16 10082 * and.w #imm,rd bhi pcrel:8 10083 * and.l #imm,rd * bhi pcrel:16 10084 * and.l rs,rd bls pcrel:8 10085 * bls pcrel:16 bld #imm,rd 10086 bcc pcrel:8 bld #imm,@rd 10087 * bcc pcrel:16 bld #imm,@abs:8 10088 bhs pcrel:8 bnot #imm,rd 10089 * bhs pcrel:16 bnot #imm,@rd 10090 bcs pcrel:8 bnot #imm,@abs:8 10091 * bcs pcrel:16 bnot rs,rd 10092 blo pcrel:8 bnot rs,@rd 10093 * blo pcrel:16 bnot rs,@abs:8 10094 bne pcrel:8 bor #imm,rd 10095 * bne pcrel:16 bor #imm,@rd 10096 beq pcrel:8 bor #imm,@abs:8 10097 * beq pcrel:16 bset #imm,rd 10098 bvc pcrel:8 bset #imm,@rd 10099 * bvc pcrel:16 bset #imm,@abs:8 10100 bvs pcrel:8 bset rs,rd 10101 * bvs pcrel:16 bset rs,@rd 10102 bpl pcrel:8 bset rs,@abs:8 10103 * bpl pcrel:16 bsr pcrel:8 10104 bmi pcrel:8 bsr pcrel:16 10105 * bmi pcrel:16 bst #imm,rd 10106 bge pcrel:8 bst #imm,@rd 10107 * bge pcrel:16 bst #imm,@abs:8 10108 blt pcrel:8 btst #imm,rd 10109 * blt pcrel:16 btst #imm,@rd 10110 bgt pcrel:8 btst #imm,@abs:8 10111 * bgt pcrel:16 btst rs,rd 10112 ble pcrel:8 btst rs,@rd 10113 * ble pcrel:16 btst rs,@abs:8 10114 bclr #imm,rd bxor #imm,rd 10115 bclr #imm,@rd bxor #imm,@rd 10116 bclr #imm,@abs:8 bxor #imm,@abs:8 10117 bclr rs,rd cmp.b #imm,rd 10118 bclr rs,@rd cmp.b rs,rd 10119 bclr rs,@abs:8 cmp.w rs,rd 10120 biand #imm,rd cmp.w rs,rd 10121 biand #imm,@rd * cmp.w #imm,rd 10122 biand #imm,@abs:8 * cmp.l #imm,rd 10123 bild #imm,rd * cmp.l rs,rd 10124 bild #imm,@rd daa rs 10125 bild #imm,@abs:8 das rs 10126 bior #imm,rd dec.b rs 10127 bior #imm,@rd * dec.w #imm,rd 10128 bior #imm,@abs:8 * dec.l #imm,rd 10129 bist #imm,rd divxu.b rs,rd 10130 bist #imm,@rd * divxu.w rs,rd 10131 bist #imm,@abs:8 * divxs.b rs,rd 10132 bixor #imm,rd * divxs.w rs,rd 10133 bixor #imm,@rd eepmov 10134 bixor #imm,@abs:8 * eepmovw 10135 * exts.w rd mov.w rs,@abs:16 10136 * exts.l rd * mov.l #imm,rd 10137 * extu.w rd * mov.l rs,rd 10138 * extu.l rd * mov.l @rs,rd 10139 inc rs * mov.l @(disp:16,rs),rd 10140 * inc.w #imm,rd * mov.l @(disp:24,rs),rd 10141 * inc.l #imm,rd * mov.l @rs+,rd 10142 jmp @rs * mov.l @abs:16,rd 10143 jmp abs * mov.l @abs:24,rd 10144 jmp @@abs:8 * mov.l rs,@rd 10145 jsr @rs * mov.l rs,@(disp:16,rd) 10146 jsr abs * mov.l rs,@(disp:24,rd) 10147 jsr @@abs:8 * mov.l rs,@-rd 10148 ldc #imm,ccr * mov.l rs,@abs:16 10149 ldc rs,ccr * mov.l rs,@abs:24 10150 * ldc @abs:16,ccr movfpe @abs:16,rd 10151 * ldc @abs:24,ccr movtpe rs,@abs:16 10152 * ldc @(disp:16,rs),ccr mulxu.b rs,rd 10153 * ldc @(disp:24,rs),ccr * mulxu.w rs,rd 10154 * ldc @rs+,ccr * mulxs.b rs,rd 10155 * ldc @rs,ccr * mulxs.w rs,rd 10156 * mov.b @(disp:24,rs),rd neg.b rs 10157 * mov.b rs,@(disp:24,rd) * neg.w rs 10158 mov.b @abs:16,rd * neg.l rs 10159 mov.b rs,rd nop 10160 mov.b @abs:8,rd not.b rs 10161 mov.b rs,@abs:8 * not.w rs 10162 mov.b rs,rd * not.l rs 10163 mov.b #imm,rd or.b #imm,rd 10164 mov.b @rs,rd or.b rs,rd 10165 mov.b @(disp:16,rs),rd * or.w #imm,rd 10166 mov.b @rs+,rd * or.w rs,rd 10167 mov.b @abs:8,rd * or.l #imm,rd 10168 mov.b rs,@rd * or.l rs,rd 10169 mov.b rs,@(disp:16,rd) orc #imm,ccr 10170 mov.b rs,@-rd pop.w rs 10171 mov.b rs,@abs:8 * pop.l rs 10172 mov.w rs,@rd push.w rs 10173 * mov.w @(disp:24,rs),rd * push.l rs 10174 * mov.w rs,@(disp:24,rd) rotl.b rs 10175 * mov.w @abs:24,rd * rotl.w rs 10176 * mov.w rs,@abs:24 * rotl.l rs 10177 mov.w rs,rd rotr.b rs 10178 mov.w #imm,rd * rotr.w rs 10179 mov.w @rs,rd * rotr.l rs 10180 mov.w @(disp:16,rs),rd rotxl.b rs 10181 mov.w @rs+,rd * rotxl.w rs 10182 mov.w @abs:16,rd * rotxl.l rs 10183 mov.w rs,@(disp:16,rd) rotxr.b rs 10184 mov.w rs,@-rd * rotxr.w rs 10185 * rotxr.l rs * stc ccr,@(disp:24,rd) 10186 bpt * stc ccr,@-rd 10187 rte * stc ccr,@abs:16 10188 rts * stc ccr,@abs:24 10189 shal.b rs sub.b rs,rd 10190 * shal.w rs sub.w rs,rd 10191 * shal.l rs * sub.w #imm,rd 10192 shar.b rs * sub.l rs,rd 10193 * shar.w rs * sub.l #imm,rd 10194 * shar.l rs subs #imm,rd 10195 shll.b rs subx #imm,rd 10196 * shll.w rs subx rs,rd 10197 * shll.l rs * trapa #imm 10198 shlr.b rs xor #imm,rd 10199 * shlr.w rs xor rs,rd 10200 * shlr.l rs * xor.w #imm,rd 10201 sleep * xor.w rs,rd 10202 stc ccr,rd * xor.l #imm,rd 10203 * stc ccr,@rs * xor.l rs,rd 10204 * stc ccr,@(disp:16,rd) xorc #imm,ccr 10205 10206 Four H8/300 instructions ('add', 'cmp', 'mov', 'sub') are defined 10207with variants using the suffixes '.b', '.w', and '.l' to specify the 10208size of a memory operand. 'as' supports these suffixes, but does not 10209require them; since one of the operands is always a register, 'as' can 10210deduce the correct size. 10211 10212 For example, since 'r0' refers to a 16-bit register, 10213 mov r0,@foo 10214is equivalent to 10215 mov.w r0,@foo 10216 10217 If you use the size suffixes, 'as' issues a warning when the suffix 10218and the register size do not match. 10219 10220 10221File: as.info, Node: HPPA-Dependent, Next: ESA/390-Dependent, Prev: H8/300-Dependent, Up: Machine Dependencies 10222 102239.13 HPPA Dependent Features 10224============================ 10225 10226* Menu: 10227 10228* HPPA Notes:: Notes 10229* HPPA Options:: Options 10230* HPPA Syntax:: Syntax 10231* HPPA Floating Point:: Floating Point 10232* HPPA Directives:: HPPA Machine Directives 10233* HPPA Opcodes:: Opcodes 10234 10235 10236File: as.info, Node: HPPA Notes, Next: HPPA Options, Up: HPPA-Dependent 10237 102389.13.1 Notes 10239------------ 10240 10241As a back end for GNU CC 'as' has been throughly tested and should work 10242extremely well. We have tested it only minimally on hand written 10243assembly code and no one has tested it much on the assembly output from 10244the HP compilers. 10245 10246 The format of the debugging sections has changed since the original 10247'as' port (version 1.3X) was released; therefore, you must rebuild all 10248HPPA objects and libraries with the new assembler so that you can debug 10249the final executable. 10250 10251 The HPPA 'as' port generates a small subset of the relocations 10252available in the SOM and ELF object file formats. Additional relocation 10253support will be added as it becomes necessary. 10254 10255 10256File: as.info, Node: HPPA Options, Next: HPPA Syntax, Prev: HPPA Notes, Up: HPPA-Dependent 10257 102589.13.2 Options 10259-------------- 10260 10261'as' has no machine-dependent command-line options for the HPPA. 10262 10263 10264File: as.info, Node: HPPA Syntax, Next: HPPA Floating Point, Prev: HPPA Options, Up: HPPA-Dependent 10265 102669.13.3 Syntax 10267------------- 10268 10269The assembler syntax closely follows the HPPA instruction set reference 10270manual; assembler directives and general syntax closely follow the HPPA 10271assembly language reference manual, with a few noteworthy differences. 10272 10273 First, a colon may immediately follow a label definition. This is 10274simply for compatibility with how most assembly language programmers 10275write code. 10276 10277 Some obscure expression parsing problems may affect hand written code 10278which uses the 'spop' instructions, or code which makes significant use 10279of the '!' line separator. 10280 10281 'as' is much less forgiving about missing arguments and other similar 10282oversights than the HP assembler. 'as' notifies you of missing 10283arguments as syntax errors; this is regarded as a feature, not a bug. 10284 10285 Finally, 'as' allows you to use an external symbol without explicitly 10286importing the symbol. _Warning:_ in the future this will be an error 10287for HPPA targets. 10288 10289 Special characters for HPPA targets include: 10290 10291 ';' is the line comment character. 10292 10293 '!' can be used instead of a newline to separate statements. 10294 10295 Since '$' has no special meaning, you may use it in symbol names. 10296 10297 10298File: as.info, Node: HPPA Floating Point, Next: HPPA Directives, Prev: HPPA Syntax, Up: HPPA-Dependent 10299 103009.13.4 Floating Point 10301--------------------- 10302 10303The HPPA family uses IEEE floating-point numbers. 10304 10305 10306File: as.info, Node: HPPA Directives, Next: HPPA Opcodes, Prev: HPPA Floating Point, Up: HPPA-Dependent 10307 103089.13.5 HPPA Assembler Directives 10309-------------------------------- 10310 10311'as' for the HPPA supports many additional directives for compatibility 10312with the native assembler. This section describes them only briefly. 10313For detailed information on HPPA-specific assembler directives, see 10314'HP9000 Series 800 Assembly Language Reference Manual' (HP 92432-90001). 10315 10316 'as' does _not_ support the following assembler directives described 10317in the HP manual: 10318 10319 .endm .liston 10320 .enter .locct 10321 .leave .macro 10322 .listoff 10323 10324 Beyond those implemented for compatibility, 'as' supports one 10325additional assembler directive for the HPPA: '.param'. It conveys 10326register argument locations for static functions. Its syntax closely 10327follows the '.export' directive. 10328 10329 These are the additional directives in 'as' for the HPPA: 10330 10331'.block N' 10332'.blockz N' 10333 Reserve N bytes of storage, and initialize them to zero. 10334 10335'.call' 10336 Mark the beginning of a procedure call. Only the special case with 10337 _no arguments_ is allowed. 10338 10339'.callinfo [ PARAM=VALUE, ... ] [ FLAG, ... ]' 10340 Specify a number of parameters and flags that define the 10341 environment for a procedure. 10342 10343 PARAM may be any of 'frame' (frame size), 'entry_gr' (end of 10344 general register range), 'entry_fr' (end of float register range), 10345 'entry_sr' (end of space register range). 10346 10347 The values for FLAG are 'calls' or 'caller' (proc has subroutines), 10348 'no_calls' (proc does not call subroutines), 'save_rp' (preserve 10349 return pointer), 'save_sp' (proc preserves stack pointer), 10350 'no_unwind' (do not unwind this proc), 'hpux_int' (proc is 10351 interrupt routine). 10352 10353'.code' 10354 Assemble into the standard section called '$TEXT$', subsection 10355 '$CODE$'. 10356 10357'.copyright "STRING"' 10358 In the SOM object format, insert STRING into the object code, 10359 marked as a copyright string. 10360 10361'.copyright "STRING"' 10362 In the ELF object format, insert STRING into the object code, 10363 marked as a version string. 10364 10365'.enter' 10366 Not yet supported; the assembler rejects programs containing this 10367 directive. 10368 10369'.entry' 10370 Mark the beginning of a procedure. 10371 10372'.exit' 10373 Mark the end of a procedure. 10374 10375'.export NAME [ ,TYP ] [ ,PARAM=R ]' 10376 Make a procedure NAME available to callers. TYP, if present, must 10377 be one of 'absolute', 'code' (ELF only, not SOM), 'data', 'entry', 10378 'data', 'entry', 'millicode', 'plabel', 'pri_prog', or 'sec_prog'. 10379 10380 PARAM, if present, provides either relocation information for the 10381 procedure arguments and result, or a privilege level. PARAM may be 10382 'argwN' (where N ranges from '0' to '3', and indicates one of four 10383 one-word arguments); 'rtnval' (the procedure's result); or 10384 'priv_lev' (privilege level). For arguments or the result, R 10385 specifies how to relocate, and must be one of 'no' (not 10386 relocatable), 'gr' (argument is in general register), 'fr' (in 10387 floating point register), or 'fu' (upper half of float register). 10388 For 'priv_lev', R is an integer. 10389 10390'.half N' 10391 Define a two-byte integer constant N; synonym for the portable 'as' 10392 directive '.short'. 10393 10394'.import NAME [ ,TYP ]' 10395 Converse of '.export'; make a procedure available to call. The 10396 arguments use the same conventions as the first two arguments for 10397 '.export'. 10398 10399'.label NAME' 10400 Define NAME as a label for the current assembly location. 10401 10402'.leave' 10403 Not yet supported; the assembler rejects programs containing this 10404 directive. 10405 10406'.origin LC' 10407 Advance location counter to LC. Synonym for the 'as' portable 10408 directive '.org'. 10409 10410'.param NAME [ ,TYP ] [ ,PARAM=R ]' 10411 Similar to '.export', but used for static procedures. 10412 10413'.proc' 10414 Use preceding the first statement of a procedure. 10415 10416'.procend' 10417 Use following the last statement of a procedure. 10418 10419'LABEL .reg EXPR' 10420 Synonym for '.equ'; define LABEL with the absolute expression EXPR 10421 as its value. 10422 10423'.space SECNAME [ ,PARAMS ]' 10424 Switch to section SECNAME, creating a new section by that name if 10425 necessary. You may only use PARAMS when creating a new section, 10426 not when switching to an existing one. SECNAME may identify a 10427 section by number rather than by name. 10428 10429 If specified, the list PARAMS declares attributes of the section, 10430 identified by keywords. The keywords recognized are 'spnum=EXP' 10431 (identify this section by the number EXP, an absolute expression), 10432 'sort=EXP' (order sections according to this sort key when linking; 10433 EXP is an absolute expression), 'unloadable' (section contains no 10434 loadable data), 'notdefined' (this section defined elsewhere), and 10435 'private' (data in this section not available to other programs). 10436 10437'.spnum SECNAM' 10438 Allocate four bytes of storage, and initialize them with the 10439 section number of the section named SECNAM. (You can define the 10440 section number with the HPPA '.space' directive.) 10441 10442'.string "STR"' 10443 Copy the characters in the string STR to the object file. *Note 10444 Strings: Strings, for information on escape sequences you can use 10445 in 'as' strings. 10446 10447 _Warning!_ The HPPA version of '.string' differs from the usual 10448 'as' definition: it does _not_ write a zero byte after copying STR. 10449 10450'.stringz "STR"' 10451 Like '.string', but appends a zero byte after copying STR to object 10452 file. 10453 10454'.subspa NAME [ ,PARAMS ]' 10455'.nsubspa NAME [ ,PARAMS ]' 10456 Similar to '.space', but selects a subsection NAME within the 10457 current section. You may only specify PARAMS when you create a 10458 subsection (in the first instance of '.subspa' for this NAME). 10459 10460 If specified, the list PARAMS declares attributes of the 10461 subsection, identified by keywords. The keywords recognized are 10462 'quad=EXPR' ("quadrant" for this subsection), 'align=EXPR' 10463 (alignment for beginning of this subsection; a power of two), 10464 'access=EXPR' (value for "access rights" field), 'sort=EXPR' 10465 (sorting order for this subspace in link), 'code_only' (subsection 10466 contains only code), 'unloadable' (subsection cannot be loaded into 10467 memory), 'comdat' (subsection is comdat), 'common' (subsection is 10468 common block), 'dup_comm' (subsection may have duplicate names), or 10469 'zero' (subsection is all zeros, do not write in object file). 10470 10471 '.nsubspa' always creates a new subspace with the given name, even 10472 if one with the same name already exists. 10473 10474 'comdat', 'common' and 'dup_comm' can be used to implement various 10475 flavors of one-only support when using the SOM linker. The SOM 10476 linker only supports specific combinations of these flags. The 10477 details are not documented. A brief description is provided here. 10478 10479 'comdat' provides a form of linkonce support. It is useful for 10480 both code and data subspaces. A 'comdat' subspace has a key symbol 10481 marked by the 'is_comdat' flag or 'ST_COMDAT'. Only the first 10482 subspace for any given key is selected. The key symbol becomes 10483 universal in shared links. This is similar to the behavior of 10484 'secondary_def' symbols. 10485 10486 'common' provides Fortran named common support. It is only useful 10487 for data subspaces. Symbols with the flag 'is_common' retain this 10488 flag in shared links. Referencing a 'is_common' symbol in a shared 10489 library from outside the library doesn't work. Thus, 'is_common' 10490 symbols must be output whenever they are needed. 10491 10492 'common' and 'dup_comm' together provide Cobol common support. The 10493 subspaces in this case must all be the same length. Otherwise, 10494 this support is similar to the Fortran common support. 10495 10496 'dup_comm' by itself provides a type of one-only support for code. 10497 Only the first 'dup_comm' subspace is selected. There is a rather 10498 complex algorithm to compare subspaces. Code symbols marked with 10499 the 'dup_common' flag are hidden. This support was intended for 10500 "C++ duplicate inlines". 10501 10502 A simplified technique is used to mark the flags of symbols based 10503 on the flags of their subspace. A symbol with the scope 10504 SS_UNIVERSAL and type ST_ENTRY, ST_CODE or ST_DATA is marked with 10505 the corresponding settings of 'comdat', 'common' and 'dup_comm' 10506 from the subspace, respectively. This avoids having to introduce 10507 additional directives to mark these symbols. The HP assembler sets 10508 'is_common' from 'common'. However, it doesn't set the 10509 'dup_common' from 'dup_comm'. It doesn't have 'comdat' support. 10510 10511'.version "STR"' 10512 Write STR as version identifier in object code. 10513 10514 10515File: as.info, Node: HPPA Opcodes, Prev: HPPA Directives, Up: HPPA-Dependent 10516 105179.13.6 Opcodes 10518-------------- 10519 10520For detailed information on the HPPA machine instruction set, see 10521'PA-RISC Architecture and Instruction Set Reference Manual' (HP 1052209740-90039). 10523 10524 10525File: as.info, Node: ESA/390-Dependent, Next: i386-Dependent, Prev: HPPA-Dependent, Up: Machine Dependencies 10526 105279.14 ESA/390 Dependent Features 10528=============================== 10529 10530* Menu: 10531 10532* ESA/390 Notes:: Notes 10533* ESA/390 Options:: Options 10534* ESA/390 Syntax:: Syntax 10535* ESA/390 Floating Point:: Floating Point 10536* ESA/390 Directives:: ESA/390 Machine Directives 10537* ESA/390 Opcodes:: Opcodes 10538 10539 10540File: as.info, Node: ESA/390 Notes, Next: ESA/390 Options, Up: ESA/390-Dependent 10541 105429.14.1 Notes 10543------------ 10544 10545The ESA/390 'as' port is currently intended to be a back-end for the GNU 10546CC compiler. It is not HLASM compatible, although it does support a 10547subset of some of the HLASM directives. The only supported binary file 10548format is ELF; none of the usual MVS/VM/OE/USS object file formats, such 10549as ESD or XSD, are supported. 10550 10551 When used with the GNU CC compiler, the ESA/390 'as' will produce 10552correct, fully relocated, functional binaries, and has been used to 10553compile and execute large projects. However, many aspects should still 10554be considered experimental; these include shared library support, 10555dynamically loadable objects, and any relocation other than the 31-bit 10556relocation. 10557 10558 10559File: as.info, Node: ESA/390 Options, Next: ESA/390 Syntax, Prev: ESA/390 Notes, Up: ESA/390-Dependent 10560 105619.14.2 Options 10562-------------- 10563 10564'as' has no machine-dependent command-line options for the ESA/390. 10565 10566 10567File: as.info, Node: ESA/390 Syntax, Next: ESA/390 Floating Point, Prev: ESA/390 Options, Up: ESA/390-Dependent 10568 105699.14.3 Syntax 10570------------- 10571 10572The opcode/operand syntax follows the ESA/390 Principles of Operation 10573manual; assembler directives and general syntax are loosely based on the 10574prevailing AT&T/SVR4/ELF/Solaris style notation. HLASM-style directives 10575are _not_ supported for the most part, with the exception of those 10576described herein. 10577 10578 A leading dot in front of directives is optional, and the case of 10579directives is ignored; thus for example, .using and USING have the same 10580effect. 10581 10582 A colon may immediately follow a label definition. This is simply 10583for compatibility with how most assembly language programmers write 10584code. 10585 10586 '#' is the line comment character. 10587 10588 ';' can be used instead of a newline to separate statements. 10589 10590 Since '$' has no special meaning, you may use it in symbol names. 10591 10592 Registers can be given the symbolic names r0..r15, fp0, fp2, fp4, 10593fp6. By using thesse symbolic names, 'as' can detect simple syntax 10594errors. The name rarg or r.arg is a synonym for r11, rtca or r.tca for 10595r12, sp, r.sp, dsa r.dsa for r13, lr or r.lr for r14, rbase or r.base 10596for r3 and rpgt or r.pgt for r4. 10597 10598 '*' is the current location counter. Unlike '.' it is always 10599relative to the last USING directive. Note that this means that 10600expressions cannot use multiplication, as any occurrence of '*' will be 10601interpreted as a location counter. 10602 10603 All labels are relative to the last USING. Thus, branches to a label 10604always imply the use of base+displacement. 10605 10606 Many of the usual forms of address constants / address literals are 10607supported. Thus, 10608 .using *,r3 10609 L r15,=A(some_routine) 10610 LM r6,r7,=V(some_longlong_extern) 10611 A r1,=F'12' 10612 AH r0,=H'42' 10613 ME r6,=E'3.1416' 10614 MD r6,=D'3.14159265358979' 10615 O r6,=XL4'cacad0d0' 10616 .ltorg 10617 should all behave as expected: that is, an entry in the literal pool 10618will be created (or reused if it already exists), and the instruction 10619operands will be the displacement into the literal pool using the 10620current base register (as last declared with the '.using' directive). 10621 10622 10623File: as.info, Node: ESA/390 Floating Point, Next: ESA/390 Directives, Prev: ESA/390 Syntax, Up: ESA/390-Dependent 10624 106259.14.4 Floating Point 10626--------------------- 10627 10628The assembler generates only IEEE floating-point numbers. The older 10629floating point formats are not supported. 10630 10631 10632File: as.info, Node: ESA/390 Directives, Next: ESA/390 Opcodes, Prev: ESA/390 Floating Point, Up: ESA/390-Dependent 10633 106349.14.5 ESA/390 Assembler Directives 10635----------------------------------- 10636 10637'as' for the ESA/390 supports all of the standard ELF/SVR4 assembler 10638directives that are documented in the main part of this documentation. 10639Several additional directives are supported in order to implement the 10640ESA/390 addressing model. The most important of these are '.using' and 10641'.ltorg' 10642 10643 These are the additional directives in 'as' for the ESA/390: 10644 10645'.dc' 10646 A small subset of the usual DC directive is supported. 10647 10648'.drop REGNO' 10649 Stop using REGNO as the base register. The REGNO must have been 10650 previously declared with a '.using' directive in the same section 10651 as the current section. 10652 10653'.ebcdic STRING' 10654 Emit the EBCDIC equivalent of the indicated string. The emitted 10655 string will be null terminated. Note that the directives '.string' 10656 etc. emit ascii strings by default. 10657 10658'EQU' 10659 The standard HLASM-style EQU directive is not supported; however, 10660 the standard 'as' directive .equ can be used to the same effect. 10661 10662'.ltorg' 10663 Dump the literal pool accumulated so far; begin a new literal pool. 10664 The literal pool will be written in the current section; in order 10665 to generate correct assembly, a '.using' must have been previously 10666 specified in the same section. 10667 10668'.using EXPR,REGNO' 10669 Use REGNO as the base register for all subsequent RX, RS, and SS 10670 form instructions. The EXPR will be evaluated to obtain the base 10671 address; usually, EXPR will merely be '*'. 10672 10673 This assembler allows two '.using' directives to be simultaneously 10674 outstanding, one in the '.text' section, and one in another section 10675 (typically, the '.data' section). This feature allows dynamically 10676 loaded objects to be implemented in a relatively straightforward 10677 way. A '.using' directive must always be specified in the '.text' 10678 section; this will specify the base register that will be used for 10679 branches in the '.text' section. A second '.using' may be 10680 specified in another section; this will specify the base register 10681 that is used for non-label address literals. When a second 10682 '.using' is specified, then the subsequent '.ltorg' must be put in 10683 the same section; otherwise an error will result. 10684 10685 Thus, for example, the following code uses 'r3' to address branch 10686 targets and 'r4' to address the literal pool, which has been 10687 written to the '.data' section. The is, the constants 10688 '=A(some_routine)', '=H'42'' and '=E'3.1416'' will all appear in 10689 the '.data' section. 10690 10691 .data 10692 .using LITPOOL,r4 10693 .text 10694 BASR r3,0 10695 .using *,r3 10696 B START 10697 .long LITPOOL 10698 START: 10699 L r4,4(,r3) 10700 L r15,=A(some_routine) 10701 LTR r15,r15 10702 BNE LABEL 10703 AH r0,=H'42' 10704 LABEL: 10705 ME r6,=E'3.1416' 10706 .data 10707 LITPOOL: 10708 .ltorg 10709 10710 Note that this dual-'.using' directive semantics extends and is not 10711 compatible with HLASM semantics. Note that this assembler 10712 directive does not support the full range of HLASM semantics. 10713 10714 10715File: as.info, Node: ESA/390 Opcodes, Prev: ESA/390 Directives, Up: ESA/390-Dependent 10716 107179.14.6 Opcodes 10718-------------- 10719 10720For detailed information on the ESA/390 machine instruction set, see 10721'ESA/390 Principles of Operation' (IBM Publication Number DZ9AR004). 10722 10723 10724File: as.info, Node: i386-Dependent, Next: i860-Dependent, Prev: ESA/390-Dependent, Up: Machine Dependencies 10725 107269.15 80386 Dependent Features 10727============================= 10728 10729The i386 version 'as' supports both the original Intel 386 architecture 10730in both 16 and 32-bit mode as well as AMD x86-64 architecture extending 10731the Intel architecture to 64-bits. 10732 10733* Menu: 10734 10735* i386-Options:: Options 10736* i386-Directives:: X86 specific directives 10737* i386-Syntax:: Syntactical considerations 10738* i386-Mnemonics:: Instruction Naming 10739* i386-Regs:: Register Naming 10740* i386-Prefixes:: Instruction Prefixes 10741* i386-Memory:: Memory References 10742* i386-Jumps:: Handling of Jump Instructions 10743* i386-Float:: Floating Point 10744* i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations 10745* i386-LWP:: AMD's Lightweight Profiling Instructions 10746* i386-BMI:: Bit Manipulation Instruction 10747* i386-TBM:: AMD's Trailing Bit Manipulation Instructions 10748* i386-16bit:: Writing 16-bit Code 10749* i386-Arch:: Specifying an x86 CPU architecture 10750* i386-Bugs:: AT&T Syntax bugs 10751* i386-Notes:: Notes 10752 10753 10754File: as.info, Node: i386-Options, Next: i386-Directives, Up: i386-Dependent 10755 107569.15.1 Options 10757-------------- 10758 10759The i386 version of 'as' has a few machine dependent options: 10760 10761'--32 | --x32 | --64' 10762 Select the word size, either 32 bits or 64 bits. '--32' implies 10763 Intel i386 architecture, while '--x32' and '--64' imply AMD x86-64 10764 architecture with 32-bit or 64-bit word-size respectively. 10765 10766 These options are only available with the ELF object file format, 10767 and require that the necessary BFD support has been included (on a 10768 32-bit platform you have to add -enable-64-bit-bfd to configure 10769 enable 64-bit usage and use x86-64 as target platform). 10770 10771'-n' 10772 By default, x86 GAS replaces multiple nop instructions used for 10773 alignment within code sections with multi-byte nop instructions 10774 such as leal 0(%esi,1),%esi. This switch disables the 10775 optimization. 10776 10777'--divide' 10778 On SVR4-derived platforms, the character '/' is treated as a 10779 comment character, which means that it cannot be used in 10780 expressions. The '--divide' option turns '/' into a normal 10781 character. This does not disable '/' at the beginning of a line 10782 starting a comment, or affect using '#' for starting a comment. 10783 10784'-march=CPU[+EXTENSION...]' 10785 This option specifies the target processor. The assembler will 10786 issue an error message if an attempt is made to assemble an 10787 instruction which will not execute on the target processor. The 10788 following processor names are recognized: 'i8086', 'i186', 'i286', 10789 'i386', 'i486', 'i586', 'i686', 'pentium', 'pentiumpro', 10790 'pentiumii', 'pentiumiii', 'pentium4', 'prescott', 'nocona', 10791 'core', 'core2', 'corei7', 'l1om', 'k1om', 'iamcu', 'k6', 'k6_2', 10792 'athlon', 'opteron', 'k8', 'amdfam10', 'bdver1', 'bdver2', 10793 'bdver3', 'bdver4', 'znver1', 'btver1', 'btver2', 'generic32' and 10794 'generic64'. 10795 10796 In addition to the basic instruction set, the assembler can be told 10797 to accept various extension mnemonics. For example, 10798 '-march=i686+sse4+vmx' extends I686 with SSE4 and VMX. The 10799 following extensions are currently supported: '8087', '287', '387', 10800 '687', 'no87', 'no287', 'no387', 'no687', 'mmx', 'nommx', 'sse', 10801 'sse2', 'sse3', 'ssse3', 'sse4.1', 'sse4.2', 'sse4', 'nosse', 10802 'nosse2', 'nosse3', 'nossse3', 'nosse4.1', 'nosse4.2', 'nosse4', 10803 'avx', 'avx2', 'noavx', 'noavx2', 'adx', 'rdseed', 'prfchw', 10804 'smap', 'mpx', 'sha', 'rdpid', 'ptwrite', 'prefetchwt1', 10805 'clflushopt', 'se1', 'clwb', 'avx512f', 'avx512cd', 'avx512er', 10806 'avx512pf', 'avx512vl', 'avx512bw', 'avx512dq', 'avx512ifma', 10807 'avx512vbmi', 'avx512_4fmaps', 'avx512_4vnniw', 'avx512_vpopcntdq', 10808 'noavx512f', 'noavx512cd', 'noavx512er', 'noavx512pf', 10809 'noavx512vl', 'noavx512bw', 'noavx512dq', 'noavx512ifma', 10810 'noavx512vbmi', 'noavx512_4fmaps', 'noavx512_4vnniw', 10811 'noavx512_vpopcntdq', 'vmx', 'vmfunc', 'smx', 'xsave', 'xsaveopt', 10812 'xsavec', 'xsaves', 'aes', 'pclmul', 'fsgsbase', 'rdrnd', 'f16c', 10813 'bmi2', 'fma', 'movbe', 'ept', 'lzcnt', 'hle', 'rtm', 'invpcid', 10814 'clflush', 'mwaitx', 'clzero', 'lwp', 'fma4', 'xop', 'cx16', 10815 'syscall', 'rdtscp', '3dnow', '3dnowa', 'sse4a', 'sse5', 'svme', 10816 'abm' and 'padlock'. Note that rather than extending a basic 10817 instruction set, the extension mnemonics starting with 'no' revoke 10818 the respective functionality. 10819 10820 When the '.arch' directive is used with '-march', the '.arch' 10821 directive will take precedent. 10822 10823'-mtune=CPU' 10824 This option specifies a processor to optimize for. When used in 10825 conjunction with the '-march' option, only instructions of the 10826 processor specified by the '-march' option will be generated. 10827 10828 Valid CPU values are identical to the processor list of 10829 '-march=CPU'. 10830 10831'-msse2avx' 10832 This option specifies that the assembler should encode SSE 10833 instructions with VEX prefix. 10834 10835'-msse-check=NONE' 10836'-msse-check=WARNING' 10837'-msse-check=ERROR' 10838 These options control if the assembler should check SSE 10839 instructions. '-msse-check=NONE' will make the assembler not to 10840 check SSE instructions, which is the default. 10841 '-msse-check=WARNING' will make the assembler issue a warning for 10842 any SSE instruction. '-msse-check=ERROR' will make the assembler 10843 issue an error for any SSE instruction. 10844 10845'-mavxscalar=128' 10846'-mavxscalar=256' 10847 These options control how the assembler should encode scalar AVX 10848 instructions. '-mavxscalar=128' will encode scalar AVX 10849 instructions with 128bit vector length, which is the default. 10850 '-mavxscalar=256' will encode scalar AVX instructions with 256bit 10851 vector length. 10852 10853'-mevexlig=128' 10854'-mevexlig=256' 10855'-mevexlig=512' 10856 These options control how the assembler should encode 10857 length-ignored (LIG) EVEX instructions. '-mevexlig=128' will 10858 encode LIG EVEX instructions with 128bit vector length, which is 10859 the default. '-mevexlig=256' and '-mevexlig=512' will encode LIG 10860 EVEX instructions with 256bit and 512bit vector length, 10861 respectively. 10862 10863'-mevexwig=0' 10864'-mevexwig=1' 10865 These options control how the assembler should encode w-ignored 10866 (WIG) EVEX instructions. '-mevexwig=0' will encode WIG EVEX 10867 instructions with evex.w = 0, which is the default. '-mevexwig=1' 10868 will encode WIG EVEX instructions with evex.w = 1. 10869 10870'-mmnemonic=ATT' 10871'-mmnemonic=INTEL' 10872 This option specifies instruction mnemonic for matching 10873 instructions. The '.att_mnemonic' and '.intel_mnemonic' directives 10874 will take precedent. 10875 10876'-msyntax=ATT' 10877'-msyntax=INTEL' 10878 This option specifies instruction syntax when processing 10879 instructions. The '.att_syntax' and '.intel_syntax' directives 10880 will take precedent. 10881 10882'-mnaked-reg' 10883 This opetion specifies that registers don't require a '%' prefix. 10884 The '.att_syntax' and '.intel_syntax' directives will take 10885 precedent. 10886 10887'-madd-bnd-prefix' 10888 This option forces the assembler to add BND prefix to all branches, 10889 even if such prefix was not explicitly specified in the source 10890 code. 10891 10892'-mno-shared' 10893 On ELF target, the assembler normally optimizes out non-PLT 10894 relocations against defined non-weak global branch targets with 10895 default visibility. The '-mshared' option tells the assembler to 10896 generate code which may go into a shared library where all non-weak 10897 global branch targets with default visibility can be preempted. 10898 The resulting code is slightly bigger. This option only affects 10899 the handling of branch instructions. 10900 10901'-mbig-obj' 10902 On x86-64 PE/COFF target this option forces the use of big object 10903 file format, which allows more than 32768 sections. 10904 10905'-momit-lock-prefix=NO' 10906'-momit-lock-prefix=YES' 10907 These options control how the assembler should encode lock prefix. 10908 This option is intended as a workaround for processors, that fail 10909 on lock prefix. This option can only be safely used with 10910 single-core, single-thread computers '-momit-lock-prefix=YES' will 10911 omit all lock prefixes. '-momit-lock-prefix=NO' will encode lock 10912 prefix as usual, which is the default. 10913 10914'-mfence-as-lock-add=NO' 10915'-mfence-as-lock-add=YES' 10916 These options control how the assembler should encode lfence, 10917 mfence and sfence. '-mfence-as-lock-add=YES' will encode lfence, 10918 mfence and sfence as 'lock addl $0x0, (%rsp)' in 64-bit mode and 10919 'lock addl $0x0, (%esp)' in 32-bit mode. '-mfence-as-lock-add=NO' 10920 will encode lfence, mfence and sfence as usual, which is the 10921 default. 10922 10923'-mrelax-relocations=NO' 10924'-mrelax-relocations=YES' 10925 These options control whether the assembler should generate relax 10926 relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX 10927 and R_X86_64_REX_GOTPCRELX, in 64-bit mode. 10928 '-mrelax-relocations=YES' will generate relax relocations. 10929 '-mrelax-relocations=NO' will not generate relax relocations. The 10930 default can be controlled by a configure option 10931 '--enable-x86-relax-relocations'. 10932 10933'-mevexrcig=RNE' 10934'-mevexrcig=RD' 10935'-mevexrcig=RU' 10936'-mevexrcig=RZ' 10937 These options control how the assembler should encode SAE-only EVEX 10938 instructions. '-mevexrcig=RNE' will encode RC bits of EVEX 10939 instruction with 00, which is the default. '-mevexrcig=RD', 10940 '-mevexrcig=RU' and '-mevexrcig=RZ' will encode SAE-only EVEX 10941 instructions with 01, 10 and 11 RC bits, respectively. 10942 10943'-mamd64' 10944'-mintel64' 10945 This option specifies that the assembler should accept only AMD64 10946 or Intel64 ISA in 64-bit mode. The default is to accept both. 10947 10948 10949File: as.info, Node: i386-Directives, Next: i386-Syntax, Prev: i386-Options, Up: i386-Dependent 10950 109519.15.2 x86 specific Directives 10952------------------------------ 10953 10954'.lcomm SYMBOL , LENGTH[, ALIGNMENT]' 10955 Reserve LENGTH (an absolute expression) bytes for a local common 10956 denoted by SYMBOL. The section and value of SYMBOL are those of 10957 the new local common. The addresses are allocated in the bss 10958 section, so that at run-time the bytes start off zeroed. Since 10959 SYMBOL is not declared global, it is normally not visible to 'ld'. 10960 The optional third parameter, ALIGNMENT, specifies the desired 10961 alignment of the symbol in the bss section. 10962 10963 This directive is only available for COFF based x86 targets. 10964 10965 10966File: as.info, Node: i386-Syntax, Next: i386-Mnemonics, Prev: i386-Directives, Up: i386-Dependent 10967 109689.15.3 i386 Syntactical Considerations 10969-------------------------------------- 10970 10971* Menu: 10972 10973* i386-Variations:: AT&T Syntax versus Intel Syntax 10974* i386-Chars:: Special Characters 10975 10976 10977File: as.info, Node: i386-Variations, Next: i386-Chars, Up: i386-Syntax 10978 109799.15.3.1 AT&T Syntax versus Intel Syntax 10980........................................ 10981 10982'as' now supports assembly using Intel assembler syntax. 10983'.intel_syntax' selects Intel mode, and '.att_syntax' switches back to 10984the usual AT&T mode for compatibility with the output of 'gcc'. Either 10985of these directives may have an optional argument, 'prefix', or 10986'noprefix' specifying whether registers require a '%' prefix. AT&T 10987System V/386 assembler syntax is quite different from Intel syntax. We 10988mention these differences because almost all 80386 documents use Intel 10989syntax. Notable differences between the two syntaxes are: 10990 10991 * AT&T immediate operands are preceded by '$'; Intel immediate 10992 operands are undelimited (Intel 'push 4' is AT&T 'pushl $4'). AT&T 10993 register operands are preceded by '%'; Intel register operands are 10994 undelimited. AT&T absolute (as opposed to PC relative) jump/call 10995 operands are prefixed by '*'; they are undelimited in Intel syntax. 10996 10997 * AT&T and Intel syntax use the opposite order for source and 10998 destination operands. Intel 'add eax, 4' is 'addl $4, %eax'. The 10999 'source, dest' convention is maintained for compatibility with 11000 previous Unix assemblers. Note that 'bound', 'invlpga', and 11001 instructions with 2 immediate operands, such as the 'enter' 11002 instruction, do _not_ have reversed order. *note i386-Bugs::. 11003 11004 * In AT&T syntax the size of memory operands is determined from the 11005 last character of the instruction mnemonic. Mnemonic suffixes of 11006 'b', 'w', 'l' and 'q' specify byte (8-bit), word (16-bit), long 11007 (32-bit) and quadruple word (64-bit) memory references. Intel 11008 syntax accomplishes this by prefixing memory operands (_not_ the 11009 instruction mnemonics) with 'byte ptr', 'word ptr', 'dword ptr' and 11010 'qword ptr'. Thus, Intel 'mov al, byte ptr FOO' is 'movb FOO, %al' 11011 in AT&T syntax. 11012 11013 In 64-bit code, 'movabs' can be used to encode the 'mov' 11014 instruction with the 64-bit displacement or immediate operand. 11015 11016 * Immediate form long jumps and calls are 'lcall/ljmp $SECTION, 11017 $OFFSET' in AT&T syntax; the Intel syntax is 'call/jmp far 11018 SECTION:OFFSET'. Also, the far return instruction is 'lret 11019 $STACK-ADJUST' in AT&T syntax; Intel syntax is 'ret far 11020 STACK-ADJUST'. 11021 11022 * The AT&T assembler does not provide support for multiple section 11023 programs. Unix style systems expect all programs to be single 11024 sections. 11025 11026 11027File: as.info, Node: i386-Chars, Prev: i386-Variations, Up: i386-Syntax 11028 110299.15.3.2 Special Characters 11030........................... 11031 11032The presence of a '#' appearing anywhere on a line indicates the start 11033of a comment that extends to the end of that line. 11034 11035 If a '#' appears as the first character of a line then the whole line 11036is treated as a comment, but in this case the line can also be a logical 11037line number directive (*note Comments::) or a preprocessor control 11038command (*note Preprocessing::). 11039 11040 If the '--divide' command line option has not been specified then the 11041'/' character appearing anywhere on a line also introduces a line 11042comment. 11043 11044 The ';' character can be used to separate statements on the same 11045line. 11046 11047 11048File: as.info, Node: i386-Mnemonics, Next: i386-Regs, Prev: i386-Syntax, Up: i386-Dependent 11049 110509.15.4 i386-Mnemonics 11051--------------------- 11052 110539.15.4.1 Instruction Naming 11054........................... 11055 11056Instruction mnemonics are suffixed with one character modifiers which 11057specify the size of operands. The letters 'b', 'w', 'l' and 'q' specify 11058byte, word, long and quadruple word operands. If no suffix is specified 11059by an instruction then 'as' tries to fill in the missing suffix based on 11060the destination register operand (the last one by convention). Thus, 11061'mov %ax, %bx' is equivalent to 'movw %ax, %bx'; also, 'mov $1, %bx' is 11062equivalent to 'movw $1, bx'. Note that this is incompatible with the 11063AT&T Unix assembler which assumes that a missing mnemonic suffix implies 11064long operand size. (This incompatibility does not affect compiler 11065output since compilers always explicitly specify the mnemonic suffix.) 11066 11067 Almost all instructions have the same names in AT&T and Intel format. 11068There are a few exceptions. The sign extend and zero extend 11069instructions need two sizes to specify them. They need a size to 11070sign/zero extend _from_ and a size to zero extend _to_. This is 11071accomplished by using two instruction mnemonic suffixes in AT&T syntax. 11072Base names for sign extend and zero extend are 'movs...' and 'movz...' 11073in AT&T syntax ('movsx' and 'movzx' in Intel syntax). The instruction 11074mnemonic suffixes are tacked on to this base name, the _from_ suffix 11075before the _to_ suffix. Thus, 'movsbl %al, %edx' is AT&T syntax for 11076"move sign extend _from_ %al _to_ %edx." Possible suffixes, thus, are 11077'bl' (from byte to long), 'bw' (from byte to word), 'wl' (from word to 11078long), 'bq' (from byte to quadruple word), 'wq' (from word to quadruple 11079word), and 'lq' (from long to quadruple word). 11080 11081 Different encoding options can be specified via optional mnemonic 11082suffix. '.s' suffix swaps 2 register operands in encoding when moving 11083from one register to another. '.d8' or '.d32' suffix prefers 8bit or 1108432bit displacement in encoding. 11085 11086 The Intel-syntax conversion instructions 11087 11088 * 'cbw' -- sign-extend byte in '%al' to word in '%ax', 11089 11090 * 'cwde' -- sign-extend word in '%ax' to long in '%eax', 11091 11092 * 'cwd' -- sign-extend word in '%ax' to long in '%dx:%ax', 11093 11094 * 'cdq' -- sign-extend dword in '%eax' to quad in '%edx:%eax', 11095 11096 * 'cdqe' -- sign-extend dword in '%eax' to quad in '%rax' (x86-64 11097 only), 11098 11099 * 'cqo' -- sign-extend quad in '%rax' to octuple in '%rdx:%rax' 11100 (x86-64 only), 11101 11102are called 'cbtw', 'cwtl', 'cwtd', 'cltd', 'cltq', and 'cqto' in AT&T 11103naming. 'as' accepts either naming for these instructions. 11104 11105 Far call/jump instructions are 'lcall' and 'ljmp' in AT&T syntax, but 11106are 'call far' and 'jump far' in Intel convention. 11107 111089.15.4.2 AT&T Mnemonic versus Intel Mnemonic 11109............................................ 11110 11111'as' supports assembly using Intel mnemonic. '.intel_mnemonic' selects 11112Intel mnemonic with Intel syntax, and '.att_mnemonic' switches back to 11113the usual AT&T mnemonic with AT&T syntax for compatibility with the 11114output of 'gcc'. Several x87 instructions, 'fadd', 'fdiv', 'fdivp', 11115'fdivr', 'fdivrp', 'fmul', 'fsub', 'fsubp', 'fsubr' and 'fsubrp', are 11116implemented in AT&T System V/386 assembler with different mnemonics from 11117those in Intel IA32 specification. 'gcc' generates those instructions 11118with AT&T mnemonic. 11119 11120 11121File: as.info, Node: i386-Regs, Next: i386-Prefixes, Prev: i386-Mnemonics, Up: i386-Dependent 11122 111239.15.5 Register Naming 11124---------------------- 11125 11126Register operands are always prefixed with '%'. The 80386 registers 11127consist of 11128 11129 * the 8 32-bit registers '%eax' (the accumulator), '%ebx', '%ecx', 11130 '%edx', '%edi', '%esi', '%ebp' (the frame pointer), and '%esp' (the 11131 stack pointer). 11132 11133 * the 8 16-bit low-ends of these: '%ax', '%bx', '%cx', '%dx', '%di', 11134 '%si', '%bp', and '%sp'. 11135 11136 * the 8 8-bit registers: '%ah', '%al', '%bh', '%bl', '%ch', '%cl', 11137 '%dh', and '%dl' (These are the high-bytes and low-bytes of '%ax', 11138 '%bx', '%cx', and '%dx') 11139 11140 * the 6 section registers '%cs' (code section), '%ds' (data section), 11141 '%ss' (stack section), '%es', '%fs', and '%gs'. 11142 11143 * the 5 processor control registers '%cr0', '%cr2', '%cr3', '%cr4', 11144 and '%cr8'. 11145 11146 * the 6 debug registers '%db0', '%db1', '%db2', '%db3', '%db6', and 11147 '%db7'. 11148 11149 * the 2 test registers '%tr6' and '%tr7'. 11150 11151 * the 8 floating point register stack '%st' or equivalently '%st(0)', 11152 '%st(1)', '%st(2)', '%st(3)', '%st(4)', '%st(5)', '%st(6)', and 11153 '%st(7)'. These registers are overloaded by 8 MMX registers 11154 '%mm0', '%mm1', '%mm2', '%mm3', '%mm4', '%mm5', '%mm6' and '%mm7'. 11155 11156 * the 8 128-bit SSE registers registers '%xmm0', '%xmm1', '%xmm2', 11157 '%xmm3', '%xmm4', '%xmm5', '%xmm6' and '%xmm7'. 11158 11159 The AMD x86-64 architecture extends the register set by: 11160 11161 * enhancing the 8 32-bit registers to 64-bit: '%rax' (the 11162 accumulator), '%rbx', '%rcx', '%rdx', '%rdi', '%rsi', '%rbp' (the 11163 frame pointer), '%rsp' (the stack pointer) 11164 11165 * the 8 extended registers '%r8'-'%r15'. 11166 11167 * the 8 32-bit low ends of the extended registers: '%r8d'-'%r15d'. 11168 11169 * the 8 16-bit low ends of the extended registers: '%r8w'-'%r15w'. 11170 11171 * the 8 8-bit low ends of the extended registers: '%r8b'-'%r15b'. 11172 11173 * the 4 8-bit registers: '%sil', '%dil', '%bpl', '%spl'. 11174 11175 * the 8 debug registers: '%db8'-'%db15'. 11176 11177 * the 8 128-bit SSE registers: '%xmm8'-'%xmm15'. 11178 11179 With the AVX extensions more registers were made available: 11180 11181 * the 16 256-bit SSE '%ymm0'-'%ymm15' (only the first 8 available in 11182 32-bit mode). The bottom 128 bits are overlaid with the 11183 'xmm0'-'xmm15' registers. 11184 11185 The AVX2 extensions made in 64-bit mode more registers available: 11186 11187 * the 16 128-bit registers '%xmm16'-'%xmm31' and the 16 256-bit 11188 registers '%ymm16'-'%ymm31'. 11189 11190 The AVX512 extensions added the following registers: 11191 11192 * the 32 512-bit registers '%zmm0'-'%zmm31' (only the first 8 11193 available in 32-bit mode). The bottom 128 bits are overlaid with 11194 the '%xmm0'-'%xmm31' registers and the first 256 bits are overlaid 11195 with the '%ymm0'-'%ymm31' registers. 11196 11197 * the 8 mask registers '%k0'-'%k7'. 11198 11199 11200File: as.info, Node: i386-Prefixes, Next: i386-Memory, Prev: i386-Regs, Up: i386-Dependent 11201 112029.15.6 Instruction Prefixes 11203--------------------------- 11204 11205Instruction prefixes are used to modify the following instruction. They 11206are used to repeat string instructions, to provide section overrides, to 11207perform bus lock operations, and to change operand and address sizes. 11208(Most instructions that normally operate on 32-bit operands will use 1120916-bit operands if the instruction has an "operand size" prefix.) 11210Instruction prefixes are best written on the same line as the 11211instruction they act upon. For example, the 'scas' (scan string) 11212instruction is repeated with: 11213 11214 repne scas %es:(%edi),%al 11215 11216 You may also place prefixes on the lines immediately preceding the 11217instruction, but this circumvents checks that 'as' does with prefixes, 11218and will not work with all prefixes. 11219 11220 Here is a list of instruction prefixes: 11221 11222 * Section override prefixes 'cs', 'ds', 'ss', 'es', 'fs', 'gs'. 11223 These are automatically added by specifying using the 11224 SECTION:MEMORY-OPERAND form for memory references. 11225 11226 * Operand/Address size prefixes 'data16' and 'addr16' change 32-bit 11227 operands/addresses into 16-bit operands/addresses, while 'data32' 11228 and 'addr32' change 16-bit ones (in a '.code16' section) into 11229 32-bit operands/addresses. These prefixes _must_ appear on the 11230 same line of code as the instruction they modify. For example, in 11231 a 16-bit '.code16' section, you might write: 11232 11233 addr32 jmpl *(%ebx) 11234 11235 * The bus lock prefix 'lock' inhibits interrupts during execution of 11236 the instruction it precedes. (This is only valid with certain 11237 instructions; see a 80386 manual for details). 11238 11239 * The wait for coprocessor prefix 'wait' waits for the coprocessor to 11240 complete the current instruction. This should never be needed for 11241 the 80386/80387 combination. 11242 11243 * The 'rep', 'repe', and 'repne' prefixes are added to string 11244 instructions to make them repeat '%ecx' times ('%cx' times if the 11245 current address size is 16-bits). 11246 * The 'rex' family of prefixes is used by x86-64 to encode extensions 11247 to i386 instruction set. The 'rex' prefix has four bits -- an 11248 operand size overwrite ('64') used to change operand size from 11249 32-bit to 64-bit and X, Y and Z extensions bits used to extend the 11250 register set. 11251 11252 You may write the 'rex' prefixes directly. The 'rex64xyz' 11253 instruction emits 'rex' prefix with all the bits set. By omitting 11254 the '64', 'x', 'y' or 'z' you may write other prefixes as well. 11255 Normally, there is no need to write the prefixes explicitly, since 11256 gas will automatically generate them based on the instruction 11257 operands. 11258 11259 11260File: as.info, Node: i386-Memory, Next: i386-Jumps, Prev: i386-Prefixes, Up: i386-Dependent 11261 112629.15.7 Memory References 11263------------------------ 11264 11265An Intel syntax indirect memory reference of the form 11266 11267 SECTION:[BASE + INDEX*SCALE + DISP] 11268 11269is translated into the AT&T syntax 11270 11271 SECTION:DISP(BASE, INDEX, SCALE) 11272 11273where BASE and INDEX are the optional 32-bit base and index registers, 11274DISP is the optional displacement, and SCALE, taking the values 1, 2, 4, 11275and 8, multiplies INDEX to calculate the address of the operand. If no 11276SCALE is specified, SCALE is taken to be 1. SECTION specifies the 11277optional section register for the memory operand, and may override the 11278default section register (see a 80386 manual for section register 11279defaults). Note that section overrides in AT&T syntax _must_ be 11280preceded by a '%'. If you specify a section override which coincides 11281with the default section register, 'as' does _not_ output any section 11282register override prefixes to assemble the given instruction. Thus, 11283section overrides can be specified to emphasize which section register 11284is used for a given memory operand. 11285 11286 Here are some examples of Intel and AT&T style memory references: 11287 11288AT&T: '-4(%ebp)', Intel: '[ebp - 4]' 11289 BASE is '%ebp'; DISP is '-4'. SECTION is missing, and the default 11290 section is used ('%ss' for addressing with '%ebp' as the base 11291 register). INDEX, SCALE are both missing. 11292 11293AT&T: 'foo(,%eax,4)', Intel: '[foo + eax*4]' 11294 INDEX is '%eax' (scaled by a SCALE 4); DISP is 'foo'. All other 11295 fields are missing. The section register here defaults to '%ds'. 11296 11297AT&T: 'foo(,1)'; Intel '[foo]' 11298 This uses the value pointed to by 'foo' as a memory operand. Note 11299 that BASE and INDEX are both missing, but there is only _one_ ','. 11300 This is a syntactic exception. 11301 11302AT&T: '%gs:foo'; Intel 'gs:foo' 11303 This selects the contents of the variable 'foo' with section 11304 register SECTION being '%gs'. 11305 11306 Absolute (as opposed to PC relative) call and jump operands must be 11307prefixed with '*'. If no '*' is specified, 'as' always chooses PC 11308relative addressing for jump/call labels. 11309 11310 Any instruction that has a memory operand, but no register operand, 11311_must_ specify its size (byte, word, long, or quadruple) with an 11312instruction mnemonic suffix ('b', 'w', 'l' or 'q', respectively). 11313 11314 The x86-64 architecture adds an RIP (instruction pointer relative) 11315addressing. This addressing mode is specified by using 'rip' as a base 11316register. Only constant offsets are valid. For example: 11317 11318AT&T: '1234(%rip)', Intel: '[rip + 1234]' 11319 Points to the address 1234 bytes past the end of the current 11320 instruction. 11321 11322AT&T: 'symbol(%rip)', Intel: '[rip + symbol]' 11323 Points to the 'symbol' in RIP relative way, this is shorter than 11324 the default absolute addressing. 11325 11326 Other addressing modes remain unchanged in x86-64 architecture, 11327except registers used are 64-bit instead of 32-bit. 11328 11329 11330File: as.info, Node: i386-Jumps, Next: i386-Float, Prev: i386-Memory, Up: i386-Dependent 11331 113329.15.8 Handling of Jump Instructions 11333------------------------------------ 11334 11335Jump instructions are always optimized to use the smallest possible 11336displacements. This is accomplished by using byte (8-bit) displacement 11337jumps whenever the target is sufficiently close. If a byte displacement 11338is insufficient a long displacement is used. We do not support word 11339(16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump 11340instruction with the 'data16' instruction prefix), since the 80386 11341insists upon masking '%eip' to 16 bits after the word displacement is 11342added. (See also *note i386-Arch::) 11343 11344 Note that the 'jcxz', 'jecxz', 'loop', 'loopz', 'loope', 'loopnz' and 11345'loopne' instructions only come in byte displacements, so that if you 11346use these instructions ('gcc' does not use them) you may get an error 11347message (and incorrect code). The AT&T 80386 assembler tries to get 11348around this problem by expanding 'jcxz foo' to 11349 11350 jcxz cx_zero 11351 jmp cx_nonzero 11352 cx_zero: jmp foo 11353 cx_nonzero: 11354 11355 11356File: as.info, Node: i386-Float, Next: i386-SIMD, Prev: i386-Jumps, Up: i386-Dependent 11357 113589.15.9 Floating Point 11359--------------------- 11360 11361All 80387 floating point types except packed BCD are supported. (BCD 11362support may be added without much difficulty). These data types are 1136316-, 32-, and 64- bit integers, and single (32-bit), double (64-bit), 11364and extended (80-bit) precision floating point. Each supported type has 11365an instruction mnemonic suffix and a constructor associated with it. 11366Instruction mnemonic suffixes specify the operand's data type. 11367Constructors build these data types into memory. 11368 11369 * Floating point constructors are '.float' or '.single', '.double', 11370 and '.tfloat' for 32-, 64-, and 80-bit formats. These correspond 11371 to instruction mnemonic suffixes 's', 'l', and 't'. 't' stands for 11372 80-bit (ten byte) real. The 80387 only supports this format via 11373 the 'fldt' (load 80-bit real to stack top) and 'fstpt' (store 11374 80-bit real and pop stack) instructions. 11375 11376 * Integer constructors are '.word', '.long' or '.int', and '.quad' 11377 for the 16-, 32-, and 64-bit integer formats. The corresponding 11378 instruction mnemonic suffixes are 's' (single), 'l' (long), and 'q' 11379 (quad). As with the 80-bit real format, the 64-bit 'q' format is 11380 only present in the 'fildq' (load quad integer to stack top) and 11381 'fistpq' (store quad integer and pop stack) instructions. 11382 11383 Register to register operations should not use instruction mnemonic 11384suffixes. 'fstl %st, %st(1)' will give a warning, and be assembled as 11385if you wrote 'fst %st, %st(1)', since all register to register 11386operations use 80-bit floating point operands. (Contrast this with 11387'fstl %st, mem', which converts '%st' from 80-bit to 64-bit floating 11388point format, then stores the result in the 4 byte location 'mem') 11389 11390 11391File: as.info, Node: i386-SIMD, Next: i386-LWP, Prev: i386-Float, Up: i386-Dependent 11392 113939.15.10 Intel's MMX and AMD's 3DNow! SIMD Operations 11394---------------------------------------------------- 11395 11396'as' supports Intel's MMX instruction set (SIMD instructions for integer 11397data), available on Intel's Pentium MMX processors and Pentium II 11398processors, AMD's K6 and K6-2 processors, Cyrix' M2 processor, and 11399probably others. It also supports AMD's 3DNow! instruction set (SIMD 11400instructions for 32-bit floating point data) available on AMD's K6-2 11401processor and possibly others in the future. 11402 11403 Currently, 'as' does not support Intel's floating point SIMD, Katmai 11404(KNI). 11405 11406 The eight 64-bit MMX operands, also used by 3DNow!, are called 11407'%mm0', '%mm1', ... '%mm7'. They contain eight 8-bit integers, four 1140816-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit 11409floating point values. The MMX registers cannot be used at the same 11410time as the floating point stack. 11411 11412 See Intel and AMD documentation, keeping in mind that the operand 11413order in instructions is reversed from the Intel syntax. 11414 11415 11416File: as.info, Node: i386-LWP, Next: i386-BMI, Prev: i386-SIMD, Up: i386-Dependent 11417 114189.15.11 AMD's Lightweight Profiling Instructions 11419------------------------------------------------ 11420 11421'as' supports AMD's Lightweight Profiling (LWP) instruction set, 11422available on AMD's Family 15h (Orochi) processors. 11423 11424 LWP enables applications to collect and manage performance data, and 11425react to performance events. The collection of performance data 11426requires no context switches. LWP runs in the context of a thread and 11427so several counters can be used independently across multiple threads. 11428LWP can be used in both 64-bit and legacy 32-bit modes. 11429 11430 For detailed information on the LWP instruction set, see the 'AMD 11431Lightweight Profiling Specification' available at Lightweight Profiling 11432Specification (http://developer.amd.com/cpu/LWP). 11433 11434 11435File: as.info, Node: i386-BMI, Next: i386-TBM, Prev: i386-LWP, Up: i386-Dependent 11436 114379.15.12 Bit Manipulation Instructions 11438------------------------------------- 11439 11440'as' supports the Bit Manipulation (BMI) instruction set. 11441 11442 BMI instructions provide several instructions implementing individual 11443bit manipulation operations such as isolation, masking, setting, or 11444resetting. 11445 11446 11447File: as.info, Node: i386-TBM, Next: i386-16bit, Prev: i386-BMI, Up: i386-Dependent 11448 114499.15.13 AMD's Trailing Bit Manipulation Instructions 11450---------------------------------------------------- 11451 11452'as' supports AMD's Trailing Bit Manipulation (TBM) instruction set, 11453available on AMD's BDVER2 processors (Trinity and Viperfish). 11454 11455 TBM instructions provide instructions implementing individual bit 11456manipulation operations such as isolating, masking, setting, resetting, 11457complementing, and operations on trailing zeros and ones. 11458 11459 11460File: as.info, Node: i386-16bit, Next: i386-Arch, Prev: i386-TBM, Up: i386-Dependent 11461 114629.15.14 Writing 16-bit Code 11463--------------------------- 11464 11465While 'as' normally writes only "pure" 32-bit i386 code or 64-bit x86-64 11466code depending on the default configuration, it also supports writing 11467code to run in real mode or in 16-bit protected mode code segments. To 11468do this, put a '.code16' or '.code16gcc' directive before the assembly 11469language instructions to be run in 16-bit mode. You can switch 'as' to 11470writing 32-bit code with the '.code32' directive or 64-bit code with the 11471'.code64' directive. 11472 11473 '.code16gcc' provides experimental support for generating 16-bit code 11474from gcc, and differs from '.code16' in that 'call', 'ret', 'enter', 11475'leave', 'push', 'pop', 'pusha', 'popa', 'pushf', and 'popf' 11476instructions default to 32-bit size. This is so that the stack pointer 11477is manipulated in the same way over function calls, allowing access to 11478function parameters at the same stack offsets as in 32-bit mode. 11479'.code16gcc' also automatically adds address size prefixes where 11480necessary to use the 32-bit addressing modes that gcc generates. 11481 11482 The code which 'as' generates in 16-bit mode will not necessarily run 11483on a 16-bit pre-80386 processor. To write code that runs on such a 11484processor, you must refrain from using _any_ 32-bit constructs which 11485require 'as' to output address or operand size prefixes. 11486 11487 Note that writing 16-bit code instructions by explicitly specifying a 11488prefix or an instruction mnemonic suffix within a 32-bit code section 11489generates different machine instructions than those generated for a 1149016-bit code segment. In a 32-bit code section, the following code 11491generates the machine opcode bytes '66 6a 04', which pushes the value 11492'4' onto the stack, decrementing '%esp' by 2. 11493 11494 pushw $4 11495 11496 The same code in a 16-bit code section would generate the machine 11497opcode bytes '6a 04' (i.e., without the operand size prefix), which is 11498correct since the processor default operand size is assumed to be 16 11499bits in a 16-bit code section. 11500 11501 11502File: as.info, Node: i386-Arch, Next: i386-Bugs, Prev: i386-16bit, Up: i386-Dependent 11503 115049.15.15 Specifying CPU Architecture 11505----------------------------------- 11506 11507'as' may be told to assemble for a particular CPU (sub-)architecture 11508with the '.arch CPU_TYPE' directive. This directive enables a warning 11509when gas detects an instruction that is not supported on the CPU 11510specified. The choices for CPU_TYPE are: 11511 11512'i8086' 'i186' 'i286' 'i386' 11513'i486' 'i586' 'i686' 'pentium' 11514'pentiumpro' 'pentiumii' 'pentiumiii' 'pentium4' 11515'prescott' 'nocona' 'core' 'core2' 11516'corei7' 'l1om' 'k1om' 11517 'iamcu' 11518'k6' 'k6_2' 'athlon' 'k8' 11519'amdfam10' 'bdver1' 'bdver2' 'bdver3' 11520'bdver4' 'znver1' 'btver1' 'btver2' 11521'generic32' 'generic64' 11522'.mmx' '.sse' '.sse2' '.sse3' 11523'.ssse3' '.sse4.1' '.sse4.2' '.sse4' 11524'.avx' '.vmx' '.smx' '.ept' 11525'.clflush' '.movbe' '.xsave' '.xsaveopt' 11526'.aes' '.pclmul' '.fma' '.fsgsbase' 11527'.rdrnd' '.f16c' '.avx2' '.bmi2' 11528'.lzcnt' '.invpcid' '.vmfunc' '.hle' 11529'.rtm' '.adx' '.rdseed' '.prfchw' 11530'.smap' '.mpx' '.sha' '.prefetchwt1' 11531'.clflushopt' '.xsavec' '.xsaves' '.se1' 11532'.avx512f' '.avx512cd' '.avx512er' '.avx512pf' 11533'.avx512vl' '.avx512bw' '.avx512dq' '.avx512ifma' 11534'.avx512vbmi' '.avx512_4fmaps''.avx512_4vnniw' 11535'.avx512_vpopcntdq''.clwb' '.rdpid' '.ptwrite' 11536'.3dnow' '.3dnowa' '.sse4a' '.sse5' 11537'.syscall' '.rdtscp' '.svme' '.abm' 11538'.lwp' '.fma4' '.xop' '.cx16' 11539'.padlock' '.clzero' '.mwaitx' 11540 11541 Apart from the warning, there are only two other effects on 'as' 11542operation; Firstly, if you specify a CPU other than 'i486', then shift 11543by one instructions such as 'sarl $1, %eax' will automatically use a two 11544byte opcode sequence. The larger three byte opcode sequence is used on 11545the 486 (and when no architecture is specified) because it executes 11546faster on the 486. Note that you can explicitly request the two byte 11547opcode by writing 'sarl %eax'. Secondly, if you specify 'i8086', 11548'i186', or 'i286', _and_ '.code16' or '.code16gcc' then byte offset 11549conditional jumps will be promoted when necessary to a two instruction 11550sequence consisting of a conditional jump of the opposite sense around 11551an unconditional jump to the target. 11552 11553 Following the CPU architecture (but not a sub-architecture, which are 11554those starting with a dot), you may specify 'jumps' or 'nojumps' to 11555control automatic promotion of conditional jumps. 'jumps' is the 11556default, and enables jump promotion; All external jumps will be of the 11557long variety, and file-local jumps will be promoted as necessary. 11558(*note i386-Jumps::) 'nojumps' leaves external conditional jumps as byte 11559offset jumps, and warns about file-local conditional jumps that 'as' 11560promotes. Unconditional jumps are treated as for 'jumps'. 11561 11562 For example 11563 11564 .arch i8086,nojumps 11565 11566 11567File: as.info, Node: i386-Bugs, Next: i386-Notes, Prev: i386-Arch, Up: i386-Dependent 11568 115699.15.16 AT&T Syntax bugs 11570------------------------ 11571 11572The UnixWare assembler, and probably other AT&T derived ix86 Unix 11573assemblers, generate floating point instructions with reversed source 11574and destination registers in certain cases. Unfortunately, gcc and 11575possibly many other programs use this reversed syntax, so we're stuck 11576with it. 11577 11578 For example 11579 11580 fsub %st,%st(3) 11581results in '%st(3)' being updated to '%st - %st(3)' rather than the 11582expected '%st(3) - %st'. This happens with all the non-commutative 11583arithmetic floating point operations with two register operands where 11584the source register is '%st' and the destination register is '%st(i)'. 11585 11586 11587File: as.info, Node: i386-Notes, Prev: i386-Bugs, Up: i386-Dependent 11588 115899.15.17 Notes 11590------------- 11591 11592There is some trickery concerning the 'mul' and 'imul' instructions that 11593deserves mention. The 16-, 32-, 64- and 128-bit expanding multiplies 11594(base opcode '0xf6'; extension 4 for 'mul' and 5 for 'imul') can be 11595output only in the one operand form. Thus, 'imul %ebx, %eax' does _not_ 11596select the expanding multiply; the expanding multiply would clobber the 11597'%edx' register, and this would confuse 'gcc' output. Use 'imul %ebx' 11598to get the 64-bit product in '%edx:%eax'. 11599 11600 We have added a two operand form of 'imul' when the first operand is 11601an immediate mode expression and the second operand is a register. This 11602is just a shorthand, so that, multiplying '%eax' by 69, for example, can 11603be done with 'imul $69, %eax' rather than 'imul $69, %eax, %eax'. 11604 11605 11606File: as.info, Node: i860-Dependent, Next: i960-Dependent, Prev: i386-Dependent, Up: Machine Dependencies 11607 116089.16 Intel i860 Dependent Features 11609================================== 11610 11611* Menu: 11612 11613* Notes-i860:: i860 Notes 11614* Options-i860:: i860 Command-line Options 11615* Directives-i860:: i860 Machine Directives 11616* Opcodes for i860:: i860 Opcodes 11617* Syntax of i860:: i860 Syntax 11618 11619 11620File: as.info, Node: Notes-i860, Next: Options-i860, Up: i860-Dependent 11621 116229.16.1 i860 Notes 11623----------------- 11624 11625This is a fairly complete i860 assembler which is compatible with the 11626UNIX System V/860 Release 4 assembler. However, it does not currently 11627support SVR4 PIC (i.e., '@GOT, @GOTOFF, @PLT'). 11628 11629 Like the SVR4/860 assembler, the output object format is ELF32. 11630Currently, this is the only supported object format. If there is 11631sufficient interest, other formats such as COFF may be implemented. 11632 11633 Both the Intel and AT&T/SVR4 syntaxes are supported, with the latter 11634being the default. One difference is that AT&T syntax requires the '%' 11635prefix on register names while Intel syntax does not. Another 11636difference is in the specification of relocatable expressions. The 11637Intel syntax is 'ha%expression' whereas the SVR4 syntax is 11638'[expression]@ha' (and similarly for the "l" and "h" selectors). 11639 11640 11641File: as.info, Node: Options-i860, Next: Directives-i860, Prev: Notes-i860, Up: i860-Dependent 11642 116439.16.2 i860 Command-line Options 11644-------------------------------- 11645 116469.16.2.1 SVR4 compatibility options 11647................................... 11648 11649'-V' 11650 Print assembler version. 11651'-Qy' 11652 Ignored. 11653'-Qn' 11654 Ignored. 11655 116569.16.2.2 Other options 11657...................... 11658 11659'-EL' 11660 Select little endian output (this is the default). 11661'-EB' 11662 Select big endian output. Note that the i860 always reads 11663 instructions as little endian data, so this option only effects 11664 data and not instructions. 11665'-mwarn-expand' 11666 Emit a warning message if any pseudo-instruction expansions 11667 occurred. For example, a 'or' instruction with an immediate larger 11668 than 16-bits will be expanded into two instructions. This is a 11669 very undesirable feature to rely on, so this flag can help detect 11670 any code where it happens. One use of it, for instance, has been 11671 to find and eliminate any place where 'gcc' may emit these 11672 pseudo-instructions. 11673'-mxp' 11674 Enable support for the i860XP instructions and control registers. 11675 By default, this option is disabled so that only the base 11676 instruction set (i.e., i860XR) is supported. 11677'-mintel-syntax' 11678 The i860 assembler defaults to AT&T/SVR4 syntax. This option 11679 enables the Intel syntax. 11680 11681 11682File: as.info, Node: Directives-i860, Next: Opcodes for i860, Prev: Options-i860, Up: i860-Dependent 11683 116849.16.3 i860 Machine Directives 11685------------------------------ 11686 11687'.dual' 11688 Enter dual instruction mode. While this directive is supported, 11689 the preferred way to use dual instruction mode is to explicitly 11690 code the dual bit with the 'd.' prefix. 11691 11692'.enddual' 11693 Exit dual instruction mode. While this directive is supported, the 11694 preferred way to use dual instruction mode is to explicitly code 11695 the dual bit with the 'd.' prefix. 11696 11697'.atmp' 11698 Change the temporary register used when expanding pseudo 11699 operations. The default register is 'r31'. 11700 11701 The '.dual', '.enddual', and '.atmp' directives are available only in 11702the Intel syntax mode. 11703 11704 Both syntaxes allow for the standard '.align' directive. However, 11705the Intel syntax additionally allows keywords for the alignment 11706parameter: "'.align type'", where 'type' is one of '.short', '.long', 11707'.quad', '.single', '.double' representing alignments of 2, 4, 16, 4, 11708and 8, respectively. 11709 11710 11711File: as.info, Node: Opcodes for i860, Next: Syntax of i860, Prev: Directives-i860, Up: i860-Dependent 11712 117139.16.4 i860 Opcodes 11714------------------- 11715 11716All of the Intel i860XR and i860XP machine instructions are supported. 11717Please see either _i860 Microprocessor Programmer's Reference Manual_ or 11718_i860 Microprocessor Architecture_ for more information. 11719 117209.16.4.1 Other instruction support (pseudo-instructions) 11721........................................................ 11722 11723For compatibility with some other i860 assemblers, a number of 11724pseudo-instructions are supported. While these are supported, they are 11725a very undesirable feature that should be avoided - in particular, when 11726they result in an expansion to multiple actual i860 instructions. Below 11727are the pseudo-instructions that result in expansions. 11728 * Load large immediate into general register: 11729 11730 The pseudo-instruction 'mov imm,%rn' (where the immediate does not 11731 fit within a signed 16-bit field) will be expanded into: 11732 orh large_imm@h,%r0,%rn 11733 or large_imm@l,%rn,%rn 11734 * Load/store with relocatable address expression: 11735 11736 For example, the pseudo-instruction 'ld.b addr_exp(%rx),%rn' will 11737 be expanded into: 11738 orh addr_exp@ha,%rx,%r31 11739 ld.l addr_exp@l(%r31),%rn 11740 11741 The analogous expansions apply to 'ld.x, st.x, fld.x, pfld.x, 11742 fst.x', and 'pst.x' as well. 11743 * Signed large immediate with add/subtract: 11744 11745 If any of the arithmetic operations 'adds, addu, subs, subu' are 11746 used with an immediate larger than 16-bits (signed), then they will 11747 be expanded. For instance, the pseudo-instruction 'adds 11748 large_imm,%rx,%rn' expands to: 11749 orh large_imm@h,%r0,%r31 11750 or large_imm@l,%r31,%r31 11751 adds %r31,%rx,%rn 11752 * Unsigned large immediate with logical operations: 11753 11754 Logical operations ('or, andnot, or, xor') also result in 11755 expansions. The pseudo-instruction 'or large_imm,%rx,%rn' results 11756 in: 11757 orh large_imm@h,%rx,%r31 11758 or large_imm@l,%r31,%rn 11759 11760 Similarly for the others, except for 'and' which expands to: 11761 andnot (-1 - large_imm)@h,%rx,%r31 11762 andnot (-1 - large_imm)@l,%r31,%rn 11763 11764 11765File: as.info, Node: Syntax of i860, Prev: Opcodes for i860, Up: i860-Dependent 11766 117679.16.5 i860 Syntax 11768------------------ 11769 11770* Menu: 11771 11772* i860-Chars:: Special Characters 11773 11774 11775File: as.info, Node: i860-Chars, Up: Syntax of i860 11776 117779.16.5.1 Special Characters 11778........................... 11779 11780The presence of a '#' appearing anywhere on a line indicates the start 11781of a comment that extends to the end of that line. 11782 11783 If a '#' appears as the first character of a line then the whole line 11784is treated as a comment, but in this case the line can also be a logical 11785line number directive (*note Comments::) or a preprocessor control 11786command (*note Preprocessing::). 11787 11788 The ';' character can be used to separate statements on the same 11789line. 11790 11791 11792File: as.info, Node: i960-Dependent, Next: IA-64-Dependent, Prev: i860-Dependent, Up: Machine Dependencies 11793 117949.17 Intel 80960 Dependent Features 11795=================================== 11796 11797* Menu: 11798 11799* Options-i960:: i960 Command-line Options 11800* Floating Point-i960:: Floating Point 11801* Directives-i960:: i960 Machine Directives 11802* Opcodes for i960:: i960 Opcodes 11803* Syntax of i960:: i960 Syntax 11804 11805 11806File: as.info, Node: Options-i960, Next: Floating Point-i960, Up: i960-Dependent 11807 118089.17.1 i960 Command-line Options 11809-------------------------------- 11810 11811'-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC' 11812 Select the 80960 architecture. Instructions or features not 11813 supported by the selected architecture cause fatal errors. 11814 11815 '-ACA' is equivalent to '-ACA_A'; '-AKC' is equivalent to '-AMC'. 11816 Synonyms are provided for compatibility with other tools. 11817 11818 If you do not specify any of these options, 'as' generates code for 11819 any instruction or feature that is supported by _some_ version of 11820 the 960 (even if this means mixing architectures!). In principle, 11821 'as' attempts to deduce the minimal sufficient processor type if 11822 none is specified; depending on the object code format, the 11823 processor type may be recorded in the object file. If it is 11824 critical that the 'as' output match a specific architecture, 11825 specify that architecture explicitly. 11826 11827'-b' 11828 Add code to collect information about conditional branches taken, 11829 for later optimization using branch prediction bits. (The 11830 conditional branch instructions have branch prediction bits in the 11831 CA, CB, and CC architectures.) If BR represents a conditional 11832 branch instruction, the following represents the code generated by 11833 the assembler when '-b' is specified: 11834 11835 call INCREMENT ROUTINE 11836 .word 0 # pre-counter 11837 Label: BR 11838 call INCREMENT ROUTINE 11839 .word 0 # post-counter 11840 11841 The counter following a branch records the number of times that 11842 branch was _not_ taken; the difference between the two counters is 11843 the number of times the branch _was_ taken. 11844 11845 A table of every such 'Label' is also generated, so that the 11846 external postprocessor 'gbr960' (supplied by Intel) can locate all 11847 the counters. This table is always labeled '__BRANCH_TABLE__'; 11848 this is a local symbol to permit collecting statistics for many 11849 separate object files. The table is word aligned, and begins with 11850 a two-word header. The first word, initialized to 0, is used in 11851 maintaining linked lists of branch tables. The second word is a 11852 count of the number of entries in the table, which follow 11853 immediately: each is a word, pointing to one of the labels 11854 illustrated above. 11855 11856 +------------+------------+------------+ ... +------------+ 11857 | | | | | | 11858 | *NEXT | COUNT: N | *BRLAB 1 | | *BRLAB N | 11859 | | | | | | 11860 +------------+------------+------------+ ... +------------+ 11861 11862 __BRANCH_TABLE__ layout 11863 11864 The first word of the header is used to locate multiple branch 11865 tables, since each object file may contain one. Normally the links 11866 are maintained with a call to an initialization routine, placed at 11867 the beginning of each function in the file. The GNU C compiler 11868 generates these calls automatically when you give it a '-b' option. 11869 For further details, see the documentation of 'gbr960'. 11870 11871'-no-relax' 11872 Normally, Compare-and-Branch instructions with targets that require 11873 displacements greater than 13 bits (or that have external targets) 11874 are replaced with the corresponding compare (or 'chkbit') and 11875 branch instructions. You can use the '-no-relax' option to specify 11876 that 'as' should generate errors instead, if the target 11877 displacement is larger than 13 bits. 11878 11879 This option does not affect the Compare-and-Jump instructions; the 11880 code emitted for them is _always_ adjusted when necessary 11881 (depending on displacement size), regardless of whether you use 11882 '-no-relax'. 11883 11884 11885File: as.info, Node: Floating Point-i960, Next: Directives-i960, Prev: Options-i960, Up: i960-Dependent 11886 118879.17.2 Floating Point 11888--------------------- 11889 11890'as' generates IEEE floating-point numbers for the directives '.float', 11891'.double', '.extended', and '.single'. 11892 11893 11894File: as.info, Node: Directives-i960, Next: Opcodes for i960, Prev: Floating Point-i960, Up: i960-Dependent 11895 118969.17.3 i960 Machine Directives 11897------------------------------ 11898 11899'.bss SYMBOL, LENGTH, ALIGN' 11900 Reserve LENGTH bytes in the bss section for a local SYMBOL, aligned 11901 to the power of two specified by ALIGN. LENGTH and ALIGN must be 11902 positive absolute expressions. This directive differs from 11903 '.lcomm' only in that it permits you to specify an alignment. 11904 *Note '.lcomm': Lcomm. 11905 11906'.extended FLONUMS' 11907 '.extended' expects zero or more flonums, separated by commas; for 11908 each flonum, '.extended' emits an IEEE extended-format (80-bit) 11909 floating-point number. 11910 11911'.leafproc CALL-LAB, BAL-LAB' 11912 You can use the '.leafproc' directive in conjunction with the 11913 optimized 'callj' instruction to enable faster calls of leaf 11914 procedures. If a procedure is known to call no other procedures, 11915 you may define an entry point that skips procedure prolog code (and 11916 that does not depend on system-supplied saved context), and declare 11917 it as the BAL-LAB using '.leafproc'. If the procedure also has an 11918 entry point that goes through the normal prolog, you can specify 11919 that entry point as CALL-LAB. 11920 11921 A '.leafproc' declaration is meant for use in conjunction with the 11922 optimized call instruction 'callj'; the directive records the data 11923 needed later to choose between converting the 'callj' into a 'bal' 11924 or a 'call'. 11925 11926 CALL-LAB is optional; if only one argument is present, or if the 11927 two arguments are identical, the single argument is assumed to be 11928 the 'bal' entry point. 11929 11930'.sysproc NAME, INDEX' 11931 The '.sysproc' directive defines a name for a system procedure. 11932 After you define it using '.sysproc', you can use NAME to refer to 11933 the system procedure identified by INDEX when calling procedures 11934 with the optimized call instruction 'callj'. 11935 11936 Both arguments are required; INDEX must be between 0 and 31 11937 (inclusive). 11938 11939 11940File: as.info, Node: Opcodes for i960, Next: Syntax of i960, Prev: Directives-i960, Up: i960-Dependent 11941 119429.17.4 i960 Opcodes 11943------------------- 11944 11945All Intel 960 machine instructions are supported; *note i960 11946Command-line Options: Options-i960. for a discussion of selecting the 11947instruction subset for a particular 960 architecture. 11948 11949 Some opcodes are processed beyond simply emitting a single 11950corresponding instruction: 'callj', and Compare-and-Branch or 11951Compare-and-Jump instructions with target displacements larger than 13 11952bits. 11953 11954* Menu: 11955 11956* callj-i960:: 'callj' 11957* Compare-and-branch-i960:: Compare-and-Branch 11958 11959 11960File: as.info, Node: callj-i960, Next: Compare-and-branch-i960, Up: Opcodes for i960 11961 119629.17.4.1 'callj' 11963................ 11964 11965You can write 'callj' to have the assembler or the linker determine the 11966most appropriate form of subroutine call: 'call', 'bal', or 'calls'. If 11967the assembly source contains enough information--a '.leafproc' or 11968'.sysproc' directive defining the operand--then 'as' translates the 11969'callj'; if not, it simply emits the 'callj', leaving it for the linker 11970to resolve. 11971 11972 11973File: as.info, Node: Compare-and-branch-i960, Prev: callj-i960, Up: Opcodes for i960 11974 119759.17.4.2 Compare-and-Branch 11976........................... 11977 11978The 960 architectures provide combined Compare-and-Branch instructions 11979that permit you to store the branch target in the lower 13 bits of the 11980instruction word itself. However, if you specify a branch target far 11981enough away that its address won't fit in 13 bits, the assembler can 11982either issue an error, or convert your Compare-and-Branch instruction 11983into separate instructions to do the compare and the branch. 11984 11985 Whether 'as' gives an error or expands the instruction depends on two 11986choices you can make: whether you use the '-no-relax' option, and 11987whether you use a "Compare and Branch" instruction or a "Compare and 11988Jump" instruction. The "Jump" instructions are _always_ expanded if 11989necessary; the "Branch" instructions are expanded when necessary 11990_unless_ you specify '-no-relax'--in which case 'as' gives an error 11991instead. 11992 11993 These are the Compare-and-Branch instructions, their "Jump" variants, 11994and the instruction pairs they may expand into: 11995 11996 Compare and 11997 Branch Jump Expanded to 11998 ------ ------ ------------ 11999 bbc chkbit; bno 12000 bbs chkbit; bo 12001 cmpibe cmpije cmpi; be 12002 cmpibg cmpijg cmpi; bg 12003 cmpibge cmpijge cmpi; bge 12004 cmpibl cmpijl cmpi; bl 12005 cmpible cmpijle cmpi; ble 12006 cmpibno cmpijno cmpi; bno 12007 cmpibne cmpijne cmpi; bne 12008 cmpibo cmpijo cmpi; bo 12009 cmpobe cmpoje cmpo; be 12010 cmpobg cmpojg cmpo; bg 12011 cmpobge cmpojge cmpo; bge 12012 cmpobl cmpojl cmpo; bl 12013 cmpoble cmpojle cmpo; ble 12014 cmpobne cmpojne cmpo; bne 12015 12016 12017File: as.info, Node: Syntax of i960, Prev: Opcodes for i960, Up: i960-Dependent 12018 120199.17.5 Syntax for the i960 12020-------------------------- 12021 12022* Menu: 12023 12024* i960-Chars:: Special Characters 12025 12026 12027File: as.info, Node: i960-Chars, Up: Syntax of i960 12028 120299.17.5.1 Special Characters 12030........................... 12031 12032The presence of a '#' on a line indicates the start of a comment that 12033extends to the end of the current line. 12034 12035 If a '#' appears as the first character of a line, the whole line is 12036treated as a comment, but in this case the line can also be a logical 12037line number directive (*note Comments::) or a preprocessor control 12038command (*note Preprocessing::). 12039 12040 The ';' character can be used to separate statements on the same 12041line. 12042 12043 12044File: as.info, Node: IA-64-Dependent, Next: IP2K-Dependent, Prev: i960-Dependent, Up: Machine Dependencies 12045 120469.18 IA-64 Dependent Features 12047============================= 12048 12049* Menu: 12050 12051* IA-64 Options:: Options 12052* IA-64 Syntax:: Syntax 12053* IA-64 Opcodes:: Opcodes 12054 12055 12056File: as.info, Node: IA-64 Options, Next: IA-64 Syntax, Up: IA-64-Dependent 12057 120589.18.1 Options 12059-------------- 12060 12061'-mconstant-gp' 12062 This option instructs the assembler to mark the resulting object 12063 file as using the "constant GP" model. With this model, it is 12064 assumed that the entire program uses a single global pointer (GP) 12065 value. Note that this option does not in any fashion affect the 12066 machine code emitted by the assembler. All it does is turn on the 12067 EF_IA_64_CONS_GP flag in the ELF file header. 12068 12069'-mauto-pic' 12070 This option instructs the assembler to mark the resulting object 12071 file as using the "constant GP without function descriptor" data 12072 model. This model is like the "constant GP" model, except that it 12073 additionally does away with function descriptors. What this means 12074 is that the address of a function refers directly to the function's 12075 code entry-point. Normally, such an address would refer to a 12076 function descriptor, which contains both the code entry-point and 12077 the GP-value needed by the function. Note that this option does 12078 not in any fashion affect the machine code emitted by the 12079 assembler. All it does is turn on the EF_IA_64_NOFUNCDESC_CONS_GP 12080 flag in the ELF file header. 12081 12082'-milp32' 12083'-milp64' 12084'-mlp64' 12085'-mp64' 12086 These options select the data model. The assembler defaults to 12087 '-mlp64' (LP64 data model). 12088 12089'-mle' 12090'-mbe' 12091 These options select the byte order. The '-mle' option selects 12092 little-endian byte order (default) and '-mbe' selects big-endian 12093 byte order. Note that IA-64 machine code always uses little-endian 12094 byte order. 12095 12096'-mtune=itanium1' 12097'-mtune=itanium2' 12098 Tune for a particular IA-64 CPU, ITANIUM1 or ITANIUM2. The default 12099 is ITANIUM2. 12100 12101'-munwind-check=warning' 12102'-munwind-check=error' 12103 These options control what the assembler will do when performing 12104 consistency checks on unwind directives. '-munwind-check=warning' 12105 will make the assembler issue a warning when an unwind directive 12106 check fails. This is the default. '-munwind-check=error' will 12107 make the assembler issue an error when an unwind directive check 12108 fails. 12109 12110'-mhint.b=ok' 12111'-mhint.b=warning' 12112'-mhint.b=error' 12113 These options control what the assembler will do when the 'hint.b' 12114 instruction is used. '-mhint.b=ok' will make the assembler accept 12115 'hint.b'. '-mint.b=warning' will make the assembler issue a 12116 warning when 'hint.b' is used. '-mhint.b=error' will make the 12117 assembler treat 'hint.b' as an error, which is the default. 12118 12119'-x' 12120'-xexplicit' 12121 These options turn on dependency violation checking. 12122 12123'-xauto' 12124 This option instructs the assembler to automatically insert stop 12125 bits where necessary to remove dependency violations. This is the 12126 default mode. 12127 12128'-xnone' 12129 This option turns off dependency violation checking. 12130 12131'-xdebug' 12132 This turns on debug output intended to help tracking down bugs in 12133 the dependency violation checker. 12134 12135'-xdebugn' 12136 This is a shortcut for -xnone -xdebug. 12137 12138'-xdebugx' 12139 This is a shortcut for -xexplicit -xdebug. 12140 12141 12142File: as.info, Node: IA-64 Syntax, Next: IA-64 Opcodes, Prev: IA-64 Options, Up: IA-64-Dependent 12143 121449.18.2 Syntax 12145------------- 12146 12147The assembler syntax closely follows the IA-64 Assembly Language 12148Reference Guide. 12149 12150* Menu: 12151 12152* IA-64-Chars:: Special Characters 12153* IA-64-Regs:: Register Names 12154* IA-64-Bits:: Bit Names 12155* IA-64-Relocs:: Relocations 12156 12157 12158File: as.info, Node: IA-64-Chars, Next: IA-64-Regs, Up: IA-64 Syntax 12159 121609.18.2.1 Special Characters 12161........................... 12162 12163'//' is the line comment token. 12164 12165 ';' can be used instead of a newline to separate statements. 12166 12167 12168File: as.info, Node: IA-64-Regs, Next: IA-64-Bits, Prev: IA-64-Chars, Up: IA-64 Syntax 12169 121709.18.2.2 Register Names 12171....................... 12172 12173The 128 integer registers are referred to as 'rN'. The 128 12174floating-point registers are referred to as 'fN'. The 128 application 12175registers are referred to as 'arN'. The 128 control registers are 12176referred to as 'crN'. The 64 one-bit predicate registers are referred 12177to as 'pN'. The 8 branch registers are referred to as 'bN'. In 12178addition, the assembler defines a number of aliases: 'gp' ('r1'), 'sp' 12179('r12'), 'rp' ('b0'), 'ret0' ('r8'), 'ret1' ('r9'), 'ret2' ('r10'), 12180'ret3' ('r9'), 'fargN' ('f8+N'), and 'fretN' ('f8+N'). 12181 12182 For convenience, the assembler also defines aliases for all named 12183application and control registers. For example, 'ar.bsp' refers to the 12184register backing store pointer ('ar17'). Similarly, 'cr.eoi' refers to 12185the end-of-interrupt register ('cr67'). 12186 12187 12188File: as.info, Node: IA-64-Bits, Next: IA-64-Relocs, Prev: IA-64-Regs, Up: IA-64 Syntax 12189 121909.18.2.3 IA-64 Processor-Status-Register (PSR) Bit Names 12191........................................................ 12192 12193The assembler defines bit masks for each of the bits in the IA-64 12194processor status register. For example, 'psr.ic' corresponds to a value 12195of 0x2000. These masks are primarily intended for use with the 12196'ssm'/'sum' and 'rsm'/'rum' instructions, but they can be used anywhere 12197else where an integer constant is expected. 12198 12199 12200File: as.info, Node: IA-64-Relocs, Prev: IA-64-Bits, Up: IA-64 Syntax 12201 122029.18.2.4 Relocations 12203.................... 12204 12205In addition to the standard IA-64 relocations, the following relocations 12206are implemented by 'as': 12207 12208'@slotcount(V)' 12209 Convert the address offset V into a slot count. This pseudo 12210 function is available only on VMS. The expression V must be known 12211 at assembly time: it can't reference undefined symbols or symbols 12212 in different sections. 12213 12214 12215File: as.info, Node: IA-64 Opcodes, Prev: IA-64 Syntax, Up: IA-64-Dependent 12216 122179.18.3 Opcodes 12218-------------- 12219 12220For detailed information on the IA-64 machine instruction set, see the 12221IA-64 Architecture Handbook 12222(http://developer.intel.com/design/itanium/arch_spec.htm). 12223 12224 12225File: as.info, Node: IP2K-Dependent, Next: LM32-Dependent, Prev: IA-64-Dependent, Up: Machine Dependencies 12226 122279.19 IP2K Dependent Features 12228============================ 12229 12230* Menu: 12231 12232* IP2K-Opts:: IP2K Options 12233* IP2K-Syntax:: IP2K Syntax 12234 12235 12236File: as.info, Node: IP2K-Opts, Next: IP2K-Syntax, Up: IP2K-Dependent 12237 122389.19.1 IP2K Options 12239------------------- 12240 12241The Ubicom IP2K version of 'as' has a few machine dependent options: 12242 12243'-mip2022ext' 12244 'as' can assemble the extended IP2022 instructions, but it will 12245 only do so if this is specifically allowed via this command line 12246 option. 12247 12248'-mip2022' 12249 This option restores the assembler's default behaviour of not 12250 permitting the extended IP2022 instructions to be assembled. 12251 12252 12253File: as.info, Node: IP2K-Syntax, Prev: IP2K-Opts, Up: IP2K-Dependent 12254 122559.19.2 IP2K Syntax 12256------------------ 12257 12258* Menu: 12259 12260* IP2K-Chars:: Special Characters 12261 12262 12263File: as.info, Node: IP2K-Chars, Up: IP2K-Syntax 12264 122659.19.2.1 Special Characters 12266........................... 12267 12268The presence of a ';' on a line indicates the start of a comment that 12269extends to the end of the current line. 12270 12271 If a '#' appears as the first character of a line, the whole line is 12272treated as a comment, but in this case the line can also be a logical 12273line number directive (*note Comments::) or a preprocessor control 12274command (*note Preprocessing::). 12275 12276 The IP2K assembler does not currently support a line separator 12277character. 12278 12279 12280File: as.info, Node: LM32-Dependent, Next: M32C-Dependent, Prev: IP2K-Dependent, Up: Machine Dependencies 12281 122829.20 LM32 Dependent Features 12283============================ 12284 12285* Menu: 12286 12287* LM32 Options:: Options 12288* LM32 Syntax:: Syntax 12289* LM32 Opcodes:: Opcodes 12290 12291 12292File: as.info, Node: LM32 Options, Next: LM32 Syntax, Up: LM32-Dependent 12293 122949.20.1 Options 12295-------------- 12296 12297'-mmultiply-enabled' 12298 Enable multiply instructions. 12299 12300'-mdivide-enabled' 12301 Enable divide instructions. 12302 12303'-mbarrel-shift-enabled' 12304 Enable barrel-shift instructions. 12305 12306'-msign-extend-enabled' 12307 Enable sign extend instructions. 12308 12309'-muser-enabled' 12310 Enable user defined instructions. 12311 12312'-micache-enabled' 12313 Enable instruction cache related CSRs. 12314 12315'-mdcache-enabled' 12316 Enable data cache related CSRs. 12317 12318'-mbreak-enabled' 12319 Enable break instructions. 12320 12321'-mall-enabled' 12322 Enable all instructions and CSRs. 12323 12324 12325File: as.info, Node: LM32 Syntax, Next: LM32 Opcodes, Prev: LM32 Options, Up: LM32-Dependent 12326 123279.20.2 Syntax 12328------------- 12329 12330* Menu: 12331 12332* LM32-Regs:: Register Names 12333* LM32-Modifiers:: Relocatable Expression Modifiers 12334* LM32-Chars:: Special Characters 12335 12336 12337File: as.info, Node: LM32-Regs, Next: LM32-Modifiers, Up: LM32 Syntax 12338 123399.20.2.1 Register Names 12340....................... 12341 12342LM32 has 32 x 32-bit general purpose registers 'r0', 'r1', ... 'r31'. 12343 12344 The following aliases are defined: 'gp' - 'r26', 'fp' - 'r27', 'sp' - 12345'r28', 'ra' - 'r29', 'ea' - 'r30', 'ba' - 'r31'. 12346 12347 LM32 has the following Control and Status Registers (CSRs). 12348 12349'IE' 12350 Interrupt enable. 12351'IM' 12352 Interrupt mask. 12353'IP' 12354 Interrupt pending. 12355'ICC' 12356 Instruction cache control. 12357'DCC' 12358 Data cache control. 12359'CC' 12360 Cycle counter. 12361'CFG' 12362 Configuration. 12363'EBA' 12364 Exception base address. 12365'DC' 12366 Debug control. 12367'DEBA' 12368 Debug exception base address. 12369'JTX' 12370 JTAG transmit. 12371'JRX' 12372 JTAG receive. 12373'BP0' 12374 Breakpoint 0. 12375'BP1' 12376 Breakpoint 1. 12377'BP2' 12378 Breakpoint 2. 12379'BP3' 12380 Breakpoint 3. 12381'WP0' 12382 Watchpoint 0. 12383'WP1' 12384 Watchpoint 1. 12385'WP2' 12386 Watchpoint 2. 12387'WP3' 12388 Watchpoint 3. 12389 12390 12391File: as.info, Node: LM32-Modifiers, Next: LM32-Chars, Prev: LM32-Regs, Up: LM32 Syntax 12392 123939.20.2.2 Relocatable Expression Modifiers 12394......................................... 12395 12396The assembler supports several modifiers when using relocatable 12397addresses in LM32 instruction operands. The general syntax is the 12398following: 12399 12400 modifier(relocatable-expression) 12401 12402'lo' 12403 12404 This modifier allows you to use bits 0 through 15 of an address 12405 expression as 16 bit relocatable expression. 12406 12407'hi' 12408 12409 This modifier allows you to use bits 16 through 23 of an address 12410 expression as 16 bit relocatable expression. 12411 12412 For example 12413 12414 ori r4, r4, lo(sym+10) 12415 orhi r4, r4, hi(sym+10) 12416 12417'gp' 12418 12419 This modified creates a 16-bit relocatable expression that is the 12420 offset of the symbol from the global pointer. 12421 12422 mva r4, gp(sym) 12423 12424'got' 12425 12426 This modifier places a symbol in the GOT and creates a 16-bit 12427 relocatable expression that is the offset into the GOT of this 12428 symbol. 12429 12430 lw r4, (gp+got(sym)) 12431 12432'gotofflo16' 12433 12434 This modifier allows you to use the bits 0 through 15 of an address 12435 which is an offset from the GOT. 12436 12437'gotoffhi16' 12438 12439 This modifier allows you to use the bits 16 through 31 of an 12440 address which is an offset from the GOT. 12441 12442 orhi r4, r4, gotoffhi16(lsym) 12443 addi r4, r4, gotofflo16(lsym) 12444 12445 12446File: as.info, Node: LM32-Chars, Prev: LM32-Modifiers, Up: LM32 Syntax 12447 124489.20.2.3 Special Characters 12449........................... 12450 12451The presence of a '#' on a line indicates the start of a comment that 12452extends to the end of the current line. Note that if a line starts with 12453a '#' character then it can also be a logical line number directive 12454(*note Comments::) or a preprocessor control command (*note 12455Preprocessing::). 12456 12457 A semicolon (';') can be used to separate multiple statements on the 12458same line. 12459 12460 12461File: as.info, Node: LM32 Opcodes, Prev: LM32 Syntax, Up: LM32-Dependent 12462 124639.20.3 Opcodes 12464-------------- 12465 12466For detailed information on the LM32 machine instruction set, see 12467<http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/>. 12468 12469 'as' implements all the standard LM32 opcodes. 12470 12471 12472File: as.info, Node: M32C-Dependent, Next: M32R-Dependent, Prev: LM32-Dependent, Up: Machine Dependencies 12473 124749.21 M32C Dependent Features 12475============================ 12476 12477'as' can assemble code for several different members of the Renesas M32C 12478family. Normally the default is to assemble code for the M16C 12479microprocessor. The '-m32c' option may be used to change the default to 12480the M32C microprocessor. 12481 12482* Menu: 12483 12484* M32C-Opts:: M32C Options 12485* M32C-Syntax:: M32C Syntax 12486 12487 12488File: as.info, Node: M32C-Opts, Next: M32C-Syntax, Up: M32C-Dependent 12489 124909.21.1 M32C Options 12491------------------- 12492 12493The Renesas M32C version of 'as' has these machine-dependent options: 12494 12495'-m32c' 12496 Assemble M32C instructions. 12497 12498'-m16c' 12499 Assemble M16C instructions (default). 12500 12501'-relax' 12502 Enable support for link-time relaxations. 12503 12504'-h-tick-hex' 12505 Support H'00 style hex constants in addition to 0x00 style. 12506 12507 12508File: as.info, Node: M32C-Syntax, Prev: M32C-Opts, Up: M32C-Dependent 12509 125109.21.2 M32C Syntax 12511------------------ 12512 12513* Menu: 12514 12515* M32C-Modifiers:: Symbolic Operand Modifiers 12516* M32C-Chars:: Special Characters 12517 12518 12519File: as.info, Node: M32C-Modifiers, Next: M32C-Chars, Up: M32C-Syntax 12520 125219.21.2.1 Symbolic Operand Modifiers 12522................................... 12523 12524The assembler supports several modifiers when using symbol addresses in 12525M32C instruction operands. The general syntax is the following: 12526 12527 %modifier(symbol) 12528 12529'%dsp8' 12530'%dsp16' 12531 12532 These modifiers override the assembler's assumptions about how big 12533 a symbol's address is. Normally, when it sees an operand like 12534 'sym[a0]' it assumes 'sym' may require the widest displacement 12535 field (16 bits for '-m16c', 24 bits for '-m32c'). These modifiers 12536 tell it to assume the address will fit in an 8 or 16 bit 12537 (respectively) unsigned displacement. Note that, of course, if it 12538 doesn't actually fit you will get linker errors. Example: 12539 12540 mov.w %dsp8(sym)[a0],r1 12541 mov.b #0,%dsp8(sym)[a0] 12542 12543'%hi8' 12544 12545 This modifier allows you to load bits 16 through 23 of a 24 bit 12546 address into an 8 bit register. This is useful with, for example, 12547 the M16C 'smovf' instruction, which expects a 20 bit address in 12548 'r1h' and 'a0'. Example: 12549 12550 mov.b #%hi8(sym),r1h 12551 mov.w #%lo16(sym),a0 12552 smovf.b 12553 12554'%lo16' 12555 12556 Likewise, this modifier allows you to load bits 0 through 15 of a 12557 24 bit address into a 16 bit register. 12558 12559'%hi16' 12560 12561 This modifier allows you to load bits 16 through 31 of a 32 bit 12562 address into a 16 bit register. While the M32C family only has 24 12563 bits of address space, it does support addresses in pairs of 16 bit 12564 registers (like 'a1a0' for the 'lde' instruction). This modifier 12565 is for loading the upper half in such cases. Example: 12566 12567 mov.w #%hi16(sym),a1 12568 mov.w #%lo16(sym),a0 12569 ... 12570 lde.w [a1a0],r1 12571 12572 12573File: as.info, Node: M32C-Chars, Prev: M32C-Modifiers, Up: M32C-Syntax 12574 125759.21.2.2 Special Characters 12576........................... 12577 12578The presence of a ';' character on a line indicates the start of a 12579comment that extends to the end of that line. 12580 12581 If a '#' appears as the first character of a line, the whole line is 12582treated as a comment, but in this case the line can also be a logical 12583line number directive (*note Comments::) or a preprocessor control 12584command (*note Preprocessing::). 12585 12586 The '|' character can be used to separate statements on the same 12587line. 12588 12589 12590File: as.info, Node: M32R-Dependent, Next: M68K-Dependent, Prev: M32C-Dependent, Up: Machine Dependencies 12591 125929.22 M32R Dependent Features 12593============================ 12594 12595* Menu: 12596 12597* M32R-Opts:: M32R Options 12598* M32R-Directives:: M32R Directives 12599* M32R-Warnings:: M32R Warnings 12600 12601 12602File: as.info, Node: M32R-Opts, Next: M32R-Directives, Up: M32R-Dependent 12603 126049.22.1 M32R Options 12605------------------- 12606 12607The Renease M32R version of 'as' has a few machine dependent options: 12608 12609'-m32rx' 12610 'as' can assemble code for several different members of the Renesas 12611 M32R family. Normally the default is to assemble code for the M32R 12612 microprocessor. This option may be used to change the default to 12613 the M32RX microprocessor, which adds some more instructions to the 12614 basic M32R instruction set, and some additional parameters to some 12615 of the original instructions. 12616 12617'-m32r2' 12618 This option changes the target processor to the M32R2 12619 microprocessor. 12620 12621'-m32r' 12622 This option can be used to restore the assembler's default 12623 behaviour of assembling for the M32R microprocessor. This can be 12624 useful if the default has been changed by a previous command line 12625 option. 12626 12627'-little' 12628 This option tells the assembler to produce little-endian code and 12629 data. The default is dependent upon how the toolchain was 12630 configured. 12631 12632'-EL' 12633 This is a synonym for _-little_. 12634 12635'-big' 12636 This option tells the assembler to produce big-endian code and 12637 data. 12638 12639'-EB' 12640 This is a synonum for _-big_. 12641 12642'-KPIC' 12643 This option specifies that the output of the assembler should be 12644 marked as position-independent code (PIC). 12645 12646'-parallel' 12647 This option tells the assembler to attempts to combine two 12648 sequential instructions into a single, parallel instruction, where 12649 it is legal to do so. 12650 12651'-no-parallel' 12652 This option disables a previously enabled _-parallel_ option. 12653 12654'-no-bitinst' 12655 This option disables the support for the extended bit-field 12656 instructions provided by the M32R2. If this support needs to be 12657 re-enabled the _-bitinst_ switch can be used to restore it. 12658 12659'-O' 12660 This option tells the assembler to attempt to optimize the 12661 instructions that it produces. This includes filling delay slots 12662 and converting sequential instructions into parallel ones. This 12663 option implies _-parallel_. 12664 12665'-warn-explicit-parallel-conflicts' 12666 Instructs 'as' to produce warning messages when questionable 12667 parallel instructions are encountered. This option is enabled by 12668 default, but 'gcc' disables it when it invokes 'as' directly. 12669 Questionable instructions are those whose behaviour would be 12670 different if they were executed sequentially. For example the code 12671 fragment 'mv r1, r2 || mv r3, r1' produces a different result from 12672 'mv r1, r2 \n mv r3, r1' since the former moves r1 into r3 and then 12673 r2 into r1, whereas the later moves r2 into r1 and r3. 12674 12675'-Wp' 12676 This is a shorter synonym for the 12677 _-warn-explicit-parallel-conflicts_ option. 12678 12679'-no-warn-explicit-parallel-conflicts' 12680 Instructs 'as' not to produce warning messages when questionable 12681 parallel instructions are encountered. 12682 12683'-Wnp' 12684 This is a shorter synonym for the 12685 _-no-warn-explicit-parallel-conflicts_ option. 12686 12687'-ignore-parallel-conflicts' 12688 This option tells the assembler's to stop checking parallel 12689 instructions for constraint violations. This ability is provided 12690 for hardware vendors testing chip designs and should not be used 12691 under normal circumstances. 12692 12693'-no-ignore-parallel-conflicts' 12694 This option restores the assembler's default behaviour of checking 12695 parallel instructions to detect constraint violations. 12696 12697'-Ip' 12698 This is a shorter synonym for the _-ignore-parallel-conflicts_ 12699 option. 12700 12701'-nIp' 12702 This is a shorter synonym for the _-no-ignore-parallel-conflicts_ 12703 option. 12704 12705'-warn-unmatched-high' 12706 This option tells the assembler to produce a warning message if a 12707 '.high' pseudo op is encountered without a matching '.low' pseudo 12708 op. The presence of such an unmatched pseudo op usually indicates 12709 a programming error. 12710 12711'-no-warn-unmatched-high' 12712 Disables a previously enabled _-warn-unmatched-high_ option. 12713 12714'-Wuh' 12715 This is a shorter synonym for the _-warn-unmatched-high_ option. 12716 12717'-Wnuh' 12718 This is a shorter synonym for the _-no-warn-unmatched-high_ option. 12719 12720 12721File: as.info, Node: M32R-Directives, Next: M32R-Warnings, Prev: M32R-Opts, Up: M32R-Dependent 12722 127239.22.2 M32R Directives 12724---------------------- 12725 12726The Renease M32R version of 'as' has a few architecture specific 12727directives: 12728 12729'low EXPRESSION' 12730 The 'low' directive computes the value of its expression and places 12731 the lower 16-bits of the result into the immediate-field of the 12732 instruction. For example: 12733 12734 or3 r0, r0, #low(0x12345678) ; compute r0 = r0 | 0x5678 12735 add3, r0, r0, #low(fred) ; compute r0 = r0 + low 16-bits of address of fred 12736 12737'high EXPRESSION' 12738 The 'high' directive computes the value of its expression and 12739 places the upper 16-bits of the result into the immediate-field of 12740 the instruction. For example: 12741 12742 seth r0, #high(0x12345678) ; compute r0 = 0x12340000 12743 seth, r0, #high(fred) ; compute r0 = upper 16-bits of address of fred 12744 12745'shigh EXPRESSION' 12746 The 'shigh' directive is very similar to the 'high' directive. It 12747 also computes the value of its expression and places the upper 12748 16-bits of the result into the immediate-field of the instruction. 12749 The difference is that 'shigh' also checks to see if the lower 12750 16-bits could be interpreted as a signed number, and if so it 12751 assumes that a borrow will occur from the upper-16 bits. To 12752 compensate for this the 'shigh' directive pre-biases the upper 16 12753 bit value by adding one to it. For example: 12754 12755 For example: 12756 12757 seth r0, #shigh(0x12345678) ; compute r0 = 0x12340000 12758 seth r0, #shigh(0x00008000) ; compute r0 = 0x00010000 12759 12760 In the second example the lower 16-bits are 0x8000. If these are 12761 treated as a signed value and sign extended to 32-bits then the 12762 value becomes 0xffff8000. If this value is then added to 12763 0x00010000 then the result is 0x00008000. 12764 12765 This behaviour is to allow for the different semantics of the 'or3' 12766 and 'add3' instructions. The 'or3' instruction treats its 16-bit 12767 immediate argument as unsigned whereas the 'add3' treats its 16-bit 12768 immediate as a signed value. So for example: 12769 12770 seth r0, #shigh(0x00008000) 12771 add3 r0, r0, #low(0x00008000) 12772 12773 Produces the correct result in r0, whereas: 12774 12775 seth r0, #shigh(0x00008000) 12776 or3 r0, r0, #low(0x00008000) 12777 12778 Stores 0xffff8000 into r0. 12779 12780 Note - the 'shigh' directive does not know where in the assembly 12781 source code the lower 16-bits of the value are going set, so it 12782 cannot check to make sure that an 'or3' instruction is being used 12783 rather than an 'add3' instruction. It is up to the programmer to 12784 make sure that correct directives are used. 12785 12786'.m32r' 12787 The directive performs a similar thing as the _-m32r_ command line 12788 option. It tells the assembler to only accept M32R instructions 12789 from now on. An instructions from later M32R architectures are 12790 refused. 12791 12792'.m32rx' 12793 The directive performs a similar thing as the _-m32rx_ command line 12794 option. It tells the assembler to start accepting the extra 12795 instructions in the M32RX ISA as well as the ordinary M32R ISA. 12796 12797'.m32r2' 12798 The directive performs a similar thing as the _-m32r2_ command line 12799 option. It tells the assembler to start accepting the extra 12800 instructions in the M32R2 ISA as well as the ordinary M32R ISA. 12801 12802'.little' 12803 The directive performs a similar thing as the _-little_ command 12804 line option. It tells the assembler to start producing 12805 little-endian code and data. This option should be used with care 12806 as producing mixed-endian binary files is fraught with danger. 12807 12808'.big' 12809 The directive performs a similar thing as the _-big_ command line 12810 option. It tells the assembler to start producing big-endian code 12811 and data. This option should be used with care as producing 12812 mixed-endian binary files is fraught with danger. 12813 12814 12815File: as.info, Node: M32R-Warnings, Prev: M32R-Directives, Up: M32R-Dependent 12816 128179.22.3 M32R Warnings 12818-------------------- 12819 12820There are several warning and error messages that can be produced by 12821'as' which are specific to the M32R: 12822 12823'output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?' 12824 This message is only produced if warnings for explicit parallel 12825 conflicts have been enabled. It indicates that the assembler has 12826 encountered a parallel instruction in which the destination 12827 register of the left hand instruction is used as an input register 12828 in the right hand instruction. For example in this code fragment 12829 'mv r1, r2 || neg r3, r1' register r1 is the destination of the 12830 move instruction and the input to the neg instruction. 12831 12832'output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?' 12833 This message is only produced if warnings for explicit parallel 12834 conflicts have been enabled. It indicates that the assembler has 12835 encountered a parallel instruction in which the destination 12836 register of the right hand instruction is used as an input register 12837 in the left hand instruction. For example in this code fragment 12838 'mv r1, r2 || neg r2, r3' register r2 is the destination of the neg 12839 instruction and the input to the move instruction. 12840 12841'instruction '...' is for the M32RX only' 12842 This message is produced when the assembler encounters an 12843 instruction which is only supported by the M32Rx processor, and the 12844 '-m32rx' command line flag has not been specified to allow assembly 12845 of such instructions. 12846 12847'unknown instruction '...'' 12848 This message is produced when the assembler encounters an 12849 instruction which it does not recognize. 12850 12851'only the NOP instruction can be issued in parallel on the m32r' 12852 This message is produced when the assembler encounters a parallel 12853 instruction which does not involve a NOP instruction and the 12854 '-m32rx' command line flag has not been specified. Only the M32Rx 12855 processor is able to execute two instructions in parallel. 12856 12857'instruction '...' cannot be executed in parallel.' 12858 This message is produced when the assembler encounters a parallel 12859 instruction which is made up of one or two instructions which 12860 cannot be executed in parallel. 12861 12862'Instructions share the same execution pipeline' 12863 This message is produced when the assembler encounters a parallel 12864 instruction whoes components both use the same execution pipeline. 12865 12866'Instructions write to the same destination register.' 12867 This message is produced when the assembler encounters a parallel 12868 instruction where both components attempt to modify the same 12869 register. For example these code fragments will produce this 12870 message: 'mv r1, r2 || neg r1, r3' 'jl r0 || mv r14, r1' 'st r2, 12871 @-r1 || mv r1, r3' 'mv r1, r2 || ld r0, @r1+' 'cmp r1, r2 || addx 12872 r3, r4' (Both write to the condition bit) 12873 12874 12875File: as.info, Node: M68K-Dependent, Next: M68HC11-Dependent, Prev: M32R-Dependent, Up: Machine Dependencies 12876 128779.23 M680x0 Dependent Features 12878============================== 12879 12880* Menu: 12881 12882* M68K-Opts:: M680x0 Options 12883* M68K-Syntax:: Syntax 12884* M68K-Moto-Syntax:: Motorola Syntax 12885* M68K-Float:: Floating Point 12886* M68K-Directives:: 680x0 Machine Directives 12887* M68K-opcodes:: Opcodes 12888 12889 12890File: as.info, Node: M68K-Opts, Next: M68K-Syntax, Up: M68K-Dependent 12891 128929.23.1 M680x0 Options 12893--------------------- 12894 12895The Motorola 680x0 version of 'as' has a few machine dependent options: 12896 12897'-march=ARCHITECTURE' 12898 This option specifies a target architecture. The following 12899 architectures are recognized: '68000', '68010', '68020', '68030', 12900 '68040', '68060', 'cpu32', 'isaa', 'isaaplus', 'isab', 'isac' and 12901 'cfv4e'. 12902 12903'-mcpu=CPU' 12904 This option specifies a target cpu. When used in conjunction with 12905 the '-march' option, the cpu must be within the specified 12906 architecture. Also, the generic features of the architecture are 12907 used for instruction generation, rather than those of the specific 12908 chip. 12909 12910'-m[no-]68851' 12911'-m[no-]68881' 12912'-m[no-]div' 12913'-m[no-]usp' 12914'-m[no-]float' 12915'-m[no-]mac' 12916'-m[no-]emac' 12917 12918 Enable or disable various architecture specific features. If a 12919 chip or architecture by default supports an option (for instance 12920 '-march=isaaplus' includes the '-mdiv' option), explicitly 12921 disabling the option will override the default. 12922 12923'-l' 12924 You can use the '-l' option to shorten the size of references to 12925 undefined symbols. If you do not use the '-l' option, references 12926 to undefined symbols are wide enough for a full 'long' (32 bits). 12927 (Since 'as' cannot know where these symbols end up, 'as' can only 12928 allocate space for the linker to fill in later. Since 'as' does 12929 not know how far away these symbols are, it allocates as much space 12930 as it can.) If you use this option, the references are only one 12931 word wide (16 bits). This may be useful if you want the object 12932 file to be as small as possible, and you know that the relevant 12933 symbols are always less than 17 bits away. 12934 12935'--register-prefix-optional' 12936 For some configurations, especially those where the compiler 12937 normally does not prepend an underscore to the names of user 12938 variables, the assembler requires a '%' before any use of a 12939 register name. This is intended to let the assembler distinguish 12940 between C variables and functions named 'a0' through 'a7', and so 12941 on. The '%' is always accepted, but is not required for certain 12942 configurations, notably 'sun3'. The '--register-prefix-optional' 12943 option may be used to permit omitting the '%' even for 12944 configurations for which it is normally required. If this is done, 12945 it will generally be impossible to refer to C variables and 12946 functions with the same names as register names. 12947 12948'--bitwise-or' 12949 Normally the character '|' is treated as a comment character, which 12950 means that it can not be used in expressions. The '--bitwise-or' 12951 option turns '|' into a normal character. In this mode, you must 12952 either use C style comments, or start comments with a '#' character 12953 at the beginning of a line. 12954 12955'--base-size-default-16 --base-size-default-32' 12956 If you use an addressing mode with a base register without 12957 specifying the size, 'as' will normally use the full 32 bit value. 12958 For example, the addressing mode '%a0@(%d0)' is equivalent to 12959 '%a0@(%d0:l)'. You may use the '--base-size-default-16' option to 12960 tell 'as' to default to using the 16 bit value. In this case, 12961 '%a0@(%d0)' is equivalent to '%a0@(%d0:w)'. You may use the 12962 '--base-size-default-32' option to restore the default behaviour. 12963 12964'--disp-size-default-16 --disp-size-default-32' 12965 If you use an addressing mode with a displacement, and the value of 12966 the displacement is not known, 'as' will normally assume that the 12967 value is 32 bits. For example, if the symbol 'disp' has not been 12968 defined, 'as' will assemble the addressing mode '%a0@(disp,%d0)' as 12969 though 'disp' is a 32 bit value. You may use the 12970 '--disp-size-default-16' option to tell 'as' to instead assume that 12971 the displacement is 16 bits. In this case, 'as' will assemble 12972 '%a0@(disp,%d0)' as though 'disp' is a 16 bit value. You may use 12973 the '--disp-size-default-32' option to restore the default 12974 behaviour. 12975 12976'--pcrel' 12977 Always keep branches PC-relative. In the M680x0 architecture all 12978 branches are defined as PC-relative. However, on some processors 12979 they are limited to word displacements maximum. When 'as' needs a 12980 long branch that is not available, it normally emits an absolute 12981 jump instead. This option disables this substitution. When this 12982 option is given and no long branches are available, only word 12983 branches will be emitted. An error message will be generated if a 12984 word branch cannot reach its target. This option has no effect on 12985 68020 and other processors that have long branches. *note Branch 12986 Improvement: M68K-Branch. 12987 12988'-m68000' 12989 'as' can assemble code for several different members of the 12990 Motorola 680x0 family. The default depends upon how 'as' was 12991 configured when it was built; normally, the default is to assemble 12992 code for the 68020 microprocessor. The following options may be 12993 used to change the default. These options control which 12994 instructions and addressing modes are permitted. The members of 12995 the 680x0 family are very similar. For detailed information about 12996 the differences, see the Motorola manuals. 12997 12998 '-m68000' 12999 '-m68ec000' 13000 '-m68hc000' 13001 '-m68hc001' 13002 '-m68008' 13003 '-m68302' 13004 '-m68306' 13005 '-m68307' 13006 '-m68322' 13007 '-m68356' 13008 Assemble for the 68000. '-m68008', '-m68302', and so on are 13009 synonyms for '-m68000', since the chips are the same from the 13010 point of view of the assembler. 13011 13012 '-m68010' 13013 Assemble for the 68010. 13014 13015 '-m68020' 13016 '-m68ec020' 13017 Assemble for the 68020. This is normally the default. 13018 13019 '-m68030' 13020 '-m68ec030' 13021 Assemble for the 68030. 13022 13023 '-m68040' 13024 '-m68ec040' 13025 Assemble for the 68040. 13026 13027 '-m68060' 13028 '-m68ec060' 13029 Assemble for the 68060. 13030 13031 '-mcpu32' 13032 '-m68330' 13033 '-m68331' 13034 '-m68332' 13035 '-m68333' 13036 '-m68334' 13037 '-m68336' 13038 '-m68340' 13039 '-m68341' 13040 '-m68349' 13041 '-m68360' 13042 Assemble for the CPU32 family of chips. 13043 13044 '-m5200' 13045 '-m5202' 13046 '-m5204' 13047 '-m5206' 13048 '-m5206e' 13049 '-m521x' 13050 '-m5249' 13051 '-m528x' 13052 '-m5307' 13053 '-m5407' 13054 '-m547x' 13055 '-m548x' 13056 '-mcfv4' 13057 '-mcfv4e' 13058 Assemble for the ColdFire family of chips. 13059 13060 '-m68881' 13061 '-m68882' 13062 Assemble 68881 floating point instructions. This is the 13063 default for the 68020, 68030, and the CPU32. The 68040 and 13064 68060 always support floating point instructions. 13065 13066 '-mno-68881' 13067 Do not assemble 68881 floating point instructions. This is 13068 the default for 68000 and the 68010. The 68040 and 68060 13069 always support floating point instructions, even if this 13070 option is used. 13071 13072 '-m68851' 13073 Assemble 68851 MMU instructions. This is the default for the 13074 68020, 68030, and 68060. The 68040 accepts a somewhat 13075 different set of MMU instructions; '-m68851' and '-m68040' 13076 should not be used together. 13077 13078 '-mno-68851' 13079 Do not assemble 68851 MMU instructions. This is the default 13080 for the 68000, 68010, and the CPU32. The 68040 accepts a 13081 somewhat different set of MMU instructions. 13082 13083 13084File: as.info, Node: M68K-Syntax, Next: M68K-Moto-Syntax, Prev: M68K-Opts, Up: M68K-Dependent 13085 130869.23.2 Syntax 13087------------- 13088 13089This syntax for the Motorola 680x0 was developed at MIT. 13090 13091 The 680x0 version of 'as' uses instructions names and syntax 13092compatible with the Sun assembler. Intervening periods are ignored; for 13093example, 'movl' is equivalent to 'mov.l'. 13094 13095 In the following table APC stands for any of the address registers 13096('%a0' through '%a7'), the program counter ('%pc'), the zero-address 13097relative to the program counter ('%zpc'), a suppressed address register 13098('%za0' through '%za7'), or it may be omitted entirely. The use of SIZE 13099means one of 'w' or 'l', and it may be omitted, along with the leading 13100colon, unless a scale is also specified. The use of SCALE means one of 13101'1', '2', '4', or '8', and it may always be omitted along with the 13102leading colon. 13103 13104 The following addressing modes are understood: 13105"Immediate" 13106 '#NUMBER' 13107 13108"Data Register" 13109 '%d0' through '%d7' 13110 13111"Address Register" 13112 '%a0' through '%a7' 13113 '%a7' is also known as '%sp', i.e., the Stack Pointer. '%a6' is 13114 also known as '%fp', the Frame Pointer. 13115 13116"Address Register Indirect" 13117 '%a0@' through '%a7@' 13118 13119"Address Register Postincrement" 13120 '%a0@+' through '%a7@+' 13121 13122"Address Register Predecrement" 13123 '%a0@-' through '%a7@-' 13124 13125"Indirect Plus Offset" 13126 'APC@(NUMBER)' 13127 13128"Index" 13129 'APC@(NUMBER,REGISTER:SIZE:SCALE)' 13130 13131 The NUMBER may be omitted. 13132 13133"Postindex" 13134 'APC@(NUMBER)@(ONUMBER,REGISTER:SIZE:SCALE)' 13135 13136 The ONUMBER or the REGISTER, but not both, may be omitted. 13137 13138"Preindex" 13139 'APC@(NUMBER,REGISTER:SIZE:SCALE)@(ONUMBER)' 13140 13141 The NUMBER may be omitted. Omitting the REGISTER produces the 13142 Postindex addressing mode. 13143 13144"Absolute" 13145 'SYMBOL', or 'DIGITS', optionally followed by ':b', ':w', or ':l'. 13146 13147 13148File: as.info, Node: M68K-Moto-Syntax, Next: M68K-Float, Prev: M68K-Syntax, Up: M68K-Dependent 13149 131509.23.3 Motorola Syntax 13151---------------------- 13152 13153The standard Motorola syntax for this chip differs from the syntax 13154already discussed (*note Syntax: M68K-Syntax.). 'as' can accept 13155Motorola syntax for operands, even if MIT syntax is used for other 13156operands in the same instruction. The two kinds of syntax are fully 13157compatible. 13158 13159 In the following table APC stands for any of the address registers 13160('%a0' through '%a7'), the program counter ('%pc'), the zero-address 13161relative to the program counter ('%zpc'), or a suppressed address 13162register ('%za0' through '%za7'). The use of SIZE means one of 'w' or 13163'l', and it may always be omitted along with the leading dot. The use 13164of SCALE means one of '1', '2', '4', or '8', and it may always be 13165omitted along with the leading asterisk. 13166 13167 The following additional addressing modes are understood: 13168 13169"Address Register Indirect" 13170 '(%a0)' through '(%a7)' 13171 '%a7' is also known as '%sp', i.e., the Stack Pointer. '%a6' is 13172 also known as '%fp', the Frame Pointer. 13173 13174"Address Register Postincrement" 13175 '(%a0)+' through '(%a7)+' 13176 13177"Address Register Predecrement" 13178 '-(%a0)' through '-(%a7)' 13179 13180"Indirect Plus Offset" 13181 'NUMBER(%A0)' through 'NUMBER(%A7)', or 'NUMBER(%PC)'. 13182 13183 The NUMBER may also appear within the parentheses, as in 13184 '(NUMBER,%A0)'. When used with the PC, the NUMBER may be omitted 13185 (with an address register, omitting the NUMBER produces Address 13186 Register Indirect mode). 13187 13188"Index" 13189 'NUMBER(APC,REGISTER.SIZE*SCALE)' 13190 13191 The NUMBER may be omitted, or it may appear within the parentheses. 13192 The APC may be omitted. The REGISTER and the APC may appear in 13193 either order. If both APC and REGISTER are address registers, and 13194 the SIZE and SCALE are omitted, then the first register is taken as 13195 the base register, and the second as the index register. 13196 13197"Postindex" 13198 '([NUMBER,APC],REGISTER.SIZE*SCALE,ONUMBER)' 13199 13200 The ONUMBER, or the REGISTER, or both, may be omitted. Either the 13201 NUMBER or the APC may be omitted, but not both. 13202 13203"Preindex" 13204 '([NUMBER,APC,REGISTER.SIZE*SCALE],ONUMBER)' 13205 13206 The NUMBER, or the APC, or the REGISTER, or any two of them, may be 13207 omitted. The ONUMBER may be omitted. The REGISTER and the APC may 13208 appear in either order. If both APC and REGISTER are address 13209 registers, and the SIZE and SCALE are omitted, then the first 13210 register is taken as the base register, and the second as the index 13211 register. 13212 13213 13214File: as.info, Node: M68K-Float, Next: M68K-Directives, Prev: M68K-Moto-Syntax, Up: M68K-Dependent 13215 132169.23.4 Floating Point 13217--------------------- 13218 13219Packed decimal (P) format floating literals are not supported. Feel 13220free to add the code! 13221 13222 The floating point formats generated by directives are these. 13223 13224'.float' 13225 'Single' precision floating point constants. 13226 13227'.double' 13228 'Double' precision floating point constants. 13229 13230'.extend' 13231'.ldouble' 13232 'Extended' precision ('long double') floating point constants. 13233 13234 13235File: as.info, Node: M68K-Directives, Next: M68K-opcodes, Prev: M68K-Float, Up: M68K-Dependent 13236 132379.23.5 680x0 Machine Directives 13238------------------------------- 13239 13240In order to be compatible with the Sun assembler the 680x0 assembler 13241understands the following directives. 13242 13243'.data1' 13244 This directive is identical to a '.data 1' directive. 13245 13246'.data2' 13247 This directive is identical to a '.data 2' directive. 13248 13249'.even' 13250 This directive is a special case of the '.align' directive; it 13251 aligns the output to an even byte boundary. 13252 13253'.skip' 13254 This directive is identical to a '.space' directive. 13255 13256'.arch NAME' 13257 Select the target architecture and extension features. Valid 13258 values for NAME are the same as for the '-march' command line 13259 option. This directive cannot be specified after any instructions 13260 have been assembled. If it is given multiple times, or in 13261 conjunction with the '-march' option, all uses must be for the same 13262 architecture and extension set. 13263 13264'.cpu NAME' 13265 Select the target cpu. Valid valuse for NAME are the same as for 13266 the '-mcpu' command line option. This directive cannot be 13267 specified after any instructions have been assembled. If it is 13268 given multiple times, or in conjunction with the '-mopt' option, 13269 all uses must be for the same cpu. 13270 13271 13272File: as.info, Node: M68K-opcodes, Prev: M68K-Directives, Up: M68K-Dependent 13273 132749.23.6 Opcodes 13275-------------- 13276 13277* Menu: 13278 13279* M68K-Branch:: Branch Improvement 13280* M68K-Chars:: Special Characters 13281 13282 13283File: as.info, Node: M68K-Branch, Next: M68K-Chars, Up: M68K-opcodes 13284 132859.23.6.1 Branch Improvement 13286........................... 13287 13288Certain pseudo opcodes are permitted for branch instructions. They 13289expand to the shortest branch instruction that reach the target. 13290Generally these mnemonics are made by substituting 'j' for 'b' at the 13291start of a Motorola mnemonic. 13292 13293 The following table summarizes the pseudo-operations. A '*' flags 13294cases that are more fully described after the table: 13295 13296 Displacement 13297 +------------------------------------------------------------ 13298 | 68020 68000/10, not PC-relative OK 13299 Pseudo-Op |BYTE WORD LONG ABSOLUTE LONG JUMP ** 13300 +------------------------------------------------------------ 13301 jbsr |bsrs bsrw bsrl jsr 13302 jra |bras braw bral jmp 13303 * jXX |bXXs bXXw bXXl bNXs;jmp 13304 * dbXX | N/A dbXXw dbXX;bras;bral dbXX;bras;jmp 13305 fjXX | N/A fbXXw fbXXl N/A 13306 13307 XX: condition 13308 NX: negative of condition XX 13309 13310 '*'--see full description below 13311 '**'--this expansion mode is disallowed by '--pcrel' 13312 13313'jbsr' 13314'jra' 13315 These are the simplest jump pseudo-operations; they always map to 13316 one particular machine instruction, depending on the displacement 13317 to the branch target. This instruction will be a byte or word 13318 branch is that is sufficient. Otherwise, a long branch will be 13319 emitted if available. If no long branches are available and the 13320 '--pcrel' option is not given, an absolute long jump will be 13321 emitted instead. If no long branches are available, the '--pcrel' 13322 option is given, and a word branch cannot reach the target, an 13323 error message is generated. 13324 13325 In addition to standard branch operands, 'as' allows these 13326 pseudo-operations to have all operands that are allowed for jsr and 13327 jmp, substituting these instructions if the operand given is not 13328 valid for a branch instruction. 13329 13330'jXX' 13331 Here, 'jXX' stands for an entire family of pseudo-operations, where 13332 XX is a conditional branch or condition-code test. The full list 13333 of pseudo-ops in this family is: 13334 jhi jls jcc jcs jne jeq jvc 13335 jvs jpl jmi jge jlt jgt jle 13336 13337 Usually, each of these pseudo-operations expands to a single branch 13338 instruction. However, if a word branch is not sufficient, no long 13339 branches are available, and the '--pcrel' option is not given, 'as' 13340 issues a longer code fragment in terms of NX, the opposite 13341 condition to XX. For example, under these conditions: 13342 jXX foo 13343 gives 13344 bNXs oof 13345 jmp foo 13346 oof: 13347 13348'dbXX' 13349 The full family of pseudo-operations covered here is 13350 dbhi dbls dbcc dbcs dbne dbeq dbvc 13351 dbvs dbpl dbmi dbge dblt dbgt dble 13352 dbf dbra dbt 13353 13354 Motorola 'dbXX' instructions allow word displacements only. When a 13355 word displacement is sufficient, each of these pseudo-operations 13356 expands to the corresponding Motorola instruction. When a word 13357 displacement is not sufficient and long branches are available, 13358 when the source reads 'dbXX foo', 'as' emits 13359 dbXX oo1 13360 bras oo2 13361 oo1:bral foo 13362 oo2: 13363 13364 If, however, long branches are not available and the '--pcrel' 13365 option is not given, 'as' emits 13366 dbXX oo1 13367 bras oo2 13368 oo1:jmp foo 13369 oo2: 13370 13371'fjXX' 13372 This family includes 13373 fjne fjeq fjge fjlt fjgt fjle fjf 13374 fjt fjgl fjgle fjnge fjngl fjngle fjngt 13375 fjnle fjnlt fjoge fjogl fjogt fjole fjolt 13376 fjor fjseq fjsf fjsne fjst fjueq fjuge 13377 fjugt fjule fjult fjun 13378 13379 Each of these pseudo-operations always expands to a single Motorola 13380 coprocessor branch instruction, word or long. All Motorola 13381 coprocessor branch instructions allow both word and long 13382 displacements. 13383 13384 13385File: as.info, Node: M68K-Chars, Prev: M68K-Branch, Up: M68K-opcodes 13386 133879.23.6.2 Special Characters 13388........................... 13389 13390Line comments are introduced by the '|' character appearing anywhere on 13391a line, unless the '--bitwise-or' command line option has been 13392specified. 13393 13394 An asterisk ('*') as the first character on a line marks the start of 13395a line comment as well. 13396 13397 A hash character ('#') as the first character on a line also marks 13398the start of a line comment, but in this case it could also be a logical 13399line number directive (*note Comments::) or a preprocessor control 13400command (*note Preprocessing::). If the hash character appears 13401elsewhere on a line it is used to introduce an immediate value. (This 13402is for compatibility with Sun's assembler). 13403 13404 Multiple statements on the same line can appear if they are separated 13405by the ';' character. 13406 13407 13408File: as.info, Node: M68HC11-Dependent, Next: Meta-Dependent, Prev: M68K-Dependent, Up: Machine Dependencies 13409 134109.24 M68HC11 and M68HC12 Dependent Features 13411=========================================== 13412 13413* Menu: 13414 13415* M68HC11-Opts:: M68HC11 and M68HC12 Options 13416* M68HC11-Syntax:: Syntax 13417* M68HC11-Modifiers:: Symbolic Operand Modifiers 13418* M68HC11-Directives:: Assembler Directives 13419* M68HC11-Float:: Floating Point 13420* M68HC11-opcodes:: Opcodes 13421 13422 13423File: as.info, Node: M68HC11-Opts, Next: M68HC11-Syntax, Up: M68HC11-Dependent 13424 134259.24.1 M68HC11 and M68HC12 Options 13426---------------------------------- 13427 13428The Motorola 68HC11 and 68HC12 version of 'as' have a few machine 13429dependent options. 13430 13431'-m68hc11' 13432 This option switches the assembler into the M68HC11 mode. In this 13433 mode, the assembler only accepts 68HC11 operands and mnemonics. It 13434 produces code for the 68HC11. 13435 13436'-m68hc12' 13437 This option switches the assembler into the M68HC12 mode. In this 13438 mode, the assembler also accepts 68HC12 operands and mnemonics. It 13439 produces code for the 68HC12. A few 68HC11 instructions are 13440 replaced by some 68HC12 instructions as recommended by Motorola 13441 specifications. 13442 13443'-m68hcs12' 13444 This option switches the assembler into the M68HCS12 mode. This 13445 mode is similar to '-m68hc12' but specifies to assemble for the 13446 68HCS12 series. The only difference is on the assembling of the 13447 'movb' and 'movw' instruction when a PC-relative operand is used. 13448 13449'-mm9s12x' 13450 This option switches the assembler into the M9S12X mode. This mode 13451 is similar to '-m68hc12' but specifies to assemble for the S12X 13452 series which is a superset of the HCS12. 13453 13454'-mm9s12xg' 13455 This option switches the assembler into the XGATE mode for the RISC 13456 co-processor featured on some S12X-family chips. 13457 13458'--xgate-ramoffset' 13459 This option instructs the linker to offset RAM addresses from S12X 13460 address space into XGATE address space. 13461 13462'-mshort' 13463 This option controls the ABI and indicates to use a 16-bit integer 13464 ABI. It has no effect on the assembled instructions. This is the 13465 default. 13466 13467'-mlong' 13468 This option controls the ABI and indicates to use a 32-bit integer 13469 ABI. 13470 13471'-mshort-double' 13472 This option controls the ABI and indicates to use a 32-bit float 13473 ABI. This is the default. 13474 13475'-mlong-double' 13476 This option controls the ABI and indicates to use a 64-bit float 13477 ABI. 13478 13479'--strict-direct-mode' 13480 You can use the '--strict-direct-mode' option to disable the 13481 automatic translation of direct page mode addressing into extended 13482 mode when the instruction does not support direct mode. For 13483 example, the 'clr' instruction does not support direct page mode 13484 addressing. When it is used with the direct page mode, 'as' will 13485 ignore it and generate an absolute addressing. This option 13486 prevents 'as' from doing this, and the wrong usage of the direct 13487 page mode will raise an error. 13488 13489'--short-branches' 13490 The '--short-branches' option turns off the translation of relative 13491 branches into absolute branches when the branch offset is out of 13492 range. By default 'as' transforms the relative branch ('bsr', 13493 'bgt', 'bge', 'beq', 'bne', 'ble', 'blt', 'bhi', 'bcc', 'bls', 13494 'bcs', 'bmi', 'bvs', 'bvs', 'bra') into an absolute branch when the 13495 offset is out of the -128 .. 127 range. In that case, the 'bsr' 13496 instruction is translated into a 'jsr', the 'bra' instruction is 13497 translated into a 'jmp' and the conditional branches instructions 13498 are inverted and followed by a 'jmp'. This option disables these 13499 translations and 'as' will generate an error if a relative branch 13500 is out of range. This option does not affect the optimization 13501 associated to the 'jbra', 'jbsr' and 'jbXX' pseudo opcodes. 13502 13503'--force-long-branches' 13504 The '--force-long-branches' option forces the translation of 13505 relative branches into absolute branches. This option does not 13506 affect the optimization associated to the 'jbra', 'jbsr' and 'jbXX' 13507 pseudo opcodes. 13508 13509'--print-insn-syntax' 13510 You can use the '--print-insn-syntax' option to obtain the syntax 13511 description of the instruction when an error is detected. 13512 13513'--print-opcodes' 13514 The '--print-opcodes' option prints the list of all the 13515 instructions with their syntax. The first item of each line 13516 represents the instruction name and the rest of the line indicates 13517 the possible operands for that instruction. The list is printed in 13518 alphabetical order. Once the list is printed 'as' exits. 13519 13520'--generate-example' 13521 The '--generate-example' option is similar to '--print-opcodes' but 13522 it generates an example for each instruction instead. 13523 13524 13525File: as.info, Node: M68HC11-Syntax, Next: M68HC11-Modifiers, Prev: M68HC11-Opts, Up: M68HC11-Dependent 13526 135279.24.2 Syntax 13528------------- 13529 13530In the M68HC11 syntax, the instruction name comes first and it may be 13531followed by one or several operands (up to three). Operands are 13532separated by comma (','). In the normal mode, 'as' will complain if too 13533many operands are specified for a given instruction. In the MRI mode 13534(turned on with '-M' option), it will treat them as comments. Example: 13535 13536 inx 13537 lda #23 13538 bset 2,x #4 13539 brclr *bot #8 foo 13540 13541 The presence of a ';' character or a '!' character anywhere on a line 13542indicates the start of a comment that extends to the end of that line. 13543 13544 A '*' or a '#' character at the start of a line also introduces a 13545line comment, but these characters do not work elsewhere on the line. 13546If the first character of the line is a '#' then as well as starting a 13547comment, the line could also be logical line number directive (*note 13548Comments::) or a preprocessor control command (*note Preprocessing::). 13549 13550 The M68HC11 assembler does not currently support a line separator 13551character. 13552 13553 The following addressing modes are understood for 68HC11 and 68HC12: 13554"Immediate" 13555 '#NUMBER' 13556 13557"Address Register" 13558 'NUMBER,X', 'NUMBER,Y' 13559 13560 The NUMBER may be omitted in which case 0 is assumed. 13561 13562"Direct Addressing mode" 13563 '*SYMBOL', or '*DIGITS' 13564 13565"Absolute" 13566 'SYMBOL', or 'DIGITS' 13567 13568 The M68HC12 has other more complex addressing modes. All of them are 13569supported and they are represented below: 13570 13571"Constant Offset Indexed Addressing Mode" 13572 'NUMBER,REG' 13573 13574 The NUMBER may be omitted in which case 0 is assumed. The register 13575 can be either 'X', 'Y', 'SP' or 'PC'. The assembler will use the 13576 smaller post-byte definition according to the constant value (5-bit 13577 constant offset, 9-bit constant offset or 16-bit constant offset). 13578 If the constant is not known by the assembler it will use the 13579 16-bit constant offset post-byte and the value will be resolved at 13580 link time. 13581 13582"Offset Indexed Indirect" 13583 '[NUMBER,REG]' 13584 13585 The register can be either 'X', 'Y', 'SP' or 'PC'. 13586 13587"Auto Pre-Increment/Pre-Decrement/Post-Increment/Post-Decrement" 13588 'NUMBER,-REG' 'NUMBER,+REG' 'NUMBER,REG-' 'NUMBER,REG+' 13589 13590 The number must be in the range '-8'..'+8' and must not be 0. The 13591 register can be either 'X', 'Y', 'SP' or 'PC'. 13592 13593"Accumulator Offset" 13594 'ACC,REG' 13595 13596 The accumulator register can be either 'A', 'B' or 'D'. The 13597 register can be either 'X', 'Y', 'SP' or 'PC'. 13598 13599"Accumulator D offset indexed-indirect" 13600 '[D,REG]' 13601 13602 The register can be either 'X', 'Y', 'SP' or 'PC'. 13603 13604 For example: 13605 13606 ldab 1024,sp 13607 ldd [10,x] 13608 orab 3,+x 13609 stab -2,y- 13610 ldx a,pc 13611 sty [d,sp] 13612 13613 13614File: as.info, Node: M68HC11-Modifiers, Next: M68HC11-Directives, Prev: M68HC11-Syntax, Up: M68HC11-Dependent 13615 136169.24.3 Symbolic Operand Modifiers 13617--------------------------------- 13618 13619The assembler supports several modifiers when using symbol addresses in 1362068HC11 and 68HC12 instruction operands. The general syntax is the 13621following: 13622 13623 %modifier(symbol) 13624 13625'%addr' 13626 This modifier indicates to the assembler and linker to use the 13627 16-bit physical address corresponding to the symbol. This is 13628 intended to be used on memory window systems to map a symbol in the 13629 memory bank window. If the symbol is in a memory expansion part, 13630 the physical address corresponds to the symbol address within the 13631 memory bank window. If the symbol is not in a memory expansion 13632 part, this is the symbol address (using or not using the %addr 13633 modifier has no effect in that case). 13634 13635'%page' 13636 This modifier indicates to use the memory page number corresponding 13637 to the symbol. If the symbol is in a memory expansion part, its 13638 page number is computed by the linker as a number used to map the 13639 page containing the symbol in the memory bank window. If the 13640 symbol is not in a memory expansion part, the page number is 0. 13641 13642'%hi' 13643 This modifier indicates to use the 8-bit high part of the physical 13644 address of the symbol. 13645 13646'%lo' 13647 This modifier indicates to use the 8-bit low part of the physical 13648 address of the symbol. 13649 13650 For example a 68HC12 call to a function 'foo_example' stored in 13651memory expansion part could be written as follows: 13652 13653 call %addr(foo_example),%page(foo_example) 13654 13655 and this is equivalent to 13656 13657 call foo_example 13658 13659 And for 68HC11 it could be written as follows: 13660 13661 ldab #%page(foo_example) 13662 stab _page_switch 13663 jsr %addr(foo_example) 13664 13665 13666File: as.info, Node: M68HC11-Directives, Next: M68HC11-Float, Prev: M68HC11-Modifiers, Up: M68HC11-Dependent 13667 136689.24.4 Assembler Directives 13669--------------------------- 13670 13671The 68HC11 and 68HC12 version of 'as' have the following specific 13672assembler directives: 13673 13674'.relax' 13675 The relax directive is used by the 'GNU Compiler' to emit a 13676 specific relocation to mark a group of instructions for linker 13677 relaxation. The sequence of instructions within the group must be 13678 known to the linker so that relaxation can be performed. 13679 13680'.mode [mshort|mlong|mshort-double|mlong-double]' 13681 This directive specifies the ABI. It overrides the '-mshort', 13682 '-mlong', '-mshort-double' and '-mlong-double' options. 13683 13684'.far SYMBOL' 13685 This directive marks the symbol as a 'far' symbol meaning that it 13686 uses a 'call/rtc' calling convention as opposed to 'jsr/rts'. 13687 During a final link, the linker will identify references to the 13688 'far' symbol and will verify the proper calling convention. 13689 13690'.interrupt SYMBOL' 13691 This directive marks the symbol as an interrupt entry point. This 13692 information is then used by the debugger to correctly unwind the 13693 frame across interrupts. 13694 13695'.xrefb SYMBOL' 13696 This directive is defined for compatibility with the 'Specification 13697 for Motorola 8 and 16-Bit Assembly Language Input Standard' and is 13698 ignored. 13699 13700 13701File: as.info, Node: M68HC11-Float, Next: M68HC11-opcodes, Prev: M68HC11-Directives, Up: M68HC11-Dependent 13702 137039.24.5 Floating Point 13704--------------------- 13705 13706Packed decimal (P) format floating literals are not supported. Feel 13707free to add the code! 13708 13709 The floating point formats generated by directives are these. 13710 13711'.float' 13712 'Single' precision floating point constants. 13713 13714'.double' 13715 'Double' precision floating point constants. 13716 13717'.extend' 13718'.ldouble' 13719 'Extended' precision ('long double') floating point constants. 13720 13721 13722File: as.info, Node: M68HC11-opcodes, Prev: M68HC11-Float, Up: M68HC11-Dependent 13723 137249.24.6 Opcodes 13725-------------- 13726 13727* Menu: 13728 13729* M68HC11-Branch:: Branch Improvement 13730 13731 13732File: as.info, Node: M68HC11-Branch, Up: M68HC11-opcodes 13733 137349.24.6.1 Branch Improvement 13735........................... 13736 13737Certain pseudo opcodes are permitted for branch instructions. They 13738expand to the shortest branch instruction that reach the target. 13739Generally these mnemonics are made by prepending 'j' to the start of 13740Motorola mnemonic. These pseudo opcodes are not affected by the 13741'--short-branches' or '--force-long-branches' options. 13742 13743 The following table summarizes the pseudo-operations. 13744 13745 Displacement Width 13746 +-------------------------------------------------------------+ 13747 | Options | 13748 | --short-branches --force-long-branches | 13749 +--------------------------+----------------------------------+ 13750 Op |BYTE WORD | BYTE WORD | 13751 +--------------------------+----------------------------------+ 13752 bsr | bsr <pc-rel> <error> | jsr <abs> | 13753 bra | bra <pc-rel> <error> | jmp <abs> | 13754 jbsr | bsr <pc-rel> jsr <abs> | bsr <pc-rel> jsr <abs> | 13755 jbra | bra <pc-rel> jmp <abs> | bra <pc-rel> jmp <abs> | 13756 bXX | bXX <pc-rel> <error> | bNX +3; jmp <abs> | 13757 jbXX | bXX <pc-rel> bNX +3; | bXX <pc-rel> bNX +3; jmp <abs> | 13758 | jmp <abs> | | 13759 +--------------------------+----------------------------------+ 13760 XX: condition 13761 NX: negative of condition XX 13762 13763 13764'jbsr' 13765'jbra' 13766 These are the simplest jump pseudo-operations; they always map to 13767 one particular machine instruction, depending on the displacement 13768 to the branch target. 13769 13770'jbXX' 13771 Here, 'jbXX' stands for an entire family of pseudo-operations, 13772 where XX is a conditional branch or condition-code test. The full 13773 list of pseudo-ops in this family is: 13774 jbcc jbeq jbge jbgt jbhi jbvs jbpl jblo 13775 jbcs jbne jblt jble jbls jbvc jbmi 13776 13777 For the cases of non-PC relative displacements and long 13778 displacements, 'as' issues a longer code fragment in terms of NX, 13779 the opposite condition to XX. For example, for the non-PC relative 13780 case: 13781 jbXX foo 13782 gives 13783 bNXs oof 13784 jmp foo 13785 oof: 13786 13787 13788File: as.info, Node: Meta-Dependent, Next: MicroBlaze-Dependent, Prev: M68HC11-Dependent, Up: Machine Dependencies 13789 137909.25 Meta Dependent Features 13791============================ 13792 13793* Menu: 13794 13795* Meta Options:: Options 13796* Meta Syntax:: Meta Assembler Syntax 13797 13798 13799File: as.info, Node: Meta Options, Next: Meta Syntax, Up: Meta-Dependent 13800 138019.25.1 Options 13802-------------- 13803 13804The Imagination Technologies Meta architecture is implemented in a 13805number of versions, with each new version adding new features such as 13806instructions and registers. For precise details of what instructions 13807each core supports, please see the chip's technical reference manual. 13808 13809 The following table lists all available Meta options. 13810 13811'-mcpu=metac11' 13812 Generate code for Meta 1.1. 13813 13814'-mcpu=metac12' 13815 Generate code for Meta 1.2. 13816 13817'-mcpu=metac21' 13818 Generate code for Meta 2.1. 13819 13820'-mfpu=metac21' 13821 Allow code to use FPU hardware of Meta 2.1. 13822 13823 13824File: as.info, Node: Meta Syntax, Prev: Meta Options, Up: Meta-Dependent 13825 138269.25.2 Syntax 13827------------- 13828 13829* Menu: 13830 13831* Meta-Chars:: Special Characters 13832* Meta-Regs:: Register Names 13833 13834 13835File: as.info, Node: Meta-Chars, Next: Meta-Regs, Up: Meta Syntax 13836 138379.25.2.1 Special Characters 13838........................... 13839 13840'!' is the line comment character. 13841 13842 You can use ';' instead of a newline to separate statements. 13843 13844 Since '$' has no special meaning, you may use it in symbol names. 13845 13846 13847File: as.info, Node: Meta-Regs, Prev: Meta-Chars, Up: Meta Syntax 13848 138499.25.2.2 Register Names 13850....................... 13851 13852Registers can be specified either using their mnemonic names, such as 13853'D0Re0', or using the unit plus register number separated by a '.', such 13854as 'D0.0'. 13855 13856 13857File: as.info, Node: MicroBlaze-Dependent, Next: MIPS-Dependent, Prev: Meta-Dependent, Up: Machine Dependencies 13858 138599.26 MicroBlaze Dependent Features 13860================================== 13861 13862The Xilinx MicroBlaze processor family includes several variants, all 13863using the same core instruction set. This chapter covers features of 13864the GNU assembler that are specific to the MicroBlaze architecture. For 13865details about the MicroBlaze instruction set, please see the 'MicroBlaze 13866Processor Reference Guide (UG081)' available at www.xilinx.com. 13867 13868* Menu: 13869 13870* MicroBlaze Directives:: Directives for MicroBlaze Processors. 13871* MicroBlaze Syntax:: Syntax for the MicroBlaze 13872 13873 13874File: as.info, Node: MicroBlaze Directives, Next: MicroBlaze Syntax, Up: MicroBlaze-Dependent 13875 138769.26.1 Directives 13877----------------- 13878 13879A number of assembler directives are available for MicroBlaze. 13880 13881'.data8 EXPRESSION,...' 13882 This directive is an alias for '.byte'. Each expression is 13883 assembled into an eight-bit value. 13884 13885'.data16 EXPRESSION,...' 13886 This directive is an alias for '.hword'. Each expression is 13887 assembled into an 16-bit value. 13888 13889'.data32 EXPRESSION,...' 13890 This directive is an alias for '.word'. Each expression is 13891 assembled into an 32-bit value. 13892 13893'.ent NAME[,LABEL]' 13894 This directive is an alias for '.func' denoting the start of 13895 function NAME at (optional) LABEL. 13896 13897'.end NAME[,LABEL]' 13898 This directive is an alias for '.endfunc' denoting the end of 13899 function NAME. 13900 13901'.gpword LABEL,...' 13902 This directive is an alias for '.rva'. The resolved address of 13903 LABEL is stored in the data section. 13904 13905'.weakext LABEL' 13906 Declare that LABEL is a weak external symbol. 13907 13908'.rodata' 13909 Switch to .rodata section. Equivalent to '.section .rodata' 13910 13911'.sdata2' 13912 Switch to .sdata2 section. Equivalent to '.section .sdata2' 13913 13914'.sdata' 13915 Switch to .sdata section. Equivalent to '.section .sdata' 13916 13917'.bss' 13918 Switch to .bss section. Equivalent to '.section .bss' 13919 13920'.sbss' 13921 Switch to .sbss section. Equivalent to '.section .sbss' 13922 13923 13924File: as.info, Node: MicroBlaze Syntax, Prev: MicroBlaze Directives, Up: MicroBlaze-Dependent 13925 139269.26.2 Syntax for the MicroBlaze 13927-------------------------------- 13928 13929* Menu: 13930 13931* MicroBlaze-Chars:: Special Characters 13932 13933 13934File: as.info, Node: MicroBlaze-Chars, Up: MicroBlaze Syntax 13935 139369.26.2.1 Special Characters 13937........................... 13938 13939The presence of a '#' on a line indicates the start of a comment that 13940extends to the end of the current line. 13941 13942 If a '#' appears as the first character of a line, the whole line is 13943treated as a comment, but in this case the line can also be a logical 13944line number directive (*note Comments::) or a preprocessor control 13945command (*note Preprocessing::). 13946 13947 The ';' character can be used to separate statements on the same 13948line. 13949 13950 13951File: as.info, Node: MIPS-Dependent, Next: MMIX-Dependent, Prev: MicroBlaze-Dependent, Up: Machine Dependencies 13952 139539.27 MIPS Dependent Features 13954============================ 13955 13956GNU 'as' for MIPS architectures supports several different MIPS 13957processors, and MIPS ISA levels I through V, MIPS32, and MIPS64. For 13958information about the MIPS instruction set, see 'MIPS RISC 13959Architecture', by Kane and Heindrich (Prentice-Hall). For an overview 13960of MIPS assembly conventions, see "Appendix D: Assembly Language 13961Programming" in the same work. 13962 13963* Menu: 13964 13965* MIPS Options:: Assembler options 13966* MIPS Macros:: High-level assembly macros 13967* MIPS Symbol Sizes:: Directives to override the size of symbols 13968* MIPS Small Data:: Controlling the use of small data accesses 13969* MIPS ISA:: Directives to override the ISA level 13970* MIPS assembly options:: Directives to control code generation 13971* MIPS autoextend:: Directives for extending MIPS 16 bit instructions 13972* MIPS insn:: Directive to mark data as an instruction 13973* MIPS FP ABIs:: Marking which FP ABI is in use 13974* MIPS NaN Encodings:: Directives to record which NaN encoding is being used 13975* MIPS Option Stack:: Directives to save and restore options 13976* MIPS ASE Instruction Generation Overrides:: Directives to control 13977 generation of MIPS ASE instructions 13978* MIPS Floating-Point:: Directives to override floating-point options 13979* MIPS Syntax:: MIPS specific syntactical considerations 13980 13981 13982File: as.info, Node: MIPS Options, Next: MIPS Macros, Up: MIPS-Dependent 13983 139849.27.1 Assembler options 13985------------------------ 13986 13987The MIPS configurations of GNU 'as' support these special options: 13988 13989'-G NUM' 13990 Set the "small data" limit to N bytes. The default limit is 8 13991 bytes. *Note Controlling the use of small data accesses: MIPS 13992 Small Data. 13993 13994'-EB' 13995'-EL' 13996 Any MIPS configuration of 'as' can select big-endian or 13997 little-endian output at run time (unlike the other GNU development 13998 tools, which must be configured for one or the other). Use '-EB' 13999 to select big-endian output, and '-EL' for little-endian. 14000 14001'-KPIC' 14002 Generate SVR4-style PIC. This option tells the assembler to 14003 generate SVR4-style position-independent macro expansions. It also 14004 tells the assembler to mark the output file as PIC. 14005 14006'-mvxworks-pic' 14007 Generate VxWorks PIC. This option tells the assembler to generate 14008 VxWorks-style position-independent macro expansions. 14009 14010'-mips1' 14011'-mips2' 14012'-mips3' 14013'-mips4' 14014'-mips5' 14015'-mips32' 14016'-mips32r2' 14017'-mips32r3' 14018'-mips32r5' 14019'-mips32r6' 14020'-mips64' 14021'-mips64r2' 14022'-mips64r3' 14023'-mips64r5' 14024'-mips64r6' 14025 Generate code for a particular MIPS Instruction Set Architecture 14026 level. '-mips1' corresponds to the R2000 and R3000 processors, 14027 '-mips2' to the R6000 processor, '-mips3' to the R4000 processor, 14028 and '-mips4' to the R8000 and R10000 processors. '-mips5', 14029 '-mips32', '-mips32r2', '-mips32r3', '-mips32r5', '-mips32r6', 14030 '-mips64', '-mips64r2', '-mips64r3', '-mips64r5', and '-mips64r6' 14031 correspond to generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32 14032 Release 3, MIPS32 Release 5, MIPS32 Release 6, MIPS64, and MIPS64 14033 Release 2, MIPS64 Release 3, MIPS64 Release 5, and MIPS64 Release 6 14034 ISA processors, respectively. You can also switch instruction sets 14035 during the assembly; see *note Directives to override the ISA 14036 level: MIPS ISA. 14037 14038'-mgp32' 14039'-mfp32' 14040 Some macros have different expansions for 32-bit and 64-bit 14041 registers. The register sizes are normally inferred from the ISA 14042 and ABI, but these flags force a certain group of registers to be 14043 treated as 32 bits wide at all times. '-mgp32' controls the size 14044 of general-purpose registers and '-mfp32' controls the size of 14045 floating-point registers. 14046 14047 The '.set gp=32' and '.set fp=32' directives allow the size of 14048 registers to be changed for parts of an object. The default value 14049 is restored by '.set gp=default' and '.set fp=default'. 14050 14051 On some MIPS variants there is a 32-bit mode flag; when this flag 14052 is set, 64-bit instructions generate a trap. Also, some 32-bit 14053 OSes only save the 32-bit registers on a context switch, so it is 14054 essential never to use the 64-bit registers. 14055 14056'-mgp64' 14057'-mfp64' 14058 Assume that 64-bit registers are available. This is provided in 14059 the interests of symmetry with '-mgp32' and '-mfp32'. 14060 14061 The '.set gp=64' and '.set fp=64' directives allow the size of 14062 registers to be changed for parts of an object. The default value 14063 is restored by '.set gp=default' and '.set fp=default'. 14064 14065'-mfpxx' 14066 Make no assumptions about whether 32-bit or 64-bit floating-point 14067 registers are available. This is provided to support having 14068 modules compatible with either '-mfp32' or '-mfp64'. This option 14069 can only be used with MIPS II and above. 14070 14071 The '.set fp=xx' directive allows a part of an object to be marked 14072 as not making assumptions about 32-bit or 64-bit FP registers. The 14073 default value is restored by '.set fp=default'. 14074 14075'-modd-spreg' 14076'-mno-odd-spreg' 14077 Enable use of floating-point operations on odd-numbered 14078 single-precision registers when supported by the ISA. '-mfpxx' 14079 implies '-mno-odd-spreg', otherwise the default is '-modd-spreg' 14080 14081'-mips16' 14082'-no-mips16' 14083 Generate code for the MIPS 16 processor. This is equivalent to 14084 putting '.set mips16' at the start of the assembly file. 14085 '-no-mips16' turns off this option. 14086 14087'-mmicromips' 14088'-mno-micromips' 14089 Generate code for the microMIPS processor. This is equivalent to 14090 putting '.set micromips' at the start of the assembly file. 14091 '-mno-micromips' turns off this option. This is equivalent to 14092 putting '.set nomicromips' at the start of the assembly file. 14093 14094'-msmartmips' 14095'-mno-smartmips' 14096 Enables the SmartMIPS extensions to the MIPS32 instruction set, 14097 which provides a number of new instructions which target smartcard 14098 and cryptographic applications. This is equivalent to putting 14099 '.set smartmips' at the start of the assembly file. 14100 '-mno-smartmips' turns off this option. 14101 14102'-mips3d' 14103'-no-mips3d' 14104 Generate code for the MIPS-3D Application Specific Extension. This 14105 tells the assembler to accept MIPS-3D instructions. '-no-mips3d' 14106 turns off this option. 14107 14108'-mdmx' 14109'-no-mdmx' 14110 Generate code for the MDMX Application Specific Extension. This 14111 tells the assembler to accept MDMX instructions. '-no-mdmx' turns 14112 off this option. 14113 14114'-mdsp' 14115'-mno-dsp' 14116 Generate code for the DSP Release 1 Application Specific Extension. 14117 This tells the assembler to accept DSP Release 1 instructions. 14118 '-mno-dsp' turns off this option. 14119 14120'-mdspr2' 14121'-mno-dspr2' 14122 Generate code for the DSP Release 2 Application Specific Extension. 14123 This option implies '-mdsp'. This tells the assembler to accept 14124 DSP Release 2 instructions. '-mno-dspr2' turns off this option. 14125 14126'-mdspr3' 14127'-mno-dspr3' 14128 Generate code for the DSP Release 3 Application Specific Extension. 14129 This option implies '-mdsp' and '-mdspr2'. This tells the 14130 assembler to accept DSP Release 3 instructions. '-mno-dspr3' turns 14131 off this option. 14132 14133'-mmt' 14134'-mno-mt' 14135 Generate code for the MT Application Specific Extension. This 14136 tells the assembler to accept MT instructions. '-mno-mt' turns off 14137 this option. 14138 14139'-mmcu' 14140'-mno-mcu' 14141 Generate code for the MCU Application Specific Extension. This 14142 tells the assembler to accept MCU instructions. '-mno-mcu' turns 14143 off this option. 14144 14145'-mmsa' 14146'-mno-msa' 14147 Generate code for the MIPS SIMD Architecture Extension. This tells 14148 the assembler to accept MSA instructions. '-mno-msa' turns off 14149 this option. 14150 14151'-mxpa' 14152'-mno-xpa' 14153 Generate code for the MIPS eXtended Physical Address (XPA) 14154 Extension. This tells the assembler to accept XPA instructions. 14155 '-mno-xpa' turns off this option. 14156 14157'-mvirt' 14158'-mno-virt' 14159 Generate code for the Virtualization Application Specific 14160 Extension. This tells the assembler to accept Virtualization 14161 instructions. '-mno-virt' turns off this option. 14162 14163'-minsn32' 14164'-mno-insn32' 14165 Only use 32-bit instruction encodings when generating code for the 14166 microMIPS processor. This option inhibits the use of any 16-bit 14167 instructions. This is equivalent to putting '.set insn32' at the 14168 start of the assembly file. '-mno-insn32' turns off this option. 14169 This is equivalent to putting '.set noinsn32' at the start of the 14170 assembly file. By default '-mno-insn32' is selected, allowing all 14171 instructions to be used. 14172 14173'-mfix7000' 14174'-mno-fix7000' 14175 Cause nops to be inserted if the read of the destination register 14176 of an mfhi or mflo instruction occurs in the following two 14177 instructions. 14178 14179'-mfix-rm7000' 14180'-mno-fix-rm7000' 14181 Cause nops to be inserted if a dmult or dmultu instruction is 14182 followed by a load instruction. 14183 14184'-mfix-loongson2f-jump' 14185'-mno-fix-loongson2f-jump' 14186 Eliminate instruction fetch from outside 256M region to work around 14187 the Loongson2F 'jump' instructions. Without it, under extreme 14188 cases, the kernel may crash. The issue has been solved in latest 14189 processor batches, but this fix has no side effect to them. 14190 14191'-mfix-loongson2f-nop' 14192'-mno-fix-loongson2f-nop' 14193 Replace nops by 'or at,at,zero' to work around the Loongson2F 'nop' 14194 errata. Without it, under extreme cases, the CPU might deadlock. 14195 The issue has been solved in later Loongson2F batches, but this fix 14196 has no side effect to them. 14197 14198'-mfix-vr4120' 14199'-mno-fix-vr4120' 14200 Insert nops to work around certain VR4120 errata. This option is 14201 intended to be used on GCC-generated code: it is not designed to 14202 catch all problems in hand-written assembler code. 14203 14204'-mfix-vr4130' 14205'-mno-fix-vr4130' 14206 Insert nops to work around the VR4130 'mflo'/'mfhi' errata. 14207 14208'-mfix-24k' 14209'-mno-fix-24k' 14210 Insert nops to work around the 24K 'eret'/'deret' errata. 14211 14212'-mfix-cn63xxp1' 14213'-mno-fix-cn63xxp1' 14214 Replace 'pref' hints 0 - 4 and 6 - 24 with hint 28 to work around 14215 certain CN63XXP1 errata. 14216 14217'-m4010' 14218'-no-m4010' 14219 Generate code for the LSI R4010 chip. This tells the assembler to 14220 accept the R4010-specific instructions ('addciu', 'ffc', etc.), and 14221 to not schedule 'nop' instructions around accesses to the 'HI' and 14222 'LO' registers. '-no-m4010' turns off this option. 14223 14224'-m4650' 14225'-no-m4650' 14226 Generate code for the MIPS R4650 chip. This tells the assembler to 14227 accept the 'mad' and 'madu' instruction, and to not schedule 'nop' 14228 instructions around accesses to the 'HI' and 'LO' registers. 14229 '-no-m4650' turns off this option. 14230 14231'-m3900' 14232'-no-m3900' 14233'-m4100' 14234'-no-m4100' 14235 For each option '-mNNNN', generate code for the MIPS RNNNN chip. 14236 This tells the assembler to accept instructions specific to that 14237 chip, and to schedule for that chip's hazards. 14238 14239'-march=CPU' 14240 Generate code for a particular MIPS CPU. It is exactly equivalent 14241 to '-mCPU', except that there are more value of CPU understood. 14242 Valid CPU value are: 14243 14244 2000, 3000, 3900, 4000, 4010, 4100, 4111, vr4120, vr4130, 14245 vr4181, 4300, 4400, 4600, 4650, 5000, rm5200, rm5230, rm5231, 14246 rm5261, rm5721, vr5400, vr5500, 6000, rm7000, 8000, rm9000, 14247 10000, 12000, 14000, 16000, 4kc, 4km, 4kp, 4ksc, 4kec, 4kem, 14248 4kep, 4ksd, m4k, m4kp, m14k, m14kc, m14ke, m14kec, 24kc, 14249 24kf2_1, 24kf, 24kf1_1, 24kec, 24kef2_1, 24kef, 24kef1_1, 14250 34kc, 34kf2_1, 34kf, 34kf1_1, 34kn, 74kc, 74kf2_1, 74kf, 14251 74kf1_1, 74kf3_2, 1004kc, 1004kf2_1, 1004kf, 1004kf1_1, 14252 interaptiv, m5100, m5101, p5600, 5kc, 5kf, 20kc, 25kf, sb1, 14253 sb1a, i6400, p6600, loongson2e, loongson2f, loongson3a, 14254 octeon, octeon+, octeon2, octeon3, xlr, xlp 14255 14256 For compatibility reasons, 'Nx' and 'Bfx' are accepted as synonyms 14257 for 'Nf1_1'. These values are deprecated. 14258 14259'-mtune=CPU' 14260 Schedule and tune for a particular MIPS CPU. Valid CPU values are 14261 identical to '-march=CPU'. 14262 14263'-mabi=ABI' 14264 Record which ABI the source code uses. The recognized arguments 14265 are: '32', 'n32', 'o64', '64' and 'eabi'. 14266 14267'-msym32' 14268'-mno-sym32' 14269 Equivalent to adding '.set sym32' or '.set nosym32' to the 14270 beginning of the assembler input. *Note MIPS Symbol Sizes::. 14271 14272'-nocpp' 14273 This option is ignored. It is accepted for command-line 14274 compatibility with other assemblers, which use it to turn off C 14275 style preprocessing. With GNU 'as', there is no need for '-nocpp', 14276 because the GNU assembler itself never runs the C preprocessor. 14277 14278'-msoft-float' 14279'-mhard-float' 14280 Disable or enable floating-point instructions. Note that by 14281 default floating-point instructions are always allowed even with 14282 CPU targets that don't have support for these instructions. 14283 14284'-msingle-float' 14285'-mdouble-float' 14286 Disable or enable double-precision floating-point operations. Note 14287 that by default double-precision floating-point operations are 14288 always allowed even with CPU targets that don't have support for 14289 these operations. 14290 14291'--construct-floats' 14292'--no-construct-floats' 14293 The '--no-construct-floats' option disables the construction of 14294 double width floating point constants by loading the two halves of 14295 the value into the two single width floating point registers that 14296 make up the double width register. This feature is useful if the 14297 processor support the FR bit in its status register, and this bit 14298 is known (by the programmer) to be set. This bit prevents the 14299 aliasing of the double width register by the single width 14300 registers. 14301 14302 By default '--construct-floats' is selected, allowing construction 14303 of these floating point constants. 14304 14305'--relax-branch' 14306'--no-relax-branch' 14307 The '--relax-branch' option enables the relaxation of out-of-range 14308 branches. Any branches whose target cannot be reached directly are 14309 converted to a small instruction sequence including an 14310 inverse-condition branch to the physically next instruction, and a 14311 jump to the original target is inserted between the two 14312 instructions. In PIC code the jump will involve further 14313 instructions for address calculation. 14314 14315 The 'BC1ANY2F', 'BC1ANY2T', 'BC1ANY4F', 'BC1ANY4T', 'BPOSGE32' and 14316 'BPOSGE64' instructions are excluded from relaxation, because they 14317 have no complementing counterparts. They could be relaxed with the 14318 use of a longer sequence involving another branch, however this has 14319 not been implemented and if their target turns out of reach, they 14320 produce an error even if branch relaxation is enabled. 14321 14322 Also no MIPS16 branches are ever relaxed. 14323 14324 By default '--no-relax-branch' is selected, causing any 14325 out-of-range branches to produce an error. 14326 14327'-mignore-branch-isa' 14328'-mno-ignore-branch-isa' 14329 Ignore branch checks for invalid transitions between ISA modes. 14330 14331 The semantics of branches does not provide for an ISA mode switch, 14332 so in most cases the ISA mode a branch has been encoded for has to 14333 be the same as the ISA mode of the branch's target label. If the 14334 ISA modes do not match, then such a branch, if taken, will cause 14335 the ISA mode to remain unchanged and instructions that follow will 14336 be executed in the wrong ISA mode causing the program to misbehave 14337 or crash. 14338 14339 In the case of the 'BAL' instruction it may be possible to relax it 14340 to an equivalent 'JALX' instruction so that the ISA mode is 14341 switched at the run time as required. For other branches no 14342 relaxation is possible and therefore GAS has checks implemented 14343 that verify in branch assembly that the two ISA modes match, and 14344 report an error otherwise so that the problem with code can be 14345 diagnosed at the assembly time rather than at the run time. 14346 14347 However some assembly code, including generated code produced by 14348 some versions of GCC, may incorrectly include branches to data 14349 labels, which appear to require a mode switch but are either dead 14350 or immediately followed by valid instructions encoded for the same 14351 ISA the branch has been encoded for. While not strictly correct at 14352 the source level such code will execute as intended, so to help 14353 with these cases '-mignore-branch-isa' is supported which disables 14354 ISA mode checks for branches. 14355 14356 By default '-mno-ignore-branch-isa' is selected, causing any 14357 invalid branch requiring a transition between ISA modes to produce 14358 an error. 14359 14360'-mnan=ENCODING' 14361 This option indicates whether the source code uses the IEEE 2008 14362 NaN encoding ('-mnan=2008') or the original MIPS encoding 14363 ('-mnan=legacy'). It is equivalent to adding a '.nan' directive to 14364 the beginning of the source file. *Note MIPS NaN Encodings::. 14365 14366 '-mnan=legacy' is the default if no '-mnan' option or '.nan' 14367 directive is used. 14368 14369'--trap' 14370'--no-break' 14371 'as' automatically macro expands certain division and 14372 multiplication instructions to check for overflow and division by 14373 zero. This option causes 'as' to generate code to take a trap 14374 exception rather than a break exception when an error is detected. 14375 The trap instructions are only supported at Instruction Set 14376 Architecture level 2 and higher. 14377 14378'--break' 14379'--no-trap' 14380 Generate code to take a break exception rather than a trap 14381 exception when an error is detected. This is the default. 14382 14383'-mpdr' 14384'-mno-pdr' 14385 Control generation of '.pdr' sections. Off by default on IRIX, on 14386 elsewhere. 14387 14388'-mshared' 14389'-mno-shared' 14390 When generating code using the Unix calling conventions (selected 14391 by '-KPIC' or '-mcall_shared'), gas will normally generate code 14392 which can go into a shared library. The '-mno-shared' option tells 14393 gas to generate code which uses the calling convention, but can not 14394 go into a shared library. The resulting code is slightly more 14395 efficient. This option only affects the handling of the '.cpload' 14396 and '.cpsetup' pseudo-ops. 14397 14398 14399File: as.info, Node: MIPS Macros, Next: MIPS Symbol Sizes, Prev: MIPS Options, Up: MIPS-Dependent 14400 144019.27.2 High-level assembly macros 14402--------------------------------- 14403 14404MIPS assemblers have traditionally provided a wider range of 14405instructions than the MIPS architecture itself. These extra 14406instructions are usually referred to as "macro" instructions (1). 14407 14408 Some MIPS macro instructions extend an underlying architectural 14409instruction while others are entirely new. An example of the former 14410type is 'and', which allows the third operand to be either a register or 14411an arbitrary immediate value. Examples of the latter type include 14412'bgt', which branches to the third operand when the first operand is 14413greater than the second operand, and 'ulh', which implements an 14414unaligned 2-byte load. 14415 14416 One of the most common extensions provided by macros is to expand 14417memory offsets to the full address range (32 or 64 bits) and to allow 14418symbolic offsets such as 'my_data + 4' to be used in place of integer 14419constants. For example, the architectural instruction 'lbu' allows only 14420a signed 16-bit offset, whereas the macro 'lbu' allows code such as 'lbu 14421$4,array+32769($5)'. The implementation of these symbolic offsets 14422depends on several factors, such as whether the assembler is generating 14423SVR4-style PIC (selected by '-KPIC', *note Assembler options: MIPS 14424Options.), the size of symbols (*note Directives to override the size of 14425symbols: MIPS Symbol Sizes.), and the small data limit (*note 14426Controlling the use of small data accesses: MIPS Small Data.). 14427 14428 Sometimes it is undesirable to have one assembly instruction expand 14429to several machine instructions. The directive '.set nomacro' tells the 14430assembler to warn when this happens. '.set macro' restores the default 14431behavior. 14432 14433 Some macro instructions need a temporary register to store 14434intermediate results. This register is usually '$1', also known as 14435'$at', but it can be changed to any core register REG using '.set 14436at=REG'. Note that '$at' always refers to '$1' regardless of which 14437register is being used as the temporary register. 14438 14439 Implicit uses of the temporary register in macros could interfere 14440with explicit uses in the assembly code. The assembler therefore warns 14441whenever it sees an explicit use of the temporary register. The 14442directive '.set noat' silences this warning while '.set at' restores the 14443default behavior. It is safe to use '.set noat' while '.set nomacro' is 14444in effect since single-instruction macros never need a temporary 14445register. 14446 14447 Note that while the GNU assembler provides these macros for 14448compatibility, it does not make any attempt to optimize them with the 14449surrounding code. 14450 14451 ---------- Footnotes ---------- 14452 14453 (1) The term "macro" is somewhat overloaded here, since these macros 14454have no relation to those defined by '.macro', *note '.macro': Macro. 14455 14456 14457File: as.info, Node: MIPS Symbol Sizes, Next: MIPS Small Data, Prev: MIPS Macros, Up: MIPS-Dependent 14458 144599.27.3 Directives to override the size of symbols 14460------------------------------------------------- 14461 14462The n64 ABI allows symbols to have any 64-bit value. Although this 14463provides a great deal of flexibility, it means that some macros have 14464much longer expansions than their 32-bit counterparts. For example, the 14465non-PIC expansion of 'dla $4,sym' is usually: 14466 14467 lui $4,%highest(sym) 14468 lui $1,%hi(sym) 14469 daddiu $4,$4,%higher(sym) 14470 daddiu $1,$1,%lo(sym) 14471 dsll32 $4,$4,0 14472 daddu $4,$4,$1 14473 14474 whereas the 32-bit expansion is simply: 14475 14476 lui $4,%hi(sym) 14477 daddiu $4,$4,%lo(sym) 14478 14479 n64 code is sometimes constructed in such a way that all symbolic 14480constants are known to have 32-bit values, and in such cases, it's 14481preferable to use the 32-bit expansion instead of the 64-bit expansion. 14482 14483 You can use the '.set sym32' directive to tell the assembler that, 14484from this point on, all expressions of the form 'SYMBOL' or 'SYMBOL + 14485OFFSET' have 32-bit values. For example: 14486 14487 .set sym32 14488 dla $4,sym 14489 lw $4,sym+16 14490 sw $4,sym+0x8000($4) 14491 14492 will cause the assembler to treat 'sym', 'sym+16' and 'sym+0x8000' as 1449332-bit values. The handling of non-symbolic addresses is not affected. 14494 14495 The directive '.set nosym32' ends a '.set sym32' block and reverts to 14496the normal behavior. It is also possible to change the symbol size 14497using the command-line options '-msym32' and '-mno-sym32'. 14498 14499 These options and directives are always accepted, but at present, 14500they have no effect for anything other than n64. 14501 14502 14503File: as.info, Node: MIPS Small Data, Next: MIPS ISA, Prev: MIPS Symbol Sizes, Up: MIPS-Dependent 14504 145059.27.4 Controlling the use of small data accesses 14506------------------------------------------------- 14507 14508It often takes several instructions to load the address of a symbol. 14509For example, when 'addr' is a 32-bit symbol, the non-PIC expansion of 14510'dla $4,addr' is usually: 14511 14512 lui $4,%hi(addr) 14513 daddiu $4,$4,%lo(addr) 14514 14515 The sequence is much longer when 'addr' is a 64-bit symbol. *Note 14516Directives to override the size of symbols: MIPS Symbol Sizes. 14517 14518 In order to cut down on this overhead, most embedded MIPS systems set 14519aside a 64-kilobyte "small data" area and guarantee that all data of 14520size N and smaller will be placed in that area. The limit N is passed 14521to both the assembler and the linker using the command-line option '-G 14522N', *note Assembler options: MIPS Options. Note that the same value of 14523N must be used when linking and when assembling all input files to the 14524link; any inconsistency could cause a relocation overflow error. 14525 14526 The size of an object in the '.bss' section is set by the '.comm' or 14527'.lcomm' directive that defines it. The size of an external object may 14528be set with the '.extern' directive. For example, '.extern sym,4' 14529declares that the object at 'sym' is 4 bytes in length, while leaving 14530'sym' otherwise undefined. 14531 14532 When no '-G' option is given, the default limit is 8 bytes. The 14533option '-G 0' prevents any data from being automatically classified as 14534small. 14535 14536 It is also possible to mark specific objects as small by putting them 14537in the special sections '.sdata' and '.sbss', which are "small" 14538counterparts of '.data' and '.bss' respectively. The toolchain will 14539treat such data as small regardless of the '-G' setting. 14540 14541 On startup, systems that support a small data area are expected to 14542initialize register '$28', also known as '$gp', in such a way that small 14543data can be accessed using a 16-bit offset from that register. For 14544example, when 'addr' is small data, the 'dla $4,addr' instruction above 14545is equivalent to: 14546 14547 daddiu $4,$28,%gp_rel(addr) 14548 14549 Small data is not supported for SVR4-style PIC. 14550 14551 14552File: as.info, Node: MIPS ISA, Next: MIPS assembly options, Prev: MIPS Small Data, Up: MIPS-Dependent 14553 145549.27.5 Directives to override the ISA level 14555------------------------------------------- 14556 14557GNU 'as' supports an additional directive to change the MIPS Instruction 14558Set Architecture level on the fly: '.set mipsN'. N should be a number 14559from 0 to 5, or 32, 32r2, 32r3, 32r5, 32r6, 64, 64r2, 64r3, 64r5 or 1456064r6. The values other than 0 make the assembler accept instructions 14561for the corresponding ISA level, from that point on in the assembly. 14562'.set mipsN' affects not only which instructions are permitted, but also 14563how certain macros are expanded. '.set mips0' restores the ISA level to 14564its original level: either the level you selected with command line 14565options, or the default for your configuration. You can use this 14566feature to permit specific MIPS III instructions while assembling in 32 14567bit mode. Use this directive with care! 14568 14569 The '.set arch=CPU' directive provides even finer control. It 14570changes the effective CPU target and allows the assembler to use 14571instructions specific to a particular CPU. All CPUs supported by the 14572'-march' command line option are also selectable by this directive. The 14573original value is restored by '.set arch=default'. 14574 14575 The directive '.set mips16' puts the assembler into MIPS 16 mode, in 14576which it will assemble instructions for the MIPS 16 processor. Use 14577'.set nomips16' to return to normal 32 bit mode. 14578 14579 Traditional MIPS assemblers do not support this directive. 14580 14581 The directive '.set micromips' puts the assembler into microMIPS 14582mode, in which it will assemble instructions for the microMIPS 14583processor. Use '.set nomicromips' to return to normal 32 bit mode. 14584 14585 Traditional MIPS assemblers do not support this directive. 14586 14587 14588File: as.info, Node: MIPS assembly options, Next: MIPS autoextend, Prev: MIPS ISA, Up: MIPS-Dependent 14589 145909.27.6 Directives to control code generation 14591-------------------------------------------- 14592 14593The '.module' directive allows command line options to be set directly 14594from assembly. The format of the directive matches the '.set' directive 14595but only those options which are relevant to a whole module are 14596supported. The effect of a '.module' directive is the same as the 14597corresponding command line option. Where '.set' directives support 14598returning to a default then the '.module' directives do not as they 14599define the defaults. 14600 14601 These module-level directives must appear first in assembly. 14602 14603 Traditional MIPS assemblers do not support this directive. 14604 14605 The directive '.set insn32' makes the assembler only use 32-bit 14606instruction encodings when generating code for the microMIPS processor. 14607This directive inhibits the use of any 16-bit instructions from that 14608point on in the assembly. The '.set noinsn32' directive allows 16-bit 14609instructions to be accepted. 14610 14611 Traditional MIPS assemblers do not support this directive. 14612 14613 14614File: as.info, Node: MIPS autoextend, Next: MIPS insn, Prev: MIPS assembly options, Up: MIPS-Dependent 14615 146169.27.7 Directives for extending MIPS 16 bit instructions 14617-------------------------------------------------------- 14618 14619By default, MIPS 16 instructions are automatically extended to 32 bits 14620when necessary. The directive '.set noautoextend' will turn this off. 14621When '.set noautoextend' is in effect, any 32 bit instruction must be 14622explicitly extended with the '.e' modifier (e.g., 'li.e $4,1000'). The 14623directive '.set autoextend' may be used to once again automatically 14624extend instructions when necessary. 14625 14626 This directive is only meaningful when in MIPS 16 mode. Traditional 14627MIPS assemblers do not support this directive. 14628 14629 14630File: as.info, Node: MIPS insn, Next: MIPS FP ABIs, Prev: MIPS autoextend, Up: MIPS-Dependent 14631 146329.27.8 Directive to mark data as an instruction 14633----------------------------------------------- 14634 14635The '.insn' directive tells 'as' that the following data is actually 14636instructions. This makes a difference in MIPS 16 and microMIPS modes: 14637when loading the address of a label which precedes instructions, 'as' 14638automatically adds 1 to the value, so that jumping to the loaded address 14639will do the right thing. 14640 14641 The '.global' and '.globl' directives supported by 'as' will by 14642default mark the symbol as pointing to a region of data not code. This 14643means that, for example, any instructions following such a symbol will 14644not be disassembled by 'objdump' as it will regard them as data. To 14645change this behavior an optional section name can be placed after the 14646symbol name in the '.global' directive. If this section exists and is 14647known to be a code section, then the symbol will be marked as pointing 14648at code not data. Ie the syntax for the directive is: 14649 14650 '.global SYMBOL[ SECTION][, SYMBOL[ SECTION]] ...', 14651 14652 Here is a short example: 14653 14654 .global foo .text, bar, baz .data 14655 foo: 14656 nop 14657 bar: 14658 .word 0x0 14659 baz: 14660 .word 0x1 14661 14662 14663 14664File: as.info, Node: MIPS FP ABIs, Next: MIPS NaN Encodings, Prev: MIPS insn, Up: MIPS-Dependent 14665 146669.27.9 Directives to control the FP ABI 14667--------------------------------------- 14668 14669* Menu: 14670 14671* MIPS FP ABI History:: History of FP ABIs 14672* MIPS FP ABI Variants:: Supported FP ABIs 14673* MIPS FP ABI Selection:: Automatic selection of FP ABI 14674* MIPS FP ABI Compatibility:: Linking different FP ABI variants 14675 14676 14677File: as.info, Node: MIPS FP ABI History, Next: MIPS FP ABI Variants, Up: MIPS FP ABIs 14678 146799.27.9.1 History of FP ABIs 14680........................... 14681 14682The MIPS ABIs support a variety of different floating-point extensions 14683where calling-convention and register sizes vary for floating-point 14684data. The extensions exist to support a wide variety of optional 14685architecture features. The resulting ABI variants are generally 14686incompatible with each other and must be tracked carefully. 14687 14688 Traditionally the use of an explicit '.gnu_attribute 4, N' directive 14689is used to indicate which ABI is in use by a specific module. It was 14690then left to the user to ensure that command line options and the 14691selected ABI were compatible with some potential for inconsistencies. 14692 14693 14694File: as.info, Node: MIPS FP ABI Variants, Next: MIPS FP ABI Selection, Prev: MIPS FP ABI History, Up: MIPS FP ABIs 14695 146969.27.9.2 Supported FP ABIs 14697.......................... 14698 14699The supported floating-point ABI variants are: 14700 14701'0 - No floating-point' 14702 This variant is used to indicate that floating-point is not used 14703 within the module at all and therefore has no impact on the ABI. 14704 This is the default. 14705 14706'1 - Double-precision' 14707 This variant indicates that double-precision support is used. For 14708 64-bit ABIs this means that 64-bit wide floating-point registers 14709 are required. For 32-bit ABIs this means that 32-bit wide 14710 floating-point registers are required and double-precision 14711 operations use pairs of registers. 14712 14713'2 - Single-precision' 14714 This variant indicates that single-precision support is used. 14715 Double precision operations will be supported via soft-float 14716 routines. 14717 14718'3 - Soft-float' 14719 This variant indicates that although floating-point support is used 14720 all operations are emulated in software. This means the ABI is 14721 modified to pass all floating-point data in general-purpose 14722 registers. 14723 14724'4 - Deprecated' 14725 This variant existed as an initial attempt at supporting 64-bit 14726 wide floating-point registers for O32 ABI on a MIPS32r2 CPU. This 14727 has been superseded by 5, 6 and 7. 14728 14729'5 - Double-precision 32-bit CPU, 32-bit or 64-bit FPU' 14730 This variant is used by 32-bit ABIs to indicate that the 14731 floating-point code in the module has been designed to operate 14732 correctly with either 32-bit wide or 64-bit wide floating-point 14733 registers. Double-precision support is used. Only O32 currently 14734 supports this variant and requires a minimum architecture of MIPS 14735 II. 14736 14737'6 - Double-precision 32-bit FPU, 64-bit FPU' 14738 This variant is used by 32-bit ABIs to indicate that the 14739 floating-point code in the module requires 64-bit wide 14740 floating-point registers. Double-precision support is used. Only 14741 O32 currently supports this variant and requires a minimum 14742 architecture of MIPS32r2. 14743 14744'7 - Double-precision compat 32-bit FPU, 64-bit FPU' 14745 This variant is used by 32-bit ABIs to indicate that the 14746 floating-point code in the module requires 64-bit wide 14747 floating-point registers. Double-precision support is used. This 14748 differs from the previous ABI as it restricts use of odd-numbered 14749 single-precision registers. Only O32 currently supports this 14750 variant and requires a minimum architecture of MIPS32r2. 14751 14752 14753File: as.info, Node: MIPS FP ABI Selection, Next: MIPS FP ABI Compatibility, Prev: MIPS FP ABI Variants, Up: MIPS FP ABIs 14754 147559.27.9.3 Automatic selection of FP ABI 14756...................................... 14757 14758In order to simplify and add safety to the process of selecting the 14759correct floating-point ABI, the assembler will automatically infer the 14760correct '.gnu_attribute 4, N' directive based on command line options 14761and '.module' overrides. Where an explicit '.gnu_attribute 4, N' 14762directive has been seen then a warning will be raised if it does not 14763match an inferred setting. 14764 14765 The floating-point ABI is inferred as follows. If '-msoft-float' has 14766been used the module will be marked as soft-float. If '-msingle-float' 14767has been used then the module will be marked as single-precision. The 14768remaining ABIs are then selected based on the FP register width. 14769Double-precision is selected if the width of GP and FP registers match 14770and the special double-precision variants for 32-bit ABIs are then 14771selected depending on '-mfpxx', '-mfp64' and '-mno-odd-spreg'. 14772 14773 14774File: as.info, Node: MIPS FP ABI Compatibility, Prev: MIPS FP ABI Selection, Up: MIPS FP ABIs 14775 147769.27.9.4 Linking different FP ABI variants 14777.......................................... 14778 14779Modules using the default FP ABI (no floating-point) can be linked with 14780any other (singular) FP ABI variant. 14781 14782 Special compatibility support exists for O32 with the four 14783double-precision FP ABI variants. The '-mfpxx' FP ABI is specifically 14784designed to be compatible with the standard double-precision ABI and the 14785'-mfp64' FP ABIs. This makes it desirable for O32 modules to be built 14786as '-mfpxx' to ensure the maximum compatibility with other modules 14787produced for more specific needs. The only FP ABIs which cannot be 14788linked together are the standard double-precision ABI and the full 14789'-mfp64' ABI with '-modd-spreg'. 14790 14791 14792File: as.info, Node: MIPS NaN Encodings, Next: MIPS Option Stack, Prev: MIPS FP ABIs, Up: MIPS-Dependent 14793 147949.27.10 Directives to record which NaN encoding is being used 14795------------------------------------------------------------- 14796 14797The IEEE 754 floating-point standard defines two types of not-a-number 14798(NaN) data: "signalling" NaNs and "quiet" NaNs. The original version of 14799the standard did not specify how these two types should be 14800distinguished. Most implementations followed the i387 model, in which 14801the first bit of the significand is set for quiet NaNs and clear for 14802signalling NaNs. However, the original MIPS implementation assigned the 14803opposite meaning to the bit, so that it was set for signalling NaNs and 14804clear for quiet NaNs. 14805 14806 The 2008 revision of the standard formally suggested the i387 choice 14807and as from Sep 2012 the current release of the MIPS architecture 14808therefore optionally supports that form. Code that uses one NaN 14809encoding would usually be incompatible with code that uses the other NaN 14810encoding, so MIPS ELF objects have a flag ('EF_MIPS_NAN2008') to record 14811which encoding is being used. 14812 14813 Assembly files can use the '.nan' directive to select between the two 14814encodings. '.nan 2008' says that the assembly file uses the IEEE 14815754-2008 encoding while '.nan legacy' says that the file uses the 14816original MIPS encoding. If several '.nan' directives are given, the 14817final setting is the one that is used. 14818 14819 The command-line options '-mnan=legacy' and '-mnan=2008' can be used 14820instead of '.nan legacy' and '.nan 2008' respectively. However, any 14821'.nan' directive overrides the command-line setting. 14822 14823 '.nan legacy' is the default if no '.nan' directive or '-mnan' option 14824is given. 14825 14826 Note that GNU 'as' does not produce NaNs itself and therefore these 14827directives do not affect code generation. They simply control the 14828setting of the 'EF_MIPS_NAN2008' flag. 14829 14830 Traditional MIPS assemblers do not support these directives. 14831 14832 14833File: as.info, Node: MIPS Option Stack, Next: MIPS ASE Instruction Generation Overrides, Prev: MIPS NaN Encodings, Up: MIPS-Dependent 14834 148359.27.11 Directives to save and restore options 14836---------------------------------------------- 14837 14838The directives '.set push' and '.set pop' may be used to save and 14839restore the current settings for all the options which are controlled by 14840'.set'. The '.set push' directive saves the current settings on a 14841stack. The '.set pop' directive pops the stack and restores the 14842settings. 14843 14844 These directives can be useful inside an macro which must change an 14845option such as the ISA level or instruction reordering but does not want 14846to change the state of the code which invoked the macro. 14847 14848 Traditional MIPS assemblers do not support these directives. 14849 14850 14851File: as.info, Node: MIPS ASE Instruction Generation Overrides, Next: MIPS Floating-Point, Prev: MIPS Option Stack, Up: MIPS-Dependent 14852 148539.27.12 Directives to control generation of MIPS ASE instructions 14854----------------------------------------------------------------- 14855 14856The directive '.set mips3d' makes the assembler accept instructions from 14857the MIPS-3D Application Specific Extension from that point on in the 14858assembly. The '.set nomips3d' directive prevents MIPS-3D instructions 14859from being accepted. 14860 14861 The directive '.set smartmips' makes the assembler accept 14862instructions from the SmartMIPS Application Specific Extension to the 14863MIPS32 ISA from that point on in the assembly. The '.set nosmartmips' 14864directive prevents SmartMIPS instructions from being accepted. 14865 14866 The directive '.set mdmx' makes the assembler accept instructions 14867from the MDMX Application Specific Extension from that point on in the 14868assembly. The '.set nomdmx' directive prevents MDMX instructions from 14869being accepted. 14870 14871 The directive '.set dsp' makes the assembler accept instructions from 14872the DSP Release 1 Application Specific Extension from that point on in 14873the assembly. The '.set nodsp' directive prevents DSP Release 1 14874instructions from being accepted. 14875 14876 The directive '.set dspr2' makes the assembler accept instructions 14877from the DSP Release 2 Application Specific Extension from that point on 14878in the assembly. This directive implies '.set dsp'. The '.set nodspr2' 14879directive prevents DSP Release 2 instructions from being accepted. 14880 14881 The directive '.set dspr3' makes the assembler accept instructions 14882from the DSP Release 3 Application Specific Extension from that point on 14883in the assembly. This directive implies '.set dsp' and '.set dspr2'. 14884The '.set nodspr3' directive prevents DSP Release 3 instructions from 14885being accepted. 14886 14887 The directive '.set mt' makes the assembler accept instructions from 14888the MT Application Specific Extension from that point on in the 14889assembly. The '.set nomt' directive prevents MT instructions from being 14890accepted. 14891 14892 The directive '.set mcu' makes the assembler accept instructions from 14893the MCU Application Specific Extension from that point on in the 14894assembly. The '.set nomcu' directive prevents MCU instructions from 14895being accepted. 14896 14897 The directive '.set msa' makes the assembler accept instructions from 14898the MIPS SIMD Architecture Extension from that point on in the assembly. 14899The '.set nomsa' directive prevents MSA instructions from being 14900accepted. 14901 14902 The directive '.set virt' makes the assembler accept instructions 14903from the Virtualization Application Specific Extension from that point 14904on in the assembly. The '.set novirt' directive prevents Virtualization 14905instructions from being accepted. 14906 14907 The directive '.set xpa' makes the assembler accept instructions from 14908the XPA Extension from that point on in the assembly. The '.set noxpa' 14909directive prevents XPA instructions from being accepted. 14910 14911 Traditional MIPS assemblers do not support these directives. 14912 14913 14914File: as.info, Node: MIPS Floating-Point, Next: MIPS Syntax, Prev: MIPS ASE Instruction Generation Overrides, Up: MIPS-Dependent 14915 149169.27.13 Directives to override floating-point options 14917----------------------------------------------------- 14918 14919The directives '.set softfloat' and '.set hardfloat' provide finer 14920control of disabling and enabling float-point instructions. These 14921directives always override the default (that hard-float instructions are 14922accepted) or the command-line options ('-msoft-float' and 14923'-mhard-float'). 14924 14925 The directives '.set singlefloat' and '.set doublefloat' provide 14926finer control of disabling and enabling double-precision float-point 14927operations. These directives always override the default (that 14928double-precision operations are accepted) or the command-line options 14929('-msingle-float' and '-mdouble-float'). 14930 14931 Traditional MIPS assemblers do not support these directives. 14932 14933 14934File: as.info, Node: MIPS Syntax, Prev: MIPS Floating-Point, Up: MIPS-Dependent 14935 149369.27.14 Syntactical considerations for the MIPS assembler 14937--------------------------------------------------------- 14938 14939* Menu: 14940 14941* MIPS-Chars:: Special Characters 14942 14943 14944File: as.info, Node: MIPS-Chars, Up: MIPS Syntax 14945 149469.27.14.1 Special Characters 14947............................ 14948 14949The presence of a '#' on a line indicates the start of a comment that 14950extends to the end of the current line. 14951 14952 If a '#' appears as the first character of a line, the whole line is 14953treated as a comment, but in this case the line can also be a logical 14954line number directive (*note Comments::) or a preprocessor control 14955command (*note Preprocessing::). 14956 14957 The ';' character can be used to separate statements on the same 14958line. 14959 14960 14961File: as.info, Node: MMIX-Dependent, Next: MSP430-Dependent, Prev: MIPS-Dependent, Up: Machine Dependencies 14962 149639.28 MMIX Dependent Features 14964============================ 14965 14966* Menu: 14967 14968* MMIX-Opts:: Command-line Options 14969* MMIX-Expand:: Instruction expansion 14970* MMIX-Syntax:: Syntax 14971* MMIX-mmixal:: Differences to 'mmixal' syntax and semantics 14972 14973 14974File: as.info, Node: MMIX-Opts, Next: MMIX-Expand, Up: MMIX-Dependent 14975 149769.28.1 Command-line Options 14977--------------------------- 14978 14979The MMIX version of 'as' has some machine-dependent options. 14980 14981 When '--fixed-special-register-names' is specified, only the register 14982names specified in *note MMIX-Regs:: are recognized in the instructions 14983'PUT' and 'GET'. 14984 14985 You can use the '--globalize-symbols' to make all symbols global. 14986This option is useful when splitting up a 'mmixal' program into several 14987files. 14988 14989 The '--gnu-syntax' turns off most syntax compatibility with 'mmixal'. 14990Its usability is currently doubtful. 14991 14992 The '--relax' option is not fully supported, but will eventually make 14993the object file prepared for linker relaxation. 14994 14995 If you want to avoid inadvertently calling a predefined symbol and 14996would rather get an error, for example when using 'as' with a compiler 14997or other machine-generated code, specify '--no-predefined-syms'. This 14998turns off built-in predefined definitions of all such symbols, including 14999rounding-mode symbols, segment symbols, 'BIT' symbols, and 'TRAP' 15000symbols used in 'mmix' "system calls". It also turns off predefined 15001special-register names, except when used in 'PUT' and 'GET' 15002instructions. 15003 15004 By default, some instructions are expanded to fit the size of the 15005operand or an external symbol (*note MMIX-Expand::). By passing 15006'--no-expand', no such expansion will be done, instead causing errors at 15007link time if the operand does not fit. 15008 15009 The 'mmixal' documentation (*note mmixsite::) specifies that global 15010registers allocated with the 'GREG' directive (*note MMIX-greg::) and 15011initialized to the same non-zero value, will refer to the same global 15012register. This isn't strictly enforceable in 'as' since the final 15013addresses aren't known until link-time, but it will do an effort unless 15014the '--no-merge-gregs' option is specified. (Register merging isn't yet 15015implemented in 'ld'.) 15016 15017 'as' will warn every time it expands an instruction to fit an operand 15018unless the option '-x' is specified. It is believed that this behaviour 15019is more useful than just mimicking 'mmixal''s behaviour, in which 15020instructions are only expanded if the '-x' option is specified, and 15021assembly fails otherwise, when an instruction needs to be expanded. It 15022needs to be kept in mind that 'mmixal' is both an assembler and linker, 15023while 'as' will expand instructions that at link stage can be 15024contracted. (Though linker relaxation isn't yet implemented in 'ld'.) 15025The option '-x' also imples '--linker-allocated-gregs'. 15026 15027 If instruction expansion is enabled, 'as' can expand a 'PUSHJ' 15028instruction into a series of instructions. The shortest expansion is to 15029not expand it, but just mark the call as redirectable to a stub, which 15030'ld' creates at link-time, but only if the original 'PUSHJ' instruction 15031is found not to reach the target. The stub consists of the necessary 15032instructions to form a jump to the target. This happens if 'as' can 15033assert that the 'PUSHJ' instruction can reach such a stub. The option 15034'--no-pushj-stubs' disables this shorter expansion, and the longer 15035series of instructions is then created at assembly-time. The option 15036'--no-stubs' is a synonym, intended for compatibility with future 15037releases, where generation of stubs for other instructions may be 15038implemented. 15039 15040 Usually a two-operand-expression (*note GREG-base::) without a 15041matching 'GREG' directive is treated as an error by 'as'. When the 15042option '--linker-allocated-gregs' is in effect, they are instead passed 15043through to the linker, which will allocate as many global registers as 15044is needed. 15045 15046 15047File: as.info, Node: MMIX-Expand, Next: MMIX-Syntax, Prev: MMIX-Opts, Up: MMIX-Dependent 15048 150499.28.2 Instruction expansion 15050---------------------------- 15051 15052When 'as' encounters an instruction with an operand that is either not 15053known or does not fit the operand size of the instruction, 'as' (and 15054'ld') will expand the instruction into a sequence of instructions 15055semantically equivalent to the operand fitting the instruction. 15056Expansion will take place for the following instructions: 15057 15058'GETA' 15059 Expands to a sequence of four instructions: 'SETL', 'INCML', 15060 'INCMH' and 'INCH'. The operand must be a multiple of four. 15061Conditional branches 15062 A branch instruction is turned into a branch with the complemented 15063 condition and prediction bit over five instructions; four 15064 instructions setting '$255' to the operand value, which like with 15065 'GETA' must be a multiple of four, and a final 'GO $255,$255,0'. 15066'PUSHJ' 15067 Similar to expansion for conditional branches; four instructions 15068 set '$255' to the operand value, followed by a 'PUSHGO 15069 $255,$255,0'. 15070'JMP' 15071 Similar to conditional branches and 'PUSHJ'. The final instruction 15072 is 'GO $255,$255,0'. 15073 15074 The linker 'ld' is expected to shrink these expansions for code 15075assembled with '--relax' (though not currently implemented). 15076 15077 15078File: as.info, Node: MMIX-Syntax, Next: MMIX-mmixal, Prev: MMIX-Expand, Up: MMIX-Dependent 15079 150809.28.3 Syntax 15081------------- 15082 15083The assembly syntax is supposed to be upward compatible with that 15084described in Sections 1.3 and 1.4 of 'The Art of Computer Programming, 15085Volume 1'. Draft versions of those chapters as well as other MMIX 15086information is located at 15087<http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html>. Most code 15088examples from the mmixal package located there should work unmodified 15089when assembled and linked as single files, with a few noteworthy 15090exceptions (*note MMIX-mmixal::). 15091 15092 Before an instruction is emitted, the current location is aligned to 15093the next four-byte boundary. If a label is defined at the beginning of 15094the line, its value will be the aligned value. 15095 15096 In addition to the traditional hex-prefix '0x', a hexadecimal number 15097can also be specified by the prefix character '#'. 15098 15099 After all operands to an MMIX instruction or directive have been 15100specified, the rest of the line is ignored, treated as a comment. 15101 15102* Menu: 15103 15104* MMIX-Chars:: Special Characters 15105* MMIX-Symbols:: Symbols 15106* MMIX-Regs:: Register Names 15107* MMIX-Pseudos:: Assembler Directives 15108 15109 15110File: as.info, Node: MMIX-Chars, Next: MMIX-Symbols, Up: MMIX-Syntax 15111 151129.28.3.1 Special Characters 15113........................... 15114 15115The characters '*' and '#' are line comment characters; each start a 15116comment at the beginning of a line, but only at the beginning of a line. 15117A '#' prefixes a hexadecimal number if found elsewhere on a line. If a 15118'#' appears at the start of a line the whole line is treated as a 15119comment, but the line can also act as a logical line number directive 15120(*note Comments::) or a preprocessor control command (*note 15121Preprocessing::). 15122 15123 Two other characters, '%' and '!', each start a comment anywhere on 15124the line. Thus you can't use the 'modulus' and 'not' operators in 15125expressions normally associated with these two characters. 15126 15127 A ';' is a line separator, treated as a new-line, so separate 15128instructions can be specified on a single line. 15129 15130 15131File: as.info, Node: MMIX-Symbols, Next: MMIX-Regs, Prev: MMIX-Chars, Up: MMIX-Syntax 15132 151339.28.3.2 Symbols 15134................ 15135 15136The character ':' is permitted in identifiers. There are two exceptions 15137to it being treated as any other symbol character: if a symbol begins 15138with ':', it means that the symbol is in the global namespace and that 15139the current prefix should not be prepended to that symbol (*note 15140MMIX-prefix::). The ':' is then not considered part of the symbol. For 15141a symbol in the label position (first on a line), a ':' at the end of a 15142symbol is silently stripped off. A label is permitted, but not 15143required, to be followed by a ':', as with many other assembly formats. 15144 15145 The character '@' in an expression, is a synonym for '.', the current 15146location. 15147 15148 In addition to the common forward and backward local symbol formats 15149(*note Symbol Names::), they can be specified with upper-case 'B' and 15150'F', as in '8B' and '9F'. A local label defined for the current 15151position is written with a 'H' appended to the number: 15152 3H LDB $0,$1,2 15153 This and traditional local-label formats cannot be mixed: a label 15154must be defined and referred to using the same format. 15155 15156 There's a minor caveat: just as for the ordinary local symbols, the 15157local symbols are translated into ordinary symbols using control 15158characters are to hide the ordinal number of the symbol. Unfortunately, 15159these symbols are not translated back in error messages. Thus you may 15160see confusing error messages when local symbols are used. Control 15161characters '\003' (control-C) and '\004' (control-D) are used for the 15162MMIX-specific local-symbol syntax. 15163 15164 The symbol 'Main' is handled specially; it is always global. 15165 15166 By defining the symbols '__.MMIX.start..text' and 15167'__.MMIX.start..data', the address of respectively the '.text' and 15168'.data' segments of the final program can be defined, though when 15169linking more than one object file, the code or data in the object file 15170containing the symbol is not guaranteed to be start at that position; 15171just the final executable. *Note MMIX-loc::. 15172 15173 15174File: as.info, Node: MMIX-Regs, Next: MMIX-Pseudos, Prev: MMIX-Symbols, Up: MMIX-Syntax 15175 151769.28.3.3 Register names 15177....................... 15178 15179Local and global registers are specified as '$0' to '$255'. The 15180recognized special register names are 'rJ', 'rA', 'rB', 'rC', 'rD', 15181'rE', 'rF', 'rG', 'rH', 'rI', 'rK', 'rL', 'rM', 'rN', 'rO', 'rP', 'rQ', 15182'rR', 'rS', 'rT', 'rU', 'rV', 'rW', 'rX', 'rY', 'rZ', 'rBB', 'rTT', 15183'rWW', 'rXX', 'rYY' and 'rZZ'. A leading ':' is optional for special 15184register names. 15185 15186 Local and global symbols can be equated to register names and used in 15187place of ordinary registers. 15188 15189 Similarly for special registers, local and global symbols can be 15190used. Also, symbols equated from numbers and constant expressions are 15191allowed in place of a special register, except when either of the 15192options '--no-predefined-syms' and '--fixed-special-register-names' are 15193specified. Then only the special register names above are allowed for 15194the instructions having a special register operand; 'GET' and 'PUT'. 15195 15196 15197File: as.info, Node: MMIX-Pseudos, Prev: MMIX-Regs, Up: MMIX-Syntax 15198 151999.28.3.4 Assembler Directives 15200............................. 15201 15202'LOC' 15203 15204 The 'LOC' directive sets the current location to the value of the 15205 operand field, which may include changing sections. If the operand 15206 is a constant, the section is set to either '.data' if the value is 15207 '0x2000000000000000' or larger, else it is set to '.text'. Within 15208 a section, the current location may only be changed to 15209 monotonically higher addresses. A LOC expression must be a 15210 previously defined symbol or a "pure" constant. 15211 15212 An example, which sets the label PREV to the current location, and 15213 updates the current location to eight bytes forward: 15214 prev LOC @+8 15215 15216 When a LOC has a constant as its operand, a symbol 15217 '__.MMIX.start..text' or '__.MMIX.start..data' is defined depending 15218 on the address as mentioned above. Each such symbol is interpreted 15219 as special by the linker, locating the section at that address. 15220 Note that if multiple files are linked, the first object file with 15221 that section will be mapped to that address (not necessarily the 15222 file with the LOC definition). 15223 15224'LOCAL' 15225 15226 Example: 15227 LOCAL external_symbol 15228 LOCAL 42 15229 .local asymbol 15230 15231 This directive-operation generates a link-time assertion that the 15232 operand does not correspond to a global register. The operand is 15233 an expression that at link-time resolves to a register symbol or a 15234 number. A number is treated as the register having that number. 15235 There is one restriction on the use of this directive: the 15236 pseudo-directive must be placed in a section with contents, code or 15237 data. 15238 15239'IS' 15240 15241 The 'IS' directive: 15242 asymbol IS an_expression 15243 sets the symbol 'asymbol' to 'an_expression'. A symbol may not be 15244 set more than once using this directive. Local labels may be set 15245 using this directive, for example: 15246 5H IS @+4 15247 15248'GREG' 15249 15250 This directive reserves a global register, gives it an initial 15251 value and optionally gives it a symbolic name. Some examples: 15252 15253 areg GREG 15254 breg GREG data_value 15255 GREG data_buffer 15256 .greg creg, another_data_value 15257 15258 The symbolic register name can be used in place of a (non-special) 15259 register. If a value isn't provided, it defaults to zero. Unless 15260 the option '--no-merge-gregs' is specified, non-zero registers 15261 allocated with this directive may be eliminated by 'as'; another 15262 register with the same value used in its place. Any of the 15263 instructions 'CSWAP', 'GO', 'LDA', 'LDBU', 'LDB', 'LDHT', 'LDOU', 15264 'LDO', 'LDSF', 'LDTU', 'LDT', 'LDUNC', 'LDVTS', 'LDWU', 'LDW', 15265 'PREGO', 'PRELD', 'PREST', 'PUSHGO', 'STBU', 'STB', 'STCO', 'STHT', 15266 'STOU', 'STSF', 'STTU', 'STT', 'STUNC', 'SYNCD', 'SYNCID', can have 15267 a value nearby an initial value in place of its second and third 15268 operands. Here, "nearby" is defined as within the range 0...255 15269 from the initial value of such an allocated register. 15270 15271 buffer1 BYTE 0,0,0,0,0 15272 buffer2 BYTE 0,0,0,0,0 15273 ... 15274 GREG buffer1 15275 LDOU $42,buffer2 15276 In the example above, the 'Y' field of the 'LDOUI' instruction 15277 (LDOU with a constant Z) will be replaced with the global register 15278 allocated for 'buffer1', and the 'Z' field will have the value 5, 15279 the offset from 'buffer1' to 'buffer2'. The result is equivalent 15280 to this code: 15281 buffer1 BYTE 0,0,0,0,0 15282 buffer2 BYTE 0,0,0,0,0 15283 ... 15284 tmpreg GREG buffer1 15285 LDOU $42,tmpreg,(buffer2-buffer1) 15286 15287 Global registers allocated with this directive are allocated in 15288 order higher-to-lower within a file. Other than that, the exact 15289 order of register allocation and elimination is undefined. For 15290 example, the order is undefined when more than one file with such 15291 directives are linked together. With the options '-x' and 15292 '--linker-allocated-gregs', 'GREG' directives for two-operand cases 15293 like the one mentioned above can be omitted. Sufficient global 15294 registers will then be allocated by the linker. 15295 15296'BYTE' 15297 15298 The 'BYTE' directive takes a series of operands separated by a 15299 comma. If an operand is a string (*note Strings::), each character 15300 of that string is emitted as a byte. Other operands must be 15301 constant expressions without forward references, in the range 15302 0...255. If you need operands having expressions with forward 15303 references, use '.byte' (*note Byte::). An operand can be omitted, 15304 defaulting to a zero value. 15305 15306'WYDE' 15307'TETRA' 15308'OCTA' 15309 15310 The directives 'WYDE', 'TETRA' and 'OCTA' emit constants of two, 15311 four and eight bytes size respectively. Before anything else 15312 happens for the directive, the current location is aligned to the 15313 respective constant-size boundary. If a label is defined at the 15314 beginning of the line, its value will be that after the alignment. 15315 A single operand can be omitted, defaulting to a zero value emitted 15316 for the directive. Operands can be expressed as strings (*note 15317 Strings::), in which case each character in the string is emitted 15318 as a separate constant of the size indicated by the directive. 15319 15320'PREFIX' 15321 15322 The 'PREFIX' directive sets a symbol name prefix to be prepended to 15323 all symbols (except local symbols, *note MMIX-Symbols::), that are 15324 not prefixed with ':', until the next 'PREFIX' directive. Such 15325 prefixes accumulate. For example, 15326 PREFIX a 15327 PREFIX b 15328 c IS 0 15329 defines a symbol 'abc' with the value 0. 15330 15331'BSPEC' 15332'ESPEC' 15333 15334 A pair of 'BSPEC' and 'ESPEC' directives delimit a section of 15335 special contents (without specified semantics). Example: 15336 BSPEC 42 15337 TETRA 1,2,3 15338 ESPEC 15339 The single operand to 'BSPEC' must be number in the range 0...255. 15340 The 'BSPEC' number 80 is used by the GNU binutils implementation. 15341 15342 15343File: as.info, Node: MMIX-mmixal, Prev: MMIX-Syntax, Up: MMIX-Dependent 15344 153459.28.4 Differences to 'mmixal' 15346------------------------------ 15347 15348The binutils 'as' and 'ld' combination has a few differences in function 15349compared to 'mmixal' (*note mmixsite::). 15350 15351 The replacement of a symbol with a GREG-allocated register (*note 15352GREG-base::) is not handled the exactly same way in 'as' as in 'mmixal'. 15353This is apparent in the 'mmixal' example file 'inout.mms', where 15354different registers with different offsets, eventually yielding the same 15355address, are used in the first instruction. This type of difference 15356should however not affect the function of any program unless it has 15357specific assumptions about the allocated register number. 15358 15359 Line numbers (in the 'mmo' object format) are currently not 15360supported. 15361 15362 Expression operator precedence is not that of mmixal: operator 15363precedence is that of the C programming language. It's recommended to 15364use parentheses to explicitly specify wanted operator precedence 15365whenever more than one type of operators are used. 15366 15367 The serialize unary operator '&', the fractional division operator 15368'//', the logical not operator '!' and the modulus operator '%' are not 15369available. 15370 15371 Symbols are not global by default, unless the option 15372'--globalize-symbols' is passed. Use the '.global' directive to 15373globalize symbols (*note Global::). 15374 15375 Operand syntax is a bit stricter with 'as' than 'mmixal'. For 15376example, you can't say 'addu 1,2,3', instead you must write 'addu 15377$1,$2,3'. 15378 15379 You can't LOC to a lower address than those already visited (i.e., 15380"backwards"). 15381 15382 A LOC directive must come before any emitted code. 15383 15384 Predefined symbols are visible as file-local symbols after use. (In 15385the ELF file, that is--the linked mmo file has no notion of a file-local 15386symbol.) 15387 15388 Some mapping of constant expressions to sections in LOC expressions 15389is attempted, but that functionality is easily confused and should be 15390avoided unless compatibility with 'mmixal' is required. A LOC 15391expression to '0x2000000000000000' or higher, maps to the '.data' 15392section and lower addresses map to the '.text' section (*note 15393MMIX-loc::). 15394 15395 The code and data areas are each contiguous. Sparse programs with 15396far-away LOC directives will take up the same amount of space as a 15397contiguous program with zeros filled in the gaps between the LOC 15398directives. If you need sparse programs, you might try and get the 15399wanted effect with a linker script and splitting up the code parts into 15400sections (*note Section::). Assembly code for this, to be compatible 15401with 'mmixal', would look something like: 15402 .if 0 15403 LOC away_expression 15404 .else 15405 .section away,"ax" 15406 .fi 15407 'as' will not execute the LOC directive and 'mmixal' ignores the 15408lines with '.'. This construct can be used generally to help 15409compatibility. 15410 15411 Symbols can't be defined twice-not even to the same value. 15412 15413 Instruction mnemonics are recognized case-insensitive, though the 15414'IS' and 'GREG' pseudo-operations must be specified in upper-case 15415characters. 15416 15417 There's no unicode support. 15418 15419 The following is a list of programs in 'mmix.tar.gz', available at 15420<http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html>, last checked 15421with the version dated 2001-08-25 (md5sum 15422c393470cfc86fac040487d22d2bf0172) that assemble with 'mmixal' but do not 15423assemble with 'as': 15424 15425'silly.mms' 15426 LOC to a previous address. 15427'sim.mms' 15428 Redefines symbol 'Done'. 15429'test.mms' 15430 Uses the serial operator '&'. 15431 15432 15433File: as.info, Node: MSP430-Dependent, Next: NDS32-Dependent, Prev: MMIX-Dependent, Up: Machine Dependencies 15434 154359.29 MSP 430 Dependent Features 15436=============================== 15437 15438* Menu: 15439 15440* MSP430 Options:: Options 15441* MSP430 Syntax:: Syntax 15442* MSP430 Floating Point:: Floating Point 15443* MSP430 Directives:: MSP 430 Machine Directives 15444* MSP430 Opcodes:: Opcodes 15445* MSP430 Profiling Capability:: Profiling Capability 15446 15447 15448File: as.info, Node: MSP430 Options, Next: MSP430 Syntax, Up: MSP430-Dependent 15449 154509.29.1 Options 15451-------------- 15452 15453'-mmcu' 15454 selects the mcu architecture. If the architecture is 430Xv2 then 15455 this also enables NOP generation unless the '-mN' is also 15456 specified. 15457 15458'-mcpu' 15459 selects the cpu architecture. If the architecture is 430Xv2 then 15460 this also enables NOP generation unless the '-mN' is also 15461 specified. 15462 15463'-msilicon-errata=NAME[,NAME...]' 15464 Implements a fixup for named silicon errata. Multiple silicon 15465 errata can be specified by multiple uses of the '-msilicon-errata' 15466 option and/or by including the errata names, separated by commas, 15467 on an individual '-msilicon-errata' option. Errata names currently 15468 recognised by the assembler are: 15469 15470 'cpu4' 15471 'PUSH #4' and 'PUSH #8' need longer encodings on the MSP430. 15472 This option is enabled by default, and cannot be disabled. 15473 'cpu8' 15474 Do not set the 'SP' to an odd value. 15475 'cpu11' 15476 Do not update the 'SR' and the 'PC' in the same instruction. 15477 'cpu12' 15478 Do not use the 'PC' in a 'CMP' or 'BIT' instruction. 15479 'cpu13' 15480 Do not use an arithmetic instruction to modify the 'SR'. 15481 'cpu19' 15482 Insert 'NOP' after 'CPUOFF'. 15483 15484'-msilicon-errata-warn=NAME[,NAME...]' 15485 Like the '-msilicon-errata' option except that instead of fixing 15486 the specified errata, a warning message is issued instead. This 15487 option can be used alongside '-msilicon-errata' to generate 15488 messages whenever a problem is fixed, or on its own in order to 15489 inspect code for potential problems. 15490 15491'-mP' 15492 enables polymorph instructions handler. 15493 15494'-mQ' 15495 enables relaxation at assembly time. DANGEROUS! 15496 15497'-ml' 15498 indicates that the input uses the large code model. 15499 15500'-mn' 15501 enables the generation of a NOP instruction following any 15502 instruction that might change the interrupts enabled/disabled 15503 state. The pipelined nature of the MSP430 core means that any 15504 instruction that changes the interrupt state ('EINT', 'DINT', 'BIC 15505 #8, SR', 'BIS #8, SR' or 'MOV.W <>, SR') must be followed by a NOP 15506 instruction in order to ensure the correct processing of 15507 interrupts. By default it is up to the programmer to supply these 15508 NOP instructions, but this command line option enables the 15509 automatic insertion by the assembler, if they are missing. 15510 15511'-mN' 15512 disables the generation of a NOP instruction following any 15513 instruction that might change the interrupts enabled/disabled 15514 state. This is the default behaviour. 15515 15516'-my' 15517 tells the assembler to generate a warning message if a NOP does not 15518 immediately forllow an instruction that enables or disables 15519 interrupts. This is the default. 15520 15521 Note that this option can be stacked with the '-mn' option so that 15522 the assembler will both warn about missing NOP instructions and 15523 then insert them automatically. 15524 15525'-mY' 15526 disables warnings about missing NOP instructions. 15527 15528'-md' 15529 mark the object file as one that requires data to copied from ROM 15530 to RAM at execution startup. Disabled by default. 15531 15532 15533File: as.info, Node: MSP430 Syntax, Next: MSP430 Floating Point, Prev: MSP430 Options, Up: MSP430-Dependent 15534 155359.29.2 Syntax 15536------------- 15537 15538* Menu: 15539 15540* MSP430-Macros:: Macros 15541* MSP430-Chars:: Special Characters 15542* MSP430-Regs:: Register Names 15543* MSP430-Ext:: Assembler Extensions 15544 15545 15546File: as.info, Node: MSP430-Macros, Next: MSP430-Chars, Up: MSP430 Syntax 15547 155489.29.2.1 Macros 15549............... 15550 15551The macro syntax used on the MSP 430 is like that described in the MSP 15552430 Family Assembler Specification. Normal 'as' macros should still 15553work. 15554 15555 Additional built-in macros are: 15556 15557'llo(exp)' 15558 Extracts least significant word from 32-bit expression 'exp'. 15559 15560'lhi(exp)' 15561 Extracts most significant word from 32-bit expression 'exp'. 15562 15563'hlo(exp)' 15564 Extracts 3rd word from 64-bit expression 'exp'. 15565 15566'hhi(exp)' 15567 Extracts 4rd word from 64-bit expression 'exp'. 15568 15569 They normally being used as an immediate source operand. 15570 mov #llo(1), r10 ; == mov #1, r10 15571 mov #lhi(1), r10 ; == mov #0, r10 15572 15573 15574File: as.info, Node: MSP430-Chars, Next: MSP430-Regs, Prev: MSP430-Macros, Up: MSP430 Syntax 15575 155769.29.2.2 Special Characters 15577........................... 15578 15579A semicolon (';') appearing anywhere on a line starts a comment that 15580extends to the end of that line. 15581 15582 If a '#' appears as the first character of a line then the whole line 15583is treated as a comment, but it can also be a logical line number 15584directive (*note Comments::) or a preprocessor control command (*note 15585Preprocessing::). 15586 15587 Multiple statements can appear on the same line provided that they 15588are separated by the '{' character. 15589 15590 The character '$' in jump instructions indicates current location and 15591implemented only for TI syntax compatibility. 15592 15593 15594File: as.info, Node: MSP430-Regs, Next: MSP430-Ext, Prev: MSP430-Chars, Up: MSP430 Syntax 15595 155969.29.2.3 Register Names 15597....................... 15598 15599General-purpose registers are represented by predefined symbols of the 15600form 'rN' (for global registers), where N represents a number between 15601'0' and '15'. The leading letters may be in either upper or lower case; 15602for example, 'r13' and 'R7' are both valid register names. 15603 15604 Register names 'PC', 'SP' and 'SR' cannot be used as register names 15605and will be treated as variables. Use 'r0', 'r1', and 'r2' instead. 15606 15607 15608File: as.info, Node: MSP430-Ext, Prev: MSP430-Regs, Up: MSP430 Syntax 15609 156109.29.2.4 Assembler Extensions 15611............................. 15612 15613'@rN' 15614 As destination operand being treated as '0(rn)' 15615 15616'0(rN)' 15617 As source operand being treated as '@rn' 15618 15619'jCOND +N' 15620 Skips next N bytes followed by jump instruction and equivalent to 15621 'jCOND $+N+2' 15622 15623 Also, there are some instructions, which cannot be found in other 15624assemblers. These are branch instructions, which has different opcodes 15625upon jump distance. They all got PC relative addressing mode. 15626 15627'beq label' 15628 A polymorph instruction which is 'jeq label' in case if jump 15629 distance within allowed range for cpu's jump instruction. If not, 15630 this unrolls into a sequence of 15631 jne $+6 15632 br label 15633 15634'bne label' 15635 A polymorph instruction which is 'jne label' or 'jeq +4; br label' 15636 15637'blt label' 15638 A polymorph instruction which is 'jl label' or 'jge +4; br label' 15639 15640'bltn label' 15641 A polymorph instruction which is 'jn label' or 'jn +2; jmp +4; br 15642 label' 15643 15644'bltu label' 15645 A polymorph instruction which is 'jlo label' or 'jhs +2; br label' 15646 15647'bge label' 15648 A polymorph instruction which is 'jge label' or 'jl +4; br label' 15649 15650'bgeu label' 15651 A polymorph instruction which is 'jhs label' or 'jlo +4; br label' 15652 15653'bgt label' 15654 A polymorph instruction which is 'jeq +2; jge label' or 'jeq +6; jl 15655 +4; br label' 15656 15657'bgtu label' 15658 A polymorph instruction which is 'jeq +2; jhs label' or 'jeq +6; 15659 jlo +4; br label' 15660 15661'bleu label' 15662 A polymorph instruction which is 'jeq label; jlo label' or 'jeq +2; 15663 jhs +4; br label' 15664 15665'ble label' 15666 A polymorph instruction which is 'jeq label; jl label' or 'jeq +2; 15667 jge +4; br label' 15668 15669'jump label' 15670 A polymorph instruction which is 'jmp label' or 'br label' 15671 15672 15673File: as.info, Node: MSP430 Floating Point, Next: MSP430 Directives, Prev: MSP430 Syntax, Up: MSP430-Dependent 15674 156759.29.3 Floating Point 15676--------------------- 15677 15678The MSP 430 family uses IEEE 32-bit floating-point numbers. 15679 15680 15681File: as.info, Node: MSP430 Directives, Next: MSP430 Opcodes, Prev: MSP430 Floating Point, Up: MSP430-Dependent 15682 156839.29.4 MSP 430 Machine Directives 15684--------------------------------- 15685 15686'.file' 15687 This directive is ignored; it is accepted for compatibility with 15688 other MSP 430 assemblers. 15689 15690 _Warning:_ in other versions of the GNU assembler, '.file' is 15691 used for the directive called '.app-file' in the MSP 430 15692 support. 15693 15694'.line' 15695 This directive is ignored; it is accepted for compatibility with 15696 other MSP 430 assemblers. 15697 15698'.arch' 15699 Sets the target microcontroller in the same way as the '-mmcu' 15700 command line option. 15701 15702'.cpu' 15703 Sets the target architecture in the same way as the '-mcpu' command 15704 line option. 15705 15706'.profiler' 15707 This directive instructs assembler to add new profile entry to the 15708 object file. 15709 15710'.refsym' 15711 This directive instructs assembler to add an undefined reference to 15712 the symbol following the directive. The maximum symbol name length 15713 is 1023 characters. No relocation is created for this symbol; it 15714 will exist purely for pulling in object files from archives. Note 15715 that this reloc is not sufficient to prevent garbage collection; 15716 use a KEEP() directive in the linker file to preserve such objects. 15717 15718 15719File: as.info, Node: MSP430 Opcodes, Next: MSP430 Profiling Capability, Prev: MSP430 Directives, Up: MSP430-Dependent 15720 157219.29.5 Opcodes 15722-------------- 15723 15724'as' implements all the standard MSP 430 opcodes. No additional 15725pseudo-instructions are needed on this family. 15726 15727 For information on the 430 machine instruction set, see 'MSP430 15728User's Manual, document slau049d', Texas Instrument, Inc. 15729 15730 15731File: as.info, Node: MSP430 Profiling Capability, Prev: MSP430 Opcodes, Up: MSP430-Dependent 15732 157339.29.6 Profiling Capability 15734--------------------------- 15735 15736It is a performance hit to use gcc's profiling approach for this tiny 15737target. Even more - jtag hardware facility does not perform any 15738profiling functions. However we've got gdb's built-in simulator where 15739we can do anything. 15740 15741 We define new section '.profiler' which holds all profiling 15742information. We define new pseudo operation '.profiler' which will 15743instruct assembler to add new profile entry to the object file. Profile 15744should take place at the present address. 15745 15746 Pseudo operation format: 15747 15748 '.profiler flags,function_to_profile [, cycle_corrector, extra]' 15749 15750 where: 15751 15752 'flags' is a combination of the following characters: 15753 15754 's' 15755 function entry 15756 'x' 15757 function exit 15758 'i' 15759 function is in init section 15760 'f' 15761 function is in fini section 15762 'l' 15763 library call 15764 'c' 15765 libc standard call 15766 'd' 15767 stack value demand 15768 'I' 15769 interrupt service routine 15770 'P' 15771 prologue start 15772 'p' 15773 prologue end 15774 'E' 15775 epilogue start 15776 'e' 15777 epilogue end 15778 'j' 15779 long jump / sjlj unwind 15780 'a' 15781 an arbitrary code fragment 15782 't' 15783 extra parameter saved (a constant value like frame size) 15784 15785'function_to_profile' 15786 a function address 15787'cycle_corrector' 15788 a value which should be added to the cycle counter, zero if 15789 omitted. 15790'extra' 15791 any extra parameter, zero if omitted. 15792 15793 For example: 15794 .global fxx 15795 .type fxx,@function 15796 fxx: 15797 .LFrameOffset_fxx=0x08 15798 .profiler "scdP", fxx ; function entry. 15799 ; we also demand stack value to be saved 15800 push r11 15801 push r10 15802 push r9 15803 push r8 15804 .profiler "cdpt",fxx,0, .LFrameOffset_fxx ; check stack value at this point 15805 ; (this is a prologue end) 15806 ; note, that spare var filled with 15807 ; the farme size 15808 mov r15,r8 15809 ... 15810 .profiler cdE,fxx ; check stack 15811 pop r8 15812 pop r9 15813 pop r10 15814 pop r11 15815 .profiler xcde,fxx,3 ; exit adds 3 to the cycle counter 15816 ret ; cause 'ret' insn takes 3 cycles 15817 15818 15819File: as.info, Node: NDS32-Dependent, Next: NiosII-Dependent, Prev: MSP430-Dependent, Up: Machine Dependencies 15820 158219.30 NDS32 Dependent Features 15822============================= 15823 15824The NDS32 processors family includes high-performance and low-power 1582532-bit processors for high-end to low-end. GNU 'as' for NDS32 15826architectures supports NDS32 ISA version 3. For detail about NDS32 15827instruction set, please see the AndeStar ISA User Manual which is 15828availible at http://www.andestech.com/en/index/index.htm 15829 15830* Menu: 15831 15832* NDS32 Options:: Assembler options 15833* NDS32 Syntax:: High-level assembly macros 15834 15835 15836File: as.info, Node: NDS32 Options, Next: NDS32 Syntax, Up: NDS32-Dependent 15837 158389.30.1 NDS32 Options 15839-------------------- 15840 15841The NDS32 configurations of GNU 'as' support these special options: 15842 15843'-O1' 15844 Optimize for performance. 15845 15846'-Os' 15847 Optimize for space. 15848 15849'-EL' 15850 Produce little endian data output. 15851 15852'-EB' 15853 Produce little endian data output. 15854 15855'-mpic' 15856 Generate PIC. 15857 15858'-mno-fp-as-gp-relax' 15859 Suppress fp-as-gp relaxation for this file. 15860 15861'-mb2bb-relax' 15862 Back-to-back branch optimization. 15863 15864'-mno-all-relax' 15865 Suppress all relaxation for this file. 15866 15867'-march=<arch name>' 15868 Assemble for architecture <arch name> which could be v3, v3j, v3m, 15869 v3f, v3s, v2, v2j, v2f, v2s. 15870 15871'-mbaseline=<baseline>' 15872 Assemble for baseline <baseline> which could be v2, v3, v3m. 15873 15874'-mfpu-freg=FREG' 15875 Specify a FPU configuration. 15876 '0 8 SP / 4 DP registers' 15877 '1 16 SP / 8 DP registers' 15878 '2 32 SP / 16 DP registers' 15879 '3 32 SP / 32 DP registers' 15880 15881'-mabi=ABI' 15882 Specify a abi version <abi> could be v1, v2, v2fp, v2fpp. 15883 15884'-m[no-]mac' 15885 Enable/Disable Multiply instructions support. 15886 15887'-m[no-]div' 15888 Enable/Disable Divide instructions support. 15889 15890'-m[no-]16bit-ext' 15891 Enable/Disable 16-bit extension 15892 15893'-m[no-]dx-regs' 15894 Enable/Disable d0/d1 registers 15895 15896'-m[no-]perf-ext' 15897 Enable/Disable Performance extension 15898 15899'-m[no-]perf2-ext' 15900 Enable/Disable Performance extension 2 15901 15902'-m[no-]string-ext' 15903 Enable/Disable String extension 15904 15905'-m[no-]reduced-regs' 15906 Enable/Disable Reduced Register configuration (GPR16) option 15907 15908'-m[no-]audio-isa-ext' 15909 Enable/Disable AUDIO ISA extension 15910 15911'-m[no-]fpu-sp-ext' 15912 Enable/Disable FPU SP extension 15913 15914'-m[no-]fpu-dp-ext' 15915 Enable/Disable FPU DP extension 15916 15917'-m[no-]fpu-fma' 15918 Enable/Disable FPU fused-multiply-add instructions 15919 15920'-mall-ext' 15921 Turn on all extensions and instructions support 15922 15923 15924File: as.info, Node: NDS32 Syntax, Prev: NDS32 Options, Up: NDS32-Dependent 15925 159269.30.2 Syntax 15927------------- 15928 15929* Menu: 15930 15931* NDS32-Chars:: Special Characters 15932* NDS32-Regs:: Register Names 15933* NDS32-Ops:: Pseudo Instructions 15934 15935 15936File: as.info, Node: NDS32-Chars, Next: NDS32-Regs, Up: NDS32 Syntax 15937 159389.30.2.1 Special Characters 15939........................... 15940 15941Use '#' at column 1 and '!' anywhere in the line except inside quotes. 15942 15943 Multiple instructions in a line are allowed though not recommended 15944and should be separated by ';'. 15945 15946 Assembler is not case-sensitive in general except user defined label. 15947For example, 'jral F1' is different from 'jral f1' while it is the same 15948as 'JRAL F1'. 15949 15950 15951File: as.info, Node: NDS32-Regs, Next: NDS32-Ops, Prev: NDS32-Chars, Up: NDS32 Syntax 15952 159539.30.2.2 Register Names 15954....................... 15955 15956'General purpose registers (GPR)' 15957 There are 32 32-bit general purpose registers $r0 to $r31. 15958 15959'Accumulators d0 and d1' 15960 64-bit accumulators: $d0.hi, $d0.lo, $d1.hi, and $d1.lo. 15961 15962'Assembler reserved register $ta' 15963 Register $ta ($r15) is reserved for assembler using. 15964 15965'Operating system reserved registers $p0 and $p1' 15966 Registers $p0 ($r26) and $p1 ($r27) are used by operating system as 15967 scratch registers. 15968 15969'Frame pointer $fp' 15970 Register $r28 is regarded as the frame pointer. 15971 15972'Global pointer' 15973 Register $r29 is regarded as the global pointer. 15974 15975'Link pointer' 15976 Register $r30 is regarded as the link pointer. 15977 15978'Stack pointer' 15979 Register $r31 is regarded as the stack pointer. 15980 15981 15982File: as.info, Node: NDS32-Ops, Prev: NDS32-Regs, Up: NDS32 Syntax 15983 159849.30.2.3 Pseudo Instructions 15985............................ 15986 15987'li rt5,imm32' 15988 load 32-bit integer into register rt5. 'sethi rt5,hi20(imm32)' and 15989 then 'ori rt5,reg,lo12(imm32)'. 15990 15991'la rt5,var' 15992 Load 32-bit address of var into register rt5. 'sethi 15993 rt5,hi20(var)' and then 'ori reg,rt5,lo12(var)' 15994 15995'l.[bhw] rt5,var' 15996 Load value of var into register rt5. 'sethi $ta,hi20(var)' and 15997 then 'l[bhw]i rt5,[$ta+lo12(var)]' 15998 15999'l.[bh]s rt5,var' 16000 Load value of var into register rt5. 'sethi $ta,hi20(var)' and 16001 then 'l[bh]si rt5,[$ta+lo12(var)]' 16002 16003'l.[bhw]p rt5,var,inc' 16004 Load value of var into register rt5 and increment $ta by amount 16005 inc. 'la $ta,var' and then 'l[bhw]i.bi rt5,[$ta],inc' 16006 16007'l.[bhw]pc rt5,inc' 16008 Continue loading value of var into register rt5 and increment $ta 16009 by amount inc. 'l[bhw]i.bi rt5,[$ta],inc.' 16010 16011'l.[bh]sp rt5,var,inc' 16012 Load value of var into register rt5 and increment $ta by amount 16013 inc. 'la $ta,var' and then 'l[bh]si.bi rt5,[$ta],inc' 16014 16015'l.[bh]spc rt5,inc' 16016 Continue loading value of var into register rt5 and increment $ta 16017 by amount inc. 'l[bh]si.bi rt5,[$ta],inc.' 16018 16019's.[bhw] rt5,var' 16020 Store register rt5 to var. 'sethi $ta,hi20(var)' and then 's[bhw]i 16021 rt5,[$ta+lo12(var)]' 16022 16023's.[bhw]p rt5,var,inc' 16024 Store register rt5 to var and increment $ta by amount inc. 'la 16025 $ta,var' and then 's[bhw]i.bi rt5,[$ta],inc' 16026 16027's.[bhw]pc rt5,inc' 16028 Continue storing register rt5 to var and increment $ta by amount 16029 inc. 's[bhw]i.bi rt5,[$ta],inc.' 16030 16031'not rt5,ra5' 16032 Alias of 'nor rt5,ra5,ra5'. 16033 16034'neg rt5,ra5' 16035 Alias of 'subri rt5,ra5,0'. 16036 16037'br rb5' 16038 Depending on how it is assembled, it is translated into 'r5 rb5' or 16039 'jr rb5'. 16040 16041'b label' 16042 Branch to label depending on how it is assembled, it is translated 16043 into 'j8 label', 'j label', or "'la $ta,label' 'br $ta'". 16044 16045'bral rb5' 16046 Alias of jral br5 depending on how it is assembled, it is 16047 translated into 'jral5 rb5' or 'jral rb5'. 16048 16049'bal fname' 16050 Alias of jal fname depending on how it is assembled, it is 16051 translated into 'jal fname' or "'la $ta,fname' 'bral $ta'". 16052 16053'call fname' 16054 Call function fname same as 'jal fname'. 16055 16056'move rt5,ra5' 16057 For 16-bit, this is 'mov55 rt5,ra5'. For no 16-bit, this is 'ori 16058 rt5,ra5,0'. 16059 16060'move rt5,var' 16061 This is the same as 'l.w rt5,var'. 16062 16063'move rt5,imm32' 16064 This is the same as 'li rt5,imm32'. 16065 16066'pushm ra5,rb5' 16067 Push contents of registers from ra5 to rb5 into stack. 16068 16069'push ra5' 16070 Push content of register ra5 into stack. (same 'pushm ra5,ra5'). 16071 16072'push.d var' 16073 Push value of double-word variable var into stack. 16074 16075'push.w var' 16076 Push value of word variable var into stack. 16077 16078'push.h var' 16079 Push value of half-word variable var into stack. 16080 16081'push.b var' 16082 Push value of byte variable var into stack. 16083 16084'pusha var' 16085 Push 32-bit address of variable var into stack. 16086 16087'pushi imm32' 16088 Push 32-bit immediate value into stack. 16089 16090'popm ra5,rb5' 16091 Pop top of stack values into registers ra5 to rb5. 16092 16093'pop rt5' 16094 Pop top of stack value into register. (same as 'popm rt5,rt5'.) 16095 16096'pop.d var,ra5' 16097 Pop value of double-word variable var from stack using register ra5 16098 as 2nd scratch register. (1st is $ta) 16099 16100'pop.w var,ra5' 16101 Pop value of word variable var from stack using register ra5. 16102 16103'pop.h var,ra5' 16104 Pop value of half-word variable var from stack using register ra5. 16105 16106'pop.b var,ra5' 16107 Pop value of byte variable var from stack using register ra5. 16108 16109 16110File: as.info, Node: NiosII-Dependent, Next: NS32K-Dependent, Prev: NDS32-Dependent, Up: Machine Dependencies 16111 161129.31 Nios II Dependent Features 16113=============================== 16114 16115* Menu: 16116 16117* Nios II Options:: Options 16118* Nios II Syntax:: Syntax 16119* Nios II Relocations:: Relocations 16120* Nios II Directives:: Nios II Machine Directives 16121* Nios II Opcodes:: Opcodes 16122 16123 16124File: as.info, Node: Nios II Options, Next: Nios II Syntax, Up: NiosII-Dependent 16125 161269.31.1 Options 16127-------------- 16128 16129'-relax-section' 16130 Replace identified out-of-range branches with PC-relative 'jmp' 16131 sequences when possible. The generated code sequences are suitable 16132 for use in position-independent code, but there is a practical 16133 limit on the extended branch range because of the length of the 16134 sequences. This option is the default. 16135 16136'-relax-all' 16137 Replace branch instructions not determinable to be in range and all 16138 call instructions with 'jmp' and 'callr' sequences (respectively). 16139 This option generates absolute relocations against the target 16140 symbols and is not appropriate for position-independent code. 16141 16142'-no-relax' 16143 Do not replace any branches or calls. 16144 16145'-EB' 16146 Generate big-endian output. 16147 16148'-EL' 16149 Generate little-endian output. This is the default. 16150 16151'-march=ARCHITECTURE' 16152 This option specifies the target architecture. The assembler 16153 issues an error message if an attempt is made to assemble an 16154 instruction which will not execute on the target architecture. The 16155 following architecture names are recognized: 'r1', 'r2'. The 16156 default is 'r1'. 16157 16158 16159File: as.info, Node: Nios II Syntax, Next: Nios II Relocations, Prev: Nios II Options, Up: NiosII-Dependent 16160 161619.31.2 Syntax 16162------------- 16163 16164* Menu: 16165 16166* Nios II Chars:: Special Characters 16167 16168 16169File: as.info, Node: Nios II Chars, Up: Nios II Syntax 16170 161719.31.2.1 Special Characters 16172........................... 16173 16174'#' is the line comment character. ';' is the line separator character. 16175 16176 16177File: as.info, Node: Nios II Relocations, Next: Nios II Directives, Prev: Nios II Syntax, Up: NiosII-Dependent 16178 161799.31.3 Nios II Machine Relocations 16180---------------------------------- 16181 16182'%hiadj(EXPRESSION)' 16183 Extract the upper 16 bits of EXPRESSION and add one if the 15th bit 16184 is set. 16185 16186 The value of '%hiadj(EXPRESSION)' is: 16187 ((EXPRESSION >> 16) & 0xffff) + ((EXPRESSION >> 15) & 0x01) 16188 16189 The '%hiadj' relocation is intended to be used with the 'addi', 16190 'ld' or 'st' instructions along with a '%lo', in order to load a 16191 32-bit constant. 16192 16193 movhi r2, %hiadj(symbol) 16194 addi r2, r2, %lo(symbol) 16195 16196'%hi(EXPRESSION)' 16197 Extract the upper 16 bits of EXPRESSION. 16198 16199'%lo(EXPRESSION)' 16200 Extract the lower 16 bits of EXPRESSION. 16201 16202'%gprel(EXPRESSION)' 16203 Subtract the value of the symbol '_gp' from EXPRESSION. 16204 16205 The intention of the '%gprel' relocation is to have a fast small 16206 area of memory which only takes a 16-bit immediate to access. 16207 16208 .section .sdata 16209 fastint: 16210 .int 123 16211 .section .text 16212 ldw r4, %gprel(fastint)(gp) 16213 16214'%call(EXPRESSION)' 16215'%call_lo(EXPRESSION)' 16216'%call_hiadj(EXPRESSION)' 16217'%got(EXPRESSION)' 16218'%got_lo(EXPRESSION)' 16219'%got_hiadj(EXPRESSION)' 16220'%gotoff(EXPRESSION)' 16221'%gotoff_lo(EXPRESSION)' 16222'%gotoff_hiadj(EXPRESSION)' 16223'%tls_gd(EXPRESSION)' 16224'%tls_ie(EXPRESSION)' 16225'%tls_le(EXPRESSION)' 16226'%tls_ldm(EXPRESSION)' 16227'%tls_ldo(EXPRESSION)' 16228 16229 These relocations support the ABI for Linux Systems documented in 16230 the 'Nios II Processor Reference Handbook'. 16231 16232 16233File: as.info, Node: Nios II Directives, Next: Nios II Opcodes, Prev: Nios II Relocations, Up: NiosII-Dependent 16234 162359.31.4 Nios II Machine Directives 16236--------------------------------- 16237 16238'.align EXPRESSION [, EXPRESSION]' 16239 This is the generic '.align' directive, however this aligns to a 16240 power of two. 16241 16242'.half EXPRESSION' 16243 Create an aligned constant 2 bytes in size. 16244 16245'.word EXPRESSION' 16246 Create an aligned constant 4 bytes in size. 16247 16248'.dword EXPRESSION' 16249 Create an aligned constant 8 bytes in size. 16250 16251'.2byte EXPRESSION' 16252 Create an unaligned constant 2 bytes in size. 16253 16254'.4byte EXPRESSION' 16255 Create an unaligned constant 4 bytes in size. 16256 16257'.8byte EXPRESSION' 16258 Create an unaligned constant 8 bytes in size. 16259 16260'.16byte EXPRESSION' 16261 Create an unaligned constant 16 bytes in size. 16262 16263'.set noat' 16264 Allows assembly code to use 'at' register without warning. Macro 16265 or relaxation expansions generate warnings. 16266 16267'.set at' 16268 Assembly code using 'at' register generates warnings, and macro 16269 expansion and relaxation are enabled. 16270 16271'.set nobreak' 16272 Allows assembly code to use 'ba' and 'bt' registers without 16273 warning. 16274 16275'.set break' 16276 Turns warnings back on for using 'ba' and 'bt' registers. 16277 16278'.set norelax' 16279 Do not replace any branches or calls. 16280 16281'.set relaxsection' 16282 Replace identified out-of-range branches with 'jmp' sequences 16283 (default). 16284 16285'.set relaxsection' 16286 Replace all branch and call instructions with 'jmp' and 'callr' 16287 sequences. 16288 16289'.set ...' 16290 All other '.set' are the normal use. 16291 16292 16293File: as.info, Node: Nios II Opcodes, Prev: Nios II Directives, Up: NiosII-Dependent 16294 162959.31.5 Opcodes 16296-------------- 16297 16298'as' implements all the standard Nios II opcodes documented in the 'Nios 16299II Processor Reference Handbook', including the assembler 16300pseudo-instructions. 16301 16302 16303File: as.info, Node: NS32K-Dependent, Next: PDP-11-Dependent, Prev: NiosII-Dependent, Up: Machine Dependencies 16304 163059.32 NS32K Dependent Features 16306============================= 16307 16308* Menu: 16309 16310* NS32K Syntax:: Syntax 16311 16312 16313File: as.info, Node: NS32K Syntax, Up: NS32K-Dependent 16314 163159.32.1 Syntax 16316------------- 16317 16318* Menu: 16319 16320* NS32K-Chars:: Special Characters 16321 16322 16323File: as.info, Node: NS32K-Chars, Up: NS32K Syntax 16324 163259.32.1.1 Special Characters 16326........................... 16327 16328The presence of a '#' appearing anywhere on a line indicates the start 16329of a comment that extends to the end of that line. 16330 16331 If a '#' appears as the first character of a line then the whole line 16332is treated as a comment, but in this case the line can also be a logical 16333line number directive (*note Comments::) or a preprocessor control 16334command (*note Preprocessing::). 16335 16336 If Sequent compatibility has been configured into the assembler then 16337the '|' character appearing as the first character on a line will also 16338indicate the start of a line comment. 16339 16340 The ';' character can be used to separate statements on the same 16341line. 16342 16343 16344File: as.info, Node: PDP-11-Dependent, Next: PJ-Dependent, Prev: NS32K-Dependent, Up: Machine Dependencies 16345 163469.33 PDP-11 Dependent Features 16347============================== 16348 16349* Menu: 16350 16351* PDP-11-Options:: Options 16352* PDP-11-Pseudos:: Assembler Directives 16353* PDP-11-Syntax:: DEC Syntax versus BSD Syntax 16354* PDP-11-Mnemonics:: Instruction Naming 16355* PDP-11-Synthetic:: Synthetic Instructions 16356 16357 16358File: as.info, Node: PDP-11-Options, Next: PDP-11-Pseudos, Up: PDP-11-Dependent 16359 163609.33.1 Options 16361-------------- 16362 16363The PDP-11 version of 'as' has a rich set of machine dependent options. 16364 163659.33.1.1 Code Generation Options 16366................................ 16367 16368'-mpic | -mno-pic' 16369 Generate position-independent (or position-dependent) code. 16370 16371 The default is to generate position-independent code. 16372 163739.33.1.2 Instruction Set Extension Options 16374.......................................... 16375 16376These options enables or disables the use of extensions over the base 16377line instruction set as introduced by the first PDP-11 CPU: the KA11. 16378Most options come in two variants: a '-m'EXTENSION that enables 16379EXTENSION, and a '-mno-'EXTENSION that disables EXTENSION. 16380 16381 The default is to enable all extensions. 16382 16383'-mall | -mall-extensions' 16384 Enable all instruction set extensions. 16385 16386'-mno-extensions' 16387 Disable all instruction set extensions. 16388 16389'-mcis | -mno-cis' 16390 Enable (or disable) the use of the commercial instruction set, 16391 which consists of these instructions: 'ADDNI', 'ADDN', 'ADDPI', 16392 'ADDP', 'ASHNI', 'ASHN', 'ASHPI', 'ASHP', 'CMPCI', 'CMPC', 'CMPNI', 16393 'CMPN', 'CMPPI', 'CMPP', 'CVTLNI', 'CVTLN', 'CVTLPI', 'CVTLP', 16394 'CVTNLI', 'CVTNL', 'CVTNPI', 'CVTNP', 'CVTPLI', 'CVTPL', 'CVTPNI', 16395 'CVTPN', 'DIVPI', 'DIVP', 'L2DR', 'L3DR', 'LOCCI', 'LOCC', 'MATCI', 16396 'MATC', 'MOVCI', 'MOVC', 'MOVRCI', 'MOVRC', 'MOVTCI', 'MOVTC', 16397 'MULPI', 'MULP', 'SCANCI', 'SCANC', 'SKPCI', 'SKPC', 'SPANCI', 16398 'SPANC', 'SUBNI', 'SUBN', 'SUBPI', and 'SUBP'. 16399 16400'-mcsm | -mno-csm' 16401 Enable (or disable) the use of the 'CSM' instruction. 16402 16403'-meis | -mno-eis' 16404 Enable (or disable) the use of the extended instruction set, which 16405 consists of these instructions: 'ASHC', 'ASH', 'DIV', 'MARK', 16406 'MUL', 'RTT', 'SOB' 'SXT', and 'XOR'. 16407 16408'-mfis | -mkev11' 16409'-mno-fis | -mno-kev11' 16410 Enable (or disable) the use of the KEV11 floating-point 16411 instructions: 'FADD', 'FDIV', 'FMUL', and 'FSUB'. 16412 16413'-mfpp | -mfpu | -mfp-11' 16414'-mno-fpp | -mno-fpu | -mno-fp-11' 16415 Enable (or disable) the use of FP-11 floating-point instructions: 16416 'ABSF', 'ADDF', 'CFCC', 'CLRF', 'CMPF', 'DIVF', 'LDCFF', 'LDCIF', 16417 'LDEXP', 'LDF', 'LDFPS', 'MODF', 'MULF', 'NEGF', 'SETD', 'SETF', 16418 'SETI', 'SETL', 'STCFF', 'STCFI', 'STEXP', 'STF', 'STFPS', 'STST', 16419 'SUBF', and 'TSTF'. 16420 16421'-mlimited-eis | -mno-limited-eis' 16422 Enable (or disable) the use of the limited extended instruction 16423 set: 'MARK', 'RTT', 'SOB', 'SXT', and 'XOR'. 16424 16425 The -mno-limited-eis options also implies -mno-eis. 16426 16427'-mmfpt | -mno-mfpt' 16428 Enable (or disable) the use of the 'MFPT' instruction. 16429 16430'-mmultiproc | -mno-multiproc' 16431 Enable (or disable) the use of multiprocessor instructions: 16432 'TSTSET' and 'WRTLCK'. 16433 16434'-mmxps | -mno-mxps' 16435 Enable (or disable) the use of the 'MFPS' and 'MTPS' instructions. 16436 16437'-mspl | -mno-spl' 16438 Enable (or disable) the use of the 'SPL' instruction. 16439 16440 Enable (or disable) the use of the microcode instructions: 'LDUB', 16441 'MED', and 'XFC'. 16442 164439.33.1.3 CPU Model Options 16444.......................... 16445 16446These options enable the instruction set extensions supported by a 16447particular CPU, and disables all other extensions. 16448 16449'-mka11' 16450 KA11 CPU. Base line instruction set only. 16451 16452'-mkb11' 16453 KB11 CPU. Enable extended instruction set and 'SPL'. 16454 16455'-mkd11a' 16456 KD11-A CPU. Enable limited extended instruction set. 16457 16458'-mkd11b' 16459 KD11-B CPU. Base line instruction set only. 16460 16461'-mkd11d' 16462 KD11-D CPU. Base line instruction set only. 16463 16464'-mkd11e' 16465 KD11-E CPU. Enable extended instruction set, 'MFPS', and 'MTPS'. 16466 16467'-mkd11f | -mkd11h | -mkd11q' 16468 KD11-F, KD11-H, or KD11-Q CPU. Enable limited extended instruction 16469 set, 'MFPS', and 'MTPS'. 16470 16471'-mkd11k' 16472 KD11-K CPU. Enable extended instruction set, 'LDUB', 'MED', 'MFPS', 16473 'MFPT', 'MTPS', and 'XFC'. 16474 16475'-mkd11z' 16476 KD11-Z CPU. Enable extended instruction set, 'CSM', 'MFPS', 'MFPT', 16477 'MTPS', and 'SPL'. 16478 16479'-mf11' 16480 F11 CPU. Enable extended instruction set, 'MFPS', 'MFPT', and 16481 'MTPS'. 16482 16483'-mj11' 16484 J11 CPU. Enable extended instruction set, 'CSM', 'MFPS', 'MFPT', 16485 'MTPS', 'SPL', 'TSTSET', and 'WRTLCK'. 16486 16487'-mt11' 16488 T11 CPU. Enable limited extended instruction set, 'MFPS', and 16489 'MTPS'. 16490 164919.33.1.4 Machine Model Options 16492.............................. 16493 16494These options enable the instruction set extensions supported by a 16495particular machine model, and disables all other extensions. 16496 16497'-m11/03' 16498 Same as '-mkd11f'. 16499 16500'-m11/04' 16501 Same as '-mkd11d'. 16502 16503'-m11/05 | -m11/10' 16504 Same as '-mkd11b'. 16505 16506'-m11/15 | -m11/20' 16507 Same as '-mka11'. 16508 16509'-m11/21' 16510 Same as '-mt11'. 16511 16512'-m11/23 | -m11/24' 16513 Same as '-mf11'. 16514 16515'-m11/34' 16516 Same as '-mkd11e'. 16517 16518'-m11/34a' 16519 Ame as '-mkd11e' '-mfpp'. 16520 16521'-m11/35 | -m11/40' 16522 Same as '-mkd11a'. 16523 16524'-m11/44' 16525 Same as '-mkd11z'. 16526 16527'-m11/45 | -m11/50 | -m11/55 | -m11/70' 16528 Same as '-mkb11'. 16529 16530'-m11/53 | -m11/73 | -m11/83 | -m11/84 | -m11/93 | -m11/94' 16531 Same as '-mj11'. 16532 16533'-m11/60' 16534 Same as '-mkd11k'. 16535 16536 16537File: as.info, Node: PDP-11-Pseudos, Next: PDP-11-Syntax, Prev: PDP-11-Options, Up: PDP-11-Dependent 16538 165399.33.2 Assembler Directives 16540--------------------------- 16541 16542The PDP-11 version of 'as' has a few machine dependent assembler 16543directives. 16544 16545'.bss' 16546 Switch to the 'bss' section. 16547 16548'.even' 16549 Align the location counter to an even number. 16550 16551 16552File: as.info, Node: PDP-11-Syntax, Next: PDP-11-Mnemonics, Prev: PDP-11-Pseudos, Up: PDP-11-Dependent 16553 165549.33.3 PDP-11 Assembly Language Syntax 16555-------------------------------------- 16556 16557'as' supports both DEC syntax and BSD syntax. The only difference is 16558that in DEC syntax, a '#' character is used to denote an immediate 16559constants, while in BSD syntax the character for this purpose is '$'. 16560 16561 general-purpose registers are named 'r0' through 'r7'. Mnemonic 16562alternatives for 'r6' and 'r7' are 'sp' and 'pc', respectively. 16563 16564 Floating-point registers are named 'ac0' through 'ac3', or 16565alternatively 'fr0' through 'fr3'. 16566 16567 Comments are started with a '#' or a '/' character, and extend to the 16568end of the line. (FIXME: clash with immediates?) 16569 16570 Multiple statements on the same line can be separated by the ';' 16571character. 16572 16573 16574File: as.info, Node: PDP-11-Mnemonics, Next: PDP-11-Synthetic, Prev: PDP-11-Syntax, Up: PDP-11-Dependent 16575 165769.33.4 Instruction Naming 16577------------------------- 16578 16579Some instructions have alternative names. 16580 16581'BCC' 16582 'BHIS' 16583 16584'BCS' 16585 'BLO' 16586 16587'L2DR' 16588 'L2D' 16589 16590'L3DR' 16591 'L3D' 16592 16593'SYS' 16594 'TRAP' 16595 16596 16597File: as.info, Node: PDP-11-Synthetic, Prev: PDP-11-Mnemonics, Up: PDP-11-Dependent 16598 165999.33.5 Synthetic Instructions 16600----------------------------- 16601 16602The 'JBR' and 'J'CC synthetic instructions are not supported yet. 16603 16604 16605File: as.info, Node: PJ-Dependent, Next: PPC-Dependent, Prev: PDP-11-Dependent, Up: Machine Dependencies 16606 166079.34 picoJava Dependent Features 16608================================ 16609 16610* Menu: 16611 16612* PJ Options:: Options 16613* PJ Syntax:: PJ Syntax 16614 16615 16616File: as.info, Node: PJ Options, Next: PJ Syntax, Up: PJ-Dependent 16617 166189.34.1 Options 16619-------------- 16620 16621'as' has two additional command-line options for the picoJava 16622architecture. 16623'-ml' 16624 This option selects little endian data output. 16625 16626'-mb' 16627 This option selects big endian data output. 16628 16629 16630File: as.info, Node: PJ Syntax, Prev: PJ Options, Up: PJ-Dependent 16631 166329.34.2 PJ Syntax 16633---------------- 16634 16635* Menu: 16636 16637* PJ-Chars:: Special Characters 16638 16639 16640File: as.info, Node: PJ-Chars, Up: PJ Syntax 16641 166429.34.2.1 Special Characters 16643........................... 16644 16645The presence of a '!' or '/' on a line indicates the start of a comment 16646that extends to the end of the current line. 16647 16648 If a '#' appears as the first character of a line then the whole line 16649is treated as a comment, but in this case the line could also be a 16650logical line number directive (*note Comments::) or a preprocessor 16651control command (*note Preprocessing::). 16652 16653 The ';' character can be used to separate statements on the same 16654line. 16655 16656 16657File: as.info, Node: PPC-Dependent, Next: RL78-Dependent, Prev: PJ-Dependent, Up: Machine Dependencies 16658 166599.35 PowerPC Dependent Features 16660=============================== 16661 16662* Menu: 16663 16664* PowerPC-Opts:: Options 16665* PowerPC-Pseudo:: PowerPC Assembler Directives 16666* PowerPC-Syntax:: PowerPC Syntax 16667 16668 16669File: as.info, Node: PowerPC-Opts, Next: PowerPC-Pseudo, Up: PPC-Dependent 16670 166719.35.1 Options 16672-------------- 16673 16674The PowerPC chip family includes several successive levels, using the 16675same core instruction set, but including a few additional instructions 16676at each level. There are exceptions to this however. For details on 16677what instructions each variant supports, please see the chip's 16678architecture reference manual. 16679 16680 The following table lists all available PowerPC options. 16681 16682'-a32' 16683 Generate ELF32 or XCOFF32. 16684 16685'-a64' 16686 Generate ELF64 or XCOFF64. 16687 16688'-K PIC' 16689 Set EF_PPC_RELOCATABLE_LIB in ELF flags. 16690 16691'-mpwrx | -mpwr2' 16692 Generate code for POWER/2 (RIOS2). 16693 16694'-mpwr' 16695 Generate code for POWER (RIOS1) 16696 16697'-m601' 16698 Generate code for PowerPC 601. 16699 16700'-mppc, -mppc32, -m603, -m604' 16701 Generate code for PowerPC 603/604. 16702 16703'-m403, -m405' 16704 Generate code for PowerPC 403/405. 16705 16706'-m440' 16707 Generate code for PowerPC 440. BookE and some 405 instructions. 16708 16709'-m464' 16710 Generate code for PowerPC 464. 16711 16712'-m476' 16713 Generate code for PowerPC 476. 16714 16715'-m7400, -m7410, -m7450, -m7455' 16716 Generate code for PowerPC 7400/7410/7450/7455. 16717 16718'-m750cl' 16719 Generate code for PowerPC 750CL. 16720 16721'-m821, -m850, -m860' 16722 Generate code for PowerPC 821/850/860. 16723 16724'-mppc64, -m620' 16725 Generate code for PowerPC 620/625/630. 16726 16727'-me500, -me500x2' 16728 Generate code for Motorola e500 core complex. 16729 16730'-me500mc' 16731 Generate code for Freescale e500mc core complex. 16732 16733'-me500mc64' 16734 Generate code for Freescale e500mc64 core complex. 16735 16736'-me5500' 16737 Generate code for Freescale e5500 core complex. 16738 16739'-me6500' 16740 Generate code for Freescale e6500 core complex. 16741 16742'-mspe' 16743 Generate code for Motorola SPE instructions. 16744 16745'-mtitan' 16746 Generate code for AppliedMicro Titan core complex. 16747 16748'-mppc64bridge' 16749 Generate code for PowerPC 64, including bridge insns. 16750 16751'-mbooke' 16752 Generate code for 32-bit BookE. 16753 16754'-ma2' 16755 Generate code for A2 architecture. 16756 16757'-me300' 16758 Generate code for PowerPC e300 family. 16759 16760'-maltivec' 16761 Generate code for processors with AltiVec instructions. 16762 16763'-mvle' 16764 Generate code for Freescale PowerPC VLE instructions. 16765 16766'-mvsx' 16767 Generate code for processors with Vector-Scalar (VSX) instructions. 16768 16769'-mhtm' 16770 Generate code for processors with Hardware Transactional Memory 16771 instructions. 16772 16773'-mpower4, -mpwr4' 16774 Generate code for Power4 architecture. 16775 16776'-mpower5, -mpwr5, -mpwr5x' 16777 Generate code for Power5 architecture. 16778 16779'-mpower6, -mpwr6' 16780 Generate code for Power6 architecture. 16781 16782'-mpower7, -mpwr7' 16783 Generate code for Power7 architecture. 16784 16785'-mpower8, -mpwr8' 16786 Generate code for Power8 architecture. 16787 16788'-mpower9, -mpwr9' 16789 Generate code for Power9 architecture. 16790 16791'-mcell' 16792'-mcell' 16793 Generate code for Cell Broadband Engine architecture. 16794 16795'-mcom' 16796 Generate code Power/PowerPC common instructions. 16797 16798'-many' 16799 Generate code for any architecture (PWR/PWRX/PPC). 16800 16801'-mregnames' 16802 Allow symbolic names for registers. 16803 16804'-mno-regnames' 16805 Do not allow symbolic names for registers. 16806 16807'-mrelocatable' 16808 Support for GCC's -mrelocatable option. 16809 16810'-mrelocatable-lib' 16811 Support for GCC's -mrelocatable-lib option. 16812 16813'-memb' 16814 Set PPC_EMB bit in ELF flags. 16815 16816'-mlittle, -mlittle-endian, -le' 16817 Generate code for a little endian machine. 16818 16819'-mbig, -mbig-endian, -be' 16820 Generate code for a big endian machine. 16821 16822'-msolaris' 16823 Generate code for Solaris. 16824 16825'-mno-solaris' 16826 Do not generate code for Solaris. 16827 16828'-nops=COUNT' 16829 If an alignment directive inserts more than COUNT nops, put a 16830 branch at the beginning to skip execution of the nops. 16831 16832 16833File: as.info, Node: PowerPC-Pseudo, Next: PowerPC-Syntax, Prev: PowerPC-Opts, Up: PPC-Dependent 16834 168359.35.2 PowerPC Assembler Directives 16836----------------------------------- 16837 16838A number of assembler directives are available for PowerPC. The 16839following table is far from complete. 16840 16841'.machine "string"' 16842 This directive allows you to change the machine for which code is 16843 generated. '"string"' may be any of the -m cpu selection options 16844 (without the -m) enclosed in double quotes, '"push"', or '"pop"'. 16845 '.machine "push"' saves the currently selected cpu, which may be 16846 restored with '.machine "pop"'. 16847 16848 16849File: as.info, Node: PowerPC-Syntax, Prev: PowerPC-Pseudo, Up: PPC-Dependent 16850 168519.35.3 PowerPC Syntax 16852--------------------- 16853 16854* Menu: 16855 16856* PowerPC-Chars:: Special Characters 16857 16858 16859File: as.info, Node: PowerPC-Chars, Up: PowerPC-Syntax 16860 168619.35.3.1 Special Characters 16862........................... 16863 16864The presence of a '#' on a line indicates the start of a comment that 16865extends to the end of the current line. 16866 16867 If a '#' appears as the first character of a line then the whole line 16868is treated as a comment, but in this case the line could also be a 16869logical line number directive (*note Comments::) or a preprocessor 16870control command (*note Preprocessing::). 16871 16872 If the assembler has been configured for the ppc-*-solaris* target 16873then the '!' character also acts as a line comment character. This can 16874be disabled via the '-mno-solaris' command line option. 16875 16876 The ';' character can be used to separate statements on the same 16877line. 16878 16879 16880File: as.info, Node: RL78-Dependent, Next: RISC-V-Dependent, Prev: PPC-Dependent, Up: Machine Dependencies 16881 168829.36 RL78 Dependent Features 16883============================ 16884 16885* Menu: 16886 16887* RL78-Opts:: RL78 Assembler Command Line Options 16888* RL78-Modifiers:: Symbolic Operand Modifiers 16889* RL78-Directives:: Assembler Directives 16890* RL78-Syntax:: Syntax 16891 16892 16893File: as.info, Node: RL78-Opts, Next: RL78-Modifiers, Up: RL78-Dependent 16894 168959.36.1 RL78 Options 16896------------------- 16897 16898'relax' 16899 Enable support for link-time relaxation. 16900 16901'norelax' 16902 Disable support for link-time relaxation (default). 16903 16904'mg10' 16905 Mark the generated binary as targeting the G10 variant of the RL78 16906 architecture. 16907 16908'mg13' 16909 Mark the generated binary as targeting the G13 variant of the RL78 16910 architecture. 16911 16912'mg14' 16913'mrl78' 16914 Mark the generated binary as targeting the G14 variant of the RL78 16915 architecture. This is the default. 16916 16917'm32bit-doubles' 16918 Mark the generated binary as one that uses 32-bits to hold the 16919 'double' floating point type. This is the default. 16920 16921'm64bit-doubles' 16922 Mark the generated binary as one that uses 64-bits to hold the 16923 'double' floating point type. 16924 16925 16926File: as.info, Node: RL78-Modifiers, Next: RL78-Directives, Prev: RL78-Opts, Up: RL78-Dependent 16927 169289.36.2 Symbolic Operand Modifiers 16929--------------------------------- 16930 16931The RL78 has three modifiers that adjust the relocations used by the 16932linker: 16933 16934'%lo16()' 16935 16936 When loading a 20-bit (or wider) address into registers, this 16937 modifier selects the 16 least significant bits. 16938 16939 movw ax,#%lo16(_sym) 16940 16941'%hi16()' 16942 16943 When loading a 20-bit (or wider) address into registers, this 16944 modifier selects the 16 most significant bits. 16945 16946 movw ax,#%hi16(_sym) 16947 16948'%hi8()' 16949 16950 When loading a 20-bit (or wider) address into registers, this 16951 modifier selects the 8 bits that would go into CS or ES (i.e. bits 16952 23..16). 16953 16954 mov es, #%hi8(_sym) 16955 16956 16957File: as.info, Node: RL78-Directives, Next: RL78-Syntax, Prev: RL78-Modifiers, Up: RL78-Dependent 16958 169599.36.3 Assembler Directives 16960--------------------------- 16961 16962In addition to the common directives, the RL78 adds these: 16963 16964'.double' 16965 Output a constant in "double" format, which is either a 32-bit or a 16966 64-bit floating point value, depending upon the setting of the 16967 '-m32bit-doubles'|'-m64bit-doubles' command line option. 16968 16969'.bss' 16970 Select the BSS section. 16971 16972'.3byte' 16973 Output a constant value in a three byte format. 16974 16975'.int' 16976'.word' 16977 Output a constant value in a four byte format. 16978 16979 16980File: as.info, Node: RL78-Syntax, Prev: RL78-Directives, Up: RL78-Dependent 16981 169829.36.4 Syntax for the RL78 16983-------------------------- 16984 16985* Menu: 16986 16987* RL78-Chars:: Special Characters 16988 16989 16990File: as.info, Node: RL78-Chars, Up: RL78-Syntax 16991 169929.36.4.1 Special Characters 16993........................... 16994 16995The presence of a ';' appearing anywhere on a line indicates the start 16996of a comment that extends to the end of that line. 16997 16998 If a '#' appears as the first character of a line then the whole line 16999is treated as a comment, but in this case the line can also be a logical 17000line number directive (*note Comments::) or a preprocessor control 17001command (*note Preprocessing::). 17002 17003 The '|' character can be used to separate statements on the same 17004line. 17005 17006 17007File: as.info, Node: RISC-V-Dependent, Next: RX-Dependent, Prev: RL78-Dependent, Up: Machine Dependencies 17008 170099.37 RISC-V Dependent Features 17010============================== 17011 17012* Menu: 17013 17014* RISC-V-Opts:: RISC-V Options 17015 17016 17017File: as.info, Node: RISC-V-Opts, Up: RISC-V-Dependent 17018 170199.37.1 Options 17020-------------- 17021 17022The following table lists all availiable RISC-V specific options 17023 17024'-fpic' 17025 Generate position-independent code 17026 17027'-fno-pic' 17028 Don't generate position-independent code (default) 17029 17030'-march=ISA' 17031 Select the base isa, as specified by ISA. For example 17032 -march=rv32ima. 17033 17034'-mabi=ABI' 17035 Selects the ABI, which is either "ilp32" or "lp64", optionally 17036 followed by "f", "d", or "q" to indicate single-precision, 17037 double-precision, or quad-precision floating-point calling 17038 convention, or none to indicate the soft-float calling convention. 17039 17040 17041File: as.info, Node: RX-Dependent, Next: S/390-Dependent, Prev: RISC-V-Dependent, Up: Machine Dependencies 17042 170439.38 RX Dependent Features 17044========================== 17045 17046* Menu: 17047 17048* RX-Opts:: RX Assembler Command Line Options 17049* RX-Modifiers:: Symbolic Operand Modifiers 17050* RX-Directives:: Assembler Directives 17051* RX-Float:: Floating Point 17052* RX-Syntax:: Syntax 17053 17054 17055File: as.info, Node: RX-Opts, Next: RX-Modifiers, Up: RX-Dependent 17056 170579.38.1 RX Options 17058----------------- 17059 17060The Renesas RX port of 'as' has a few target specfic command line 17061options: 17062 17063'-m32bit-doubles' 17064 This option controls the ABI and indicates to use a 32-bit float 17065 ABI. It has no effect on the assembled instructions, but it does 17066 influence the behaviour of the '.double' pseudo-op. This is the 17067 default. 17068 17069'-m64bit-doubles' 17070 This option controls the ABI and indicates to use a 64-bit float 17071 ABI. It has no effect on the assembled instructions, but it does 17072 influence the behaviour of the '.double' pseudo-op. 17073 17074'-mbig-endian' 17075 This option controls the ABI and indicates to use a big-endian data 17076 ABI. It has no effect on the assembled instructions, but it does 17077 influence the behaviour of the '.short', '.hword', '.int', '.word', 17078 '.long', '.quad' and '.octa' pseudo-ops. 17079 17080'-mlittle-endian' 17081 This option controls the ABI and indicates to use a little-endian 17082 data ABI. It has no effect on the assembled instructions, but it 17083 does influence the behaviour of the '.short', '.hword', '.int', 17084 '.word', '.long', '.quad' and '.octa' pseudo-ops. This is the 17085 default. 17086 17087'-muse-conventional-section-names' 17088 This option controls the default names given to the code (.text), 17089 initialised data (.data) and uninitialised data sections (.bss). 17090 17091'-muse-renesas-section-names' 17092 This option controls the default names given to the code (.P), 17093 initialised data (.D_1) and uninitialised data sections (.B_1). 17094 This is the default. 17095 17096'-msmall-data-limit' 17097 This option tells the assembler that the small data limit feature 17098 of the RX port of GCC is being used. This results in the assembler 17099 generating an undefined reference to a symbol called '__gp' for use 17100 by the relocations that are needed to support the small data limit 17101 feature. This option is not enabled by default as it would 17102 otherwise pollute the symbol table. 17103 17104'-mpid' 17105 This option tells the assembler that the position independent data 17106 of the RX port of GCC is being used. This results in the assembler 17107 generating an undefined reference to a symbol called '__pid_base', 17108 and also setting the RX_PID flag bit in the e_flags field of the 17109 ELF header of the object file. 17110 17111'-mint-register=NUM' 17112 This option tells the assembler how many registers have been 17113 reserved for use by interrupt handlers. This is needed in order to 17114 compute the correct values for the '%gpreg' and '%pidreg' meta 17115 registers. 17116 17117'-mgcc-abi' 17118 This option tells the assembler that the old GCC ABI is being used 17119 by the assembled code. With this version of the ABI function 17120 arguments that are passed on the stack are aligned to a 32-bit 17121 boundary. 17122 17123'-mrx-abi' 17124 This option tells the assembler that the official RX ABI is being 17125 used by the assembled code. With this version of the ABI function 17126 arguments that are passed on the stack are aligned to their natural 17127 alignments. This option is the default. 17128 17129'-mcpu=NAME' 17130 This option tells the assembler the target CPU type. Currently the 17131 'rx100', 'rx200', 'rx600', 'rx610' and 'rxv2' are recognised as 17132 valid cpu names. Attempting to assemble an instruction not 17133 supported by the indicated cpu type will result in an error message 17134 being generated. 17135 17136'-mno-allow-string-insns' 17137 This option tells the assembler to mark the object file that it is 17138 building as one that does not use the string instructions 'SMOVF', 17139 'SCMPU', 'SMOVB', 'SMOVU', 'SUNTIL' 'SWHILE' or the 'RMPA' 17140 instruction. In addition the mark tells the linker to complain if 17141 an attempt is made to link the binary with another one that does 17142 use any of these instructions. 17143 17144 Note - the inverse of this option, '-mallow-string-insns', is not 17145 needed. The assembler automatically detects the use of the the 17146 instructions in the source code and labels the resulting object 17147 file appropriately. If no string instructions are detected then 17148 the object file is labelled as being one that can be linked with 17149 either string-using or string-banned object files. 17150 17151 17152File: as.info, Node: RX-Modifiers, Next: RX-Directives, Prev: RX-Opts, Up: RX-Dependent 17153 171549.38.2 Symbolic Operand Modifiers 17155--------------------------------- 17156 17157The assembler supports one modifier when using symbol addresses in RX 17158instruction operands. The general syntax is the following: 17159 17160 %gp(symbol) 17161 17162 The modifier returns the offset from the __GP symbol to the specified 17163symbol as a 16-bit value. The intent is that this offset should be used 17164in a register+offset move instruction when generating references to 17165small data. Ie, like this: 17166 17167 mov.W %gp(_foo)[%gpreg], r1 17168 17169 The assembler also supports two meta register names which can be used 17170to refer to registers whose values may not be known to the programmer. 17171These meta register names are: 17172 17173'%gpreg' 17174 The small data address register. 17175 17176'%pidreg' 17177 The PID base address register. 17178 17179 Both registers normally have the value r13, but this can change if 17180some registers have been reserved for use by interrupt handlers or if 17181both the small data limit and position independent data features are 17182being used at the same time. 17183 17184 17185File: as.info, Node: RX-Directives, Next: RX-Float, Prev: RX-Modifiers, Up: RX-Dependent 17186 171879.38.3 Assembler Directives 17188--------------------------- 17189 17190The RX version of 'as' has the following specific assembler directives: 17191 17192'.3byte' 17193 Inserts a 3-byte value into the output file at the current 17194 location. 17195 17196'.fetchalign' 17197 If the next opcode following this directive spans a fetch line 17198 boundary (8 byte boundary), the opcode is aligned to that boundary. 17199 If the next opcode does not span a fetch line, this directive has 17200 no effect. Note that one or more labels may be between this 17201 directive and the opcode; those labels are aligned as well. Any 17202 inserted bytes due to alignment will form a NOP opcode. 17203 17204 17205File: as.info, Node: RX-Float, Next: RX-Syntax, Prev: RX-Directives, Up: RX-Dependent 17206 172079.38.4 Floating Point 17208--------------------- 17209 17210The floating point formats generated by directives are these. 17211 17212'.float' 17213 'Single' precision (32-bit) floating point constants. 17214 17215'.double' 17216 If the '-m64bit-doubles' command line option has been specified 17217 then then 'double' directive generates 'double' precision (64-bit) 17218 floating point constants, otherwise it generates 'single' precision 17219 (32-bit) floating point constants. To force the generation of 17220 64-bit floating point constants used the 'dc.d' directive instead. 17221 17222 17223File: as.info, Node: RX-Syntax, Prev: RX-Float, Up: RX-Dependent 17224 172259.38.5 Syntax for the RX 17226------------------------ 17227 17228* Menu: 17229 17230* RX-Chars:: Special Characters 17231 17232 17233File: as.info, Node: RX-Chars, Up: RX-Syntax 17234 172359.38.5.1 Special Characters 17236........................... 17237 17238The presence of a ';' appearing anywhere on a line indicates the start 17239of a comment that extends to the end of that line. 17240 17241 If a '#' appears as the first character of a line then the whole line 17242is treated as a comment, but in this case the line can also be a logical 17243line number directive (*note Comments::) or a preprocessor control 17244command (*note Preprocessing::). 17245 17246 The '!' character can be used to separate statements on the same 17247line. 17248 17249 17250File: as.info, Node: S/390-Dependent, Next: SCORE-Dependent, Prev: RX-Dependent, Up: Machine Dependencies 17251 172529.39 IBM S/390 Dependent Features 17253================================= 17254 17255The s390 version of 'as' supports two architectures modes and eleven 17256chip levels. The architecture modes are the Enterprise System 17257Architecture (ESA) and the newer z/Architecture mode. The chip levels 17258are g5 (or arch3), g6, z900 (or arch5), z990 (or arch6), z9-109, z9-ec 17259(or arch7), z10 (or arch8), z196 (or arch9), zEC12 (or arch10), z13 (or 17260arch11), and arch12. 17261 17262* Menu: 17263 17264* s390 Options:: Command-line Options. 17265* s390 Characters:: Special Characters. 17266* s390 Syntax:: Assembler Instruction syntax. 17267* s390 Directives:: Assembler Directives. 17268* s390 Floating Point:: Floating Point. 17269 17270 17271File: as.info, Node: s390 Options, Next: s390 Characters, Up: S/390-Dependent 17272 172739.39.1 Options 17274-------------- 17275 17276The following table lists all available s390 specific options: 17277 17278'-m31 | -m64' 17279 Select 31- or 64-bit ABI implying a word size of 32- or 64-bit. 17280 17281 These options are only available with the ELF object file format, 17282 and require that the necessary BFD support has been included (on a 17283 31-bit platform you must add -enable-64-bit-bfd on the call to the 17284 configure script to enable 64-bit usage and use s390x as target 17285 platform). 17286 17287'-mesa | -mzarch' 17288 Select the architecture mode, either the Enterprise System 17289 Architecture (esa) mode or the z/Architecture mode (zarch). 17290 17291 The 64-bit instructions are only available with the z/Architecture 17292 mode. The combination of '-m64' and '-mesa' results in a warning 17293 message. 17294 17295'-march=CPU' 17296 This option specifies the target processor. The following 17297 processor names are recognized: 'g5' (or 'arch3'), 'g6', 'z900' (or 17298 'arch5'), 'z990' (or 'arch6'), 'z9-109', 'z9-ec' (or 'arch7'), 17299 'z10' (or 'arch8'), 'z196' (or 'arch9'), 'zEC12' (or 'arch10') and 17300 'z13' (or 'arch11'). 17301 17302 Assembling an instruction that is not supported on the target 17303 processor results in an error message. 17304 17305 The processor names starting with 'arch' refer to the edition 17306 number in the Principle of Operations manual. They can be used as 17307 alternate processor names and have been added for compatibility 17308 with the IBM XL compiler. 17309 17310 'arch3', 'g5' and 'g6' cannot be used with the '-mzarch' option 17311 since the z/Architecture mode is not supported on these processor 17312 levels. 17313 17314 There is no 'arch4' option supported. 'arch4' matches 17315 '-march=arch5 -mesa'. 17316 17317'-mregnames' 17318 Allow symbolic names for registers. 17319 17320'-mno-regnames' 17321 Do not allow symbolic names for registers. 17322 17323'-mwarn-areg-zero' 17324 Warn whenever the operand for a base or index register has been 17325 specified but evaluates to zero. This can indicate the misuse of 17326 general purpose register 0 as an address register. 17327 17328 17329File: as.info, Node: s390 Characters, Next: s390 Syntax, Prev: s390 Options, Up: S/390-Dependent 17330 173319.39.2 Special Characters 17332------------------------- 17333 17334'#' is the line comment character. 17335 17336 If a '#' appears as the first character of a line then the whole line 17337is treated as a comment, but in this case the line could also be a 17338logical line number directive (*note Comments::) or a preprocessor 17339control command (*note Preprocessing::). 17340 17341 The ';' character can be used instead of a newline to separate 17342statements. 17343 17344 17345File: as.info, Node: s390 Syntax, Next: s390 Directives, Prev: s390 Characters, Up: S/390-Dependent 17346 173479.39.3 Instruction syntax 17348------------------------- 17349 17350The assembler syntax closely follows the syntax outlined in Enterprise 17351Systems Architecture/390 Principles of Operation (SA22-7201) and the 17352z/Architecture Principles of Operation (SA22-7832). 17353 17354 Each instruction has two major parts, the instruction mnemonic and 17355the instruction operands. The instruction format varies. 17356 17357* Menu: 17358 17359* s390 Register:: Register Naming 17360* s390 Mnemonics:: Instruction Mnemonics 17361* s390 Operands:: Instruction Operands 17362* s390 Formats:: Instruction Formats 17363* s390 Aliases:: Instruction Aliases 17364* s390 Operand Modifier:: Instruction Operand Modifier 17365* s390 Instruction Marker:: Instruction Marker 17366* s390 Literal Pool Entries:: Literal Pool Entries 17367 17368 17369File: as.info, Node: s390 Register, Next: s390 Mnemonics, Up: s390 Syntax 17370 173719.39.3.1 Register naming 17372........................ 17373 17374The 'as' recognizes a number of predefined symbols for the various 17375processor registers. A register specification in one of the instruction 17376formats is an unsigned integer between 0 and 15. The specific 17377instruction and the position of the register in the instruction format 17378denotes the type of the register. The register symbols are prefixed 17379with '%': 17380 17381 %rN the 16 general purpose registers, 0 <= N <= 15 17382 %fN the 16 floating point registers, 0 <= N <= 15 17383 %aN the 16 access registers, 0 <= N <= 15 17384 %cN the 16 control registers, 0 <= N <= 15 17385 %lit an alias for the general purpose register %r13 17386 %sp an alias for the general purpose register %r15 17387 17388 17389File: as.info, Node: s390 Mnemonics, Next: s390 Operands, Prev: s390 Register, Up: s390 Syntax 17390 173919.39.3.2 Instruction Mnemonics 17392.............................. 17393 17394All instructions documented in the Principles of Operation are supported 17395with the mnemonic and order of operands as described. The instruction 17396mnemonic identifies the instruction format (*note s390 Formats::) and 17397the specific operation code for the instruction. For example, the 'lr' 17398mnemonic denotes the instruction format 'RR' with the operation code 17399'0x18'. 17400 17401 The definition of the various mnemonics follows a scheme, where the 17402first character usually hint at the type of the instruction: 17403 17404 a add instruction, for example 'al' for add logical 32-bit 17405 b branch instruction, for example 'bc' for branch on condition 17406 c compare or convert instruction, for example 'cr' for compare 17407 register 32-bit 17408 d divide instruction, for example 'dlr' devide logical register 17409 64-bit to 32-bit 17410 i insert instruction, for example 'ic' insert character 17411 l load instruction, for example 'ltr' load and test register 17412 mv move instruction, for example 'mvc' move character 17413 m multiply instruction, for example 'mh' multiply halfword 17414 n and instruction, for example 'ni' and immediate 17415 o or instruction, for example 'oc' or character 17416 sla, sll shift left single instruction 17417 sra, srl shift right single instruction 17418 st store instruction, for example 'stm' store multiple 17419 s subtract instruction, for example 'slr' subtract 17420 logical 32-bit 17421 t test or translate instruction, of example 'tm' test under mask 17422 x exclusive or instruction, for example 'xc' exclusive or 17423 character 17424 17425 Certain characters at the end of the mnemonic may describe a property 17426of the instruction: 17427 17428 c the instruction uses a 8-bit character operand 17429 f the instruction extends a 32-bit operand to 64 bit 17430 g the operands are treated as 64-bit values 17431 h the operand uses a 16-bit halfword operand 17432 i the instruction uses an immediate operand 17433 l the instruction uses unsigned, logical operands 17434 m the instruction uses a mask or operates on multiple values 17435 r if r is the last character, the instruction operates on registers 17436 y the instruction uses 20-bit displacements 17437 17438 There are many exceptions to the scheme outlined in the above lists, 17439in particular for the priviledged instructions. For non-priviledged 17440instruction it works quite well, for example the instruction 'clgfr' c: 17441compare instruction, l: unsigned operands, g: 64-bit operands, f: 32- to 1744264-bit extension, r: register operands. The instruction compares an 1744364-bit value in a register with the zero extended 32-bit value from a 17444second register. For a complete list of all mnemonics see appendix B in 17445the Principles of Operation. 17446 17447 17448File: as.info, Node: s390 Operands, Next: s390 Formats, Prev: s390 Mnemonics, Up: s390 Syntax 17449 174509.39.3.3 Instruction Operands 17451............................. 17452 17453Instruction operands can be grouped into three classes, operands located 17454in registers, immediate operands, and operands in storage. 17455 17456 A register operand can be located in general, floating-point, access, 17457or control register. The register is identified by a four-bit field. 17458The field containing the register operand is called the R field. 17459 17460 Immediate operands are contained within the instruction and can have 174618, 16 or 32 bits. The field containing the immediate operand is called 17462the I field. Dependent on the instruction the I field is either signed 17463or unsigned. 17464 17465 A storage operand consists of an address and a length. The address 17466of a storage operands can be specified in any of these ways: 17467 17468 * The content of a single general R 17469 * The sum of the content of a general register called the base 17470 register B plus the content of a displacement field D 17471 * The sum of the contents of two general registers called the index 17472 register X and the base register B plus the content of a 17473 displacement field 17474 * The sum of the current instruction address and a 32-bit signed 17475 immediate field multiplied by two. 17476 17477 The length of a storage operand can be: 17478 17479 * Implied by the instruction 17480 * Specified by a bitmask 17481 * Specified by a four-bit or eight-bit length field L 17482 * Specified by the content of a general register 17483 17484 The notation for storage operand addresses formed from multiple 17485fields is as follows: 17486 17487'Dn(Bn)' 17488 the address for operand number n is formed from the content of 17489 general register Bn called the base register and the displacement 17490 field Dn. 17491'Dn(Xn,Bn)' 17492 the address for operand number n is formed from the content of 17493 general register Xn called the index register, general register Bn 17494 called the base register and the displacement field Dn. 17495'Dn(Ln,Bn)' 17496 the address for operand number n is formed from the content of 17497 general regiser Bn called the base register and the displacement 17498 field Dn. The length of the operand n is specified by the field 17499 Ln. 17500 17501 The base registers Bn and the index registers Xn of a storage operand 17502can be skipped. If Bn and Xn are skipped, a zero will be stored to the 17503operand field. The notation changes as follows: 17504 17505 full notation short notation 17506 ---------------------------------------------- 17507 Dn(0,Bn) Dn(Bn) 17508 Dn(0,0) Dn 17509 Dn(0) Dn 17510 Dn(Ln,0) Dn(Ln) 17511 17512 17513File: as.info, Node: s390 Formats, Next: s390 Aliases, Prev: s390 Operands, Up: s390 Syntax 17514 175159.39.3.4 Instruction Formats 17516............................ 17517 17518The Principles of Operation manuals lists 26 instruction formats where 17519some of the formats have multiple variants. For the '.insn' pseudo 17520directive the assembler recognizes some of the formats. Typically, the 17521most general variant of the instruction format is used by the '.insn' 17522directive. 17523 17524 The following table lists the abbreviations used in the table of 17525instruction formats: 17526 17527 OpCode / OpCd Part of the op code. 17528 Bx Base register number for operand x. 17529 Dx Displacement for operand x. 17530 DLx Displacement lower 12 bits for operand x. 17531 DHx Displacement higher 8-bits for operand x. 17532 Rx Register number for operand x. 17533 Xx Index register number for operand x. 17534 Ix Signed immediate for operand x. 17535 Ux Unsigned immediate for operand x. 17536 17537 An instruction is two, four, or six bytes in length and must be 17538aligned on a 2 byte boundary. The first two bits of the instruction 17539specify the length of the instruction, 00 indicates a two byte 17540instruction, 01 and 10 indicates a four byte instruction, and 11 17541indicates a six byte instruction. 17542 17543 The following table lists the s390 instruction formats that are 17544available with the '.insn' pseudo directive: 17545 17546'E format' 17547 +-------------+ 17548 | OpCode | 17549 +-------------+ 17550 0 15 17551 17552'RI format: <insn> R1,I2' 17553 +--------+----+----+------------------+ 17554 | OpCode | R1 |OpCd| I2 | 17555 +--------+----+----+------------------+ 17556 0 8 12 16 31 17557 17558'RIE format: <insn> R1,R3,I2' 17559 +--------+----+----+------------------+--------+--------+ 17560 | OpCode | R1 | R3 | I2 |////////| OpCode | 17561 +--------+----+----+------------------+--------+--------+ 17562 0 8 12 16 32 40 47 17563 17564'RIL format: <insn> R1,I2' 17565 +--------+----+----+------------------------------------+ 17566 | OpCode | R1 |OpCd| I2 | 17567 +--------+----+----+------------------------------------+ 17568 0 8 12 16 47 17569 17570'RILU format: <insn> R1,U2' 17571 +--------+----+----+------------------------------------+ 17572 | OpCode | R1 |OpCd| U2 | 17573 +--------+----+----+------------------------------------+ 17574 0 8 12 16 47 17575 17576'RIS format: <insn> R1,I2,M3,D4(B4)' 17577 +--------+----+----+----+-------------+--------+--------+ 17578 | OpCode | R1 | M3 | B4 | D4 | I2 | Opcode | 17579 +--------+----+----+----+-------------+--------+--------+ 17580 0 8 12 16 20 32 36 47 17581 17582'RR format: <insn> R1,R2' 17583 +--------+----+----+ 17584 | OpCode | R1 | R2 | 17585 +--------+----+----+ 17586 0 8 12 15 17587 17588'RRE format: <insn> R1,R2' 17589 +------------------+--------+----+----+ 17590 | OpCode |////////| R1 | R2 | 17591 +------------------+--------+----+----+ 17592 0 16 24 28 31 17593 17594'RRF format: <insn> R1,R2,R3,M4' 17595 +------------------+----+----+----+----+ 17596 | OpCode | R3 | M4 | R1 | R2 | 17597 +------------------+----+----+----+----+ 17598 0 16 20 24 28 31 17599 17600'RRS format: <insn> R1,R2,M3,D4(B4)' 17601 +--------+----+----+----+-------------+----+----+--------+ 17602 | OpCode | R1 | R3 | B4 | D4 | M3 |////| OpCode | 17603 +--------+----+----+----+-------------+----+----+--------+ 17604 0 8 12 16 20 32 36 40 47 17605 17606'RS format: <insn> R1,R3,D2(B2)' 17607 +--------+----+----+----+-------------+ 17608 | OpCode | R1 | R3 | B2 | D2 | 17609 +--------+----+----+----+-------------+ 17610 0 8 12 16 20 31 17611 17612'RSE format: <insn> R1,R3,D2(B2)' 17613 +--------+----+----+----+-------------+--------+--------+ 17614 | OpCode | R1 | R3 | B2 | D2 |////////| OpCode | 17615 +--------+----+----+----+-------------+--------+--------+ 17616 0 8 12 16 20 32 40 47 17617 17618'RSI format: <insn> R1,R3,I2' 17619 +--------+----+----+------------------------------------+ 17620 | OpCode | R1 | R3 | I2 | 17621 +--------+----+----+------------------------------------+ 17622 0 8 12 16 47 17623 17624'RSY format: <insn> R1,R3,D2(B2)' 17625 +--------+----+----+----+-------------+--------+--------+ 17626 | OpCode | R1 | R3 | B2 | DL2 | DH2 | OpCode | 17627 +--------+----+----+----+-------------+--------+--------+ 17628 0 8 12 16 20 32 40 47 17629 17630'RX format: <insn> R1,D2(X2,B2)' 17631 +--------+----+----+----+-------------+ 17632 | OpCode | R1 | X2 | B2 | D2 | 17633 +--------+----+----+----+-------------+ 17634 0 8 12 16 20 31 17635 17636'RXE format: <insn> R1,D2(X2,B2)' 17637 +--------+----+----+----+-------------+--------+--------+ 17638 | OpCode | R1 | X2 | B2 | D2 |////////| OpCode | 17639 +--------+----+----+----+-------------+--------+--------+ 17640 0 8 12 16 20 32 40 47 17641 17642'RXF format: <insn> R1,R3,D2(X2,B2)' 17643 +--------+----+----+----+-------------+----+---+--------+ 17644 | OpCode | R3 | X2 | B2 | D2 | R1 |///| OpCode | 17645 +--------+----+----+----+-------------+----+---+--------+ 17646 0 8 12 16 20 32 36 40 47 17647 17648'RXY format: <insn> R1,D2(X2,B2)' 17649 +--------+----+----+----+-------------+--------+--------+ 17650 | OpCode | R1 | X2 | B2 | DL2 | DH2 | OpCode | 17651 +--------+----+----+----+-------------+--------+--------+ 17652 0 8 12 16 20 32 36 40 47 17653 17654'S format: <insn> D2(B2)' 17655 +------------------+----+-------------+ 17656 | OpCode | B2 | D2 | 17657 +------------------+----+-------------+ 17658 0 16 20 31 17659 17660'SI format: <insn> D1(B1),I2' 17661 +--------+---------+----+-------------+ 17662 | OpCode | I2 | B1 | D1 | 17663 +--------+---------+----+-------------+ 17664 0 8 16 20 31 17665 17666'SIY format: <insn> D1(B1),U2' 17667 +--------+---------+----+-------------+--------+--------+ 17668 | OpCode | I2 | B1 | DL1 | DH1 | OpCode | 17669 +--------+---------+----+-------------+--------+--------+ 17670 0 8 16 20 32 36 40 47 17671 17672'SIL format: <insn> D1(B1),I2' 17673 +------------------+----+-------------+-----------------+ 17674 | OpCode | B1 | D1 | I2 | 17675 +------------------+----+-------------+-----------------+ 17676 0 16 20 32 47 17677 17678'SS format: <insn> D1(R1,B1),D2(B3),R3' 17679 +--------+----+----+----+-------------+----+------------+ 17680 | OpCode | R1 | R3 | B1 | D1 | B2 | D2 | 17681 +--------+----+----+----+-------------+----+------------+ 17682 0 8 12 16 20 32 36 47 17683 17684'SSE format: <insn> D1(B1),D2(B2)' 17685 +------------------+----+-------------+----+------------+ 17686 | OpCode | B1 | D1 | B2 | D2 | 17687 +------------------+----+-------------+----+------------+ 17688 0 8 12 16 20 32 36 47 17689 17690'SSF format: <insn> D1(B1),D2(B2),R3' 17691 +--------+----+----+----+-------------+----+------------+ 17692 | OpCode | R3 |OpCd| B1 | D1 | B2 | D2 | 17693 +--------+----+----+----+-------------+----+------------+ 17694 0 8 12 16 20 32 36 47 17695 17696 For the complete list of all instruction format variants see the 17697Principles of Operation manuals. 17698 17699 17700File: as.info, Node: s390 Aliases, Next: s390 Operand Modifier, Prev: s390 Formats, Up: s390 Syntax 17701 177029.39.3.5 Instruction Aliases 17703............................ 17704 17705A specific bit pattern can have multiple mnemonics, for example the bit 17706pattern '0xa7000000' has the mnemonics 'tmh' and 'tmlh'. In addition, 17707there are a number of mnemonics recognized by 'as' that are not present 17708in the Principles of Operation. These are the short forms of the branch 17709instructions, where the condition code mask operand is encoded in the 17710mnemonic. This is relevant for the branch instructions, the compare and 17711branch instructions, and the compare and trap instructions. 17712 17713 For the branch instructions there are 20 condition code strings that 17714can be used as part of the mnemonic in place of a mask operand in the 17715instruction format: 17716 17717 instruction short form 17718 ---------------------------------------------- 17719 bcr M1,R2 b<m>r R2 17720 bc M1,D2(X2,B2) b<m> D2(X2,B2) 17721 brc M1,I2 j<m> I2 17722 brcl M1,I2 jg<m> I2 17723 17724 In the mnemonic for a branch instruction the condition code string 17725<m> can be any of the following: 17726 17727 o jump on overflow / if ones 17728 h jump on A high 17729 p jump on plus 17730 nle jump on not low or equal 17731 l jump on A low 17732 m jump on minus 17733 nhe jump on not high or equal 17734 lh jump on low or high 17735 ne jump on A not equal B 17736 nz jump on not zero / if not zeros 17737 e jump on A equal B 17738 z jump on zero / if zeroes 17739 nlh jump on not low or high 17740 he jump on high or equal 17741 nl jump on A not low 17742 nm jump on not minus / if not mixed 17743 le jump on low or equal 17744 nh jump on A not high 17745 np jump on not plus 17746 no jump on not overflow / if not ones 17747 17748 For the compare and branch, and compare and trap instructions there 17749are 12 condition code strings that can be used as part of the mnemonic 17750in place of a mask operand in the instruction format: 17751 17752 instruction short form 17753 ------------------------------------------------------------ 17754 crb R1,R2,M3,D4(B4) crb<m> R1,R2,D4(B4) 17755 cgrb R1,R2,M3,D4(B4) cgrb<m> R1,R2,D4(B4) 17756 crj R1,R2,M3,I4 crj<m> R1,R2,I4 17757 cgrj R1,R2,M3,I4 cgrj<m> R1,R2,I4 17758 cib R1,I2,M3,D4(B4) cib<m> R1,I2,D4(B4) 17759 cgib R1,I2,M3,D4(B4) cgib<m> R1,I2,D4(B4) 17760 cij R1,I2,M3,I4 cij<m> R1,I2,I4 17761 cgij R1,I2,M3,I4 cgij<m> R1,I2,I4 17762 crt R1,R2,M3 crt<m> R1,R2 17763 cgrt R1,R2,M3 cgrt<m> R1,R2 17764 cit R1,I2,M3 cit<m> R1,I2 17765 cgit R1,I2,M3 cgit<m> R1,I2 17766 clrb R1,R2,M3,D4(B4) clrb<m> R1,R2,D4(B4) 17767 clgrb R1,R2,M3,D4(B4) clgrb<m> R1,R2,D4(B4) 17768 clrj R1,R2,M3,I4 clrj<m> R1,R2,I4 17769 clgrj R1,R2,M3,I4 clgrj<m> R1,R2,I4 17770 clib R1,I2,M3,D4(B4) clib<m> R1,I2,D4(B4) 17771 clgib R1,I2,M3,D4(B4) clgib<m> R1,I2,D4(B4) 17772 clij R1,I2,M3,I4 clij<m> R1,I2,I4 17773 clgij R1,I2,M3,I4 clgij<m> R1,I2,I4 17774 clrt R1,R2,M3 clrt<m> R1,R2 17775 clgrt R1,R2,M3 clgrt<m> R1,R2 17776 clfit R1,I2,M3 clfit<m> R1,I2 17777 clgit R1,I2,M3 clgit<m> R1,I2 17778 17779 In the mnemonic for a compare and branch and compare and trap 17780instruction the condition code string <m> can be any of the following: 17781 17782 h jump on A high 17783 nle jump on not low or equal 17784 l jump on A low 17785 nhe jump on not high or equal 17786 ne jump on A not equal B 17787 lh jump on low or high 17788 e jump on A equal B 17789 nlh jump on not low or high 17790 nl jump on A not low 17791 he jump on high or equal 17792 nh jump on A not high 17793 le jump on low or equal 17794 17795 17796File: as.info, Node: s390 Operand Modifier, Next: s390 Instruction Marker, Prev: s390 Aliases, Up: s390 Syntax 17797 177989.39.3.6 Instruction Operand Modifier 17799..................................... 17800 17801If a symbol modifier is attached to a symbol in an expression for an 17802instruction operand field, the symbol term is replaced with a reference 17803to an object in the global offset table (GOT) or the procedure linkage 17804table (PLT). The following expressions are allowed: 'symbol@modifier + 17805constant', 'symbol@modifier + label + constant', and 'symbol@modifier - 17806label + constant'. The term 'symbol' is the symbol that will be entered 17807into the GOT or PLT, 'label' is a local label, and 'constant' is an 17808arbitrary expression that the assembler can evaluate to a constant 17809value. 17810 17811 The term '(symbol + constant1)@modifier +/- label + constant2' is 17812also accepted but a warning message is printed and the term is converted 17813to 'symbol@modifier +/- label + constant1 + constant2'. 17814 17815'@got' 17816'@got12' 17817 The @got modifier can be used for displacement fields, 16-bit 17818 immediate fields and 32-bit pc-relative immediate fields. The 17819 @got12 modifier is synonym to @got. The symbol is added to the 17820 GOT. For displacement fields and 16-bit immediate fields the symbol 17821 term is replaced with the offset from the start of the GOT to the 17822 GOT slot for the symbol. For a 32-bit pc-relative field the 17823 pc-relative offset to the GOT slot from the current instruction 17824 address is used. 17825'@gotent' 17826 The @gotent modifier can be used for 32-bit pc-relative immediate 17827 fields. The symbol is added to the GOT and the symbol term is 17828 replaced with the pc-relative offset from the current instruction 17829 to the GOT slot for the symbol. 17830'@gotoff' 17831 The @gotoff modifier can be used for 16-bit immediate fields. The 17832 symbol term is replaced with the offset from the start of the GOT 17833 to the address of the symbol. 17834'@gotplt' 17835 The @gotplt modifier can be used for displacement fields, 16-bit 17836 immediate fields, and 32-bit pc-relative immediate fields. A 17837 procedure linkage table entry is generated for the symbol and a 17838 jump slot for the symbol is added to the GOT. For displacement 17839 fields and 16-bit immediate fields the symbol term is replaced with 17840 the offset from the start of the GOT to the jump slot for the 17841 symbol. For a 32-bit pc-relative field the pc-relative offset to 17842 the jump slot from the current instruction address is used. 17843'@plt' 17844 The @plt modifier can be used for 16-bit and 32-bit pc-relative 17845 immediate fields. A procedure linkage table entry is generated for 17846 the symbol. The symbol term is replaced with the relative offset 17847 from the current instruction to the PLT entry for the symbol. 17848'@pltoff' 17849 The @pltoff modifier can be used for 16-bit immediate fields. The 17850 symbol term is replaced with the offset from the start of the PLT 17851 to the address of the symbol. 17852'@gotntpoff' 17853 The @gotntpoff modifier can be used for displacement fields. The 17854 symbol is added to the static TLS block and the negated offset to 17855 the symbol in the static TLS block is added to the GOT. The symbol 17856 term is replaced with the offset to the GOT slot from the start of 17857 the GOT. 17858'@indntpoff' 17859 The @indntpoff modifier can be used for 32-bit pc-relative 17860 immediate fields. The symbol is added to the static TLS block and 17861 the negated offset to the symbol in the static TLS block is added 17862 to the GOT. The symbol term is replaced with the pc-relative offset 17863 to the GOT slot from the current instruction address. 17864 17865 For more information about the thread local storage modifiers 17866'gotntpoff' and 'indntpoff' see the ELF extension documentation 'ELF 17867Handling For Thread-Local Storage'. 17868 17869 17870File: as.info, Node: s390 Instruction Marker, Next: s390 Literal Pool Entries, Prev: s390 Operand Modifier, Up: s390 Syntax 17871 178729.39.3.7 Instruction Marker 17873........................... 17874 17875The thread local storage instruction markers are used by the linker to 17876perform code optimization. 17877 17878':tls_load' 17879 The :tls_load marker is used to flag the load instruction in the 17880 initial exec TLS model that retrieves the offset from the thread 17881 pointer to a thread local storage variable from the GOT. 17882':tls_gdcall' 17883 The :tls_gdcall marker is used to flag the branch-and-save 17884 instruction to the __tls_get_offset function in the global dynamic 17885 TLS model. 17886':tls_ldcall' 17887 The :tls_ldcall marker is used to flag the branch-and-save 17888 instruction to the __tls_get_offset function in the local dynamic 17889 TLS model. 17890 17891 For more information about the thread local storage instruction 17892marker and the linker optimizations see the ELF extension documentation 17893'ELF Handling For Thread-Local Storage'. 17894 17895 17896File: as.info, Node: s390 Literal Pool Entries, Prev: s390 Instruction Marker, Up: s390 Syntax 17897 178989.39.3.8 Literal Pool Entries 17899............................. 17900 17901A literal pool is a collection of values. To access the values a 17902pointer to the literal pool is loaded to a register, the literal pool 17903register. Usually, register %r13 is used as the literal pool register 17904(*note s390 Register::). Literal pool entries are created by adding the 17905suffix :lit1, :lit2, :lit4, or :lit8 to the end of an expression for an 17906instruction operand. The expression is added to the literal pool and 17907the operand is replaced with the offset to the literal in the literal 17908pool. 17909 17910':lit1' 17911 The literal pool entry is created as an 8-bit value. An operand 17912 modifier must not be used for the original expression. 17913':lit2' 17914 The literal pool entry is created as a 16 bit value. The operand 17915 modifier @got may be used in the original expression. The term 17916 'x@got:lit2' will put the got offset for the global symbol x to the 17917 literal pool as 16 bit value. 17918':lit4' 17919 The literal pool entry is created as a 32-bit value. The operand 17920 modifier @got and @plt may be used in the original expression. The 17921 term 'x@got:lit4' will put the got offset for the global symbol x 17922 to the literal pool as a 32-bit value. The term 'x@plt:lit4' will 17923 put the plt offset for the global symbol x to the literal pool as a 17924 32-bit value. 17925':lit8' 17926 The literal pool entry is created as a 64-bit value. The operand 17927 modifier @got and @plt may be used in the original expression. The 17928 term 'x@got:lit8' will put the got offset for the global symbol x 17929 to the literal pool as a 64-bit value. The term 'x@plt:lit8' will 17930 put the plt offset for the global symbol x to the literal pool as a 17931 64-bit value. 17932 17933 The assembler directive '.ltorg' is used to emit all literal pool 17934entries to the current position. 17935 17936 17937File: as.info, Node: s390 Directives, Next: s390 Floating Point, Prev: s390 Syntax, Up: S/390-Dependent 17938 179399.39.4 Assembler Directives 17940--------------------------- 17941 17942'as' for s390 supports all of the standard ELF assembler directives as 17943outlined in the main part of this document. Some directives have been 17944extended and there are some additional directives, which are only 17945available for the s390 'as'. 17946 17947'.insn' 17948 This directive permits the numeric representation of an 17949 instructions and makes the assembler insert the operands according 17950 to one of the instructions formats for '.insn' (*note s390 17951 Formats::). For example, the instruction 'l %r1,24(%r15)' could be 17952 written as '.insn rx,0x58000000,%r1,24(%r15)'. 17953'.short' 17954'.long' 17955'.quad' 17956 This directive places one or more 16-bit (.short), 32-bit (.long), 17957 or 64-bit (.quad) values into the current section. If an ELF or 17958 TLS modifier is used only the following expressions are allowed: 17959 'symbol@modifier + constant', 'symbol@modifier + label + constant', 17960 and 'symbol@modifier - label + constant'. The following modifiers 17961 are available: 17962 '@got' 17963 '@got12' 17964 The @got modifier can be used for .short, .long and .quad. 17965 The @got12 modifier is synonym to @got. The symbol is added 17966 to the GOT. The symbol term is replaced with offset from the 17967 start of the GOT to the GOT slot for the symbol. 17968 '@gotoff' 17969 The @gotoff modifier can be used for .short, .long and .quad. 17970 The symbol term is replaced with the offset from the start of 17971 the GOT to the address of the symbol. 17972 '@gotplt' 17973 The @gotplt modifier can be used for .long and .quad. A 17974 procedure linkage table entry is generated for the symbol and 17975 a jump slot for the symbol is added to the GOT. The symbol 17976 term is replaced with the offset from the start of the GOT to 17977 the jump slot for the symbol. 17978 '@plt' 17979 The @plt modifier can be used for .long and .quad. A 17980 procedure linkage table entry us generated for the symbol. 17981 The symbol term is replaced with the address of the PLT entry 17982 for the symbol. 17983 '@pltoff' 17984 The @pltoff modifier can be used for .short, .long and .quad. 17985 The symbol term is replaced with the offset from the start of 17986 the PLT to the address of the symbol. 17987 '@tlsgd' 17988 '@tlsldm' 17989 The @tlsgd and @tlsldm modifier can be used for .long and 17990 .quad. A tls_index structure for the symbol is added to the 17991 GOT. The symbol term is replaced with the offset from the 17992 start of the GOT to the tls_index structure. 17993 '@gotntpoff' 17994 '@indntpoff' 17995 The @gotntpoff and @indntpoff modifier can be used for .long 17996 and .quad. The symbol is added to the static TLS block and 17997 the negated offset to the symbol in the static TLS block is 17998 added to the GOT. For @gotntpoff the symbol term is replaced 17999 with the offset from the start of the GOT to the GOT slot, for 18000 @indntpoff the symbol term is replaced with the address of the 18001 GOT slot. 18002 '@dtpoff' 18003 The @dtpoff modifier can be used for .long and .quad. The 18004 symbol term is replaced with the offset of the symbol relative 18005 to the start of the TLS block it is contained in. 18006 '@ntpoff' 18007 The @ntpoff modifier can be used for .long and .quad. The 18008 symbol term is replaced with the offset of the symbol relative 18009 to the TCB pointer. 18010 18011 For more information about the thread local storage modifiers see 18012 the ELF extension documentation 'ELF Handling For Thread-Local 18013 Storage'. 18014 18015'.ltorg' 18016 This directive causes the current contents of the literal pool to 18017 be dumped to the current location (*note s390 Literal Pool 18018 Entries::). 18019 18020'.machine STRING[+EXTENSION]...' 18021 18022 This directive allows changing the machine for which code is 18023 generated. 'string' may be any of the '-march=' selection options, 18024 or 'push', or 'pop'. '.machine push' saves the currently selected 18025 cpu, which may be restored with '.machine pop'. Be aware that the 18026 cpu string has to be put into double quotes in case it contains 18027 characters not appropriate for identifiers. So you have to write 18028 '"z9-109"' instead of just 'z9-109'. Extensions can be specified 18029 after the cpu name, separated by plus charaters. Valid extensions 18030 are: 'htm', 'nohtm', 'vx', 'novx'. They extend the basic 18031 instruction set with features from a higher cpu level, or remove 18032 support for a feature from the given cpu level. 18033 18034 Example: 'z13+nohtm' allows all instructions of the z13 cpu except 18035 instructions from the HTM facility. 18036 18037'.machinemode string' 18038 This directive allows to change the architecture mode for which 18039 code is being generated. 'string' may be 'esa', 'zarch', 18040 'zarch_nohighgprs', 'push', or 'pop'. '.machinemode 18041 zarch_nohighgprs' can be used to prevent the 'highgprs' flag from 18042 being set in the ELF header of the output file. This is useful in 18043 situations where the code is gated with a runtime check which makes 18044 sure that the code is only executed on kernels providing the 18045 'highgprs' feature. '.machinemode push' saves the currently 18046 selected mode, which may be restored with '.machinemode pop'. 18047 18048 18049File: as.info, Node: s390 Floating Point, Prev: s390 Directives, Up: S/390-Dependent 18050 180519.39.5 Floating Point 18052--------------------- 18053 18054The assembler recognizes both the IEEE floating-point instruction and 18055the hexadecimal floating-point instructions. The floating-point 18056constructors '.float', '.single', and '.double' always emit the IEEE 18057format. To assemble hexadecimal floating-point constants the '.long' 18058and '.quad' directives must be used. 18059 18060 18061File: as.info, Node: SCORE-Dependent, Next: SH-Dependent, Prev: S/390-Dependent, Up: Machine Dependencies 18062 180639.40 SCORE Dependent Features 18064============================= 18065 18066* Menu: 18067 18068* SCORE-Opts:: Assembler options 18069* SCORE-Pseudo:: SCORE Assembler Directives 18070* SCORE-Syntax:: Syntax 18071 18072 18073File: as.info, Node: SCORE-Opts, Next: SCORE-Pseudo, Up: SCORE-Dependent 18074 180759.40.1 Options 18076-------------- 18077 18078The following table lists all available SCORE options. 18079 18080'-G NUM' 18081 This option sets the largest size of an object that can be 18082 referenced implicitly with the 'gp' register. The default value is 18083 8. 18084 18085'-EB' 18086 Assemble code for a big-endian cpu 18087 18088'-EL' 18089 Assemble code for a little-endian cpu 18090 18091'-FIXDD' 18092 Assemble code for fix data dependency 18093 18094'-NWARN' 18095 Assemble code for no warning message for fix data dependency 18096 18097'-SCORE5' 18098 Assemble code for target is SCORE5 18099 18100'-SCORE5U' 18101 Assemble code for target is SCORE5U 18102 18103'-SCORE7' 18104 Assemble code for target is SCORE7, this is default setting 18105 18106'-SCORE3' 18107 Assemble code for target is SCORE3 18108 18109'-march=score7' 18110 Assemble code for target is SCORE7, this is default setting 18111 18112'-march=score3' 18113 Assemble code for target is SCORE3 18114 18115'-USE_R1' 18116 Assemble code for no warning message when using temp register r1 18117 18118'-KPIC' 18119 Generate code for PIC. This option tells the assembler to generate 18120 score position-independent macro expansions. It also tells the 18121 assembler to mark the output file as PIC. 18122 18123'-O0' 18124 Assembler will not perform any optimizations 18125 18126'-V' 18127 Sunplus release version 18128 18129 18130File: as.info, Node: SCORE-Pseudo, Next: SCORE-Syntax, Prev: SCORE-Opts, Up: SCORE-Dependent 18131 181329.40.2 SCORE Assembler Directives 18133--------------------------------- 18134 18135A number of assembler directives are available for SCORE. The following 18136table is far from complete. 18137 18138'.set nwarn' 18139 Let the assembler not to generate warnings if the source machine 18140 language instructions happen data dependency. 18141 18142'.set fixdd' 18143 Let the assembler to insert bubbles (32 bit nop instruction / 16 18144 bit nop! Instruction) if the source machine language instructions 18145 happen data dependency. 18146 18147'.set nofixdd' 18148 Let the assembler to generate warnings if the source machine 18149 language instructions happen data dependency. (Default) 18150 18151'.set r1' 18152 Let the assembler not to generate warnings if the source program 18153 uses r1. allow user to use r1 18154 18155'set nor1' 18156 Let the assembler to generate warnings if the source program uses 18157 r1. (Default) 18158 18159'.sdata' 18160 Tell the assembler to add subsequent data into the sdata section 18161 18162'.rdata' 18163 Tell the assembler to add subsequent data into the rdata section 18164 18165'.frame "frame-register", "offset", "return-pc-register"' 18166 Describe a stack frame. "frame-register" is the frame register, 18167 "offset" is the distance from the frame register to the virtual 18168 frame pointer, "return-pc-register" is the return program register. 18169 You must use ".ent" before ".frame" and only one ".frame" can be 18170 used per ".ent". 18171 18172'.mask "bitmask", "frameoffset"' 18173 Indicate which of the integer registers are saved in the current 18174 function's stack frame, this is for the debugger to explain the 18175 frame chain. 18176 18177'.ent "proc-name"' 18178 Set the beginning of the procedure "proc_name". Use this directive 18179 when you want to generate information for the debugger. 18180 18181'.end proc-name' 18182 Set the end of a procedure. Use this directive to generate 18183 information for the debugger. 18184 18185'.bss' 18186 Switch the destination of following statements into the bss 18187 section, which is used for data that is uninitialized anywhere. 18188 18189 18190File: as.info, Node: SCORE-Syntax, Prev: SCORE-Pseudo, Up: SCORE-Dependent 18191 181929.40.3 SCORE Syntax 18193------------------- 18194 18195* Menu: 18196 18197* SCORE-Chars:: Special Characters 18198 18199 18200File: as.info, Node: SCORE-Chars, Up: SCORE-Syntax 18201 182029.40.3.1 Special Characters 18203........................... 18204 18205The presence of a '#' appearing anywhere on a line indicates the start 18206of a comment that extends to the end of that line. 18207 18208 If a '#' appears as the first character of a line then the whole line 18209is treated as a comment, but in this case the line can also be a logical 18210line number directive (*note Comments::) or a preprocessor control 18211command (*note Preprocessing::). 18212 18213 The ';' character can be used to separate statements on the same 18214line. 18215 18216 18217File: as.info, Node: SH-Dependent, Next: SH64-Dependent, Prev: SCORE-Dependent, Up: Machine Dependencies 18218 182199.41 Renesas / SuperH SH Dependent Features 18220=========================================== 18221 18222* Menu: 18223 18224* SH Options:: Options 18225* SH Syntax:: Syntax 18226* SH Floating Point:: Floating Point 18227* SH Directives:: SH Machine Directives 18228* SH Opcodes:: Opcodes 18229 18230 18231File: as.info, Node: SH Options, Next: SH Syntax, Up: SH-Dependent 18232 182339.41.1 Options 18234-------------- 18235 18236'as' has following command-line options for the Renesas (formerly 18237Hitachi) / SuperH SH family. 18238 18239'--little' 18240 Generate little endian code. 18241 18242'--big' 18243 Generate big endian code. 18244 18245'--relax' 18246 Alter jump instructions for long displacements. 18247 18248'--small' 18249 Align sections to 4 byte boundaries, not 16. 18250 18251'--dsp' 18252 Enable sh-dsp insns, and disable sh3e / sh4 insns. 18253 18254'--renesas' 18255 Disable optimization with section symbol for compatibility with 18256 Renesas assembler. 18257 18258'--allow-reg-prefix' 18259 Allow '$' as a register name prefix. 18260 18261'--fdpic' 18262 Generate an FDPIC object file. 18263 18264'--isa=sh4 | sh4a' 18265 Specify the sh4 or sh4a instruction set. 18266'--isa=dsp' 18267 Enable sh-dsp insns, and disable sh3e / sh4 insns. 18268'--isa=fp' 18269 Enable sh2e, sh3e, sh4, and sh4a insn sets. 18270'--isa=all' 18271 Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets. 18272 18273'-h-tick-hex' 18274 Support H'00 style hex constants in addition to 0x00 style. 18275 18276 18277File: as.info, Node: SH Syntax, Next: SH Floating Point, Prev: SH Options, Up: SH-Dependent 18278 182799.41.2 Syntax 18280------------- 18281 18282* Menu: 18283 18284* SH-Chars:: Special Characters 18285* SH-Regs:: Register Names 18286* SH-Addressing:: Addressing Modes 18287 18288 18289File: as.info, Node: SH-Chars, Next: SH-Regs, Up: SH Syntax 18290 182919.41.2.1 Special Characters 18292........................... 18293 18294'!' is the line comment character. 18295 18296 You can use ';' instead of a newline to separate statements. 18297 18298 If a '#' appears as the first character of a line then the whole line 18299is treated as a comment, but in this case the line could also be a 18300logical line number directive (*note Comments::) or a preprocessor 18301control command (*note Preprocessing::). 18302 18303 Since '$' has no special meaning, you may use it in symbol names. 18304 18305 18306File: as.info, Node: SH-Regs, Next: SH-Addressing, Prev: SH-Chars, Up: SH Syntax 18307 183089.41.2.2 Register Names 18309....................... 18310 18311You can use the predefined symbols 'r0', 'r1', 'r2', 'r3', 'r4', 'r5', 18312'r6', 'r7', 'r8', 'r9', 'r10', 'r11', 'r12', 'r13', 'r14', and 'r15' to 18313refer to the SH registers. 18314 18315 The SH also has these control registers: 18316 18317'pr' 18318 procedure register (holds return address) 18319 18320'pc' 18321 program counter 18322 18323'mach' 18324'macl' 18325 high and low multiply accumulator registers 18326 18327'sr' 18328 status register 18329 18330'gbr' 18331 global base register 18332 18333'vbr' 18334 vector base register (for interrupt vectors) 18335 18336 18337File: as.info, Node: SH-Addressing, Prev: SH-Regs, Up: SH Syntax 18338 183399.41.2.3 Addressing Modes 18340......................... 18341 18342'as' understands the following addressing modes for the SH. 'RN' in the 18343following refers to any of the numbered registers, but _not_ the control 18344registers. 18345 18346'RN' 18347 Register direct 18348 18349'@RN' 18350 Register indirect 18351 18352'@-RN' 18353 Register indirect with pre-decrement 18354 18355'@RN+' 18356 Register indirect with post-increment 18357 18358'@(DISP, RN)' 18359 Register indirect with displacement 18360 18361'@(R0, RN)' 18362 Register indexed 18363 18364'@(DISP, GBR)' 18365 'GBR' offset 18366 18367'@(R0, GBR)' 18368 GBR indexed 18369 18370'ADDR' 18371'@(DISP, PC)' 18372 PC relative address (for branch or for addressing memory). The 18373 'as' implementation allows you to use the simpler form ADDR 18374 anywhere a PC relative address is called for; the alternate form is 18375 supported for compatibility with other assemblers. 18376 18377'#IMM' 18378 Immediate data 18379 18380 18381File: as.info, Node: SH Floating Point, Next: SH Directives, Prev: SH Syntax, Up: SH-Dependent 18382 183839.41.3 Floating Point 18384--------------------- 18385 18386SH2E, SH3E and SH4 groups have on-chip floating-point unit (FPU). Other 18387SH groups can use '.float' directive to generate IEEE floating-point 18388numbers. 18389 18390 SH2E and SH3E support single-precision floating point calculations as 18391well as entirely PCAPI compatible emulation of double-precision floating 18392point calculations. SH2E and SH3E instructions are a subset of the 18393floating point calculations conforming to the IEEE754 standard. 18394 18395 In addition to single-precision and double-precision floating-point 18396operation capability, the on-chip FPU of SH4 has a 128-bit graphic 18397engine that enables 32-bit floating-point data to be processed 128 bits 18398at a time. It also supports 4 * 4 array operations and inner product 18399operations. Also, a superscalar architecture is employed that enables 18400simultaneous execution of two instructions (including FPU instructions), 18401providing performance of up to twice that of conventional architectures 18402at the same frequency. 18403 18404 18405File: as.info, Node: SH Directives, Next: SH Opcodes, Prev: SH Floating Point, Up: SH-Dependent 18406 184079.41.4 SH Machine Directives 18408---------------------------- 18409 18410'uaword' 18411'ualong' 18412'uaquad' 18413 'as' will issue a warning when a misaligned '.word', '.long', or 18414 '.quad' directive is used. You may use '.uaword', '.ualong', or 18415 '.uaquad' to indicate that the value is intentionally misaligned. 18416 18417 18418File: as.info, Node: SH Opcodes, Prev: SH Directives, Up: SH-Dependent 18419 184209.41.5 Opcodes 18421-------------- 18422 18423For detailed information on the SH machine instruction set, see 18424'SH-Microcomputer User's Manual' (Renesas) or 'SH-4 32-bit CPU Core 18425Architecture' (SuperH) and 'SuperH (SH) 64-Bit RISC Series' (SuperH). 18426 18427 'as' implements all the standard SH opcodes. No additional 18428pseudo-instructions are needed on this family. Note, however, that 18429because 'as' supports a simpler form of PC-relative addressing, you may 18430simply write (for example) 18431 18432 mov.l bar,r0 18433 18434where other assemblers might require an explicit displacement to 'bar' 18435from the program counter: 18436 18437 mov.l @(DISP, PC) 18438 18439 Here is a summary of SH opcodes: 18440 18441 Legend: 18442 Rn a numbered register 18443 Rm another numbered register 18444 #imm immediate data 18445 disp displacement 18446 disp8 8-bit displacement 18447 disp12 12-bit displacement 18448 18449 add #imm,Rn lds.l @Rn+,PR 18450 add Rm,Rn mac.w @Rm+,@Rn+ 18451 addc Rm,Rn mov #imm,Rn 18452 addv Rm,Rn mov Rm,Rn 18453 and #imm,R0 mov.b Rm,@(R0,Rn) 18454 and Rm,Rn mov.b Rm,@-Rn 18455 and.b #imm,@(R0,GBR) mov.b Rm,@Rn 18456 bf disp8 mov.b @(disp,Rm),R0 18457 bra disp12 mov.b @(disp,GBR),R0 18458 bsr disp12 mov.b @(R0,Rm),Rn 18459 bt disp8 mov.b @Rm+,Rn 18460 clrmac mov.b @Rm,Rn 18461 clrt mov.b R0,@(disp,Rm) 18462 cmp/eq #imm,R0 mov.b R0,@(disp,GBR) 18463 cmp/eq Rm,Rn mov.l Rm,@(disp,Rn) 18464 cmp/ge Rm,Rn mov.l Rm,@(R0,Rn) 18465 cmp/gt Rm,Rn mov.l Rm,@-Rn 18466 cmp/hi Rm,Rn mov.l Rm,@Rn 18467 cmp/hs Rm,Rn mov.l @(disp,Rn),Rm 18468 cmp/pl Rn mov.l @(disp,GBR),R0 18469 cmp/pz Rn mov.l @(disp,PC),Rn 18470 cmp/str Rm,Rn mov.l @(R0,Rm),Rn 18471 div0s Rm,Rn mov.l @Rm+,Rn 18472 div0u mov.l @Rm,Rn 18473 div1 Rm,Rn mov.l R0,@(disp,GBR) 18474 exts.b Rm,Rn mov.w Rm,@(R0,Rn) 18475 exts.w Rm,Rn mov.w Rm,@-Rn 18476 extu.b Rm,Rn mov.w Rm,@Rn 18477 extu.w Rm,Rn mov.w @(disp,Rm),R0 18478 jmp @Rn mov.w @(disp,GBR),R0 18479 jsr @Rn mov.w @(disp,PC),Rn 18480 ldc Rn,GBR mov.w @(R0,Rm),Rn 18481 ldc Rn,SR mov.w @Rm+,Rn 18482 ldc Rn,VBR mov.w @Rm,Rn 18483 ldc.l @Rn+,GBR mov.w R0,@(disp,Rm) 18484 ldc.l @Rn+,SR mov.w R0,@(disp,GBR) 18485 ldc.l @Rn+,VBR mova @(disp,PC),R0 18486 lds Rn,MACH movt Rn 18487 lds Rn,MACL muls Rm,Rn 18488 lds Rn,PR mulu Rm,Rn 18489 lds.l @Rn+,MACH neg Rm,Rn 18490 lds.l @Rn+,MACL negc Rm,Rn 18491 nop stc VBR,Rn 18492 not Rm,Rn stc.l GBR,@-Rn 18493 or #imm,R0 stc.l SR,@-Rn 18494 or Rm,Rn stc.l VBR,@-Rn 18495 or.b #imm,@(R0,GBR) sts MACH,Rn 18496 rotcl Rn sts MACL,Rn 18497 rotcr Rn sts PR,Rn 18498 rotl Rn sts.l MACH,@-Rn 18499 rotr Rn sts.l MACL,@-Rn 18500 rte sts.l PR,@-Rn 18501 rts sub Rm,Rn 18502 sett subc Rm,Rn 18503 shal Rn subv Rm,Rn 18504 shar Rn swap.b Rm,Rn 18505 shll Rn swap.w Rm,Rn 18506 shll16 Rn tas.b @Rn 18507 shll2 Rn trapa #imm 18508 shll8 Rn tst #imm,R0 18509 shlr Rn tst Rm,Rn 18510 shlr16 Rn tst.b #imm,@(R0,GBR) 18511 shlr2 Rn xor #imm,R0 18512 shlr8 Rn xor Rm,Rn 18513 sleep xor.b #imm,@(R0,GBR) 18514 stc GBR,Rn xtrct Rm,Rn 18515 stc SR,Rn 18516 18517 18518File: as.info, Node: SH64-Dependent, Next: Sparc-Dependent, Prev: SH-Dependent, Up: Machine Dependencies 18519 185209.42 SuperH SH64 Dependent Features 18521=================================== 18522 18523* Menu: 18524 18525* SH64 Options:: Options 18526* SH64 Syntax:: Syntax 18527* SH64 Directives:: SH64 Machine Directives 18528* SH64 Opcodes:: Opcodes 18529 18530 18531File: as.info, Node: SH64 Options, Next: SH64 Syntax, Up: SH64-Dependent 18532 185339.42.1 Options 18534-------------- 18535 18536'-isa=sh4 | sh4a' 18537 Specify the sh4 or sh4a instruction set. 18538'-isa=dsp' 18539 Enable sh-dsp insns, and disable sh3e / sh4 insns. 18540'-isa=fp' 18541 Enable sh2e, sh3e, sh4, and sh4a insn sets. 18542'-isa=all' 18543 Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets. 18544'-isa=shmedia | -isa=shcompact' 18545 Specify the default instruction set. 'SHmedia' specifies the 18546 32-bit opcodes, and 'SHcompact' specifies the 16-bit opcodes 18547 compatible with previous SH families. The default depends on the 18548 ABI selected; the default for the 64-bit ABI is SHmedia, and the 18549 default for the 32-bit ABI is SHcompact. If neither the ABI nor 18550 the ISA is specified, the default is 32-bit SHcompact. 18551 18552 Note that the '.mode' pseudo-op is not permitted if the ISA is not 18553 specified on the command line. 18554 18555'-abi=32 | -abi=64' 18556 Specify the default ABI. If the ISA is specified and the ABI is 18557 not, the default ABI depends on the ISA, with SHmedia defaulting to 18558 64-bit and SHcompact defaulting to 32-bit. 18559 18560 Note that the '.abi' pseudo-op is not permitted if the ABI is not 18561 specified on the command line. When the ABI is specified on the 18562 command line, any '.abi' pseudo-ops in the source must match it. 18563 18564'-shcompact-const-crange' 18565 Emit code-range descriptors for constants in SHcompact code 18566 sections. 18567 18568'-no-mix' 18569 Disallow SHmedia code in the same section as constants and 18570 SHcompact code. 18571 18572'-no-expand' 18573 Do not expand MOVI, PT, PTA or PTB instructions. 18574 18575'-expand-pt32' 18576 With -abi=64, expand PT, PTA and PTB instructions to 32 bits only. 18577 18578'-h-tick-hex' 18579 Support H'00 style hex constants in addition to 0x00 style. 18580 18581 18582File: as.info, Node: SH64 Syntax, Next: SH64 Directives, Prev: SH64 Options, Up: SH64-Dependent 18583 185849.42.2 Syntax 18585------------- 18586 18587* Menu: 18588 18589* SH64-Chars:: Special Characters 18590* SH64-Regs:: Register Names 18591* SH64-Addressing:: Addressing Modes 18592 18593 18594File: as.info, Node: SH64-Chars, Next: SH64-Regs, Up: SH64 Syntax 18595 185969.42.2.1 Special Characters 18597........................... 18598 18599'!' is the line comment character. 18600 18601 If a '#' appears as the first character of a line then the whole line 18602is treated as a comment, but in this case the line could also be a 18603logical line number directive (*note Comments::) or a preprocessor 18604control command (*note Preprocessing::). 18605 18606 You can use ';' instead of a newline to separate statements. 18607 18608 Since '$' has no special meaning, you may use it in symbol names. 18609 18610 18611File: as.info, Node: SH64-Regs, Next: SH64-Addressing, Prev: SH64-Chars, Up: SH64 Syntax 18612 186139.42.2.2 Register Names 18614....................... 18615 18616You can use the predefined symbols 'r0' through 'r63' to refer to the 18617SH64 general registers, 'cr0' through 'cr63' for control registers, 18618'tr0' through 'tr7' for target address registers, 'fr0' through 'fr63' 18619for single-precision floating point registers, 'dr0' through 'dr62' 18620(even numbered registers only) for double-precision floating point 18621registers, 'fv0' through 'fv60' (multiples of four only) for 18622single-precision floating point vectors, 'fp0' through 'fp62' (even 18623numbered registers only) for single-precision floating point pairs, 18624'mtrx0' through 'mtrx48' (multiples of 16 only) for 4x4 matrices of 18625single-precision floating point registers, 'pc' for the program counter, 18626and 'fpscr' for the floating point status and control register. 18627 18628 You can also refer to the control registers by the mnemonics 'sr', 18629'ssr', 'pssr', 'intevt', 'expevt', 'pexpevt', 'tra', 'spc', 'pspc', 18630'resvec', 'vbr', 'tea', 'dcr', 'kcr0', 'kcr1', 'ctc', and 'usr'. 18631 18632 18633File: as.info, Node: SH64-Addressing, Prev: SH64-Regs, Up: SH64 Syntax 18634 186359.42.2.3 Addressing Modes 18636......................... 18637 18638SH64 operands consist of either a register or immediate value. The 18639immediate value can be a constant or label reference (or portion of a 18640label reference), as in this example: 18641 18642 movi 4,r2 18643 pt function, tr4 18644 movi (function >> 16) & 65535,r0 18645 shori function & 65535, r0 18646 ld.l r0,4,r0 18647 18648 Instruction label references can reference labels in either SHmedia 18649or SHcompact. To differentiate between the two, labels in SHmedia 18650sections will always have the least significant bit set (i.e. they will 18651be odd), which SHcompact labels will have the least significant bit 18652reset (i.e. they will be even). If you need to reference the actual 18653address of a label, you can use the 'datalabel' modifier, as in this 18654example: 18655 18656 .long function 18657 .long datalabel function 18658 18659 In that example, the first longword may or may not have the least 18660significant bit set depending on whether the label is an SHmedia label 18661or an SHcompact label. The second longword will be the actual address 18662of the label, regardless of what type of label it is. 18663 18664 18665File: as.info, Node: SH64 Directives, Next: SH64 Opcodes, Prev: SH64 Syntax, Up: SH64-Dependent 18666 186679.42.3 SH64 Machine Directives 18668------------------------------ 18669 18670In addition to the SH directives, the SH64 provides the following 18671directives: 18672 18673'.mode [shmedia|shcompact]' 18674'.isa [shmedia|shcompact]' 18675 Specify the ISA for the following instructions (the two directives 18676 are equivalent). Note that programs such as 'objdump' rely on 18677 symbolic labels to determine when such mode switches occur (by 18678 checking the least significant bit of the label's address), so such 18679 mode/isa changes should always be followed by a label (in practice, 18680 this is true anyway). Note that you cannot use these directives if 18681 you didn't specify an ISA on the command line. 18682 18683'.abi [32|64]' 18684 Specify the ABI for the following instructions. Note that you 18685 cannot use this directive unless you specified an ABI on the 18686 command line, and the ABIs specified must match. 18687 18688 18689File: as.info, Node: SH64 Opcodes, Prev: SH64 Directives, Up: SH64-Dependent 18690 186919.42.4 Opcodes 18692-------------- 18693 18694For detailed information on the SH64 machine instruction set, see 18695'SuperH 64 bit RISC Series Architecture Manual' (SuperH, Inc.). 18696 18697 'as' implements all the standard SH64 opcodes. In addition, the 18698following pseudo-opcodes may be expanded into one or more alternate 18699opcodes: 18700 18701'movi' 18702 If the value doesn't fit into a standard 'movi' opcode, 'as' will 18703 replace the 'movi' with a sequence of 'movi' and 'shori' opcodes. 18704 18705'pt' 18706 This expands to a sequence of 'movi' and 'shori' opcode, followed 18707 by a 'ptrel' opcode, or to a 'pta' or 'ptb' opcode, depending on 18708 the label referenced. 18709 18710 18711File: as.info, Node: Sparc-Dependent, Next: TIC54X-Dependent, Prev: SH64-Dependent, Up: Machine Dependencies 18712 187139.43 SPARC Dependent Features 18714============================= 18715 18716* Menu: 18717 18718* Sparc-Opts:: Options 18719* Sparc-Aligned-Data:: Option to enforce aligned data 18720* Sparc-Syntax:: Syntax 18721* Sparc-Float:: Floating Point 18722* Sparc-Directives:: Sparc Machine Directives 18723 18724 18725File: as.info, Node: Sparc-Opts, Next: Sparc-Aligned-Data, Up: Sparc-Dependent 18726 187279.43.1 Options 18728-------------- 18729 18730The SPARC chip family includes several successive versions, using the 18731same core instruction set, but including a few additional instructions 18732at each version. There are exceptions to this however. For details on 18733what instructions each variant supports, please see the chip's 18734architecture reference manual. 18735 18736 By default, 'as' assumes the core instruction set (SPARC v6), but 18737"bumps" the architecture level as needed: it switches to successively 18738higher architectures as it encounters instructions that only exist in 18739the higher levels. 18740 18741 If not configured for SPARC v9 ('sparc64-*-*') GAS will not bump past 18742sparclite by default, an option must be passed to enable the v9 18743instructions. 18744 18745 GAS treats sparclite as being compatible with v8, unless an 18746architecture is explicitly requested. SPARC v9 is always incompatible 18747with sparclite. 18748 18749'-Av6 | -Av7 | -Av8 | -Aleon | -Asparclet | -Asparclite' 18750'-Av8plus | -Av8plusa | -Av8plusb | -Av8plusc | -Av8plusd | -Av8plusv | -Av8plusm' 18751'-Av9 | -Av9a | -Av9b | -Av9c | -Av9d | -Av9e | -Av9v | -Av9m' 18752'-Asparc | -Asparcvis | -Asparcvis2 | -Asparcfmaf | -Asparcima' 18753'-Asparcvis3 | -Asparcvis3r | -Asparc5' 18754 Use one of the '-A' options to select one of the SPARC 18755 architectures explicitly. If you select an architecture 18756 explicitly, 'as' reports a fatal error if it encounters an 18757 instruction or feature requiring an incompatible or higher level. 18758 18759 '-Av8plus', '-Av8plusa', '-Av8plusb', '-Av8plusc', '-Av8plusd', and 18760 '-Av8plusv' select a 32 bit environment. 18761 18762 '-Av9', '-Av9a', '-Av9b', '-Av9c', '-Av9d', '-Av9e', '-Av9v' and 18763 '-Av9m' select a 64 bit environment and are not available unless 18764 GAS is explicitly configured with 64 bit environment support. 18765 18766 '-Av8plusa' and '-Av9a' enable the SPARC V9 instruction set with 18767 UltraSPARC VIS 1.0 extensions. 18768 18769 '-Av8plusb' and '-Av9b' enable the UltraSPARC VIS 2.0 instructions, 18770 as well as the instructions enabled by '-Av8plusa' and '-Av9a'. 18771 18772 '-Av8plusc' and '-Av9c' enable the UltraSPARC Niagara instructions, 18773 as well as the instructions enabled by '-Av8plusb' and '-Av9b'. 18774 18775 '-Av8plusd' and '-Av9d' enable the floating point fused 18776 multiply-add, VIS 3.0, and HPC extension instructions, as well as 18777 the instructions enabled by '-Av8plusc' and '-Av9c'. 18778 18779 '-Av8pluse' and '-Av9e' enable the cryptographic instructions, as 18780 well as the instructions enabled by '-Av8plusd' and '-Av9d'. 18781 18782 '-Av8plusv' and '-Av9v' enable floating point unfused multiply-add, 18783 and integer multiply-add, as well as the instructions enabled by 18784 '-Av8pluse' and '-Av9e'. 18785 18786 '-Av8plusm' and '-Av9m' enable the VIS 4.0, subtract extended, 18787 xmpmul, xmontmul and xmontsqr instructions, as well as the 18788 instructions enabled by '-Av8plusv' and '-Av9v'. 18789 18790 '-Asparc' specifies a v9 environment. It is equivalent to '-Av9' 18791 if the word size is 64-bit, and '-Av8plus' otherwise. 18792 18793 '-Asparcvis' specifies a v9a environment. It is equivalent to 18794 '-Av9a' if the word size is 64-bit, and '-Av8plusa' otherwise. 18795 18796 '-Asparcvis2' specifies a v9b environment. It is equivalent to 18797 '-Av9b' if the word size is 64-bit, and '-Av8plusb' otherwise. 18798 18799 '-Asparcfmaf' specifies a v9b environment with the floating point 18800 fused multiply-add instructions enabled. 18801 18802 '-Asparcima' specifies a v9b environment with the integer 18803 multiply-add instructions enabled. 18804 18805 '-Asparcvis3' specifies a v9b environment with the VIS 3.0, HPC , 18806 and floating point fused multiply-add instructions enabled. 18807 18808 '-Asparcvis3r' specifies a v9b environment with the VIS 3.0, HPC, 18809 and floating point unfused multiply-add instructions enabled. 18810 18811 '-Asparc5' is equivalent to '-Av9m'. 18812 18813'-xarch=v8plus | -xarch=v8plusa | -xarch=v8plusb | -xarch=v8plusc' 18814'-xarch=v8plusd | -xarch=v8plusv | -xarch=v8plusm | -xarch=v9 | -xarch=v9a' 18815'-xarch=v9b | -xarch=v9c | -xarch=v9d | -xarch=v9e | -xarch=v9v | -xarch=v9m' 18816'-xarch=sparc | -xarch=sparcvis | -xarch=sparcvis2' 18817'-xarch=sparcfmaf | -xarch=sparcima | -xarch=sparcvis3' 18818'-xarch=sparcvis3r | -xarch=sparc5' 18819 For compatibility with the SunOS v9 assembler. These options are 18820 equivalent to -Av8plus, -Av8plusa, -Av8plusb, -Av8plusc, -Av8plusd, 18821 -Av8plusv, -Av8plusm, -Av9, -Av9a, -Av9b, -Av9c, -Av9d, -Av9e, 18822 -Av9v, -Av9m, -Asparc, -Asparcvis, -Asparcvis2, -Asparcfmaf, 18823 -Asparcima, -Asparcvis3, and -Asparcvis3r, respectively. 18824 18825'-bump' 18826 Warn whenever it is necessary to switch to another level. If an 18827 architecture level is explicitly requested, GAS will not issue 18828 warnings until that level is reached, and will then bump the level 18829 as required (except between incompatible levels). 18830 18831'-32 | -64' 18832 Select the word size, either 32 bits or 64 bits. These options are 18833 only available with the ELF object file format, and require that 18834 the necessary BFD support has been included. 18835 18836'--dcti-couples-detect' 18837 Warn if a DCTI (delayed control transfer instruction) couple is 18838 found when generating code for a variant of the SPARC architecture 18839 in which the execution of the couple is unpredictable, or very 18840 slow. This is disabled by default. 18841 18842 18843File: as.info, Node: Sparc-Aligned-Data, Next: Sparc-Syntax, Prev: Sparc-Opts, Up: Sparc-Dependent 18844 188459.43.2 Enforcing aligned data 18846----------------------------- 18847 18848SPARC GAS normally permits data to be misaligned. For example, it 18849permits the '.long' pseudo-op to be used on a byte boundary. However, 18850the native SunOS assemblers issue an error when they see misaligned 18851data. 18852 18853 You can use the '--enforce-aligned-data' option to make SPARC GAS 18854also issue an error about misaligned data, just as the SunOS assemblers 18855do. 18856 18857 The '--enforce-aligned-data' option is not the default because gcc 18858issues misaligned data pseudo-ops when it initializes certain packed 18859data structures (structures defined using the 'packed' attribute). You 18860may have to assemble with GAS in order to initialize packed data 18861structures in your own code. 18862 18863 18864File: as.info, Node: Sparc-Syntax, Next: Sparc-Float, Prev: Sparc-Aligned-Data, Up: Sparc-Dependent 18865 188669.43.3 Sparc Syntax 18867------------------- 18868 18869The assembler syntax closely follows The Sparc Architecture Manual, 18870versions 8 and 9, as well as most extensions defined by Sun for their 18871UltraSPARC and Niagara line of processors. 18872 18873* Menu: 18874 18875* Sparc-Chars:: Special Characters 18876* Sparc-Regs:: Register Names 18877* Sparc-Constants:: Constant Names 18878* Sparc-Relocs:: Relocations 18879* Sparc-Size-Translations:: Size Translations 18880 18881 18882File: as.info, Node: Sparc-Chars, Next: Sparc-Regs, Up: Sparc-Syntax 18883 188849.43.3.1 Special Characters 18885........................... 18886 18887A '!' character appearing anywhere on a line indicates the start of a 18888comment that extends to the end of that line. 18889 18890 If a '#' appears as the first character of a line then the whole line 18891is treated as a comment, but in this case the line could also be a 18892logical line number directive (*note Comments::) or a preprocessor 18893control command (*note Preprocessing::). 18894 18895 ';' can be used instead of a newline to separate statements. 18896 18897 18898File: as.info, Node: Sparc-Regs, Next: Sparc-Constants, Prev: Sparc-Chars, Up: Sparc-Syntax 18899 189009.43.3.2 Register Names 18901....................... 18902 18903The Sparc integer register file is broken down into global, outgoing, 18904local, and incoming. 18905 18906 * The 8 global registers are referred to as '%gN'. 18907 18908 * The 8 outgoing registers are referred to as '%oN'. 18909 18910 * The 8 local registers are referred to as '%lN'. 18911 18912 * The 8 incoming registers are referred to as '%iN'. 18913 18914 * The frame pointer register '%i6' can be referenced using the alias 18915 '%fp'. 18916 18917 * The stack pointer register '%o6' can be referenced using the alias 18918 '%sp'. 18919 18920 Floating point registers are simply referred to as '%fN'. When 18921assembling for pre-V9, only 32 floating point registers are available. 18922For V9 and later there are 64, but there are restrictions when 18923referencing the upper 32 registers. They can only be accessed as double 18924or quad, and thus only even or quad numbered accesses are allowed. For 18925example, '%f34' is a legal floating point register, but '%f35' is not. 18926 18927 Floating point registers accessed as double can also be referred 18928using the '%dN' notation, where N is even. Similarly, floating point 18929registers accessed as quad can be referred using the '%qN' notation, 18930where N is a multiple of 4. For example, '%f4' can be denoted as both 18931'%d4' and '%q4'. On the other hand, '%f2' can be denoted as '%d2' but 18932not as '%q2'. 18933 18934 Certain V9 instructions allow access to ancillary state registers. 18935Most simply they can be referred to as '%asrN' where N can be from 16 to 1893631. However, there are some aliases defined to reference ASR registers 18937defined for various UltraSPARC processors: 18938 18939 * The tick compare register is referred to as '%tick_cmpr'. 18940 18941 * The system tick register is referred to as '%stick'. An alias, 18942 '%sys_tick', exists but is deprecated and should not be used by new 18943 software. 18944 18945 * The system tick compare register is referred to as '%stick_cmpr'. 18946 An alias, '%sys_tick_cmpr', exists but is deprecated and should not 18947 be used by new software. 18948 18949 * The software interrupt register is referred to as '%softint'. 18950 18951 * The set software interrupt register is referred to as 18952 '%set_softint'. The mnemonic '%softint_set' is provided as an 18953 alias. 18954 18955 * The clear software interrupt register is referred to as 18956 '%clear_softint'. The mnemonic '%softint_clear' is provided as an 18957 alias. 18958 18959 * The performance instrumentation counters register is referred to as 18960 '%pic'. 18961 18962 * The performance control register is referred to as '%pcr'. 18963 18964 * The graphics status register is referred to as '%gsr'. 18965 18966 * The V9 dispatch control register is referred to as '%dcr'. 18967 18968 Various V9 branch and conditional move instructions allow 18969specification of which set of integer condition codes to test. These 18970are referred to as '%xcc' and '%icc'. 18971 18972 Additionally, GAS supports the so-called "natural" condition codes; 18973these are referred to as '%ncc' and reference to '%icc' if the word size 18974is 32, '%xcc' if the word size is 64. 18975 18976 In V9, there are 4 sets of floating point condition codes which are 18977referred to as '%fccN'. 18978 18979 Several special privileged and non-privileged registers exist: 18980 18981 * The V9 address space identifier register is referred to as '%asi'. 18982 18983 * The V9 restorable windows register is referred to as '%canrestore'. 18984 18985 * The V9 savable windows register is referred to as '%cansave'. 18986 18987 * The V9 clean windows register is referred to as '%cleanwin'. 18988 18989 * The V9 current window pointer register is referred to as '%cwp'. 18990 18991 * The floating-point queue register is referred to as '%fq'. 18992 18993 * The V8 co-processor queue register is referred to as '%cq'. 18994 18995 * The floating point status register is referred to as '%fsr'. 18996 18997 * The other windows register is referred to as '%otherwin'. 18998 18999 * The V9 program counter register is referred to as '%pc'. 19000 19001 * The V9 next program counter register is referred to as '%npc'. 19002 19003 * The V9 processor interrupt level register is referred to as '%pil'. 19004 19005 * The V9 processor state register is referred to as '%pstate'. 19006 19007 * The trap base address register is referred to as '%tba'. 19008 19009 * The V9 tick register is referred to as '%tick'. 19010 19011 * The V9 trap level is referred to as '%tl'. 19012 19013 * The V9 trap program counter is referred to as '%tpc'. 19014 19015 * The V9 trap next program counter is referred to as '%tnpc'. 19016 19017 * The V9 trap state is referred to as '%tstate'. 19018 19019 * The V9 trap type is referred to as '%tt'. 19020 19021 * The V9 condition codes is referred to as '%ccr'. 19022 19023 * The V9 floating-point registers state is referred to as '%fprs'. 19024 19025 * The V9 version register is referred to as '%ver'. 19026 19027 * The V9 window state register is referred to as '%wstate'. 19028 19029 * The Y register is referred to as '%y'. 19030 19031 * The V8 window invalid mask register is referred to as '%wim'. 19032 19033 * The V8 processor state register is referred to as '%psr'. 19034 19035 * The V9 global register level register is referred to as '%gl'. 19036 19037 Several special register names exist for hypervisor mode code: 19038 19039 * The hyperprivileged processor state register is referred to as 19040 '%hpstate'. 19041 19042 * The hyperprivileged trap state register is referred to as 19043 '%htstate'. 19044 19045 * The hyperprivileged interrupt pending register is referred to as 19046 '%hintp'. 19047 19048 * The hyperprivileged trap base address register is referred to as 19049 '%htba'. 19050 19051 * The hyperprivileged implementation version register is referred to 19052 as '%hver'. 19053 19054 * The hyperprivileged system tick offset register is referred to as 19055 '%hstick_offset'. Note that there is no '%hstick' register, the 19056 normal '%stick' is used. 19057 19058 * The hyperprivileged system tick enable register is referred to as 19059 '%hstick_enable'. 19060 19061 * The hyperprivileged system tick compare register is referred to as 19062 '%hstick_cmpr'. 19063 19064 19065File: as.info, Node: Sparc-Constants, Next: Sparc-Relocs, Prev: Sparc-Regs, Up: Sparc-Syntax 19066 190679.43.3.3 Constants 19068.................. 19069 19070Several Sparc instructions take an immediate operand field for which 19071mnemonic names exist. Two such examples are 'membar' and 'prefetch'. 19072Another example are the set of V9 memory access instruction that allow 19073specification of an address space identifier. 19074 19075 The 'membar' instruction specifies a memory barrier that is the 19076defined by the operand which is a bitmask. The supported mask mnemonics 19077are: 19078 19079 * '#Sync' requests that all operations (including nonmemory reference 19080 operations) appearing prior to the 'membar' must have been 19081 performed and the effects of any exceptions become visible before 19082 any instructions after the 'membar' may be initiated. This 19083 corresponds to 'membar' cmask field bit 2. 19084 19085 * '#MemIssue' requests that all memory reference operations appearing 19086 prior to the 'membar' must have been performed before any memory 19087 operation after the 'membar' may be initiated. This corresponds to 19088 'membar' cmask field bit 1. 19089 19090 * '#Lookaside' requests that a store appearing prior to the 'membar' 19091 must complete before any load following the 'membar' referencing 19092 the same address can be initiated. This corresponds to 'membar' 19093 cmask field bit 0. 19094 19095 * '#StoreStore' defines that the effects of all stores appearing 19096 prior to the 'membar' instruction must be visible to all processors 19097 before the effect of any stores following the 'membar'. Equivalent 19098 to the deprecated 'stbar' instruction. This corresponds to 19099 'membar' mmask field bit 3. 19100 19101 * '#LoadStore' defines all loads appearing prior to the 'membar' 19102 instruction must have been performed before the effect of any 19103 stores following the 'membar' is visible to any other processor. 19104 This corresponds to 'membar' mmask field bit 2. 19105 19106 * '#StoreLoad' defines that the effects of all stores appearing prior 19107 to the 'membar' instruction must be visible to all processors 19108 before loads following the 'membar' may be performed. This 19109 corresponds to 'membar' mmask field bit 1. 19110 19111 * '#LoadLoad' defines that all loads appearing prior to the 'membar' 19112 instruction must have been performed before any loads following the 19113 'membar' may be performed. This corresponds to 'membar' mmask 19114 field bit 0. 19115 19116 These values can be ored together, for example: 19117 19118 membar #Sync 19119 membar #StoreLoad | #LoadLoad 19120 membar #StoreLoad | #StoreStore 19121 19122 The 'prefetch' and 'prefetcha' instructions take a prefetch function 19123code. The following prefetch function code constant mnemonics are 19124available: 19125 19126 * '#n_reads' requests a prefetch for several reads, and corresponds 19127 to a prefetch function code of 0. 19128 19129 '#one_read' requests a prefetch for one read, and corresponds to a 19130 prefetch function code of 1. 19131 19132 '#n_writes' requests a prefetch for several writes (and possibly 19133 reads), and corresponds to a prefetch function code of 2. 19134 19135 '#one_write' requests a prefetch for one write, and corresponds to 19136 a prefetch function code of 3. 19137 19138 '#page' requests a prefetch page, and corresponds to a prefetch 19139 function code of 4. 19140 19141 '#invalidate' requests a prefetch invalidate, and corresponds to a 19142 prefetch function code of 16. 19143 19144 '#unified' requests a prefetch to the nearest unified cache, and 19145 corresponds to a prefetch function code of 17. 19146 19147 '#n_reads_strong' requests a strong prefetch for several reads, and 19148 corresponds to a prefetch function code of 20. 19149 19150 '#one_read_strong' requests a strong prefetch for one read, and 19151 corresponds to a prefetch function code of 21. 19152 19153 '#n_writes_strong' requests a strong prefetch for several writes, 19154 and corresponds to a prefetch function code of 22. 19155 19156 '#one_write_strong' requests a strong prefetch for one write, and 19157 corresponds to a prefetch function code of 23. 19158 19159 Onle one prefetch code may be specified. Here are some examples: 19160 19161 prefetch [%l0 + %l2], #one_read 19162 prefetch [%g2 + 8], #n_writes 19163 prefetcha [%g1] 0x8, #unified 19164 prefetcha [%o0 + 0x10] %asi, #n_reads 19165 19166 The actual behavior of a given prefetch function code is processor 19167 specific. If a processor does not implement a given prefetch 19168 function code, it will treat the prefetch instruction as a nop. 19169 19170 For instructions that accept an immediate address space identifier, 19171 'as' provides many mnemonics corresponding to V9 defined as well as 19172 UltraSPARC and Niagara extended values. For example, '#ASI_P' and 19173 '#ASI_BLK_INIT_QUAD_LDD_AIUS'. See the V9 and processor specific 19174 manuals for details. 19175 19176 19177File: as.info, Node: Sparc-Relocs, Next: Sparc-Size-Translations, Prev: Sparc-Constants, Up: Sparc-Syntax 19178 191799.43.3.4 Relocations 19180.................... 19181 19182ELF relocations are available as defined in the 32-bit and 64-bit Sparc 19183ELF specifications. 19184 19185 'R_SPARC_HI22' is obtained using '%hi' and 'R_SPARC_LO10' is obtained 19186using '%lo'. Likewise 'R_SPARC_HIX22' is obtained from '%hix' and 19187'R_SPARC_LOX10' is obtained using '%lox'. For example: 19188 19189 sethi %hi(symbol), %g1 19190 or %g1, %lo(symbol), %g1 19191 19192 sethi %hix(symbol), %g1 19193 xor %g1, %lox(symbol), %g1 19194 19195 These "high" mnemonics extract bits 31:10 of their operand, and the 19196"low" mnemonics extract bits 9:0 of their operand. 19197 19198 V9 code model relocations can be requested as follows: 19199 19200 * 'R_SPARC_HH22' is requested using '%hh'. It can also be generated 19201 using '%uhi'. 19202 * 'R_SPARC_HM10' is requested using '%hm'. It can also be generated 19203 using '%ulo'. 19204 * 'R_SPARC_LM22' is requested using '%lm'. 19205 19206 * 'R_SPARC_H44' is requested using '%h44'. 19207 * 'R_SPARC_M44' is requested using '%m44'. 19208 * 'R_SPARC_L44' is requested using '%l44' or '%l34'. 19209 * 'R_SPARC_H34' is requested using '%h34'. 19210 19211 The '%l34' generates a 'R_SPARC_L44' relocation because it calculates 19212the necessary value, and therefore no explicit 'R_SPARC_L34' relocation 19213needed to be created for this purpose. 19214 19215 The '%h34' and '%l34' relocations are used for the abs34 code model. 19216Here is an example abs34 address generation sequence: 19217 19218 sethi %h34(symbol), %g1 19219 sllx %g1, 2, %g1 19220 or %g1, %l34(symbol), %g1 19221 19222 The PC relative relocation 'R_SPARC_PC22' can be obtained by 19223enclosing an operand inside of '%pc22'. Likewise, the 'R_SPARC_PC10' 19224relocation can be obtained using '%pc10'. These are mostly used when 19225assembling PIC code. For example, the standard PIC sequence on Sparc to 19226get the base of the global offset table, PC relative, into a register, 19227can be performed as: 19228 19229 sethi %pc22(_GLOBAL_OFFSET_TABLE_-4), %l7 19230 add %l7, %pc10(_GLOBAL_OFFSET_TABLE_+4), %l7 19231 19232 Several relocations exist to allow the link editor to potentially 19233optimize GOT data references. The 'R_SPARC_GOTDATA_OP_HIX22' relocation 19234can obtained by enclosing an operand inside of '%gdop_hix22'. The 19235'R_SPARC_GOTDATA_OP_LOX10' relocation can obtained by enclosing an 19236operand inside of '%gdop_lox10'. Likewise, 'R_SPARC_GOTDATA_OP' can be 19237obtained by enclosing an operand inside of '%gdop'. For example, 19238assuming the GOT base is in register '%l7': 19239 19240 sethi %gdop_hix22(symbol), %l1 19241 xor %l1, %gdop_lox10(symbol), %l1 19242 ld [%l7 + %l1], %l2, %gdop(symbol) 19243 19244 There are many relocations that can be requested for access to thread 19245local storage variables. All of the Sparc TLS mnemonics are supported: 19246 19247 * 'R_SPARC_TLS_GD_HI22' is requested using '%tgd_hi22'. 19248 * 'R_SPARC_TLS_GD_LO10' is requested using '%tgd_lo10'. 19249 * 'R_SPARC_TLS_GD_ADD' is requested using '%tgd_add'. 19250 * 'R_SPARC_TLS_GD_CALL' is requested using '%tgd_call'. 19251 19252 * 'R_SPARC_TLS_LDM_HI22' is requested using '%tldm_hi22'. 19253 * 'R_SPARC_TLS_LDM_LO10' is requested using '%tldm_lo10'. 19254 * 'R_SPARC_TLS_LDM_ADD' is requested using '%tldm_add'. 19255 * 'R_SPARC_TLS_LDM_CALL' is requested using '%tldm_call'. 19256 19257 * 'R_SPARC_TLS_LDO_HIX22' is requested using '%tldo_hix22'. 19258 * 'R_SPARC_TLS_LDO_LOX10' is requested using '%tldo_lox10'. 19259 * 'R_SPARC_TLS_LDO_ADD' is requested using '%tldo_add'. 19260 19261 * 'R_SPARC_TLS_IE_HI22' is requested using '%tie_hi22'. 19262 * 'R_SPARC_TLS_IE_LO10' is requested using '%tie_lo10'. 19263 * 'R_SPARC_TLS_IE_LD' is requested using '%tie_ld'. 19264 * 'R_SPARC_TLS_IE_LDX' is requested using '%tie_ldx'. 19265 * 'R_SPARC_TLS_IE_ADD' is requested using '%tie_add'. 19266 19267 * 'R_SPARC_TLS_LE_HIX22' is requested using '%tle_hix22'. 19268 * 'R_SPARC_TLS_LE_LOX10' is requested using '%tle_lox10'. 19269 19270 Here are some example TLS model sequences. 19271 19272 First, General Dynamic: 19273 19274 sethi %tgd_hi22(symbol), %l1 19275 add %l1, %tgd_lo10(symbol), %l1 19276 add %l7, %l1, %o0, %tgd_add(symbol) 19277 call __tls_get_addr, %tgd_call(symbol) 19278 nop 19279 19280 Local Dynamic: 19281 19282 sethi %tldm_hi22(symbol), %l1 19283 add %l1, %tldm_lo10(symbol), %l1 19284 add %l7, %l1, %o0, %tldm_add(symbol) 19285 call __tls_get_addr, %tldm_call(symbol) 19286 nop 19287 19288 sethi %tldo_hix22(symbol), %l1 19289 xor %l1, %tldo_lox10(symbol), %l1 19290 add %o0, %l1, %l1, %tldo_add(symbol) 19291 19292 Initial Exec: 19293 19294 sethi %tie_hi22(symbol), %l1 19295 add %l1, %tie_lo10(symbol), %l1 19296 ld [%l7 + %l1], %o0, %tie_ld(symbol) 19297 add %g7, %o0, %o0, %tie_add(symbol) 19298 19299 sethi %tie_hi22(symbol), %l1 19300 add %l1, %tie_lo10(symbol), %l1 19301 ldx [%l7 + %l1], %o0, %tie_ldx(symbol) 19302 add %g7, %o0, %o0, %tie_add(symbol) 19303 19304 And finally, Local Exec: 19305 19306 sethi %tle_hix22(symbol), %l1 19307 add %l1, %tle_lox10(symbol), %l1 19308 add %g7, %l1, %l1 19309 19310 When assembling for 64-bit, and a secondary constant addend is 19311specified in an address expression that would normally generate an 19312'R_SPARC_LO10' relocation, the assembler will emit an 'R_SPARC_OLO10' 19313instead. 19314 19315 19316File: as.info, Node: Sparc-Size-Translations, Prev: Sparc-Relocs, Up: Sparc-Syntax 19317 193189.43.3.5 Size Translations 19319.......................... 19320 19321Often it is desirable to write code in an operand size agnostic manner. 19322'as' provides support for this via operand size opcode translations. 19323Translations are supported for loads, stores, shifts, compare-and-swap 19324atomics, and the 'clr' synthetic instruction. 19325 19326 If generating 32-bit code, 'as' will generate the 32-bit opcode. 19327Whereas if 64-bit code is being generated, the 64-bit opcode will be 19328emitted. For example 'ldn' will be transformed into 'ld' for 32-bit 19329code and 'ldx' for 64-bit code. 19330 19331 Here is an example meant to demonstrate all the supported opcode 19332translations: 19333 19334 ldn [%o0], %o1 19335 ldna [%o0] %asi, %o2 19336 stn %o1, [%o0] 19337 stna %o2, [%o0] %asi 19338 slln %o3, 3, %o3 19339 srln %o4, 8, %o4 19340 sran %o5, 12, %o5 19341 casn [%o0], %o1, %o2 19342 casna [%o0] %asi, %o1, %o2 19343 clrn %g1 19344 19345 In 32-bit mode 'as' will emit: 19346 19347 ld [%o0], %o1 19348 lda [%o0] %asi, %o2 19349 st %o1, [%o0] 19350 sta %o2, [%o0] %asi 19351 sll %o3, 3, %o3 19352 srl %o4, 8, %o4 19353 sra %o5, 12, %o5 19354 cas [%o0], %o1, %o2 19355 casa [%o0] %asi, %o1, %o2 19356 clr %g1 19357 19358 And in 64-bit mode 'as' will emit: 19359 19360 ldx [%o0], %o1 19361 ldxa [%o0] %asi, %o2 19362 stx %o1, [%o0] 19363 stxa %o2, [%o0] %asi 19364 sllx %o3, 3, %o3 19365 srlx %o4, 8, %o4 19366 srax %o5, 12, %o5 19367 casx [%o0], %o1, %o2 19368 casxa [%o0] %asi, %o1, %o2 19369 clrx %g1 19370 19371 Finally, the '.nword' translating directive is supported as well. It 19372is documented in the section on Sparc machine directives. 19373 19374 19375File: as.info, Node: Sparc-Float, Next: Sparc-Directives, Prev: Sparc-Syntax, Up: Sparc-Dependent 19376 193779.43.4 Floating Point 19378--------------------- 19379 19380The Sparc uses IEEE floating-point numbers. 19381 19382 19383File: as.info, Node: Sparc-Directives, Prev: Sparc-Float, Up: Sparc-Dependent 19384 193859.43.5 Sparc Machine Directives 19386------------------------------- 19387 19388The Sparc version of 'as' supports the following additional machine 19389directives: 19390 19391'.align' 19392 This must be followed by the desired alignment in bytes. 19393 19394'.common' 19395 This must be followed by a symbol name, a positive number, and 19396 '"bss"'. This behaves somewhat like '.comm', but the syntax is 19397 different. 19398 19399'.half' 19400 This is functionally identical to '.short'. 19401 19402'.nword' 19403 On the Sparc, the '.nword' directive produces native word sized 19404 value, ie. if assembling with -32 it is equivalent to '.word', if 19405 assembling with -64 it is equivalent to '.xword'. 19406 19407'.proc' 19408 This directive is ignored. Any text following it on the same line 19409 is also ignored. 19410 19411'.register' 19412 This directive declares use of a global application or system 19413 register. It must be followed by a register name %g2, %g3, %g6 or 19414 %g7, comma and the symbol name for that register. If symbol name 19415 is '#scratch', it is a scratch register, if it is '#ignore', it 19416 just suppresses any errors about using undeclared global register, 19417 but does not emit any information about it into the object file. 19418 This can be useful e.g. if you save the register before use and 19419 restore it after. 19420 19421'.reserve' 19422 This must be followed by a symbol name, a positive number, and 19423 '"bss"'. This behaves somewhat like '.lcomm', but the syntax is 19424 different. 19425 19426'.seg' 19427 This must be followed by '"text"', '"data"', or '"data1"'. It 19428 behaves like '.text', '.data', or '.data 1'. 19429 19430'.skip' 19431 This is functionally identical to the '.space' directive. 19432 19433'.word' 19434 On the Sparc, the '.word' directive produces 32 bit values, instead 19435 of the 16 bit values it produces on many other machines. 19436 19437'.xword' 19438 On the Sparc V9 processor, the '.xword' directive produces 64 bit 19439 values. 19440 19441 19442File: as.info, Node: TIC54X-Dependent, Next: TIC6X-Dependent, Prev: Sparc-Dependent, Up: Machine Dependencies 19443 194449.44 TIC54X Dependent Features 19445============================== 19446 19447* Menu: 19448 19449* TIC54X-Opts:: Command-line Options 19450* TIC54X-Block:: Blocking 19451* TIC54X-Env:: Environment Settings 19452* TIC54X-Constants:: Constants Syntax 19453* TIC54X-Subsyms:: String Substitution 19454* TIC54X-Locals:: Local Label Syntax 19455* TIC54X-Builtins:: Builtin Assembler Math Functions 19456* TIC54X-Ext:: Extended Addressing Support 19457* TIC54X-Directives:: Directives 19458* TIC54X-Macros:: Macro Features 19459* TIC54X-MMRegs:: Memory-mapped Registers 19460* TIC54X-Syntax:: Syntax 19461 19462 19463File: as.info, Node: TIC54X-Opts, Next: TIC54X-Block, Up: TIC54X-Dependent 19464 194659.44.1 Options 19466-------------- 19467 19468The TMS320C54X version of 'as' has a few machine-dependent options. 19469 19470 You can use the '-mfar-mode' option to enable extended addressing 19471mode. All addresses will be assumed to be > 16 bits, and the 19472appropriate relocation types will be used. This option is equivalent to 19473using the '.far_mode' directive in the assembly code. If you do not use 19474the '-mfar-mode' option, all references will be assumed to be 16 bits. 19475This option may be abbreviated to '-mf'. 19476 19477 You can use the '-mcpu' option to specify a particular CPU. This 19478option is equivalent to using the '.version' directive in the assembly 19479code. For recognized CPU codes, see *Note '.version': 19480TIC54X-Directives. The default CPU version is '542'. 19481 19482 You can use the '-merrors-to-file' option to redirect error output to 19483a file (this provided for those deficient environments which don't 19484provide adequate output redirection). This option may be abbreviated to 19485'-me'. 19486 19487 19488File: as.info, Node: TIC54X-Block, Next: TIC54X-Env, Prev: TIC54X-Opts, Up: TIC54X-Dependent 19489 194909.44.2 Blocking 19491--------------- 19492 19493A blocked section or memory block is guaranteed not to cross the 19494blocking boundary (usually a page, or 128 words) if it is smaller than 19495the blocking size, or to start on a page boundary if it is larger than 19496the blocking size. 19497 19498 19499File: as.info, Node: TIC54X-Env, Next: TIC54X-Constants, Prev: TIC54X-Block, Up: TIC54X-Dependent 19500 195019.44.3 Environment Settings 19502--------------------------- 19503 19504'C54XDSP_DIR' and 'A_DIR' are semicolon-separated paths which are added 19505to the list of directories normally searched for source and include 19506files. 'C54XDSP_DIR' will override 'A_DIR'. 19507 19508 19509File: as.info, Node: TIC54X-Constants, Next: TIC54X-Subsyms, Prev: TIC54X-Env, Up: TIC54X-Dependent 19510 195119.44.4 Constants Syntax 19512----------------------- 19513 19514The TIC54X version of 'as' allows the following additional constant 19515formats, using a suffix to indicate the radix: 19516 19517 Binary 000000B, 011000b 19518 Octal 10Q, 224q 19519 Hexadecimal 45h, 0FH 19520 19521 19522 19523File: as.info, Node: TIC54X-Subsyms, Next: TIC54X-Locals, Prev: TIC54X-Constants, Up: TIC54X-Dependent 19524 195259.44.5 String Substitution 19526-------------------------- 19527 19528A subset of allowable symbols (which we'll call subsyms) may be assigned 19529arbitrary string values. This is roughly equivalent to C preprocessor 19530#define macros. When 'as' encounters one of these symbols, the symbol 19531is replaced in the input stream by its string value. Subsym names 19532*must* begin with a letter. 19533 19534 Subsyms may be defined using the '.asg' and '.eval' directives (*Note 19535'.asg': TIC54X-Directives, *Note '.eval': TIC54X-Directives. 19536 19537 Expansion is recursive until a previously encountered symbol is seen, 19538at which point substitution stops. 19539 19540 In this example, x is replaced with SYM2; SYM2 is replaced with SYM1, 19541and SYM1 is replaced with x. At this point, x has already been 19542encountered and the substitution stops. 19543 19544 .asg "x",SYM1 19545 .asg "SYM1",SYM2 19546 .asg "SYM2",x 19547 add x,a ; final code assembled is "add x, a" 19548 19549 Macro parameters are converted to subsyms; a side effect of this is 19550the normal 'as' '\ARG' dereferencing syntax is unnecessary. Subsyms 19551defined within a macro will have global scope, unless the '.var' 19552directive is used to identify the subsym as a local macro variable *note 19553'.var': TIC54X-Directives. 19554 19555 Substitution may be forced in situations where replacement might be 19556ambiguous by placing colons on either side of the subsym. The following 19557code: 19558 19559 .eval "10",x 19560 LAB:X: add #x, a 19561 19562 When assembled becomes: 19563 19564 LAB10 add #10, a 19565 19566 Smaller parts of the string assigned to a subsym may be accessed with 19567the following syntax: 19568 19569':SYMBOL(CHAR_INDEX):' 19570 Evaluates to a single-character string, the character at 19571 CHAR_INDEX. 19572':SYMBOL(START,LENGTH):' 19573 Evaluates to a substring of SYMBOL beginning at START with length 19574 LENGTH. 19575 19576 19577File: as.info, Node: TIC54X-Locals, Next: TIC54X-Builtins, Prev: TIC54X-Subsyms, Up: TIC54X-Dependent 19578 195799.44.6 Local Labels 19580------------------- 19581 19582Local labels may be defined in two ways: 19583 19584 * $N, where N is a decimal number between 0 and 9 19585 * LABEL?, where LABEL is any legal symbol name. 19586 19587 Local labels thus defined may be redefined or automatically 19588generated. The scope of a local label is based on when it may be 19589undefined or reset. This happens when one of the following situations 19590is encountered: 19591 19592 * .newblock directive *note '.newblock': TIC54X-Directives. 19593 * The current section is changed (.sect, .text, or .data) 19594 * Entering or leaving an included file 19595 * The macro scope where the label was defined is exited 19596 19597 19598File: as.info, Node: TIC54X-Builtins, Next: TIC54X-Ext, Prev: TIC54X-Locals, Up: TIC54X-Dependent 19599 196009.44.7 Math Builtins 19601-------------------- 19602 19603The following built-in functions may be used to generate a 19604floating-point value. All return a floating-point value except '$cvi', 19605'$int', and '$sgn', which return an integer value. 19606 19607'$acos(EXPR)' 19608 Returns the floating point arccosine of EXPR. 19609 19610'$asin(EXPR)' 19611 Returns the floating point arcsine of EXPR. 19612 19613'$atan(EXPR)' 19614 Returns the floating point arctangent of EXPR. 19615 19616'$atan2(EXPR1,EXPR2)' 19617 Returns the floating point arctangent of EXPR1 / EXPR2. 19618 19619'$ceil(EXPR)' 19620 Returns the smallest integer not less than EXPR as floating point. 19621 19622'$cosh(EXPR)' 19623 Returns the floating point hyperbolic cosine of EXPR. 19624 19625'$cos(EXPR)' 19626 Returns the floating point cosine of EXPR. 19627 19628'$cvf(EXPR)' 19629 Returns the integer value EXPR converted to floating-point. 19630 19631'$cvi(EXPR)' 19632 Returns the floating point value EXPR converted to integer. 19633 19634'$exp(EXPR)' 19635 Returns the floating point value e ^ EXPR. 19636 19637'$fabs(EXPR)' 19638 Returns the floating point absolute value of EXPR. 19639 19640'$floor(EXPR)' 19641 Returns the largest integer that is not greater than EXPR as 19642 floating point. 19643 19644'$fmod(EXPR1,EXPR2)' 19645 Returns the floating point remainder of EXPR1 / EXPR2. 19646 19647'$int(EXPR)' 19648 Returns 1 if EXPR evaluates to an integer, zero otherwise. 19649 19650'$ldexp(EXPR1,EXPR2)' 19651 Returns the floating point value EXPR1 * 2 ^ EXPR2. 19652 19653'$log10(EXPR)' 19654 Returns the base 10 logarithm of EXPR. 19655 19656'$log(EXPR)' 19657 Returns the natural logarithm of EXPR. 19658 19659'$max(EXPR1,EXPR2)' 19660 Returns the floating point maximum of EXPR1 and EXPR2. 19661 19662'$min(EXPR1,EXPR2)' 19663 Returns the floating point minimum of EXPR1 and EXPR2. 19664 19665'$pow(EXPR1,EXPR2)' 19666 Returns the floating point value EXPR1 ^ EXPR2. 19667 19668'$round(EXPR)' 19669 Returns the nearest integer to EXPR as a floating point number. 19670 19671'$sgn(EXPR)' 19672 Returns -1, 0, or 1 based on the sign of EXPR. 19673 19674'$sin(EXPR)' 19675 Returns the floating point sine of EXPR. 19676 19677'$sinh(EXPR)' 19678 Returns the floating point hyperbolic sine of EXPR. 19679 19680'$sqrt(EXPR)' 19681 Returns the floating point square root of EXPR. 19682 19683'$tan(EXPR)' 19684 Returns the floating point tangent of EXPR. 19685 19686'$tanh(EXPR)' 19687 Returns the floating point hyperbolic tangent of EXPR. 19688 19689'$trunc(EXPR)' 19690 Returns the integer value of EXPR truncated towards zero as 19691 floating point. 19692 19693 19694File: as.info, Node: TIC54X-Ext, Next: TIC54X-Directives, Prev: TIC54X-Builtins, Up: TIC54X-Dependent 19695 196969.44.8 Extended Addressing 19697-------------------------- 19698 19699The 'LDX' pseudo-op is provided for loading the extended addressing bits 19700of a label or address. For example, if an address '_label' resides in 19701extended program memory, the value of '_label' may be loaded as follows: 19702 ldx #_label,16,a ; loads extended bits of _label 19703 or #_label,a ; loads lower 16 bits of _label 19704 bacc a ; full address is in accumulator A 19705 19706 19707File: as.info, Node: TIC54X-Directives, Next: TIC54X-Macros, Prev: TIC54X-Ext, Up: TIC54X-Dependent 19708 197099.44.9 Directives 19710----------------- 19711 19712'.align [SIZE]' 19713'.even' 19714 Align the section program counter on the next boundary, based on 19715 SIZE. SIZE may be any power of 2. '.even' is equivalent to 19716 '.align' with a SIZE of 2. 19717 '1' 19718 Align SPC to word boundary 19719 '2' 19720 Align SPC to longword boundary (same as .even) 19721 '128' 19722 Align SPC to page boundary 19723 19724'.asg STRING, NAME' 19725 Assign NAME the string STRING. String replacement is performed on 19726 STRING before assignment. 19727 19728'.eval STRING, NAME' 19729 Evaluate the contents of string STRING and assign the result as a 19730 string to the subsym NAME. String replacement is performed on 19731 STRING before assignment. 19732 19733'.bss SYMBOL, SIZE [, [BLOCKING_FLAG] [,ALIGNMENT_FLAG]]' 19734 Reserve space for SYMBOL in the .bss section. SIZE is in words. 19735 If present, BLOCKING_FLAG indicates the allocated space should be 19736 aligned on a page boundary if it would otherwise cross a page 19737 boundary. If present, ALIGNMENT_FLAG causes the assembler to 19738 allocate SIZE on a long word boundary. 19739 19740'.byte VALUE [,...,VALUE_N]' 19741'.ubyte VALUE [,...,VALUE_N]' 19742'.char VALUE [,...,VALUE_N]' 19743'.uchar VALUE [,...,VALUE_N]' 19744 Place one or more bytes into consecutive words of the current 19745 section. The upper 8 bits of each word is zero-filled. If a label 19746 is used, it points to the word allocated for the first byte 19747 encountered. 19748 19749'.clink ["SECTION_NAME"]' 19750 Set STYP_CLINK flag for this section, which indicates to the linker 19751 that if no symbols from this section are referenced, the section 19752 should not be included in the link. If SECTION_NAME is omitted, 19753 the current section is used. 19754 19755'.c_mode' 19756 TBD. 19757 19758'.copy "FILENAME" | FILENAME' 19759'.include "FILENAME" | FILENAME' 19760 Read source statements from FILENAME. The normal include search 19761 path is used. Normally .copy will cause statements from the 19762 included file to be printed in the assembly listing and .include 19763 will not, but this distinction is not currently implemented. 19764 19765'.data' 19766 Begin assembling code into the .data section. 19767 19768'.double VALUE [,...,VALUE_N]' 19769'.ldouble VALUE [,...,VALUE_N]' 19770'.float VALUE [,...,VALUE_N]' 19771'.xfloat VALUE [,...,VALUE_N]' 19772 Place an IEEE single-precision floating-point representation of one 19773 or more floating-point values into the current section. All but 19774 '.xfloat' align the result on a longword boundary. Values are 19775 stored most-significant word first. 19776 19777'.drlist' 19778'.drnolist' 19779 Control printing of directives to the listing file. Ignored. 19780 19781'.emsg STRING' 19782'.mmsg STRING' 19783'.wmsg STRING' 19784 Emit a user-defined error, message, or warning, respectively. 19785 19786'.far_mode' 19787 Use extended addressing when assembling statements. This should 19788 appear only once per file, and is equivalent to the -mfar-mode 19789 option *note '-mfar-mode': TIC54X-Opts. 19790 19791'.fclist' 19792'.fcnolist' 19793 Control printing of false conditional blocks to the listing file. 19794 19795'.field VALUE [,SIZE]' 19796 Initialize a bitfield of SIZE bits in the current section. If 19797 VALUE is relocatable, then SIZE must be 16. SIZE defaults to 16 19798 bits. If VALUE does not fit into SIZE bits, the value will be 19799 truncated. Successive '.field' directives will pack starting at 19800 the current word, filling the most significant bits first, and 19801 aligning to the start of the next word if the field size does not 19802 fit into the space remaining in the current word. A '.align' 19803 directive with an operand of 1 will force the next '.field' 19804 directive to begin packing into a new word. If a label is used, it 19805 points to the word that contains the specified field. 19806 19807'.global SYMBOL [,...,SYMBOL_N]' 19808'.def SYMBOL [,...,SYMBOL_N]' 19809'.ref SYMBOL [,...,SYMBOL_N]' 19810 '.def' nominally identifies a symbol defined in the current file 19811 and available to other files. '.ref' identifies a symbol used in 19812 the current file but defined elsewhere. Both map to the standard 19813 '.global' directive. 19814 19815'.half VALUE [,...,VALUE_N]' 19816'.uhalf VALUE [,...,VALUE_N]' 19817'.short VALUE [,...,VALUE_N]' 19818'.ushort VALUE [,...,VALUE_N]' 19819'.int VALUE [,...,VALUE_N]' 19820'.uint VALUE [,...,VALUE_N]' 19821'.word VALUE [,...,VALUE_N]' 19822'.uword VALUE [,...,VALUE_N]' 19823 Place one or more values into consecutive words of the current 19824 section. If a label is used, it points to the word allocated for 19825 the first value encountered. 19826 19827'.label SYMBOL' 19828 Define a special SYMBOL to refer to the load time address of the 19829 current section program counter. 19830 19831'.length' 19832'.width' 19833 Set the page length and width of the output listing file. Ignored. 19834 19835'.list' 19836'.nolist' 19837 Control whether the source listing is printed. Ignored. 19838 19839'.long VALUE [,...,VALUE_N]' 19840'.ulong VALUE [,...,VALUE_N]' 19841'.xlong VALUE [,...,VALUE_N]' 19842 Place one or more 32-bit values into consecutive words in the 19843 current section. The most significant word is stored first. 19844 '.long' and '.ulong' align the result on a longword boundary; 19845 'xlong' does not. 19846 19847'.loop [COUNT]' 19848'.break [CONDITION]' 19849'.endloop' 19850 Repeatedly assemble a block of code. '.loop' begins the block, and 19851 '.endloop' marks its termination. COUNT defaults to 1024, and 19852 indicates the number of times the block should be repeated. 19853 '.break' terminates the loop so that assembly begins after the 19854 '.endloop' directive. The optional CONDITION will cause the loop 19855 to terminate only if it evaluates to zero. 19856 19857'MACRO_NAME .macro [PARAM1][,...PARAM_N]' 19858'[.mexit]' 19859'.endm' 19860 See the section on macros for more explanation (*Note 19861 TIC54X-Macros::. 19862 19863'.mlib "FILENAME" | FILENAME' 19864 Load the macro library FILENAME. FILENAME must be an archived 19865 library (BFD ar-compatible) of text files, expected to contain only 19866 macro definitions. The standard include search path is used. 19867 19868'.mlist' 19869'.mnolist' 19870 Control whether to include macro and loop block expansions in the 19871 listing output. Ignored. 19872 19873'.mmregs' 19874 Define global symbolic names for the 'c54x registers. Supposedly 19875 equivalent to executing '.set' directives for each register with 19876 its memory-mapped value, but in reality is provided only for 19877 compatibility and does nothing. 19878 19879'.newblock' 19880 This directive resets any TIC54X local labels currently defined. 19881 Normal 'as' local labels are unaffected. 19882 19883'.option OPTION_LIST' 19884 Set listing options. Ignored. 19885 19886'.sblock "SECTION_NAME" | SECTION_NAME [,"NAME_N" | NAME_N]' 19887 Designate SECTION_NAME for blocking. Blocking guarantees that a 19888 section will start on a page boundary (128 words) if it would 19889 otherwise cross a page boundary. Only initialized sections may be 19890 designated with this directive. See also *Note TIC54X-Block::. 19891 19892'.sect "SECTION_NAME"' 19893 Define a named initialized section and make it the current section. 19894 19895'SYMBOL .set "VALUE"' 19896'SYMBOL .equ "VALUE"' 19897 Equate a constant VALUE to a SYMBOL, which is placed in the symbol 19898 table. SYMBOL may not be previously defined. 19899 19900'.space SIZE_IN_BITS' 19901'.bes SIZE_IN_BITS' 19902 Reserve the given number of bits in the current section and 19903 zero-fill them. If a label is used with '.space', it points to the 19904 *first* word reserved. With '.bes', the label points to the *last* 19905 word reserved. 19906 19907'.sslist' 19908'.ssnolist' 19909 Controls the inclusion of subsym replacement in the listing output. 19910 Ignored. 19911 19912'.string "STRING" [,...,"STRING_N"]' 19913'.pstring "STRING" [,...,"STRING_N"]' 19914 Place 8-bit characters from STRING into the current section. 19915 '.string' zero-fills the upper 8 bits of each word, while 19916 '.pstring' puts two characters into each word, filling the 19917 most-significant bits first. Unused space is zero-filled. If a 19918 label is used, it points to the first word initialized. 19919 19920'[STAG] .struct [OFFSET]' 19921'[NAME_1] element [COUNT_1]' 19922'[NAME_2] element [COUNT_2]' 19923'[TNAME] .tag STAGX [TCOUNT]' 19924'...' 19925'[NAME_N] element [COUNT_N]' 19926'[SSIZE] .endstruct' 19927'LABEL .tag [STAG]' 19928 Assign symbolic offsets to the elements of a structure. STAG 19929 defines a symbol to use to reference the structure. OFFSET 19930 indicates a starting value to use for the first element 19931 encountered; otherwise it defaults to zero. Each element can have 19932 a named offset, NAME, which is a symbol assigned the value of the 19933 element's offset into the structure. If STAG is missing, these 19934 become global symbols. COUNT adjusts the offset that many times, 19935 as if 'element' were an array. 'element' may be one of '.byte', 19936 '.word', '.long', '.float', or any equivalent of those, and the 19937 structure offset is adjusted accordingly. '.field' and '.string' 19938 are also allowed; the size of '.field' is one bit, and '.string' is 19939 considered to be one word in size. Only element descriptors, 19940 structure/union tags, '.align' and conditional assembly directives 19941 are allowed within '.struct'/'.endstruct'. '.align' aligns member 19942 offsets to word boundaries only. SSIZE, if provided, will always 19943 be assigned the size of the structure. 19944 19945 The '.tag' directive, in addition to being used to define a 19946 structure/union element within a structure, may be used to apply a 19947 structure to a symbol. Once applied to LABEL, the individual 19948 structure elements may be applied to LABEL to produce the desired 19949 offsets using LABEL as the structure base. 19950 19951'.tab' 19952 Set the tab size in the output listing. Ignored. 19953 19954'[UTAG] .union' 19955'[NAME_1] element [COUNT_1]' 19956'[NAME_2] element [COUNT_2]' 19957'[TNAME] .tag UTAGX[,TCOUNT]' 19958'...' 19959'[NAME_N] element [COUNT_N]' 19960'[USIZE] .endstruct' 19961'LABEL .tag [UTAG]' 19962 Similar to '.struct', but the offset after each element is reset to 19963 zero, and the USIZE is set to the maximum of all defined elements. 19964 Starting offset for the union is always zero. 19965 19966'[SYMBOL] .usect "SECTION_NAME", SIZE, [,[BLOCKING_FLAG] [,ALIGNMENT_FLAG]]' 19967 Reserve space for variables in a named, uninitialized section 19968 (similar to .bss). '.usect' allows definitions sections 19969 independent of .bss. SYMBOL points to the first location reserved 19970 by this allocation. The symbol may be used as a variable name. 19971 SIZE is the allocated size in words. BLOCKING_FLAG indicates 19972 whether to block this section on a page boundary (128 words) (*note 19973 TIC54X-Block::). ALIGNMENT FLAG indicates whether the section 19974 should be longword-aligned. 19975 19976'.var SYM[,..., SYM_N]' 19977 Define a subsym to be a local variable within a macro. See *Note 19978 TIC54X-Macros::. 19979 19980'.version VERSION' 19981 Set which processor to build instructions for. Though the 19982 following values are accepted, the op is ignored. 19983 '541' 19984 '542' 19985 '543' 19986 '545' 19987 '545LP' 19988 '546LP' 19989 '548' 19990 '549' 19991 19992 19993File: as.info, Node: TIC54X-Macros, Next: TIC54X-MMRegs, Prev: TIC54X-Directives, Up: TIC54X-Dependent 19994 199959.44.10 Macros 19996-------------- 19997 19998Macros do not require explicit dereferencing of arguments (i.e., \ARG). 19999 20000 During macro expansion, the macro parameters are converted to 20001subsyms. If the number of arguments passed the macro invocation exceeds 20002the number of parameters defined, the last parameter is assigned the 20003string equivalent of all remaining arguments. If fewer arguments are 20004given than parameters, the missing parameters are assigned empty 20005strings. To include a comma in an argument, you must enclose the 20006argument in quotes. 20007 20008 The following built-in subsym functions allow examination of the 20009string value of subsyms (or ordinary strings). The arguments are 20010strings unless otherwise indicated (subsyms passed as args will be 20011replaced by the strings they represent). 20012'$symlen(STR)' 20013 Returns the length of STR. 20014 20015'$symcmp(STR1,STR2)' 20016 Returns 0 if STR1 == STR2, non-zero otherwise. 20017 20018'$firstch(STR,CH)' 20019 Returns index of the first occurrence of character constant CH in 20020 STR. 20021 20022'$lastch(STR,CH)' 20023 Returns index of the last occurrence of character constant CH in 20024 STR. 20025 20026'$isdefed(SYMBOL)' 20027 Returns zero if the symbol SYMBOL is not in the symbol table, 20028 non-zero otherwise. 20029 20030'$ismember(SYMBOL,LIST)' 20031 Assign the first member of comma-separated string LIST to SYMBOL; 20032 LIST is reassigned the remainder of the list. Returns zero if LIST 20033 is a null string. Both arguments must be subsyms. 20034 20035'$iscons(EXPR)' 20036 Returns 1 if string EXPR is binary, 2 if octal, 3 if hexadecimal, 4 20037 if a character, 5 if decimal, and zero if not an integer. 20038 20039'$isname(NAME)' 20040 Returns 1 if NAME is a valid symbol name, zero otherwise. 20041 20042'$isreg(REG)' 20043 Returns 1 if REG is a valid predefined register name (AR0-AR7 20044 only). 20045 20046'$structsz(STAG)' 20047 Returns the size of the structure or union represented by STAG. 20048 20049'$structacc(STAG)' 20050 Returns the reference point of the structure or union represented 20051 by STAG. Always returns zero. 20052 20053 20054File: as.info, Node: TIC54X-MMRegs, Next: TIC54X-Syntax, Prev: TIC54X-Macros, Up: TIC54X-Dependent 20055 200569.44.11 Memory-mapped Registers 20057------------------------------- 20058 20059The following symbols are recognized as memory-mapped registers: 20060 20061 20062File: as.info, Node: TIC54X-Syntax, Prev: TIC54X-MMRegs, Up: TIC54X-Dependent 20063 200649.44.12 TIC54X Syntax 20065--------------------- 20066 20067* Menu: 20068 20069* TIC54X-Chars:: Special Characters 20070 20071 20072File: as.info, Node: TIC54X-Chars, Up: TIC54X-Syntax 20073 200749.44.12.1 Special Characters 20075............................ 20076 20077The presence of a ';' appearing anywhere on a line indicates the start 20078of a comment that extends to the end of that line. 20079 20080 If a '#' appears as the first character of a line then the whole line 20081is treated as a comment, but in this case the line can also be a logical 20082line number directive (*note Comments::) or a preprocessor control 20083command (*note Preprocessing::). 20084 20085 The presence of an asterisk ('*') at the start of a line also 20086indicates a comment that extends to the end of that line. 20087 20088 The TIC54X assembler does not currently support a line separator 20089character. 20090 20091 20092File: as.info, Node: TIC6X-Dependent, Next: TILE-Gx-Dependent, Prev: TIC54X-Dependent, Up: Machine Dependencies 20093 200949.45 TIC6X Dependent Features 20095============================= 20096 20097* Menu: 20098 20099* TIC6X Options:: Options 20100* TIC6X Syntax:: Syntax 20101* TIC6X Directives:: Directives 20102 20103 20104File: as.info, Node: TIC6X Options, Next: TIC6X Syntax, Up: TIC6X-Dependent 20105 201069.45.1 TIC6X Options 20107-------------------- 20108 20109'-march=ARCH' 20110 Enable (only) instructions from architecture ARCH. By default, all 20111 instructions are permitted. 20112 20113 The following values of ARCH are accepted: 'c62x', 'c64x', 'c64x+', 20114 'c67x', 'c67x+', 'c674x'. 20115 20116'-mdsbt' 20117'-mno-dsbt' 20118 The '-mdsbt' option causes the assembler to generate the 20119 'Tag_ABI_DSBT' attribute with a value of 1, indicating that the 20120 code is using DSBT addressing. The '-mno-dsbt' option, the 20121 default, causes the tag to have a value of 0, indicating that the 20122 code does not use DSBT addressing. The linker will emit a warning 20123 if objects of different type (DSBT and non-DSBT) are linked 20124 together. 20125 20126'-mpid=no' 20127'-mpid=near' 20128'-mpid=far' 20129 The '-mpid=' option causes the assembler to generate the 20130 'Tag_ABI_PID' attribute with a value indicating the form of data 20131 addressing used by the code. '-mpid=no', the default, indicates 20132 position-dependent data addressing, '-mpid=near' indicates 20133 position-independent addressing with GOT accesses using near DP 20134 addressing, and '-mpid=far' indicates position-independent 20135 addressing with GOT accesses using far DP addressing. The linker 20136 will emit a warning if objects built with different settings of 20137 this option are linked together. 20138 20139'-mpic' 20140'-mno-pic' 20141 The '-mpic' option causes the assembler to generate the 20142 'Tag_ABI_PIC' attribute with a value of 1, indicating that the code 20143 is using position-independent code addressing, The '-mno-pic' 20144 option, the default, causes the tag to have a value of 0, 20145 indicating position-dependent code addressing. The linker will 20146 emit a warning if objects of different type (position-dependent and 20147 position-independent) are linked together. 20148 20149'-mbig-endian' 20150'-mlittle-endian' 20151 Generate code for the specified endianness. The default is 20152 little-endian. 20153 20154 20155File: as.info, Node: TIC6X Syntax, Next: TIC6X Directives, Prev: TIC6X Options, Up: TIC6X-Dependent 20156 201579.45.2 TIC6X Syntax 20158------------------- 20159 20160The presence of a ';' on a line indicates the start of a comment that 20161extends to the end of the current line. If a '#' or '*' appears as the 20162first character of a line, the whole line is treated as a comment. Note 20163that if a line starts with a '#' character then it can also be a logical 20164line number directive (*note Comments::) or a preprocessor control 20165command (*note Preprocessing::). 20166 20167 The '@' character can be used instead of a newline to separate 20168statements. 20169 20170 Instruction, register and functional unit names are case-insensitive. 20171'as' requires fully-specified functional unit names, such as '.S1', 20172'.L1X' or '.D1T2', on all instructions using a functional unit. 20173 20174 For some instructions, there may be syntactic ambiguity between 20175register or functional unit names and the names of labels or other 20176symbols. To avoid this, enclose the ambiguous symbol name in 20177parentheses; register and functional unit names may not be enclosed in 20178parentheses. 20179 20180 20181File: as.info, Node: TIC6X Directives, Prev: TIC6X Syntax, Up: TIC6X-Dependent 20182 201839.45.3 TIC6X Directives 20184----------------------- 20185 20186Directives controlling the set of instructions accepted by the assembler 20187have effect for instructions between the directive and any subsequent 20188directive overriding it. 20189 20190'.arch ARCH' 20191 This has the same effect as '-march=ARCH'. 20192 20193'.cantunwind' 20194 Prevents unwinding through the current function. No personality 20195 routine or exception table data is required or permitted. 20196 20197 If this is not specified then frame unwinding information will be 20198 constructed from CFI directives. *note CFI directives::. 20199 20200'.c6xabi_attribute TAG, VALUE' 20201 Set the C6000 EABI build attribute TAG to VALUE. 20202 20203 The TAG is either an attribute number or one of 'Tag_ISA', 20204 'Tag_ABI_wchar_t', 'Tag_ABI_stack_align_needed', 20205 'Tag_ABI_stack_align_preserved', 'Tag_ABI_DSBT', 'Tag_ABI_PID', 20206 'Tag_ABI_PIC', 'TAG_ABI_array_object_alignment', 20207 'TAG_ABI_array_object_align_expected', 'Tag_ABI_compatibility' and 20208 'Tag_ABI_conformance'. The VALUE is either a 'number', '"string"', 20209 or 'number, "string"' depending on the tag. 20210 20211'.ehtype SYMBOL' 20212 Output an exception type table reference to SYMBOL. 20213 20214'.endp' 20215 Marks the end of and exception table or function. If preceeded by 20216 a '.handlerdata' directive then this also switched back to the 20217 previous text section. 20218 20219'.handlerdata' 20220 Marks the end of the current function, and the start of the 20221 exception table entry for that function. Anything between this 20222 directive and the '.endp' directive will be added to the exception 20223 table entry. 20224 20225 Must be preceded by a CFI block containing a '.cfi_lsda' directive. 20226 20227'.nocmp' 20228 Disallow use of C64x+ compact instructions in the current text 20229 section. 20230 20231'.personalityindex INDEX' 20232 Sets the personality routine for the current function to the ABI 20233 specified compact routine number INDEX 20234 20235'.personality NAME' 20236 Sets the personality routine for the current function to NAME. 20237 20238'.scomm SYMBOL, SIZE, ALIGN' 20239 Like '.comm', creating a common symbol SYMBOL with size SIZE and 20240 alignment ALIGN, but unlike when using '.comm', this symbol will be 20241 placed into the small BSS section by the linker. 20242 20243 20244File: as.info, Node: TILE-Gx-Dependent, Next: TILEPro-Dependent, Prev: TIC6X-Dependent, Up: Machine Dependencies 20245 202469.46 TILE-Gx Dependent Features 20247=============================== 20248 20249* Menu: 20250 20251* TILE-Gx Options:: TILE-Gx Options 20252* TILE-Gx Syntax:: TILE-Gx Syntax 20253* TILE-Gx Directives:: TILE-Gx Directives 20254 20255 20256File: as.info, Node: TILE-Gx Options, Next: TILE-Gx Syntax, Up: TILE-Gx-Dependent 20257 202589.46.1 Options 20259-------------- 20260 20261The following table lists all available TILE-Gx specific options: 20262 20263'-m32 | -m64' 20264 Select the word size, either 32 bits or 64 bits. 20265 20266'-EB | -EL' 20267 Select the endianness, either big-endian (-EB) or little-endian 20268 (-EL). 20269 20270 20271File: as.info, Node: TILE-Gx Syntax, Next: TILE-Gx Directives, Prev: TILE-Gx Options, Up: TILE-Gx-Dependent 20272 202739.46.2 Syntax 20274------------- 20275 20276Block comments are delimited by '/*' and '*/'. End of line comments may 20277be introduced by '#'. 20278 20279 Instructions consist of a leading opcode or macro name followed by 20280whitespace and an optional comma-separated list of operands: 20281 20282 OPCODE [OPERAND, ...] 20283 20284 Instructions must be separated by a newline or semicolon. 20285 20286 There are two ways to write code: either write naked instructions, 20287which the assembler is free to combine into VLIW bundles, or specify the 20288VLIW bundles explicitly. 20289 20290 Bundles are specified using curly braces: 20291 20292 { ADD r3,r4,r5 ; ADD r7,r8,r9 ; LW r10,r11 } 20293 20294 A bundle can span multiple lines. If you want to put multiple 20295instructions on a line, whether in a bundle or not, you need to separate 20296them with semicolons as in this example. 20297 20298 A bundle may contain one or more instructions, up to the limit 20299specified by the ISA (currently three). If fewer instructions are 20300specified than the hardware supports in a bundle, the assembler inserts 20301'fnop' instructions automatically. 20302 20303 The assembler will prefer to preserve the ordering of instructions 20304within the bundle, putting the first instruction in a lower-numbered 20305pipeline than the next one, etc. This fact, combined with the optional 20306use of explicit 'fnop' or 'nop' instructions, allows precise control 20307over which pipeline executes each instruction. 20308 20309 If the instructions cannot be bundled in the listed order, the 20310assembler will automatically try to find a valid pipeline assignment. 20311If there is no way to bundle the instructions together, the assembler 20312reports an error. 20313 20314 The assembler does not yet auto-bundle (automatically combine 20315multiple instructions into one bundle), but it reserves the right to do 20316so in the future. If you want to force an instruction to run by itself, 20317put it in a bundle explicitly with curly braces and use 'nop' 20318instructions (not 'fnop') to fill the remaining pipeline slots in that 20319bundle. 20320 20321* Menu: 20322 20323* TILE-Gx Opcodes:: Opcode Naming Conventions. 20324* TILE-Gx Registers:: Register Naming. 20325* TILE-Gx Modifiers:: Symbolic Operand Modifiers. 20326 20327 20328File: as.info, Node: TILE-Gx Opcodes, Next: TILE-Gx Registers, Up: TILE-Gx Syntax 20329 203309.46.2.1 Opcode Names 20331..................... 20332 20333For a complete list of opcodes and descriptions of their semantics, see 20334'TILE-Gx Instruction Set Architecture', available upon request at 20335www.tilera.com. 20336 20337 20338File: as.info, Node: TILE-Gx Registers, Next: TILE-Gx Modifiers, Prev: TILE-Gx Opcodes, Up: TILE-Gx Syntax 20339 203409.46.2.2 Register Names 20341....................... 20342 20343General-purpose registers are represented by predefined symbols of the 20344form 'rN', where N represents a number between '0' and '63'. However, 20345the following registers have canonical names that must be used instead: 20346 20347'r54' 20348 sp 20349 20350'r55' 20351 lr 20352 20353'r56' 20354 sn 20355 20356'r57' 20357 idn0 20358 20359'r58' 20360 idn1 20361 20362'r59' 20363 udn0 20364 20365'r60' 20366 udn1 20367 20368'r61' 20369 udn2 20370 20371'r62' 20372 udn3 20373 20374'r63' 20375 zero 20376 20377 The assembler will emit a warning if a numeric name is used instead 20378of the non-numeric name. The '.no_require_canonical_reg_names' 20379assembler pseudo-op turns off this warning. 20380'.require_canonical_reg_names' turns it back on. 20381 20382 20383File: as.info, Node: TILE-Gx Modifiers, Prev: TILE-Gx Registers, Up: TILE-Gx Syntax 20384 203859.46.2.3 Symbolic Operand Modifiers 20386................................... 20387 20388The assembler supports several modifiers when using symbol addresses in 20389TILE-Gx instruction operands. The general syntax is the following: 20390 20391 modifier(symbol) 20392 20393 The following modifiers are supported: 20394 20395'hw0' 20396 20397 This modifier is used to load bits 0-15 of the symbol's address. 20398 20399'hw1' 20400 20401 This modifier is used to load bits 16-31 of the symbol's address. 20402 20403'hw2' 20404 20405 This modifier is used to load bits 32-47 of the symbol's address. 20406 20407'hw3' 20408 20409 This modifier is used to load bits 48-63 of the symbol's address. 20410 20411'hw0_last' 20412 20413 This modifier yields the same value as 'hw0', but it also checks 20414 that the value does not overflow. 20415 20416'hw1_last' 20417 20418 This modifier yields the same value as 'hw1', but it also checks 20419 that the value does not overflow. 20420 20421'hw2_last' 20422 20423 This modifier yields the same value as 'hw2', but it also checks 20424 that the value does not overflow. 20425 20426 A 48-bit symbolic value is constructed by using the following 20427 idiom: 20428 20429 moveli r0, hw2_last(sym) 20430 shl16insli r0, r0, hw1(sym) 20431 shl16insli r0, r0, hw0(sym) 20432 20433'hw0_got' 20434 20435 This modifier is used to load bits 0-15 of the symbol's offset in 20436 the GOT entry corresponding to the symbol. 20437 20438'hw0_last_got' 20439 20440 This modifier yields the same value as 'hw0_got', but it also 20441 checks that the value does not overflow. 20442 20443'hw1_last_got' 20444 20445 This modifier is used to load bits 16-31 of the symbol's offset in 20446 the GOT entry corresponding to the symbol, and it also checks that 20447 the value does not overflow. 20448 20449'plt' 20450 20451 This modifier is used for function symbols. It causes a _procedure 20452 linkage table_, an array of code stubs, to be created at the time 20453 the shared object is created or linked against, together with a 20454 global offset table entry. The value is a pc-relative offset to 20455 the corresponding stub code in the procedure linkage table. This 20456 arrangement causes the run-time symbol resolver to be called to 20457 look up and set the value of the symbol the first time the function 20458 is called (at latest; depending environment variables). It is only 20459 safe to leave the symbol unresolved this way if all references are 20460 function calls. 20461 20462'hw0_plt' 20463 20464 This modifier is used to load bits 0-15 of the pc-relative address 20465 of a plt entry. 20466 20467'hw1_plt' 20468 20469 This modifier is used to load bits 16-31 of the pc-relative address 20470 of a plt entry. 20471 20472'hw1_last_plt' 20473 20474 This modifier yields the same value as 'hw1_plt', but it also 20475 checks that the value does not overflow. 20476 20477'hw2_last_plt' 20478 20479 This modifier is used to load bits 32-47 of the pc-relative address 20480 of a plt entry, and it also checks that the value does not 20481 overflow. 20482 20483'hw0_tls_gd' 20484 20485 This modifier is used to load bits 0-15 of the offset of the GOT 20486 entry of the symbol's TLS descriptor, to be used for 20487 general-dynamic TLS accesses. 20488 20489'hw0_last_tls_gd' 20490 20491 This modifier yields the same value as 'hw0_tls_gd', but it also 20492 checks that the value does not overflow. 20493 20494'hw1_last_tls_gd' 20495 20496 This modifier is used to load bits 16-31 of the offset of the GOT 20497 entry of the symbol's TLS descriptor, to be used for 20498 general-dynamic TLS accesses. It also checks that the value does 20499 not overflow. 20500 20501'hw0_tls_ie' 20502 20503 This modifier is used to load bits 0-15 of the offset of the GOT 20504 entry containing the offset of the symbol's address from the TCB, 20505 to be used for initial-exec TLS accesses. 20506 20507'hw0_last_tls_ie' 20508 20509 This modifier yields the same value as 'hw0_tls_ie', but it also 20510 checks that the value does not overflow. 20511 20512'hw1_last_tls_ie' 20513 20514 This modifier is used to load bits 16-31 of the offset of the GOT 20515 entry containing the offset of the symbol's address from the TCB, 20516 to be used for initial-exec TLS accesses. It also checks that the 20517 value does not overflow. 20518 20519'hw0_tls_le' 20520 20521 This modifier is used to load bits 0-15 of the offset of the 20522 symbol's address from the TCB, to be used for local-exec TLS 20523 accesses. 20524 20525'hw0_last_tls_le' 20526 20527 This modifier yields the same value as 'hw0_tls_le', but it also 20528 checks that the value does not overflow. 20529 20530'hw1_last_tls_le' 20531 20532 This modifier is used to load bits 16-31 of the offset of the 20533 symbol's address from the TCB, to be used for local-exec TLS 20534 accesses. It also checks that the value does not overflow. 20535 20536'tls_gd_call' 20537 20538 This modifier is used to tag an instrution as the "call" part of a 20539 calling sequence for a TLS GD reference of its operand. 20540 20541'tls_gd_add' 20542 20543 This modifier is used to tag an instruction as the "add" part of a 20544 calling sequence for a TLS GD reference of its operand. 20545 20546'tls_ie_load' 20547 20548 This modifier is used to tag an instruction as the "load" part of a 20549 calling sequence for a TLS IE reference of its operand. 20550 20551 20552File: as.info, Node: TILE-Gx Directives, Prev: TILE-Gx Syntax, Up: TILE-Gx-Dependent 20553 205549.46.3 TILE-Gx Directives 20555------------------------- 20556 20557'.align EXPRESSION [, EXPRESSION]' 20558 This is the generic .ALIGN directive. The first argument is the 20559 requested alignment in bytes. 20560 20561'.allow_suspicious_bundles' 20562 Turns on error checking for combinations of instructions in a 20563 bundle that probably indicate a programming error. This is on by 20564 default. 20565 20566'.no_allow_suspicious_bundles' 20567 Turns off error checking for combinations of instructions in a 20568 bundle that probably indicate a programming error. 20569 20570'.require_canonical_reg_names' 20571 Require that canonical register names be used, and emit a warning 20572 if the numeric names are used. This is on by default. 20573 20574'.no_require_canonical_reg_names' 20575 Permit the use of numeric names for registers that have canonical 20576 names. 20577 20578 20579File: as.info, Node: TILEPro-Dependent, Next: V850-Dependent, Prev: TILE-Gx-Dependent, Up: Machine Dependencies 20580 205819.47 TILEPro Dependent Features 20582=============================== 20583 20584* Menu: 20585 20586* TILEPro Options:: TILEPro Options 20587* TILEPro Syntax:: TILEPro Syntax 20588* TILEPro Directives:: TILEPro Directives 20589 20590 20591File: as.info, Node: TILEPro Options, Next: TILEPro Syntax, Up: TILEPro-Dependent 20592 205939.47.1 Options 20594-------------- 20595 20596'as' has no machine-dependent command-line options for TILEPro. 20597 20598 20599File: as.info, Node: TILEPro Syntax, Next: TILEPro Directives, Prev: TILEPro Options, Up: TILEPro-Dependent 20600 206019.47.2 Syntax 20602------------- 20603 20604Block comments are delimited by '/*' and '*/'. End of line comments may 20605be introduced by '#'. 20606 20607 Instructions consist of a leading opcode or macro name followed by 20608whitespace and an optional comma-separated list of operands: 20609 20610 OPCODE [OPERAND, ...] 20611 20612 Instructions must be separated by a newline or semicolon. 20613 20614 There are two ways to write code: either write naked instructions, 20615which the assembler is free to combine into VLIW bundles, or specify the 20616VLIW bundles explicitly. 20617 20618 Bundles are specified using curly braces: 20619 20620 { ADD r3,r4,r5 ; ADD r7,r8,r9 ; LW r10,r11 } 20621 20622 A bundle can span multiple lines. If you want to put multiple 20623instructions on a line, whether in a bundle or not, you need to separate 20624them with semicolons as in this example. 20625 20626 A bundle may contain one or more instructions, up to the limit 20627specified by the ISA (currently three). If fewer instructions are 20628specified than the hardware supports in a bundle, the assembler inserts 20629'fnop' instructions automatically. 20630 20631 The assembler will prefer to preserve the ordering of instructions 20632within the bundle, putting the first instruction in a lower-numbered 20633pipeline than the next one, etc. This fact, combined with the optional 20634use of explicit 'fnop' or 'nop' instructions, allows precise control 20635over which pipeline executes each instruction. 20636 20637 If the instructions cannot be bundled in the listed order, the 20638assembler will automatically try to find a valid pipeline assignment. 20639If there is no way to bundle the instructions together, the assembler 20640reports an error. 20641 20642 The assembler does not yet auto-bundle (automatically combine 20643multiple instructions into one bundle), but it reserves the right to do 20644so in the future. If you want to force an instruction to run by itself, 20645put it in a bundle explicitly with curly braces and use 'nop' 20646instructions (not 'fnop') to fill the remaining pipeline slots in that 20647bundle. 20648 20649* Menu: 20650 20651* TILEPro Opcodes:: Opcode Naming Conventions. 20652* TILEPro Registers:: Register Naming. 20653* TILEPro Modifiers:: Symbolic Operand Modifiers. 20654 20655 20656File: as.info, Node: TILEPro Opcodes, Next: TILEPro Registers, Up: TILEPro Syntax 20657 206589.47.2.1 Opcode Names 20659..................... 20660 20661For a complete list of opcodes and descriptions of their semantics, see 20662'TILE Processor User Architecture Manual', available upon request at 20663www.tilera.com. 20664 20665 20666File: as.info, Node: TILEPro Registers, Next: TILEPro Modifiers, Prev: TILEPro Opcodes, Up: TILEPro Syntax 20667 206689.47.2.2 Register Names 20669....................... 20670 20671General-purpose registers are represented by predefined symbols of the 20672form 'rN', where N represents a number between '0' and '63'. However, 20673the following registers have canonical names that must be used instead: 20674 20675'r54' 20676 sp 20677 20678'r55' 20679 lr 20680 20681'r56' 20682 sn 20683 20684'r57' 20685 idn0 20686 20687'r58' 20688 idn1 20689 20690'r59' 20691 udn0 20692 20693'r60' 20694 udn1 20695 20696'r61' 20697 udn2 20698 20699'r62' 20700 udn3 20701 20702'r63' 20703 zero 20704 20705 The assembler will emit a warning if a numeric name is used instead 20706of the canonical name. The '.no_require_canonical_reg_names' assembler 20707pseudo-op turns off this warning. '.require_canonical_reg_names' turns 20708it back on. 20709 20710 20711File: as.info, Node: TILEPro Modifiers, Prev: TILEPro Registers, Up: TILEPro Syntax 20712 207139.47.2.3 Symbolic Operand Modifiers 20714................................... 20715 20716The assembler supports several modifiers when using symbol addresses in 20717TILEPro instruction operands. The general syntax is the following: 20718 20719 modifier(symbol) 20720 20721 The following modifiers are supported: 20722 20723'lo16' 20724 20725 This modifier is used to load the low 16 bits of the symbol's 20726 address, sign-extended to a 32-bit value (sign-extension allows it 20727 to be range-checked against signed 16 bit immediate operands 20728 without complaint). 20729 20730'hi16' 20731 20732 This modifier is used to load the high 16 bits of the symbol's 20733 address, also sign-extended to a 32-bit value. 20734 20735'ha16' 20736 20737 'ha16(N)' is identical to 'hi16(N)', except if 'lo16(N)' is 20738 negative it adds one to the 'hi16(N)' value. This way 'lo16' and 20739 'ha16' can be added to create any 32-bit value using 'auli'. For 20740 example, here is how you move an arbitrary 32-bit address into r3: 20741 20742 moveli r3, lo16(sym) 20743 auli r3, r3, ha16(sym) 20744 20745'got' 20746 20747 This modifier is used to load the offset of the GOT entry 20748 corresponding to the symbol. 20749 20750'got_lo16' 20751 20752 This modifier is used to load the sign-extended low 16 bits of the 20753 offset of the GOT entry corresponding to the symbol. 20754 20755'got_hi16' 20756 20757 This modifier is used to load the sign-extended high 16 bits of the 20758 offset of the GOT entry corresponding to the symbol. 20759 20760'got_ha16' 20761 20762 This modifier is like 'got_hi16', but it adds one if 'got_lo16' of 20763 the input value is negative. 20764 20765'plt' 20766 20767 This modifier is used for function symbols. It causes a _procedure 20768 linkage table_, an array of code stubs, to be created at the time 20769 the shared object is created or linked against, together with a 20770 global offset table entry. The value is a pc-relative offset to 20771 the corresponding stub code in the procedure linkage table. This 20772 arrangement causes the run-time symbol resolver to be called to 20773 look up and set the value of the symbol the first time the function 20774 is called (at latest; depending environment variables). It is only 20775 safe to leave the symbol unresolved this way if all references are 20776 function calls. 20777 20778'tls_gd' 20779 20780 This modifier is used to load the offset of the GOT entry of the 20781 symbol's TLS descriptor, to be used for general-dynamic TLS 20782 accesses. 20783 20784'tls_gd_lo16' 20785 20786 This modifier is used to load the sign-extended low 16 bits of the 20787 offset of the GOT entry of the symbol's TLS descriptor, to be used 20788 for general dynamic TLS accesses. 20789 20790'tls_gd_hi16' 20791 20792 This modifier is used to load the sign-extended high 16 bits of the 20793 offset of the GOT entry of the symbol's TLS descriptor, to be used 20794 for general dynamic TLS accesses. 20795 20796'tls_gd_ha16' 20797 20798 This modifier is like 'tls_gd_hi16', but it adds one to the value 20799 if 'tls_gd_lo16' of the input value is negative. 20800 20801'tls_ie' 20802 20803 This modifier is used to load the offset of the GOT entry 20804 containing the offset of the symbol's address from the TCB, to be 20805 used for initial-exec TLS accesses. 20806 20807'tls_ie_lo16' 20808 20809 This modifier is used to load the low 16 bits of the offset of the 20810 GOT entry containing the offset of the symbol's address from the 20811 TCB, to be used for initial-exec TLS accesses. 20812 20813'tls_ie_hi16' 20814 20815 This modifier is used to load the high 16 bits of the offset of the 20816 GOT entry containing the offset of the symbol's address from the 20817 TCB, to be used for initial-exec TLS accesses. 20818 20819'tls_ie_ha16' 20820 20821 This modifier is like 'tls_ie_hi16', but it adds one to the value 20822 if 'tls_ie_lo16' of the input value is negative. 20823 20824'tls_le' 20825 20826 This modifier is used to load the offset of the symbol's address 20827 from the TCB, to be used for local-exec TLS accesses. 20828 20829'tls_le_lo16' 20830 20831 This modifier is used to load the low 16 bits of the offset of the 20832 symbol's address from the TCB, to be used for local-exec TLS 20833 accesses. 20834 20835'tls_le_hi16' 20836 20837 This modifier is used to load the high 16 bits of the offset of the 20838 symbol's address from the TCB, to be used for local-exec TLS 20839 accesses. 20840 20841'tls_le_ha16' 20842 20843 This modifier is like 'tls_le_hi16', but it adds one to the value 20844 if 'tls_le_lo16' of the input value is negative. 20845 20846'tls_gd_call' 20847 20848 This modifier is used to tag an instrution as the "call" part of a 20849 calling sequence for a TLS GD reference of its operand. 20850 20851'tls_gd_add' 20852 20853 This modifier is used to tag an instruction as the "add" part of a 20854 calling sequence for a TLS GD reference of its operand. 20855 20856'tls_ie_load' 20857 20858 This modifier is used to tag an instruction as the "load" part of a 20859 calling sequence for a TLS IE reference of its operand. 20860 20861 20862File: as.info, Node: TILEPro Directives, Prev: TILEPro Syntax, Up: TILEPro-Dependent 20863 208649.47.3 TILEPro Directives 20865------------------------- 20866 20867'.align EXPRESSION [, EXPRESSION]' 20868 This is the generic .ALIGN directive. The first argument is the 20869 requested alignment in bytes. 20870 20871'.allow_suspicious_bundles' 20872 Turns on error checking for combinations of instructions in a 20873 bundle that probably indicate a programming error. This is on by 20874 default. 20875 20876'.no_allow_suspicious_bundles' 20877 Turns off error checking for combinations of instructions in a 20878 bundle that probably indicate a programming error. 20879 20880'.require_canonical_reg_names' 20881 Require that canonical register names be used, and emit a warning 20882 if the numeric names are used. This is on by default. 20883 20884'.no_require_canonical_reg_names' 20885 Permit the use of numeric names for registers that have canonical 20886 names. 20887 20888 20889File: as.info, Node: V850-Dependent, Next: Vax-Dependent, Prev: TILEPro-Dependent, Up: Machine Dependencies 20890 208919.48 v850 Dependent Features 20892============================ 20893 20894* Menu: 20895 20896* V850 Options:: Options 20897* V850 Syntax:: Syntax 20898* V850 Floating Point:: Floating Point 20899* V850 Directives:: V850 Machine Directives 20900* V850 Opcodes:: Opcodes 20901 20902 20903File: as.info, Node: V850 Options, Next: V850 Syntax, Up: V850-Dependent 20904 209059.48.1 Options 20906-------------- 20907 20908'as' supports the following additional command-line options for the V850 20909processor family: 20910 20911'-wsigned_overflow' 20912 Causes warnings to be produced when signed immediate values 20913 overflow the space available for then within their opcodes. By 20914 default this option is disabled as it is possible to receive 20915 spurious warnings due to using exact bit patterns as immediate 20916 constants. 20917 20918'-wunsigned_overflow' 20919 Causes warnings to be produced when unsigned immediate values 20920 overflow the space available for then within their opcodes. By 20921 default this option is disabled as it is possible to receive 20922 spurious warnings due to using exact bit patterns as immediate 20923 constants. 20924 20925'-mv850' 20926 Specifies that the assembled code should be marked as being 20927 targeted at the V850 processor. This allows the linker to detect 20928 attempts to link such code with code assembled for other 20929 processors. 20930 20931'-mv850e' 20932 Specifies that the assembled code should be marked as being 20933 targeted at the V850E processor. This allows the linker to detect 20934 attempts to link such code with code assembled for other 20935 processors. 20936 20937'-mv850e1' 20938 Specifies that the assembled code should be marked as being 20939 targeted at the V850E1 processor. This allows the linker to detect 20940 attempts to link such code with code assembled for other 20941 processors. 20942 20943'-mv850any' 20944 Specifies that the assembled code should be marked as being 20945 targeted at the V850 processor but support instructions that are 20946 specific to the extended variants of the process. This allows the 20947 production of binaries that contain target specific code, but which 20948 are also intended to be used in a generic fashion. For example 20949 libgcc.a contains generic routines used by the code produced by GCC 20950 for all versions of the v850 architecture, together with support 20951 routines only used by the V850E architecture. 20952 20953'-mv850e2' 20954 Specifies that the assembled code should be marked as being 20955 targeted at the V850E2 processor. This allows the linker to detect 20956 attempts to link such code with code assembled for other 20957 processors. 20958 20959'-mv850e2v3' 20960 Specifies that the assembled code should be marked as being 20961 targeted at the V850E2V3 processor. This allows the linker to 20962 detect attempts to link such code with code assembled for other 20963 processors. 20964 20965'-mv850e2v4' 20966 This is an alias for '-mv850e3v5'. 20967 20968'-mv850e3v5' 20969 Specifies that the assembled code should be marked as being 20970 targeted at the V850E3V5 processor. This allows the linker to 20971 detect attempts to link such code with code assembled for other 20972 processors. 20973 20974'-mrelax' 20975 Enables relaxation. This allows the .longcall and .longjump pseudo 20976 ops to be used in the assembler source code. These ops label 20977 sections of code which are either a long function call or a long 20978 branch. The assembler will then flag these sections of code and 20979 the linker will attempt to relax them. 20980 20981'-mgcc-abi' 20982 Marks the generated object file as supporting the old GCC ABI. 20983 20984'-mrh850-abi' 20985 Marks the generated object file as supporting the RH850 ABI. This 20986 is the default. 20987 20988'-m8byte-align' 20989 Marks the generated object file as supporting a maximum 64-bits of 20990 alignment for variables defined in the source code. 20991 20992'-m4byte-align' 20993 Marks the generated object file as supporting a maximum 32-bits of 20994 alignment for variables defined in the source code. This is the 20995 default. 20996 20997'-msoft-float' 20998 Marks the generated object file as not using any floating point 20999 instructions - and hence can be linked with other V850 binaries 21000 that do or do not use floating point. This is the default for 21001 binaries for architectures earlier than the 'e2v3'. 21002 21003'-mhard-float' 21004 Marks the generated object file as one that uses floating point 21005 instructions - and hence can only be linked with other V850 21006 binaries that use the same kind of floating point instructions, or 21007 with binaries that do not use floating point at all. This is the 21008 default for binaries the 'e2v3' and later architectures. 21009 21010 21011File: as.info, Node: V850 Syntax, Next: V850 Floating Point, Prev: V850 Options, Up: V850-Dependent 21012 210139.48.2 Syntax 21014------------- 21015 21016* Menu: 21017 21018* V850-Chars:: Special Characters 21019* V850-Regs:: Register Names 21020 21021 21022File: as.info, Node: V850-Chars, Next: V850-Regs, Up: V850 Syntax 21023 210249.48.2.1 Special Characters 21025........................... 21026 21027'#' is the line comment character. If a '#' appears as the first 21028character of a line, the whole line is treated as a comment, but in this 21029case the line can also be a logical line number directive (*note 21030Comments::) or a preprocessor control command (*note Preprocessing::). 21031 21032 Two dashes ('--') can also be used to start a line comment. 21033 21034 The ';' character can be used to separate statements on the same 21035line. 21036 21037 21038File: as.info, Node: V850-Regs, Prev: V850-Chars, Up: V850 Syntax 21039 210409.48.2.2 Register Names 21041....................... 21042 21043'as' supports the following names for registers: 21044'general register 0' 21045 r0, zero 21046'general register 1' 21047 r1 21048'general register 2' 21049 r2, hp 21050'general register 3' 21051 r3, sp 21052'general register 4' 21053 r4, gp 21054'general register 5' 21055 r5, tp 21056'general register 6' 21057 r6 21058'general register 7' 21059 r7 21060'general register 8' 21061 r8 21062'general register 9' 21063 r9 21064'general register 10' 21065 r10 21066'general register 11' 21067 r11 21068'general register 12' 21069 r12 21070'general register 13' 21071 r13 21072'general register 14' 21073 r14 21074'general register 15' 21075 r15 21076'general register 16' 21077 r16 21078'general register 17' 21079 r17 21080'general register 18' 21081 r18 21082'general register 19' 21083 r19 21084'general register 20' 21085 r20 21086'general register 21' 21087 r21 21088'general register 22' 21089 r22 21090'general register 23' 21091 r23 21092'general register 24' 21093 r24 21094'general register 25' 21095 r25 21096'general register 26' 21097 r26 21098'general register 27' 21099 r27 21100'general register 28' 21101 r28 21102'general register 29' 21103 r29 21104'general register 30' 21105 r30, ep 21106'general register 31' 21107 r31, lp 21108'system register 0' 21109 eipc 21110'system register 1' 21111 eipsw 21112'system register 2' 21113 fepc 21114'system register 3' 21115 fepsw 21116'system register 4' 21117 ecr 21118'system register 5' 21119 psw 21120'system register 16' 21121 ctpc 21122'system register 17' 21123 ctpsw 21124'system register 18' 21125 dbpc 21126'system register 19' 21127 dbpsw 21128'system register 20' 21129 ctbp 21130 21131 21132File: as.info, Node: V850 Floating Point, Next: V850 Directives, Prev: V850 Syntax, Up: V850-Dependent 21133 211349.48.3 Floating Point 21135--------------------- 21136 21137The V850 family uses IEEE floating-point numbers. 21138 21139 21140File: as.info, Node: V850 Directives, Next: V850 Opcodes, Prev: V850 Floating Point, Up: V850-Dependent 21141 211429.48.4 V850 Machine Directives 21143------------------------------ 21144 21145'.offset <EXPRESSION>' 21146 Moves the offset into the current section to the specified amount. 21147 21148'.section "name", <type>' 21149 This is an extension to the standard .section directive. It sets 21150 the current section to be <type> and creates an alias for this 21151 section called "name". 21152 21153'.v850' 21154 Specifies that the assembled code should be marked as being 21155 targeted at the V850 processor. This allows the linker to detect 21156 attempts to link such code with code assembled for other 21157 processors. 21158 21159'.v850e' 21160 Specifies that the assembled code should be marked as being 21161 targeted at the V850E processor. This allows the linker to detect 21162 attempts to link such code with code assembled for other 21163 processors. 21164 21165'.v850e1' 21166 Specifies that the assembled code should be marked as being 21167 targeted at the V850E1 processor. This allows the linker to detect 21168 attempts to link such code with code assembled for other 21169 processors. 21170 21171'.v850e2' 21172 Specifies that the assembled code should be marked as being 21173 targeted at the V850E2 processor. This allows the linker to detect 21174 attempts to link such code with code assembled for other 21175 processors. 21176 21177'.v850e2v3' 21178 Specifies that the assembled code should be marked as being 21179 targeted at the V850E2V3 processor. This allows the linker to 21180 detect attempts to link such code with code assembled for other 21181 processors. 21182 21183'.v850e2v4' 21184 Specifies that the assembled code should be marked as being 21185 targeted at the V850E3V5 processor. This allows the linker to 21186 detect attempts to link such code with code assembled for other 21187 processors. 21188 21189'.v850e3v5' 21190 Specifies that the assembled code should be marked as being 21191 targeted at the V850E3V5 processor. This allows the linker to 21192 detect attempts to link such code with code assembled for other 21193 processors. 21194 21195 21196File: as.info, Node: V850 Opcodes, Prev: V850 Directives, Up: V850-Dependent 21197 211989.48.5 Opcodes 21199-------------- 21200 21201'as' implements all the standard V850 opcodes. 21202 21203 'as' also implements the following pseudo ops: 21204 21205'hi0()' 21206 Computes the higher 16 bits of the given expression and stores it 21207 into the immediate operand field of the given instruction. For 21208 example: 21209 21210 'mulhi hi0(here - there), r5, r6' 21211 21212 computes the difference between the address of labels 'here' and 21213 'there', takes the upper 16 bits of this difference, shifts it down 21214 16 bits and then multiplies it by the lower 16 bits in register 5, 21215 putting the result into register 6. 21216 21217'lo()' 21218 Computes the lower 16 bits of the given expression and stores it 21219 into the immediate operand field of the given instruction. For 21220 example: 21221 21222 'addi lo(here - there), r5, r6' 21223 21224 computes the difference between the address of labels 'here' and 21225 'there', takes the lower 16 bits of this difference and adds it to 21226 register 5, putting the result into register 6. 21227 21228'hi()' 21229 Computes the higher 16 bits of the given expression and then adds 21230 the value of the most significant bit of the lower 16 bits of the 21231 expression and stores the result into the immediate operand field 21232 of the given instruction. For example the following code can be 21233 used to compute the address of the label 'here' and store it into 21234 register 6: 21235 21236 'movhi hi(here), r0, r6' 'movea lo(here), r6, r6' 21237 21238 The reason for this special behaviour is that movea performs a sign 21239 extension on its immediate operand. So for example if the address 21240 of 'here' was 0xFFFFFFFF then without the special behaviour of the 21241 hi() pseudo-op the movhi instruction would put 0xFFFF0000 into r6, 21242 then the movea instruction would takes its immediate operand, 21243 0xFFFF, sign extend it to 32 bits, 0xFFFFFFFF, and then add it into 21244 r6 giving 0xFFFEFFFF which is wrong (the fifth nibble is E). With 21245 the hi() pseudo op adding in the top bit of the lo() pseudo op, the 21246 movhi instruction actually stores 0 into r6 (0xFFFF + 1 = 0x0000), 21247 so that the movea instruction stores 0xFFFFFFFF into r6 - the right 21248 value. 21249 21250'hilo()' 21251 Computes the 32 bit value of the given expression and stores it 21252 into the immediate operand field of the given instruction (which 21253 must be a mov instruction). For example: 21254 21255 'mov hilo(here), r6' 21256 21257 computes the absolute address of label 'here' and puts the result 21258 into register 6. 21259 21260'sdaoff()' 21261 Computes the offset of the named variable from the start of the 21262 Small Data Area (whoes address is held in register 4, the GP 21263 register) and stores the result as a 16 bit signed value in the 21264 immediate operand field of the given instruction. For example: 21265 21266 'ld.w sdaoff(_a_variable)[gp],r6' 21267 21268 loads the contents of the location pointed to by the label 21269 '_a_variable' into register 6, provided that the label is located 21270 somewhere within +/- 32K of the address held in the GP register. 21271 [Note the linker assumes that the GP register contains a fixed 21272 address set to the address of the label called '__gp'. This can 21273 either be set up automatically by the linker, or specifically set 21274 by using the '--defsym __gp=<value>' command line option]. 21275 21276'tdaoff()' 21277 Computes the offset of the named variable from the start of the 21278 Tiny Data Area (whoes address is held in register 30, the EP 21279 register) and stores the result as a 4,5, 7 or 8 bit unsigned value 21280 in the immediate operand field of the given instruction. For 21281 example: 21282 21283 'sld.w tdaoff(_a_variable)[ep],r6' 21284 21285 loads the contents of the location pointed to by the label 21286 '_a_variable' into register 6, provided that the label is located 21287 somewhere within +256 bytes of the address held in the EP register. 21288 [Note the linker assumes that the EP register contains a fixed 21289 address set to the address of the label called '__ep'. This can 21290 either be set up automatically by the linker, or specifically set 21291 by using the '--defsym __ep=<value>' command line option]. 21292 21293'zdaoff()' 21294 Computes the offset of the named variable from address 0 and stores 21295 the result as a 16 bit signed value in the immediate operand field 21296 of the given instruction. For example: 21297 21298 'movea zdaoff(_a_variable),zero,r6' 21299 21300 puts the address of the label '_a_variable' into register 6, 21301 assuming that the label is somewhere within the first 32K of 21302 memory. (Strictly speaking it also possible to access the last 32K 21303 of memory as well, as the offsets are signed). 21304 21305'ctoff()' 21306 Computes the offset of the named variable from the start of the 21307 Call Table Area (whoes address is helg in system register 20, the 21308 CTBP register) and stores the result a 6 or 16 bit unsigned value 21309 in the immediate field of then given instruction or piece of data. 21310 For example: 21311 21312 'callt ctoff(table_func1)' 21313 21314 will put the call the function whoes address is held in the call 21315 table at the location labeled 'table_func1'. 21316 21317'.longcall name' 21318 Indicates that the following sequence of instructions is a long 21319 call to function 'name'. The linker will attempt to shorten this 21320 call sequence if 'name' is within a 22bit offset of the call. Only 21321 valid if the '-mrelax' command line switch has been enabled. 21322 21323'.longjump name' 21324 Indicates that the following sequence of instructions is a long 21325 jump to label 'name'. The linker will attempt to shorten this code 21326 sequence if 'name' is within a 22bit offset of the jump. Only 21327 valid if the '-mrelax' command line switch has been enabled. 21328 21329 For information on the V850 instruction set, see 'V850 Family 2133032-/16-Bit single-Chip Microcontroller Architecture Manual' from NEC. 21331Ltd. 21332 21333 21334File: as.info, Node: Vax-Dependent, Next: Visium-Dependent, Prev: V850-Dependent, Up: Machine Dependencies 21335 213369.49 VAX Dependent Features 21337=========================== 21338 21339* Menu: 21340 21341* VAX-Opts:: VAX Command-Line Options 21342* VAX-float:: VAX Floating Point 21343* VAX-directives:: Vax Machine Directives 21344* VAX-opcodes:: VAX Opcodes 21345* VAX-branch:: VAX Branch Improvement 21346* VAX-operands:: VAX Operands 21347* VAX-no:: Not Supported on VAX 21348* VAX-Syntax:: VAX Syntax 21349 21350 21351File: as.info, Node: VAX-Opts, Next: VAX-float, Up: Vax-Dependent 21352 213539.49.1 VAX Command-Line Options 21354------------------------------- 21355 21356The Vax version of 'as' accepts any of the following options, gives a 21357warning message that the option was ignored and proceeds. These options 21358are for compatibility with scripts designed for other people's 21359assemblers. 21360 21361'-D (Debug)' 21362'-S (Symbol Table)' 21363'-T (Token Trace)' 21364 These are obsolete options used to debug old assemblers. 21365 21366'-d (Displacement size for JUMPs)' 21367 This option expects a number following the '-d'. Like options that 21368 expect filenames, the number may immediately follow the '-d' (old 21369 standard) or constitute the whole of the command line argument that 21370 follows '-d' (GNU standard). 21371 21372'-V (Virtualize Interpass Temporary File)' 21373 Some other assemblers use a temporary file. This option commanded 21374 them to keep the information in active memory rather than in a disk 21375 file. 'as' always does this, so this option is redundant. 21376 21377'-J (JUMPify Longer Branches)' 21378 Many 32-bit computers permit a variety of branch instructions to do 21379 the same job. Some of these instructions are short (and fast) but 21380 have a limited range; others are long (and slow) but can branch 21381 anywhere in virtual memory. Often there are 3 flavors of branch: 21382 short, medium and long. Some other assemblers would emit short and 21383 medium branches, unless told by this option to emit short and long 21384 branches. 21385 21386'-t (Temporary File Directory)' 21387 Some other assemblers may use a temporary file, and this option 21388 takes a filename being the directory to site the temporary file. 21389 Since 'as' does not use a temporary disk file, this option makes no 21390 difference. '-t' needs exactly one filename. 21391 21392 The Vax version of the assembler accepts additional options when 21393compiled for VMS: 21394 21395'-h N' 21396 External symbol or section (used for global variables) names are 21397 not case sensitive on VAX/VMS and always mapped to upper case. 21398 This is contrary to the C language definition which explicitly 21399 distinguishes upper and lower case. To implement a standard 21400 conforming C compiler, names must be changed (mapped) to preserve 21401 the case information. The default mapping is to convert all lower 21402 case characters to uppercase and adding an underscore followed by a 21403 6 digit hex value, representing a 24 digit binary value. The one 21404 digits in the binary value represent which characters are uppercase 21405 in the original symbol name. 21406 21407 The '-h N' option determines how we map names. This takes several 21408 values. No '-h' switch at all allows case hacking as described 21409 above. A value of zero ('-h0') implies names should be upper case, 21410 and inhibits the case hack. A value of 2 ('-h2') implies names 21411 should be all lower case, with no case hack. A value of 3 ('-h3') 21412 implies that case should be preserved. The value 1 is unused. The 21413 '-H' option directs 'as' to display every mapped symbol during 21414 assembly. 21415 21416 Symbols whose names include a dollar sign '$' are exceptions to the 21417 general name mapping. These symbols are normally only used to 21418 reference VMS library names. Such symbols are always mapped to 21419 upper case. 21420 21421'-+' 21422 The '-+' option causes 'as' to truncate any symbol name larger than 21423 31 characters. The '-+' option also prevents some code following 21424 the '_main' symbol normally added to make the object file 21425 compatible with Vax-11 "C". 21426 21427'-1' 21428 This option is ignored for backward compatibility with 'as' version 21429 1.x. 21430 21431'-H' 21432 The '-H' option causes 'as' to print every symbol which was changed 21433 by case mapping. 21434 21435 21436File: as.info, Node: VAX-float, Next: VAX-directives, Prev: VAX-Opts, Up: Vax-Dependent 21437 214389.49.2 VAX Floating Point 21439------------------------- 21440 21441Conversion of flonums to floating point is correct, and compatible with 21442previous assemblers. Rounding is towards zero if the remainder is 21443exactly half the least significant bit. 21444 21445 'D', 'F', 'G' and 'H' floating point formats are understood. 21446 21447 Immediate floating literals (_e.g._ 'S`$6.9') are rendered 21448correctly. Again, rounding is towards zero in the boundary case. 21449 21450 The '.float' directive produces 'f' format numbers. The '.double' 21451directive produces 'd' format numbers. 21452 21453 21454File: as.info, Node: VAX-directives, Next: VAX-opcodes, Prev: VAX-float, Up: Vax-Dependent 21455 214569.49.3 Vax Machine Directives 21457----------------------------- 21458 21459The Vax version of the assembler supports four directives for generating 21460Vax floating point constants. They are described in the table below. 21461 21462'.dfloat' 21463 This expects zero or more flonums, separated by commas, and 21464 assembles Vax 'd' format 64-bit floating point constants. 21465 21466'.ffloat' 21467 This expects zero or more flonums, separated by commas, and 21468 assembles Vax 'f' format 32-bit floating point constants. 21469 21470'.gfloat' 21471 This expects zero or more flonums, separated by commas, and 21472 assembles Vax 'g' format 64-bit floating point constants. 21473 21474'.hfloat' 21475 This expects zero or more flonums, separated by commas, and 21476 assembles Vax 'h' format 128-bit floating point constants. 21477 21478 21479File: as.info, Node: VAX-opcodes, Next: VAX-branch, Prev: VAX-directives, Up: Vax-Dependent 21480 214819.49.4 VAX Opcodes 21482------------------ 21483 21484All DEC mnemonics are supported. Beware that 'case...' instructions 21485have exactly 3 operands. The dispatch table that follows the 'case...' 21486instruction should be made with '.word' statements. This is compatible 21487with all unix assemblers we know of. 21488 21489 21490File: as.info, Node: VAX-branch, Next: VAX-operands, Prev: VAX-opcodes, Up: Vax-Dependent 21491 214929.49.5 VAX Branch Improvement 21493----------------------------- 21494 21495Certain pseudo opcodes are permitted. They are for branch instructions. 21496They expand to the shortest branch instruction that reaches the target. 21497Generally these mnemonics are made by substituting 'j' for 'b' at the 21498start of a DEC mnemonic. This feature is included both for 21499compatibility and to help compilers. If you do not need this feature, 21500avoid these opcodes. Here are the mnemonics, and the code they can 21501expand into. 21502 21503'jbsb' 21504 'Jsb' is already an instruction mnemonic, so we chose 'jbsb'. 21505 (byte displacement) 21506 'bsbb ...' 21507 (word displacement) 21508 'bsbw ...' 21509 (long displacement) 21510 'jsb ...' 21511'jbr' 21512'jr' 21513 Unconditional branch. 21514 (byte displacement) 21515 'brb ...' 21516 (word displacement) 21517 'brw ...' 21518 (long displacement) 21519 'jmp ...' 21520'jCOND' 21521 COND may be any one of the conditional branches 'neq', 'nequ', 21522 'eql', 'eqlu', 'gtr', 'geq', 'lss', 'gtru', 'lequ', 'vc', 'vs', 21523 'gequ', 'cc', 'lssu', 'cs'. COND may also be one of the bit tests 21524 'bs', 'bc', 'bss', 'bcs', 'bsc', 'bcc', 'bssi', 'bcci', 'lbs', 21525 'lbc'. NOTCOND is the opposite condition to COND. 21526 (byte displacement) 21527 'bCOND ...' 21528 (word displacement) 21529 'bNOTCOND foo ; brw ... ; foo:' 21530 (long displacement) 21531 'bNOTCOND foo ; jmp ... ; foo:' 21532'jacbX' 21533 X may be one of 'b d f g h l w'. 21534 (word displacement) 21535 'OPCODE ...' 21536 (long displacement) 21537 OPCODE ..., foo ; 21538 brb bar ; 21539 foo: jmp ... ; 21540 bar: 21541'jaobYYY' 21542 YYY may be one of 'lss leq'. 21543'jsobZZZ' 21544 ZZZ may be one of 'geq gtr'. 21545 (byte displacement) 21546 'OPCODE ...' 21547 (word displacement) 21548 OPCODE ..., foo ; 21549 brb bar ; 21550 foo: brw DESTINATION ; 21551 bar: 21552 (long displacement) 21553 OPCODE ..., foo ; 21554 brb bar ; 21555 foo: jmp DESTINATION ; 21556 bar: 21557'aobleq' 21558'aoblss' 21559'sobgeq' 21560'sobgtr' 21561 (byte displacement) 21562 'OPCODE ...' 21563 (word displacement) 21564 OPCODE ..., foo ; 21565 brb bar ; 21566 foo: brw DESTINATION ; 21567 bar: 21568 (long displacement) 21569 OPCODE ..., foo ; 21570 brb bar ; 21571 foo: jmp DESTINATION ; 21572 bar: 21573 21574 21575File: as.info, Node: VAX-operands, Next: VAX-no, Prev: VAX-branch, Up: Vax-Dependent 21576 215779.49.6 VAX Operands 21578------------------- 21579 21580The immediate character is '$' for Unix compatibility, not '#' as DEC 21581writes it. 21582 21583 The indirect character is '*' for Unix compatibility, not '@' as DEC 21584writes it. 21585 21586 The displacement sizing character is '`' (an accent grave) for Unix 21587compatibility, not '^' as DEC writes it. The letter preceding '`' may 21588have either case. 'G' is not understood, but all other letters ('b i l 21589s w') are understood. 21590 21591 Register names understood are 'r0 r1 r2 ... r15 ap fp sp pc'. Upper 21592and lower case letters are equivalent. 21593 21594 For instance 21595 tstb *w`$4(r5) 21596 21597 Any expression is permitted in an operand. Operands are comma 21598separated. 21599 21600 21601File: as.info, Node: VAX-no, Next: VAX-Syntax, Prev: VAX-operands, Up: Vax-Dependent 21602 216039.49.7 Not Supported on VAX 21604--------------------------- 21605 21606Vax bit fields can not be assembled with 'as'. Someone can add the 21607required code if they really need it. 21608 21609 21610File: as.info, Node: VAX-Syntax, Prev: VAX-no, Up: Vax-Dependent 21611 216129.49.8 VAX Syntax 21613----------------- 21614 21615* Menu: 21616 21617* VAX-Chars:: Special Characters 21618 21619 21620File: as.info, Node: VAX-Chars, Up: VAX-Syntax 21621 216229.49.8.1 Special Characters 21623........................... 21624 21625The presence of a '#' appearing anywhere on a line indicates the start 21626of a comment that extends to the end of that line. 21627 21628 If a '#' appears as the first character of a line then the whole line 21629is treated as a comment, but in this case the line can also be a logical 21630line number directive (*note Comments::) or a preprocessor control 21631command (*note Preprocessing::). 21632 21633 The ';' character can be used to separate statements on the same 21634line. 21635 21636 21637File: as.info, Node: Visium-Dependent, Next: XGATE-Dependent, Prev: Vax-Dependent, Up: Machine Dependencies 21638 216399.50 Visium Dependent Features 21640============================== 21641 21642* Menu: 21643 21644* Visium Options:: Options 21645* Visium Syntax:: Syntax 21646* Visium Opcodes:: Opcodes 21647 21648 21649File: as.info, Node: Visium Options, Next: Visium Syntax, Up: Visium-Dependent 21650 216519.50.1 Options 21652-------------- 21653 21654The Visium assembler implements one machine-specific option: 21655 21656'-mtune=ARCH' 21657 This option specifies the target architecture. If an attempt is 21658 made to assemble an instruction that will not execute on the target 21659 architecture, the assembler will issue an error message. 21660 21661 The following names are recognized: 'mcm24' 'mcm' 'gr5' 'gr6' 21662 21663 21664File: as.info, Node: Visium Syntax, Next: Visium Opcodes, Prev: Visium Options, Up: Visium-Dependent 21665 216669.50.2 Syntax 21667------------- 21668 21669* Menu: 21670 21671* Visium Characters:: Special Characters 21672* Visium Registers:: Register Names 21673 21674 21675File: as.info, Node: Visium Characters, Next: Visium Registers, Up: Visium Syntax 21676 216779.50.2.1 Special Characters 21678........................... 21679 21680Line comments are introduced either by the '!' character or by the ';' 21681character appearing anywhere on a line. 21682 21683 A hash character ('#') as the first character on a line also marks 21684the start of a line comment, but in this case it could also be a logical 21685line number directive (*note Comments::) or a preprocessor control 21686command (*note Preprocessing::). 21687 21688 The Visium assembler does not currently support a line separator 21689character. 21690 21691 21692File: as.info, Node: Visium Registers, Prev: Visium Characters, Up: Visium Syntax 21693 216949.50.2.2 Register Names 21695....................... 21696 21697Registers can be specified either by using their canonical mnemonic 21698names or by using their alias if they have one, for example 'sp'. 21699 21700 21701File: as.info, Node: Visium Opcodes, Prev: Visium Syntax, Up: Visium-Dependent 21702 217039.50.3 Opcodes 21704-------------- 21705 21706All the standard opcodes of the architecture are implemented, along with 21707the following three pseudo-instructions: 'cmp', 'cmpc', 'move'. 21708 21709 In addition, the following two illegal opcodes are implemented and 21710used by the simulation: 21711 21712 stop 5-bit immediate, SourceA 21713 trace 5-bit immediate, SourceA 21714 21715 21716File: as.info, Node: XGATE-Dependent, Next: XSTORMY16-Dependent, Prev: Visium-Dependent, Up: Machine Dependencies 21717 217189.51 XGATE Dependent Features 21719============================= 21720 21721* Menu: 21722 21723* XGATE-Opts:: XGATE Options 21724* XGATE-Syntax:: Syntax 21725* XGATE-Directives:: Assembler Directives 21726* XGATE-Float:: Floating Point 21727* XGATE-opcodes:: Opcodes 21728 21729 21730File: as.info, Node: XGATE-Opts, Next: XGATE-Syntax, Up: XGATE-Dependent 21731 217329.51.1 XGATE Options 21733-------------------- 21734 21735The Freescale XGATE version of 'as' has a few machine dependent options. 21736 21737'-mshort' 21738 This option controls the ABI and indicates to use a 16-bit integer 21739 ABI. It has no effect on the assembled instructions. This is the 21740 default. 21741 21742'-mlong' 21743 This option controls the ABI and indicates to use a 32-bit integer 21744 ABI. 21745 21746'-mshort-double' 21747 This option controls the ABI and indicates to use a 32-bit float 21748 ABI. This is the default. 21749 21750'-mlong-double' 21751 This option controls the ABI and indicates to use a 64-bit float 21752 ABI. 21753 21754'--print-insn-syntax' 21755 You can use the '--print-insn-syntax' option to obtain the syntax 21756 description of the instruction when an error is detected. 21757 21758'--print-opcodes' 21759 The '--print-opcodes' option prints the list of all the 21760 instructions with their syntax. Once the list is printed 'as' 21761 exits. 21762 21763 21764File: as.info, Node: XGATE-Syntax, Next: XGATE-Directives, Prev: XGATE-Opts, Up: XGATE-Dependent 21765 217669.51.2 Syntax 21767------------- 21768 21769In XGATE RISC syntax, the instruction name comes first and it may be 21770followed by up to three operands. Operands are separated by commas 21771(','). 'as' will complain if too many operands are specified for a 21772given instruction. The same will happen if you specified too few 21773operands. 21774 21775 nop 21776 ldl #23 21777 CMP R1, R2 21778 21779 The presence of a ';' character or a '!' character anywhere on a line 21780indicates the start of a comment that extends to the end of that line. 21781 21782 A '*' or a '#' character at the start of a line also introduces a 21783line comment, but these characters do not work elsewhere on the line. 21784If the first character of the line is a '#' then as well as starting a 21785comment, the line could also be logical line number directive (*note 21786Comments::) or a preprocessor control command (*note Preprocessing::). 21787 21788 The XGATE assembler does not currently support a line separator 21789character. 21790 21791 The following addressing modes are understood for XGATE: 21792"Inherent" 21793 '' 21794 21795"Immediate 3 Bit Wide" 21796 '#NUMBER' 21797 21798"Immediate 4 Bit Wide" 21799 '#NUMBER' 21800 21801"Immediate 8 Bit Wide" 21802 '#NUMBER' 21803 21804"Monadic Addressing" 21805 'REG' 21806 21807"Dyadic Addressing" 21808 'REG, REG' 21809 21810"Triadic Addressing" 21811 'REG, REG, REG' 21812 21813"Relative Addressing 9 Bit Wide" 21814 '*SYMBOL' 21815 21816"Relative Addressing 10 Bit Wide" 21817 '*SYMBOL' 21818 21819"Index Register plus Immediate Offset" 21820 'REG, (REG, #NUMBER)' 21821 21822"Index Register plus Register Offset" 21823 'REG, REG, REG' 21824 21825"Index Register plus Register Offset with Post-increment" 21826 'REG, REG, REG+' 21827 21828"Index Register plus Register Offset with Pre-decrement" 21829 'REG, REG, -REG' 21830 21831 The register can be either 'R0', 'R1', 'R2', 'R3', 'R4', 'R5', 'R6' 21832 or 'R7'. 21833 21834 Convience macro opcodes to deal with 16-bit values have been added. 21835 21836"Immediate 16 Bit Wide" 21837 '#NUMBER', or '*SYMBOL' 21838 21839 For example: 21840 21841 ldw R1, #1024 21842 ldw R3, timer 21843 ldw R1, (R1, #0) 21844 COM R1 21845 stw R2, (R1, #0) 21846 21847 21848File: as.info, Node: XGATE-Directives, Next: XGATE-Float, Prev: XGATE-Syntax, Up: XGATE-Dependent 21849 218509.51.3 Assembler Directives 21851--------------------------- 21852 21853The XGATE version of 'as' have the following specific assembler 21854directives: 21855 21856 21857File: as.info, Node: XGATE-Float, Next: XGATE-opcodes, Prev: XGATE-Directives, Up: XGATE-Dependent 21858 218599.51.4 Floating Point 21860--------------------- 21861 21862Packed decimal (P) format floating literals are not supported(yet). 21863 21864 The floating point formats generated by directives are these. 21865 21866'.float' 21867 'Single' precision floating point constants. 21868 21869'.double' 21870 'Double' precision floating point constants. 21871 21872'.extend' 21873'.ldouble' 21874 'Extended' precision ('long double') floating point constants. 21875 21876 21877File: as.info, Node: XGATE-opcodes, Prev: XGATE-Float, Up: XGATE-Dependent 21878 218799.51.5 Opcodes 21880-------------- 21881 21882 21883File: as.info, Node: XSTORMY16-Dependent, Next: Xtensa-Dependent, Prev: XGATE-Dependent, Up: Machine Dependencies 21884 218859.52 XStormy16 Dependent Features 21886================================= 21887 21888* Menu: 21889 21890* XStormy16 Syntax:: Syntax 21891* XStormy16 Directives:: Machine Directives 21892* XStormy16 Opcodes:: Pseudo-Opcodes 21893 21894 21895File: as.info, Node: XStormy16 Syntax, Next: XStormy16 Directives, Up: XSTORMY16-Dependent 21896 218979.52.1 Syntax 21898------------- 21899 21900* Menu: 21901 21902* XStormy16-Chars:: Special Characters 21903 21904 21905File: as.info, Node: XStormy16-Chars, Up: XStormy16 Syntax 21906 219079.52.1.1 Special Characters 21908........................... 21909 21910'#' is the line comment character. If a '#' appears as the first 21911character of a line, the whole line is treated as a comment, but in this 21912case the line can also be a logical line number directive (*note 21913Comments::) or a preprocessor control command (*note Preprocessing::). 21914 21915 A semicolon (';') can be used to start a comment that extends from 21916wherever the character appears on the line up to the end of the line. 21917 21918 The '|' character can be used to separate statements on the same 21919line. 21920 21921 21922File: as.info, Node: XStormy16 Directives, Next: XStormy16 Opcodes, Prev: XStormy16 Syntax, Up: XSTORMY16-Dependent 21923 219249.52.2 XStormy16 Machine Directives 21925----------------------------------- 21926 21927'.16bit_pointers' 21928 Like the '--16bit-pointers' command line option this directive 21929 indicates that the assembly code makes use of 16-bit pointers. 21930 21931'.32bit_pointers' 21932 Like the '--32bit-pointers' command line option this directive 21933 indicates that the assembly code makes use of 32-bit pointers. 21934 21935'.no_pointers' 21936 Like the '--no-pointers' command line option this directive 21937 indicates that the assembly code does not makes use pointers. 21938 21939 21940File: as.info, Node: XStormy16 Opcodes, Prev: XStormy16 Directives, Up: XSTORMY16-Dependent 21941 219429.52.3 XStormy16 Pseudo-Opcodes 21943------------------------------- 21944 21945'as' implements all the standard XStormy16 opcodes. 21946 21947 'as' also implements the following pseudo ops: 21948 21949'@lo()' 21950 Computes the lower 16 bits of the given expression and stores it 21951 into the immediate operand field of the given instruction. For 21952 example: 21953 21954 'add r6, @lo(here - there)' 21955 21956 computes the difference between the address of labels 'here' and 21957 'there', takes the lower 16 bits of this difference and adds it to 21958 register 6. 21959 21960'@hi()' 21961 Computes the higher 16 bits of the given expression and stores it 21962 into the immediate operand field of the given instruction. For 21963 example: 21964 21965 'addc r7, @hi(here - there)' 21966 21967 computes the difference between the address of labels 'here' and 21968 'there', takes the upper 16 bits of this difference, shifts it down 21969 16 bits and then adds it, along with the carry bit, to the value in 21970 register 7. 21971 21972 21973File: as.info, Node: Xtensa-Dependent, Next: Z80-Dependent, Prev: XSTORMY16-Dependent, Up: Machine Dependencies 21974 219759.53 Xtensa Dependent Features 21976============================== 21977 21978This chapter covers features of the GNU assembler that are specific to 21979the Xtensa architecture. For details about the Xtensa instruction set, 21980please consult the 'Xtensa Instruction Set Architecture (ISA) Reference 21981Manual'. 21982 21983* Menu: 21984 21985* Xtensa Options:: Command-line Options. 21986* Xtensa Syntax:: Assembler Syntax for Xtensa Processors. 21987* Xtensa Optimizations:: Assembler Optimizations. 21988* Xtensa Relaxation:: Other Automatic Transformations. 21989* Xtensa Directives:: Directives for Xtensa Processors. 21990 21991 21992File: as.info, Node: Xtensa Options, Next: Xtensa Syntax, Up: Xtensa-Dependent 21993 219949.53.1 Command Line Options 21995--------------------------- 21996 21997'--text-section-literals | --no-text-section-literals' 21998 Control the treatment of literal pools. The default is 21999 '--no-text-section-literals', which places literals in separate 22000 sections in the output file. This allows the literal pool to be 22001 placed in a data RAM/ROM. With '--text-section-literals', the 22002 literals are interspersed in the text section in order to keep them 22003 as close as possible to their references. This may be necessary 22004 for large assembly files, where the literals would otherwise be out 22005 of range of the 'L32R' instructions in the text section. Literals 22006 are grouped into pools following '.literal_position' directives or 22007 preceding 'ENTRY' instructions. These options only affect literals 22008 referenced via PC-relative 'L32R' instructions; literals for 22009 absolute mode 'L32R' instructions are handled separately. *Note 22010 literal: Literal Directive. 22011 22012'--auto-litpools | --no-auto-litpools' 22013 Control the treatment of literal pools. The default is 22014 '--no-auto-litpools', which in the absence of 22015 '--text-section-literals' places literals in separate sections in 22016 the output file. This allows the literal pool to be placed in a 22017 data RAM/ROM. With '--auto-litpools', the literals are interspersed 22018 in the text section in order to keep them as close as possible to 22019 their references, explicit '.literal_position' directives are not 22020 required. This may be necessary for very large functions, where 22021 single literal pool at the beginning of the function may not be 22022 reachable by 'L32R' instructions at the end. These options only 22023 affect literals referenced via PC-relative 'L32R' instructions; 22024 literals for absolute mode 'L32R' instructions are handled 22025 separately. When used together with '--text-section-literals', 22026 '--auto-litpools' takes precedence. *Note literal: Literal 22027 Directive. 22028 22029'--absolute-literals | --no-absolute-literals' 22030 Indicate to the assembler whether 'L32R' instructions use absolute 22031 or PC-relative addressing. If the processor includes the absolute 22032 addressing option, the default is to use absolute 'L32R' 22033 relocations. Otherwise, only the PC-relative 'L32R' relocations 22034 can be used. 22035 22036'--target-align | --no-target-align' 22037 Enable or disable automatic alignment to reduce branch penalties at 22038 some expense in code size. *Note Automatic Instruction Alignment: 22039 Xtensa Automatic Alignment. This optimization is enabled by 22040 default. Note that the assembler will always align instructions 22041 like 'LOOP' that have fixed alignment requirements. 22042 22043'--longcalls | --no-longcalls' 22044 Enable or disable transformation of call instructions to allow 22045 calls across a greater range of addresses. *Note Function Call 22046 Relaxation: Xtensa Call Relaxation. This option should be used 22047 when call targets can potentially be out of range. It may degrade 22048 both code size and performance, but the linker can generally 22049 optimize away the unnecessary overhead when a call ends up within 22050 range. The default is '--no-longcalls'. 22051 22052'--transform | --no-transform' 22053 Enable or disable all assembler transformations of Xtensa 22054 instructions, including both relaxation and optimization. The 22055 default is '--transform'; '--no-transform' should only be used in 22056 the rare cases when the instructions must be exactly as specified 22057 in the assembly source. Using '--no-transform' causes out of range 22058 instruction operands to be errors. 22059 22060'--rename-section OLDNAME=NEWNAME' 22061 Rename the OLDNAME section to NEWNAME. This option can be used 22062 multiple times to rename multiple sections. 22063 22064'--trampolines | --no-trampolines' 22065 Enable or disable transformation of jump instructions to allow 22066 jumps across a greater range of addresses. *Note Jump Trampolines: 22067 Xtensa Jump Relaxation. This option should be used when jump 22068 targets can potentially be out of range. In the absence of such 22069 jumps this option does not affect code size or performance. The 22070 default is '--trampolines'. 22071 22072 22073File: as.info, Node: Xtensa Syntax, Next: Xtensa Optimizations, Prev: Xtensa Options, Up: Xtensa-Dependent 22074 220759.53.2 Assembler Syntax 22076----------------------- 22077 22078Block comments are delimited by '/*' and '*/'. End of line comments may 22079be introduced with either '#' or '//'. 22080 22081 If a '#' appears as the first character of a line then the whole line 22082is treated as a comment, but in this case the line could also be a 22083logical line number directive (*note Comments::) or a preprocessor 22084control command (*note Preprocessing::). 22085 22086 Instructions consist of a leading opcode or macro name followed by 22087whitespace and an optional comma-separated list of operands: 22088 22089 OPCODE [OPERAND, ...] 22090 22091 Instructions must be separated by a newline or semicolon (';'). 22092 22093 FLIX instructions, which bundle multiple opcodes together in a single 22094instruction, are specified by enclosing the bundled opcodes inside 22095braces: 22096 22097 { 22098 [FORMAT] 22099 OPCODE0 [OPERANDS] 22100 OPCODE1 [OPERANDS] 22101 OPCODE2 [OPERANDS] 22102 ... 22103 } 22104 22105 The opcodes in a FLIX instruction are listed in the same order as the 22106corresponding instruction slots in the TIE format declaration. 22107Directives and labels are not allowed inside the braces of a FLIX 22108instruction. A particular TIE format name can optionally be specified 22109immediately after the opening brace, but this is usually unnecessary. 22110The assembler will automatically search for a format that can encode the 22111specified opcodes, so the format name need only be specified in rare 22112cases where there is more than one applicable format and where it 22113matters which of those formats is used. A FLIX instruction can also be 22114specified on a single line by separating the opcodes with semicolons: 22115 22116 { [FORMAT;] OPCODE0 [OPERANDS]; OPCODE1 [OPERANDS]; OPCODE2 [OPERANDS]; ... } 22117 22118 If an opcode can only be encoded in a FLIX instruction but is not 22119specified as part of a FLIX bundle, the assembler will choose the 22120smallest format where the opcode can be encoded and will fill unused 22121instruction slots with no-ops. 22122 22123* Menu: 22124 22125* Xtensa Opcodes:: Opcode Naming Conventions. 22126* Xtensa Registers:: Register Naming. 22127 22128 22129File: as.info, Node: Xtensa Opcodes, Next: Xtensa Registers, Up: Xtensa Syntax 22130 221319.53.2.1 Opcode Names 22132..................... 22133 22134See the 'Xtensa Instruction Set Architecture (ISA) Reference Manual' for 22135a complete list of opcodes and descriptions of their semantics. 22136 22137 If an opcode name is prefixed with an underscore character ('_'), 22138'as' will not transform that instruction in any way. The underscore 22139prefix disables both optimization (*note Xtensa Optimizations: Xtensa 22140Optimizations.) and relaxation (*note Xtensa Relaxation: Xtensa 22141Relaxation.) for that particular instruction. Only use the underscore 22142prefix when it is essential to select the exact opcode produced by the 22143assembler. Using this feature unnecessarily makes the code less 22144efficient by disabling assembler optimization and less flexible by 22145disabling relaxation. 22146 22147 Note that this special handling of underscore prefixes only applies 22148to Xtensa opcodes, not to either built-in macros or user-defined macros. 22149When an underscore prefix is used with a macro (e.g., '_MOV'), it refers 22150to a different macro. The assembler generally provides built-in macros 22151both with and without the underscore prefix, where the underscore 22152versions behave as if the underscore carries through to the instructions 22153in the macros. For example, '_MOV' may expand to '_MOV.N'. 22154 22155 The underscore prefix only applies to individual instructions, not to 22156series of instructions. For example, if a series of instructions have 22157underscore prefixes, the assembler will not transform the individual 22158instructions, but it may insert other instructions between them (e.g., 22159to align a 'LOOP' instruction). To prevent the assembler from modifying 22160a series of instructions as a whole, use the 'no-transform' directive. 22161*Note transform: Transform Directive. 22162 22163 22164File: as.info, Node: Xtensa Registers, Prev: Xtensa Opcodes, Up: Xtensa Syntax 22165 221669.53.2.2 Register Names 22167....................... 22168 22169The assembly syntax for a register file entry is the "short" name for a 22170TIE register file followed by the index into that register file. For 22171example, the general-purpose 'AR' register file has a short name of 'a', 22172so these registers are named 'a0'...'a15'. As a special feature, 'sp' 22173is also supported as a synonym for 'a1'. Additional registers may be 22174added by processor configuration options and by designer-defined TIE 22175extensions. An initial '$' character is optional in all register names. 22176 22177 22178File: as.info, Node: Xtensa Optimizations, Next: Xtensa Relaxation, Prev: Xtensa Syntax, Up: Xtensa-Dependent 22179 221809.53.3 Xtensa Optimizations 22181--------------------------- 22182 22183The optimizations currently supported by 'as' are generation of density 22184instructions where appropriate and automatic branch target alignment. 22185 22186* Menu: 22187 22188* Density Instructions:: Using Density Instructions. 22189* Xtensa Automatic Alignment:: Automatic Instruction Alignment. 22190 22191 22192File: as.info, Node: Density Instructions, Next: Xtensa Automatic Alignment, Up: Xtensa Optimizations 22193 221949.53.3.1 Using Density Instructions 22195................................... 22196 22197The Xtensa instruction set has a code density option that provides 2219816-bit versions of some of the most commonly used opcodes. Use of these 22199opcodes can significantly reduce code size. When possible, the 22200assembler automatically translates instructions from the core Xtensa 22201instruction set into equivalent instructions from the Xtensa code 22202density option. This translation can be disabled by using underscore 22203prefixes (*note Opcode Names: Xtensa Opcodes.), by using the 22204'--no-transform' command-line option (*note Command Line Options: Xtensa 22205Options.), or by using the 'no-transform' directive (*note transform: 22206Transform Directive.). 22207 22208 It is a good idea _not_ to use the density instructions directly. 22209The assembler will automatically select dense instructions where 22210possible. If you later need to use an Xtensa processor without the code 22211density option, the same assembly code will then work without 22212modification. 22213 22214 22215File: as.info, Node: Xtensa Automatic Alignment, Prev: Density Instructions, Up: Xtensa Optimizations 22216 222179.53.3.2 Automatic Instruction Alignment 22218........................................ 22219 22220The Xtensa assembler will automatically align certain instructions, both 22221to optimize performance and to satisfy architectural requirements. 22222 22223 As an optimization to improve performance, the assembler attempts to 22224align branch targets so they do not cross instruction fetch boundaries. 22225(Xtensa processors can be configured with either 32-bit or 64-bit 22226instruction fetch widths.) An instruction immediately following a call 22227is treated as a branch target in this context, because it will be the 22228target of a return from the call. This alignment has the potential to 22229reduce branch penalties at some expense in code size. This optimization 22230is enabled by default. You can disable it with the '--no-target-align' 22231command-line option (*note Command Line Options: Xtensa Options.). 22232 22233 The target alignment optimization is done without adding instructions 22234that could increase the execution time of the program. If there are 22235density instructions in the code preceding a target, the assembler can 22236change the target alignment by widening some of those instructions to 22237the equivalent 24-bit instructions. Extra bytes of padding can be 22238inserted immediately following unconditional jump and return 22239instructions. This approach is usually successful in aligning many, but 22240not all, branch targets. 22241 22242 The 'LOOP' family of instructions must be aligned such that the first 22243instruction in the loop body does not cross an instruction fetch 22244boundary (e.g., with a 32-bit fetch width, a 'LOOP' instruction must be 22245on either a 1 or 2 mod 4 byte boundary). The assembler knows about this 22246restriction and inserts the minimal number of 2 or 3 byte no-op 22247instructions to satisfy it. When no-op instructions are added, any 22248label immediately preceding the original loop will be moved in order to 22249refer to the loop instruction, not the newly generated no-op 22250instruction. To preserve binary compatibility across processors with 22251different fetch widths, the assembler conservatively assumes a 32-bit 22252fetch width when aligning 'LOOP' instructions (except if the first 22253instruction in the loop is a 64-bit instruction). 22254 22255 Previous versions of the assembler automatically aligned 'ENTRY' 22256instructions to 4-byte boundaries, but that alignment is now the 22257programmer's responsibility. 22258 22259 22260File: as.info, Node: Xtensa Relaxation, Next: Xtensa Directives, Prev: Xtensa Optimizations, Up: Xtensa-Dependent 22261 222629.53.4 Xtensa Relaxation 22263------------------------ 22264 22265When an instruction operand is outside the range allowed for that 22266particular instruction field, 'as' can transform the code to use a 22267functionally-equivalent instruction or sequence of instructions. This 22268process is known as "relaxation". This is typically done for branch 22269instructions because the distance of the branch targets is not known 22270until assembly-time. The Xtensa assembler offers branch relaxation and 22271also extends this concept to function calls, 'MOVI' instructions and 22272other instructions with immediate fields. 22273 22274* Menu: 22275 22276* Xtensa Branch Relaxation:: Relaxation of Branches. 22277* Xtensa Call Relaxation:: Relaxation of Function Calls. 22278* Xtensa Jump Relaxation:: Relaxation of Jumps. 22279* Xtensa Immediate Relaxation:: Relaxation of other Immediate Fields. 22280 22281 22282File: as.info, Node: Xtensa Branch Relaxation, Next: Xtensa Call Relaxation, Up: Xtensa Relaxation 22283 222849.53.4.1 Conditional Branch Relaxation 22285...................................... 22286 22287When the target of a branch is too far away from the branch itself, 22288i.e., when the offset from the branch to the target is too large to fit 22289in the immediate field of the branch instruction, it may be necessary to 22290replace the branch with a branch around a jump. For example, 22291 22292 beqz a2, L 22293 22294 may result in: 22295 22296 bnez.n a2, M 22297 j L 22298 M: 22299 22300 (The 'BNEZ.N' instruction would be used in this example only if the 22301density option is available. Otherwise, 'BNEZ' would be used.) 22302 22303 This relaxation works well because the unconditional jump instruction 22304has a much larger offset range than the various conditional branches. 22305However, an error will occur if a branch target is beyond the range of a 22306jump instruction. 'as' cannot relax unconditional jumps. Similarly, an 22307error will occur if the original input contains an unconditional jump to 22308a target that is out of range. 22309 22310 Branch relaxation is enabled by default. It can be disabled by using 22311underscore prefixes (*note Opcode Names: Xtensa Opcodes.), the 22312'--no-transform' command-line option (*note Command Line Options: Xtensa 22313Options.), or the 'no-transform' directive (*note transform: Transform 22314Directive.). 22315 22316 22317File: as.info, Node: Xtensa Call Relaxation, Next: Xtensa Jump Relaxation, Prev: Xtensa Branch Relaxation, Up: Xtensa Relaxation 22318 223199.53.4.2 Function Call Relaxation 22320................................. 22321 22322Function calls may require relaxation because the Xtensa immediate call 22323instructions ('CALL0', 'CALL4', 'CALL8' and 'CALL12') provide a 22324PC-relative offset of only 512 Kbytes in either direction. For larger 22325programs, it may be necessary to use indirect calls ('CALLX0', 'CALLX4', 22326'CALLX8' and 'CALLX12') where the target address is specified in a 22327register. The Xtensa assembler can automatically relax immediate call 22328instructions into indirect call instructions. This relaxation is done 22329by loading the address of the called function into the callee's return 22330address register and then using a 'CALLX' instruction. So, for example: 22331 22332 call8 func 22333 22334 might be relaxed to: 22335 22336 .literal .L1, func 22337 l32r a8, .L1 22338 callx8 a8 22339 22340 Because the addresses of targets of function calls are not generally 22341known until link-time, the assembler must assume the worst and relax all 22342the calls to functions in other source files, not just those that really 22343will be out of range. The linker can recognize calls that were 22344unnecessarily relaxed, and it will remove the overhead introduced by the 22345assembler for those cases where direct calls are sufficient. 22346 22347 Call relaxation is disabled by default because it can have a negative 22348effect on both code size and performance, although the linker can 22349usually eliminate the unnecessary overhead. If a program is too large 22350and some of the calls are out of range, function call relaxation can be 22351enabled using the '--longcalls' command-line option or the 'longcalls' 22352directive (*note longcalls: Longcalls Directive.). 22353 22354 22355File: as.info, Node: Xtensa Jump Relaxation, Next: Xtensa Immediate Relaxation, Prev: Xtensa Call Relaxation, Up: Xtensa Relaxation 22356 223579.53.4.3 Jump Relaxation 22358........................ 22359 22360Jump instruction may require relaxation because the Xtensa jump 22361instruction ('J') provide a PC-relative offset of only 128 Kbytes in 22362either direction. One option is to use jump long ('J.L') instruction, 22363which depending on jump distance may be assembled as jump ('J') or 22364indirect jump ('JX'). However it needs a free register. When there's 22365no spare register it is possible to plant intermediate jump sites 22366(trampolines) between the jump instruction and its target. These sites 22367may be located in areas unreachable by normal code execution flow, in 22368that case they only contain intermediate jumps, or they may be inserted 22369in the middle of code block, in which case there's an additional jump 22370from the beginning of the trampoline to the instruction past its end. 22371So, for example: 22372 22373 j 1f 22374 ... 22375 retw 22376 ... 22377 mov a10, a2 22378 call8 func 22379 ... 22380 1: 22381 ... 22382 22383 might be relaxed to: 22384 22385 j .L0_TR_1 22386 ... 22387 retw 22388 .L0_TR_1: 22389 j 1f 22390 ... 22391 mov a10, a2 22392 call8 func 22393 ... 22394 1: 22395 ... 22396 22397 or to: 22398 22399 j .L0_TR_1 22400 ... 22401 retw 22402 ... 22403 mov a10, a2 22404 j .L0_TR_0 22405 .L0_TR_1: 22406 j 1f 22407 .L0_TR_0: 22408 call8 func 22409 ... 22410 1: 22411 ... 22412 22413 The Xtensa assempler uses trampolines with jump around only when it 22414cannot find suitable unreachable trampoline. There may be multiple 22415trampolines between the jump instruction and its target. 22416 22417 This relaxation does not apply to jumps to undefined symbols, 22418assuming they will reach their targets once resolved. 22419 22420 Jump relaxation is enabled by default because it does not affect code 22421size or performance while the code itself is small. This relaxation may 22422be disabled completely with '--no-trampolines' or '--no-transform' 22423command-line options (*note Command Line Options: Xtensa Options.). 22424 22425 22426File: as.info, Node: Xtensa Immediate Relaxation, Prev: Xtensa Jump Relaxation, Up: Xtensa Relaxation 22427 224289.53.4.4 Other Immediate Field Relaxation 22429......................................... 22430 22431The assembler normally performs the following other relaxations. They 22432can be disabled by using underscore prefixes (*note Opcode Names: Xtensa 22433Opcodes.), the '--no-transform' command-line option (*note Command Line 22434Options: Xtensa Options.), or the 'no-transform' directive (*note 22435transform: Transform Directive.). 22436 22437 The 'MOVI' machine instruction can only materialize values in the 22438range from -2048 to 2047. Values outside this range are best 22439materialized with 'L32R' instructions. Thus: 22440 22441 movi a0, 100000 22442 22443 is assembled into the following machine code: 22444 22445 .literal .L1, 100000 22446 l32r a0, .L1 22447 22448 The 'L8UI' machine instruction can only be used with immediate 22449offsets in the range from 0 to 255. The 'L16SI' and 'L16UI' machine 22450instructions can only be used with offsets from 0 to 510. The 'L32I' 22451machine instruction can only be used with offsets from 0 to 1020. A 22452load offset outside these ranges can be materialized with an 'L32R' 22453instruction if the destination register of the load is different than 22454the source address register. For example: 22455 22456 l32i a1, a0, 2040 22457 22458 is translated to: 22459 22460 .literal .L1, 2040 22461 l32r a1, .L1 22462 add a1, a0, a1 22463 l32i a1, a1, 0 22464 22465If the load destination and source address register are the same, an 22466out-of-range offset causes an error. 22467 22468 The Xtensa 'ADDI' instruction only allows immediate operands in the 22469range from -128 to 127. There are a number of alternate instruction 22470sequences for the 'ADDI' operation. First, if the immediate is 0, the 22471'ADDI' will be turned into a 'MOV.N' instruction (or the equivalent 'OR' 22472instruction if the code density option is not available). If the 'ADDI' 22473immediate is outside of the range -128 to 127, but inside the range 22474-32896 to 32639, an 'ADDMI' instruction or 'ADDMI'/'ADDI' sequence will 22475be used. Finally, if the immediate is outside of this range and a free 22476register is available, an 'L32R'/'ADD' sequence will be used with a 22477literal allocated from the literal pool. 22478 22479 For example: 22480 22481 addi a5, a6, 0 22482 addi a5, a6, 512 22483 addi a5, a6, 513 22484 addi a5, a6, 50000 22485 22486 is assembled into the following: 22487 22488 .literal .L1, 50000 22489 mov.n a5, a6 22490 addmi a5, a6, 0x200 22491 addmi a5, a6, 0x200 22492 addi a5, a5, 1 22493 l32r a5, .L1 22494 add a5, a6, a5 22495 22496 22497File: as.info, Node: Xtensa Directives, Prev: Xtensa Relaxation, Up: Xtensa-Dependent 22498 224999.53.5 Directives 22500----------------- 22501 22502The Xtensa assembler supports a region-based directive syntax: 22503 22504 .begin DIRECTIVE [OPTIONS] 22505 ... 22506 .end DIRECTIVE 22507 22508 All the Xtensa-specific directives that apply to a region of code use 22509this syntax. 22510 22511 The directive applies to code between the '.begin' and the '.end'. 22512The state of the option after the '.end' reverts to what it was before 22513the '.begin'. A nested '.begin'/'.end' region can further change the 22514state of the directive without having to be aware of its outer state. 22515For example, consider: 22516 22517 .begin no-transform 22518 L: add a0, a1, a2 22519 .begin transform 22520 M: add a0, a1, a2 22521 .end transform 22522 N: add a0, a1, a2 22523 .end no-transform 22524 22525 The 'ADD' opcodes at 'L' and 'N' in the outer 'no-transform' region 22526both result in 'ADD' machine instructions, but the assembler selects an 22527'ADD.N' instruction for the 'ADD' at 'M' in the inner 'transform' 22528region. 22529 22530 The advantage of this style is that it works well inside macros which 22531can preserve the context of their callers. 22532 22533 The following directives are available: 22534* Menu: 22535 22536* Schedule Directive:: Enable instruction scheduling. 22537* Longcalls Directive:: Use Indirect Calls for Greater Range. 22538* Transform Directive:: Disable All Assembler Transformations. 22539* Literal Directive:: Intermix Literals with Instructions. 22540* Literal Position Directive:: Specify Inline Literal Pool Locations. 22541* Literal Prefix Directive:: Specify Literal Section Name Prefix. 22542* Absolute Literals Directive:: Control PC-Relative vs. Absolute Literals. 22543 22544 22545File: as.info, Node: Schedule Directive, Next: Longcalls Directive, Up: Xtensa Directives 22546 225479.53.5.1 schedule 22548................. 22549 22550The 'schedule' directive is recognized only for compatibility with 22551Tensilica's assembler. 22552 22553 .begin [no-]schedule 22554 .end [no-]schedule 22555 22556 This directive is ignored and has no effect on 'as'. 22557 22558 22559File: as.info, Node: Longcalls Directive, Next: Transform Directive, Prev: Schedule Directive, Up: Xtensa Directives 22560 225619.53.5.2 longcalls 22562.................. 22563 22564The 'longcalls' directive enables or disables function call relaxation. 22565*Note Function Call Relaxation: Xtensa Call Relaxation. 22566 22567 .begin [no-]longcalls 22568 .end [no-]longcalls 22569 22570 Call relaxation is disabled by default unless the '--longcalls' 22571command-line option is specified. The 'longcalls' directive overrides 22572the default determined by the command-line options. 22573 22574 22575File: as.info, Node: Transform Directive, Next: Literal Directive, Prev: Longcalls Directive, Up: Xtensa Directives 22576 225779.53.5.3 transform 22578.................. 22579 22580This directive enables or disables all assembler transformation, 22581including relaxation (*note Xtensa Relaxation: Xtensa Relaxation.) and 22582optimization (*note Xtensa Optimizations: Xtensa Optimizations.). 22583 22584 .begin [no-]transform 22585 .end [no-]transform 22586 22587 Transformations are enabled by default unless the '--no-transform' 22588option is used. The 'transform' directive overrides the default 22589determined by the command-line options. An underscore opcode prefix, 22590disabling transformation of that opcode, always takes precedence over 22591both directives and command-line flags. 22592 22593 22594File: as.info, Node: Literal Directive, Next: Literal Position Directive, Prev: Transform Directive, Up: Xtensa Directives 22595 225969.53.5.4 literal 22597................ 22598 22599The '.literal' directive is used to define literal pool data, i.e., 22600read-only 32-bit data accessed via 'L32R' instructions. 22601 22602 .literal LABEL, VALUE[, VALUE...] 22603 22604 This directive is similar to the standard '.word' directive, except 22605that the actual location of the literal data is determined by the 22606assembler and linker, not by the position of the '.literal' directive. 22607Using this directive gives the assembler freedom to locate the literal 22608data in the most appropriate place and possibly to combine identical 22609literals. For example, the code: 22610 22611 entry sp, 40 22612 .literal .L1, sym 22613 l32r a4, .L1 22614 22615 can be used to load a pointer to the symbol 'sym' into register 'a4'. 22616The value of 'sym' will not be placed between the 'ENTRY' and 'L32R' 22617instructions; instead, the assembler puts the data in a literal pool. 22618 22619 Literal pools are placed by default in separate literal sections; 22620however, when using the '--text-section-literals' option (*note Command 22621Line Options: Xtensa Options.), the literal pools for PC-relative mode 22622'L32R' instructions are placed in the current section.(1) These text 22623section literal pools are created automatically before 'ENTRY' 22624instructions and manually after '.literal_position' directives (*note 22625literal_position: Literal Position Directive.). If there are no 22626preceding 'ENTRY' instructions, explicit '.literal_position' directives 22627must be used to place the text section literal pools; otherwise, 'as' 22628will report an error. 22629 22630 When literals are placed in separate sections, the literal section 22631names are derived from the names of the sections where the literals are 22632defined. The base literal section names are '.literal' for PC-relative 22633mode 'L32R' instructions and '.lit4' for absolute mode 'L32R' 22634instructions (*note absolute-literals: Absolute Literals Directive.). 22635These base names are used for literals defined in the default '.text' 22636section. For literals defined in other sections or within the scope of 22637a 'literal_prefix' directive (*note literal_prefix: Literal Prefix 22638Directive.), the following rules determine the literal section name: 22639 22640 1. If the current section is a member of a section group, the literal 22641 section name includes the group name as a suffix to the base 22642 '.literal' or '.lit4' name, with a period to separate the base name 22643 and group name. The literal section is also made a member of the 22644 group. 22645 22646 2. If the current section name (or 'literal_prefix' value) begins with 22647 "'.gnu.linkonce.KIND.'", the literal section name is formed by 22648 replacing "'.KIND'" with the base '.literal' or '.lit4' name. For 22649 example, for literals defined in a section named 22650 '.gnu.linkonce.t.func', the literal section will be 22651 '.gnu.linkonce.literal.func' or '.gnu.linkonce.lit4.func'. 22652 22653 3. If the current section name (or 'literal_prefix' value) ends with 22654 '.text', the literal section name is formed by replacing that 22655 suffix with the base '.literal' or '.lit4' name. For example, for 22656 literals defined in a section named '.iram0.text', the literal 22657 section will be '.iram0.literal' or '.iram0.lit4'. 22658 22659 4. If none of the preceding conditions apply, the literal section name 22660 is formed by adding the base '.literal' or '.lit4' name as a suffix 22661 to the current section name (or 'literal_prefix' value). 22662 22663 ---------- Footnotes ---------- 22664 22665 (1) Literals for the '.init' and '.fini' sections are always placed 22666in separate sections, even when '--text-section-literals' is enabled. 22667 22668 22669File: as.info, Node: Literal Position Directive, Next: Literal Prefix Directive, Prev: Literal Directive, Up: Xtensa Directives 22670 226719.53.5.5 literal_position 22672......................... 22673 22674When using '--text-section-literals' to place literals inline in the 22675section being assembled, the '.literal_position' directive can be used 22676to mark a potential location for a literal pool. 22677 22678 .literal_position 22679 22680 The '.literal_position' directive is ignored when the 22681'--text-section-literals' option is not used or when 'L32R' instructions 22682use the absolute addressing mode. 22683 22684 The assembler will automatically place text section literal pools 22685before 'ENTRY' instructions, so the '.literal_position' directive is 22686only needed to specify some other location for a literal pool. You may 22687need to add an explicit jump instruction to skip over an inline literal 22688pool. 22689 22690 For example, an interrupt vector does not begin with an 'ENTRY' 22691instruction so the assembler will be unable to automatically find a good 22692place to put a literal pool. Moreover, the code for the interrupt 22693vector must be at a specific starting address, so the literal pool 22694cannot come before the start of the code. The literal pool for the 22695vector must be explicitly positioned in the middle of the vector (before 22696any uses of the literals, due to the negative offsets used by 22697PC-relative 'L32R' instructions). The '.literal_position' directive can 22698be used to do this. In the following code, the literal for 'M' will 22699automatically be aligned correctly and is placed after the unconditional 22700jump. 22701 22702 .global M 22703 code_start: 22704 j continue 22705 .literal_position 22706 .align 4 22707 continue: 22708 movi a4, M 22709 22710 22711File: as.info, Node: Literal Prefix Directive, Next: Absolute Literals Directive, Prev: Literal Position Directive, Up: Xtensa Directives 22712 227139.53.5.6 literal_prefix 22714....................... 22715 22716The 'literal_prefix' directive allows you to override the default 22717literal section names, which are derived from the names of the sections 22718where the literals are defined. 22719 22720 .begin literal_prefix [NAME] 22721 .end literal_prefix 22722 22723 For literals defined within the delimited region, the literal section 22724names are derived from the NAME argument instead of the name of the 22725current section. The rules used to derive the literal section names do 22726not change. *Note literal: Literal Directive. If the NAME argument is 22727omitted, the literal sections revert to the defaults. This directive 22728has no effect when using the '--text-section-literals' option (*note 22729Command Line Options: Xtensa Options.). 22730 22731 22732File: as.info, Node: Absolute Literals Directive, Prev: Literal Prefix Directive, Up: Xtensa Directives 22733 227349.53.5.7 absolute-literals 22735.......................... 22736 22737The 'absolute-literals' and 'no-absolute-literals' directives control 22738the absolute vs. PC-relative mode for 'L32R' instructions. These are 22739relevant only for Xtensa configurations that include the absolute 22740addressing option for 'L32R' instructions. 22741 22742 .begin [no-]absolute-literals 22743 .end [no-]absolute-literals 22744 22745 These directives do not change the 'L32R' mode--they only cause the 22746assembler to emit the appropriate kind of relocation for 'L32R' 22747instructions and to place the literal values in the appropriate section. 22748To change the 'L32R' mode, the program must write the 'LITBASE' special 22749register. It is the programmer's responsibility to keep track of the 22750mode and indicate to the assembler which mode is used in each region of 22751code. 22752 22753 If the Xtensa configuration includes the absolute 'L32R' addressing 22754option, the default is to assume absolute 'L32R' addressing unless the 22755'--no-absolute-literals' command-line option is specified. Otherwise, 22756the default is to assume PC-relative 'L32R' addressing. The 22757'absolute-literals' directive can then be used to override the default 22758determined by the command-line options. 22759 22760 22761File: as.info, Node: Z80-Dependent, Next: Z8000-Dependent, Prev: Xtensa-Dependent, Up: Machine Dependencies 22762 227639.54 Z80 Dependent Features 22764=========================== 22765 22766* Menu: 22767 22768* Z80 Options:: Options 22769* Z80 Syntax:: Syntax 22770* Z80 Floating Point:: Floating Point 22771* Z80 Directives:: Z80 Machine Directives 22772* Z80 Opcodes:: Opcodes 22773 22774 22775File: as.info, Node: Z80 Options, Next: Z80 Syntax, Up: Z80-Dependent 22776 227779.54.1 Options 22778-------------- 22779 22780The Zilog Z80 and Ascii R800 version of 'as' have a few machine 22781dependent options. 22782'-z80' 22783 Produce code for the Z80 processor. There are additional options 22784 to request warnings and error messages for undocumented 22785 instructions. 22786'-ignore-undocumented-instructions' 22787'-Wnud' 22788 Silently assemble undocumented Z80-instructions that have been 22789 adopted as documented R800-instructions. 22790'-ignore-unportable-instructions' 22791'-Wnup' 22792 Silently assemble all undocumented Z80-instructions. 22793'-warn-undocumented-instructions' 22794'-Wud' 22795 Issue warnings for undocumented Z80-instructions that work on R800, 22796 do not assemble other undocumented instructions without warning. 22797'-warn-unportable-instructions' 22798'-Wup' 22799 Issue warnings for other undocumented Z80-instructions, do not 22800 treat any undocumented instructions as errors. 22801'-forbid-undocumented-instructions' 22802'-Fud' 22803 Treat all undocumented z80-instructions as errors. 22804'-forbid-unportable-instructions' 22805'-Fup' 22806 Treat undocumented z80-instructions that do not work on R800 as 22807 errors. 22808 22809'-r800' 22810 Produce code for the R800 processor. The assembler does not 22811 support undocumented instructions for the R800. In line with 22812 common practice, 'as' uses Z80 instruction names for the R800 22813 processor, as far as they exist. 22814 22815 22816File: as.info, Node: Z80 Syntax, Next: Z80 Floating Point, Prev: Z80 Options, Up: Z80-Dependent 22817 228189.54.2 Syntax 22819------------- 22820 22821The assembler syntax closely follows the 'Z80 family CPU User Manual' by 22822Zilog. In expressions a single '=' may be used as "is equal to" 22823comparison operator. 22824 22825 Suffices can be used to indicate the radix of integer constants; 'H' 22826or 'h' for hexadecimal, 'D' or 'd' for decimal, 'Q', 'O', 'q' or 'o' for 22827octal, and 'B' for binary. 22828 22829 The suffix 'b' denotes a backreference to local label. 22830 22831* Menu: 22832 22833* Z80-Chars:: Special Characters 22834* Z80-Regs:: Register Names 22835* Z80-Case:: Case Sensitivity 22836 22837 22838File: as.info, Node: Z80-Chars, Next: Z80-Regs, Up: Z80 Syntax 22839 228409.54.2.1 Special Characters 22841........................... 22842 22843The semicolon ';' is the line comment character; 22844 22845 If a '#' appears as the first character of a line then the whole line 22846is treated as a comment, but in this case the line could also be a 22847logical line number directive (*note Comments::) or a preprocessor 22848control command (*note Preprocessing::). 22849 22850 The Z80 assembler does not support a line separator character. 22851 22852 The dollar sign '$' can be used as a prefix for hexadecimal numbers 22853and as a symbol denoting the current location counter. 22854 22855 A backslash '\' is an ordinary character for the Z80 assembler. 22856 22857 The single quote ''' must be followed by a closing quote. If there 22858is one character in between, it is a character constant, otherwise it is 22859a string constant. 22860 22861 22862File: as.info, Node: Z80-Regs, Next: Z80-Case, Prev: Z80-Chars, Up: Z80 Syntax 22863 228649.54.2.2 Register Names 22865....................... 22866 22867The registers are referred to with the letters assigned to them by 22868Zilog. In addition 'as' recognizes 'ixl' and 'ixh' as the least and 22869most significant octet in 'ix', and similarly 'iyl' and 'iyh' as parts 22870of 'iy'. 22871 22872 22873File: as.info, Node: Z80-Case, Prev: Z80-Regs, Up: Z80 Syntax 22874 228759.54.2.3 Case Sensitivity 22876......................... 22877 22878Upper and lower case are equivalent in register names, opcodes, 22879condition codes and assembler directives. The case of letters is 22880significant in labels and symbol names. The case is also important to 22881distinguish the suffix 'b' for a backward reference to a local label 22882from the suffix 'B' for a number in binary notation. 22883 22884 22885File: as.info, Node: Z80 Floating Point, Next: Z80 Directives, Prev: Z80 Syntax, Up: Z80-Dependent 22886 228879.54.3 Floating Point 22888--------------------- 22889 22890Floating-point numbers are not supported. 22891 22892 22893File: as.info, Node: Z80 Directives, Next: Z80 Opcodes, Prev: Z80 Floating Point, Up: Z80-Dependent 22894 228959.54.4 Z80 Assembler Directives 22896------------------------------- 22897 22898'as' for the Z80 supports some additional directives for compatibility 22899with other assemblers. 22900 22901 These are the additional directives in 'as' for the Z80: 22902 22903'db EXPRESSION|STRING[,EXPRESSION|STRING...]' 22904'defb EXPRESSION|STRING[,EXPRESSION|STRING...]' 22905 For each STRING the characters are copied to the object file, for 22906 each other EXPRESSION the value is stored in one byte. A warning 22907 is issued in case of an overflow. 22908 22909'dw EXPRESSION[,EXPRESSION...]' 22910'defw EXPRESSION[,EXPRESSION...]' 22911 For each EXPRESSION the value is stored in two bytes, ignoring 22912 overflow. 22913 22914'd24 EXPRESSION[,EXPRESSION...]' 22915'def24 EXPRESSION[,EXPRESSION...]' 22916 For each EXPRESSION the value is stored in three bytes, ignoring 22917 overflow. 22918 22919'd32 EXPRESSION[,EXPRESSION...]' 22920'def32 EXPRESSION[,EXPRESSION...]' 22921 For each EXPRESSION the value is stored in four bytes, ignoring 22922 overflow. 22923 22924'ds COUNT[, VALUE]' 22925'defs COUNT[, VALUE]' 22926 Fill COUNT bytes in the object file with VALUE, if VALUE is omitted 22927 it defaults to zero. 22928 22929'SYMBOL equ EXPRESSION' 22930'SYMBOL defl EXPRESSION' 22931 These directives set the value of SYMBOL to EXPRESSION. If 'equ' 22932 is used, it is an error if SYMBOL is already defined. Symbols 22933 defined with 'equ' are not protected from redefinition. 22934 22935'set' 22936 This is a normal instruction on Z80, and not an assembler 22937 directive. 22938 22939'psect NAME' 22940 A synonym for *Note Section::, no second argument should be given. 22941 22942 22943File: as.info, Node: Z80 Opcodes, Prev: Z80 Directives, Up: Z80-Dependent 22944 229459.54.5 Opcodes 22946-------------- 22947 22948In line with common practice, Z80 mnemonics are used for both the Z80 22949and the R800. 22950 22951 In many instructions it is possible to use one of the half index 22952registers ('ixl','ixh','iyl','iyh') in stead of an 8-bit general purpose 22953register. This yields instructions that are documented on the R800 and 22954undocumented on the Z80. Similarly 'in f,(c)' is documented on the R800 22955and undocumented on the Z80. 22956 22957 The assembler also supports the following undocumented 22958Z80-instructions, that have not been adopted in the R800 instruction 22959set: 22960'out (c),0' 22961 Sends zero to the port pointed to by register c. 22962 22963'sli M' 22964 Equivalent to 'M = (M<<1)+1', the operand M can be any operand that 22965 is valid for 'sla'. One can use 'sll' as a synonym for 'sli'. 22966 22967'OP (ix+D), R' 22968 This is equivalent to 22969 22970 ld R, (ix+D) 22971 OPC R 22972 ld (ix+D), R 22973 22974 The operation 'OPC' may be any of 'res B,', 'set B,', 'rl', 'rlc', 22975 'rr', 'rrc', 'sla', 'sli', 'sra' and 'srl', and the register 'R' 22976 may be any of 'a', 'b', 'c', 'd', 'e', 'h' and 'l'. 22977 22978'OPC (iy+D), R' 22979 As above, but with 'iy' instead of 'ix'. 22980 22981 The web site at <http://www.z80.info> is a good starting place to 22982find more information on programming the Z80. 22983 22984 22985File: as.info, Node: Z8000-Dependent, Prev: Z80-Dependent, Up: Machine Dependencies 22986 229879.55 Z8000 Dependent Features 22988============================= 22989 22990The Z8000 as supports both members of the Z8000 family: the unsegmented 22991Z8002, with 16 bit addresses, and the segmented Z8001 with 24 bit 22992addresses. 22993 22994 When the assembler is in unsegmented mode (specified with the 22995'unsegm' directive), an address takes up one word (16 bit) sized 22996register. When the assembler is in segmented mode (specified with the 22997'segm' directive), a 24-bit address takes up a long (32 bit) register. 22998*Note Assembler Directives for the Z8000: Z8000 Directives, for a list 22999of other Z8000 specific assembler directives. 23000 23001* Menu: 23002 23003* Z8000 Options:: Command-line options for the Z8000 23004* Z8000 Syntax:: Assembler syntax for the Z8000 23005* Z8000 Directives:: Special directives for the Z8000 23006* Z8000 Opcodes:: Opcodes 23007 23008 23009File: as.info, Node: Z8000 Options, Next: Z8000 Syntax, Up: Z8000-Dependent 23010 230119.55.1 Options 23012-------------- 23013 23014'-z8001' 23015 Generate segmented code by default. 23016 23017'-z8002' 23018 Generate unsegmented code by default. 23019 23020 23021File: as.info, Node: Z8000 Syntax, Next: Z8000 Directives, Prev: Z8000 Options, Up: Z8000-Dependent 23022 230239.55.2 Syntax 23024------------- 23025 23026* Menu: 23027 23028* Z8000-Chars:: Special Characters 23029* Z8000-Regs:: Register Names 23030* Z8000-Addressing:: Addressing Modes 23031 23032 23033File: as.info, Node: Z8000-Chars, Next: Z8000-Regs, Up: Z8000 Syntax 23034 230359.55.2.1 Special Characters 23036........................... 23037 23038'!' is the line comment character. 23039 23040 If a '#' appears as the first character of a line then the whole line 23041is treated as a comment, but in this case the line could also be a 23042logical line number directive (*note Comments::) or a preprocessor 23043control command (*note Preprocessing::). 23044 23045 You can use ';' instead of a newline to separate statements. 23046 23047 23048File: as.info, Node: Z8000-Regs, Next: Z8000-Addressing, Prev: Z8000-Chars, Up: Z8000 Syntax 23049 230509.55.2.2 Register Names 23051....................... 23052 23053The Z8000 has sixteen 16 bit registers, numbered 0 to 15. You can refer 23054to different sized groups of registers by register number, with the 23055prefix 'r' for 16 bit registers, 'rr' for 32 bit registers and 'rq' for 2305664 bit registers. You can also refer to the contents of the first eight 23057(of the sixteen 16 bit registers) by bytes. They are named 'rlN' and 23058'rhN'. 23059 23060_byte registers_ 23061 rl0 rh0 rl1 rh1 rl2 rh2 rl3 rh3 23062 rl4 rh4 rl5 rh5 rl6 rh6 rl7 rh7 23063 23064_word registers_ 23065 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 23066 23067_long word registers_ 23068 rr0 rr2 rr4 rr6 rr8 rr10 rr12 rr14 23069 23070_quad word registers_ 23071 rq0 rq4 rq8 rq12 23072 23073 23074File: as.info, Node: Z8000-Addressing, Prev: Z8000-Regs, Up: Z8000 Syntax 23075 230769.55.2.3 Addressing Modes 23077......................... 23078 23079as understands the following addressing modes for the Z8000: 23080 23081'rlN' 23082'rhN' 23083'rN' 23084'rrN' 23085'rqN' 23086 Register direct: 8bit, 16bit, 32bit, and 64bit registers. 23087 23088'@rN' 23089'@rrN' 23090 Indirect register: @rrN in segmented mode, @rN in unsegmented mode. 23091 23092'ADDR' 23093 Direct: the 16 bit or 24 bit address (depending on whether the 23094 assembler is in segmented or unsegmented mode) of the operand is in 23095 the instruction. 23096 23097'address(rN)' 23098 Indexed: the 16 or 24 bit address is added to the 16 bit register 23099 to produce the final address in memory of the operand. 23100 23101'rN(#IMM)' 23102'rrN(#IMM)' 23103 Base Address: the 16 or 24 bit register is added to the 16 bit sign 23104 extended immediate displacement to produce the final address in 23105 memory of the operand. 23106 23107'rN(rM)' 23108'rrN(rM)' 23109 Base Index: the 16 or 24 bit register rN or rrN is added to the 23110 sign extended 16 bit index register rM to produce the final address 23111 in memory of the operand. 23112 23113'#XX' 23114 Immediate data XX. 23115 23116 23117File: as.info, Node: Z8000 Directives, Next: Z8000 Opcodes, Prev: Z8000 Syntax, Up: Z8000-Dependent 23118 231199.55.3 Assembler Directives for the Z8000 23120----------------------------------------- 23121 23122The Z8000 port of as includes additional assembler directives, for 23123compatibility with other Z8000 assemblers. These do not begin with '.' 23124(unlike the ordinary as directives). 23125 23126'segm' 23127'.z8001' 23128 Generate code for the segmented Z8001. 23129 23130'unsegm' 23131'.z8002' 23132 Generate code for the unsegmented Z8002. 23133 23134'name' 23135 Synonym for '.file' 23136 23137'global' 23138 Synonym for '.global' 23139 23140'wval' 23141 Synonym for '.word' 23142 23143'lval' 23144 Synonym for '.long' 23145 23146'bval' 23147 Synonym for '.byte' 23148 23149'sval' 23150 Assemble a string. 'sval' expects one string literal, delimited by 23151 single quotes. It assembles each byte of the string into 23152 consecutive addresses. You can use the escape sequence '%XX' 23153 (where XX represents a two-digit hexadecimal number) to represent 23154 the character whose ASCII value is XX. Use this feature to 23155 describe single quote and other characters that may not appear in 23156 string literals as themselves. For example, the C statement 23157 'char *a = "he said \"it's 50% off\"";' is represented in Z8000 23158 assembly language (shown with the assembler output in hex at the 23159 left) as 23160 23161 68652073 sval 'he said %22it%27s 50%25 off%22%00' 23162 61696420 23163 22697427 23164 73203530 23165 25206F66 23166 662200 23167 23168'rsect' 23169 synonym for '.section' 23170 23171'block' 23172 synonym for '.space' 23173 23174'even' 23175 special case of '.align'; aligns output to even byte boundary. 23176 23177 23178File: as.info, Node: Z8000 Opcodes, Prev: Z8000 Directives, Up: Z8000-Dependent 23179 231809.55.4 Opcodes 23181-------------- 23182 23183For detailed information on the Z8000 machine instruction set, see 23184'Z8000 Technical Manual'. 23185 23186 The following table summarizes the opcodes and their arguments: 23187 23188 rs 16 bit source register 23189 rd 16 bit destination register 23190 rbs 8 bit source register 23191 rbd 8 bit destination register 23192 rrs 32 bit source register 23193 rrd 32 bit destination register 23194 rqs 64 bit source register 23195 rqd 64 bit destination register 23196 addr 16/24 bit address 23197 imm immediate data 23198 23199 adc rd,rs clrb addr cpsir @rd,@rs,rr,cc 23200 adcb rbd,rbs clrb addr(rd) cpsirb @rd,@rs,rr,cc 23201 add rd,@rs clrb rbd dab rbd 23202 add rd,addr com @rd dbjnz rbd,disp7 23203 add rd,addr(rs) com addr dec @rd,imm4m1 23204 add rd,imm16 com addr(rd) dec addr(rd),imm4m1 23205 add rd,rs com rd dec addr,imm4m1 23206 addb rbd,@rs comb @rd dec rd,imm4m1 23207 addb rbd,addr comb addr decb @rd,imm4m1 23208 addb rbd,addr(rs) comb addr(rd) decb addr(rd),imm4m1 23209 addb rbd,imm8 comb rbd decb addr,imm4m1 23210 addb rbd,rbs comflg flags decb rbd,imm4m1 23211 addl rrd,@rs cp @rd,imm16 di i2 23212 addl rrd,addr cp addr(rd),imm16 div rrd,@rs 23213 addl rrd,addr(rs) cp addr,imm16 div rrd,addr 23214 addl rrd,imm32 cp rd,@rs div rrd,addr(rs) 23215 addl rrd,rrs cp rd,addr div rrd,imm16 23216 and rd,@rs cp rd,addr(rs) div rrd,rs 23217 and rd,addr cp rd,imm16 divl rqd,@rs 23218 and rd,addr(rs) cp rd,rs divl rqd,addr 23219 and rd,imm16 cpb @rd,imm8 divl rqd,addr(rs) 23220 and rd,rs cpb addr(rd),imm8 divl rqd,imm32 23221 andb rbd,@rs cpb addr,imm8 divl rqd,rrs 23222 andb rbd,addr cpb rbd,@rs djnz rd,disp7 23223 andb rbd,addr(rs) cpb rbd,addr ei i2 23224 andb rbd,imm8 cpb rbd,addr(rs) ex rd,@rs 23225 andb rbd,rbs cpb rbd,imm8 ex rd,addr 23226 bit @rd,imm4 cpb rbd,rbs ex rd,addr(rs) 23227 bit addr(rd),imm4 cpd rd,@rs,rr,cc ex rd,rs 23228 bit addr,imm4 cpdb rbd,@rs,rr,cc exb rbd,@rs 23229 bit rd,imm4 cpdr rd,@rs,rr,cc exb rbd,addr 23230 bit rd,rs cpdrb rbd,@rs,rr,cc exb rbd,addr(rs) 23231 bitb @rd,imm4 cpi rd,@rs,rr,cc exb rbd,rbs 23232 bitb addr(rd),imm4 cpib rbd,@rs,rr,cc ext0e imm8 23233 bitb addr,imm4 cpir rd,@rs,rr,cc ext0f imm8 23234 bitb rbd,imm4 cpirb rbd,@rs,rr,cc ext8e imm8 23235 bitb rbd,rs cpl rrd,@rs ext8f imm8 23236 bpt cpl rrd,addr exts rrd 23237 call @rd cpl rrd,addr(rs) extsb rd 23238 call addr cpl rrd,imm32 extsl rqd 23239 call addr(rd) cpl rrd,rrs halt 23240 calr disp12 cpsd @rd,@rs,rr,cc in rd,@rs 23241 clr @rd cpsdb @rd,@rs,rr,cc in rd,imm16 23242 clr addr cpsdr @rd,@rs,rr,cc inb rbd,@rs 23243 clr addr(rd) cpsdrb @rd,@rs,rr,cc inb rbd,imm16 23244 clr rd cpsi @rd,@rs,rr,cc inc @rd,imm4m1 23245 clrb @rd cpsib @rd,@rs,rr,cc inc addr(rd),imm4m1 23246 inc addr,imm4m1 ldb rbd,rs(rx) mult rrd,addr(rs) 23247 inc rd,imm4m1 ldb rd(imm16),rbs mult rrd,imm16 23248 incb @rd,imm4m1 ldb rd(rx),rbs mult rrd,rs 23249 incb addr(rd),imm4m1 ldctl ctrl,rs multl rqd,@rs 23250 incb addr,imm4m1 ldctl rd,ctrl multl rqd,addr 23251 incb rbd,imm4m1 ldd @rs,@rd,rr multl rqd,addr(rs) 23252 ind @rd,@rs,ra lddb @rs,@rd,rr multl rqd,imm32 23253 indb @rd,@rs,rba lddr @rs,@rd,rr multl rqd,rrs 23254 inib @rd,@rs,ra lddrb @rs,@rd,rr neg @rd 23255 inibr @rd,@rs,ra ldi @rd,@rs,rr neg addr 23256 iret ldib @rd,@rs,rr neg addr(rd) 23257 jp cc,@rd ldir @rd,@rs,rr neg rd 23258 jp cc,addr ldirb @rd,@rs,rr negb @rd 23259 jp cc,addr(rd) ldk rd,imm4 negb addr 23260 jr cc,disp8 ldl @rd,rrs negb addr(rd) 23261 ld @rd,imm16 ldl addr(rd),rrs negb rbd 23262 ld @rd,rs ldl addr,rrs nop 23263 ld addr(rd),imm16 ldl rd(imm16),rrs or rd,@rs 23264 ld addr(rd),rs ldl rd(rx),rrs or rd,addr 23265 ld addr,imm16 ldl rrd,@rs or rd,addr(rs) 23266 ld addr,rs ldl rrd,addr or rd,imm16 23267 ld rd(imm16),rs ldl rrd,addr(rs) or rd,rs 23268 ld rd(rx),rs ldl rrd,imm32 orb rbd,@rs 23269 ld rd,@rs ldl rrd,rrs orb rbd,addr 23270 ld rd,addr ldl rrd,rs(imm16) orb rbd,addr(rs) 23271 ld rd,addr(rs) ldl rrd,rs(rx) orb rbd,imm8 23272 ld rd,imm16 ldm @rd,rs,n orb rbd,rbs 23273 ld rd,rs ldm addr(rd),rs,n out @rd,rs 23274 ld rd,rs(imm16) ldm addr,rs,n out imm16,rs 23275 ld rd,rs(rx) ldm rd,@rs,n outb @rd,rbs 23276 lda rd,addr ldm rd,addr(rs),n outb imm16,rbs 23277 lda rd,addr(rs) ldm rd,addr,n outd @rd,@rs,ra 23278 lda rd,rs(imm16) ldps @rs outdb @rd,@rs,rba 23279 lda rd,rs(rx) ldps addr outib @rd,@rs,ra 23280 ldar rd,disp16 ldps addr(rs) outibr @rd,@rs,ra 23281 ldb @rd,imm8 ldr disp16,rs pop @rd,@rs 23282 ldb @rd,rbs ldr rd,disp16 pop addr(rd),@rs 23283 ldb addr(rd),imm8 ldrb disp16,rbs pop addr,@rs 23284 ldb addr(rd),rbs ldrb rbd,disp16 pop rd,@rs 23285 ldb addr,imm8 ldrl disp16,rrs popl @rd,@rs 23286 ldb addr,rbs ldrl rrd,disp16 popl addr(rd),@rs 23287 ldb rbd,@rs mbit popl addr,@rs 23288 ldb rbd,addr mreq rd popl rrd,@rs 23289 ldb rbd,addr(rs) mres push @rd,@rs 23290 ldb rbd,imm8 mset push @rd,addr 23291 ldb rbd,rbs mult rrd,@rs push @rd,addr(rs) 23292 ldb rbd,rs(imm16) mult rrd,addr push @rd,imm16 23293 push @rd,rs set addr,imm4 subl rrd,imm32 23294 pushl @rd,@rs set rd,imm4 subl rrd,rrs 23295 pushl @rd,addr set rd,rs tcc cc,rd 23296 pushl @rd,addr(rs) setb @rd,imm4 tccb cc,rbd 23297 pushl @rd,rrs setb addr(rd),imm4 test @rd 23298 res @rd,imm4 setb addr,imm4 test addr 23299 res addr(rd),imm4 setb rbd,imm4 test addr(rd) 23300 res addr,imm4 setb rbd,rs test rd 23301 res rd,imm4 setflg imm4 testb @rd 23302 res rd,rs sinb rbd,imm16 testb addr 23303 resb @rd,imm4 sinb rd,imm16 testb addr(rd) 23304 resb addr(rd),imm4 sind @rd,@rs,ra testb rbd 23305 resb addr,imm4 sindb @rd,@rs,rba testl @rd 23306 resb rbd,imm4 sinib @rd,@rs,ra testl addr 23307 resb rbd,rs sinibr @rd,@rs,ra testl addr(rd) 23308 resflg imm4 sla rd,imm8 testl rrd 23309 ret cc slab rbd,imm8 trdb @rd,@rs,rba 23310 rl rd,imm1or2 slal rrd,imm8 trdrb @rd,@rs,rba 23311 rlb rbd,imm1or2 sll rd,imm8 trib @rd,@rs,rbr 23312 rlc rd,imm1or2 sllb rbd,imm8 trirb @rd,@rs,rbr 23313 rlcb rbd,imm1or2 slll rrd,imm8 trtdrb @ra,@rb,rbr 23314 rldb rbb,rba sout imm16,rs trtib @ra,@rb,rr 23315 rr rd,imm1or2 soutb imm16,rbs trtirb @ra,@rb,rbr 23316 rrb rbd,imm1or2 soutd @rd,@rs,ra trtrb @ra,@rb,rbr 23317 rrc rd,imm1or2 soutdb @rd,@rs,rba tset @rd 23318 rrcb rbd,imm1or2 soutib @rd,@rs,ra tset addr 23319 rrdb rbb,rba soutibr @rd,@rs,ra tset addr(rd) 23320 rsvd36 sra rd,imm8 tset rd 23321 rsvd38 srab rbd,imm8 tsetb @rd 23322 rsvd78 sral rrd,imm8 tsetb addr 23323 rsvd7e srl rd,imm8 tsetb addr(rd) 23324 rsvd9d srlb rbd,imm8 tsetb rbd 23325 rsvd9f srll rrd,imm8 xor rd,@rs 23326 rsvdb9 sub rd,@rs xor rd,addr 23327 rsvdbf sub rd,addr xor rd,addr(rs) 23328 sbc rd,rs sub rd,addr(rs) xor rd,imm16 23329 sbcb rbd,rbs sub rd,imm16 xor rd,rs 23330 sc imm8 sub rd,rs xorb rbd,@rs 23331 sda rd,rs subb rbd,@rs xorb rbd,addr 23332 sdab rbd,rs subb rbd,addr xorb rbd,addr(rs) 23333 sdal rrd,rs subb rbd,addr(rs) xorb rbd,imm8 23334 sdl rd,rs subb rbd,imm8 xorb rbd,rbs 23335 sdlb rbd,rs subb rbd,rbs xorb rbd,rbs 23336 sdll rrd,rs subl rrd,@rs 23337 set @rd,imm4 subl rrd,addr 23338 set addr(rd),imm4 subl rrd,addr(rs) 23339 23340 23341File: as.info, Node: Reporting Bugs, Next: Acknowledgements, Prev: Machine Dependencies, Up: Top 23342 2334310 Reporting Bugs 23344***************** 23345 23346Your bug reports play an essential role in making 'as' reliable. 23347 23348 Reporting a bug may help you by bringing a solution to your problem, 23349or it may not. But in any case the principal function of a bug report 23350is to help the entire community by making the next version of 'as' work 23351better. Bug reports are your contribution to the maintenance of 'as'. 23352 23353 In order for a bug report to serve its purpose, you must include the 23354information that enables us to fix the bug. 23355 23356* Menu: 23357 23358* Bug Criteria:: Have you found a bug? 23359* Bug Reporting:: How to report bugs 23360 23361 23362File: as.info, Node: Bug Criteria, Next: Bug Reporting, Up: Reporting Bugs 23363 2336410.1 Have You Found a Bug? 23365========================== 23366 23367If you are not sure whether you have found a bug, here are some 23368guidelines: 23369 23370 * If the assembler gets a fatal signal, for any input whatever, that 23371 is a 'as' bug. Reliable assemblers never crash. 23372 23373 * If 'as' produces an error message for valid input, that is a bug. 23374 23375 * If 'as' does not produce an error message for invalid input, that 23376 is a bug. However, you should note that your idea of "invalid 23377 input" might be our idea of "an extension" or "support for 23378 traditional practice". 23379 23380 * If you are an experienced user of assemblers, your suggestions for 23381 improvement of 'as' are welcome in any case. 23382 23383 23384File: as.info, Node: Bug Reporting, Prev: Bug Criteria, Up: Reporting Bugs 23385 2338610.2 How to Report Bugs 23387======================= 23388 23389A number of companies and individuals offer support for GNU products. 23390If you obtained 'as' from a support organization, we recommend you 23391contact that organization first. 23392 23393 You can find contact information for many support companies and 23394individuals in the file 'etc/SERVICE' in the GNU Emacs distribution. 23395 23396 In any event, we also recommend that you send bug reports for 'as' to 23397<http://www.sourceware.org/bugzilla/>. 23398 23399 The fundamental principle of reporting bugs usefully is this: *report 23400all the facts*. If you are not sure whether to state a fact or leave it 23401out, state it! 23402 23403 Often people omit facts because they think they know what causes the 23404problem and assume that some details do not matter. Thus, you might 23405assume that the name of a symbol you use in an example does not matter. 23406Well, probably it does not, but one cannot be sure. Perhaps the bug is 23407a stray memory reference which happens to fetch from the location where 23408that name is stored in memory; perhaps, if the name were different, the 23409contents of that location would fool the assembler into doing the right 23410thing despite the bug. Play it safe and give a specific, complete 23411example. That is the easiest thing for you to do, and the most helpful. 23412 23413 Keep in mind that the purpose of a bug report is to enable us to fix 23414the bug if it is new to us. Therefore, always write your bug reports on 23415the assumption that the bug has not been reported previously. 23416 23417 Sometimes people give a few sketchy facts and ask, "Does this ring a 23418bell?" This cannot help us fix a bug, so it is basically useless. We 23419respond by asking for enough details to enable us to investigate. You 23420might as well expedite matters by sending them to begin with. 23421 23422 To enable us to fix the bug, you should include all these things: 23423 23424 * The version of 'as'. 'as' announces it if you start it with the 23425 '--version' argument. 23426 23427 Without this, we will not know whether there is any point in 23428 looking for the bug in the current version of 'as'. 23429 23430 * Any patches you may have applied to the 'as' source. 23431 23432 * The type of machine you are using, and the operating system name 23433 and version number. 23434 23435 * What compiler (and its version) was used to compile 'as'--e.g. 23436 "'gcc-2.7'". 23437 23438 * The command arguments you gave the assembler to assemble your 23439 example and observe the bug. To guarantee you will not omit 23440 something important, list them all. A copy of the Makefile (or the 23441 output from make) is sufficient. 23442 23443 If we were to try to guess the arguments, we would probably guess 23444 wrong and then we might not encounter the bug. 23445 23446 * A complete input file that will reproduce the bug. If the bug is 23447 observed when the assembler is invoked via a compiler, send the 23448 assembler source, not the high level language source. Most 23449 compilers will produce the assembler source when run with the '-S' 23450 option. If you are using 'gcc', use the options '-v --save-temps'; 23451 this will save the assembler source in a file with an extension of 23452 '.s', and also show you exactly how 'as' is being run. 23453 23454 * A description of what behavior you observe that you believe is 23455 incorrect. For example, "It gets a fatal signal." 23456 23457 Of course, if the bug is that 'as' gets a fatal signal, then we 23458 will certainly notice it. But if the bug is incorrect output, we 23459 might not notice unless it is glaringly wrong. You might as well 23460 not give us a chance to make a mistake. 23461 23462 Even if the problem you experience is a fatal signal, you should 23463 still say so explicitly. Suppose something strange is going on, 23464 such as, your copy of 'as' is out of sync, or you have encountered 23465 a bug in the C library on your system. (This has happened!) Your 23466 copy might crash and ours would not. If you told us to expect a 23467 crash, then when ours fails to crash, we would know that the bug 23468 was not happening for us. If you had not told us to expect a 23469 crash, then we would not be able to draw any conclusion from our 23470 observations. 23471 23472 * If you wish to suggest changes to the 'as' source, send us context 23473 diffs, as generated by 'diff' with the '-u', '-c', or '-p' option. 23474 Always send diffs from the old file to the new file. If you even 23475 discuss something in the 'as' source, refer to it by context, not 23476 by line number. 23477 23478 The line numbers in our development sources will not match those in 23479 your sources. Your line numbers would convey no useful information 23480 to us. 23481 23482 Here are some things that are not necessary: 23483 23484 * A description of the envelope of the bug. 23485 23486 Often people who encounter a bug spend a lot of time investigating 23487 which changes to the input file will make the bug go away and which 23488 changes will not affect it. 23489 23490 This is often time consuming and not very useful, because the way 23491 we will find the bug is by running a single example under the 23492 debugger with breakpoints, not by pure deduction from a series of 23493 examples. We recommend that you save your time for something else. 23494 23495 Of course, if you can find a simpler example to report _instead_ of 23496 the original one, that is a convenience for us. Errors in the 23497 output will be easier to spot, running under the debugger will take 23498 less time, and so on. 23499 23500 However, simplification is not vital; if you do not want to do 23501 this, report the bug anyway and send us the entire test case you 23502 used. 23503 23504 * A patch for the bug. 23505 23506 A patch for the bug does help us if it is a good one. But do not 23507 omit the necessary information, such as the test case, on the 23508 assumption that a patch is all we need. We might see problems with 23509 your patch and decide to fix the problem another way, or we might 23510 not understand it at all. 23511 23512 Sometimes with a program as complicated as 'as' it is very hard to 23513 construct an example that will make the program follow a certain 23514 path through the code. If you do not send us the example, we will 23515 not be able to construct one, so we will not be able to verify that 23516 the bug is fixed. 23517 23518 And if we cannot understand what bug you are trying to fix, or why 23519 your patch should be an improvement, we will not install it. A 23520 test case will help us to understand. 23521 23522 * A guess about what the bug is or what it depends on. 23523 23524 Such guesses are usually wrong. Even we cannot guess right about 23525 such things without first using the debugger to find the facts. 23526 23527 23528File: as.info, Node: Acknowledgements, Next: GNU Free Documentation License, Prev: Reporting Bugs, Up: Top 23529 2353011 Acknowledgements 23531******************* 23532 23533If you have contributed to GAS and your name isn't listed here, it is 23534not meant as a slight. We just don't know about it. Send mail to the 23535maintainer, and we'll correct the situation. Currently the maintainer 23536is Nick Clifton (email address 'nickc@redhat.com'). 23537 23538 Dean Elsner wrote the original GNU assembler for the VAX.(1) 23539 23540 Jay Fenlason maintained GAS for a while, adding support for 23541GDB-specific debug information and the 68k series machines, most of the 23542preprocessing pass, and extensive changes in 'messages.c', 23543'input-file.c', 'write.c'. 23544 23545 K. Richard Pixley maintained GAS for a while, adding various 23546enhancements and many bug fixes, including merging support for several 23547processors, breaking GAS up to handle multiple object file format back 23548ends (including heavy rewrite, testing, an integration of the coff and 23549b.out back ends), adding configuration including heavy testing and 23550verification of cross assemblers and file splits and renaming, converted 23551GAS to strictly ANSI C including full prototypes, added support for 23552m680[34]0 and cpu32, did considerable work on i960 including a COFF port 23553(including considerable amounts of reverse engineering), a SPARC opcode 23554file rewrite, DECstation, rs6000, and hp300hpux host ports, updated 23555"know" assertions and made them work, much other reorganization, 23556cleanup, and lint. 23557 23558 Ken Raeburn wrote the high-level BFD interface code to replace most 23559of the code in format-specific I/O modules. 23560 23561 The original VMS support was contributed by David L. Kashtan. Eric 23562Youngdale has done much work with it since. 23563 23564 The Intel 80386 machine description was written by Eliot Dresselhaus. 23565 23566 Minh Tran-Le at IntelliCorp contributed some AIX 386 support. 23567 23568 The Motorola 88k machine description was contributed by Devon Bowen 23569of Buffalo University and Torbjorn Granlund of the Swedish Institute of 23570Computer Science. 23571 23572 Keith Knowles at the Open Software Foundation wrote the original MIPS 23573back end ('tc-mips.c', 'tc-mips.h'), and contributed Rose format support 23574(which hasn't been merged in yet). Ralph Campbell worked with the MIPS 23575code to support a.out format. 23576 23577 Support for the Zilog Z8k and Renesas H8/300 processors (tc-z8k, 23578tc-h8300), and IEEE 695 object file format (obj-ieee), was written by 23579Steve Chamberlain of Cygnus Support. Steve also modified the COFF back 23580end to use BFD for some low-level operations, for use with the H8/300 23581and AMD 29k targets. 23582 23583 John Gilmore built the AMD 29000 support, added '.include' support, 23584and simplified the configuration of which versions accept which 23585directives. He updated the 68k machine description so that Motorola's 23586opcodes always produced fixed-size instructions (e.g., 'jsr'), while 23587synthetic instructions remained shrinkable ('jbsr'). John fixed many 23588bugs, including true tested cross-compilation support, and one bug in 23589relaxation that took a week and required the proverbial one-bit fix. 23590 23591 Ian Lance Taylor of Cygnus Support merged the Motorola and MIT syntax 23592for the 68k, completed support for some COFF targets (68k, i386 SVR3, 23593and SCO Unix), added support for MIPS ECOFF and ELF targets, wrote the 23594initial RS/6000 and PowerPC assembler, and made a few other minor 23595patches. 23596 23597 Steve Chamberlain made GAS able to generate listings. 23598 23599 Hewlett-Packard contributed support for the HP9000/300. 23600 23601 Jeff Law wrote GAS and BFD support for the native HPPA object format 23602(SOM) along with a fairly extensive HPPA testsuite (for both SOM and ELF 23603object formats). This work was supported by both the Center for 23604Software Science at the University of Utah and Cygnus Support. 23605 23606 Support for ELF format files has been worked on by Mark Eichin of 23607Cygnus Support (original, incomplete implementation for SPARC), Pete 23608Hoogenboom and Jeff Law at the University of Utah (HPPA mainly), Michael 23609Meissner of the Open Software Foundation (i386 mainly), and Ken Raeburn 23610of Cygnus Support (sparc, and some initial 64-bit support). 23611 23612 Linas Vepstas added GAS support for the ESA/390 "IBM 370" 23613architecture. 23614 23615 Richard Henderson rewrote the Alpha assembler. Klaus Kaempf wrote 23616GAS and BFD support for openVMS/Alpha. 23617 23618 Timothy Wall, Michael Hayes, and Greg Smart contributed to the 23619various tic* flavors. 23620 23621 David Heine, Sterling Augustine, Bob Wilson and John Ruttenberg from 23622Tensilica, Inc. added support for Xtensa processors. 23623 23624 Several engineers at Cygnus Support have also provided many small bug 23625fixes and configuration enhancements. 23626 23627 Jon Beniston added support for the Lattice Mico32 architecture. 23628 23629 Many others have contributed large or small bugfixes and 23630enhancements. If you have contributed significant work and are not 23631mentioned on this list, and want to be, let us know. Some of the 23632history has been lost; we are not intentionally leaving anyone out. 23633 23634 ---------- Footnotes ---------- 23635 23636 (1) Any more details? 23637 23638 23639File: as.info, Node: GNU Free Documentation License, Next: AS Index, Prev: Acknowledgements, Up: Top 23640 23641Appendix A GNU Free Documentation License 23642***************************************** 23643 23644 Version 1.3, 3 November 2008 23645 23646 Copyright (C) 2000, 2001, 2002, 2007, 2008 Free Software Foundation, Inc. 23647 <http://fsf.org/> 23648 23649 Everyone is permitted to copy and distribute verbatim copies 23650 of this license document, but changing it is not allowed. 23651 23652 0. PREAMBLE 23653 23654 The purpose of this License is to make a manual, textbook, or other 23655 functional and useful document "free" in the sense of freedom: to 23656 assure everyone the effective freedom to copy and redistribute it, 23657 with or without modifying it, either commercially or 23658 noncommercially. Secondarily, this License preserves for the 23659 author and publisher a way to get credit for their work, while not 23660 being considered responsible for modifications made by others. 23661 23662 This License is a kind of "copyleft", which means that derivative 23663 works of the document must themselves be free in the same sense. 23664 It complements the GNU General Public License, which is a copyleft 23665 license designed for free software. 23666 23667 We have designed this License in order to use it for manuals for 23668 free software, because free software needs free documentation: a 23669 free program should come with manuals providing the same freedoms 23670 that the software does. But this License is not limited to 23671 software manuals; it can be used for any textual work, regardless 23672 of subject matter or whether it is published as a printed book. We 23673 recommend this License principally for works whose purpose is 23674 instruction or reference. 23675 23676 1. APPLICABILITY AND DEFINITIONS 23677 23678 This License applies to any manual or other work, in any medium, 23679 that contains a notice placed by the copyright holder saying it can 23680 be distributed under the terms of this License. Such a notice 23681 grants a world-wide, royalty-free license, unlimited in duration, 23682 to use that work under the conditions stated herein. The 23683 "Document", below, refers to any such manual or work. Any member 23684 of the public is a licensee, and is addressed as "you". You accept 23685 the license if you copy, modify or distribute the work in a way 23686 requiring permission under copyright law. 23687 23688 A "Modified Version" of the Document means any work containing the 23689 Document or a portion of it, either copied verbatim, or with 23690 modifications and/or translated into another language. 23691 23692 A "Secondary Section" is a named appendix or a front-matter section 23693 of the Document that deals exclusively with the relationship of the 23694 publishers or authors of the Document to the Document's overall 23695 subject (or to related matters) and contains nothing that could 23696 fall directly within that overall subject. (Thus, if the Document 23697 is in part a textbook of mathematics, a Secondary Section may not 23698 explain any mathematics.) The relationship could be a matter of 23699 historical connection with the subject or with related matters, or 23700 of legal, commercial, philosophical, ethical or political position 23701 regarding them. 23702 23703 The "Invariant Sections" are certain Secondary Sections whose 23704 titles are designated, as being those of Invariant Sections, in the 23705 notice that says that the Document is released under this License. 23706 If a section does not fit the above definition of Secondary then it 23707 is not allowed to be designated as Invariant. The Document may 23708 contain zero Invariant Sections. If the Document does not identify 23709 any Invariant Sections then there are none. 23710 23711 The "Cover Texts" are certain short passages of text that are 23712 listed, as Front-Cover Texts or Back-Cover Texts, in the notice 23713 that says that the Document is released under this License. A 23714 Front-Cover Text may be at most 5 words, and a Back-Cover Text may 23715 be at most 25 words. 23716 23717 A "Transparent" copy of the Document means a machine-readable copy, 23718 represented in a format whose specification is available to the 23719 general public, that is suitable for revising the document 23720 straightforwardly with generic text editors or (for images composed 23721 of pixels) generic paint programs or (for drawings) some widely 23722 available drawing editor, and that is suitable for input to text 23723 formatters or for automatic translation to a variety of formats 23724 suitable for input to text formatters. A copy made in an otherwise 23725 Transparent file format whose markup, or absence of markup, has 23726 been arranged to thwart or discourage subsequent modification by 23727 readers is not Transparent. An image format is not Transparent if 23728 used for any substantial amount of text. A copy that is not 23729 "Transparent" is called "Opaque". 23730 23731 Examples of suitable formats for Transparent copies include plain 23732 ASCII without markup, Texinfo input format, LaTeX input format, 23733 SGML or XML using a publicly available DTD, and standard-conforming 23734 simple HTML, PostScript or PDF designed for human modification. 23735 Examples of transparent image formats include PNG, XCF and JPG. 23736 Opaque formats include proprietary formats that can be read and 23737 edited only by proprietary word processors, SGML or XML for which 23738 the DTD and/or processing tools are not generally available, and 23739 the machine-generated HTML, PostScript or PDF produced by some word 23740 processors for output purposes only. 23741 23742 The "Title Page" means, for a printed book, the title page itself, 23743 plus such following pages as are needed to hold, legibly, the 23744 material this License requires to appear in the title page. For 23745 works in formats which do not have any title page as such, "Title 23746 Page" means the text near the most prominent appearance of the 23747 work's title, preceding the beginning of the body of the text. 23748 23749 The "publisher" means any person or entity that distributes copies 23750 of the Document to the public. 23751 23752 A section "Entitled XYZ" means a named subunit of the Document 23753 whose title either is precisely XYZ or contains XYZ in parentheses 23754 following text that translates XYZ in another language. (Here XYZ 23755 stands for a specific section name mentioned below, such as 23756 "Acknowledgements", "Dedications", "Endorsements", or "History".) 23757 To "Preserve the Title" of such a section when you modify the 23758 Document means that it remains a section "Entitled XYZ" according 23759 to this definition. 23760 23761 The Document may include Warranty Disclaimers next to the notice 23762 which states that this License applies to the Document. These 23763 Warranty Disclaimers are considered to be included by reference in 23764 this License, but only as regards disclaiming warranties: any other 23765 implication that these Warranty Disclaimers may have is void and 23766 has no effect on the meaning of this License. 23767 23768 2. VERBATIM COPYING 23769 23770 You may copy and distribute the Document in any medium, either 23771 commercially or noncommercially, provided that this License, the 23772 copyright notices, and the license notice saying this License 23773 applies to the Document are reproduced in all copies, and that you 23774 add no other conditions whatsoever to those of this License. You 23775 may not use technical measures to obstruct or control the reading 23776 or further copying of the copies you make or distribute. However, 23777 you may accept compensation in exchange for copies. If you 23778 distribute a large enough number of copies you must also follow the 23779 conditions in section 3. 23780 23781 You may also lend copies, under the same conditions stated above, 23782 and you may publicly display copies. 23783 23784 3. COPYING IN QUANTITY 23785 23786 If you publish printed copies (or copies in media that commonly 23787 have printed covers) of the Document, numbering more than 100, and 23788 the Document's license notice requires Cover Texts, you must 23789 enclose the copies in covers that carry, clearly and legibly, all 23790 these Cover Texts: Front-Cover Texts on the front cover, and 23791 Back-Cover Texts on the back cover. Both covers must also clearly 23792 and legibly identify you as the publisher of these copies. The 23793 front cover must present the full title with all words of the title 23794 equally prominent and visible. You may add other material on the 23795 covers in addition. Copying with changes limited to the covers, as 23796 long as they preserve the title of the Document and satisfy these 23797 conditions, can be treated as verbatim copying in other respects. 23798 23799 If the required texts for either cover are too voluminous to fit 23800 legibly, you should put the first ones listed (as many as fit 23801 reasonably) on the actual cover, and continue the rest onto 23802 adjacent pages. 23803 23804 If you publish or distribute Opaque copies of the Document 23805 numbering more than 100, you must either include a machine-readable 23806 Transparent copy along with each Opaque copy, or state in or with 23807 each Opaque copy a computer-network location from which the general 23808 network-using public has access to download using public-standard 23809 network protocols a complete Transparent copy of the Document, free 23810 of added material. If you use the latter option, you must take 23811 reasonably prudent steps, when you begin distribution of Opaque 23812 copies in quantity, to ensure that this Transparent copy will 23813 remain thus accessible at the stated location until at least one 23814 year after the last time you distribute an Opaque copy (directly or 23815 through your agents or retailers) of that edition to the public. 23816 23817 It is requested, but not required, that you contact the authors of 23818 the Document well before redistributing any large number of copies, 23819 to give them a chance to provide you with an updated version of the 23820 Document. 23821 23822 4. MODIFICATIONS 23823 23824 You may copy and distribute a Modified Version of the Document 23825 under the conditions of sections 2 and 3 above, provided that you 23826 release the Modified Version under precisely this License, with the 23827 Modified Version filling the role of the Document, thus licensing 23828 distribution and modification of the Modified Version to whoever 23829 possesses a copy of it. In addition, you must do these things in 23830 the Modified Version: 23831 23832 A. Use in the Title Page (and on the covers, if any) a title 23833 distinct from that of the Document, and from those of previous 23834 versions (which should, if there were any, be listed in the 23835 History section of the Document). You may use the same title 23836 as a previous version if the original publisher of that 23837 version gives permission. 23838 23839 B. List on the Title Page, as authors, one or more persons or 23840 entities responsible for authorship of the modifications in 23841 the Modified Version, together with at least five of the 23842 principal authors of the Document (all of its principal 23843 authors, if it has fewer than five), unless they release you 23844 from this requirement. 23845 23846 C. State on the Title page the name of the publisher of the 23847 Modified Version, as the publisher. 23848 23849 D. Preserve all the copyright notices of the Document. 23850 23851 E. Add an appropriate copyright notice for your modifications 23852 adjacent to the other copyright notices. 23853 23854 F. Include, immediately after the copyright notices, a license 23855 notice giving the public permission to use the Modified 23856 Version under the terms of this License, in the form shown in 23857 the Addendum below. 23858 23859 G. Preserve in that license notice the full lists of Invariant 23860 Sections and required Cover Texts given in the Document's 23861 license notice. 23862 23863 H. Include an unaltered copy of this License. 23864 23865 I. Preserve the section Entitled "History", Preserve its Title, 23866 and add to it an item stating at least the title, year, new 23867 authors, and publisher of the Modified Version as given on the 23868 Title Page. If there is no section Entitled "History" in the 23869 Document, create one stating the title, year, authors, and 23870 publisher of the Document as given on its Title Page, then add 23871 an item describing the Modified Version as stated in the 23872 previous sentence. 23873 23874 J. Preserve the network location, if any, given in the Document 23875 for public access to a Transparent copy of the Document, and 23876 likewise the network locations given in the Document for 23877 previous versions it was based on. These may be placed in the 23878 "History" section. You may omit a network location for a work 23879 that was published at least four years before the Document 23880 itself, or if the original publisher of the version it refers 23881 to gives permission. 23882 23883 K. For any section Entitled "Acknowledgements" or "Dedications", 23884 Preserve the Title of the section, and preserve in the section 23885 all the substance and tone of each of the contributor 23886 acknowledgements and/or dedications given therein. 23887 23888 L. Preserve all the Invariant Sections of the Document, unaltered 23889 in their text and in their titles. Section numbers or the 23890 equivalent are not considered part of the section titles. 23891 23892 M. Delete any section Entitled "Endorsements". Such a section 23893 may not be included in the Modified Version. 23894 23895 N. Do not retitle any existing section to be Entitled 23896 "Endorsements" or to conflict in title with any Invariant 23897 Section. 23898 23899 O. Preserve any Warranty Disclaimers. 23900 23901 If the Modified Version includes new front-matter sections or 23902 appendices that qualify as Secondary Sections and contain no 23903 material copied from the Document, you may at your option designate 23904 some or all of these sections as invariant. To do this, add their 23905 titles to the list of Invariant Sections in the Modified Version's 23906 license notice. These titles must be distinct from any other 23907 section titles. 23908 23909 You may add a section Entitled "Endorsements", provided it contains 23910 nothing but endorsements of your Modified Version by various 23911 parties--for example, statements of peer review or that the text 23912 has been approved by an organization as the authoritative 23913 definition of a standard. 23914 23915 You may add a passage of up to five words as a Front-Cover Text, 23916 and a passage of up to 25 words as a Back-Cover Text, to the end of 23917 the list of Cover Texts in the Modified Version. Only one passage 23918 of Front-Cover Text and one of Back-Cover Text may be added by (or 23919 through arrangements made by) any one entity. If the Document 23920 already includes a cover text for the same cover, previously added 23921 by you or by arrangement made by the same entity you are acting on 23922 behalf of, you may not add another; but you may replace the old 23923 one, on explicit permission from the previous publisher that added 23924 the old one. 23925 23926 The author(s) and publisher(s) of the Document do not by this 23927 License give permission to use their names for publicity for or to 23928 assert or imply endorsement of any Modified Version. 23929 23930 5. COMBINING DOCUMENTS 23931 23932 You may combine the Document with other documents released under 23933 this License, under the terms defined in section 4 above for 23934 modified versions, provided that you include in the combination all 23935 of the Invariant Sections of all of the original documents, 23936 unmodified, and list them all as Invariant Sections of your 23937 combined work in its license notice, and that you preserve all 23938 their Warranty Disclaimers. 23939 23940 The combined work need only contain one copy of this License, and 23941 multiple identical Invariant Sections may be replaced with a single 23942 copy. If there are multiple Invariant Sections with the same name 23943 but different contents, make the title of each such section unique 23944 by adding at the end of it, in parentheses, the name of the 23945 original author or publisher of that section if known, or else a 23946 unique number. Make the same adjustment to the section titles in 23947 the list of Invariant Sections in the license notice of the 23948 combined work. 23949 23950 In the combination, you must combine any sections Entitled 23951 "History" in the various original documents, forming one section 23952 Entitled "History"; likewise combine any sections Entitled 23953 "Acknowledgements", and any sections Entitled "Dedications". You 23954 must delete all sections Entitled "Endorsements." 23955 23956 6. COLLECTIONS OF DOCUMENTS 23957 23958 You may make a collection consisting of the Document and other 23959 documents released under this License, and replace the individual 23960 copies of this License in the various documents with a single copy 23961 that is included in the collection, provided that you follow the 23962 rules of this License for verbatim copying of each of the documents 23963 in all other respects. 23964 23965 You may extract a single document from such a collection, and 23966 distribute it individually under this License, provided you insert 23967 a copy of this License into the extracted document, and follow this 23968 License in all other respects regarding verbatim copying of that 23969 document. 23970 23971 7. AGGREGATION WITH INDEPENDENT WORKS 23972 23973 A compilation of the Document or its derivatives with other 23974 separate and independent documents or works, in or on a volume of a 23975 storage or distribution medium, is called an "aggregate" if the 23976 copyright resulting from the compilation is not used to limit the 23977 legal rights of the compilation's users beyond what the individual 23978 works permit. When the Document is included in an aggregate, this 23979 License does not apply to the other works in the aggregate which 23980 are not themselves derivative works of the Document. 23981 23982 If the Cover Text requirement of section 3 is applicable to these 23983 copies of the Document, then if the Document is less than one half 23984 of the entire aggregate, the Document's Cover Texts may be placed 23985 on covers that bracket the Document within the aggregate, or the 23986 electronic equivalent of covers if the Document is in electronic 23987 form. Otherwise they must appear on printed covers that bracket 23988 the whole aggregate. 23989 23990 8. TRANSLATION 23991 23992 Translation is considered a kind of modification, so you may 23993 distribute translations of the Document under the terms of section 23994 4. Replacing Invariant Sections with translations requires special 23995 permission from their copyright holders, but you may include 23996 translations of some or all Invariant Sections in addition to the 23997 original versions of these Invariant Sections. You may include a 23998 translation of this License, and all the license notices in the 23999 Document, and any Warranty Disclaimers, provided that you also 24000 include the original English version of this License and the 24001 original versions of those notices and disclaimers. In case of a 24002 disagreement between the translation and the original version of 24003 this License or a notice or disclaimer, the original version will 24004 prevail. 24005 24006 If a section in the Document is Entitled "Acknowledgements", 24007 "Dedications", or "History", the requirement (section 4) to 24008 Preserve its Title (section 1) will typically require changing the 24009 actual title. 24010 24011 9. TERMINATION 24012 24013 You may not copy, modify, sublicense, or distribute the Document 24014 except as expressly provided under this License. Any attempt 24015 otherwise to copy, modify, sublicense, or distribute it is void, 24016 and will automatically terminate your rights under this License. 24017 24018 However, if you cease all violation of this License, then your 24019 license from a particular copyright holder is reinstated (a) 24020 provisionally, unless and until the copyright holder explicitly and 24021 finally terminates your license, and (b) permanently, if the 24022 copyright holder fails to notify you of the violation by some 24023 reasonable means prior to 60 days after the cessation. 24024 24025 Moreover, your license from a particular copyright holder is 24026 reinstated permanently if the copyright holder notifies you of the 24027 violation by some reasonable means, this is the first time you have 24028 received notice of violation of this License (for any work) from 24029 that copyright holder, and you cure the violation prior to 30 days 24030 after your receipt of the notice. 24031 24032 Termination of your rights under this section does not terminate 24033 the licenses of parties who have received copies or rights from you 24034 under this License. If your rights have been terminated and not 24035 permanently reinstated, receipt of a copy of some or all of the 24036 same material does not give you any rights to use it. 24037 24038 10. FUTURE REVISIONS OF THIS LICENSE 24039 24040 The Free Software Foundation may publish new, revised versions of 24041 the GNU Free Documentation License from time to time. Such new 24042 versions will be similar in spirit to the present version, but may 24043 differ in detail to address new problems or concerns. See 24044 <http://www.gnu.org/copyleft/>. 24045 24046 Each version of the License is given a distinguishing version 24047 number. If the Document specifies that a particular numbered 24048 version of this License "or any later version" applies to it, you 24049 have the option of following the terms and conditions either of 24050 that specified version or of any later version that has been 24051 published (not as a draft) by the Free Software Foundation. If the 24052 Document does not specify a version number of this License, you may 24053 choose any version ever published (not as a draft) by the Free 24054 Software Foundation. If the Document specifies that a proxy can 24055 decide which future versions of this License can be used, that 24056 proxy's public statement of acceptance of a version permanently 24057 authorizes you to choose that version for the Document. 24058 24059 11. RELICENSING 24060 24061 "Massive Multiauthor Collaboration Site" (or "MMC Site") means any 24062 World Wide Web server that publishes copyrightable works and also 24063 provides prominent facilities for anybody to edit those works. A 24064 public wiki that anybody can edit is an example of such a server. 24065 A "Massive Multiauthor Collaboration" (or "MMC") contained in the 24066 site means any set of copyrightable works thus published on the MMC 24067 site. 24068 24069 "CC-BY-SA" means the Creative Commons Attribution-Share Alike 3.0 24070 license published by Creative Commons Corporation, a not-for-profit 24071 corporation with a principal place of business in San Francisco, 24072 California, as well as future copyleft versions of that license 24073 published by that same organization. 24074 24075 "Incorporate" means to publish or republish a Document, in whole or 24076 in part, as part of another Document. 24077 24078 An MMC is "eligible for relicensing" if it is licensed under this 24079 License, and if all works that were first published under this 24080 License somewhere other than this MMC, and subsequently 24081 incorporated in whole or in part into the MMC, (1) had no cover 24082 texts or invariant sections, and (2) were thus incorporated prior 24083 to November 1, 2008. 24084 24085 The operator of an MMC Site may republish an MMC contained in the 24086 site under CC-BY-SA on the same site at any time before August 1, 24087 2009, provided the MMC is eligible for relicensing. 24088 24089ADDENDUM: How to use this License for your documents 24090==================================================== 24091 24092To use this License in a document you have written, include a copy of 24093the License in the document and put the following copyright and license 24094notices just after the title page: 24095 24096 Copyright (C) YEAR YOUR NAME. 24097 Permission is granted to copy, distribute and/or modify this document 24098 under the terms of the GNU Free Documentation License, Version 1.3 24099 or any later version published by the Free Software Foundation; 24100 with no Invariant Sections, no Front-Cover Texts, and no Back-Cover 24101 Texts. A copy of the license is included in the section entitled ``GNU 24102 Free Documentation License''. 24103 24104 If you have Invariant Sections, Front-Cover Texts and Back-Cover 24105Texts, replace the "with...Texts." line with this: 24106 24107 with the Invariant Sections being LIST THEIR TITLES, with 24108 the Front-Cover Texts being LIST, and with the Back-Cover Texts 24109 being LIST. 24110 24111 If you have Invariant Sections without Cover Texts, or some other 24112combination of the three, merge those two alternatives to suit the 24113situation. 24114 24115 If your document contains nontrivial examples of program code, we 24116recommend releasing these examples in parallel under your choice of free 24117software license, such as the GNU General Public License, to permit 24118their use in free software. 24119 24120 24121File: as.info, Node: AS Index, Prev: GNU Free Documentation License, Up: Top 24122 24123AS Index 24124******** 24125 24126[index] 24127* Menu: 24128 24129* \" (doublequote character): Strings. (line 43) 24130* \b (backspace character): Strings. (line 15) 24131* \DDD (octal character code): Strings. (line 30) 24132* \f (formfeed character): Strings. (line 18) 24133* \n (newline character): Strings. (line 21) 24134* \r (carriage return character): Strings. (line 24) 24135* \t (tab): Strings. (line 27) 24136* \XD... (hex character code): Strings. (line 36) 24137* \\ (\ character): Strings. (line 40) 24138* #: Comments. (line 33) 24139* #APP: Preprocessing. (line 26) 24140* #NO_APP: Preprocessing. (line 26) 24141* $ in symbol names: D10V-Chars. (line 46) 24142* $ in symbol names <1>: D30V-Chars. (line 70) 24143* $ in symbol names <2>: Meta-Chars. (line 10) 24144* $ in symbol names <3>: SH-Chars. (line 15) 24145* $ in symbol names <4>: SH64-Chars. (line 15) 24146* $a: ARM Mapping Symbols. 24147 (line 9) 24148* $acos math builtin, TIC54X: TIC54X-Builtins. (line 10) 24149* $asin math builtin, TIC54X: TIC54X-Builtins. (line 13) 24150* $atan math builtin, TIC54X: TIC54X-Builtins. (line 16) 24151* $atan2 math builtin, TIC54X: TIC54X-Builtins. (line 19) 24152* $ceil math builtin, TIC54X: TIC54X-Builtins. (line 22) 24153* $cos math builtin, TIC54X: TIC54X-Builtins. (line 28) 24154* $cosh math builtin, TIC54X: TIC54X-Builtins. (line 25) 24155* $cvf math builtin, TIC54X: TIC54X-Builtins. (line 31) 24156* $cvi math builtin, TIC54X: TIC54X-Builtins. (line 34) 24157* $d: AArch64 Mapping Symbols. 24158 (line 12) 24159* $d <1>: ARM Mapping Symbols. 24160 (line 15) 24161* $exp math builtin, TIC54X: TIC54X-Builtins. (line 37) 24162* $fabs math builtin, TIC54X: TIC54X-Builtins. (line 40) 24163* $firstch subsym builtin, TIC54X: TIC54X-Macros. (line 26) 24164* $floor math builtin, TIC54X: TIC54X-Builtins. (line 43) 24165* $fmod math builtin, TIC54X: TIC54X-Builtins. (line 47) 24166* $int math builtin, TIC54X: TIC54X-Builtins. (line 50) 24167* $iscons subsym builtin, TIC54X: TIC54X-Macros. (line 43) 24168* $isdefed subsym builtin, TIC54X: TIC54X-Macros. (line 34) 24169* $ismember subsym builtin, TIC54X: TIC54X-Macros. (line 38) 24170* $isname subsym builtin, TIC54X: TIC54X-Macros. (line 47) 24171* $isreg subsym builtin, TIC54X: TIC54X-Macros. (line 50) 24172* $lastch subsym builtin, TIC54X: TIC54X-Macros. (line 30) 24173* $ldexp math builtin, TIC54X: TIC54X-Builtins. (line 53) 24174* $log math builtin, TIC54X: TIC54X-Builtins. (line 59) 24175* $log10 math builtin, TIC54X: TIC54X-Builtins. (line 56) 24176* $max math builtin, TIC54X: TIC54X-Builtins. (line 62) 24177* $min math builtin, TIC54X: TIC54X-Builtins. (line 65) 24178* $pow math builtin, TIC54X: TIC54X-Builtins. (line 68) 24179* $round math builtin, TIC54X: TIC54X-Builtins. (line 71) 24180* $sgn math builtin, TIC54X: TIC54X-Builtins. (line 74) 24181* $sin math builtin, TIC54X: TIC54X-Builtins. (line 77) 24182* $sinh math builtin, TIC54X: TIC54X-Builtins. (line 80) 24183* $sqrt math builtin, TIC54X: TIC54X-Builtins. (line 83) 24184* $structacc subsym builtin, TIC54X: TIC54X-Macros. (line 57) 24185* $structsz subsym builtin, TIC54X: TIC54X-Macros. (line 54) 24186* $symcmp subsym builtin, TIC54X: TIC54X-Macros. (line 23) 24187* $symlen subsym builtin, TIC54X: TIC54X-Macros. (line 20) 24188* $t: ARM Mapping Symbols. 24189 (line 12) 24190* $tan math builtin, TIC54X: TIC54X-Builtins. (line 86) 24191* $tanh math builtin, TIC54X: TIC54X-Builtins. (line 89) 24192* $trunc math builtin, TIC54X: TIC54X-Builtins. (line 92) 24193* $x: AArch64 Mapping Symbols. 24194 (line 9) 24195* %gp: RX-Modifiers. (line 6) 24196* %gpreg: RX-Modifiers. (line 22) 24197* %pidreg: RX-Modifiers. (line 25) 24198* -+ option, VAX/VMS: VAX-Opts. (line 71) 24199* --: Command Line. (line 10) 24200* --32 option, i386: i386-Options. (line 8) 24201* --32 option, x86-64: i386-Options. (line 8) 24202* --64 option, i386: i386-Options. (line 8) 24203* --64 option, x86-64: i386-Options. (line 8) 24204* --absolute-literals: Xtensa Options. (line 39) 24205* --allow-reg-prefix: SH Options. (line 9) 24206* --alternate: alternate. (line 6) 24207* --auto-litpools: Xtensa Options. (line 22) 24208* --base-size-default-16: M68K-Opts. (line 66) 24209* --base-size-default-32: M68K-Opts. (line 66) 24210* --big: SH Options. (line 9) 24211* --bitwise-or option, M680x0: M68K-Opts. (line 59) 24212* --compress-debug-sections= option: Overview. (line 346) 24213* --disp-size-default-16: M68K-Opts. (line 75) 24214* --disp-size-default-32: M68K-Opts. (line 75) 24215* --divide option, i386: i386-Options. (line 24) 24216* --dsp: SH Options. (line 9) 24217* --emulation=crisaout command line option, CRIS: CRIS-Opts. (line 9) 24218* --emulation=criself command line option, CRIS: CRIS-Opts. (line 9) 24219* --enforce-aligned-data: Sparc-Aligned-Data. (line 11) 24220* --fatal-warnings: W. (line 16) 24221* --fdpic: SH Options. (line 31) 24222* --fix-v4bx command line option, ARM: ARM Options. (line 191) 24223* --fixed-special-register-names command line option, MMIX: MMIX-Opts. 24224 (line 8) 24225* --force-long-branches: M68HC11-Opts. (line 81) 24226* --generate-example: M68HC11-Opts. (line 98) 24227* --globalize-symbols command line option, MMIX: MMIX-Opts. (line 12) 24228* --gnu-syntax command line option, MMIX: MMIX-Opts. (line 16) 24229* --linker-allocated-gregs command line option, MMIX: MMIX-Opts. 24230 (line 67) 24231* --listing-cont-lines: listing. (line 34) 24232* --listing-lhs-width: listing. (line 16) 24233* --listing-lhs-width2: listing. (line 21) 24234* --listing-rhs-width: listing. (line 28) 24235* --little: SH Options. (line 9) 24236* --longcalls: Xtensa Options. (line 53) 24237* --march=ARCHITECTURE command line option, CRIS: CRIS-Opts. (line 34) 24238* --MD: MD. (line 6) 24239* --mul-bug-abort command line option, CRIS: CRIS-Opts. (line 63) 24240* --no-absolute-literals: Xtensa Options. (line 39) 24241* --no-auto-litpools: Xtensa Options. (line 22) 24242* --no-expand command line option, MMIX: MMIX-Opts. (line 31) 24243* --no-longcalls: Xtensa Options. (line 53) 24244* --no-merge-gregs command line option, MMIX: MMIX-Opts. (line 36) 24245* --no-mul-bug-abort command line option, CRIS: CRIS-Opts. (line 63) 24246* --no-pad-sections: no-pad-sections. (line 6) 24247* --no-predefined-syms command line option, MMIX: MMIX-Opts. (line 22) 24248* --no-pushj-stubs command line option, MMIX: MMIX-Opts. (line 54) 24249* --no-stubs command line option, MMIX: MMIX-Opts. (line 54) 24250* --no-target-align: Xtensa Options. (line 46) 24251* --no-text-section-literals: Xtensa Options. (line 7) 24252* --no-trampolines: Xtensa Options. (line 74) 24253* --no-transform: Xtensa Options. (line 62) 24254* --no-underscore command line option, CRIS: CRIS-Opts. (line 15) 24255* --no-warn: W. (line 11) 24256* --pcrel: M68K-Opts. (line 87) 24257* --pic command line option, CRIS: CRIS-Opts. (line 27) 24258* --print-insn-syntax: M68HC11-Opts. (line 87) 24259* --print-insn-syntax <1>: XGATE-Opts. (line 25) 24260* --print-opcodes: M68HC11-Opts. (line 91) 24261* --print-opcodes <1>: XGATE-Opts. (line 29) 24262* --register-prefix-optional option, M680x0: M68K-Opts. (line 46) 24263* --relax: SH Options. (line 9) 24264* --relax command line option, MMIX: MMIX-Opts. (line 19) 24265* --rename-section: Xtensa Options. (line 70) 24266* --renesas: SH Options. (line 9) 24267* --sectname-subst: Section. (line 71) 24268* --short-branches: M68HC11-Opts. (line 67) 24269* --small: SH Options. (line 9) 24270* --statistics: statistics. (line 6) 24271* --strict-direct-mode: M68HC11-Opts. (line 57) 24272* --target-align: Xtensa Options. (line 46) 24273* --text-section-literals: Xtensa Options. (line 7) 24274* --traditional-format: traditional-format. (line 6) 24275* --trampolines: Xtensa Options. (line 74) 24276* --transform: Xtensa Options. (line 62) 24277* --underscore command line option, CRIS: CRIS-Opts. (line 15) 24278* --warn: W. (line 19) 24279* --x32 option, i386: i386-Options. (line 8) 24280* --x32 option, x86-64: i386-Options. (line 8) 24281* --xgate-ramoffset: M68HC11-Opts. (line 36) 24282* -1 option, VAX/VMS: VAX-Opts. (line 77) 24283* -32addr command line option, Alpha: Alpha Options. (line 57) 24284* -a: a. (line 6) 24285* -A options, i960: Options-i960. (line 6) 24286* -ac: a. (line 6) 24287* -ad: a. (line 6) 24288* -ag: a. (line 6) 24289* -ah: a. (line 6) 24290* -al: a. (line 6) 24291* -Aleon: Sparc-Opts. (line 25) 24292* -an: a. (line 6) 24293* -as: a. (line 6) 24294* -Asparc: Sparc-Opts. (line 25) 24295* -Asparcfmaf: Sparc-Opts. (line 25) 24296* -Asparcima: Sparc-Opts. (line 25) 24297* -Asparclet: Sparc-Opts. (line 25) 24298* -Asparclite: Sparc-Opts. (line 25) 24299* -Asparcvis: Sparc-Opts. (line 25) 24300* -Asparcvis2: Sparc-Opts. (line 25) 24301* -Asparcvis3: Sparc-Opts. (line 25) 24302* -Asparcvis3r: Sparc-Opts. (line 25) 24303* -Av6: Sparc-Opts. (line 25) 24304* -Av7: Sparc-Opts. (line 25) 24305* -Av8: Sparc-Opts. (line 25) 24306* -Av9: Sparc-Opts. (line 25) 24307* -Av9a: Sparc-Opts. (line 25) 24308* -Av9b: Sparc-Opts. (line 25) 24309* -Av9c: Sparc-Opts. (line 25) 24310* -Av9d: Sparc-Opts. (line 25) 24311* -Av9e: Sparc-Opts. (line 25) 24312* -Av9m: Sparc-Opts. (line 25) 24313* -Av9v: Sparc-Opts. (line 25) 24314* -b option, i960: Options-i960. (line 22) 24315* -big option, M32R: M32R-Opts. (line 35) 24316* -D: D. (line 6) 24317* -D, ignored on VAX: VAX-Opts. (line 11) 24318* -d, VAX option: VAX-Opts. (line 16) 24319* -eabi= command line option, ARM: ARM Options. (line 167) 24320* -EB command line option, AArch64: AArch64 Options. (line 6) 24321* -EB command line option, ARC: ARC Options. (line 84) 24322* -EB command line option, ARM: ARM Options. (line 172) 24323* -EB option (MIPS): MIPS Options. (line 13) 24324* -EB option, M32R: M32R-Opts. (line 39) 24325* -EB option, TILE-Gx: TILE-Gx Options. (line 11) 24326* -EL command line option, AArch64: AArch64 Options. (line 10) 24327* -EL command line option, ARC: ARC Options. (line 88) 24328* -EL command line option, ARM: ARM Options. (line 183) 24329* -EL option (MIPS): MIPS Options. (line 13) 24330* -EL option, M32R: M32R-Opts. (line 32) 24331* -EL option, TILE-Gx: TILE-Gx Options. (line 11) 24332* -f: f. (line 6) 24333* -F command line option, Alpha: Alpha Options. (line 57) 24334* -fno-pic option, RISC-V: RISC-V-Opts. (line 11) 24335* -fpic option, RISC-V: RISC-V-Opts. (line 8) 24336* -g command line option, Alpha: Alpha Options. (line 47) 24337* -G command line option, Alpha: Alpha Options. (line 53) 24338* -G option (MIPS): MIPS Options. (line 8) 24339* -h option, VAX/VMS: VAX-Opts. (line 45) 24340* -H option, VAX/VMS: VAX-Opts. (line 81) 24341* -I PATH: I. (line 6) 24342* -ignore-parallel-conflicts option, M32RX: M32R-Opts. (line 87) 24343* -Ip option, M32RX: M32R-Opts. (line 97) 24344* -J, ignored on VAX: VAX-Opts. (line 27) 24345* -K: K. (line 6) 24346* -k command line option, ARM: ARM Options. (line 187) 24347* -KPIC option, M32R: M32R-Opts. (line 42) 24348* -KPIC option, MIPS: MIPS Options. (line 21) 24349* -L: L. (line 6) 24350* -l option, M680x0: M68K-Opts. (line 34) 24351* -little option, M32R: M32R-Opts. (line 27) 24352* -M: M. (line 6) 24353* -m11/03: PDP-11-Options. (line 140) 24354* -m11/04: PDP-11-Options. (line 143) 24355* -m11/05: PDP-11-Options. (line 146) 24356* -m11/10: PDP-11-Options. (line 146) 24357* -m11/15: PDP-11-Options. (line 149) 24358* -m11/20: PDP-11-Options. (line 149) 24359* -m11/21: PDP-11-Options. (line 152) 24360* -m11/23: PDP-11-Options. (line 155) 24361* -m11/24: PDP-11-Options. (line 155) 24362* -m11/34: PDP-11-Options. (line 158) 24363* -m11/34a: PDP-11-Options. (line 161) 24364* -m11/35: PDP-11-Options. (line 164) 24365* -m11/40: PDP-11-Options. (line 164) 24366* -m11/44: PDP-11-Options. (line 167) 24367* -m11/45: PDP-11-Options. (line 170) 24368* -m11/50: PDP-11-Options. (line 170) 24369* -m11/53: PDP-11-Options. (line 173) 24370* -m11/55: PDP-11-Options. (line 170) 24371* -m11/60: PDP-11-Options. (line 176) 24372* -m11/70: PDP-11-Options. (line 170) 24373* -m11/73: PDP-11-Options. (line 173) 24374* -m11/83: PDP-11-Options. (line 173) 24375* -m11/84: PDP-11-Options. (line 173) 24376* -m11/93: PDP-11-Options. (line 173) 24377* -m11/94: PDP-11-Options. (line 173) 24378* -m16c option, M16C: M32C-Opts. (line 12) 24379* -m31 option, s390: s390 Options. (line 8) 24380* -m32 option, TILE-Gx: TILE-Gx Options. (line 8) 24381* -m32bit-doubles: RX-Opts. (line 9) 24382* -m32c option, M32C: M32C-Opts. (line 9) 24383* -m32r option, M32R: M32R-Opts. (line 21) 24384* -m32rx option, M32R2: M32R-Opts. (line 17) 24385* -m32rx option, M32RX: M32R-Opts. (line 9) 24386* -m4byte-align command line option, V850: V850 Options. (line 90) 24387* -m64 option, s390: s390 Options. (line 8) 24388* -m64 option, TILE-Gx: TILE-Gx Options. (line 8) 24389* -m64bit-doubles: RX-Opts. (line 15) 24390* -m68000 and related options: M68K-Opts. (line 99) 24391* -m68hc11: M68HC11-Opts. (line 9) 24392* -m68hc12: M68HC11-Opts. (line 14) 24393* -m68hcs12: M68HC11-Opts. (line 21) 24394* -m8byte-align command line option, V850: V850 Options. (line 86) 24395* -mabi= command line option, AArch64: AArch64 Options. (line 14) 24396* -mabi=ABI option, RISC-V: RISC-V-Opts. (line 18) 24397* -madd-bnd-prefix option, i386: i386-Options. (line 134) 24398* -madd-bnd-prefix option, x86-64: i386-Options. (line 134) 24399* -mall: PDP-11-Options. (line 26) 24400* -mall-enabled command line option, LM32: LM32 Options. (line 30) 24401* -mall-extensions: PDP-11-Options. (line 26) 24402* -mall-opcodes command line option, AVR: AVR Options. (line 108) 24403* -mamd64 option, x86-64: i386-Options. (line 190) 24404* -mapcs-26 command line option, ARM: ARM Options. (line 139) 24405* -mapcs-32 command line option, ARM: ARM Options. (line 139) 24406* -mapcs-float command line option, ARM: ARM Options. (line 153) 24407* -mapcs-reentrant command line option, ARM: ARM Options. (line 158) 24408* -march= command line option, AArch64: AArch64 Options. (line 39) 24409* -march= command line option, ARM: ARM Options. (line 73) 24410* -march= command line option, M680x0: M68K-Opts. (line 8) 24411* -march= command line option, TIC6X: TIC6X Options. (line 6) 24412* -march= option, i386: i386-Options. (line 31) 24413* -march= option, s390: s390 Options. (line 25) 24414* -march= option, x86-64: i386-Options. (line 31) 24415* -march=ISA option, RISC-V: RISC-V-Opts. (line 14) 24416* -matpcs command line option, ARM: ARM Options. (line 145) 24417* -mavxscalar= option, i386: i386-Options. (line 92) 24418* -mavxscalar= option, x86-64: i386-Options. (line 92) 24419* -mbarrel-shift-enabled command line option, LM32: LM32 Options. 24420 (line 12) 24421* -mbig-endian: RX-Opts. (line 20) 24422* -mbig-obj option, x86-64: i386-Options. (line 148) 24423* -mbreak-enabled command line option, LM32: LM32 Options. (line 27) 24424* -mccs command line option, ARM: ARM Options. (line 200) 24425* -mcis: PDP-11-Options. (line 32) 24426* -mcode-density command line option, ARC: ARC Options. (line 93) 24427* -mconstant-gp command line option, IA-64: IA-64 Options. (line 6) 24428* -mCPU command line option, Alpha: Alpha Options. (line 6) 24429* -mcpu option, cpu: TIC54X-Opts. (line 15) 24430* -mcpu=: RX-Opts. (line 75) 24431* -mcpu= command line option, AArch64: AArch64 Options. (line 19) 24432* -mcpu= command line option, ARM: ARM Options. (line 6) 24433* -mcpu= command line option, Blackfin: Blackfin Options. (line 6) 24434* -mcpu= command line option, M680x0: M68K-Opts. (line 14) 24435* -mcpu=CPU command line option, ARC: ARC Options. (line 10) 24436* -mcsm: PDP-11-Options. (line 43) 24437* -mdcache-enabled command line option, LM32: LM32 Options. (line 24) 24438* -mdebug command line option, Alpha: Alpha Options. (line 25) 24439* -mdivide-enabled command line option, LM32: LM32 Options. (line 9) 24440* -mdpfp command line option, ARC: ARC Options. (line 108) 24441* -mdsbt command line option, TIC6X: TIC6X Options. (line 13) 24442* -me option, stderr redirect: TIC54X-Opts. (line 20) 24443* -meis: PDP-11-Options. (line 46) 24444* -mepiphany command line option, Epiphany: Epiphany Options. 24445 (line 9) 24446* -mepiphany16 command line option, Epiphany: Epiphany Options. 24447 (line 13) 24448* -merrors-to-file option, stderr redirect: TIC54X-Opts. (line 20) 24449* -mesa option, s390: s390 Options. (line 17) 24450* -mevexlig= option, i386: i386-Options. (line 100) 24451* -mevexlig= option, x86-64: i386-Options. (line 100) 24452* -mevexrcig= option, i386: i386-Options. (line 180) 24453* -mevexrcig= option, x86-64: i386-Options. (line 180) 24454* -mevexwig= option, i386: i386-Options. (line 110) 24455* -mevexwig= option, x86-64: i386-Options. (line 110) 24456* -mf option, far-mode: TIC54X-Opts. (line 8) 24457* -mf11: PDP-11-Options. (line 122) 24458* -mfar-mode option, far-mode: TIC54X-Opts. (line 8) 24459* -mfdpic command line option, Blackfin: Blackfin Options. (line 19) 24460* -mfence-as-lock-add= option, i386: i386-Options. (line 161) 24461* -mfence-as-lock-add= option, x86-64: i386-Options. (line 161) 24462* -mfis: PDP-11-Options. (line 51) 24463* -mfloat-abi= command line option, ARM: ARM Options. (line 162) 24464* -mfp-11: PDP-11-Options. (line 56) 24465* -mfpp: PDP-11-Options. (line 56) 24466* -mfpu: PDP-11-Options. (line 56) 24467* -mfpu= command line option, ARM: ARM Options. (line 90) 24468* -mfpuda command line option, ARC: ARC Options. (line 111) 24469* -mgcc-abi: RX-Opts. (line 63) 24470* -mgcc-abi command line option, V850: V850 Options. (line 79) 24471* -mhard-float command line option, V850: V850 Options. (line 101) 24472* -micache-enabled command line option, LM32: LM32 Options. (line 21) 24473* -mimplicit-it command line option, ARM: ARM Options. (line 123) 24474* -mint-register: RX-Opts. (line 57) 24475* -mintel64 option, x86-64: i386-Options. (line 190) 24476* -mip2022 option, IP2K: IP2K-Opts. (line 14) 24477* -mip2022ext option, IP2022: IP2K-Opts. (line 9) 24478* -mj11: PDP-11-Options. (line 126) 24479* -mka11: PDP-11-Options. (line 92) 24480* -mkb11: PDP-11-Options. (line 95) 24481* -mkd11a: PDP-11-Options. (line 98) 24482* -mkd11b: PDP-11-Options. (line 101) 24483* -mkd11d: PDP-11-Options. (line 104) 24484* -mkd11e: PDP-11-Options. (line 107) 24485* -mkd11f: PDP-11-Options. (line 110) 24486* -mkd11h: PDP-11-Options. (line 110) 24487* -mkd11k: PDP-11-Options. (line 114) 24488* -mkd11q: PDP-11-Options. (line 110) 24489* -mkd11z: PDP-11-Options. (line 118) 24490* -mkev11: PDP-11-Options. (line 51) 24491* -mkev11 <1>: PDP-11-Options. (line 51) 24492* -mlimited-eis: PDP-11-Options. (line 64) 24493* -mlink-relax command line option, AVR: AVR Options. (line 120) 24494* -mlittle-endian: RX-Opts. (line 26) 24495* -mlong: M68HC11-Opts. (line 45) 24496* -mlong <1>: XGATE-Opts. (line 13) 24497* -mlong-double: M68HC11-Opts. (line 53) 24498* -mlong-double <1>: XGATE-Opts. (line 21) 24499* -mm9s12x: M68HC11-Opts. (line 27) 24500* -mm9s12xg: M68HC11-Opts. (line 32) 24501* -mmcu= command line option, AVR: AVR Options. (line 6) 24502* -mmfpt: PDP-11-Options. (line 70) 24503* -mmicrocode: PDP-11-Options. (line 83) 24504* -mmnemonic= option, i386: i386-Options. (line 117) 24505* -mmnemonic= option, x86-64: i386-Options. (line 117) 24506* -mmultiply-enabled command line option, LM32: LM32 Options. 24507 (line 6) 24508* -mmutiproc: PDP-11-Options. (line 73) 24509* -mmxps: PDP-11-Options. (line 77) 24510* -mnaked-reg option, i386: i386-Options. (line 129) 24511* -mnaked-reg option, x86-64: i386-Options. (line 129) 24512* -mnan= command line option, MIPS: MIPS Options. (line 379) 24513* -mno-allow-string-insns: RX-Opts. (line 82) 24514* -mno-cis: PDP-11-Options. (line 32) 24515* -mno-csm: PDP-11-Options. (line 43) 24516* -mno-dsbt command line option, TIC6X: TIC6X Options. (line 13) 24517* -mno-eis: PDP-11-Options. (line 46) 24518* -mno-extensions: PDP-11-Options. (line 29) 24519* -mno-fdpic command line option, Blackfin: Blackfin Options. 24520 (line 22) 24521* -mno-fis: PDP-11-Options. (line 51) 24522* -mno-fp-11: PDP-11-Options. (line 56) 24523* -mno-fpp: PDP-11-Options. (line 56) 24524* -mno-fpu: PDP-11-Options. (line 56) 24525* -mno-kev11: PDP-11-Options. (line 51) 24526* -mno-limited-eis: PDP-11-Options. (line 64) 24527* -mno-link-relax command line option, AVR: AVR Options. (line 124) 24528* -mno-mfpt: PDP-11-Options. (line 70) 24529* -mno-microcode: PDP-11-Options. (line 83) 24530* -mno-mutiproc: PDP-11-Options. (line 73) 24531* -mno-mxps: PDP-11-Options. (line 77) 24532* -mno-pic: PDP-11-Options. (line 11) 24533* -mno-pic command line option, TIC6X: TIC6X Options. (line 36) 24534* -mno-regnames option, s390: s390 Options. (line 50) 24535* -mno-skip-bug command line option, AVR: AVR Options. (line 111) 24536* -mno-spl: PDP-11-Options. (line 80) 24537* -mno-sym32: MIPS Options. (line 288) 24538* -mno-verbose-error command line option, AArch64: AArch64 Options. 24539 (line 59) 24540* -mno-wrap command line option, AVR: AVR Options. (line 114) 24541* -mnopic command line option, Blackfin: Blackfin Options. (line 22) 24542* -mnps400 command line option, ARC: ARC Options. (line 102) 24543* -momit-lock-prefix= option, i386: i386-Options. (line 152) 24544* -momit-lock-prefix= option, x86-64: i386-Options. (line 152) 24545* -mpic: PDP-11-Options. (line 11) 24546* -mpic command line option, TIC6X: TIC6X Options. (line 36) 24547* -mpid: RX-Opts. (line 50) 24548* -mpid= command line option, TIC6X: TIC6X Options. (line 23) 24549* -mregnames option, s390: s390 Options. (line 47) 24550* -mrelax command line option, ARC: ARC Options. (line 97) 24551* -mrelax command line option, V850: V850 Options. (line 72) 24552* -mrelax-relocations= option, i386: i386-Options. (line 170) 24553* -mrelax-relocations= option, x86-64: i386-Options. (line 170) 24554* -mrh850-abi command line option, V850: V850 Options. (line 82) 24555* -mrmw command line option, AVR: AVR Options. (line 117) 24556* -mrx-abi: RX-Opts. (line 69) 24557* -mshared option, i386: i386-Options. (line 139) 24558* -mshared option, x86-64: i386-Options. (line 139) 24559* -mshort: M68HC11-Opts. (line 40) 24560* -mshort <1>: XGATE-Opts. (line 8) 24561* -mshort-double: M68HC11-Opts. (line 49) 24562* -mshort-double <1>: XGATE-Opts. (line 17) 24563* -msign-extend-enabled command line option, LM32: LM32 Options. 24564 (line 15) 24565* -msmall-data-limit: RX-Opts. (line 42) 24566* -msoft-float command line option, V850: V850 Options. (line 95) 24567* -mspfp command line option, ARC: ARC Options. (line 105) 24568* -mspl: PDP-11-Options. (line 80) 24569* -msse-check= option, i386: i386-Options. (line 82) 24570* -msse-check= option, x86-64: i386-Options. (line 82) 24571* -msse2avx option, i386: i386-Options. (line 78) 24572* -msse2avx option, x86-64: i386-Options. (line 78) 24573* -msym32: MIPS Options. (line 288) 24574* -msyntax= option, i386: i386-Options. (line 123) 24575* -msyntax= option, x86-64: i386-Options. (line 123) 24576* -mt11: PDP-11-Options. (line 130) 24577* -mthumb command line option, ARM: ARM Options. (line 114) 24578* -mthumb-interwork command line option, ARM: ARM Options. (line 119) 24579* -mtune= option, i386: i386-Options. (line 70) 24580* -mtune= option, x86-64: i386-Options. (line 70) 24581* -mtune=ARCH command line option, Visium: Visium Options. (line 8) 24582* -muse-conventional-section-names: RX-Opts. (line 33) 24583* -muse-renesas-section-names: RX-Opts. (line 37) 24584* -muser-enabled command line option, LM32: LM32 Options. (line 18) 24585* -mv850 command line option, V850: V850 Options. (line 23) 24586* -mv850any command line option, V850: V850 Options. (line 41) 24587* -mv850e command line option, V850: V850 Options. (line 29) 24588* -mv850e1 command line option, V850: V850 Options. (line 35) 24589* -mv850e2 command line option, V850: V850 Options. (line 51) 24590* -mv850e2v3 command line option, V850: V850 Options. (line 57) 24591* -mv850e2v4 command line option, V850: V850 Options. (line 63) 24592* -mv850e3v5 command line option, V850: V850 Options. (line 66) 24593* -mverbose-error command line option, AArch64: AArch64 Options. 24594 (line 55) 24595* -mvxworks-pic option, MIPS: MIPS Options. (line 26) 24596* -mwarn-areg-zero option, s390: s390 Options. (line 53) 24597* -mwarn-deprecated command line option, ARM: ARM Options. (line 195) 24598* -mwarn-syms command line option, ARM: ARM Options. (line 203) 24599* -mzarch option, s390: s390 Options. (line 17) 24600* -m[no-]68851 command line option, M680x0: M68K-Opts. (line 21) 24601* -m[no-]68881 command line option, M680x0: M68K-Opts. (line 21) 24602* -m[no-]div command line option, M680x0: M68K-Opts. (line 21) 24603* -m[no-]emac command line option, M680x0: M68K-Opts. (line 21) 24604* -m[no-]float command line option, M680x0: M68K-Opts. (line 21) 24605* -m[no-]mac command line option, M680x0: M68K-Opts. (line 21) 24606* -m[no-]usp command line option, M680x0: M68K-Opts. (line 21) 24607* -N command line option, CRIS: CRIS-Opts. (line 59) 24608* -nIp option, M32RX: M32R-Opts. (line 101) 24609* -no-bitinst, M32R2: M32R-Opts. (line 54) 24610* -no-ignore-parallel-conflicts option, M32RX: M32R-Opts. (line 93) 24611* -no-mdebug command line option, Alpha: Alpha Options. (line 25) 24612* -no-parallel option, M32RX: M32R-Opts. (line 51) 24613* -no-relax option, i960: Options-i960. (line 66) 24614* -no-warn-explicit-parallel-conflicts option, M32RX: M32R-Opts. 24615 (line 79) 24616* -no-warn-unmatched-high option, M32R: M32R-Opts. (line 111) 24617* -nocpp ignored (MIPS): MIPS Options. (line 291) 24618* -noreplace command line option, Alpha: Alpha Options. (line 40) 24619* -o: o. (line 6) 24620* -O option, M32RX: M32R-Opts. (line 59) 24621* -parallel option, M32RX: M32R-Opts. (line 46) 24622* -R: R. (line 6) 24623* -r800 command line option, Z80: Z80 Options. (line 35) 24624* -relax command line option, Alpha: Alpha Options. (line 32) 24625* -replace command line option, Alpha: Alpha Options. (line 40) 24626* -S, ignored on VAX: VAX-Opts. (line 11) 24627* -T, ignored on VAX: VAX-Opts. (line 11) 24628* -t, ignored on VAX: VAX-Opts. (line 36) 24629* -v: v. (line 6) 24630* -V, redundant on VAX: VAX-Opts. (line 22) 24631* -version: v. (line 6) 24632* -W: W. (line 11) 24633* -warn-explicit-parallel-conflicts option, M32RX: M32R-Opts. 24634 (line 65) 24635* -warn-unmatched-high option, M32R: M32R-Opts. (line 105) 24636* -Wnp option, M32RX: M32R-Opts. (line 83) 24637* -Wnuh option, M32RX: M32R-Opts. (line 117) 24638* -Wp option, M32RX: M32R-Opts. (line 75) 24639* -wsigned_overflow command line option, V850: V850 Options. (line 9) 24640* -Wuh option, M32RX: M32R-Opts. (line 114) 24641* -wunsigned_overflow command line option, V850: V850 Options. 24642 (line 16) 24643* -x command line option, MMIX: MMIX-Opts. (line 44) 24644* -z80 command line option, Z80: Z80 Options. (line 8) 24645* -z8001 command line option, Z8000: Z8000 Options. (line 6) 24646* -z8002 command line option, Z8000: Z8000 Options. (line 9) 24647* . (symbol): Dot. (line 6) 24648* .2byte directive, ARM: ARM Directives. (line 6) 24649* .4byte directive, ARM: ARM Directives. (line 6) 24650* .8byte directive, ARM: ARM Directives. (line 6) 24651* .align directive, ARM: ARM Directives. (line 11) 24652* .align directive, TILE-Gx: TILE-Gx Directives. (line 6) 24653* .align directive, TILEPro: TILEPro Directives. (line 6) 24654* .allow_suspicious_bundles directive, TILE-Gx: TILE-Gx Directives. 24655 (line 10) 24656* .allow_suspicious_bundles directive, TILEPro: TILEPro Directives. 24657 (line 10) 24658* .arch directive, AArch64: AArch64 Directives. (line 6) 24659* .arch directive, ARM: ARM Directives. (line 18) 24660* .arch directive, TIC6X: TIC6X Directives. (line 10) 24661* .arch_extension directive, AArch64: AArch64 Directives. (line 13) 24662* .arch_extension directive, ARM: ARM Directives. (line 25) 24663* .arm directive, ARM: ARM Directives. (line 33) 24664* .big directive, M32RX: M32R-Directives. (line 88) 24665* .bss directive, AArch64: AArch64 Directives. (line 21) 24666* .bss directive, ARM: ARM Directives. (line 36) 24667* .c6xabi_attribute directive, TIC6X: TIC6X Directives. (line 20) 24668* .cantunwind directive, ARM: ARM Directives. (line 39) 24669* .cantunwind directive, TIC6X: TIC6X Directives. (line 13) 24670* .code directive, ARM: ARM Directives. (line 43) 24671* .cpu directive, AArch64: AArch64 Directives. (line 24) 24672* .cpu directive, ARM: ARM Directives. (line 47) 24673* .dn and .qn directives, ARM: ARM Directives. (line 54) 24674* .dword directive, AArch64: AArch64 Directives. (line 28) 24675* .eabi_attribute directive, ARM: ARM Directives. (line 78) 24676* .ehtype directive, TIC6X: TIC6X Directives. (line 31) 24677* .endp directive, TIC6X: TIC6X Directives. (line 34) 24678* .even directive, AArch64: AArch64 Directives. (line 31) 24679* .even directive, ARM: ARM Directives. (line 106) 24680* .extend directive, ARM: ARM Directives. (line 109) 24681* .fnend directive, ARM: ARM Directives. (line 115) 24682* .fnstart directive, ARM: ARM Directives. (line 123) 24683* .force_thumb directive, ARM: ARM Directives. (line 126) 24684* .fpu directive, ARM: ARM Directives. (line 130) 24685* .global: MIPS insn. (line 12) 24686* .gnu_attribute 4, N directive, MIPS: MIPS FP ABI History. 24687 (line 6) 24688* .gnu_attribute Tag_GNU_MIPS_ABI_FP, N directive, MIPS: MIPS FP ABI History. 24689 (line 6) 24690* .handlerdata directive, ARM: ARM Directives. (line 134) 24691* .handlerdata directive, TIC6X: TIC6X Directives. (line 39) 24692* .insn: MIPS insn. (line 6) 24693* .insn directive, s390: s390 Directives. (line 11) 24694* .inst directive, AArch64: AArch64 Directives. (line 35) 24695* .inst directive, ARM: ARM Directives. (line 143) 24696* .ldouble directive, ARM: ARM Directives. (line 109) 24697* .little directive, M32RX: M32R-Directives. (line 82) 24698* .long directive, s390: s390 Directives. (line 16) 24699* .ltorg directive, AArch64: AArch64 Directives. (line 39) 24700* .ltorg directive, ARM: ARM Directives. (line 153) 24701* .ltorg directive, s390: s390 Directives. (line 79) 24702* .m32r directive, M32R: M32R-Directives. (line 66) 24703* .m32r2 directive, M32R2: M32R-Directives. (line 77) 24704* .m32rx directive, M32RX: M32R-Directives. (line 72) 24705* .machine directive, s390: s390 Directives. (line 84) 24706* .machinemode directive, s390: s390 Directives. (line 101) 24707* .module: MIPS assembly options. 24708 (line 6) 24709* .module fp=NN directive, MIPS: MIPS FP ABI Selection. 24710 (line 6) 24711* .movsp directive, ARM: ARM Directives. (line 167) 24712* .nan directive, MIPS: MIPS NaN Encodings. (line 6) 24713* .nocmp directive, TIC6X: TIC6X Directives. (line 47) 24714* .no_pointers directive, XStormy16: XStormy16 Directives. 24715 (line 14) 24716* .o: Object. (line 6) 24717* .object_arch directive, ARM: ARM Directives. (line 172) 24718* .packed directive, ARM: ARM Directives. (line 178) 24719* .pad directive, ARM: ARM Directives. (line 183) 24720* .param on HPPA: HPPA Directives. (line 19) 24721* .personality directive, ARM: ARM Directives. (line 188) 24722* .personality directive, TIC6X: TIC6X Directives. (line 55) 24723* .personalityindex directive, ARM: ARM Directives. (line 191) 24724* .personalityindex directive, TIC6X: TIC6X Directives. (line 51) 24725* .pool directive, AArch64: AArch64 Directives. (line 53) 24726* .pool directive, ARM: ARM Directives. (line 195) 24727* .quad directive, s390: s390 Directives. (line 16) 24728* .req directive, AArch64: AArch64 Directives. (line 56) 24729* .req directive, ARM: ARM Directives. (line 198) 24730* .require_canonical_reg_names directive, TILE-Gx: TILE-Gx Directives. 24731 (line 19) 24732* .require_canonical_reg_names directive, TILEPro: TILEPro Directives. 24733 (line 19) 24734* .save directive, ARM: ARM Directives. (line 203) 24735* .scomm directive, TIC6X: TIC6X Directives. (line 58) 24736* .secrel32 directive, ARM: ARM Directives. (line 241) 24737* .set arch=CPU: MIPS ISA. (line 18) 24738* .set at: MIPS Macros. (line 41) 24739* .set at=REG: MIPS Macros. (line 35) 24740* .set autoextend: MIPS autoextend. (line 6) 24741* .set doublefloat: MIPS Floating-Point. 24742 (line 12) 24743* .set dsp: MIPS ASE Instruction Generation Overrides. 24744 (line 21) 24745* .set dspr2: MIPS ASE Instruction Generation Overrides. 24746 (line 26) 24747* .set dspr3: MIPS ASE Instruction Generation Overrides. 24748 (line 31) 24749* .set hardfloat: MIPS Floating-Point. 24750 (line 6) 24751* .set insn32: MIPS assembly options. 24752 (line 18) 24753* .set macro: MIPS Macros. (line 30) 24754* .set mcu: MIPS ASE Instruction Generation Overrides. 24755 (line 42) 24756* .set mdmx: MIPS ASE Instruction Generation Overrides. 24757 (line 16) 24758* .set mips3d: MIPS ASE Instruction Generation Overrides. 24759 (line 6) 24760* .set mipsN: MIPS ISA. (line 6) 24761* .set msa: MIPS ASE Instruction Generation Overrides. 24762 (line 47) 24763* .set mt: MIPS ASE Instruction Generation Overrides. 24764 (line 37) 24765* .set noat: MIPS Macros. (line 41) 24766* .set noautoextend: MIPS autoextend. (line 6) 24767* .set nodsp: MIPS ASE Instruction Generation Overrides. 24768 (line 21) 24769* .set nodspr2: MIPS ASE Instruction Generation Overrides. 24770 (line 26) 24771* .set nodspr3: MIPS ASE Instruction Generation Overrides. 24772 (line 31) 24773* .set noinsn32: MIPS assembly options. 24774 (line 18) 24775* .set nomacro: MIPS Macros. (line 30) 24776* .set nomcu: MIPS ASE Instruction Generation Overrides. 24777 (line 42) 24778* .set nomdmx: MIPS ASE Instruction Generation Overrides. 24779 (line 16) 24780* .set nomips3d: MIPS ASE Instruction Generation Overrides. 24781 (line 6) 24782* .set nomsa: MIPS ASE Instruction Generation Overrides. 24783 (line 47) 24784* .set nomt: MIPS ASE Instruction Generation Overrides. 24785 (line 37) 24786* .set nosmartmips: MIPS ASE Instruction Generation Overrides. 24787 (line 11) 24788* .set nosym32: MIPS Symbol Sizes. (line 6) 24789* .set novirt: MIPS ASE Instruction Generation Overrides. 24790 (line 52) 24791* .set noxpa: MIPS ASE Instruction Generation Overrides. 24792 (line 57) 24793* .set pop: MIPS Option Stack. (line 6) 24794* .set push: MIPS Option Stack. (line 6) 24795* .set singlefloat: MIPS Floating-Point. 24796 (line 12) 24797* .set smartmips: MIPS ASE Instruction Generation Overrides. 24798 (line 11) 24799* .set softfloat: MIPS Floating-Point. 24800 (line 6) 24801* .set sym32: MIPS Symbol Sizes. (line 6) 24802* .set virt: MIPS ASE Instruction Generation Overrides. 24803 (line 52) 24804* .set xpa: MIPS ASE Instruction Generation Overrides. 24805 (line 57) 24806* .setfp directive, ARM: ARM Directives. (line 227) 24807* .short directive, s390: s390 Directives. (line 16) 24808* .syntax directive, ARM: ARM Directives. (line 246) 24809* .thumb directive, ARM: ARM Directives. (line 250) 24810* .thumb_func directive, ARM: ARM Directives. (line 253) 24811* .thumb_set directive, ARM: ARM Directives. (line 264) 24812* .tlsdescadd directive, AArch64: AArch64 Directives. (line 61) 24813* .tlsdesccall directive, AArch64: AArch64 Directives. (line 64) 24814* .tlsdescldr directive, AArch64: AArch64 Directives. (line 67) 24815* .tlsdescseq directive, ARM: ARM Directives. (line 271) 24816* .unreq directive, AArch64: AArch64 Directives. (line 70) 24817* .unreq directive, ARM: ARM Directives. (line 276) 24818* .unwind_raw directive, ARM: ARM Directives. (line 287) 24819* .v850 directive, V850: V850 Directives. (line 14) 24820* .v850e directive, V850: V850 Directives. (line 20) 24821* .v850e1 directive, V850: V850 Directives. (line 26) 24822* .v850e2 directive, V850: V850 Directives. (line 32) 24823* .v850e2v3 directive, V850: V850 Directives. (line 38) 24824* .v850e2v4 directive, V850: V850 Directives. (line 44) 24825* .v850e3v5 directive, V850: V850 Directives. (line 50) 24826* .vsave directive, ARM: ARM Directives. (line 294) 24827* .xword directive, AArch64: AArch64 Directives. (line 81) 24828* .z8001: Z8000 Directives. (line 11) 24829* .z8002: Z8000 Directives. (line 15) 24830* 16-bit code, i386: i386-16bit. (line 6) 24831* 16bit_pointers directive, XStormy16: XStormy16 Directives. 24832 (line 6) 24833* 16byte directive, Nios II: Nios II Directives. (line 28) 24834* 2byte directive, Nios II: Nios II Directives. (line 19) 24835* 32bit_pointers directive, XStormy16: XStormy16 Directives. 24836 (line 10) 24837* 3DNow!, i386: i386-SIMD. (line 6) 24838* 3DNow!, x86-64: i386-SIMD. (line 6) 24839* 430 support: MSP430-Dependent. (line 6) 24840* 4byte directive, Nios II: Nios II Directives. (line 22) 24841* 8byte directive, Nios II: Nios II Directives. (line 25) 24842* : (label): Statements. (line 31) 24843* @gotoff(SYMBOL), ARC modifier: ARC Modifiers. (line 20) 24844* @gotpc(SYMBOL), ARC modifier: ARC Modifiers. (line 16) 24845* @hi pseudo-op, XStormy16: XStormy16 Opcodes. (line 21) 24846* @lo pseudo-op, XStormy16: XStormy16 Opcodes. (line 10) 24847* @pcl(SYMBOL), ARC modifier: ARC Modifiers. (line 12) 24848* @plt(SYMBOL), ARC modifier: ARC Modifiers. (line 23) 24849* @sda(SYMBOL), ARC modifier: ARC Modifiers. (line 28) 24850* @word modifier, D10V: D10V-Word. (line 6) 24851* _ opcode prefix: Xtensa Opcodes. (line 9) 24852* __DYNAMIC__, ARC pre-defined symbol: ARC Symbols. (line 14) 24853* __GLOBAL_OFFSET_TABLE__, ARC pre-defined symbol: ARC Symbols. 24854 (line 11) 24855* a.out: Object. (line 6) 24856* a.out symbol attributes: a.out Symbols. (line 6) 24857* AArch64 floating point (IEEE): AArch64 Floating Point. 24858 (line 6) 24859* AArch64 immediate character: AArch64-Chars. (line 13) 24860* AArch64 line comment character: AArch64-Chars. (line 6) 24861* AArch64 line separator: AArch64-Chars. (line 10) 24862* AArch64 machine directives: AArch64 Directives. (line 6) 24863* AArch64 opcodes: AArch64 Opcodes. (line 6) 24864* AArch64 options (none): AArch64 Options. (line 6) 24865* AArch64 register names: AArch64-Regs. (line 6) 24866* AArch64 relocations: AArch64-Relocations. 24867 (line 6) 24868* AArch64 support: AArch64-Dependent. (line 6) 24869* ABI options, SH64: SH64 Options. (line 25) 24870* abort directive: Abort. (line 6) 24871* ABORT directive: ABORT (COFF). (line 6) 24872* absolute section: Ld Sections. (line 29) 24873* absolute-literals directive: Absolute Literals Directive. 24874 (line 6) 24875* ADDI instructions, relaxation: Xtensa Immediate Relaxation. 24876 (line 43) 24877* addition, permitted arguments: Infix Ops. (line 45) 24878* addresses: Expressions. (line 6) 24879* addresses, format of: Secs Background. (line 65) 24880* addressing modes, D10V: D10V-Addressing. (line 6) 24881* addressing modes, D30V: D30V-Addressing. (line 6) 24882* addressing modes, H8/300: H8/300-Addressing. (line 6) 24883* addressing modes, M680x0: M68K-Syntax. (line 21) 24884* addressing modes, M68HC11: M68HC11-Syntax. (line 29) 24885* addressing modes, SH: SH-Addressing. (line 6) 24886* addressing modes, SH64: SH64-Addressing. (line 6) 24887* addressing modes, XGATE: XGATE-Syntax. (line 28) 24888* addressing modes, Z8000: Z8000-Addressing. (line 6) 24889* ADR reg,<label> pseudo op, ARM: ARM Opcodes. (line 25) 24890* ADRL reg,<label> pseudo op, ARM: ARM Opcodes. (line 35) 24891* ADRP, ADD, LDR/STR group relocations, AArch64: AArch64-Relocations. 24892 (line 14) 24893* advancing location counter: Org. (line 6) 24894* align directive: Align. (line 6) 24895* align directive, Nios II: Nios II Directives. (line 6) 24896* align directive, SPARC: Sparc-Directives. (line 9) 24897* align directive, TIC54X: TIC54X-Directives. (line 6) 24898* aligned instruction bundle: Bundle directives. (line 9) 24899* alignment for NEON instructions: ARM-Neon-Alignment. (line 6) 24900* alignment of branch targets: Xtensa Automatic Alignment. 24901 (line 6) 24902* alignment of LOOP instructions: Xtensa Automatic Alignment. 24903 (line 6) 24904* Alpha floating point (IEEE): Alpha Floating Point. 24905 (line 6) 24906* Alpha line comment character: Alpha-Chars. (line 6) 24907* Alpha line separator: Alpha-Chars. (line 11) 24908* Alpha notes: Alpha Notes. (line 6) 24909* Alpha options: Alpha Options. (line 6) 24910* Alpha registers: Alpha-Regs. (line 6) 24911* Alpha relocations: Alpha-Relocs. (line 6) 24912* Alpha support: Alpha-Dependent. (line 6) 24913* Alpha Syntax: Alpha Options. (line 60) 24914* Alpha-only directives: Alpha Directives. (line 9) 24915* Altera Nios II support: NiosII-Dependent. (line 6) 24916* altered difference tables: Word. (line 12) 24917* alternate syntax for the 680x0: M68K-Moto-Syntax. (line 6) 24918* ARC Branch Target Address: ARC-Regs. (line 60) 24919* ARC BTA saved on exception entry: ARC-Regs. (line 79) 24920* ARC Build configuration for: BTA Registers: ARC-Regs. (line 89) 24921* ARC Build configuration for: Core Registers: ARC-Regs. (line 97) 24922* ARC Build configuration for: Interrupts: ARC-Regs. (line 93) 24923* ARC Build Configuration Registers Version: ARC-Regs. (line 85) 24924* ARC C preprocessor macro separator: ARC-Chars. (line 31) 24925* ARC core general registers: ARC-Regs. (line 10) 24926* ARC DCCM RAM Configuration Register: ARC-Regs. (line 101) 24927* ARC Exception Cause Register: ARC-Regs. (line 63) 24928* ARC Exception Return Address: ARC-Regs. (line 76) 24929* ARC extension core registers: ARC-Regs. (line 38) 24930* ARC frame pointer: ARC-Regs. (line 17) 24931* ARC global pointer: ARC-Regs. (line 14) 24932* ARC interrupt link register: ARC-Regs. (line 27) 24933* ARC Interrupt Vector Base address: ARC-Regs. (line 66) 24934* ARC level 1 interrupt link register: ARC-Regs. (line 23) 24935* ARC level 2 interrupt link register: ARC-Regs. (line 31) 24936* ARC line comment character: ARC-Chars. (line 11) 24937* ARC line separator: ARC-Chars. (line 27) 24938* ARC link register: ARC-Regs. (line 35) 24939* ARC loop counter: ARC-Regs. (line 41) 24940* ARC machine directives: ARC Directives. (line 6) 24941* ARC opcodes: ARC Opcodes. (line 6) 24942* ARC options: ARC Options. (line 6) 24943* ARC Processor Identification register: ARC-Regs. (line 51) 24944* ARC Program Counter: ARC-Regs. (line 54) 24945* ARC register name prefix character: ARC-Chars. (line 7) 24946* ARC register names: ARC-Regs. (line 6) 24947* ARC Saved User Stack Pointer: ARC-Regs. (line 73) 24948* ARC stack pointer: ARC-Regs. (line 20) 24949* ARC Status register: ARC-Regs. (line 57) 24950* ARC STATUS32 saved on exception: ARC-Regs. (line 82) 24951* ARC Stored STATUS32 register on entry to level P0 interrupts: ARC-Regs. 24952 (line 69) 24953* ARC support: ARC-Dependent. (line 6) 24954* ARC symbol prefix character: ARC-Chars. (line 20) 24955* ARC word aligned program counter: ARC-Regs. (line 44) 24956* arch directive, i386: i386-Arch. (line 6) 24957* arch directive, M680x0: M68K-Directives. (line 22) 24958* arch directive, MSP 430: MSP430 Directives. (line 18) 24959* arch directive, x86-64: i386-Arch. (line 6) 24960* architecture options, i960: Options-i960. (line 6) 24961* architecture options, IP2022: IP2K-Opts. (line 9) 24962* architecture options, IP2K: IP2K-Opts. (line 14) 24963* architecture options, M16C: M32C-Opts. (line 12) 24964* architecture options, M32C: M32C-Opts. (line 9) 24965* architecture options, M32R: M32R-Opts. (line 21) 24966* architecture options, M32R2: M32R-Opts. (line 17) 24967* architecture options, M32RX: M32R-Opts. (line 9) 24968* architecture options, M680x0: M68K-Opts. (line 99) 24969* Architecture variant option, CRIS: CRIS-Opts. (line 34) 24970* architectures, Meta: Meta Options. (line 6) 24971* architectures, PowerPC: PowerPC-Opts. (line 6) 24972* architectures, SCORE: SCORE-Opts. (line 6) 24973* architectures, SPARC: Sparc-Opts. (line 6) 24974* arguments for addition: Infix Ops. (line 45) 24975* arguments for subtraction: Infix Ops. (line 50) 24976* arguments in expressions: Arguments. (line 6) 24977* arithmetic functions: Operators. (line 6) 24978* arithmetic operands: Arguments. (line 6) 24979* ARM data relocations: ARM-Relocations. (line 6) 24980* ARM floating point (IEEE): ARM Floating Point. (line 6) 24981* ARM identifiers: ARM-Chars. (line 19) 24982* ARM immediate character: ARM-Chars. (line 17) 24983* ARM line comment character: ARM-Chars. (line 6) 24984* ARM line separator: ARM-Chars. (line 14) 24985* ARM machine directives: ARM Directives. (line 6) 24986* ARM opcodes: ARM Opcodes. (line 6) 24987* ARM options (none): ARM Options. (line 6) 24988* ARM register names: ARM-Regs. (line 6) 24989* ARM support: ARM-Dependent. (line 6) 24990* ascii directive: Ascii. (line 6) 24991* asciz directive: Asciz. (line 6) 24992* asg directive, TIC54X: TIC54X-Directives. (line 18) 24993* assembler bugs, reporting: Bug Reporting. (line 6) 24994* assembler crash: Bug Criteria. (line 9) 24995* assembler directive .3byte, RX: RX-Directives. (line 9) 24996* assembler directive .arch, CRIS: CRIS-Pseudos. (line 50) 24997* assembler directive .dword, CRIS: CRIS-Pseudos. (line 12) 24998* assembler directive .far, M68HC11: M68HC11-Directives. (line 20) 24999* assembler directive .fetchalign, RX: RX-Directives. (line 13) 25000* assembler directive .interrupt, M68HC11: M68HC11-Directives. 25001 (line 26) 25002* assembler directive .mode, M68HC11: M68HC11-Directives. (line 16) 25003* assembler directive .relax, M68HC11: M68HC11-Directives. (line 10) 25004* assembler directive .syntax, CRIS: CRIS-Pseudos. (line 18) 25005* assembler directive .xrefb, M68HC11: M68HC11-Directives. (line 31) 25006* assembler directive BSPEC, MMIX: MMIX-Pseudos. (line 137) 25007* assembler directive BYTE, MMIX: MMIX-Pseudos. (line 101) 25008* assembler directive ESPEC, MMIX: MMIX-Pseudos. (line 137) 25009* assembler directive GREG, MMIX: MMIX-Pseudos. (line 53) 25010* assembler directive IS, MMIX: MMIX-Pseudos. (line 44) 25011* assembler directive LOC, MMIX: MMIX-Pseudos. (line 7) 25012* assembler directive LOCAL, MMIX: MMIX-Pseudos. (line 29) 25013* assembler directive OCTA, MMIX: MMIX-Pseudos. (line 113) 25014* assembler directive PREFIX, MMIX: MMIX-Pseudos. (line 125) 25015* assembler directive TETRA, MMIX: MMIX-Pseudos. (line 113) 25016* assembler directive WYDE, MMIX: MMIX-Pseudos. (line 113) 25017* assembler directives, CRIS: CRIS-Pseudos. (line 6) 25018* assembler directives, M68HC11: M68HC11-Directives. (line 6) 25019* assembler directives, M68HC12: M68HC11-Directives. (line 6) 25020* assembler directives, MMIX: MMIX-Pseudos. (line 6) 25021* assembler directives, RL78: RL78-Directives. (line 6) 25022* assembler directives, RX: RX-Directives. (line 6) 25023* assembler directives, XGATE: XGATE-Directives. (line 6) 25024* assembler internal logic error: As Sections. (line 13) 25025* assembler version: v. (line 6) 25026* assembler, and linker: Secs Background. (line 10) 25027* assembly listings, enabling: a. (line 6) 25028* assigning values to symbols: Setting Symbols. (line 6) 25029* assigning values to symbols <1>: Equ. (line 6) 25030* at register, MIPS: MIPS Macros. (line 35) 25031* atmp directive, i860: Directives-i860. (line 16) 25032* attributes, symbol: Symbol Attributes. (line 6) 25033* att_syntax pseudo op, i386: i386-Variations. (line 6) 25034* att_syntax pseudo op, x86-64: i386-Variations. (line 6) 25035* auxiliary attributes, COFF symbols: COFF Symbols. (line 19) 25036* auxiliary symbol information, COFF: Dim. (line 6) 25037* AVR line comment character: AVR-Chars. (line 6) 25038* AVR line separator: AVR-Chars. (line 14) 25039* AVR modifiers: AVR-Modifiers. (line 6) 25040* AVR opcode summary: AVR Opcodes. (line 6) 25041* AVR options (none): AVR Options. (line 6) 25042* AVR register names: AVR-Regs. (line 6) 25043* AVR support: AVR-Dependent. (line 6) 25044* A_DIR environment variable, TIC54X: TIC54X-Env. (line 6) 25045* backslash (\\): Strings. (line 40) 25046* backspace (\b): Strings. (line 15) 25047* balign directive: Balign. (line 6) 25048* balignl directive: Balign. (line 27) 25049* balignw directive: Balign. (line 27) 25050* bes directive, TIC54X: TIC54X-Directives. (line 194) 25051* big endian output, MIPS: Overview. (line 806) 25052* big endian output, PJ: Overview. (line 713) 25053* big-endian output, MIPS: MIPS Options. (line 13) 25054* big-endian output, TIC6X: TIC6X Options. (line 46) 25055* bignums: Bignums. (line 6) 25056* binary constants, TIC54X: TIC54X-Constants. (line 8) 25057* binary files, including: Incbin. (line 6) 25058* binary integers: Integers. (line 6) 25059* bit names, IA-64: IA-64-Bits. (line 6) 25060* bitfields, not supported on VAX: VAX-no. (line 6) 25061* Blackfin directives: Blackfin Directives. 25062 (line 6) 25063* Blackfin options (none): Blackfin Options. (line 6) 25064* Blackfin support: Blackfin-Dependent. (line 6) 25065* Blackfin syntax: Blackfin Syntax. (line 6) 25066* block: Z8000 Directives. (line 55) 25067* BMI, i386: i386-BMI. (line 6) 25068* BMI, x86-64: i386-BMI. (line 6) 25069* branch improvement, M680x0: M68K-Branch. (line 6) 25070* branch improvement, M68HC11: M68HC11-Branch. (line 6) 25071* branch improvement, VAX: VAX-branch. (line 6) 25072* branch instructions, relaxation: Xtensa Branch Relaxation. 25073 (line 6) 25074* branch recording, i960: Options-i960. (line 22) 25075* branch statistics table, i960: Options-i960. (line 40) 25076* Branch Target Address, ARC: ARC-Regs. (line 60) 25077* branch target alignment: Xtensa Automatic Alignment. 25078 (line 6) 25079* break directive, TIC54X: TIC54X-Directives. (line 141) 25080* BSD syntax: PDP-11-Syntax. (line 6) 25081* bss directive, i960: Directives-i960. (line 6) 25082* bss directive, TIC54X: TIC54X-Directives. (line 27) 25083* bss section: Ld Sections. (line 20) 25084* bss section <1>: bss. (line 6) 25085* BTA saved on exception entry, ARC: ARC-Regs. (line 79) 25086* bug criteria: Bug Criteria. (line 6) 25087* bug reports: Bug Reporting. (line 6) 25088* bugs in assembler: Reporting Bugs. (line 6) 25089* Build configuration for: BTA Registers, ARC: ARC-Regs. (line 89) 25090* Build configuration for: Core Registers, ARC: ARC-Regs. (line 97) 25091* Build configuration for: Interrupts, ARC: ARC-Regs. (line 93) 25092* Build Configuration Registers Version, ARC: ARC-Regs. (line 85) 25093* Built-in symbols, CRIS: CRIS-Symbols. (line 6) 25094* builtin math functions, TIC54X: TIC54X-Builtins. (line 6) 25095* builtin subsym functions, TIC54X: TIC54X-Macros. (line 16) 25096* bundle: Bundle directives. (line 9) 25097* bundle-locked: Bundle directives. (line 39) 25098* bundle_align_mode directive: Bundle directives. (line 9) 25099* bundle_lock directive: Bundle directives. (line 31) 25100* bundle_unlock directive: Bundle directives. (line 31) 25101* bus lock prefixes, i386: i386-Prefixes. (line 36) 25102* bval: Z8000 Directives. (line 30) 25103* byte directive: Byte. (line 6) 25104* byte directive, TIC54X: TIC54X-Directives. (line 34) 25105* C preprocessor macro separator, ARC: ARC-Chars. (line 31) 25106* C54XDSP_DIR environment variable, TIC54X: TIC54X-Env. (line 6) 25107* call directive, Nios II: Nios II Relocations. 25108 (line 38) 25109* call instructions, i386: i386-Mnemonics. (line 58) 25110* call instructions, relaxation: Xtensa Call Relaxation. 25111 (line 6) 25112* call instructions, x86-64: i386-Mnemonics. (line 58) 25113* callj, i960 pseudo-opcode: callj-i960. (line 6) 25114* call_hiadj directive, Nios II: Nios II Relocations. 25115 (line 38) 25116* call_lo directive, Nios II: Nios II Relocations. 25117 (line 38) 25118* carriage return (backslash-r): Strings. (line 24) 25119* case sensitivity, Z80: Z80-Case. (line 6) 25120* cfi_endproc directive: CFI directives. (line 40) 25121* cfi_fde_data directive: CFI directives. (line 66) 25122* cfi_personality directive: CFI directives. (line 47) 25123* cfi_personality_id directive: CFI directives. (line 59) 25124* cfi_sections directive: CFI directives. (line 9) 25125* cfi_startproc directive: CFI directives. (line 30) 25126* char directive, TIC54X: TIC54X-Directives. (line 34) 25127* character constant, Z80: Z80-Chars. (line 20) 25128* character constants: Characters. (line 6) 25129* character escape codes: Strings. (line 15) 25130* character escapes, Z80: Z80-Chars. (line 18) 25131* character, single: Chars. (line 6) 25132* characters used in symbols: Symbol Intro. (line 6) 25133* clink directive, TIC54X: TIC54X-Directives. (line 43) 25134* code16 directive, i386: i386-16bit. (line 6) 25135* code16gcc directive, i386: i386-16bit. (line 6) 25136* code32 directive, i386: i386-16bit. (line 6) 25137* code64 directive, i386: i386-16bit. (line 6) 25138* code64 directive, x86-64: i386-16bit. (line 6) 25139* COFF auxiliary symbol information: Dim. (line 6) 25140* COFF structure debugging: Tag. (line 6) 25141* COFF symbol attributes: COFF Symbols. (line 6) 25142* COFF symbol descriptor: Desc. (line 6) 25143* COFF symbol storage class: Scl. (line 6) 25144* COFF symbol type: Type. (line 11) 25145* COFF symbols, debugging: Def. (line 6) 25146* COFF value attribute: Val. (line 6) 25147* COMDAT: Linkonce. (line 6) 25148* comm directive: Comm. (line 6) 25149* command line conventions: Command Line. (line 6) 25150* command line options, V850: V850 Options. (line 9) 25151* command-line options ignored, VAX: VAX-Opts. (line 6) 25152* comment character, XStormy16: XStormy16-Chars. (line 11) 25153* comments: Comments. (line 6) 25154* comments, M680x0: M68K-Chars. (line 6) 25155* comments, removed by preprocessor: Preprocessing. (line 11) 25156* common directive, SPARC: Sparc-Directives. (line 12) 25157* common sections: Linkonce. (line 6) 25158* common variable storage: bss. (line 6) 25159* compare and jump expansions, i960: Compare-and-branch-i960. 25160 (line 13) 25161* compare/branch instructions, i960: Compare-and-branch-i960. 25162 (line 6) 25163* comparison expressions: Infix Ops. (line 56) 25164* conditional assembly: If. (line 6) 25165* constant, single character: Chars. (line 6) 25166* constants: Constants. (line 6) 25167* constants, bignum: Bignums. (line 6) 25168* constants, character: Characters. (line 6) 25169* constants, converted by preprocessor: Preprocessing. (line 14) 25170* constants, floating point: Flonums. (line 6) 25171* constants, integer: Integers. (line 6) 25172* constants, number: Numbers. (line 6) 25173* constants, Sparc: Sparc-Constants. (line 6) 25174* constants, string: Strings. (line 6) 25175* constants, TIC54X: TIC54X-Constants. (line 6) 25176* conversion instructions, i386: i386-Mnemonics. (line 39) 25177* conversion instructions, x86-64: i386-Mnemonics. (line 39) 25178* coprocessor wait, i386: i386-Prefixes. (line 40) 25179* copy directive, TIC54X: TIC54X-Directives. (line 52) 25180* core general registers, ARC: ARC-Regs. (line 10) 25181* cpu directive, ARC: ARC Directives. (line 27) 25182* cpu directive, M680x0: M68K-Directives. (line 30) 25183* cpu directive, MSP 430: MSP430 Directives. (line 22) 25184* CR16 line comment character: CR16-Chars. (line 6) 25185* CR16 line separator: CR16-Chars. (line 12) 25186* CR16 Operand Qualifiers: CR16 Operand Qualifiers. 25187 (line 6) 25188* CR16 support: CR16-Dependent. (line 6) 25189* crash of assembler: Bug Criteria. (line 9) 25190* CRIS --emulation=crisaout command line option: CRIS-Opts. (line 9) 25191* CRIS --emulation=criself command line option: CRIS-Opts. (line 9) 25192* CRIS --march=ARCHITECTURE command line option: CRIS-Opts. (line 34) 25193* CRIS --mul-bug-abort command line option: CRIS-Opts. (line 63) 25194* CRIS --no-mul-bug-abort command line option: CRIS-Opts. (line 63) 25195* CRIS --no-underscore command line option: CRIS-Opts. (line 15) 25196* CRIS --pic command line option: CRIS-Opts. (line 27) 25197* CRIS --underscore command line option: CRIS-Opts. (line 15) 25198* CRIS -N command line option: CRIS-Opts. (line 59) 25199* CRIS architecture variant option: CRIS-Opts. (line 34) 25200* CRIS assembler directive .arch: CRIS-Pseudos. (line 50) 25201* CRIS assembler directive .dword: CRIS-Pseudos. (line 12) 25202* CRIS assembler directive .syntax: CRIS-Pseudos. (line 18) 25203* CRIS assembler directives: CRIS-Pseudos. (line 6) 25204* CRIS built-in symbols: CRIS-Symbols. (line 6) 25205* CRIS instruction expansion: CRIS-Expand. (line 6) 25206* CRIS line comment characters: CRIS-Chars. (line 6) 25207* CRIS options: CRIS-Opts. (line 6) 25208* CRIS position-independent code: CRIS-Opts. (line 27) 25209* CRIS pseudo-op .arch: CRIS-Pseudos. (line 50) 25210* CRIS pseudo-op .dword: CRIS-Pseudos. (line 12) 25211* CRIS pseudo-op .syntax: CRIS-Pseudos. (line 18) 25212* CRIS pseudo-ops: CRIS-Pseudos. (line 6) 25213* CRIS register names: CRIS-Regs. (line 6) 25214* CRIS support: CRIS-Dependent. (line 6) 25215* CRIS symbols in position-independent code: CRIS-Pic. (line 6) 25216* ctbp register, V850: V850-Regs. (line 90) 25217* ctoff pseudo-op, V850: V850 Opcodes. (line 110) 25218* ctpc register, V850: V850-Regs. (line 82) 25219* ctpsw register, V850: V850-Regs. (line 84) 25220* current address: Dot. (line 6) 25221* current address, advancing: Org. (line 6) 25222* c_mode directive, TIC54X: TIC54X-Directives. (line 49) 25223* D10V @word modifier: D10V-Word. (line 6) 25224* D10V addressing modes: D10V-Addressing. (line 6) 25225* D10V floating point: D10V-Float. (line 6) 25226* D10V line comment character: D10V-Chars. (line 6) 25227* D10V opcode summary: D10V-Opcodes. (line 6) 25228* D10V optimization: Overview. (line 579) 25229* D10V options: D10V-Opts. (line 6) 25230* D10V registers: D10V-Regs. (line 6) 25231* D10V size modifiers: D10V-Size. (line 6) 25232* D10V sub-instruction ordering: D10V-Chars. (line 14) 25233* D10V sub-instructions: D10V-Subs. (line 6) 25234* D10V support: D10V-Dependent. (line 6) 25235* D10V syntax: D10V-Syntax. (line 6) 25236* D30V addressing modes: D30V-Addressing. (line 6) 25237* D30V floating point: D30V-Float. (line 6) 25238* D30V Guarded Execution: D30V-Guarded. (line 6) 25239* D30V line comment character: D30V-Chars. (line 6) 25240* D30V nops: Overview. (line 587) 25241* D30V nops after 32-bit multiply: Overview. (line 590) 25242* D30V opcode summary: D30V-Opcodes. (line 6) 25243* D30V optimization: Overview. (line 584) 25244* D30V options: D30V-Opts. (line 6) 25245* D30V registers: D30V-Regs. (line 6) 25246* D30V size modifiers: D30V-Size. (line 6) 25247* D30V sub-instruction ordering: D30V-Chars. (line 14) 25248* D30V sub-instructions: D30V-Subs. (line 6) 25249* D30V support: D30V-Dependent. (line 6) 25250* D30V syntax: D30V-Syntax. (line 6) 25251* data alignment on SPARC: Sparc-Aligned-Data. (line 6) 25252* data and text sections, joining: R. (line 6) 25253* data directive: Data. (line 6) 25254* data directive, TIC54X: TIC54X-Directives. (line 59) 25255* data relocations, ARM: ARM-Relocations. (line 6) 25256* data section: Ld Sections. (line 9) 25257* data1 directive, M680x0: M68K-Directives. (line 9) 25258* data2 directive, M680x0: M68K-Directives. (line 12) 25259* datalabel, SH64: SH64-Addressing. (line 16) 25260* dbpc register, V850: V850-Regs. (line 86) 25261* dbpsw register, V850: V850-Regs. (line 88) 25262* DCCM RAM Configuration Register, ARC: ARC-Regs. (line 101) 25263* debuggers, and symbol order: Symbols. (line 10) 25264* debugging COFF symbols: Def. (line 6) 25265* DEC syntax: PDP-11-Syntax. (line 6) 25266* decimal integers: Integers. (line 12) 25267* def directive: Def. (line 6) 25268* def directive, TIC54X: TIC54X-Directives. (line 101) 25269* density instructions: Density Instructions. 25270 (line 6) 25271* dependency tracking: MD. (line 6) 25272* deprecated directives: Deprecated. (line 6) 25273* desc directive: Desc. (line 6) 25274* descriptor, of a.out symbol: Symbol Desc. (line 6) 25275* dfloat directive, VAX: VAX-directives. (line 9) 25276* difference tables altered: Word. (line 12) 25277* difference tables, warning: K. (line 6) 25278* differences, mmixal: MMIX-mmixal. (line 6) 25279* dim directive: Dim. (line 6) 25280* directives and instructions: Statements. (line 20) 25281* directives for PowerPC: PowerPC-Pseudo. (line 6) 25282* directives for SCORE: SCORE-Pseudo. (line 6) 25283* directives, Blackfin: Blackfin Directives. 25284 (line 6) 25285* directives, M32R: M32R-Directives. (line 6) 25286* directives, M680x0: M68K-Directives. (line 6) 25287* directives, machine independent: Pseudo Ops. (line 6) 25288* directives, Xtensa: Xtensa Directives. (line 6) 25289* directives, Z8000: Z8000 Directives. (line 6) 25290* Disable floating-point instructions: MIPS Floating-Point. 25291 (line 6) 25292* Disable single-precision floating-point operations: MIPS Floating-Point. 25293 (line 12) 25294* displacement sizing character, VAX: VAX-operands. (line 12) 25295* dollar local symbols: Symbol Names. (line 113) 25296* dot (symbol): Dot. (line 6) 25297* double directive: Double. (line 6) 25298* double directive, i386: i386-Float. (line 14) 25299* double directive, M680x0: M68K-Float. (line 14) 25300* double directive, M68HC11: M68HC11-Float. (line 14) 25301* double directive, RX: RX-Float. (line 11) 25302* double directive, TIC54X: TIC54X-Directives. (line 62) 25303* double directive, VAX: VAX-float. (line 15) 25304* double directive, x86-64: i386-Float. (line 14) 25305* double directive, XGATE: XGATE-Float. (line 13) 25306* doublequote (\"): Strings. (line 43) 25307* drlist directive, TIC54X: TIC54X-Directives. (line 71) 25308* drnolist directive, TIC54X: TIC54X-Directives. (line 71) 25309* dual directive, i860: Directives-i860. (line 6) 25310* dword directive, Nios II: Nios II Directives. (line 16) 25311* EB command line option, Nios II: Nios II Options. (line 22) 25312* ecr register, V850: V850-Regs. (line 78) 25313* eight-byte integer: Quad. (line 9) 25314* eipc register, V850: V850-Regs. (line 70) 25315* eipsw register, V850: V850-Regs. (line 72) 25316* eject directive: Eject. (line 6) 25317* EL command line option, Nios II: Nios II Options. (line 25) 25318* ELF symbol type: Type. (line 22) 25319* else directive: Else. (line 6) 25320* elseif directive: Elseif. (line 6) 25321* empty expressions: Empty Exprs. (line 6) 25322* emsg directive, TIC54X: TIC54X-Directives. (line 75) 25323* emulation: Overview. (line 1007) 25324* encoding options, i386: i386-Mnemonics. (line 34) 25325* encoding options, x86-64: i386-Mnemonics. (line 34) 25326* end directive: End. (line 6) 25327* enddual directive, i860: Directives-i860. (line 11) 25328* endef directive: Endef. (line 6) 25329* endfunc directive: Endfunc. (line 6) 25330* endianness, MIPS: Overview. (line 806) 25331* endianness, PJ: Overview. (line 713) 25332* endif directive: Endif. (line 6) 25333* endloop directive, TIC54X: TIC54X-Directives. (line 141) 25334* endm directive: Macro. (line 137) 25335* endm directive, TIC54X: TIC54X-Directives. (line 151) 25336* endstruct directive, TIC54X: TIC54X-Directives. (line 214) 25337* endunion directive, TIC54X: TIC54X-Directives. (line 248) 25338* environment settings, TIC54X: TIC54X-Env. (line 6) 25339* EOF, newline must precede: Statements. (line 14) 25340* ep register, V850: V850-Regs. (line 66) 25341* Epiphany line comment character: Epiphany-Chars. (line 6) 25342* Epiphany line separator: Epiphany-Chars. (line 14) 25343* Epiphany options: Epiphany Options. (line 6) 25344* Epiphany support: Epiphany-Dependent. (line 6) 25345* equ directive: Equ. (line 6) 25346* equ directive, TIC54X: TIC54X-Directives. (line 189) 25347* equiv directive: Equiv. (line 6) 25348* eqv directive: Eqv. (line 6) 25349* err directive: Err. (line 6) 25350* error directive: Error. (line 6) 25351* error messages: Errors. (line 6) 25352* error on valid input: Bug Criteria. (line 12) 25353* errors, caused by warnings: W. (line 16) 25354* errors, continuing after: Z. (line 6) 25355* ESA/390 floating point (IEEE): ESA/390 Floating Point. 25356 (line 6) 25357* ESA/390 support: ESA/390-Dependent. (line 6) 25358* ESA/390 Syntax: ESA/390 Options. (line 7) 25359* ESA/390-only directives: ESA/390 Directives. (line 12) 25360* escape codes, character: Strings. (line 15) 25361* eval directive, TIC54X: TIC54X-Directives. (line 22) 25362* even: Z8000 Directives. (line 58) 25363* even directive, M680x0: M68K-Directives. (line 15) 25364* even directive, TIC54X: TIC54X-Directives. (line 6) 25365* Exception Cause Register, ARC: ARC-Regs. (line 63) 25366* Exception Return Address, ARC: ARC-Regs. (line 76) 25367* exitm directive: Macro. (line 140) 25368* expr (internal section): As Sections. (line 17) 25369* expression arguments: Arguments. (line 6) 25370* expressions: Expressions. (line 6) 25371* expressions, comparison: Infix Ops. (line 56) 25372* expressions, empty: Empty Exprs. (line 6) 25373* expressions, integer: Integer Exprs. (line 6) 25374* extAuxRegister directive, ARC: ARC Directives. (line 105) 25375* extCondCode directive, ARC: ARC Directives. (line 126) 25376* extCoreRegister directive, ARC: ARC Directives. (line 137) 25377* extend directive M680x0: M68K-Float. (line 17) 25378* extend directive M68HC11: M68HC11-Float. (line 17) 25379* extend directive XGATE: XGATE-Float. (line 16) 25380* extended directive, i960: Directives-i960. (line 13) 25381* extension core registers, ARC: ARC-Regs. (line 38) 25382* extern directive: Extern. (line 6) 25383* extInstruction directive, ARC: ARC Directives. (line 164) 25384* fail directive: Fail. (line 6) 25385* far_mode directive, TIC54X: TIC54X-Directives. (line 80) 25386* faster processing (-f): f. (line 6) 25387* fatal signal: Bug Criteria. (line 9) 25388* fclist directive, TIC54X: TIC54X-Directives. (line 85) 25389* fcnolist directive, TIC54X: TIC54X-Directives. (line 85) 25390* fepc register, V850: V850-Regs. (line 74) 25391* fepsw register, V850: V850-Regs. (line 76) 25392* ffloat directive, VAX: VAX-directives. (line 13) 25393* field directive, TIC54X: TIC54X-Directives. (line 89) 25394* file directive: File. (line 6) 25395* file directive, MSP 430: MSP430 Directives. (line 6) 25396* file name, logical: File. (line 13) 25397* file names and line numbers, in warnings/errors: Errors. (line 16) 25398* files, including: Include. (line 6) 25399* files, input: Input Files. (line 6) 25400* fill directive: Fill. (line 6) 25401* filling memory: Skip. (line 6) 25402* filling memory <1>: Space. (line 6) 25403* filling memory with zero bytes: Zero. (line 6) 25404* FLIX syntax: Xtensa Syntax. (line 6) 25405* float directive: Float. (line 6) 25406* float directive, i386: i386-Float. (line 14) 25407* float directive, M680x0: M68K-Float. (line 11) 25408* float directive, M68HC11: M68HC11-Float. (line 11) 25409* float directive, RX: RX-Float. (line 8) 25410* float directive, TIC54X: TIC54X-Directives. (line 62) 25411* float directive, VAX: VAX-float. (line 15) 25412* float directive, x86-64: i386-Float. (line 14) 25413* float directive, XGATE: XGATE-Float. (line 10) 25414* floating point numbers: Flonums. (line 6) 25415* floating point numbers (double): Double. (line 6) 25416* floating point numbers (single): Float. (line 6) 25417* floating point numbers (single) <1>: Single. (line 6) 25418* floating point, AArch64 (IEEE): AArch64 Floating Point. 25419 (line 6) 25420* floating point, Alpha (IEEE): Alpha Floating Point. 25421 (line 6) 25422* floating point, ARM (IEEE): ARM Floating Point. (line 6) 25423* floating point, D10V: D10V-Float. (line 6) 25424* floating point, D30V: D30V-Float. (line 6) 25425* floating point, ESA/390 (IEEE): ESA/390 Floating Point. 25426 (line 6) 25427* floating point, H8/300 (IEEE): H8/300 Floating Point. 25428 (line 6) 25429* floating point, HPPA (IEEE): HPPA Floating Point. 25430 (line 6) 25431* floating point, i386: i386-Float. (line 6) 25432* floating point, i960 (IEEE): Floating Point-i960. 25433 (line 6) 25434* floating point, M680x0: M68K-Float. (line 6) 25435* floating point, M68HC11: M68HC11-Float. (line 6) 25436* floating point, MSP 430 (IEEE): MSP430 Floating Point. 25437 (line 6) 25438* floating point, RX: RX-Float. (line 6) 25439* floating point, s390: s390 Floating Point. 25440 (line 6) 25441* floating point, SH (IEEE): SH Floating Point. (line 6) 25442* floating point, SPARC (IEEE): Sparc-Float. (line 6) 25443* floating point, V850 (IEEE): V850 Floating Point. 25444 (line 6) 25445* floating point, VAX: VAX-float. (line 6) 25446* floating point, x86-64: i386-Float. (line 6) 25447* floating point, XGATE: XGATE-Float. (line 6) 25448* floating point, Z80: Z80 Floating Point. (line 6) 25449* flonums: Flonums. (line 6) 25450* format of error messages: Errors. (line 38) 25451* format of warning messages: Errors. (line 12) 25452* formfeed (\f): Strings. (line 18) 25453* frame pointer, ARC: ARC-Regs. (line 17) 25454* func directive: Func. (line 6) 25455* functions, in expressions: Operators. (line 6) 25456* gbr960, i960 postprocessor: Options-i960. (line 40) 25457* gfloat directive, VAX: VAX-directives. (line 17) 25458* global: Z8000 Directives. (line 21) 25459* global directive: Global. (line 6) 25460* global directive, TIC54X: TIC54X-Directives. (line 101) 25461* global pointer, ARC: ARC-Regs. (line 14) 25462* got directive, Nios II: Nios II Relocations. 25463 (line 38) 25464* gotoff directive, Nios II: Nios II Relocations. 25465 (line 38) 25466* gotoff_hiadj directive, Nios II: Nios II Relocations. 25467 (line 38) 25468* gotoff_lo directive, Nios II: Nios II Relocations. 25469 (line 38) 25470* got_hiadj directive, Nios II: Nios II Relocations. 25471 (line 38) 25472* got_lo directive, Nios II: Nios II Relocations. 25473 (line 38) 25474* gp register, MIPS: MIPS Small Data. (line 6) 25475* gp register, V850: V850-Regs. (line 14) 25476* gprel directive, Nios II: Nios II Relocations. 25477 (line 26) 25478* grouping data: Sub-Sections. (line 6) 25479* H8/300 addressing modes: H8/300-Addressing. (line 6) 25480* H8/300 floating point (IEEE): H8/300 Floating Point. 25481 (line 6) 25482* H8/300 line comment character: H8/300-Chars. (line 6) 25483* H8/300 line separator: H8/300-Chars. (line 8) 25484* H8/300 machine directives (none): H8/300 Directives. (line 6) 25485* H8/300 opcode summary: H8/300 Opcodes. (line 6) 25486* H8/300 options: H8/300 Options. (line 6) 25487* H8/300 registers: H8/300-Regs. (line 6) 25488* H8/300 size suffixes: H8/300 Opcodes. (line 160) 25489* H8/300 support: H8/300-Dependent. (line 6) 25490* H8/300H, assembling for: H8/300 Directives. (line 8) 25491* half directive, Nios II: Nios II Directives. (line 10) 25492* half directive, SPARC: Sparc-Directives. (line 17) 25493* half directive, TIC54X: TIC54X-Directives. (line 109) 25494* hex character code (\XD...): Strings. (line 36) 25495* hexadecimal integers: Integers. (line 15) 25496* hexadecimal prefix, Z80: Z80-Chars. (line 15) 25497* hfloat directive, VAX: VAX-directives. (line 21) 25498* hi directive, Nios II: Nios II Relocations. 25499 (line 20) 25500* hi pseudo-op, V850: V850 Opcodes. (line 33) 25501* hi0 pseudo-op, V850: V850 Opcodes. (line 10) 25502* hiadj directive, Nios II: Nios II Relocations. 25503 (line 6) 25504* hidden directive: Hidden. (line 6) 25505* high directive, M32R: M32R-Directives. (line 18) 25506* hilo pseudo-op, V850: V850 Opcodes. (line 55) 25507* HPPA directives not supported: HPPA Directives. (line 11) 25508* HPPA floating point (IEEE): HPPA Floating Point. 25509 (line 6) 25510* HPPA Syntax: HPPA Options. (line 7) 25511* HPPA-only directives: HPPA Directives. (line 24) 25512* hword directive: hword. (line 6) 25513* i370 support: ESA/390-Dependent. (line 6) 25514* i386 16-bit code: i386-16bit. (line 6) 25515* i386 arch directive: i386-Arch. (line 6) 25516* i386 att_syntax pseudo op: i386-Variations. (line 6) 25517* i386 conversion instructions: i386-Mnemonics. (line 39) 25518* i386 floating point: i386-Float. (line 6) 25519* i386 immediate operands: i386-Variations. (line 15) 25520* i386 instruction naming: i386-Mnemonics. (line 9) 25521* i386 instruction prefixes: i386-Prefixes. (line 6) 25522* i386 intel_syntax pseudo op: i386-Variations. (line 6) 25523* i386 jump optimization: i386-Jumps. (line 6) 25524* i386 jump, call, return: i386-Variations. (line 40) 25525* i386 jump/call operands: i386-Variations. (line 15) 25526* i386 line comment character: i386-Chars. (line 6) 25527* i386 line separator: i386-Chars. (line 18) 25528* i386 memory references: i386-Memory. (line 6) 25529* i386 mnemonic compatibility: i386-Mnemonics. (line 64) 25530* i386 mul, imul instructions: i386-Notes. (line 6) 25531* i386 options: i386-Options. (line 6) 25532* i386 register operands: i386-Variations. (line 15) 25533* i386 registers: i386-Regs. (line 6) 25534* i386 sections: i386-Variations. (line 46) 25535* i386 size suffixes: i386-Variations. (line 28) 25536* i386 source, destination operands: i386-Variations. (line 21) 25537* i386 support: i386-Dependent. (line 6) 25538* i386 syntax compatibility: i386-Variations. (line 6) 25539* i80386 support: i386-Dependent. (line 6) 25540* i860 line comment character: i860-Chars. (line 6) 25541* i860 line separator: i860-Chars. (line 14) 25542* i860 machine directives: Directives-i860. (line 6) 25543* i860 opcodes: Opcodes for i860. (line 6) 25544* i860 support: i860-Dependent. (line 6) 25545* i960 architecture options: Options-i960. (line 6) 25546* i960 branch recording: Options-i960. (line 22) 25547* i960 callj pseudo-opcode: callj-i960. (line 6) 25548* i960 compare and jump expansions: Compare-and-branch-i960. 25549 (line 13) 25550* i960 compare/branch instructions: Compare-and-branch-i960. 25551 (line 6) 25552* i960 floating point (IEEE): Floating Point-i960. 25553 (line 6) 25554* i960 line comment character: i960-Chars. (line 6) 25555* i960 line separator: i960-Chars. (line 14) 25556* i960 machine directives: Directives-i960. (line 6) 25557* i960 opcodes: Opcodes for i960. (line 6) 25558* i960 options: Options-i960. (line 6) 25559* i960 support: i960-Dependent. (line 6) 25560* IA-64 line comment character: IA-64-Chars. (line 6) 25561* IA-64 line separator: IA-64-Chars. (line 8) 25562* IA-64 options: IA-64 Options. (line 6) 25563* IA-64 Processor-status-Register bit names: IA-64-Bits. (line 6) 25564* IA-64 registers: IA-64-Regs. (line 6) 25565* IA-64 relocations: IA-64-Relocs. (line 6) 25566* IA-64 support: IA-64-Dependent. (line 6) 25567* IA-64 Syntax: IA-64 Options. (line 85) 25568* ident directive: Ident. (line 6) 25569* identifiers, ARM: ARM-Chars. (line 19) 25570* identifiers, MSP 430: MSP430-Chars. (line 17) 25571* if directive: If. (line 6) 25572* ifb directive: If. (line 21) 25573* ifc directive: If. (line 25) 25574* ifdef directive: If. (line 16) 25575* ifeq directive: If. (line 33) 25576* ifeqs directive: If. (line 36) 25577* ifge directive: If. (line 40) 25578* ifgt directive: If. (line 44) 25579* ifle directive: If. (line 48) 25580* iflt directive: If. (line 52) 25581* ifnb directive: If. (line 56) 25582* ifnc directive: If. (line 61) 25583* ifndef directive: If. (line 65) 25584* ifne directive: If. (line 72) 25585* ifnes directive: If. (line 76) 25586* ifnotdef directive: If. (line 65) 25587* immediate character, AArch64: AArch64-Chars. (line 13) 25588* immediate character, ARM: ARM-Chars. (line 17) 25589* immediate character, M680x0: M68K-Chars. (line 13) 25590* immediate character, VAX: VAX-operands. (line 6) 25591* immediate fields, relaxation: Xtensa Immediate Relaxation. 25592 (line 6) 25593* immediate operands, i386: i386-Variations. (line 15) 25594* immediate operands, x86-64: i386-Variations. (line 15) 25595* imul instruction, i386: i386-Notes. (line 6) 25596* imul instruction, x86-64: i386-Notes. (line 6) 25597* incbin directive: Incbin. (line 6) 25598* include directive: Include. (line 6) 25599* include directive search path: I. (line 6) 25600* indirect character, VAX: VAX-operands. (line 9) 25601* infix operators: Infix Ops. (line 6) 25602* inhibiting interrupts, i386: i386-Prefixes. (line 36) 25603* input: Input Files. (line 6) 25604* input file linenumbers: Input Files. (line 35) 25605* instruction aliases, s390: s390 Aliases. (line 6) 25606* instruction bundle: Bundle directives. (line 9) 25607* instruction expansion, CRIS: CRIS-Expand. (line 6) 25608* instruction expansion, MMIX: MMIX-Expand. (line 6) 25609* instruction formats, s390: s390 Formats. (line 6) 25610* instruction marker, s390: s390 Instruction Marker. 25611 (line 6) 25612* instruction mnemonics, s390: s390 Mnemonics. (line 6) 25613* instruction naming, i386: i386-Mnemonics. (line 9) 25614* instruction naming, x86-64: i386-Mnemonics. (line 9) 25615* instruction operand modifier, s390: s390 Operand Modifier. 25616 (line 6) 25617* instruction operands, s390: s390 Operands. (line 6) 25618* instruction prefixes, i386: i386-Prefixes. (line 6) 25619* instruction set, M680x0: M68K-opcodes. (line 6) 25620* instruction set, M68HC11: M68HC11-opcodes. (line 6) 25621* instruction set, XGATE: XGATE-opcodes. (line 5) 25622* instruction summary, AVR: AVR Opcodes. (line 6) 25623* instruction summary, D10V: D10V-Opcodes. (line 6) 25624* instruction summary, D30V: D30V-Opcodes. (line 6) 25625* instruction summary, H8/300: H8/300 Opcodes. (line 6) 25626* instruction summary, LM32: LM32 Opcodes. (line 6) 25627* instruction summary, SH: SH Opcodes. (line 6) 25628* instruction summary, SH64: SH64 Opcodes. (line 6) 25629* instruction summary, Z8000: Z8000 Opcodes. (line 6) 25630* instruction syntax, s390: s390 Syntax. (line 6) 25631* instructions and directives: Statements. (line 20) 25632* int directive: Int. (line 6) 25633* int directive, H8/300: H8/300 Directives. (line 6) 25634* int directive, i386: i386-Float. (line 21) 25635* int directive, TIC54X: TIC54X-Directives. (line 109) 25636* int directive, x86-64: i386-Float. (line 21) 25637* integer expressions: Integer Exprs. (line 6) 25638* integer, 16-byte: Octa. (line 6) 25639* integer, 8-byte: Quad. (line 9) 25640* integers: Integers. (line 6) 25641* integers, 16-bit: hword. (line 6) 25642* integers, 32-bit: Int. (line 6) 25643* integers, binary: Integers. (line 6) 25644* integers, decimal: Integers. (line 12) 25645* integers, hexadecimal: Integers. (line 15) 25646* integers, octal: Integers. (line 9) 25647* integers, one byte: Byte. (line 6) 25648* intel_syntax pseudo op, i386: i386-Variations. (line 6) 25649* intel_syntax pseudo op, x86-64: i386-Variations. (line 6) 25650* internal assembler sections: As Sections. (line 6) 25651* internal directive: Internal. (line 6) 25652* interrupt link register, ARC: ARC-Regs. (line 27) 25653* Interrupt Vector Base address, ARC: ARC-Regs. (line 66) 25654* invalid input: Bug Criteria. (line 14) 25655* invocation summary: Overview. (line 6) 25656* IP2K architecture options: IP2K-Opts. (line 9) 25657* IP2K architecture options <1>: IP2K-Opts. (line 14) 25658* IP2K line comment character: IP2K-Chars. (line 6) 25659* IP2K line separator: IP2K-Chars. (line 14) 25660* IP2K options: IP2K-Opts. (line 6) 25661* IP2K support: IP2K-Dependent. (line 6) 25662* irp directive: Irp. (line 6) 25663* irpc directive: Irpc. (line 6) 25664* ISA options, SH64: SH64 Options. (line 6) 25665* joining text and data sections: R. (line 6) 25666* jump instructions, i386: i386-Mnemonics. (line 58) 25667* jump instructions, relaxation: Xtensa Jump Relaxation. 25668 (line 6) 25669* jump instructions, x86-64: i386-Mnemonics. (line 58) 25670* jump optimization, i386: i386-Jumps. (line 6) 25671* jump optimization, x86-64: i386-Jumps. (line 6) 25672* jump/call operands, i386: i386-Variations. (line 15) 25673* jump/call operands, x86-64: i386-Variations. (line 15) 25674* L16SI instructions, relaxation: Xtensa Immediate Relaxation. 25675 (line 23) 25676* L16UI instructions, relaxation: Xtensa Immediate Relaxation. 25677 (line 23) 25678* L32I instructions, relaxation: Xtensa Immediate Relaxation. 25679 (line 23) 25680* L8UI instructions, relaxation: Xtensa Immediate Relaxation. 25681 (line 23) 25682* label (:): Statements. (line 31) 25683* label directive, TIC54X: TIC54X-Directives. (line 121) 25684* labels: Labels. (line 6) 25685* lcomm directive: Lcomm. (line 6) 25686* lcomm directive <1>: ARC Directives. (line 9) 25687* lcomm directive, COFF: i386-Directives. (line 6) 25688* lcommon directive, ARC: ARC Directives. (line 24) 25689* ld: Object. (line 15) 25690* ldouble directive M680x0: M68K-Float. (line 17) 25691* ldouble directive M68HC11: M68HC11-Float. (line 17) 25692* ldouble directive XGATE: XGATE-Float. (line 16) 25693* ldouble directive, TIC54X: TIC54X-Directives. (line 62) 25694* LDR reg,=<expr> pseudo op, AArch64: AArch64 Opcodes. (line 9) 25695* LDR reg,=<label> pseudo op, ARM: ARM Opcodes. (line 15) 25696* leafproc directive, i960: Directives-i960. (line 18) 25697* length directive, TIC54X: TIC54X-Directives. (line 125) 25698* length of symbols: Symbol Intro. (line 19) 25699* level 1 interrupt link register, ARC: ARC-Regs. (line 23) 25700* level 2 interrupt link register, ARC: ARC-Regs. (line 31) 25701* lflags directive (ignored): Lflags. (line 6) 25702* line: ARC-Chars. (line 30) 25703* line comment character: Comments. (line 19) 25704* line comment character, AArch64: AArch64-Chars. (line 6) 25705* line comment character, Alpha: Alpha-Chars. (line 6) 25706* line comment character, ARC: ARC-Chars. (line 11) 25707* line comment character, ARM: ARM-Chars. (line 6) 25708* line comment character, AVR: AVR-Chars. (line 6) 25709* line comment character, CR16: CR16-Chars. (line 6) 25710* line comment character, D10V: D10V-Chars. (line 6) 25711* line comment character, D30V: D30V-Chars. (line 6) 25712* line comment character, Epiphany: Epiphany-Chars. (line 6) 25713* line comment character, H8/300: H8/300-Chars. (line 6) 25714* line comment character, i386: i386-Chars. (line 6) 25715* line comment character, i860: i860-Chars. (line 6) 25716* line comment character, i960: i960-Chars. (line 6) 25717* line comment character, IA-64: IA-64-Chars. (line 6) 25718* line comment character, IP2K: IP2K-Chars. (line 6) 25719* line comment character, LM32: LM32-Chars. (line 6) 25720* line comment character, M32C: M32C-Chars. (line 6) 25721* line comment character, M680x0: M68K-Chars. (line 6) 25722* line comment character, M68HC11: M68HC11-Syntax. (line 17) 25723* line comment character, Meta: Meta-Chars. (line 6) 25724* line comment character, MicroBlaze: MicroBlaze-Chars. (line 6) 25725* line comment character, MIPS: MIPS-Chars. (line 6) 25726* line comment character, MSP 430: MSP430-Chars. (line 6) 25727* line comment character, Nios II: Nios II Chars. (line 6) 25728* line comment character, NS32K: NS32K-Chars. (line 6) 25729* line comment character, PJ: PJ-Chars. (line 6) 25730* line comment character, PowerPC: PowerPC-Chars. (line 6) 25731* line comment character, RL78: RL78-Chars. (line 6) 25732* line comment character, RX: RX-Chars. (line 6) 25733* line comment character, s390: s390 Characters. (line 6) 25734* line comment character, SCORE: SCORE-Chars. (line 6) 25735* line comment character, SH: SH-Chars. (line 6) 25736* line comment character, SH64: SH64-Chars. (line 6) 25737* line comment character, Sparc: Sparc-Chars. (line 6) 25738* line comment character, TIC54X: TIC54X-Chars. (line 6) 25739* line comment character, TIC6X: TIC6X Syntax. (line 6) 25740* line comment character, V850: V850-Chars. (line 6) 25741* line comment character, VAX: VAX-Chars. (line 6) 25742* line comment character, Visium: Visium Characters. (line 6) 25743* line comment character, XGATE: XGATE-Syntax. (line 16) 25744* line comment character, XStormy16: XStormy16-Chars. (line 6) 25745* line comment character, Z80: Z80-Chars. (line 6) 25746* line comment character, Z8000: Z8000-Chars. (line 6) 25747* line comment characters, CRIS: CRIS-Chars. (line 6) 25748* line comment characters, MMIX: MMIX-Chars. (line 6) 25749* line directive: Line. (line 6) 25750* line directive, MSP 430: MSP430 Directives. (line 14) 25751* line numbers, in input files: Input Files. (line 35) 25752* line separator character: Statements. (line 6) 25753* line separator character, Nios II: Nios II Chars. (line 6) 25754* line separator, AArch64: AArch64-Chars. (line 10) 25755* line separator, Alpha: Alpha-Chars. (line 11) 25756* line separator, ARC: ARC-Chars. (line 27) 25757* line separator, ARM: ARM-Chars. (line 14) 25758* line separator, AVR: AVR-Chars. (line 14) 25759* line separator, CR16: CR16-Chars. (line 12) 25760* line separator, Epiphany: Epiphany-Chars. (line 14) 25761* line separator, H8/300: H8/300-Chars. (line 8) 25762* line separator, i386: i386-Chars. (line 18) 25763* line separator, i860: i860-Chars. (line 14) 25764* line separator, i960: i960-Chars. (line 14) 25765* line separator, IA-64: IA-64-Chars. (line 8) 25766* line separator, IP2K: IP2K-Chars. (line 14) 25767* line separator, LM32: LM32-Chars. (line 12) 25768* line separator, M32C: M32C-Chars. (line 14) 25769* line separator, M680x0: M68K-Chars. (line 20) 25770* line separator, M68HC11: M68HC11-Syntax. (line 26) 25771* line separator, Meta: Meta-Chars. (line 8) 25772* line separator, MicroBlaze: MicroBlaze-Chars. (line 14) 25773* line separator, MIPS: MIPS-Chars. (line 14) 25774* line separator, MSP 430: MSP430-Chars. (line 14) 25775* line separator, NS32K: NS32K-Chars. (line 18) 25776* line separator, PJ: PJ-Chars. (line 14) 25777* line separator, PowerPC: PowerPC-Chars. (line 18) 25778* line separator, RL78: RL78-Chars. (line 14) 25779* line separator, RX: RX-Chars. (line 14) 25780* line separator, s390: s390 Characters. (line 13) 25781* line separator, SCORE: SCORE-Chars. (line 14) 25782* line separator, SH: SH-Chars. (line 8) 25783* line separator, SH64: SH64-Chars. (line 13) 25784* line separator, Sparc: Sparc-Chars. (line 14) 25785* line separator, TIC54X: TIC54X-Chars. (line 17) 25786* line separator, TIC6X: TIC6X Syntax. (line 13) 25787* line separator, V850: V850-Chars. (line 13) 25788* line separator, VAX: VAX-Chars. (line 14) 25789* line separator, Visium: Visium Characters. (line 14) 25790* line separator, XGATE: XGATE-Syntax. (line 25) 25791* line separator, XStormy16: XStormy16-Chars. (line 14) 25792* line separator, Z80: Z80-Chars. (line 13) 25793* line separator, Z8000: Z8000-Chars. (line 13) 25794* lines starting with #: Comments. (line 33) 25795* link register, ARC: ARC-Regs. (line 35) 25796* linker: Object. (line 15) 25797* linker, and assembler: Secs Background. (line 10) 25798* linkonce directive: Linkonce. (line 6) 25799* list directive: List. (line 6) 25800* list directive, TIC54X: TIC54X-Directives. (line 129) 25801* listing control, turning off: Nolist. (line 6) 25802* listing control, turning on: List. (line 6) 25803* listing control: new page: Eject. (line 6) 25804* listing control: paper size: Psize. (line 6) 25805* listing control: subtitle: Sbttl. (line 6) 25806* listing control: title line: Title. (line 6) 25807* listings, enabling: a. (line 6) 25808* literal directive: Literal Directive. (line 6) 25809* literal pool entries, s390: s390 Literal Pool Entries. 25810 (line 6) 25811* literal_position directive: Literal Position Directive. 25812 (line 6) 25813* literal_prefix directive: Literal Prefix Directive. 25814 (line 6) 25815* little endian output, MIPS: Overview. (line 809) 25816* little endian output, PJ: Overview. (line 716) 25817* little-endian output, MIPS: MIPS Options. (line 13) 25818* little-endian output, TIC6X: TIC6X Options. (line 46) 25819* LM32 line comment character: LM32-Chars. (line 6) 25820* LM32 line separator: LM32-Chars. (line 12) 25821* LM32 modifiers: LM32-Modifiers. (line 6) 25822* LM32 opcode summary: LM32 Opcodes. (line 6) 25823* LM32 options (none): LM32 Options. (line 6) 25824* LM32 register names: LM32-Regs. (line 6) 25825* LM32 support: LM32-Dependent. (line 6) 25826* ln directive: Ln. (line 6) 25827* lo directive, Nios II: Nios II Relocations. 25828 (line 23) 25829* lo pseudo-op, V850: V850 Opcodes. (line 22) 25830* loc directive: Loc. (line 6) 25831* local common symbols: Lcomm. (line 6) 25832* local directive: Local. (line 6) 25833* local labels: Symbol Names. (line 43) 25834* local symbol names: Symbol Names. (line 30) 25835* local symbols, retaining in output: L. (line 6) 25836* location counter: Dot. (line 6) 25837* location counter, advancing: Org. (line 6) 25838* location counter, Z80: Z80-Chars. (line 15) 25839* loc_mark_labels directive: Loc_mark_labels. (line 6) 25840* logical file name: File. (line 13) 25841* logical line number: Line. (line 6) 25842* logical line numbers: Comments. (line 33) 25843* long directive: Long. (line 6) 25844* long directive, i386: i386-Float. (line 21) 25845* long directive, TIC54X: TIC54X-Directives. (line 133) 25846* long directive, x86-64: i386-Float. (line 21) 25847* longcall pseudo-op, V850: V850 Opcodes. (line 122) 25848* longcalls directive: Longcalls Directive. 25849 (line 6) 25850* longjump pseudo-op, V850: V850 Opcodes. (line 128) 25851* loop counter, ARC: ARC-Regs. (line 41) 25852* loop directive, TIC54X: TIC54X-Directives. (line 141) 25853* LOOP instructions, alignment: Xtensa Automatic Alignment. 25854 (line 6) 25855* low directive, M32R: M32R-Directives. (line 9) 25856* lp register, V850: V850-Regs. (line 68) 25857* lval: Z8000 Directives. (line 27) 25858* LWP, i386: i386-LWP. (line 6) 25859* LWP, x86-64: i386-LWP. (line 6) 25860* M16C architecture option: M32C-Opts. (line 12) 25861* M32C architecture option: M32C-Opts. (line 9) 25862* M32C line comment character: M32C-Chars. (line 6) 25863* M32C line separator: M32C-Chars. (line 14) 25864* M32C modifiers: M32C-Modifiers. (line 6) 25865* M32C options: M32C-Opts. (line 6) 25866* M32C support: M32C-Dependent. (line 6) 25867* M32R architecture options: M32R-Opts. (line 9) 25868* M32R architecture options <1>: M32R-Opts. (line 17) 25869* M32R architecture options <2>: M32R-Opts. (line 21) 25870* M32R directives: M32R-Directives. (line 6) 25871* M32R options: M32R-Opts. (line 6) 25872* M32R support: M32R-Dependent. (line 6) 25873* M32R warnings: M32R-Warnings. (line 6) 25874* M680x0 addressing modes: M68K-Syntax. (line 21) 25875* M680x0 architecture options: M68K-Opts. (line 99) 25876* M680x0 branch improvement: M68K-Branch. (line 6) 25877* M680x0 directives: M68K-Directives. (line 6) 25878* M680x0 floating point: M68K-Float. (line 6) 25879* M680x0 immediate character: M68K-Chars. (line 13) 25880* M680x0 line comment character: M68K-Chars. (line 6) 25881* M680x0 line separator: M68K-Chars. (line 20) 25882* M680x0 opcodes: M68K-opcodes. (line 6) 25883* M680x0 options: M68K-Opts. (line 6) 25884* M680x0 pseudo-opcodes: M68K-Branch. (line 6) 25885* M680x0 size modifiers: M68K-Syntax. (line 8) 25886* M680x0 support: M68K-Dependent. (line 6) 25887* M680x0 syntax: M68K-Syntax. (line 8) 25888* M68HC11 addressing modes: M68HC11-Syntax. (line 29) 25889* M68HC11 and M68HC12 support: M68HC11-Dependent. (line 6) 25890* M68HC11 assembler directive .far: M68HC11-Directives. (line 20) 25891* M68HC11 assembler directive .interrupt: M68HC11-Directives. 25892 (line 26) 25893* M68HC11 assembler directive .mode: M68HC11-Directives. (line 16) 25894* M68HC11 assembler directive .relax: M68HC11-Directives. (line 10) 25895* M68HC11 assembler directive .xrefb: M68HC11-Directives. (line 31) 25896* M68HC11 assembler directives: M68HC11-Directives. (line 6) 25897* M68HC11 branch improvement: M68HC11-Branch. (line 6) 25898* M68HC11 floating point: M68HC11-Float. (line 6) 25899* M68HC11 line comment character: M68HC11-Syntax. (line 17) 25900* M68HC11 line separator: M68HC11-Syntax. (line 26) 25901* M68HC11 modifiers: M68HC11-Modifiers. (line 6) 25902* M68HC11 opcodes: M68HC11-opcodes. (line 6) 25903* M68HC11 options: M68HC11-Opts. (line 6) 25904* M68HC11 pseudo-opcodes: M68HC11-Branch. (line 6) 25905* M68HC11 syntax: M68HC11-Syntax. (line 6) 25906* M68HC12 assembler directives: M68HC11-Directives. (line 6) 25907* mA6 command line option, ARC: ARC Options. (line 14) 25908* mA7 command line option, ARC: ARC Options. (line 39) 25909* machine dependencies: Machine Dependencies. 25910 (line 6) 25911* machine directives, AArch64: AArch64 Directives. (line 6) 25912* machine directives, ARC: ARC Directives. (line 6) 25913* machine directives, ARM: ARM Directives. (line 6) 25914* machine directives, H8/300 (none): H8/300 Directives. (line 6) 25915* machine directives, i860: Directives-i860. (line 6) 25916* machine directives, i960: Directives-i960. (line 6) 25917* machine directives, MSP 430: MSP430 Directives. (line 6) 25918* machine directives, Nios II: Nios II Directives. (line 6) 25919* machine directives, SH: SH Directives. (line 6) 25920* machine directives, SH64: SH64 Directives. (line 9) 25921* machine directives, SPARC: Sparc-Directives. (line 6) 25922* machine directives, TIC54X: TIC54X-Directives. (line 6) 25923* machine directives, TIC6X: TIC6X Directives. (line 6) 25924* machine directives, TILE-Gx: TILE-Gx Directives. (line 6) 25925* machine directives, TILEPro: TILEPro Directives. (line 6) 25926* machine directives, V850: V850 Directives. (line 6) 25927* machine directives, VAX: VAX-directives. (line 6) 25928* machine directives, x86: i386-Directives. (line 6) 25929* machine directives, XStormy16: XStormy16 Directives. 25930 (line 6) 25931* machine independent directives: Pseudo Ops. (line 6) 25932* machine instructions (not covered): Manual. (line 14) 25933* machine relocations, Nios II: Nios II Relocations. 25934 (line 6) 25935* machine-independent syntax: Syntax. (line 6) 25936* macro directive: Macro. (line 28) 25937* macro directive, TIC54X: TIC54X-Directives. (line 151) 25938* macros: Macro. (line 6) 25939* macros, count executed: Macro. (line 142) 25940* Macros, MSP 430: MSP430-Macros. (line 6) 25941* macros, TIC54X: TIC54X-Macros. (line 6) 25942* make rules: MD. (line 6) 25943* manual, structure and purpose: Manual. (line 6) 25944* marc600 command line option, ARC: ARC Options. (line 14) 25945* mARC601 command line option, ARC: ARC Options. (line 27) 25946* mARC700 command line option, ARC: ARC Options. (line 39) 25947* march command line option, Nios II: Nios II Options. (line 28) 25948* math builtins, TIC54X: TIC54X-Builtins. (line 6) 25949* Maximum number of continuation lines: listing. (line 34) 25950* mEM command line option, ARC: ARC Options. (line 42) 25951* memory references, i386: i386-Memory. (line 6) 25952* memory references, x86-64: i386-Memory. (line 6) 25953* memory-mapped registers, TIC54X: TIC54X-MMRegs. (line 6) 25954* merging text and data sections: R. (line 6) 25955* messages from assembler: Errors. (line 6) 25956* Meta architectures: Meta Options. (line 6) 25957* Meta line comment character: Meta-Chars. (line 6) 25958* Meta line separator: Meta-Chars. (line 8) 25959* Meta options: Meta Options. (line 6) 25960* Meta registers: Meta-Regs. (line 6) 25961* Meta support: Meta-Dependent. (line 6) 25962* mHS command line option, ARC: ARC Options. (line 64) 25963* MicroBlaze architectures: MicroBlaze-Dependent. 25964 (line 6) 25965* MicroBlaze directives: MicroBlaze Directives. 25966 (line 6) 25967* MicroBlaze line comment character: MicroBlaze-Chars. (line 6) 25968* MicroBlaze line separator: MicroBlaze-Chars. (line 14) 25969* MicroBlaze support: MicroBlaze-Dependent. 25970 (line 12) 25971* minus, permitted arguments: Infix Ops. (line 50) 25972* MIPS 32-bit microMIPS instruction generation override: MIPS assembly options. 25973 (line 18) 25974* MIPS architecture options: MIPS Options. (line 29) 25975* MIPS big-endian output: MIPS Options. (line 13) 25976* MIPS CPU override: MIPS ISA. (line 18) 25977* MIPS directives to override command line options: MIPS assembly options. 25978 (line 6) 25979* MIPS DSP Release 1 instruction generation override: MIPS ASE Instruction Generation Overrides. 25980 (line 21) 25981* MIPS DSP Release 2 instruction generation override: MIPS ASE Instruction Generation Overrides. 25982 (line 26) 25983* MIPS DSP Release 3 instruction generation override: MIPS ASE Instruction Generation Overrides. 25984 (line 31) 25985* MIPS endianness: Overview. (line 806) 25986* MIPS eXtended Physical Address (XPA) instruction generation override: MIPS ASE Instruction Generation Overrides. 25987 (line 57) 25988* MIPS IEEE 754 NaN data encoding selection: MIPS NaN Encodings. 25989 (line 6) 25990* MIPS ISA: Overview. (line 812) 25991* MIPS ISA override: MIPS ISA. (line 6) 25992* MIPS line comment character: MIPS-Chars. (line 6) 25993* MIPS line separator: MIPS-Chars. (line 14) 25994* MIPS little-endian output: MIPS Options. (line 13) 25995* MIPS MCU instruction generation override: MIPS ASE Instruction Generation Overrides. 25996 (line 42) 25997* MIPS MDMX instruction generation override: MIPS ASE Instruction Generation Overrides. 25998 (line 16) 25999* MIPS MIPS-3D instruction generation override: MIPS ASE Instruction Generation Overrides. 26000 (line 6) 26001* MIPS MT instruction generation override: MIPS ASE Instruction Generation Overrides. 26002 (line 37) 26003* MIPS option stack: MIPS Option Stack. (line 6) 26004* MIPS processor: MIPS-Dependent. (line 6) 26005* MIPS SIMD Architecture instruction generation override: MIPS ASE Instruction Generation Overrides. 26006 (line 47) 26007* MIT: M68K-Syntax. (line 6) 26008* mlib directive, TIC54X: TIC54X-Directives. (line 157) 26009* mlist directive, TIC54X: TIC54X-Directives. (line 162) 26010* MMIX assembler directive BSPEC: MMIX-Pseudos. (line 137) 26011* MMIX assembler directive BYTE: MMIX-Pseudos. (line 101) 26012* MMIX assembler directive ESPEC: MMIX-Pseudos. (line 137) 26013* MMIX assembler directive GREG: MMIX-Pseudos. (line 53) 26014* MMIX assembler directive IS: MMIX-Pseudos. (line 44) 26015* MMIX assembler directive LOC: MMIX-Pseudos. (line 7) 26016* MMIX assembler directive LOCAL: MMIX-Pseudos. (line 29) 26017* MMIX assembler directive OCTA: MMIX-Pseudos. (line 113) 26018* MMIX assembler directive PREFIX: MMIX-Pseudos. (line 125) 26019* MMIX assembler directive TETRA: MMIX-Pseudos. (line 113) 26020* MMIX assembler directive WYDE: MMIX-Pseudos. (line 113) 26021* MMIX assembler directives: MMIX-Pseudos. (line 6) 26022* MMIX line comment characters: MMIX-Chars. (line 6) 26023* MMIX options: MMIX-Opts. (line 6) 26024* MMIX pseudo-op BSPEC: MMIX-Pseudos. (line 137) 26025* MMIX pseudo-op BYTE: MMIX-Pseudos. (line 101) 26026* MMIX pseudo-op ESPEC: MMIX-Pseudos. (line 137) 26027* MMIX pseudo-op GREG: MMIX-Pseudos. (line 53) 26028* MMIX pseudo-op IS: MMIX-Pseudos. (line 44) 26029* MMIX pseudo-op LOC: MMIX-Pseudos. (line 7) 26030* MMIX pseudo-op LOCAL: MMIX-Pseudos. (line 29) 26031* MMIX pseudo-op OCTA: MMIX-Pseudos. (line 113) 26032* MMIX pseudo-op PREFIX: MMIX-Pseudos. (line 125) 26033* MMIX pseudo-op TETRA: MMIX-Pseudos. (line 113) 26034* MMIX pseudo-op WYDE: MMIX-Pseudos. (line 113) 26035* MMIX pseudo-ops: MMIX-Pseudos. (line 6) 26036* MMIX register names: MMIX-Regs. (line 6) 26037* MMIX support: MMIX-Dependent. (line 6) 26038* mmixal differences: MMIX-mmixal. (line 6) 26039* mmregs directive, TIC54X: TIC54X-Directives. (line 167) 26040* mmsg directive, TIC54X: TIC54X-Directives. (line 75) 26041* MMX, i386: i386-SIMD. (line 6) 26042* MMX, x86-64: i386-SIMD. (line 6) 26043* mnemonic compatibility, i386: i386-Mnemonics. (line 64) 26044* mnemonic suffixes, i386: i386-Variations. (line 28) 26045* mnemonic suffixes, x86-64: i386-Variations. (line 28) 26046* mnemonics for opcodes, VAX: VAX-opcodes. (line 6) 26047* mnemonics, AVR: AVR Opcodes. (line 6) 26048* mnemonics, D10V: D10V-Opcodes. (line 6) 26049* mnemonics, D30V: D30V-Opcodes. (line 6) 26050* mnemonics, H8/300: H8/300 Opcodes. (line 6) 26051* mnemonics, LM32: LM32 Opcodes. (line 6) 26052* mnemonics, SH: SH Opcodes. (line 6) 26053* mnemonics, SH64: SH64 Opcodes. (line 6) 26054* mnemonics, Z8000: Z8000 Opcodes. (line 6) 26055* mnolist directive, TIC54X: TIC54X-Directives. (line 162) 26056* mnps400 command line option, ARC: ARC Options. (line 79) 26057* modifiers, M32C: M32C-Modifiers. (line 6) 26058* Motorola syntax for the 680x0: M68K-Moto-Syntax. (line 6) 26059* MOVI instructions, relaxation: Xtensa Immediate Relaxation. 26060 (line 12) 26061* MOVN, MOVZ and MOVK group relocations, AArch64: AArch64-Relocations. 26062 (line 6) 26063* MOVW and MOVT relocations, ARM: ARM-Relocations. (line 21) 26064* MRI compatibility mode: M. (line 6) 26065* mri directive: MRI. (line 6) 26066* MRI mode, temporarily: MRI. (line 6) 26067* MSP 430 floating point (IEEE): MSP430 Floating Point. 26068 (line 6) 26069* MSP 430 identifiers: MSP430-Chars. (line 17) 26070* MSP 430 line comment character: MSP430-Chars. (line 6) 26071* MSP 430 line separator: MSP430-Chars. (line 14) 26072* MSP 430 machine directives: MSP430 Directives. (line 6) 26073* MSP 430 macros: MSP430-Macros. (line 6) 26074* MSP 430 opcodes: MSP430 Opcodes. (line 6) 26075* MSP 430 options (none): MSP430 Options. (line 6) 26076* MSP 430 profiling capability: MSP430 Profiling Capability. 26077 (line 6) 26078* MSP 430 register names: MSP430-Regs. (line 6) 26079* MSP 430 support: MSP430-Dependent. (line 6) 26080* MSP430 Assembler Extensions: MSP430-Ext. (line 6) 26081* mul instruction, i386: i386-Notes. (line 6) 26082* mul instruction, x86-64: i386-Notes. (line 6) 26083* N32K support: NS32K-Dependent. (line 6) 26084* name: Z8000 Directives. (line 18) 26085* named section: Section. (line 6) 26086* named sections: Ld Sections. (line 8) 26087* names, symbol: Symbol Names. (line 6) 26088* naming object file: o. (line 6) 26089* NDS32 options: NDS32 Options. (line 6) 26090* NDS32 processor: NDS32-Dependent. (line 6) 26091* new page, in listings: Eject. (line 6) 26092* newblock directive, TIC54X: TIC54X-Directives. (line 173) 26093* newline (\n): Strings. (line 21) 26094* newline, required at file end: Statements. (line 14) 26095* Nios II line comment character: Nios II Chars. (line 6) 26096* Nios II line separator character: Nios II Chars. (line 6) 26097* Nios II machine directives: Nios II Directives. (line 6) 26098* Nios II machine relocations: Nios II Relocations. 26099 (line 6) 26100* Nios II opcodes: Nios II Opcodes. (line 6) 26101* Nios II options: Nios II Options. (line 6) 26102* Nios II support: NiosII-Dependent. (line 6) 26103* Nios support: NiosII-Dependent. (line 6) 26104* no-absolute-literals directive: Absolute Literals Directive. 26105 (line 6) 26106* no-longcalls directive: Longcalls Directive. 26107 (line 6) 26108* no-relax command line option, Nios II: Nios II Options. (line 19) 26109* no-schedule directive: Schedule Directive. (line 6) 26110* no-transform directive: Transform Directive. 26111 (line 6) 26112* nolist directive: Nolist. (line 6) 26113* nolist directive, TIC54X: TIC54X-Directives. (line 129) 26114* NOP pseudo op, ARM: ARM Opcodes. (line 9) 26115* notes for Alpha: Alpha Notes. (line 6) 26116* NS32K line comment character: NS32K-Chars. (line 6) 26117* NS32K line separator: NS32K-Chars. (line 18) 26118* null-terminated strings: Asciz. (line 6) 26119* number constants: Numbers. (line 6) 26120* number of macros executed: Macro. (line 142) 26121* numbered subsections: Sub-Sections. (line 6) 26122* numbers, 16-bit: hword. (line 6) 26123* numeric values: Expressions. (line 6) 26124* nword directive, SPARC: Sparc-Directives. (line 20) 26125* object attributes: Object Attributes. (line 6) 26126* object file: Object. (line 6) 26127* object file format: Object Formats. (line 6) 26128* object file name: o. (line 6) 26129* object file, after errors: Z. (line 6) 26130* obsolescent directives: Deprecated. (line 6) 26131* octa directive: Octa. (line 6) 26132* octal character code (\DDD): Strings. (line 30) 26133* octal integers: Integers. (line 9) 26134* offset directive: Offset. (line 6) 26135* offset directive, V850: V850 Directives. (line 6) 26136* opcode mnemonics, VAX: VAX-opcodes. (line 6) 26137* opcode names, TILE-Gx: TILE-Gx Opcodes. (line 6) 26138* opcode names, TILEPro: TILEPro Opcodes. (line 6) 26139* opcode names, Xtensa: Xtensa Opcodes. (line 6) 26140* opcode summary, AVR: AVR Opcodes. (line 6) 26141* opcode summary, D10V: D10V-Opcodes. (line 6) 26142* opcode summary, D30V: D30V-Opcodes. (line 6) 26143* opcode summary, H8/300: H8/300 Opcodes. (line 6) 26144* opcode summary, LM32: LM32 Opcodes. (line 6) 26145* opcode summary, SH: SH Opcodes. (line 6) 26146* opcode summary, SH64: SH64 Opcodes. (line 6) 26147* opcode summary, Z8000: Z8000 Opcodes. (line 6) 26148* opcodes for AArch64: AArch64 Opcodes. (line 6) 26149* opcodes for ARC: ARC Opcodes. (line 6) 26150* opcodes for ARM: ARM Opcodes. (line 6) 26151* opcodes for MSP 430: MSP430 Opcodes. (line 6) 26152* opcodes for Nios II: Nios II Opcodes. (line 6) 26153* opcodes for V850: V850 Opcodes. (line 6) 26154* opcodes, i860: Opcodes for i860. (line 6) 26155* opcodes, i960: Opcodes for i960. (line 6) 26156* opcodes, M680x0: M68K-opcodes. (line 6) 26157* opcodes, M68HC11: M68HC11-opcodes. (line 6) 26158* operand delimiters, i386: i386-Variations. (line 15) 26159* operand delimiters, x86-64: i386-Variations. (line 15) 26160* operand notation, VAX: VAX-operands. (line 6) 26161* operands in expressions: Arguments. (line 6) 26162* operator precedence: Infix Ops. (line 11) 26163* operators, in expressions: Operators. (line 6) 26164* operators, permitted arguments: Infix Ops. (line 6) 26165* optimization, D10V: Overview. (line 579) 26166* optimization, D30V: Overview. (line 584) 26167* optimizations: Xtensa Optimizations. 26168 (line 6) 26169* option directive, TIC54X: TIC54X-Directives. (line 177) 26170* option summary: Overview. (line 6) 26171* options for AArch64 (none): AArch64 Options. (line 6) 26172* options for Alpha: Alpha Options. (line 6) 26173* options for ARC: ARC Options. (line 6) 26174* options for ARM (none): ARM Options. (line 6) 26175* options for AVR (none): AVR Options. (line 6) 26176* options for Blackfin (none): Blackfin Options. (line 6) 26177* options for i386: i386-Options. (line 6) 26178* options for IA-64: IA-64 Options. (line 6) 26179* options for LM32 (none): LM32 Options. (line 6) 26180* options for Meta: Meta Options. (line 6) 26181* options for MSP430 (none): MSP430 Options. (line 6) 26182* options for NDS32: NDS32 Options. (line 6) 26183* options for Nios II: Nios II Options. (line 6) 26184* options for PDP-11: PDP-11-Options. (line 6) 26185* options for PowerPC: PowerPC-Opts. (line 6) 26186* options for s390: s390 Options. (line 6) 26187* options for SCORE: SCORE-Opts. (line 6) 26188* options for SPARC: Sparc-Opts. (line 6) 26189* options for TIC6X: TIC6X Options. (line 6) 26190* options for V850 (none): V850 Options. (line 6) 26191* options for VAX/VMS: VAX-Opts. (line 42) 26192* options for Visium: Visium Options. (line 6) 26193* options for x86-64: i386-Options. (line 6) 26194* options for Z80: Z80 Options. (line 6) 26195* options, all versions of assembler: Invoking. (line 6) 26196* options, command line: Command Line. (line 13) 26197* options, CRIS: CRIS-Opts. (line 6) 26198* options, D10V: D10V-Opts. (line 6) 26199* options, D30V: D30V-Opts. (line 6) 26200* options, Epiphany: Epiphany Options. (line 6) 26201* options, H8/300: H8/300 Options. (line 6) 26202* options, i960: Options-i960. (line 6) 26203* options, IP2K: IP2K-Opts. (line 6) 26204* options, M32C: M32C-Opts. (line 6) 26205* options, M32R: M32R-Opts. (line 6) 26206* options, M680x0: M68K-Opts. (line 6) 26207* options, M68HC11: M68HC11-Opts. (line 6) 26208* options, MMIX: MMIX-Opts. (line 6) 26209* options, PJ: PJ Options. (line 6) 26210* options, RL78: RL78-Opts. (line 6) 26211* options, RX: RX-Opts. (line 6) 26212* options, SH: SH Options. (line 6) 26213* options, SH64: SH64 Options. (line 6) 26214* options, TIC54X: TIC54X-Opts. (line 6) 26215* options, XGATE: XGATE-Opts. (line 6) 26216* options, Z8000: Z8000 Options. (line 6) 26217* org directive: Org. (line 6) 26218* other attribute, of a.out symbol: Symbol Other. (line 6) 26219* output file: Object. (line 6) 26220* output section padding: no-pad-sections. (line 6) 26221* p2align directive: P2align. (line 6) 26222* p2alignl directive: P2align. (line 28) 26223* p2alignw directive: P2align. (line 28) 26224* padding the location counter: Align. (line 6) 26225* padding the location counter given a power of two: P2align. 26226 (line 6) 26227* padding the location counter given number of bytes: Balign. 26228 (line 6) 26229* page, in listings: Eject. (line 6) 26230* paper size, for listings: Psize. (line 6) 26231* paths for .include: I. (line 6) 26232* patterns, writing in memory: Fill. (line 6) 26233* PDP-11 comments: PDP-11-Syntax. (line 16) 26234* PDP-11 floating-point register syntax: PDP-11-Syntax. (line 13) 26235* PDP-11 general-purpose register syntax: PDP-11-Syntax. (line 10) 26236* PDP-11 instruction naming: PDP-11-Mnemonics. (line 6) 26237* PDP-11 line separator: PDP-11-Syntax. (line 19) 26238* PDP-11 support: PDP-11-Dependent. (line 6) 26239* PDP-11 syntax: PDP-11-Syntax. (line 6) 26240* PIC code generation for ARM: ARM Options. (line 187) 26241* PIC code generation for M32R: M32R-Opts. (line 42) 26242* PIC selection, MIPS: MIPS Options. (line 21) 26243* PJ endianness: Overview. (line 713) 26244* PJ line comment character: PJ-Chars. (line 6) 26245* PJ line separator: PJ-Chars. (line 14) 26246* PJ options: PJ Options. (line 6) 26247* PJ support: PJ-Dependent. (line 6) 26248* plus, permitted arguments: Infix Ops. (line 45) 26249* popsection directive: PopSection. (line 6) 26250* Position-independent code, CRIS: CRIS-Opts. (line 27) 26251* Position-independent code, symbols in, CRIS: CRIS-Pic. (line 6) 26252* PowerPC architectures: PowerPC-Opts. (line 6) 26253* PowerPC directives: PowerPC-Pseudo. (line 6) 26254* PowerPC line comment character: PowerPC-Chars. (line 6) 26255* PowerPC line separator: PowerPC-Chars. (line 18) 26256* PowerPC options: PowerPC-Opts. (line 6) 26257* PowerPC support: PPC-Dependent. (line 6) 26258* precedence of operators: Infix Ops. (line 11) 26259* precision, floating point: Flonums. (line 6) 26260* prefix operators: Prefix Ops. (line 6) 26261* prefixes, i386: i386-Prefixes. (line 6) 26262* preprocessing: Preprocessing. (line 6) 26263* preprocessing, turning on and off: Preprocessing. (line 26) 26264* previous directive: Previous. (line 6) 26265* primary attributes, COFF symbols: COFF Symbols. (line 13) 26266* print directive: Print. (line 6) 26267* proc directive, SPARC: Sparc-Directives. (line 25) 26268* Processor Identification register, ARC: ARC-Regs. (line 51) 26269* profiler directive, MSP 430: MSP430 Directives. (line 26) 26270* profiling capability for MSP 430: MSP430 Profiling Capability. 26271 (line 6) 26272* Program Counter, ARC: ARC-Regs. (line 54) 26273* protected directive: Protected. (line 6) 26274* pseudo-op .arch, CRIS: CRIS-Pseudos. (line 50) 26275* pseudo-op .dword, CRIS: CRIS-Pseudos. (line 12) 26276* pseudo-op .syntax, CRIS: CRIS-Pseudos. (line 18) 26277* pseudo-op BSPEC, MMIX: MMIX-Pseudos. (line 137) 26278* pseudo-op BYTE, MMIX: MMIX-Pseudos. (line 101) 26279* pseudo-op ESPEC, MMIX: MMIX-Pseudos. (line 137) 26280* pseudo-op GREG, MMIX: MMIX-Pseudos. (line 53) 26281* pseudo-op IS, MMIX: MMIX-Pseudos. (line 44) 26282* pseudo-op LOC, MMIX: MMIX-Pseudos. (line 7) 26283* pseudo-op LOCAL, MMIX: MMIX-Pseudos. (line 29) 26284* pseudo-op OCTA, MMIX: MMIX-Pseudos. (line 113) 26285* pseudo-op PREFIX, MMIX: MMIX-Pseudos. (line 125) 26286* pseudo-op TETRA, MMIX: MMIX-Pseudos. (line 113) 26287* pseudo-op WYDE, MMIX: MMIX-Pseudos. (line 113) 26288* pseudo-opcodes for XStormy16: XStormy16 Opcodes. (line 6) 26289* pseudo-opcodes, M680x0: M68K-Branch. (line 6) 26290* pseudo-opcodes, M68HC11: M68HC11-Branch. (line 6) 26291* pseudo-ops for branch, VAX: VAX-branch. (line 6) 26292* pseudo-ops, CRIS: CRIS-Pseudos. (line 6) 26293* pseudo-ops, machine independent: Pseudo Ops. (line 6) 26294* pseudo-ops, MMIX: MMIX-Pseudos. (line 6) 26295* psize directive: Psize. (line 6) 26296* PSR bits: IA-64-Bits. (line 6) 26297* pstring directive, TIC54X: TIC54X-Directives. (line 206) 26298* psw register, V850: V850-Regs. (line 80) 26299* purgem directive: Purgem. (line 6) 26300* purpose of GNU assembler: GNU Assembler. (line 12) 26301* pushsection directive: PushSection. (line 6) 26302* quad directive: Quad. (line 6) 26303* quad directive, i386: i386-Float. (line 21) 26304* quad directive, x86-64: i386-Float. (line 21) 26305* real-mode code, i386: i386-16bit. (line 6) 26306* ref directive, TIC54X: TIC54X-Directives. (line 101) 26307* refsym directive, MSP 430: MSP430 Directives. (line 30) 26308* register directive, SPARC: Sparc-Directives. (line 29) 26309* register name prefix character, ARC: ARC-Chars. (line 7) 26310* register names, AArch64: AArch64-Regs. (line 6) 26311* register names, Alpha: Alpha-Regs. (line 6) 26312* register names, ARC: ARC-Regs. (line 6) 26313* register names, ARM: ARM-Regs. (line 6) 26314* register names, AVR: AVR-Regs. (line 6) 26315* register names, CRIS: CRIS-Regs. (line 6) 26316* register names, H8/300: H8/300-Regs. (line 6) 26317* register names, IA-64: IA-64-Regs. (line 6) 26318* register names, LM32: LM32-Regs. (line 6) 26319* register names, MMIX: MMIX-Regs. (line 6) 26320* register names, MSP 430: MSP430-Regs. (line 6) 26321* register names, Sparc: Sparc-Regs. (line 6) 26322* register names, TILE-Gx: TILE-Gx Registers. (line 6) 26323* register names, TILEPro: TILEPro Registers. (line 6) 26324* register names, V850: V850-Regs. (line 6) 26325* register names, VAX: VAX-operands. (line 17) 26326* register names, Visium: Visium Registers. (line 6) 26327* register names, Xtensa: Xtensa Registers. (line 6) 26328* register names, Z80: Z80-Regs. (line 6) 26329* register naming, s390: s390 Register. (line 6) 26330* register operands, i386: i386-Variations. (line 15) 26331* register operands, x86-64: i386-Variations. (line 15) 26332* registers, D10V: D10V-Regs. (line 6) 26333* registers, D30V: D30V-Regs. (line 6) 26334* registers, i386: i386-Regs. (line 6) 26335* registers, Meta: Meta-Regs. (line 6) 26336* registers, SH: SH-Regs. (line 6) 26337* registers, SH64: SH64-Regs. (line 6) 26338* registers, TIC54X memory-mapped: TIC54X-MMRegs. (line 6) 26339* registers, x86-64: i386-Regs. (line 6) 26340* registers, Z8000: Z8000-Regs. (line 6) 26341* relax-all command line option, Nios II: Nios II Options. (line 13) 26342* relax-section command line option, Nios II: Nios II Options. 26343 (line 6) 26344* relaxation: Xtensa Relaxation. (line 6) 26345* relaxation of ADDI instructions: Xtensa Immediate Relaxation. 26346 (line 43) 26347* relaxation of branch instructions: Xtensa Branch Relaxation. 26348 (line 6) 26349* relaxation of call instructions: Xtensa Call Relaxation. 26350 (line 6) 26351* relaxation of immediate fields: Xtensa Immediate Relaxation. 26352 (line 6) 26353* relaxation of jump instructions: Xtensa Jump Relaxation. 26354 (line 6) 26355* relaxation of L16SI instructions: Xtensa Immediate Relaxation. 26356 (line 23) 26357* relaxation of L16UI instructions: Xtensa Immediate Relaxation. 26358 (line 23) 26359* relaxation of L32I instructions: Xtensa Immediate Relaxation. 26360 (line 23) 26361* relaxation of L8UI instructions: Xtensa Immediate Relaxation. 26362 (line 23) 26363* relaxation of MOVI instructions: Xtensa Immediate Relaxation. 26364 (line 12) 26365* reloc directive: Reloc. (line 6) 26366* relocation: Sections. (line 6) 26367* relocation example: Ld Sections. (line 40) 26368* relocations, AArch64: AArch64-Relocations. 26369 (line 6) 26370* relocations, Alpha: Alpha-Relocs. (line 6) 26371* relocations, Sparc: Sparc-Relocs. (line 6) 26372* repeat prefixes, i386: i386-Prefixes. (line 44) 26373* reporting bugs in assembler: Reporting Bugs. (line 6) 26374* rept directive: Rept. (line 6) 26375* reserve directive, SPARC: Sparc-Directives. (line 39) 26376* return instructions, i386: i386-Variations. (line 40) 26377* return instructions, x86-64: i386-Variations. (line 40) 26378* REX prefixes, i386: i386-Prefixes. (line 46) 26379* RISC-V support: RISC-V-Dependent. (line 6) 26380* RL78 assembler directives: RL78-Directives. (line 6) 26381* RL78 line comment character: RL78-Chars. (line 6) 26382* RL78 line separator: RL78-Chars. (line 14) 26383* RL78 modifiers: RL78-Modifiers. (line 6) 26384* RL78 options: RL78-Opts. (line 6) 26385* RL78 support: RL78-Dependent. (line 6) 26386* rsect: Z8000 Directives. (line 52) 26387* RX assembler directive .3byte: RX-Directives. (line 9) 26388* RX assembler directive .fetchalign: RX-Directives. (line 13) 26389* RX assembler directives: RX-Directives. (line 6) 26390* RX floating point: RX-Float. (line 6) 26391* RX line comment character: RX-Chars. (line 6) 26392* RX line separator: RX-Chars. (line 14) 26393* RX modifiers: RX-Modifiers. (line 6) 26394* RX options: RX-Opts. (line 6) 26395* RX support: RX-Dependent. (line 6) 26396* s390 floating point: s390 Floating Point. 26397 (line 6) 26398* s390 instruction aliases: s390 Aliases. (line 6) 26399* s390 instruction formats: s390 Formats. (line 6) 26400* s390 instruction marker: s390 Instruction Marker. 26401 (line 6) 26402* s390 instruction mnemonics: s390 Mnemonics. (line 6) 26403* s390 instruction operand modifier: s390 Operand Modifier. 26404 (line 6) 26405* s390 instruction operands: s390 Operands. (line 6) 26406* s390 instruction syntax: s390 Syntax. (line 6) 26407* s390 line comment character: s390 Characters. (line 6) 26408* s390 line separator: s390 Characters. (line 13) 26409* s390 literal pool entries: s390 Literal Pool Entries. 26410 (line 6) 26411* s390 options: s390 Options. (line 6) 26412* s390 register naming: s390 Register. (line 6) 26413* s390 support: S/390-Dependent. (line 6) 26414* Saved User Stack Pointer, ARC: ARC-Regs. (line 73) 26415* sblock directive, TIC54X: TIC54X-Directives. (line 180) 26416* sbttl directive: Sbttl. (line 6) 26417* schedule directive: Schedule Directive. (line 6) 26418* scl directive: Scl. (line 6) 26419* SCORE architectures: SCORE-Opts. (line 6) 26420* SCORE directives: SCORE-Pseudo. (line 6) 26421* SCORE line comment character: SCORE-Chars. (line 6) 26422* SCORE line separator: SCORE-Chars. (line 14) 26423* SCORE options: SCORE-Opts. (line 6) 26424* SCORE processor: SCORE-Dependent. (line 6) 26425* sdaoff pseudo-op, V850: V850 Opcodes. (line 65) 26426* search path for .include: I. (line 6) 26427* sect directive, TIC54X: TIC54X-Directives. (line 186) 26428* section directive (COFF version): Section. (line 16) 26429* section directive (ELF version): Section. (line 67) 26430* section directive, V850: V850 Directives. (line 9) 26431* section name substitution: Section. (line 71) 26432* section override prefixes, i386: i386-Prefixes. (line 23) 26433* Section Stack: PopSection. (line 6) 26434* Section Stack <1>: Previous. (line 6) 26435* Section Stack <2>: PushSection. (line 6) 26436* Section Stack <3>: Section. (line 62) 26437* Section Stack <4>: SubSection. (line 6) 26438* section-relative addressing: Secs Background. (line 65) 26439* sections: Sections. (line 6) 26440* sections in messages, internal: As Sections. (line 6) 26441* sections, i386: i386-Variations. (line 46) 26442* sections, named: Ld Sections. (line 8) 26443* sections, x86-64: i386-Variations. (line 46) 26444* seg directive, SPARC: Sparc-Directives. (line 44) 26445* segm: Z8000 Directives. (line 10) 26446* set at directive, Nios II: Nios II Directives. (line 35) 26447* set break directive, Nios II: Nios II Directives. (line 43) 26448* set directive: Set. (line 6) 26449* set directive, Nios II: Nios II Directives. (line 57) 26450* set directive, TIC54X: TIC54X-Directives. (line 189) 26451* set noat directive, Nios II: Nios II Directives. (line 31) 26452* set nobreak directive, Nios II: Nios II Directives. (line 39) 26453* set norelax directive, Nios II: Nios II Directives. (line 46) 26454* set relaxall directive, Nios II: Nios II Directives. (line 53) 26455* set relaxsection directive, Nios II: Nios II Directives. (line 49) 26456* SH addressing modes: SH-Addressing. (line 6) 26457* SH floating point (IEEE): SH Floating Point. (line 6) 26458* SH line comment character: SH-Chars. (line 6) 26459* SH line separator: SH-Chars. (line 8) 26460* SH machine directives: SH Directives. (line 6) 26461* SH opcode summary: SH Opcodes. (line 6) 26462* SH options: SH Options. (line 6) 26463* SH registers: SH-Regs. (line 6) 26464* SH support: SH-Dependent. (line 6) 26465* SH64 ABI options: SH64 Options. (line 25) 26466* SH64 addressing modes: SH64-Addressing. (line 6) 26467* SH64 ISA options: SH64 Options. (line 6) 26468* SH64 line comment character: SH64-Chars. (line 6) 26469* SH64 line separator: SH64-Chars. (line 13) 26470* SH64 machine directives: SH64 Directives. (line 9) 26471* SH64 opcode summary: SH64 Opcodes. (line 6) 26472* SH64 options: SH64 Options. (line 6) 26473* SH64 registers: SH64-Regs. (line 6) 26474* SH64 support: SH64-Dependent. (line 6) 26475* shigh directive, M32R: M32R-Directives. (line 26) 26476* short directive: Short. (line 6) 26477* short directive, TIC54X: TIC54X-Directives. (line 109) 26478* SIMD, i386: i386-SIMD. (line 6) 26479* SIMD, x86-64: i386-SIMD. (line 6) 26480* single character constant: Chars. (line 6) 26481* single directive: Single. (line 6) 26482* single directive, i386: i386-Float. (line 14) 26483* single directive, x86-64: i386-Float. (line 14) 26484* single quote, Z80: Z80-Chars. (line 20) 26485* sixteen bit integers: hword. (line 6) 26486* sixteen byte integer: Octa. (line 6) 26487* size directive (COFF version): Size. (line 11) 26488* size directive (ELF version): Size. (line 19) 26489* size modifiers, D10V: D10V-Size. (line 6) 26490* size modifiers, D30V: D30V-Size. (line 6) 26491* size modifiers, M680x0: M68K-Syntax. (line 8) 26492* size prefixes, i386: i386-Prefixes. (line 27) 26493* size suffixes, H8/300: H8/300 Opcodes. (line 160) 26494* size, translations, Sparc: Sparc-Size-Translations. 26495 (line 6) 26496* sizes operands, i386: i386-Variations. (line 28) 26497* sizes operands, x86-64: i386-Variations. (line 28) 26498* skip directive: Skip. (line 6) 26499* skip directive, M680x0: M68K-Directives. (line 19) 26500* skip directive, SPARC: Sparc-Directives. (line 48) 26501* sleb128 directive: Sleb128. (line 6) 26502* small data, MIPS: MIPS Small Data. (line 6) 26503* SmartMIPS instruction generation override: MIPS ASE Instruction Generation Overrides. 26504 (line 11) 26505* SOM symbol attributes: SOM Symbols. (line 6) 26506* source program: Input Files. (line 6) 26507* source, destination operands; i386: i386-Variations. (line 21) 26508* source, destination operands; x86-64: i386-Variations. (line 21) 26509* sp register: Xtensa Registers. (line 6) 26510* sp register, V850: V850-Regs. (line 12) 26511* space directive: Space. (line 6) 26512* space directive, TIC54X: TIC54X-Directives. (line 194) 26513* space used, maximum for assembly: statistics. (line 6) 26514* SPARC architectures: Sparc-Opts. (line 6) 26515* Sparc constants: Sparc-Constants. (line 6) 26516* SPARC data alignment: Sparc-Aligned-Data. (line 6) 26517* SPARC floating point (IEEE): Sparc-Float. (line 6) 26518* Sparc line comment character: Sparc-Chars. (line 6) 26519* Sparc line separator: Sparc-Chars. (line 14) 26520* SPARC machine directives: Sparc-Directives. (line 6) 26521* SPARC options: Sparc-Opts. (line 6) 26522* Sparc registers: Sparc-Regs. (line 6) 26523* Sparc relocations: Sparc-Relocs. (line 6) 26524* Sparc size translations: Sparc-Size-Translations. 26525 (line 6) 26526* SPARC support: Sparc-Dependent. (line 6) 26527* SPARC syntax: Sparc-Aligned-Data. (line 21) 26528* special characters, M680x0: M68K-Chars. (line 6) 26529* special purpose registers, MSP 430: MSP430-Regs. (line 11) 26530* sslist directive, TIC54X: TIC54X-Directives. (line 201) 26531* ssnolist directive, TIC54X: TIC54X-Directives. (line 201) 26532* stabd directive: Stab. (line 38) 26533* stabn directive: Stab. (line 49) 26534* stabs directive: Stab. (line 52) 26535* stabX directives: Stab. (line 6) 26536* stack pointer, ARC: ARC-Regs. (line 20) 26537* standard assembler sections: Secs Background. (line 27) 26538* standard input, as input file: Command Line. (line 10) 26539* statement separator character: Statements. (line 6) 26540* statement separator, AArch64: AArch64-Chars. (line 10) 26541* statement separator, Alpha: Alpha-Chars. (line 11) 26542* statement separator, ARC: ARC-Chars. (line 27) 26543* statement separator, ARM: ARM-Chars. (line 14) 26544* statement separator, AVR: AVR-Chars. (line 14) 26545* statement separator, CR16: CR16-Chars. (line 12) 26546* statement separator, Epiphany: Epiphany-Chars. (line 14) 26547* statement separator, H8/300: H8/300-Chars. (line 8) 26548* statement separator, i386: i386-Chars. (line 18) 26549* statement separator, i860: i860-Chars. (line 14) 26550* statement separator, i960: i960-Chars. (line 14) 26551* statement separator, IA-64: IA-64-Chars. (line 8) 26552* statement separator, IP2K: IP2K-Chars. (line 14) 26553* statement separator, LM32: LM32-Chars. (line 12) 26554* statement separator, M32C: M32C-Chars. (line 14) 26555* statement separator, M68HC11: M68HC11-Syntax. (line 26) 26556* statement separator, Meta: Meta-Chars. (line 8) 26557* statement separator, MicroBlaze: MicroBlaze-Chars. (line 14) 26558* statement separator, MIPS: MIPS-Chars. (line 14) 26559* statement separator, MSP 430: MSP430-Chars. (line 14) 26560* statement separator, NS32K: NS32K-Chars. (line 18) 26561* statement separator, PJ: PJ-Chars. (line 14) 26562* statement separator, PowerPC: PowerPC-Chars. (line 18) 26563* statement separator, RL78: RL78-Chars. (line 14) 26564* statement separator, RX: RX-Chars. (line 14) 26565* statement separator, s390: s390 Characters. (line 13) 26566* statement separator, SCORE: SCORE-Chars. (line 14) 26567* statement separator, SH: SH-Chars. (line 8) 26568* statement separator, SH64: SH64-Chars. (line 13) 26569* statement separator, Sparc: Sparc-Chars. (line 14) 26570* statement separator, TIC54X: TIC54X-Chars. (line 17) 26571* statement separator, TIC6X: TIC6X Syntax. (line 13) 26572* statement separator, V850: V850-Chars. (line 13) 26573* statement separator, VAX: VAX-Chars. (line 14) 26574* statement separator, Visium: Visium Characters. (line 14) 26575* statement separator, XGATE: XGATE-Syntax. (line 25) 26576* statement separator, XStormy16: XStormy16-Chars. (line 14) 26577* statement separator, Z80: Z80-Chars. (line 13) 26578* statement separator, Z8000: Z8000-Chars. (line 13) 26579* statements, structure of: Statements. (line 6) 26580* statistics, about assembly: statistics. (line 6) 26581* Status register, ARC: ARC-Regs. (line 57) 26582* STATUS32 saved on exception, ARC: ARC-Regs. (line 82) 26583* stopping the assembly: Abort. (line 6) 26584* Stored STATUS32 register on entry to level P0 interrupts, ARC: ARC-Regs. 26585 (line 69) 26586* string constants: Strings. (line 6) 26587* string directive: String. (line 8) 26588* string directive on HPPA: HPPA Directives. (line 137) 26589* string directive, TIC54X: TIC54X-Directives. (line 206) 26590* string literals: Ascii. (line 6) 26591* string, copying to object file: String. (line 8) 26592* string16 directive: String. (line 8) 26593* string16, copying to object file: String. (line 8) 26594* string32 directive: String. (line 8) 26595* string32, copying to object file: String. (line 8) 26596* string64 directive: String. (line 8) 26597* string64, copying to object file: String. (line 8) 26598* string8 directive: String. (line 8) 26599* string8, copying to object file: String. (line 8) 26600* struct directive: Struct. (line 6) 26601* struct directive, TIC54X: TIC54X-Directives. (line 214) 26602* structure debugging, COFF: Tag. (line 6) 26603* sub-instruction ordering, D10V: D10V-Chars. (line 14) 26604* sub-instruction ordering, D30V: D30V-Chars. (line 14) 26605* sub-instructions, D10V: D10V-Subs. (line 6) 26606* sub-instructions, D30V: D30V-Subs. (line 6) 26607* subexpressions: Arguments. (line 24) 26608* subsection directive: SubSection. (line 6) 26609* subsym builtins, TIC54X: TIC54X-Macros. (line 16) 26610* subtitles for listings: Sbttl. (line 6) 26611* subtraction, permitted arguments: Infix Ops. (line 50) 26612* summary of options: Overview. (line 6) 26613* support: HPPA-Dependent. (line 6) 26614* supporting files, including: Include. (line 6) 26615* suppressing warnings: W. (line 11) 26616* sval: Z8000 Directives. (line 33) 26617* symbol attributes: Symbol Attributes. (line 6) 26618* symbol attributes, a.out: a.out Symbols. (line 6) 26619* symbol attributes, COFF: COFF Symbols. (line 6) 26620* symbol attributes, SOM: SOM Symbols. (line 6) 26621* symbol descriptor, COFF: Desc. (line 6) 26622* symbol modifiers: AVR-Modifiers. (line 12) 26623* symbol modifiers <1>: LM32-Modifiers. (line 12) 26624* symbol modifiers <2>: M32C-Modifiers. (line 11) 26625* symbol modifiers <3>: M68HC11-Modifiers. (line 12) 26626* symbol modifiers, TILE-Gx: TILE-Gx Modifiers. (line 6) 26627* symbol modifiers, TILEPro: TILEPro Modifiers. (line 6) 26628* symbol names: Symbol Names. (line 6) 26629* symbol names, $ in: D10V-Chars. (line 46) 26630* symbol names, $ in <1>: D30V-Chars. (line 70) 26631* symbol names, $ in <2>: Meta-Chars. (line 10) 26632* symbol names, $ in <3>: SH-Chars. (line 15) 26633* symbol names, $ in <4>: SH64-Chars. (line 15) 26634* symbol names, local: Symbol Names. (line 30) 26635* symbol names, temporary: Symbol Names. (line 43) 26636* symbol prefix character, ARC: ARC-Chars. (line 20) 26637* symbol storage class (COFF): Scl. (line 6) 26638* symbol type: Symbol Type. (line 6) 26639* symbol type, COFF: Type. (line 11) 26640* symbol type, ELF: Type. (line 22) 26641* symbol value: Symbol Value. (line 6) 26642* symbol value, setting: Set. (line 6) 26643* symbol values, assigning: Setting Symbols. (line 6) 26644* symbol versioning: Symver. (line 6) 26645* symbol, common: Comm. (line 6) 26646* symbol, making visible to linker: Global. (line 6) 26647* symbolic debuggers, information for: Stab. (line 6) 26648* symbols: Symbols. (line 6) 26649* Symbols in position-independent code, CRIS: CRIS-Pic. (line 6) 26650* symbols with uppercase, VAX/VMS: VAX-Opts. (line 42) 26651* symbols, assigning values to: Equ. (line 6) 26652* Symbols, built-in, CRIS: CRIS-Symbols. (line 6) 26653* Symbols, CRIS, built-in: CRIS-Symbols. (line 6) 26654* symbols, local common: Lcomm. (line 6) 26655* symver directive: Symver. (line 6) 26656* syntax compatibility, i386: i386-Variations. (line 6) 26657* syntax compatibility, x86-64: i386-Variations. (line 6) 26658* syntax, AVR: AVR-Modifiers. (line 6) 26659* syntax, Blackfin: Blackfin Syntax. (line 6) 26660* syntax, D10V: D10V-Syntax. (line 6) 26661* syntax, D30V: D30V-Syntax. (line 6) 26662* syntax, LM32: LM32-Modifiers. (line 6) 26663* syntax, M680x0: M68K-Syntax. (line 8) 26664* syntax, M68HC11: M68HC11-Syntax. (line 6) 26665* syntax, M68HC11 <1>: M68HC11-Modifiers. (line 6) 26666* syntax, machine-independent: Syntax. (line 6) 26667* syntax, RL78: RL78-Modifiers. (line 6) 26668* syntax, RX: RX-Modifiers. (line 6) 26669* syntax, SPARC: Sparc-Aligned-Data. (line 20) 26670* syntax, TILE-Gx: TILE-Gx Syntax. (line 6) 26671* syntax, TILEPro: TILEPro Syntax. (line 6) 26672* syntax, XGATE: XGATE-Syntax. (line 6) 26673* syntax, Xtensa assembler: Xtensa Syntax. (line 6) 26674* sysproc directive, i960: Directives-i960. (line 37) 26675* tab (\t): Strings. (line 27) 26676* tab directive, TIC54X: TIC54X-Directives. (line 245) 26677* tag directive: Tag. (line 6) 26678* tag directive, TIC54X: TIC54X-Directives. (line 214) 26679* tag directive, TIC54X <1>: TIC54X-Directives. (line 248) 26680* TBM, i386: i386-TBM. (line 6) 26681* TBM, x86-64: i386-TBM. (line 6) 26682* tdaoff pseudo-op, V850: V850 Opcodes. (line 81) 26683* temporary symbol names: Symbol Names. (line 43) 26684* text and data sections, joining: R. (line 6) 26685* text directive: Text. (line 6) 26686* text section: Ld Sections. (line 9) 26687* tfloat directive, i386: i386-Float. (line 14) 26688* tfloat directive, x86-64: i386-Float. (line 14) 26689* Thumb support: ARM-Dependent. (line 6) 26690* TIC54X builtin math functions: TIC54X-Builtins. (line 6) 26691* TIC54X line comment character: TIC54X-Chars. (line 6) 26692* TIC54X line separator: TIC54X-Chars. (line 17) 26693* TIC54X machine directives: TIC54X-Directives. (line 6) 26694* TIC54X memory-mapped registers: TIC54X-MMRegs. (line 6) 26695* TIC54X options: TIC54X-Opts. (line 6) 26696* TIC54X subsym builtins: TIC54X-Macros. (line 16) 26697* TIC54X support: TIC54X-Dependent. (line 6) 26698* TIC54X-specific macros: TIC54X-Macros. (line 6) 26699* TIC6X big-endian output: TIC6X Options. (line 46) 26700* TIC6X line comment character: TIC6X Syntax. (line 6) 26701* TIC6X line separator: TIC6X Syntax. (line 13) 26702* TIC6X little-endian output: TIC6X Options. (line 46) 26703* TIC6X machine directives: TIC6X Directives. (line 6) 26704* TIC6X options: TIC6X Options. (line 6) 26705* TIC6X support: TIC6X-Dependent. (line 6) 26706* TILE-Gx machine directives: TILE-Gx Directives. (line 6) 26707* TILE-Gx modifiers: TILE-Gx Modifiers. (line 6) 26708* TILE-Gx opcode names: TILE-Gx Opcodes. (line 6) 26709* TILE-Gx register names: TILE-Gx Registers. (line 6) 26710* TILE-Gx support: TILE-Gx-Dependent. (line 6) 26711* TILE-Gx syntax: TILE-Gx Syntax. (line 6) 26712* TILEPro machine directives: TILEPro Directives. (line 6) 26713* TILEPro modifiers: TILEPro Modifiers. (line 6) 26714* TILEPro opcode names: TILEPro Opcodes. (line 6) 26715* TILEPro register names: TILEPro Registers. (line 6) 26716* TILEPro support: TILEPro-Dependent. (line 6) 26717* TILEPro syntax: TILEPro Syntax. (line 6) 26718* time, total for assembly: statistics. (line 6) 26719* title directive: Title. (line 6) 26720* tls_gd directive, Nios II: Nios II Relocations. 26721 (line 38) 26722* tls_ie directive, Nios II: Nios II Relocations. 26723 (line 38) 26724* tls_ldm directive, Nios II: Nios II Relocations. 26725 (line 38) 26726* tls_ldo directive, Nios II: Nios II Relocations. 26727 (line 38) 26728* tls_le directive, Nios II: Nios II Relocations. 26729 (line 38) 26730* TMS320C6X support: TIC6X-Dependent. (line 6) 26731* tp register, V850: V850-Regs. (line 16) 26732* transform directive: Transform Directive. 26733 (line 6) 26734* trusted compiler: f. (line 6) 26735* turning preprocessing on and off: Preprocessing. (line 26) 26736* type directive (COFF version): Type. (line 11) 26737* type directive (ELF version): Type. (line 22) 26738* type of a symbol: Symbol Type. (line 6) 26739* ualong directive, SH: SH Directives. (line 6) 26740* uaquad directive, SH: SH Directives. (line 6) 26741* uaword directive, SH: SH Directives. (line 6) 26742* ubyte directive, TIC54X: TIC54X-Directives. (line 34) 26743* uchar directive, TIC54X: TIC54X-Directives. (line 34) 26744* uhalf directive, TIC54X: TIC54X-Directives. (line 109) 26745* uint directive, TIC54X: TIC54X-Directives. (line 109) 26746* uleb128 directive: Uleb128. (line 6) 26747* ulong directive, TIC54X: TIC54X-Directives. (line 133) 26748* undefined section: Ld Sections. (line 36) 26749* union directive, TIC54X: TIC54X-Directives. (line 248) 26750* unsegm: Z8000 Directives. (line 14) 26751* usect directive, TIC54X: TIC54X-Directives. (line 260) 26752* ushort directive, TIC54X: TIC54X-Directives. (line 109) 26753* uword directive, TIC54X: TIC54X-Directives. (line 109) 26754* V850 command line options: V850 Options. (line 9) 26755* V850 floating point (IEEE): V850 Floating Point. 26756 (line 6) 26757* V850 line comment character: V850-Chars. (line 6) 26758* V850 line separator: V850-Chars. (line 13) 26759* V850 machine directives: V850 Directives. (line 6) 26760* V850 opcodes: V850 Opcodes. (line 6) 26761* V850 options (none): V850 Options. (line 6) 26762* V850 register names: V850-Regs. (line 6) 26763* V850 support: V850-Dependent. (line 6) 26764* val directive: Val. (line 6) 26765* value attribute, COFF: Val. (line 6) 26766* value of a symbol: Symbol Value. (line 6) 26767* var directive, TIC54X: TIC54X-Directives. (line 270) 26768* VAX bitfields not supported: VAX-no. (line 6) 26769* VAX branch improvement: VAX-branch. (line 6) 26770* VAX command-line options ignored: VAX-Opts. (line 6) 26771* VAX displacement sizing character: VAX-operands. (line 12) 26772* VAX floating point: VAX-float. (line 6) 26773* VAX immediate character: VAX-operands. (line 6) 26774* VAX indirect character: VAX-operands. (line 9) 26775* VAX line comment character: VAX-Chars. (line 6) 26776* VAX line separator: VAX-Chars. (line 14) 26777* VAX machine directives: VAX-directives. (line 6) 26778* VAX opcode mnemonics: VAX-opcodes. (line 6) 26779* VAX operand notation: VAX-operands. (line 6) 26780* VAX register names: VAX-operands. (line 17) 26781* VAX support: Vax-Dependent. (line 6) 26782* Vax-11 C compatibility: VAX-Opts. (line 42) 26783* VAX/VMS options: VAX-Opts. (line 42) 26784* version directive: Version. (line 6) 26785* version directive, TIC54X: TIC54X-Directives. (line 274) 26786* version of assembler: v. (line 6) 26787* versions of symbols: Symver. (line 6) 26788* Virtualization instruction generation override: MIPS ASE Instruction Generation Overrides. 26789 (line 52) 26790* visibility: Hidden. (line 6) 26791* visibility <1>: Internal. (line 6) 26792* visibility <2>: Protected. (line 6) 26793* Visium line comment character: Visium Characters. (line 6) 26794* Visium line separator: Visium Characters. (line 14) 26795* Visium options: Visium Options. (line 6) 26796* Visium registers: Visium Registers. (line 6) 26797* Visium support: Visium-Dependent. (line 6) 26798* VMS (VAX) options: VAX-Opts. (line 42) 26799* vtable_entry directive: VTableEntry. (line 6) 26800* vtable_inherit directive: VTableInherit. (line 6) 26801* warning directive: Warning. (line 6) 26802* warning for altered difference tables: K. (line 6) 26803* warning messages: Errors. (line 6) 26804* warnings, causing error: W. (line 16) 26805* warnings, M32R: M32R-Warnings. (line 6) 26806* warnings, suppressing: W. (line 11) 26807* warnings, switching on: W. (line 19) 26808* weak directive: Weak. (line 6) 26809* weakref directive: Weakref. (line 6) 26810* whitespace: Whitespace. (line 6) 26811* whitespace, removed by preprocessor: Preprocessing. (line 7) 26812* wide floating point directives, VAX: VAX-directives. (line 9) 26813* width directive, TIC54X: TIC54X-Directives. (line 125) 26814* Width of continuation lines of disassembly output: listing. 26815 (line 21) 26816* Width of first line disassembly output: listing. (line 16) 26817* Width of source line output: listing. (line 28) 26818* wmsg directive, TIC54X: TIC54X-Directives. (line 75) 26819* word aligned program counter, ARC: ARC-Regs. (line 44) 26820* word directive: Word. (line 6) 26821* word directive, H8/300: H8/300 Directives. (line 6) 26822* word directive, i386: i386-Float. (line 21) 26823* word directive, Nios II: Nios II Directives. (line 13) 26824* word directive, SPARC: Sparc-Directives. (line 51) 26825* word directive, TIC54X: TIC54X-Directives. (line 109) 26826* word directive, x86-64: i386-Float. (line 21) 26827* writing patterns in memory: Fill. (line 6) 26828* wval: Z8000 Directives. (line 24) 26829* x86 machine directives: i386-Directives. (line 6) 26830* x86-64 arch directive: i386-Arch. (line 6) 26831* x86-64 att_syntax pseudo op: i386-Variations. (line 6) 26832* x86-64 conversion instructions: i386-Mnemonics. (line 39) 26833* x86-64 floating point: i386-Float. (line 6) 26834* x86-64 immediate operands: i386-Variations. (line 15) 26835* x86-64 instruction naming: i386-Mnemonics. (line 9) 26836* x86-64 intel_syntax pseudo op: i386-Variations. (line 6) 26837* x86-64 jump optimization: i386-Jumps. (line 6) 26838* x86-64 jump, call, return: i386-Variations. (line 40) 26839* x86-64 jump/call operands: i386-Variations. (line 15) 26840* x86-64 memory references: i386-Memory. (line 6) 26841* x86-64 options: i386-Options. (line 6) 26842* x86-64 register operands: i386-Variations. (line 15) 26843* x86-64 registers: i386-Regs. (line 6) 26844* x86-64 sections: i386-Variations. (line 46) 26845* x86-64 size suffixes: i386-Variations. (line 28) 26846* x86-64 source, destination operands: i386-Variations. (line 21) 26847* x86-64 support: i386-Dependent. (line 6) 26848* x86-64 syntax compatibility: i386-Variations. (line 6) 26849* xfloat directive, TIC54X: TIC54X-Directives. (line 62) 26850* XGATE addressing modes: XGATE-Syntax. (line 28) 26851* XGATE assembler directives: XGATE-Directives. (line 6) 26852* XGATE floating point: XGATE-Float. (line 6) 26853* XGATE line comment character: XGATE-Syntax. (line 16) 26854* XGATE line separator: XGATE-Syntax. (line 25) 26855* XGATE opcodes: XGATE-opcodes. (line 6) 26856* XGATE options: XGATE-Opts. (line 6) 26857* XGATE support: XGATE-Dependent. (line 6) 26858* XGATE syntax: XGATE-Syntax. (line 6) 26859* xlong directive, TIC54X: TIC54X-Directives. (line 133) 26860* XStormy16 comment character: XStormy16-Chars. (line 11) 26861* XStormy16 line comment character: XStormy16-Chars. (line 6) 26862* XStormy16 line separator: XStormy16-Chars. (line 14) 26863* XStormy16 machine directives: XStormy16 Directives. 26864 (line 6) 26865* XStormy16 pseudo-opcodes: XStormy16 Opcodes. (line 6) 26866* XStormy16 support: XSTORMY16-Dependent. 26867 (line 6) 26868* Xtensa architecture: Xtensa-Dependent. (line 6) 26869* Xtensa assembler syntax: Xtensa Syntax. (line 6) 26870* Xtensa directives: Xtensa Directives. (line 6) 26871* Xtensa opcode names: Xtensa Opcodes. (line 6) 26872* Xtensa register names: Xtensa Registers. (line 6) 26873* xword directive, SPARC: Sparc-Directives. (line 55) 26874* Z80 $: Z80-Chars. (line 15) 26875* Z80 ': Z80-Chars. (line 20) 26876* Z80 floating point: Z80 Floating Point. (line 6) 26877* Z80 line comment character: Z80-Chars. (line 6) 26878* Z80 line separator: Z80-Chars. (line 13) 26879* Z80 options: Z80 Options. (line 6) 26880* Z80 registers: Z80-Regs. (line 6) 26881* Z80 support: Z80-Dependent. (line 6) 26882* Z80 Syntax: Z80 Options. (line 40) 26883* Z80, case sensitivity: Z80-Case. (line 6) 26884* Z80, \: Z80-Chars. (line 18) 26885* Z80-only directives: Z80 Directives. (line 9) 26886* Z800 addressing modes: Z8000-Addressing. (line 6) 26887* Z8000 directives: Z8000 Directives. (line 6) 26888* Z8000 line comment character: Z8000-Chars. (line 6) 26889* Z8000 line separator: Z8000-Chars. (line 13) 26890* Z8000 opcode summary: Z8000 Opcodes. (line 6) 26891* Z8000 options: Z8000 Options. (line 6) 26892* Z8000 registers: Z8000-Regs. (line 6) 26893* Z8000 support: Z8000-Dependent. (line 6) 26894* zdaoff pseudo-op, V850: V850 Opcodes. (line 98) 26895* zero directive: Zero. (line 6) 26896* zero register, V850: V850-Regs. (line 7) 26897* zero-terminated strings: Asciz. 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