1/* tc-riscv.c -- RISC-V assembler 2 Copyright (C) 2011-2017 Free Software Foundation, Inc. 3 4 Contributed by Andrew Waterman (andrew@sifive.com). 5 Based on MIPS target. 6 7 This file is part of GAS. 8 9 GAS is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3, or (at your option) 12 any later version. 13 14 GAS is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with this program; see the file COPYING3. If not, 21 see <http://www.gnu.org/licenses/>. */ 22 23#include "as.h" 24#include "config.h" 25#include "subsegs.h" 26#include "safe-ctype.h" 27 28#include "itbl-ops.h" 29#include "dwarf2dbg.h" 30#include "dw2gencfi.h" 31#include "struc-symbol.h" 32 33#include "elf/riscv.h" 34#include "opcode/riscv.h" 35 36#include <stdint.h> 37 38/* Information about an instruction, including its format, operands 39 and fixups. */ 40struct riscv_cl_insn 41{ 42 /* The opcode's entry in riscv_opcodes. */ 43 const struct riscv_opcode *insn_mo; 44 45 /* The encoded instruction bits. */ 46 insn_t insn_opcode; 47 48 /* The frag that contains the instruction. */ 49 struct frag *frag; 50 51 /* The offset into FRAG of the first instruction byte. */ 52 long where; 53 54 /* The relocs associated with the instruction, if any. */ 55 fixS *fixp; 56}; 57 58#ifndef DEFAULT_ARCH 59#define DEFAULT_ARCH "riscv64" 60#endif 61 62static const char default_arch[] = DEFAULT_ARCH; 63 64static unsigned xlen = 0; /* width of an x-register */ 65static unsigned abi_xlen = 0; /* width of a pointer in the ABI */ 66 67#define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw") 68#define ADD32_INSN (xlen == 64 ? "addiw" : "addi") 69 70static unsigned elf_flags = 0; 71 72/* This is the set of options which the .option pseudo-op may modify. */ 73 74struct riscv_set_options 75{ 76 int pic; /* Generate position-independent code. */ 77 int rvc; /* Generate RVC code. */ 78 int relax; /* Emit relocs the linker is allowed to relax. */ 79}; 80 81static struct riscv_set_options riscv_opts = 82{ 83 0, /* pic */ 84 0, /* rvc */ 85 1, /* relax */ 86}; 87 88static void 89riscv_set_rvc (bfd_boolean rvc_value) 90{ 91 if (rvc_value) 92 elf_flags |= EF_RISCV_RVC; 93 94 riscv_opts.rvc = rvc_value; 95} 96 97struct riscv_subset 98{ 99 const char *name; 100 101 struct riscv_subset *next; 102}; 103 104static struct riscv_subset *riscv_subsets; 105 106static bfd_boolean 107riscv_subset_supports (const char *feature) 108{ 109 struct riscv_subset *s; 110 char *p; 111 unsigned xlen_required = strtoul (feature, &p, 10); 112 113 if (xlen_required && xlen != xlen_required) 114 return FALSE; 115 116 for (s = riscv_subsets; s != NULL; s = s->next) 117 if (strcasecmp (s->name, p) == 0) 118 return TRUE; 119 120 return FALSE; 121} 122 123static void 124riscv_clear_subsets (void) 125{ 126 while (riscv_subsets != NULL) 127 { 128 struct riscv_subset *next = riscv_subsets->next; 129 free ((void *) riscv_subsets->name); 130 free (riscv_subsets); 131 riscv_subsets = next; 132 } 133} 134 135static void 136riscv_add_subset (const char *subset) 137{ 138 struct riscv_subset *s = xmalloc (sizeof *s); 139 140 s->name = xstrdup (subset); 141 s->next = riscv_subsets; 142 riscv_subsets = s; 143} 144 145/* Set which ISA and extensions are available. */ 146 147static void 148riscv_set_arch (const char *s) 149{ 150 const char *all_subsets = "imafdc"; 151 const char *extension = NULL; 152 const char *p = s; 153 154 riscv_clear_subsets(); 155 156 if (strncmp (p, "rv32", 4) == 0) 157 { 158 xlen = 32; 159 p += 4; 160 } 161 else if (strncmp (p, "rv64", 4) == 0) 162 { 163 xlen = 64; 164 p += 4; 165 } 166 else 167 as_fatal ("-march=%s: ISA string must begin with rv32 or rv64", s); 168 169 switch (*p) 170 { 171 case 'i': 172 break; 173 174 case 'g': 175 p++; 176 for ( ; *all_subsets != 'c'; all_subsets++) 177 { 178 const char subset[] = {*all_subsets, '\0'}; 179 riscv_add_subset (subset); 180 } 181 break; 182 183 default: 184 as_fatal ("-march=%s: first ISA subset must be `i' or `g'", s); 185 } 186 187 while (*p) 188 { 189 if (*p == 'x') 190 { 191 char *subset = xstrdup (p), *q = subset; 192 193 while (*++q != '\0' && *q != '_') 194 ; 195 *q = '\0'; 196 197 if (extension) 198 as_fatal ("-march=%s: only one non-standard extension is supported" 199 " (found `%s' and `%s')", s, extension, subset); 200 extension = subset; 201 riscv_add_subset (subset); 202 p += strlen (subset); 203 free (subset); 204 } 205 else if (*p == '_') 206 p++; 207 else if ((all_subsets = strchr (all_subsets, *p)) != NULL) 208 { 209 const char subset[] = {*p, 0}; 210 riscv_add_subset (subset); 211 all_subsets++; 212 p++; 213 } 214 else 215 as_fatal ("-march=%s: unsupported ISA subset `%c'", s, *p); 216 } 217} 218 219/* Handle of the OPCODE hash table. */ 220static struct hash_control *op_hash = NULL; 221 222/* This array holds the chars that always start a comment. If the 223 pre-processor is disabled, these aren't very useful */ 224const char comment_chars[] = "#"; 225 226/* This array holds the chars that only start a comment at the beginning of 227 a line. If the line seems to have the form '# 123 filename' 228 .line and .file directives will appear in the pre-processed output */ 229/* Note that input_file.c hand checks for '#' at the beginning of the 230 first line of the input file. This is because the compiler outputs 231 #NO_APP at the beginning of its output. */ 232/* Also note that C style comments are always supported. */ 233const char line_comment_chars[] = "#"; 234 235/* This array holds machine specific line separator characters. */ 236const char line_separator_chars[] = ";"; 237 238/* Chars that can be used to separate mant from exp in floating point nums */ 239const char EXP_CHARS[] = "eE"; 240 241/* Chars that mean this number is a floating point constant */ 242/* As in 0f12.456 */ 243/* or 0d1.2345e12 */ 244const char FLT_CHARS[] = "rRsSfFdDxXpP"; 245 246/* Macros for encoding relaxation state for RVC branches and far jumps. */ 247#define RELAX_BRANCH_ENCODE(uncond, rvc, length) \ 248 ((relax_substateT) \ 249 (0xc0000000 \ 250 | ((uncond) ? 1 : 0) \ 251 | ((rvc) ? 2 : 0) \ 252 | ((length) << 2))) 253#define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) 254#define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF) 255#define RELAX_BRANCH_RVC(i) (((i) & 2) != 0) 256#define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0) 257 258/* Is the given value a sign-extended 32-bit value? */ 259#define IS_SEXT_32BIT_NUM(x) \ 260 (((x) &~ (offsetT) 0x7fffffff) == 0 \ 261 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) 262 263/* Is the given value a zero-extended 32-bit value? Or a negated one? */ 264#define IS_ZEXT_32BIT_NUM(x) \ 265 (((x) &~ (offsetT) 0xffffffff) == 0 \ 266 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) 267 268/* Change INSN's opcode so that the operand given by FIELD has value VALUE. 269 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */ 270#define INSERT_OPERAND(FIELD, INSN, VALUE) \ 271 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD) 272 273/* Determine if an instruction matches an opcode. */ 274#define OPCODE_MATCHES(OPCODE, OP) \ 275 (((OPCODE) & MASK_##OP) == MATCH_##OP) 276 277static char *expr_end; 278 279/* The default target format to use. */ 280 281const char * 282riscv_target_format (void) 283{ 284 return xlen == 64 ? "elf64-littleriscv" : "elf32-littleriscv"; 285} 286 287/* Return the length of instruction INSN. */ 288 289static inline unsigned int 290insn_length (const struct riscv_cl_insn *insn) 291{ 292 return riscv_insn_length (insn->insn_opcode); 293} 294 295/* Initialise INSN from opcode entry MO. Leave its position unspecified. */ 296 297static void 298create_insn (struct riscv_cl_insn *insn, const struct riscv_opcode *mo) 299{ 300 insn->insn_mo = mo; 301 insn->insn_opcode = mo->match; 302 insn->frag = NULL; 303 insn->where = 0; 304 insn->fixp = NULL; 305} 306 307/* Install INSN at the location specified by its "frag" and "where" fields. */ 308 309static void 310install_insn (const struct riscv_cl_insn *insn) 311{ 312 char *f = insn->frag->fr_literal + insn->where; 313 md_number_to_chars (f, insn->insn_opcode, insn_length (insn)); 314} 315 316/* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly 317 and install the opcode in the new location. */ 318 319static void 320move_insn (struct riscv_cl_insn *insn, fragS *frag, long where) 321{ 322 insn->frag = frag; 323 insn->where = where; 324 if (insn->fixp != NULL) 325 { 326 insn->fixp->fx_frag = frag; 327 insn->fixp->fx_where = where; 328 } 329 install_insn (insn); 330} 331 332/* Add INSN to the end of the output. */ 333 334static void 335add_fixed_insn (struct riscv_cl_insn *insn) 336{ 337 char *f = frag_more (insn_length (insn)); 338 move_insn (insn, frag_now, f - frag_now->fr_literal); 339} 340 341static void 342add_relaxed_insn (struct riscv_cl_insn *insn, int max_chars, int var, 343 relax_substateT subtype, symbolS *symbol, offsetT offset) 344{ 345 frag_grow (max_chars); 346 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); 347 frag_var (rs_machine_dependent, max_chars, var, 348 subtype, symbol, offset, NULL); 349} 350 351/* Compute the length of a branch sequence, and adjust the stored length 352 accordingly. If FRAGP is NULL, the worst-case length is returned. */ 353 354static unsigned 355relaxed_branch_length (fragS *fragp, asection *sec, int update) 356{ 357 int jump, rvc, length = 8; 358 359 if (!fragp) 360 return length; 361 362 jump = RELAX_BRANCH_UNCOND (fragp->fr_subtype); 363 rvc = RELAX_BRANCH_RVC (fragp->fr_subtype); 364 length = RELAX_BRANCH_LENGTH (fragp->fr_subtype); 365 366 /* Assume jumps are in range; the linker will catch any that aren't. */ 367 length = jump ? 4 : 8; 368 369 if (fragp->fr_symbol != NULL 370 && S_IS_DEFINED (fragp->fr_symbol) 371 && !S_IS_WEAK (fragp->fr_symbol) 372 && sec == S_GET_SEGMENT (fragp->fr_symbol)) 373 { 374 offsetT val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; 375 bfd_vma rvc_range = jump ? RVC_JUMP_REACH : RVC_BRANCH_REACH; 376 val -= fragp->fr_address + fragp->fr_fix; 377 378 if (rvc && (bfd_vma)(val + rvc_range/2) < rvc_range) 379 length = 2; 380 else if ((bfd_vma)(val + RISCV_BRANCH_REACH/2) < RISCV_BRANCH_REACH) 381 length = 4; 382 else if (!jump && rvc) 383 length = 6; 384 } 385 386 if (update) 387 fragp->fr_subtype = RELAX_BRANCH_ENCODE (jump, rvc, length); 388 389 return length; 390} 391 392struct regname 393{ 394 const char *name; 395 unsigned int num; 396}; 397 398enum reg_class 399{ 400 RCLASS_GPR, 401 RCLASS_FPR, 402 RCLASS_CSR, 403 RCLASS_MAX 404}; 405 406static struct hash_control *reg_names_hash = NULL; 407 408#define ENCODE_REG_HASH(cls, n) \ 409 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1)) 410#define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX) 411#define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX) 412 413static void 414hash_reg_name (enum reg_class class, const char *name, unsigned n) 415{ 416 void *hash = ENCODE_REG_HASH (class, n); 417 const char *retval = hash_insert (reg_names_hash, name, hash); 418 419 if (retval != NULL) 420 as_fatal (_("internal error: can't hash `%s': %s"), name, retval); 421} 422 423static void 424hash_reg_names (enum reg_class class, const char * const names[], unsigned n) 425{ 426 unsigned i; 427 428 for (i = 0; i < n; i++) 429 hash_reg_name (class, names[i], i); 430} 431 432static unsigned int 433reg_lookup_internal (const char *s, enum reg_class class) 434{ 435 struct regname *r = (struct regname *) hash_find (reg_names_hash, s); 436 437 if (r == NULL || DECODE_REG_CLASS (r) != class) 438 return -1; 439 return DECODE_REG_NUM (r); 440} 441 442static bfd_boolean 443reg_lookup (char **s, enum reg_class class, unsigned int *regnop) 444{ 445 char *e; 446 char save_c; 447 int reg = -1; 448 449 /* Find end of name. */ 450 e = *s; 451 if (is_name_beginner (*e)) 452 ++e; 453 while (is_part_of_name (*e)) 454 ++e; 455 456 /* Terminate name. */ 457 save_c = *e; 458 *e = '\0'; 459 460 /* Look for the register. Advance to next token if one was recognized. */ 461 if ((reg = reg_lookup_internal (*s, class)) >= 0) 462 *s = e; 463 464 *e = save_c; 465 if (regnop) 466 *regnop = reg; 467 return reg >= 0; 468} 469 470static bfd_boolean 471arg_lookup (char **s, const char *const *array, size_t size, unsigned *regnop) 472{ 473 const char *p = strchr (*s, ','); 474 size_t i, len = p ? (size_t)(p - *s) : strlen (*s); 475 476 for (i = 0; i < size; i++) 477 if (array[i] != NULL && strncmp (array[i], *s, len) == 0) 478 { 479 *regnop = i; 480 *s += len; 481 return TRUE; 482 } 483 484 return FALSE; 485} 486 487/* For consistency checking, verify that all bits are specified either 488 by the match/mask part of the instruction definition, or by the 489 operand list. */ 490static bfd_boolean 491validate_riscv_insn (const struct riscv_opcode *opc) 492{ 493 const char *p = opc->args; 494 char c; 495 insn_t used_bits = opc->mask; 496 int insn_width = 8 * riscv_insn_length (opc->match); 497 insn_t required_bits = ~0ULL >> (64 - insn_width); 498 499 if ((used_bits & opc->match) != (opc->match & required_bits)) 500 { 501 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"), 502 opc->name, opc->args); 503 return FALSE; 504 } 505 506#define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift))) 507 while (*p) 508 switch (c = *p++) 509 { 510 case 'C': /* RVC */ 511 switch (c = *p++) 512 { 513 case 'a': used_bits |= ENCODE_RVC_J_IMM (-1U); break; 514 case 'c': break; /* RS1, constrained to equal sp */ 515 case 'i': used_bits |= ENCODE_RVC_SIMM3(-1U); break; 516 case 'j': used_bits |= ENCODE_RVC_IMM (-1U); break; 517 case 'o': used_bits |= ENCODE_RVC_IMM (-1U); break; 518 case 'k': used_bits |= ENCODE_RVC_LW_IMM (-1U); break; 519 case 'l': used_bits |= ENCODE_RVC_LD_IMM (-1U); break; 520 case 'm': used_bits |= ENCODE_RVC_LWSP_IMM (-1U); break; 521 case 'n': used_bits |= ENCODE_RVC_LDSP_IMM (-1U); break; 522 case 'p': used_bits |= ENCODE_RVC_B_IMM (-1U); break; 523 case 's': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break; 524 case 't': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break; 525 case 'u': used_bits |= ENCODE_RVC_IMM (-1U); break; 526 case 'v': used_bits |= ENCODE_RVC_IMM (-1U); break; 527 case 'w': break; /* RS1S, constrained to equal RD */ 528 case 'x': break; /* RS2S, constrained to equal RD */ 529 case 'K': used_bits |= ENCODE_RVC_ADDI4SPN_IMM (-1U); break; 530 case 'L': used_bits |= ENCODE_RVC_ADDI16SP_IMM (-1U); break; 531 case 'M': used_bits |= ENCODE_RVC_SWSP_IMM (-1U); break; 532 case 'N': used_bits |= ENCODE_RVC_SDSP_IMM (-1U); break; 533 case 'U': break; /* RS1, constrained to equal RD */ 534 case 'V': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break; 535 case '<': used_bits |= ENCODE_RVC_IMM (-1U); break; 536 case '>': used_bits |= ENCODE_RVC_IMM (-1U); break; 537 case 'T': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break; 538 case 'D': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break; 539 default: 540 as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"), 541 c, opc->name, opc->args); 542 return FALSE; 543 } 544 break; 545 case ',': break; 546 case '(': break; 547 case ')': break; 548 case '<': USE_BITS (OP_MASK_SHAMTW, OP_SH_SHAMTW); break; 549 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; 550 case 'A': break; 551 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); break; 552 case 'Z': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break; 553 case 'E': USE_BITS (OP_MASK_CSR, OP_SH_CSR); break; 554 case 'I': break; 555 case 'R': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break; 556 case 'S': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break; 557 case 'U': USE_BITS (OP_MASK_RS1, OP_SH_RS1); /* fallthru */ 558 case 'T': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break; 559 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; 560 case 'm': USE_BITS (OP_MASK_RM, OP_SH_RM); break; 561 case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break; 562 case 't': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break; 563 case 'P': USE_BITS (OP_MASK_PRED, OP_SH_PRED); break; 564 case 'Q': USE_BITS (OP_MASK_SUCC, OP_SH_SUCC); break; 565 case 'o': 566 case 'j': used_bits |= ENCODE_ITYPE_IMM (-1U); break; 567 case 'a': used_bits |= ENCODE_UJTYPE_IMM (-1U); break; 568 case 'p': used_bits |= ENCODE_SBTYPE_IMM (-1U); break; 569 case 'q': used_bits |= ENCODE_STYPE_IMM (-1U); break; 570 case 'u': used_bits |= ENCODE_UTYPE_IMM (-1U); break; 571 case '[': break; 572 case ']': break; 573 case '0': break; 574 default: 575 as_bad (_("internal: bad RISC-V opcode " 576 "(unknown operand type `%c'): %s %s"), 577 c, opc->name, opc->args); 578 return FALSE; 579 } 580#undef USE_BITS 581 if (used_bits != required_bits) 582 { 583 as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"), 584 ~(unsigned long)(used_bits & required_bits), 585 opc->name, opc->args); 586 return FALSE; 587 } 588 return TRUE; 589} 590 591struct percent_op_match 592{ 593 const char *str; 594 bfd_reloc_code_real_type reloc; 595}; 596 597/* This function is called once, at assembler startup time. It should set up 598 all the tables, etc. that the MD part of the assembler will need. */ 599 600void 601md_begin (void) 602{ 603 int i = 0; 604 unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32; 605 606 if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach)) 607 as_warn (_("Could not set architecture and machine")); 608 609 op_hash = hash_new (); 610 611 while (riscv_opcodes[i].name) 612 { 613 const char *name = riscv_opcodes[i].name; 614 const char *hash_error = 615 hash_insert (op_hash, name, (void *) &riscv_opcodes[i]); 616 617 if (hash_error) 618 { 619 fprintf (stderr, _("internal error: can't hash `%s': %s\n"), 620 riscv_opcodes[i].name, hash_error); 621 /* Probably a memory allocation problem? Give up now. */ 622 as_fatal (_("Broken assembler. No assembly attempted.")); 623 } 624 625 do 626 { 627 if (riscv_opcodes[i].pinfo != INSN_MACRO) 628 { 629 if (!validate_riscv_insn (&riscv_opcodes[i])) 630 as_fatal (_("Broken assembler. No assembly attempted.")); 631 } 632 ++i; 633 } 634 while (riscv_opcodes[i].name && !strcmp (riscv_opcodes[i].name, name)); 635 } 636 637 reg_names_hash = hash_new (); 638 hash_reg_names (RCLASS_GPR, riscv_gpr_names_numeric, NGPR); 639 hash_reg_names (RCLASS_GPR, riscv_gpr_names_abi, NGPR); 640 hash_reg_names (RCLASS_FPR, riscv_fpr_names_numeric, NFPR); 641 hash_reg_names (RCLASS_FPR, riscv_fpr_names_abi, NFPR); 642 643#define DECLARE_CSR(name, num) hash_reg_name (RCLASS_CSR, #name, num); 644#include "opcode/riscv-opc.h" 645#undef DECLARE_CSR 646 647 /* Set the default alignment for the text section. */ 648 record_alignment (text_section, riscv_opts.rvc ? 1 : 2); 649} 650 651static insn_t 652riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type, bfd_vma value) 653{ 654 switch (reloc_type) 655 { 656 case BFD_RELOC_32: 657 return value; 658 659 case BFD_RELOC_RISCV_HI20: 660 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value)); 661 662 case BFD_RELOC_RISCV_LO12_S: 663 return ENCODE_STYPE_IMM (value); 664 665 case BFD_RELOC_RISCV_LO12_I: 666 return ENCODE_ITYPE_IMM (value); 667 668 default: 669 abort (); 670 } 671} 672 673/* Output an instruction. IP is the instruction information. 674 ADDRESS_EXPR is an operand of the instruction to be used with 675 RELOC_TYPE. */ 676 677static void 678append_insn (struct riscv_cl_insn *ip, expressionS *address_expr, 679 bfd_reloc_code_real_type reloc_type) 680{ 681 dwarf2_emit_insn (0); 682 683 if (reloc_type != BFD_RELOC_UNUSED) 684 { 685 reloc_howto_type *howto; 686 687 gas_assert (address_expr); 688 if (reloc_type == BFD_RELOC_12_PCREL 689 || reloc_type == BFD_RELOC_RISCV_JMP) 690 { 691 int j = reloc_type == BFD_RELOC_RISCV_JMP; 692 int best_case = riscv_insn_length (ip->insn_opcode); 693 unsigned worst_case = relaxed_branch_length (NULL, NULL, 0); 694 add_relaxed_insn (ip, worst_case, best_case, 695 RELAX_BRANCH_ENCODE (j, best_case == 2, worst_case), 696 address_expr->X_add_symbol, 697 address_expr->X_add_number); 698 return; 699 } 700 else 701 { 702 howto = bfd_reloc_type_lookup (stdoutput, reloc_type); 703 if (howto == NULL) 704 as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type); 705 706 ip->fixp = fix_new_exp (ip->frag, ip->where, 707 bfd_get_reloc_size (howto), 708 address_expr, FALSE, reloc_type); 709 710 ip->fixp->fx_tcbit = riscv_opts.relax; 711 } 712 } 713 714 add_fixed_insn (ip); 715 install_insn (ip); 716} 717 718/* Build an instruction created by a macro expansion. This is passed 719 a pointer to the count of instructions created so far, an 720 expression, the name of the instruction to build, an operand format 721 string, and corresponding arguments. */ 722 723static void 724macro_build (expressionS *ep, const char *name, const char *fmt, ...) 725{ 726 const struct riscv_opcode *mo; 727 struct riscv_cl_insn insn; 728 bfd_reloc_code_real_type r; 729 va_list args; 730 731 va_start (args, fmt); 732 733 r = BFD_RELOC_UNUSED; 734 mo = (struct riscv_opcode *) hash_find (op_hash, name); 735 gas_assert (mo); 736 737 /* Find a non-RVC variant of the instruction. append_insn will compress 738 it if possible. */ 739 while (riscv_insn_length (mo->match) < 4) 740 mo++; 741 gas_assert (strcmp (name, mo->name) == 0); 742 743 create_insn (&insn, mo); 744 for (;;) 745 { 746 switch (*fmt++) 747 { 748 case 'd': 749 INSERT_OPERAND (RD, insn, va_arg (args, int)); 750 continue; 751 752 case 's': 753 INSERT_OPERAND (RS1, insn, va_arg (args, int)); 754 continue; 755 756 case 't': 757 INSERT_OPERAND (RS2, insn, va_arg (args, int)); 758 continue; 759 760 case '>': 761 INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); 762 continue; 763 764 case 'j': 765 case 'u': 766 case 'q': 767 gas_assert (ep != NULL); 768 r = va_arg (args, int); 769 continue; 770 771 case '\0': 772 break; 773 case ',': 774 continue; 775 default: 776 as_fatal (_("internal error: invalid macro")); 777 } 778 break; 779 } 780 va_end (args); 781 gas_assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); 782 783 append_insn (&insn, ep, r); 784} 785 786/* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits 787 unset. */ 788static void 789normalize_constant_expr (expressionS *ex) 790{ 791 if (xlen > 32) 792 return; 793 if ((ex->X_op == O_constant || ex->X_op == O_symbol) 794 && IS_ZEXT_32BIT_NUM (ex->X_add_number)) 795 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) 796 - 0x80000000); 797} 798 799/* Fail if an expression is not a constant. */ 800 801static void 802check_absolute_expr (struct riscv_cl_insn *ip, expressionS *ex) 803{ 804 if (ex->X_op == O_big) 805 as_bad (_("unsupported large constant")); 806 else if (ex->X_op != O_constant) 807 as_bad (_("Instruction %s requires absolute expression"), 808 ip->insn_mo->name); 809 normalize_constant_expr (ex); 810} 811 812static symbolS * 813make_internal_label (void) 814{ 815 return (symbolS *) local_symbol_make (FAKE_LABEL_NAME, now_seg, 816 (valueT) frag_now_fix (), frag_now); 817} 818 819/* Load an entry from the GOT. */ 820static void 821pcrel_access (int destreg, int tempreg, expressionS *ep, 822 const char *lo_insn, const char *lo_pattern, 823 bfd_reloc_code_real_type hi_reloc, 824 bfd_reloc_code_real_type lo_reloc) 825{ 826 expressionS ep2; 827 ep2.X_op = O_symbol; 828 ep2.X_add_symbol = make_internal_label (); 829 ep2.X_add_number = 0; 830 831 macro_build (ep, "auipc", "d,u", tempreg, hi_reloc); 832 macro_build (&ep2, lo_insn, lo_pattern, destreg, tempreg, lo_reloc); 833} 834 835static void 836pcrel_load (int destreg, int tempreg, expressionS *ep, const char *lo_insn, 837 bfd_reloc_code_real_type hi_reloc, 838 bfd_reloc_code_real_type lo_reloc) 839{ 840 pcrel_access (destreg, tempreg, ep, lo_insn, "d,s,j", hi_reloc, lo_reloc); 841} 842 843static void 844pcrel_store (int srcreg, int tempreg, expressionS *ep, const char *lo_insn, 845 bfd_reloc_code_real_type hi_reloc, 846 bfd_reloc_code_real_type lo_reloc) 847{ 848 pcrel_access (srcreg, tempreg, ep, lo_insn, "t,s,q", hi_reloc, lo_reloc); 849} 850 851/* PC-relative function call using AUIPC/JALR, relaxed to JAL. */ 852static void 853riscv_call (int destreg, int tempreg, expressionS *ep, 854 bfd_reloc_code_real_type reloc) 855{ 856 macro_build (ep, "auipc", "d,u", tempreg, reloc); 857 macro_build (NULL, "jalr", "d,s", destreg, tempreg); 858} 859 860/* Load an integer constant into a register. */ 861 862static void 863load_const (int reg, expressionS *ep) 864{ 865 int shift = RISCV_IMM_BITS; 866 expressionS upper = *ep, lower = *ep; 867 lower.X_add_number = (int32_t) ep->X_add_number << (32-shift) >> (32-shift); 868 upper.X_add_number -= lower.X_add_number; 869 870 if (ep->X_op != O_constant) 871 { 872 as_bad (_("unsupported large constant")); 873 return; 874 } 875 876 if (xlen > 32 && !IS_SEXT_32BIT_NUM (ep->X_add_number)) 877 { 878 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */ 879 while (((upper.X_add_number >> shift) & 1) == 0) 880 shift++; 881 882 upper.X_add_number = (int64_t) upper.X_add_number >> shift; 883 load_const (reg, &upper); 884 885 macro_build (NULL, "slli", "d,s,>", reg, reg, shift); 886 if (lower.X_add_number != 0) 887 macro_build (&lower, "addi", "d,s,j", reg, reg, BFD_RELOC_RISCV_LO12_I); 888 } 889 else 890 { 891 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */ 892 int hi_reg = 0; 893 894 if (upper.X_add_number != 0) 895 { 896 macro_build (ep, "lui", "d,u", reg, BFD_RELOC_RISCV_HI20); 897 hi_reg = reg; 898 } 899 900 if (lower.X_add_number != 0 || hi_reg == 0) 901 macro_build (ep, ADD32_INSN, "d,s,j", reg, hi_reg, 902 BFD_RELOC_RISCV_LO12_I); 903 } 904} 905 906/* Expand RISC-V assembly macros into one or more instructions. */ 907static void 908macro (struct riscv_cl_insn *ip, expressionS *imm_expr, 909 bfd_reloc_code_real_type *imm_reloc) 910{ 911 int rd = (ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD; 912 int rs1 = (ip->insn_opcode >> OP_SH_RS1) & OP_MASK_RS1; 913 int rs2 = (ip->insn_opcode >> OP_SH_RS2) & OP_MASK_RS2; 914 int mask = ip->insn_mo->mask; 915 916 switch (mask) 917 { 918 case M_LI: 919 load_const (rd, imm_expr); 920 break; 921 922 case M_LA: 923 case M_LLA: 924 /* Load the address of a symbol into a register. */ 925 if (!IS_SEXT_32BIT_NUM (imm_expr->X_add_number)) 926 as_bad (_("offset too large")); 927 928 if (imm_expr->X_op == O_constant) 929 load_const (rd, imm_expr); 930 else if (riscv_opts.pic && mask == M_LA) /* Global PIC symbol */ 931 pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN, 932 BFD_RELOC_RISCV_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); 933 else /* Local PIC symbol, or any non-PIC symbol */ 934 pcrel_load (rd, rd, imm_expr, "addi", 935 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); 936 break; 937 938 case M_LA_TLS_GD: 939 pcrel_load (rd, rd, imm_expr, "addi", 940 BFD_RELOC_RISCV_TLS_GD_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); 941 break; 942 943 case M_LA_TLS_IE: 944 pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN, 945 BFD_RELOC_RISCV_TLS_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); 946 break; 947 948 case M_LB: 949 pcrel_load (rd, rd, imm_expr, "lb", 950 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); 951 break; 952 953 case M_LBU: 954 pcrel_load (rd, rd, imm_expr, "lbu", 955 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); 956 break; 957 958 case M_LH: 959 pcrel_load (rd, rd, imm_expr, "lh", 960 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); 961 break; 962 963 case M_LHU: 964 pcrel_load (rd, rd, imm_expr, "lhu", 965 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); 966 break; 967 968 case M_LW: 969 pcrel_load (rd, rd, imm_expr, "lw", 970 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); 971 break; 972 973 case M_LWU: 974 pcrel_load (rd, rd, imm_expr, "lwu", 975 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); 976 break; 977 978 case M_LD: 979 pcrel_load (rd, rd, imm_expr, "ld", 980 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); 981 break; 982 983 case M_FLW: 984 pcrel_load (rd, rs1, imm_expr, "flw", 985 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); 986 break; 987 988 case M_FLD: 989 pcrel_load (rd, rs1, imm_expr, "fld", 990 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); 991 break; 992 993 case M_SB: 994 pcrel_store (rs2, rs1, imm_expr, "sb", 995 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); 996 break; 997 998 case M_SH: 999 pcrel_store (rs2, rs1, imm_expr, "sh", 1000 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); 1001 break; 1002 1003 case M_SW: 1004 pcrel_store (rs2, rs1, imm_expr, "sw", 1005 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); 1006 break; 1007 1008 case M_SD: 1009 pcrel_store (rs2, rs1, imm_expr, "sd", 1010 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); 1011 break; 1012 1013 case M_FSW: 1014 pcrel_store (rs2, rs1, imm_expr, "fsw", 1015 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); 1016 break; 1017 1018 case M_FSD: 1019 pcrel_store (rs2, rs1, imm_expr, "fsd", 1020 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); 1021 break; 1022 1023 case M_CALL: 1024 riscv_call (rd, rs1, imm_expr, *imm_reloc); 1025 break; 1026 1027 default: 1028 as_bad (_("Macro %s not implemented"), ip->insn_mo->name); 1029 break; 1030 } 1031} 1032 1033static const struct percent_op_match percent_op_utype[] = 1034{ 1035 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20}, 1036 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20}, 1037 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20}, 1038 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20}, 1039 {"%hi", BFD_RELOC_RISCV_HI20}, 1040 {0, 0} 1041}; 1042 1043static const struct percent_op_match percent_op_itype[] = 1044{ 1045 {"%lo", BFD_RELOC_RISCV_LO12_I}, 1046 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I}, 1047 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I}, 1048 {0, 0} 1049}; 1050 1051static const struct percent_op_match percent_op_stype[] = 1052{ 1053 {"%lo", BFD_RELOC_RISCV_LO12_S}, 1054 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S}, 1055 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S}, 1056 {0, 0} 1057}; 1058 1059static const struct percent_op_match percent_op_rtype[] = 1060{ 1061 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD}, 1062 {0, 0} 1063}; 1064 1065/* Return true if *STR points to a relocation operator. When returning true, 1066 move *STR over the operator and store its relocation code in *RELOC. 1067 Leave both *STR and *RELOC alone when returning false. */ 1068 1069static bfd_boolean 1070parse_relocation (char **str, bfd_reloc_code_real_type *reloc, 1071 const struct percent_op_match *percent_op) 1072{ 1073 for ( ; percent_op->str; percent_op++) 1074 if (strncasecmp (*str, percent_op->str, strlen (percent_op->str)) == 0) 1075 { 1076 int len = strlen (percent_op->str); 1077 1078 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') 1079 continue; 1080 1081 *str += strlen (percent_op->str); 1082 *reloc = percent_op->reloc; 1083 1084 /* Check whether the output BFD supports this relocation. 1085 If not, issue an error and fall back on something safe. */ 1086 if (*reloc != BFD_RELOC_UNUSED 1087 && !bfd_reloc_type_lookup (stdoutput, *reloc)) 1088 { 1089 as_bad ("relocation %s isn't supported by the current ABI", 1090 percent_op->str); 1091 *reloc = BFD_RELOC_UNUSED; 1092 } 1093 return TRUE; 1094 } 1095 return FALSE; 1096} 1097 1098static void 1099my_getExpression (expressionS *ep, char *str) 1100{ 1101 char *save_in; 1102 1103 save_in = input_line_pointer; 1104 input_line_pointer = str; 1105 expression (ep); 1106 expr_end = input_line_pointer; 1107 input_line_pointer = save_in; 1108} 1109 1110/* Parse string STR as a 16-bit relocatable operand. Store the 1111 expression in *EP and the relocation, if any, in RELOC. 1112 Return the number of relocation operators used (0 or 1). 1113 1114 On exit, EXPR_END points to the first character after the expression. */ 1115 1116static size_t 1117my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, 1118 char *str, const struct percent_op_match *percent_op) 1119{ 1120 size_t reloc_index; 1121 unsigned crux_depth, str_depth, regno; 1122 char *crux; 1123 1124 /* First, check for integer registers. */ 1125 if (reg_lookup (&str, RCLASS_GPR, ®no)) 1126 { 1127 ep->X_op = O_register; 1128 ep->X_add_number = regno; 1129 return 0; 1130 } 1131 1132 /* Search for the start of the main expression. 1133 End the loop with CRUX pointing to the start 1134 of the main expression and with CRUX_DEPTH containing the number 1135 of open brackets at that point. */ 1136 reloc_index = -1; 1137 str_depth = 0; 1138 do 1139 { 1140 reloc_index++; 1141 crux = str; 1142 crux_depth = str_depth; 1143 1144 /* Skip over whitespace and brackets, keeping count of the number 1145 of brackets. */ 1146 while (*str == ' ' || *str == '\t' || *str == '(') 1147 if (*str++ == '(') 1148 str_depth++; 1149 } 1150 while (*str == '%' 1151 && reloc_index < 1 1152 && parse_relocation (&str, reloc, percent_op)); 1153 1154 my_getExpression (ep, crux); 1155 str = expr_end; 1156 1157 /* Match every open bracket. */ 1158 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) 1159 if (*str++ == ')') 1160 crux_depth--; 1161 1162 if (crux_depth > 0) 1163 as_bad ("unclosed '('"); 1164 1165 expr_end = str; 1166 1167 return reloc_index; 1168} 1169 1170/* This routine assembles an instruction into its binary format. As a 1171 side effect, it sets the global variable imm_reloc to the type of 1172 relocation to do if one of the operands is an address expression. */ 1173 1174static const char * 1175riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, 1176 bfd_reloc_code_real_type *imm_reloc) 1177{ 1178 char *s; 1179 const char *args; 1180 char c = 0; 1181 struct riscv_opcode *insn; 1182 char *argsStart; 1183 unsigned int regno; 1184 char save_c = 0; 1185 int argnum; 1186 const struct percent_op_match *p; 1187 const char *error = "unrecognized opcode"; 1188 1189 /* Parse the name of the instruction. Terminate the string if whitespace 1190 is found so that hash_find only sees the name part of the string. */ 1191 for (s = str; *s != '\0'; ++s) 1192 if (ISSPACE (*s)) 1193 { 1194 save_c = *s; 1195 *s++ = '\0'; 1196 break; 1197 } 1198 1199 insn = (struct riscv_opcode *) hash_find (op_hash, str); 1200 1201 argsStart = s; 1202 for ( ; insn && insn->name && strcmp (insn->name, str) == 0; insn++) 1203 { 1204 if (!riscv_subset_supports (insn->subset)) 1205 continue; 1206 1207 create_insn (ip, insn); 1208 argnum = 1; 1209 1210 imm_expr->X_op = O_absent; 1211 *imm_reloc = BFD_RELOC_UNUSED; 1212 p = percent_op_itype; 1213 1214 for (args = insn->args;; ++args) 1215 { 1216 s += strspn (s, " \t"); 1217 switch (*args) 1218 { 1219 case '\0': /* End of args. */ 1220 if (insn->pinfo != INSN_MACRO) 1221 { 1222 if (!insn->match_func (insn, ip->insn_opcode)) 1223 break; 1224 if (riscv_insn_length (insn->match) == 2 && !riscv_opts.rvc) 1225 break; 1226 } 1227 if (*s != '\0') 1228 break; 1229 /* Successful assembly. */ 1230 error = NULL; 1231 goto out; 1232 1233 case 'C': /* RVC */ 1234 switch (*++args) 1235 { 1236 case 's': /* RS1 x8-x15 */ 1237 if (!reg_lookup (&s, RCLASS_GPR, ®no) 1238 || !(regno >= 8 && regno <= 15)) 1239 break; 1240 INSERT_OPERAND (CRS1S, *ip, regno % 8); 1241 continue; 1242 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */ 1243 if (!reg_lookup (&s, RCLASS_GPR, ®no) 1244 || EXTRACT_OPERAND (CRS1S, ip->insn_opcode) + 8 != regno) 1245 break; 1246 continue; 1247 case 't': /* RS2 x8-x15 */ 1248 if (!reg_lookup (&s, RCLASS_GPR, ®no) 1249 || !(regno >= 8 && regno <= 15)) 1250 break; 1251 INSERT_OPERAND (CRS2S, *ip, regno % 8); 1252 continue; 1253 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */ 1254 if (!reg_lookup (&s, RCLASS_GPR, ®no) 1255 || EXTRACT_OPERAND (CRS2S, ip->insn_opcode) + 8 != regno) 1256 break; 1257 continue; 1258 case 'U': /* RS1, constrained to equal RD. */ 1259 if (!reg_lookup (&s, RCLASS_GPR, ®no) 1260 || EXTRACT_OPERAND (RD, ip->insn_opcode) != regno) 1261 break; 1262 continue; 1263 case 'V': /* RS2 */ 1264 if (!reg_lookup (&s, RCLASS_GPR, ®no)) 1265 break; 1266 INSERT_OPERAND (CRS2, *ip, regno); 1267 continue; 1268 case 'c': /* RS1, constrained to equal sp. */ 1269 if (!reg_lookup (&s, RCLASS_GPR, ®no) 1270 || regno != X_SP) 1271 break; 1272 continue; 1273 case '>': 1274 if (my_getSmallExpression (imm_expr, imm_reloc, s, p) 1275 || imm_expr->X_op != O_constant 1276 || imm_expr->X_add_number <= 0 1277 || imm_expr->X_add_number >= 64) 1278 break; 1279 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number); 1280rvc_imm_done: 1281 s = expr_end; 1282 imm_expr->X_op = O_absent; 1283 continue; 1284 case '<': 1285 if (my_getSmallExpression (imm_expr, imm_reloc, s, p) 1286 || imm_expr->X_op != O_constant 1287 || !VALID_RVC_IMM (imm_expr->X_add_number) 1288 || imm_expr->X_add_number <= 0 1289 || imm_expr->X_add_number >= 32) 1290 break; 1291 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number); 1292 goto rvc_imm_done; 1293 case 'i': 1294 if (my_getSmallExpression (imm_expr, imm_reloc, s, p) 1295 || imm_expr->X_op != O_constant 1296 || imm_expr->X_add_number == 0 1297 || !VALID_RVC_SIMM3 (imm_expr->X_add_number)) 1298 break; 1299 ip->insn_opcode |= ENCODE_RVC_SIMM3 (imm_expr->X_add_number); 1300 goto rvc_imm_done; 1301 case 'j': 1302 if (my_getSmallExpression (imm_expr, imm_reloc, s, p) 1303 || imm_expr->X_op != O_constant 1304 || imm_expr->X_add_number == 0 1305 || !VALID_RVC_IMM (imm_expr->X_add_number)) 1306 break; 1307 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number); 1308 goto rvc_imm_done; 1309 case 'k': 1310 if (my_getSmallExpression (imm_expr, imm_reloc, s, p) 1311 || imm_expr->X_op != O_constant 1312 || !VALID_RVC_LW_IMM (imm_expr->X_add_number)) 1313 break; 1314 ip->insn_opcode |= ENCODE_RVC_LW_IMM (imm_expr->X_add_number); 1315 goto rvc_imm_done; 1316 case 'l': 1317 if (my_getSmallExpression (imm_expr, imm_reloc, s, p) 1318 || imm_expr->X_op != O_constant 1319 || !VALID_RVC_LD_IMM (imm_expr->X_add_number)) 1320 break; 1321 ip->insn_opcode |= ENCODE_RVC_LD_IMM (imm_expr->X_add_number); 1322 goto rvc_imm_done; 1323 case 'm': 1324 if (my_getSmallExpression (imm_expr, imm_reloc, s, p) 1325 || imm_expr->X_op != O_constant 1326 || !VALID_RVC_LWSP_IMM (imm_expr->X_add_number)) 1327 break; 1328 ip->insn_opcode |= 1329 ENCODE_RVC_LWSP_IMM (imm_expr->X_add_number); 1330 goto rvc_imm_done; 1331 case 'n': 1332 if (my_getSmallExpression (imm_expr, imm_reloc, s, p) 1333 || imm_expr->X_op != O_constant 1334 || !VALID_RVC_LDSP_IMM (imm_expr->X_add_number)) 1335 break; 1336 ip->insn_opcode |= 1337 ENCODE_RVC_LDSP_IMM (imm_expr->X_add_number); 1338 goto rvc_imm_done; 1339 case 'o': 1340 if (my_getSmallExpression (imm_expr, imm_reloc, s, p) 1341 || imm_expr->X_op != O_constant 1342 || !VALID_RVC_IMM (imm_expr->X_add_number)) 1343 break; 1344 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number); 1345 goto rvc_imm_done; 1346 case 'K': 1347 if (my_getSmallExpression (imm_expr, imm_reloc, s, p) 1348 || imm_expr->X_op != O_constant 1349 || !VALID_RVC_ADDI4SPN_IMM (imm_expr->X_add_number) 1350 || imm_expr->X_add_number == 0) 1351 break; 1352 ip->insn_opcode |= 1353 ENCODE_RVC_ADDI4SPN_IMM (imm_expr->X_add_number); 1354 goto rvc_imm_done; 1355 case 'L': 1356 if (my_getSmallExpression (imm_expr, imm_reloc, s, p) 1357 || imm_expr->X_op != O_constant 1358 || !VALID_RVC_ADDI16SP_IMM (imm_expr->X_add_number) 1359 || imm_expr->X_add_number == 0) 1360 break; 1361 ip->insn_opcode |= 1362 ENCODE_RVC_ADDI16SP_IMM (imm_expr->X_add_number); 1363 goto rvc_imm_done; 1364 case 'M': 1365 if (my_getSmallExpression (imm_expr, imm_reloc, s, p) 1366 || imm_expr->X_op != O_constant 1367 || !VALID_RVC_SWSP_IMM (imm_expr->X_add_number)) 1368 break; 1369 ip->insn_opcode |= 1370 ENCODE_RVC_SWSP_IMM (imm_expr->X_add_number); 1371 goto rvc_imm_done; 1372 case 'N': 1373 if (my_getSmallExpression (imm_expr, imm_reloc, s, p) 1374 || imm_expr->X_op != O_constant 1375 || !VALID_RVC_SDSP_IMM (imm_expr->X_add_number)) 1376 break; 1377 ip->insn_opcode |= 1378 ENCODE_RVC_SDSP_IMM (imm_expr->X_add_number); 1379 goto rvc_imm_done; 1380 case 'u': 1381 p = percent_op_utype; 1382 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)) 1383 break; 1384rvc_lui: 1385 if (imm_expr->X_op != O_constant 1386 || imm_expr->X_add_number <= 0 1387 || imm_expr->X_add_number >= RISCV_BIGIMM_REACH 1388 || (imm_expr->X_add_number >= RISCV_RVC_IMM_REACH / 2 1389 && (imm_expr->X_add_number < 1390 RISCV_BIGIMM_REACH - RISCV_RVC_IMM_REACH / 2))) 1391 break; 1392 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number); 1393 goto rvc_imm_done; 1394 case 'v': 1395 if (my_getSmallExpression (imm_expr, imm_reloc, s, p) 1396 || (imm_expr->X_add_number & (RISCV_IMM_REACH - 1)) 1397 || ((int32_t)imm_expr->X_add_number 1398 != imm_expr->X_add_number)) 1399 break; 1400 imm_expr->X_add_number = 1401 ((uint32_t) imm_expr->X_add_number) >> RISCV_IMM_BITS; 1402 goto rvc_lui; 1403 case 'p': 1404 goto branch; 1405 case 'a': 1406 goto jump; 1407 case 'D': /* Floating-point RS2 x8-x15. */ 1408 if (!reg_lookup (&s, RCLASS_FPR, ®no) 1409 || !(regno >= 8 && regno <= 15)) 1410 break; 1411 INSERT_OPERAND (CRS2S, *ip, regno % 8); 1412 continue; 1413 case 'T': /* Floating-point RS2. */ 1414 if (!reg_lookup (&s, RCLASS_FPR, ®no)) 1415 break; 1416 INSERT_OPERAND (CRS2, *ip, regno); 1417 continue; 1418 default: 1419 as_bad (_("bad RVC field specifier 'C%c'\n"), *args); 1420 } 1421 break; 1422 1423 case ',': 1424 ++argnum; 1425 if (*s++ == *args) 1426 continue; 1427 s--; 1428 break; 1429 1430 case '(': 1431 case ')': 1432 case '[': 1433 case ']': 1434 if (*s++ == *args) 1435 continue; 1436 break; 1437 1438 case '<': /* Shift amount, 0 - 31. */ 1439 my_getExpression (imm_expr, s); 1440 check_absolute_expr (ip, imm_expr); 1441 if ((unsigned long) imm_expr->X_add_number > 31) 1442 as_warn (_("Improper shift amount (%lu)"), 1443 (unsigned long) imm_expr->X_add_number); 1444 INSERT_OPERAND (SHAMTW, *ip, imm_expr->X_add_number); 1445 imm_expr->X_op = O_absent; 1446 s = expr_end; 1447 continue; 1448 1449 case '>': /* Shift amount, 0 - (XLEN-1). */ 1450 my_getExpression (imm_expr, s); 1451 check_absolute_expr (ip, imm_expr); 1452 if ((unsigned long) imm_expr->X_add_number >= xlen) 1453 as_warn (_("Improper shift amount (%lu)"), 1454 (unsigned long) imm_expr->X_add_number); 1455 INSERT_OPERAND (SHAMT, *ip, imm_expr->X_add_number); 1456 imm_expr->X_op = O_absent; 1457 s = expr_end; 1458 continue; 1459 1460 case 'Z': /* CSRRxI immediate. */ 1461 my_getExpression (imm_expr, s); 1462 check_absolute_expr (ip, imm_expr); 1463 if ((unsigned long) imm_expr->X_add_number > 31) 1464 as_warn (_("Improper CSRxI immediate (%lu)"), 1465 (unsigned long) imm_expr->X_add_number); 1466 INSERT_OPERAND (RS1, *ip, imm_expr->X_add_number); 1467 imm_expr->X_op = O_absent; 1468 s = expr_end; 1469 continue; 1470 1471 case 'E': /* Control register. */ 1472 if (reg_lookup (&s, RCLASS_CSR, ®no)) 1473 INSERT_OPERAND (CSR, *ip, regno); 1474 else 1475 { 1476 my_getExpression (imm_expr, s); 1477 check_absolute_expr (ip, imm_expr); 1478 if ((unsigned long) imm_expr->X_add_number > 0xfff) 1479 as_warn (_("Improper CSR address (%lu)"), 1480 (unsigned long) imm_expr->X_add_number); 1481 INSERT_OPERAND (CSR, *ip, imm_expr->X_add_number); 1482 imm_expr->X_op = O_absent; 1483 s = expr_end; 1484 } 1485 continue; 1486 1487 case 'm': /* Rounding mode. */ 1488 if (arg_lookup (&s, riscv_rm, ARRAY_SIZE (riscv_rm), ®no)) 1489 { 1490 INSERT_OPERAND (RM, *ip, regno); 1491 continue; 1492 } 1493 break; 1494 1495 case 'P': 1496 case 'Q': /* Fence predecessor/successor. */ 1497 if (arg_lookup (&s, riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ), 1498 ®no)) 1499 { 1500 if (*args == 'P') 1501 INSERT_OPERAND (PRED, *ip, regno); 1502 else 1503 INSERT_OPERAND (SUCC, *ip, regno); 1504 continue; 1505 } 1506 break; 1507 1508 case 'd': /* Destination register. */ 1509 case 's': /* Source register. */ 1510 case 't': /* Target register. */ 1511 if (reg_lookup (&s, RCLASS_GPR, ®no)) 1512 { 1513 c = *args; 1514 if (*s == ' ') 1515 ++s; 1516 1517 /* Now that we have assembled one operand, we use the args 1518 string to figure out where it goes in the instruction. */ 1519 switch (c) 1520 { 1521 case 's': 1522 INSERT_OPERAND (RS1, *ip, regno); 1523 break; 1524 case 'd': 1525 INSERT_OPERAND (RD, *ip, regno); 1526 break; 1527 case 't': 1528 INSERT_OPERAND (RS2, *ip, regno); 1529 break; 1530 } 1531 continue; 1532 } 1533 break; 1534 1535 case 'D': /* Floating point rd. */ 1536 case 'S': /* Floating point rs1. */ 1537 case 'T': /* Floating point rs2. */ 1538 case 'U': /* Floating point rs1 and rs2. */ 1539 case 'R': /* Floating point rs3. */ 1540 if (reg_lookup (&s, RCLASS_FPR, ®no)) 1541 { 1542 c = *args; 1543 if (*s == ' ') 1544 ++s; 1545 switch (c) 1546 { 1547 case 'D': 1548 INSERT_OPERAND (RD, *ip, regno); 1549 break; 1550 case 'S': 1551 INSERT_OPERAND (RS1, *ip, regno); 1552 break; 1553 case 'U': 1554 INSERT_OPERAND (RS1, *ip, regno); 1555 /* fallthru */ 1556 case 'T': 1557 INSERT_OPERAND (RS2, *ip, regno); 1558 break; 1559 case 'R': 1560 INSERT_OPERAND (RS3, *ip, regno); 1561 break; 1562 } 1563 continue; 1564 } 1565 1566 break; 1567 1568 case 'I': 1569 my_getExpression (imm_expr, s); 1570 if (imm_expr->X_op != O_big 1571 && imm_expr->X_op != O_constant) 1572 break; 1573 normalize_constant_expr (imm_expr); 1574 s = expr_end; 1575 continue; 1576 1577 case 'A': 1578 my_getExpression (imm_expr, s); 1579 normalize_constant_expr (imm_expr); 1580 /* The 'A' format specifier must be a symbol. */ 1581 if (imm_expr->X_op != O_symbol) 1582 break; 1583 *imm_reloc = BFD_RELOC_32; 1584 s = expr_end; 1585 continue; 1586 1587 case 'j': /* Sign-extended immediate. */ 1588 *imm_reloc = BFD_RELOC_RISCV_LO12_I; 1589 p = percent_op_itype; 1590 goto alu_op; 1591 case 'q': /* Store displacement. */ 1592 p = percent_op_stype; 1593 *imm_reloc = BFD_RELOC_RISCV_LO12_S; 1594 goto load_store; 1595 case 'o': /* Load displacement. */ 1596 p = percent_op_itype; 1597 *imm_reloc = BFD_RELOC_RISCV_LO12_I; 1598 goto load_store; 1599 case '0': /* AMO "displacement," which must be zero. */ 1600 p = percent_op_rtype; 1601 *imm_reloc = BFD_RELOC_UNUSED; 1602load_store: 1603 /* Check whether there is only a single bracketed expression 1604 left. If so, it must be the base register and the 1605 constant must be zero. */ 1606 imm_expr->X_op = O_constant; 1607 imm_expr->X_add_number = 0; 1608 if (*s == '(' && strchr (s + 1, '(') == 0) 1609 continue; 1610alu_op: 1611 /* If this value won't fit into a 16 bit offset, then go 1612 find a macro that will generate the 32 bit offset 1613 code pattern. */ 1614 if (!my_getSmallExpression (imm_expr, imm_reloc, s, p)) 1615 { 1616 normalize_constant_expr (imm_expr); 1617 if (imm_expr->X_op != O_constant 1618 || (*args == '0' && imm_expr->X_add_number != 0) 1619 || imm_expr->X_add_number >= (signed)RISCV_IMM_REACH/2 1620 || imm_expr->X_add_number < -(signed)RISCV_IMM_REACH/2) 1621 break; 1622 } 1623 1624 s = expr_end; 1625 continue; 1626 1627 case 'p': /* PC-relative offset. */ 1628branch: 1629 *imm_reloc = BFD_RELOC_12_PCREL; 1630 my_getExpression (imm_expr, s); 1631 s = expr_end; 1632 continue; 1633 1634 case 'u': /* Upper 20 bits. */ 1635 p = percent_op_utype; 1636 if (!my_getSmallExpression (imm_expr, imm_reloc, s, p) 1637 && imm_expr->X_op == O_constant) 1638 { 1639 if (imm_expr->X_add_number < 0 1640 || imm_expr->X_add_number >= (signed)RISCV_BIGIMM_REACH) 1641 as_bad (_("lui expression not in range 0..1048575")); 1642 1643 *imm_reloc = BFD_RELOC_RISCV_HI20; 1644 imm_expr->X_add_number <<= RISCV_IMM_BITS; 1645 } 1646 s = expr_end; 1647 continue; 1648 1649 case 'a': /* 20-bit PC-relative offset. */ 1650jump: 1651 my_getExpression (imm_expr, s); 1652 s = expr_end; 1653 *imm_reloc = BFD_RELOC_RISCV_JMP; 1654 continue; 1655 1656 case 'c': 1657 my_getExpression (imm_expr, s); 1658 s = expr_end; 1659 if (strcmp (s, "@plt") == 0) 1660 { 1661 *imm_reloc = BFD_RELOC_RISCV_CALL_PLT; 1662 s += 4; 1663 } 1664 else 1665 *imm_reloc = BFD_RELOC_RISCV_CALL; 1666 continue; 1667 1668 default: 1669 as_fatal (_("internal error: bad argument type %c"), *args); 1670 } 1671 break; 1672 } 1673 s = argsStart; 1674 error = _("illegal operands"); 1675 } 1676 1677out: 1678 /* Restore the character we might have clobbered above. */ 1679 if (save_c) 1680 *(argsStart - 1) = save_c; 1681 1682 return error; 1683} 1684 1685void 1686md_assemble (char *str) 1687{ 1688 struct riscv_cl_insn insn; 1689 expressionS imm_expr; 1690 bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED; 1691 1692 const char *error = riscv_ip (str, &insn, &imm_expr, &imm_reloc); 1693 1694 if (error) 1695 { 1696 as_bad ("%s `%s'", error, str); 1697 return; 1698 } 1699 1700 if (insn.insn_mo->pinfo == INSN_MACRO) 1701 macro (&insn, &imm_expr, &imm_reloc); 1702 else 1703 append_insn (&insn, &imm_expr, imm_reloc); 1704} 1705 1706const char * 1707md_atof (int type, char *litP, int *sizeP) 1708{ 1709 return ieee_md_atof (type, litP, sizeP, TARGET_BYTES_BIG_ENDIAN); 1710} 1711 1712void 1713md_number_to_chars (char *buf, valueT val, int n) 1714{ 1715 number_to_chars_littleendian (buf, val, n); 1716} 1717 1718const char *md_shortopts = "O::g::G:"; 1719 1720enum options 1721{ 1722 OPTION_MARCH = OPTION_MD_BASE, 1723 OPTION_PIC, 1724 OPTION_NO_PIC, 1725 OPTION_MABI, 1726 OPTION_END_OF_ENUM 1727}; 1728 1729struct option md_longopts[] = 1730{ 1731 {"march", required_argument, NULL, OPTION_MARCH}, 1732 {"fPIC", no_argument, NULL, OPTION_PIC}, 1733 {"fpic", no_argument, NULL, OPTION_PIC}, 1734 {"fno-pic", no_argument, NULL, OPTION_NO_PIC}, 1735 {"mabi", required_argument, NULL, OPTION_MABI}, 1736 1737 {NULL, no_argument, NULL, 0} 1738}; 1739size_t md_longopts_size = sizeof (md_longopts); 1740 1741enum float_abi { 1742 FLOAT_ABI_DEFAULT = -1, 1743 FLOAT_ABI_SOFT, 1744 FLOAT_ABI_SINGLE, 1745 FLOAT_ABI_DOUBLE, 1746 FLOAT_ABI_QUAD 1747}; 1748static enum float_abi float_abi = FLOAT_ABI_DEFAULT; 1749 1750static void 1751riscv_set_abi (unsigned new_xlen, enum float_abi new_float_abi) 1752{ 1753 abi_xlen = new_xlen; 1754 float_abi = new_float_abi; 1755} 1756 1757int 1758md_parse_option (int c, const char *arg) 1759{ 1760 switch (c) 1761 { 1762 case OPTION_MARCH: 1763 riscv_set_arch (arg); 1764 break; 1765 1766 case OPTION_NO_PIC: 1767 riscv_opts.pic = FALSE; 1768 break; 1769 1770 case OPTION_PIC: 1771 riscv_opts.pic = TRUE; 1772 break; 1773 1774 case OPTION_MABI: 1775 if (strcmp (arg, "ilp32") == 0) 1776 riscv_set_abi (32, FLOAT_ABI_SOFT); 1777 else if (strcmp (arg, "ilp32f") == 0) 1778 riscv_set_abi (32, FLOAT_ABI_SINGLE); 1779 else if (strcmp (arg, "ilp32d") == 0) 1780 riscv_set_abi (32, FLOAT_ABI_DOUBLE); 1781 else if (strcmp (arg, "ilp32q") == 0) 1782 riscv_set_abi (32, FLOAT_ABI_QUAD); 1783 else if (strcmp (arg, "lp64") == 0) 1784 riscv_set_abi (64, FLOAT_ABI_SOFT); 1785 else if (strcmp (arg, "lp64f") == 0) 1786 riscv_set_abi (64, FLOAT_ABI_SINGLE); 1787 else if (strcmp (arg, "lp64d") == 0) 1788 riscv_set_abi (64, FLOAT_ABI_DOUBLE); 1789 else if (strcmp (arg, "lp64q") == 0) 1790 riscv_set_abi (64, FLOAT_ABI_QUAD); 1791 else 1792 return 0; 1793 break; 1794 1795 default: 1796 return 0; 1797 } 1798 1799 return 1; 1800} 1801 1802void 1803riscv_after_parse_args (void) 1804{ 1805 if (xlen == 0) 1806 { 1807 if (strcmp (default_arch, "riscv32") == 0) 1808 xlen = 32; 1809 else if (strcmp (default_arch, "riscv64") == 0) 1810 xlen = 64; 1811 else 1812 as_bad ("unknown default architecture `%s'", default_arch); 1813 } 1814 1815 if (riscv_subsets == NULL) 1816 riscv_set_arch (xlen == 64 ? "rv64g" : "rv32g"); 1817 1818 /* Add the RVC extension, regardless of -march, to support .option rvc. */ 1819 riscv_set_rvc (FALSE); 1820 if (riscv_subset_supports ("c")) 1821 riscv_set_rvc (TRUE); 1822 else 1823 riscv_add_subset ("c"); 1824 1825 /* Infer ABI from ISA if not specified on command line. */ 1826 if (abi_xlen == 0) 1827 abi_xlen = xlen; 1828 else if (abi_xlen > xlen) 1829 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen, xlen); 1830 else if (abi_xlen < xlen) 1831 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen, xlen); 1832 1833 if (float_abi == FLOAT_ABI_DEFAULT) 1834 { 1835 struct riscv_subset *subset; 1836 1837 /* Assume soft-float unless D extension is present. */ 1838 float_abi = FLOAT_ABI_SOFT; 1839 1840 for (subset = riscv_subsets; subset != NULL; subset = subset->next) 1841 if (strcasecmp (subset->name, "D") == 0) 1842 float_abi = FLOAT_ABI_DOUBLE; 1843 } 1844 1845 /* Insert float_abi into the EF_RISCV_FLOAT_ABI field of elf_flags. */ 1846 elf_flags |= float_abi * (EF_RISCV_FLOAT_ABI & ~(EF_RISCV_FLOAT_ABI << 1)); 1847} 1848 1849long 1850md_pcrel_from (fixS *fixP) 1851{ 1852 return fixP->fx_where + fixP->fx_frag->fr_address; 1853} 1854 1855/* Apply a fixup to the object file. */ 1856 1857void 1858md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) 1859{ 1860 unsigned int subtype; 1861 bfd_byte *buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); 1862 bfd_boolean relaxable = FALSE; 1863 offsetT loc; 1864 1865 /* Remember value for tc_gen_reloc. */ 1866 fixP->fx_addnumber = *valP; 1867 1868 switch (fixP->fx_r_type) 1869 { 1870 case BFD_RELOC_RISCV_HI20: 1871 case BFD_RELOC_RISCV_LO12_I: 1872 case BFD_RELOC_RISCV_LO12_S: 1873 bfd_putl32 (riscv_apply_const_reloc (fixP->fx_r_type, *valP) 1874 | bfd_getl32 (buf), buf); 1875 if (fixP->fx_addsy == NULL) 1876 fixP->fx_done = TRUE; 1877 relaxable = TRUE; 1878 break; 1879 1880 case BFD_RELOC_RISCV_GOT_HI20: 1881 case BFD_RELOC_RISCV_PCREL_HI20: 1882 case BFD_RELOC_RISCV_ADD8: 1883 case BFD_RELOC_RISCV_ADD16: 1884 case BFD_RELOC_RISCV_ADD32: 1885 case BFD_RELOC_RISCV_ADD64: 1886 case BFD_RELOC_RISCV_SUB6: 1887 case BFD_RELOC_RISCV_SUB8: 1888 case BFD_RELOC_RISCV_SUB16: 1889 case BFD_RELOC_RISCV_SUB32: 1890 case BFD_RELOC_RISCV_SUB64: 1891 case BFD_RELOC_RISCV_RELAX: 1892 break; 1893 1894 case BFD_RELOC_RISCV_TPREL_HI20: 1895 case BFD_RELOC_RISCV_TPREL_LO12_I: 1896 case BFD_RELOC_RISCV_TPREL_LO12_S: 1897 case BFD_RELOC_RISCV_TPREL_ADD: 1898 relaxable = TRUE; 1899 /* Fall through. */ 1900 1901 case BFD_RELOC_RISCV_TLS_GOT_HI20: 1902 case BFD_RELOC_RISCV_TLS_GD_HI20: 1903 case BFD_RELOC_RISCV_TLS_DTPREL32: 1904 case BFD_RELOC_RISCV_TLS_DTPREL64: 1905 if (fixP->fx_addsy != NULL) 1906 S_SET_THREAD_LOCAL (fixP->fx_addsy); 1907 else 1908 as_bad_where (fixP->fx_file, fixP->fx_line, 1909 _("TLS relocation against a constant")); 1910 break; 1911 1912 case BFD_RELOC_64: 1913 case BFD_RELOC_32: 1914 case BFD_RELOC_16: 1915 case BFD_RELOC_8: 1916 case BFD_RELOC_RISCV_CFA: 1917 if (fixP->fx_addsy && fixP->fx_subsy) 1918 { 1919 fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP)); 1920 fixP->fx_next->fx_addsy = fixP->fx_subsy; 1921 fixP->fx_next->fx_subsy = NULL; 1922 fixP->fx_next->fx_offset = 0; 1923 fixP->fx_subsy = NULL; 1924 1925 switch (fixP->fx_r_type) 1926 { 1927 case BFD_RELOC_64: 1928 fixP->fx_r_type = BFD_RELOC_RISCV_ADD64; 1929 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB64; 1930 break; 1931 1932 case BFD_RELOC_32: 1933 fixP->fx_r_type = BFD_RELOC_RISCV_ADD32; 1934 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32; 1935 break; 1936 1937 case BFD_RELOC_16: 1938 fixP->fx_r_type = BFD_RELOC_RISCV_ADD16; 1939 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16; 1940 break; 1941 1942 case BFD_RELOC_8: 1943 fixP->fx_r_type = BFD_RELOC_RISCV_ADD8; 1944 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8; 1945 break; 1946 1947 case BFD_RELOC_RISCV_CFA: 1948 /* Load the byte to get the subtype. */ 1949 subtype = bfd_get_8 (NULL, &((fragS *) (fixP->fx_frag->fr_opcode))->fr_literal[fixP->fx_where]); 1950 loc = fixP->fx_frag->fr_fix - (subtype & 7); 1951 switch (subtype) 1952 { 1953 case DW_CFA_advance_loc1: 1954 fixP->fx_where = loc + 1; 1955 fixP->fx_next->fx_where = loc + 1; 1956 fixP->fx_r_type = BFD_RELOC_RISCV_SET8; 1957 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8; 1958 break; 1959 1960 case DW_CFA_advance_loc2: 1961 fixP->fx_size = 2; 1962 fixP->fx_next->fx_size = 2; 1963 fixP->fx_where = loc + 1; 1964 fixP->fx_next->fx_where = loc + 1; 1965 fixP->fx_r_type = BFD_RELOC_RISCV_SET16; 1966 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16; 1967 break; 1968 1969 case DW_CFA_advance_loc4: 1970 fixP->fx_size = 4; 1971 fixP->fx_next->fx_size = 4; 1972 fixP->fx_where = loc; 1973 fixP->fx_next->fx_where = loc; 1974 fixP->fx_r_type = BFD_RELOC_RISCV_SET32; 1975 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32; 1976 break; 1977 1978 default: 1979 if (subtype < 0x80 && (subtype & 0x40)) 1980 { 1981 /* DW_CFA_advance_loc */ 1982 fixP->fx_frag = (fragS *) fixP->fx_frag->fr_opcode; 1983 fixP->fx_next->fx_frag = fixP->fx_frag; 1984 fixP->fx_r_type = BFD_RELOC_RISCV_SET6; 1985 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB6; 1986 } 1987 else 1988 as_fatal (_("internal error: bad CFA value #%d"), subtype); 1989 break; 1990 } 1991 break; 1992 1993 default: 1994 /* This case is unreachable. */ 1995 abort (); 1996 } 1997 } 1998 /* Fall through. */ 1999 2000 case BFD_RELOC_RVA: 2001 /* If we are deleting this reloc entry, we must fill in the 2002 value now. This can happen if we have a .word which is not 2003 resolved when it appears but is later defined. */ 2004 if (fixP->fx_addsy == NULL) 2005 { 2006 gas_assert (fixP->fx_size <= sizeof (valueT)); 2007 md_number_to_chars ((char *) buf, *valP, fixP->fx_size); 2008 fixP->fx_done = 1; 2009 } 2010 break; 2011 2012 case BFD_RELOC_RISCV_JMP: 2013 if (fixP->fx_addsy) 2014 { 2015 /* Fill in a tentative value to improve objdump readability. */ 2016 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP; 2017 bfd_vma delta = target - md_pcrel_from (fixP); 2018 bfd_putl32 (bfd_getl32 (buf) | ENCODE_UJTYPE_IMM (delta), buf); 2019 } 2020 break; 2021 2022 case BFD_RELOC_12_PCREL: 2023 if (fixP->fx_addsy) 2024 { 2025 /* Fill in a tentative value to improve objdump readability. */ 2026 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP; 2027 bfd_vma delta = target - md_pcrel_from (fixP); 2028 bfd_putl32 (bfd_getl32 (buf) | ENCODE_SBTYPE_IMM (delta), buf); 2029 } 2030 break; 2031 2032 case BFD_RELOC_RISCV_RVC_BRANCH: 2033 if (fixP->fx_addsy) 2034 { 2035 /* Fill in a tentative value to improve objdump readability. */ 2036 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP; 2037 bfd_vma delta = target - md_pcrel_from (fixP); 2038 bfd_putl16 (bfd_getl16 (buf) | ENCODE_RVC_B_IMM (delta), buf); 2039 } 2040 break; 2041 2042 case BFD_RELOC_RISCV_RVC_JUMP: 2043 if (fixP->fx_addsy) 2044 { 2045 /* Fill in a tentative value to improve objdump readability. */ 2046 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP; 2047 bfd_vma delta = target - md_pcrel_from (fixP); 2048 bfd_putl16 (bfd_getl16 (buf) | ENCODE_RVC_J_IMM (delta), buf); 2049 } 2050 break; 2051 2052 case BFD_RELOC_RISCV_CALL: 2053 case BFD_RELOC_RISCV_CALL_PLT: 2054 relaxable = TRUE; 2055 break; 2056 2057 case BFD_RELOC_RISCV_PCREL_LO12_S: 2058 case BFD_RELOC_RISCV_PCREL_LO12_I: 2059 case BFD_RELOC_RISCV_ALIGN: 2060 break; 2061 2062 default: 2063 /* We ignore generic BFD relocations we don't know about. */ 2064 if (bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type) != NULL) 2065 as_fatal (_("internal error: bad relocation #%d"), fixP->fx_r_type); 2066 } 2067 2068 if (fixP->fx_subsy != NULL) 2069 as_bad_where (fixP->fx_file, fixP->fx_line, 2070 _("unsupported symbol subtraction")); 2071 2072 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */ 2073 if (relaxable && fixP->fx_tcbit && fixP->fx_addsy != NULL) 2074 { 2075 fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP)); 2076 fixP->fx_next->fx_addsy = fixP->fx_next->fx_subsy = NULL; 2077 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_RELAX; 2078 } 2079} 2080 2081/* Because the value of .cfi_remember_state may changed after relaxation, 2082 we insert a fix to relocate it again in link-time. */ 2083 2084void 2085riscv_pre_output_hook (void) 2086{ 2087 const frchainS *frch; 2088 const asection *s; 2089 2090 for (s = stdoutput->sections; s; s = s->next) 2091 for (frch = seg_info (s)->frchainP; frch; frch = frch->frch_next) 2092 { 2093 fragS *frag; 2094 2095 for (frag = frch->frch_root; frag; frag = frag->fr_next) 2096 { 2097 if (frag->fr_type == rs_cfa) 2098 { 2099 expressionS exp; 2100 2101 symbolS *add_symbol = frag->fr_symbol->sy_value.X_add_symbol; 2102 symbolS *op_symbol = frag->fr_symbol->sy_value.X_op_symbol; 2103 2104 exp.X_op = O_subtract; 2105 exp.X_add_symbol = add_symbol; 2106 exp.X_add_number = 0; 2107 exp.X_op_symbol = op_symbol; 2108 2109 fix_new_exp (frag, (int) frag->fr_offset, 1, &exp, 0, 2110 BFD_RELOC_RISCV_CFA); 2111 } 2112 } 2113 } 2114} 2115 2116 2117/* This structure is used to hold a stack of .option values. */ 2118 2119struct riscv_option_stack 2120{ 2121 struct riscv_option_stack *next; 2122 struct riscv_set_options options; 2123}; 2124 2125static struct riscv_option_stack *riscv_opts_stack; 2126 2127/* Handle the .option pseudo-op. */ 2128 2129static void 2130s_riscv_option (int x ATTRIBUTE_UNUSED) 2131{ 2132 char *name = input_line_pointer, ch; 2133 2134 while (!is_end_of_line[(unsigned char) *input_line_pointer]) 2135 ++input_line_pointer; 2136 ch = *input_line_pointer; 2137 *input_line_pointer = '\0'; 2138 2139 if (strcmp (name, "rvc") == 0) 2140 riscv_set_rvc (TRUE); 2141 else if (strcmp (name, "norvc") == 0) 2142 riscv_set_rvc (FALSE); 2143 else if (strcmp (name, "pic") == 0) 2144 riscv_opts.pic = TRUE; 2145 else if (strcmp (name, "nopic") == 0) 2146 riscv_opts.pic = FALSE; 2147 else if (strcmp (name, "relax") == 0) 2148 riscv_opts.relax = TRUE; 2149 else if (strcmp (name, "norelax") == 0) 2150 riscv_opts.relax = FALSE; 2151 else if (strcmp (name, "push") == 0) 2152 { 2153 struct riscv_option_stack *s; 2154 2155 s = (struct riscv_option_stack *) xmalloc (sizeof *s); 2156 s->next = riscv_opts_stack; 2157 s->options = riscv_opts; 2158 riscv_opts_stack = s; 2159 } 2160 else if (strcmp (name, "pop") == 0) 2161 { 2162 struct riscv_option_stack *s; 2163 2164 s = riscv_opts_stack; 2165 if (s == NULL) 2166 as_bad (_(".option pop with no .option push")); 2167 else 2168 { 2169 riscv_opts = s->options; 2170 riscv_opts_stack = s->next; 2171 free (s); 2172 } 2173 } 2174 else 2175 { 2176 as_warn (_("Unrecognized .option directive: %s\n"), name); 2177 } 2178 *input_line_pointer = ch; 2179 demand_empty_rest_of_line (); 2180} 2181 2182/* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate 2183 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for 2184 use in DWARF debug information. */ 2185 2186static void 2187s_dtprel (int bytes) 2188{ 2189 expressionS ex; 2190 char *p; 2191 2192 expression (&ex); 2193 2194 if (ex.X_op != O_symbol) 2195 { 2196 as_bad (_("Unsupported use of %s"), (bytes == 8 2197 ? ".dtpreldword" 2198 : ".dtprelword")); 2199 ignore_rest_of_line (); 2200 } 2201 2202 p = frag_more (bytes); 2203 md_number_to_chars (p, 0, bytes); 2204 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, 2205 (bytes == 8 2206 ? BFD_RELOC_RISCV_TLS_DTPREL64 2207 : BFD_RELOC_RISCV_TLS_DTPREL32)); 2208 2209 demand_empty_rest_of_line (); 2210} 2211 2212/* Handle the .bss pseudo-op. */ 2213 2214static void 2215s_bss (int ignore ATTRIBUTE_UNUSED) 2216{ 2217 subseg_set (bss_section, 0); 2218 demand_empty_rest_of_line (); 2219} 2220 2221static void 2222riscv_make_nops (char *buf, bfd_vma bytes) 2223{ 2224 bfd_vma i = 0; 2225 2226 /* RISC-V instructions cannot begin or end on odd addresses, so this case 2227 means we are not within a valid instruction sequence. It is thus safe 2228 to use a zero byte, even though that is not a valid instruction. */ 2229 if (bytes % 2 == 1) 2230 buf[i++] = 0; 2231 2232 /* Use at most one 2-byte NOP. */ 2233 if ((bytes - i) % 4 == 2) 2234 { 2235 md_number_to_chars (buf + i, RVC_NOP, 2); 2236 i += 2; 2237 } 2238 2239 /* Fill the remainder with 4-byte NOPs. */ 2240 for ( ; i < bytes; i += 4) 2241 md_number_to_chars (buf + i, RISCV_NOP, 4); 2242} 2243 2244/* Called from md_do_align. Used to create an alignment frag in a 2245 code section by emitting a worst-case NOP sequence that the linker 2246 will later relax to the correct number of NOPs. We can't compute 2247 the correct alignment now because of other linker relaxations. */ 2248 2249bfd_boolean 2250riscv_frag_align_code (int n) 2251{ 2252 bfd_vma bytes = (bfd_vma) 1 << n; 2253 bfd_vma min_text_alignment_order = riscv_opts.rvc ? 1 : 2; 2254 bfd_vma min_text_alignment = (bfd_vma) 1 << min_text_alignment_order; 2255 2256 /* First, get back to minimal alignment. */ 2257 frag_align_code (min_text_alignment_order, 0); 2258 2259 /* When not relaxing, riscv_handle_align handles code alignment. */ 2260 if (!riscv_opts.relax) 2261 return FALSE; 2262 2263 if (bytes > min_text_alignment) 2264 { 2265 bfd_vma worst_case_bytes = bytes - min_text_alignment; 2266 char *nops = frag_more (worst_case_bytes); 2267 expressionS ex; 2268 2269 ex.X_op = O_constant; 2270 ex.X_add_number = worst_case_bytes; 2271 2272 riscv_make_nops (nops, worst_case_bytes); 2273 2274 fix_new_exp (frag_now, nops - frag_now->fr_literal, 0, 2275 &ex, FALSE, BFD_RELOC_RISCV_ALIGN); 2276 } 2277 2278 return TRUE; 2279} 2280 2281/* Implement HANDLE_ALIGN. */ 2282 2283void 2284riscv_handle_align (fragS *fragP) 2285{ 2286 switch (fragP->fr_type) 2287 { 2288 case rs_align_code: 2289 /* When relaxing, riscv_frag_align_code handles code alignment. */ 2290 if (!riscv_opts.relax) 2291 { 2292 bfd_signed_vma count = fragP->fr_next->fr_address 2293 - fragP->fr_address - fragP->fr_fix; 2294 2295 if (count <= 0) 2296 break; 2297 2298 count &= MAX_MEM_FOR_RS_ALIGN_CODE; 2299 riscv_make_nops (fragP->fr_literal + fragP->fr_fix, count); 2300 fragP->fr_var = count; 2301 } 2302 break; 2303 2304 default: 2305 break; 2306 } 2307} 2308 2309int 2310md_estimate_size_before_relax (fragS *fragp, asection *segtype) 2311{ 2312 return (fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE)); 2313} 2314 2315/* Translate internal representation of relocation info to BFD target 2316 format. */ 2317 2318arelent * 2319tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) 2320{ 2321 arelent *reloc = (arelent *) xmalloc (sizeof (arelent)); 2322 2323 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); 2324 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 2325 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 2326 reloc->addend = fixp->fx_addnumber; 2327 2328 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); 2329 if (reloc->howto == NULL) 2330 { 2331 if ((fixp->fx_r_type == BFD_RELOC_16 || fixp->fx_r_type == BFD_RELOC_8) 2332 && fixp->fx_addsy != NULL && fixp->fx_subsy != NULL) 2333 { 2334 /* We don't have R_RISCV_8/16, but for this special case, 2335 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */ 2336 return reloc; 2337 } 2338 2339 as_bad_where (fixp->fx_file, fixp->fx_line, 2340 _("cannot represent %s relocation in object file"), 2341 bfd_get_reloc_code_name (fixp->fx_r_type)); 2342 return NULL; 2343 } 2344 2345 return reloc; 2346} 2347 2348int 2349riscv_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED) 2350{ 2351 if (RELAX_BRANCH_P (fragp->fr_subtype)) 2352 { 2353 offsetT old_var = fragp->fr_var; 2354 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); 2355 return fragp->fr_var - old_var; 2356 } 2357 2358 return 0; 2359} 2360 2361/* Expand far branches to multi-instruction sequences. */ 2362 2363static void 2364md_convert_frag_branch (fragS *fragp) 2365{ 2366 bfd_byte *buf; 2367 expressionS exp; 2368 fixS *fixp; 2369 insn_t insn; 2370 int rs1, reloc; 2371 2372 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; 2373 2374 exp.X_op = O_symbol; 2375 exp.X_add_symbol = fragp->fr_symbol; 2376 exp.X_add_number = fragp->fr_offset; 2377 2378 gas_assert (fragp->fr_var == RELAX_BRANCH_LENGTH (fragp->fr_subtype)); 2379 2380 if (RELAX_BRANCH_RVC (fragp->fr_subtype)) 2381 { 2382 switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype)) 2383 { 2384 case 8: 2385 case 4: 2386 /* Expand the RVC branch into a RISC-V one. */ 2387 insn = bfd_getl16 (buf); 2388 rs1 = 8 + ((insn >> OP_SH_CRS1S) & OP_MASK_CRS1S); 2389 if ((insn & MASK_C_J) == MATCH_C_J) 2390 insn = MATCH_JAL; 2391 else if ((insn & MASK_C_JAL) == MATCH_C_JAL) 2392 insn = MATCH_JAL | (X_RA << OP_SH_RD); 2393 else if ((insn & MASK_C_BEQZ) == MATCH_C_BEQZ) 2394 insn = MATCH_BEQ | (rs1 << OP_SH_RS1); 2395 else if ((insn & MASK_C_BNEZ) == MATCH_C_BNEZ) 2396 insn = MATCH_BNE | (rs1 << OP_SH_RS1); 2397 else 2398 abort (); 2399 bfd_putl32 (insn, buf); 2400 break; 2401 2402 case 6: 2403 /* Invert the branch condition. Branch over the jump. */ 2404 insn = bfd_getl16 (buf); 2405 insn ^= MATCH_C_BEQZ ^ MATCH_C_BNEZ; 2406 insn |= ENCODE_RVC_B_IMM (6); 2407 bfd_putl16 (insn, buf); 2408 buf += 2; 2409 goto jump; 2410 2411 case 2: 2412 /* Just keep the RVC branch. */ 2413 reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype) 2414 ? BFD_RELOC_RISCV_RVC_JUMP : BFD_RELOC_RISCV_RVC_BRANCH; 2415 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, 2416 2, &exp, FALSE, reloc); 2417 buf += 2; 2418 goto done; 2419 2420 default: 2421 abort (); 2422 } 2423 } 2424 2425 switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype)) 2426 { 2427 case 8: 2428 gas_assert (!RELAX_BRANCH_UNCOND (fragp->fr_subtype)); 2429 2430 /* Invert the branch condition. Branch over the jump. */ 2431 insn = bfd_getl32 (buf); 2432 insn ^= MATCH_BEQ ^ MATCH_BNE; 2433 insn |= ENCODE_SBTYPE_IMM (8); 2434 md_number_to_chars ((char *) buf, insn, 4); 2435 buf += 4; 2436 2437jump: 2438 /* Jump to the target. */ 2439 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, 2440 4, &exp, FALSE, BFD_RELOC_RISCV_JMP); 2441 md_number_to_chars ((char *) buf, MATCH_JAL, 4); 2442 buf += 4; 2443 break; 2444 2445 case 4: 2446 reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype) 2447 ? BFD_RELOC_RISCV_JMP : BFD_RELOC_12_PCREL; 2448 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, 2449 4, &exp, FALSE, reloc); 2450 buf += 4; 2451 break; 2452 2453 default: 2454 abort (); 2455 } 2456 2457done: 2458 fixp->fx_file = fragp->fr_file; 2459 fixp->fx_line = fragp->fr_line; 2460 2461 gas_assert (buf == (bfd_byte *)fragp->fr_literal 2462 + fragp->fr_fix + fragp->fr_var); 2463 2464 fragp->fr_fix += fragp->fr_var; 2465} 2466 2467/* Relax a machine dependent frag. This returns the amount by which 2468 the current size of the frag should change. */ 2469 2470void 2471md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec ATTRIBUTE_UNUSED, 2472 fragS *fragp) 2473{ 2474 gas_assert (RELAX_BRANCH_P (fragp->fr_subtype)); 2475 md_convert_frag_branch (fragp); 2476} 2477 2478void 2479md_show_usage (FILE *stream) 2480{ 2481 fprintf (stream, _("\ 2482RISC-V options:\n\ 2483 -fpic generate position-independent code\n\ 2484 -fno-pic don't generate position-independent code (default)\n\ 2485 -march=ISA set the RISC-V architecture\n\ 2486 -mabi=ABI set the RISC-V ABI\n\ 2487")); 2488} 2489 2490/* Standard calling conventions leave the CFA at SP on entry. */ 2491void 2492riscv_cfi_frame_initial_instructions (void) 2493{ 2494 cfi_add_CFA_def_cfa_register (X_SP); 2495} 2496 2497int 2498tc_riscv_regname_to_dw2regnum (char *regname) 2499{ 2500 int reg; 2501 2502 if ((reg = reg_lookup_internal (regname, RCLASS_GPR)) >= 0) 2503 return reg; 2504 2505 if ((reg = reg_lookup_internal (regname, RCLASS_FPR)) >= 0) 2506 return reg + 32; 2507 2508 as_bad (_("unknown register `%s'"), regname); 2509 return -1; 2510} 2511 2512void 2513riscv_elf_final_processing (void) 2514{ 2515 elf_elfheader (stdoutput)->e_flags |= elf_flags; 2516} 2517 2518/* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions, 2519 since these directives break relaxation when used with symbol deltas. */ 2520 2521static void 2522s_riscv_leb128 (int sign) 2523{ 2524 expressionS exp; 2525 char *save_in = input_line_pointer; 2526 2527 expression (&exp); 2528 if (exp.X_op != O_constant) 2529 as_bad (_("non-constant .%cleb128 is not supported"), sign ? 's' : 'u'); 2530 demand_empty_rest_of_line (); 2531 2532 input_line_pointer = save_in; 2533 return s_leb128 (sign); 2534} 2535 2536/* Pseudo-op table. */ 2537 2538static const pseudo_typeS riscv_pseudo_table[] = 2539{ 2540 /* RISC-V-specific pseudo-ops. */ 2541 {"option", s_riscv_option, 0}, 2542 {"half", cons, 2}, 2543 {"word", cons, 4}, 2544 {"dword", cons, 8}, 2545 {"dtprelword", s_dtprel, 4}, 2546 {"dtpreldword", s_dtprel, 8}, 2547 {"bss", s_bss, 0}, 2548 {"uleb128", s_riscv_leb128, 0}, 2549 {"sleb128", s_riscv_leb128, 1}, 2550 2551 { NULL, NULL, 0 }, 2552}; 2553 2554void 2555riscv_pop_insert (void) 2556{ 2557 extern void pop_insert (const pseudo_typeS *); 2558 2559 pop_insert (riscv_pseudo_table); 2560} 2561