1/* tc-mips.c -- assemble code for a MIPS chip. 2 Copyright (C) 1993-2017 Free Software Foundation, Inc. 3 Contributed by the OSF and Ralph Campbell. 4 Written by Keith Knowles and Ralph Campbell, working independently. 5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus 6 Support. 7 8 This file is part of GAS. 9 10 GAS is free software; you can redistribute it and/or modify 11 it under the terms of the GNU General Public License as published by 12 the Free Software Foundation; either version 3, or (at your option) 13 any later version. 14 15 GAS is distributed in the hope that it will be useful, 16 but WITHOUT ANY WARRANTY; without even the implied warranty of 17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 GNU General Public License for more details. 19 20 You should have received a copy of the GNU General Public License 21 along with GAS; see the file COPYING. If not, write to the Free 22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 23 02110-1301, USA. */ 24 25#include "as.h" 26#include "config.h" 27#include "subsegs.h" 28#include "safe-ctype.h" 29 30#include "opcode/mips.h" 31#include "itbl-ops.h" 32#include "dwarf2dbg.h" 33#include "dw2gencfi.h" 34 35/* Check assumptions made in this file. */ 36typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1]; 37typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1]; 38 39#ifdef DEBUG 40#define DBG(x) printf x 41#else 42#define DBG(x) 43#endif 44 45#define streq(a, b) (strcmp (a, b) == 0) 46 47#define SKIP_SPACE_TABS(S) \ 48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0) 49 50/* Clean up namespace so we can include obj-elf.h too. */ 51static int mips_output_flavor (void); 52static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } 53#undef OBJ_PROCESS_STAB 54#undef OUTPUT_FLAVOR 55#undef S_GET_ALIGN 56#undef S_GET_SIZE 57#undef S_SET_ALIGN 58#undef S_SET_SIZE 59#undef obj_frob_file 60#undef obj_frob_file_after_relocs 61#undef obj_frob_symbol 62#undef obj_pop_insert 63#undef obj_sec_sym_ok_for_reloc 64#undef OBJ_COPY_SYMBOL_ATTRIBUTES 65 66#include "obj-elf.h" 67/* Fix any of them that we actually care about. */ 68#undef OUTPUT_FLAVOR 69#define OUTPUT_FLAVOR mips_output_flavor() 70 71#include "elf/mips.h" 72 73#ifndef ECOFF_DEBUGGING 74#define NO_ECOFF_DEBUGGING 75#define ECOFF_DEBUGGING 0 76#endif 77 78int mips_flag_mdebug = -1; 79 80/* Control generation of .pdr sections. Off by default on IRIX: the native 81 linker doesn't know about and discards them, but relocations against them 82 remain, leading to rld crashes. */ 83#ifdef TE_IRIX 84int mips_flag_pdr = FALSE; 85#else 86int mips_flag_pdr = TRUE; 87#endif 88 89#include "ecoff.h" 90 91static char *mips_regmask_frag; 92static char *mips_flags_frag; 93 94#define ZERO 0 95#define ATREG 1 96#define S0 16 97#define S7 23 98#define TREG 24 99#define PIC_CALL_REG 25 100#define KT0 26 101#define KT1 27 102#define GP 28 103#define SP 29 104#define FP 30 105#define RA 31 106 107#define ILLEGAL_REG (32) 108 109#define AT mips_opts.at 110 111extern int target_big_endian; 112 113/* The name of the readonly data section. */ 114#define RDATA_SECTION_NAME ".rodata" 115 116/* Ways in which an instruction can be "appended" to the output. */ 117enum append_method { 118 /* Just add it normally. */ 119 APPEND_ADD, 120 121 /* Add it normally and then add a nop. */ 122 APPEND_ADD_WITH_NOP, 123 124 /* Turn an instruction with a delay slot into a "compact" version. */ 125 APPEND_ADD_COMPACT, 126 127 /* Insert the instruction before the last one. */ 128 APPEND_SWAP 129}; 130 131/* Information about an instruction, including its format, operands 132 and fixups. */ 133struct mips_cl_insn 134{ 135 /* The opcode's entry in mips_opcodes or mips16_opcodes. */ 136 const struct mips_opcode *insn_mo; 137 138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is 139 a copy of INSN_MO->match with the operands filled in. If we have 140 decided to use an extended MIPS16 instruction, this includes the 141 extension. */ 142 unsigned long insn_opcode; 143 144 /* The frag that contains the instruction. */ 145 struct frag *frag; 146 147 /* The offset into FRAG of the first instruction byte. */ 148 long where; 149 150 /* The relocs associated with the instruction, if any. */ 151 fixS *fixp[3]; 152 153 /* True if this entry cannot be moved from its current position. */ 154 unsigned int fixed_p : 1; 155 156 /* True if this instruction occurred in a .set noreorder block. */ 157 unsigned int noreorder_p : 1; 158 159 /* True for mips16 instructions that jump to an absolute address. */ 160 unsigned int mips16_absolute_jump_p : 1; 161 162 /* True if this instruction is complete. */ 163 unsigned int complete_p : 1; 164 165 /* True if this instruction is cleared from history by unconditional 166 branch. */ 167 unsigned int cleared_p : 1; 168}; 169 170/* The ABI to use. */ 171enum mips_abi_level 172{ 173 NO_ABI = 0, 174 O32_ABI, 175 O64_ABI, 176 N32_ABI, 177 N64_ABI, 178 EABI_ABI 179}; 180 181/* MIPS ABI we are using for this output file. */ 182static enum mips_abi_level mips_abi = NO_ABI; 183 184/* Whether or not we have code that can call pic code. */ 185int mips_abicalls = FALSE; 186 187/* Whether or not we have code which can be put into a shared 188 library. */ 189static bfd_boolean mips_in_shared = TRUE; 190 191/* This is the set of options which may be modified by the .set 192 pseudo-op. We use a struct so that .set push and .set pop are more 193 reliable. */ 194 195struct mips_set_options 196{ 197 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 198 if it has not been initialized. Changed by `.set mipsN', and the 199 -mipsN command line option, and the default CPU. */ 200 int isa; 201 /* Enabled Application Specific Extensions (ASEs). Changed by `.set 202 <asename>', by command line options, and based on the default 203 architecture. */ 204 int ase; 205 /* Whether we are assembling for the mips16 processor. 0 if we are 206 not, 1 if we are, and -1 if the value has not been initialized. 207 Changed by `.set mips16' and `.set nomips16', and the -mips16 and 208 -nomips16 command line options, and the default CPU. */ 209 int mips16; 210 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not, 211 1 if we are, and -1 if the value has not been initialized. Changed 212 by `.set micromips' and `.set nomicromips', and the -mmicromips 213 and -mno-micromips command line options, and the default CPU. */ 214 int micromips; 215 /* Non-zero if we should not reorder instructions. Changed by `.set 216 reorder' and `.set noreorder'. */ 217 int noreorder; 218 /* Non-zero if we should not permit the register designated "assembler 219 temporary" to be used in instructions. The value is the register 220 number, normally $at ($1). Changed by `.set at=REG', `.set noat' 221 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */ 222 unsigned int at; 223 /* Non-zero if we should warn when a macro instruction expands into 224 more than one machine instruction. Changed by `.set nomacro' and 225 `.set macro'. */ 226 int warn_about_macros; 227 /* Non-zero if we should not move instructions. Changed by `.set 228 move', `.set volatile', `.set nomove', and `.set novolatile'. */ 229 int nomove; 230 /* Non-zero if we should not optimize branches by moving the target 231 of the branch into the delay slot. Actually, we don't perform 232 this optimization anyhow. Changed by `.set bopt' and `.set 233 nobopt'. */ 234 int nobopt; 235 /* Non-zero if we should not autoextend mips16 instructions. 236 Changed by `.set autoextend' and `.set noautoextend'. */ 237 int noautoextend; 238 /* True if we should only emit 32-bit microMIPS instructions. 239 Changed by `.set insn32' and `.set noinsn32', and the -minsn32 240 and -mno-insn32 command line options. */ 241 bfd_boolean insn32; 242 /* Restrict general purpose registers and floating point registers 243 to 32 bit. This is initially determined when -mgp32 or -mfp32 244 is passed but can changed if the assembler code uses .set mipsN. */ 245 int gp; 246 int fp; 247 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march 248 command line option, and the default CPU. */ 249 int arch; 250 /* True if ".set sym32" is in effect. */ 251 bfd_boolean sym32; 252 /* True if floating-point operations are not allowed. Changed by .set 253 softfloat or .set hardfloat, by command line options -msoft-float or 254 -mhard-float. The default is false. */ 255 bfd_boolean soft_float; 256 257 /* True if only single-precision floating-point operations are allowed. 258 Changed by .set singlefloat or .set doublefloat, command-line options 259 -msingle-float or -mdouble-float. The default is false. */ 260 bfd_boolean single_float; 261 262 /* 1 if single-precision operations on odd-numbered registers are 263 allowed. */ 264 int oddspreg; 265}; 266 267/* Specifies whether module level options have been checked yet. */ 268static bfd_boolean file_mips_opts_checked = FALSE; 269 270/* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the 271 value has not been initialized. Changed by `.nan legacy' and 272 `.nan 2008', and the -mnan=legacy and -mnan=2008 command line 273 options, and the default CPU. */ 274static int mips_nan2008 = -1; 275 276/* This is the struct we use to hold the module level set of options. 277 Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and 278 fp fields to -1 to indicate that they have not been initialized. */ 279 280static struct mips_set_options file_mips_opts = 281{ 282 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1, 283 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, 284 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE, 285 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, 286 /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1 287}; 288 289/* This is similar to file_mips_opts, but for the current set of options. */ 290 291static struct mips_set_options mips_opts = 292{ 293 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1, 294 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, 295 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE, 296 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, 297 /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1 298}; 299 300/* Which bits of file_ase were explicitly set or cleared by ASE options. */ 301static unsigned int file_ase_explicit; 302 303/* These variables are filled in with the masks of registers used. 304 The object format code reads them and puts them in the appropriate 305 place. */ 306unsigned long mips_gprmask; 307unsigned long mips_cprmask[4]; 308 309/* True if any MIPS16 code was produced. */ 310static int file_ase_mips16; 311 312#define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ 313 || mips_opts.isa == ISA_MIPS32R2 \ 314 || mips_opts.isa == ISA_MIPS32R3 \ 315 || mips_opts.isa == ISA_MIPS32R5 \ 316 || mips_opts.isa == ISA_MIPS64 \ 317 || mips_opts.isa == ISA_MIPS64R2 \ 318 || mips_opts.isa == ISA_MIPS64R3 \ 319 || mips_opts.isa == ISA_MIPS64R5) 320 321/* True if any microMIPS code was produced. */ 322static int file_ase_micromips; 323 324/* True if we want to create R_MIPS_JALR for jalr $25. */ 325#ifdef TE_IRIX 326#define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI 327#else 328/* As a GNU extension, we use R_MIPS_JALR for o32 too. However, 329 because there's no place for any addend, the only acceptable 330 expression is a bare symbol. */ 331#define MIPS_JALR_HINT_P(EXPR) \ 332 (!HAVE_IN_PLACE_ADDENDS \ 333 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0)) 334#endif 335 336/* The argument of the -march= flag. The architecture we are assembling. */ 337static const char *mips_arch_string; 338 339/* The argument of the -mtune= flag. The architecture for which we 340 are optimizing. */ 341static int mips_tune = CPU_UNKNOWN; 342static const char *mips_tune_string; 343 344/* True when generating 32-bit code for a 64-bit processor. */ 345static int mips_32bitmode = 0; 346 347/* True if the given ABI requires 32-bit registers. */ 348#define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) 349 350/* Likewise 64-bit registers. */ 351#define ABI_NEEDS_64BIT_REGS(ABI) \ 352 ((ABI) == N32_ABI \ 353 || (ABI) == N64_ABI \ 354 || (ABI) == O64_ABI) 355 356#define ISA_IS_R6(ISA) \ 357 ((ISA) == ISA_MIPS32R6 \ 358 || (ISA) == ISA_MIPS64R6) 359 360/* Return true if ISA supports 64 bit wide gp registers. */ 361#define ISA_HAS_64BIT_REGS(ISA) \ 362 ((ISA) == ISA_MIPS3 \ 363 || (ISA) == ISA_MIPS4 \ 364 || (ISA) == ISA_MIPS5 \ 365 || (ISA) == ISA_MIPS64 \ 366 || (ISA) == ISA_MIPS64R2 \ 367 || (ISA) == ISA_MIPS64R3 \ 368 || (ISA) == ISA_MIPS64R5 \ 369 || (ISA) == ISA_MIPS64R6) 370 371/* Return true if ISA supports 64 bit wide float registers. */ 372#define ISA_HAS_64BIT_FPRS(ISA) \ 373 ((ISA) == ISA_MIPS3 \ 374 || (ISA) == ISA_MIPS4 \ 375 || (ISA) == ISA_MIPS5 \ 376 || (ISA) == ISA_MIPS32R2 \ 377 || (ISA) == ISA_MIPS32R3 \ 378 || (ISA) == ISA_MIPS32R5 \ 379 || (ISA) == ISA_MIPS32R6 \ 380 || (ISA) == ISA_MIPS64 \ 381 || (ISA) == ISA_MIPS64R2 \ 382 || (ISA) == ISA_MIPS64R3 \ 383 || (ISA) == ISA_MIPS64R5 \ 384 || (ISA) == ISA_MIPS64R6) 385 386/* Return true if ISA supports 64-bit right rotate (dror et al.) 387 instructions. */ 388#define ISA_HAS_DROR(ISA) \ 389 ((ISA) == ISA_MIPS64R2 \ 390 || (ISA) == ISA_MIPS64R3 \ 391 || (ISA) == ISA_MIPS64R5 \ 392 || (ISA) == ISA_MIPS64R6 \ 393 || (mips_opts.micromips \ 394 && ISA_HAS_64BIT_REGS (ISA)) \ 395 ) 396 397/* Return true if ISA supports 32-bit right rotate (ror et al.) 398 instructions. */ 399#define ISA_HAS_ROR(ISA) \ 400 ((ISA) == ISA_MIPS32R2 \ 401 || (ISA) == ISA_MIPS32R3 \ 402 || (ISA) == ISA_MIPS32R5 \ 403 || (ISA) == ISA_MIPS32R6 \ 404 || (ISA) == ISA_MIPS64R2 \ 405 || (ISA) == ISA_MIPS64R3 \ 406 || (ISA) == ISA_MIPS64R5 \ 407 || (ISA) == ISA_MIPS64R6 \ 408 || (mips_opts.ase & ASE_SMARTMIPS) \ 409 || mips_opts.micromips \ 410 ) 411 412/* Return true if ISA supports single-precision floats in odd registers. */ 413#define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\ 414 (((ISA) == ISA_MIPS32 \ 415 || (ISA) == ISA_MIPS32R2 \ 416 || (ISA) == ISA_MIPS32R3 \ 417 || (ISA) == ISA_MIPS32R5 \ 418 || (ISA) == ISA_MIPS32R6 \ 419 || (ISA) == ISA_MIPS64 \ 420 || (ISA) == ISA_MIPS64R2 \ 421 || (ISA) == ISA_MIPS64R3 \ 422 || (ISA) == ISA_MIPS64R5 \ 423 || (ISA) == ISA_MIPS64R6 \ 424 || (CPU) == CPU_R5900) \ 425 && (CPU) != CPU_LOONGSON_3A) 426 427/* Return true if ISA supports move to/from high part of a 64-bit 428 floating-point register. */ 429#define ISA_HAS_MXHC1(ISA) \ 430 ((ISA) == ISA_MIPS32R2 \ 431 || (ISA) == ISA_MIPS32R3 \ 432 || (ISA) == ISA_MIPS32R5 \ 433 || (ISA) == ISA_MIPS32R6 \ 434 || (ISA) == ISA_MIPS64R2 \ 435 || (ISA) == ISA_MIPS64R3 \ 436 || (ISA) == ISA_MIPS64R5 \ 437 || (ISA) == ISA_MIPS64R6) 438 439/* Return true if ISA supports legacy NAN. */ 440#define ISA_HAS_LEGACY_NAN(ISA) \ 441 ((ISA) == ISA_MIPS1 \ 442 || (ISA) == ISA_MIPS2 \ 443 || (ISA) == ISA_MIPS3 \ 444 || (ISA) == ISA_MIPS4 \ 445 || (ISA) == ISA_MIPS5 \ 446 || (ISA) == ISA_MIPS32 \ 447 || (ISA) == ISA_MIPS32R2 \ 448 || (ISA) == ISA_MIPS32R3 \ 449 || (ISA) == ISA_MIPS32R5 \ 450 || (ISA) == ISA_MIPS64 \ 451 || (ISA) == ISA_MIPS64R2 \ 452 || (ISA) == ISA_MIPS64R3 \ 453 || (ISA) == ISA_MIPS64R5) 454 455#define GPR_SIZE \ 456 (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \ 457 ? 32 \ 458 : mips_opts.gp) 459 460#define FPR_SIZE \ 461 (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \ 462 ? 32 \ 463 : mips_opts.fp) 464 465#define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) 466 467#define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) 468 469/* True if relocations are stored in-place. */ 470#define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) 471 472/* The ABI-derived address size. */ 473#define HAVE_64BIT_ADDRESSES \ 474 (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) 475#define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) 476 477/* The size of symbolic constants (i.e., expressions of the form 478 "SYMBOL" or "SYMBOL + OFFSET"). */ 479#define HAVE_32BIT_SYMBOLS \ 480 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) 481#define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) 482 483/* Addresses are loaded in different ways, depending on the address size 484 in use. The n32 ABI Documentation also mandates the use of additions 485 with overflow checking, but existing implementations don't follow it. */ 486#define ADDRESS_ADD_INSN \ 487 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") 488 489#define ADDRESS_ADDI_INSN \ 490 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") 491 492#define ADDRESS_LOAD_INSN \ 493 (HAVE_32BIT_ADDRESSES ? "lw" : "ld") 494 495#define ADDRESS_STORE_INSN \ 496 (HAVE_32BIT_ADDRESSES ? "sw" : "sd") 497 498/* Return true if the given CPU supports the MIPS16 ASE. */ 499#define CPU_HAS_MIPS16(cpu) \ 500 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ 501 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) 502 503/* Return true if the given CPU supports the microMIPS ASE. */ 504#define CPU_HAS_MICROMIPS(cpu) 0 505 506/* True if CPU has a dror instruction. */ 507#define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) 508 509/* True if CPU has a ror instruction. */ 510#define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) 511 512/* True if CPU is in the Octeon family */ 513#define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \ 514 || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3) 515 516/* True if CPU has seq/sne and seqi/snei instructions. */ 517#define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU)) 518 519/* True, if CPU has support for ldc1 and sdc1. */ 520#define CPU_HAS_LDC1_SDC1(CPU) \ 521 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900)) 522 523/* True if mflo and mfhi can be immediately followed by instructions 524 which write to the HI and LO registers. 525 526 According to MIPS specifications, MIPS ISAs I, II, and III need 527 (at least) two instructions between the reads of HI/LO and 528 instructions which write them, and later ISAs do not. Contradicting 529 the MIPS specifications, some MIPS IV processor user manuals (e.g. 530 the UM for the NEC Vr5000) document needing the instructions between 531 HI/LO reads and writes, as well. Therefore, we declare only MIPS32, 532 MIPS64 and later ISAs to have the interlocks, plus any specific 533 earlier-ISA CPUs for which CPU documentation declares that the 534 instructions are really interlocked. */ 535#define hilo_interlocks \ 536 (mips_opts.isa == ISA_MIPS32 \ 537 || mips_opts.isa == ISA_MIPS32R2 \ 538 || mips_opts.isa == ISA_MIPS32R3 \ 539 || mips_opts.isa == ISA_MIPS32R5 \ 540 || mips_opts.isa == ISA_MIPS32R6 \ 541 || mips_opts.isa == ISA_MIPS64 \ 542 || mips_opts.isa == ISA_MIPS64R2 \ 543 || mips_opts.isa == ISA_MIPS64R3 \ 544 || mips_opts.isa == ISA_MIPS64R5 \ 545 || mips_opts.isa == ISA_MIPS64R6 \ 546 || mips_opts.arch == CPU_R4010 \ 547 || mips_opts.arch == CPU_R5900 \ 548 || mips_opts.arch == CPU_R10000 \ 549 || mips_opts.arch == CPU_R12000 \ 550 || mips_opts.arch == CPU_R14000 \ 551 || mips_opts.arch == CPU_R16000 \ 552 || mips_opts.arch == CPU_RM7000 \ 553 || mips_opts.arch == CPU_VR5500 \ 554 || mips_opts.micromips \ 555 ) 556 557/* Whether the processor uses hardware interlocks to protect reads 558 from the GPRs after they are loaded from memory, and thus does not 559 require nops to be inserted. This applies to instructions marked 560 INSN_LOAD_MEMORY. These nops are only required at MIPS ISA 561 level I and microMIPS mode instructions are always interlocked. */ 562#define gpr_interlocks \ 563 (mips_opts.isa != ISA_MIPS1 \ 564 || mips_opts.arch == CPU_R3900 \ 565 || mips_opts.arch == CPU_R5900 \ 566 || mips_opts.micromips \ 567 ) 568 569/* Whether the processor uses hardware interlocks to avoid delays 570 required by coprocessor instructions, and thus does not require 571 nops to be inserted. This applies to instructions marked 572 INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between 573 instructions marked INSN_WRITE_COND_CODE and ones marked 574 INSN_READ_COND_CODE. These nops are only required at MIPS ISA 575 levels I, II, and III and microMIPS mode instructions are always 576 interlocked. */ 577/* Itbl support may require additional care here. */ 578#define cop_interlocks \ 579 ((mips_opts.isa != ISA_MIPS1 \ 580 && mips_opts.isa != ISA_MIPS2 \ 581 && mips_opts.isa != ISA_MIPS3) \ 582 || mips_opts.arch == CPU_R4300 \ 583 || mips_opts.micromips \ 584 ) 585 586/* Whether the processor uses hardware interlocks to protect reads 587 from coprocessor registers after they are loaded from memory, and 588 thus does not require nops to be inserted. This applies to 589 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only 590 requires at MIPS ISA level I and microMIPS mode instructions are 591 always interlocked. */ 592#define cop_mem_interlocks \ 593 (mips_opts.isa != ISA_MIPS1 \ 594 || mips_opts.micromips \ 595 ) 596 597/* Is this a mfhi or mflo instruction? */ 598#define MF_HILO_INSN(PINFO) \ 599 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) 600 601/* Whether code compression (either of the MIPS16 or the microMIPS ASEs) 602 has been selected. This implies, in particular, that addresses of text 603 labels have their LSB set. */ 604#define HAVE_CODE_COMPRESSION \ 605 ((mips_opts.mips16 | mips_opts.micromips) != 0) 606 607/* The minimum and maximum signed values that can be stored in a GPR. */ 608#define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1)) 609#define GPR_SMIN (-GPR_SMAX - 1) 610 611/* MIPS PIC level. */ 612 613enum mips_pic_level mips_pic; 614 615/* 1 if we should generate 32 bit offsets from the $gp register in 616 SVR4_PIC mode. Currently has no meaning in other modes. */ 617static int mips_big_got = 0; 618 619/* 1 if trap instructions should used for overflow rather than break 620 instructions. */ 621static int mips_trap = 0; 622 623/* 1 if double width floating point constants should not be constructed 624 by assembling two single width halves into two single width floating 625 point registers which just happen to alias the double width destination 626 register. On some architectures this aliasing can be disabled by a bit 627 in the status register, and the setting of this bit cannot be determined 628 automatically at assemble time. */ 629static int mips_disable_float_construction; 630 631/* Non-zero if any .set noreorder directives were used. */ 632 633static int mips_any_noreorder; 634 635/* Non-zero if nops should be inserted when the register referenced in 636 an mfhi/mflo instruction is read in the next two instructions. */ 637static int mips_7000_hilo_fix; 638 639/* The size of objects in the small data section. */ 640static unsigned int g_switch_value = 8; 641/* Whether the -G option was used. */ 642static int g_switch_seen = 0; 643 644#define N_RMASK 0xc4 645#define N_VFP 0xd4 646 647/* If we can determine in advance that GP optimization won't be 648 possible, we can skip the relaxation stuff that tries to produce 649 GP-relative references. This makes delay slot optimization work 650 better. 651 652 This function can only provide a guess, but it seems to work for 653 gcc output. It needs to guess right for gcc, otherwise gcc 654 will put what it thinks is a GP-relative instruction in a branch 655 delay slot. 656 657 I don't know if a fix is needed for the SVR4_PIC mode. I've only 658 fixed it for the non-PIC mode. KR 95/04/07 */ 659static int nopic_need_relax (symbolS *, int); 660 661/* handle of the OPCODE hash table */ 662static struct hash_control *op_hash = NULL; 663 664/* The opcode hash table we use for the mips16. */ 665static struct hash_control *mips16_op_hash = NULL; 666 667/* The opcode hash table we use for the microMIPS ASE. */ 668static struct hash_control *micromips_op_hash = NULL; 669 670/* This array holds the chars that always start a comment. If the 671 pre-processor is disabled, these aren't very useful */ 672const char comment_chars[] = "#"; 673 674/* This array holds the chars that only start a comment at the beginning of 675 a line. If the line seems to have the form '# 123 filename' 676 .line and .file directives will appear in the pre-processed output */ 677/* Note that input_file.c hand checks for '#' at the beginning of the 678 first line of the input file. This is because the compiler outputs 679 #NO_APP at the beginning of its output. */ 680/* Also note that C style comments are always supported. */ 681const char line_comment_chars[] = "#"; 682 683/* This array holds machine specific line separator characters. */ 684const char line_separator_chars[] = ";"; 685 686/* Chars that can be used to separate mant from exp in floating point nums */ 687const char EXP_CHARS[] = "eE"; 688 689/* Chars that mean this number is a floating point constant */ 690/* As in 0f12.456 */ 691/* or 0d1.2345e12 */ 692const char FLT_CHARS[] = "rRsSfFdDxXpP"; 693 694/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be 695 changed in read.c . Ideally it shouldn't have to know about it at all, 696 but nothing is ideal around here. 697 */ 698 699/* Types of printf format used for instruction-related error messages. 700 "I" means int ("%d") and "S" means string ("%s"). */ 701enum mips_insn_error_format { 702 ERR_FMT_PLAIN, 703 ERR_FMT_I, 704 ERR_FMT_SS, 705}; 706 707/* Information about an error that was found while assembling the current 708 instruction. */ 709struct mips_insn_error { 710 /* We sometimes need to match an instruction against more than one 711 opcode table entry. Errors found during this matching are reported 712 against a particular syntactic argument rather than against the 713 instruction as a whole. We grade these messages so that errors 714 against argument N have a greater priority than an error against 715 any argument < N, since the former implies that arguments up to N 716 were acceptable and that the opcode entry was therefore a closer match. 717 If several matches report an error against the same argument, 718 we only use that error if it is the same in all cases. 719 720 min_argnum is the minimum argument number for which an error message 721 should be accepted. It is 0 if MSG is against the instruction as 722 a whole. */ 723 int min_argnum; 724 725 /* The printf()-style message, including its format and arguments. */ 726 enum mips_insn_error_format format; 727 const char *msg; 728 union { 729 int i; 730 const char *ss[2]; 731 } u; 732}; 733 734/* The error that should be reported for the current instruction. */ 735static struct mips_insn_error insn_error; 736 737static int auto_align = 1; 738 739/* When outputting SVR4 PIC code, the assembler needs to know the 740 offset in the stack frame from which to restore the $gp register. 741 This is set by the .cprestore pseudo-op, and saved in this 742 variable. */ 743static offsetT mips_cprestore_offset = -1; 744 745/* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some 746 more optimizations, it can use a register value instead of a memory-saved 747 offset and even an other register than $gp as global pointer. */ 748static offsetT mips_cpreturn_offset = -1; 749static int mips_cpreturn_register = -1; 750static int mips_gp_register = GP; 751static int mips_gprel_offset = 0; 752 753/* Whether mips_cprestore_offset has been set in the current function 754 (or whether it has already been warned about, if not). */ 755static int mips_cprestore_valid = 0; 756 757/* This is the register which holds the stack frame, as set by the 758 .frame pseudo-op. This is needed to implement .cprestore. */ 759static int mips_frame_reg = SP; 760 761/* Whether mips_frame_reg has been set in the current function 762 (or whether it has already been warned about, if not). */ 763static int mips_frame_reg_valid = 0; 764 765/* To output NOP instructions correctly, we need to keep information 766 about the previous two instructions. */ 767 768/* Whether we are optimizing. The default value of 2 means to remove 769 unneeded NOPs and swap branch instructions when possible. A value 770 of 1 means to not swap branches. A value of 0 means to always 771 insert NOPs. */ 772static int mips_optimize = 2; 773 774/* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is 775 equivalent to seeing no -g option at all. */ 776static int mips_debug = 0; 777 778/* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ 779#define MAX_VR4130_NOPS 4 780 781/* The maximum number of NOPs needed to fill delay slots. */ 782#define MAX_DELAY_NOPS 2 783 784/* The maximum number of NOPs needed for any purpose. */ 785#define MAX_NOPS 4 786 787/* A list of previous instructions, with index 0 being the most recent. 788 We need to look back MAX_NOPS instructions when filling delay slots 789 or working around processor errata. We need to look back one 790 instruction further if we're thinking about using history[0] to 791 fill a branch delay slot. */ 792static struct mips_cl_insn history[1 + MAX_NOPS]; 793 794/* Arrays of operands for each instruction. */ 795#define MAX_OPERANDS 6 796struct mips_operand_array { 797 const struct mips_operand *operand[MAX_OPERANDS]; 798}; 799static struct mips_operand_array *mips_operands; 800static struct mips_operand_array *mips16_operands; 801static struct mips_operand_array *micromips_operands; 802 803/* Nop instructions used by emit_nop. */ 804static struct mips_cl_insn nop_insn; 805static struct mips_cl_insn mips16_nop_insn; 806static struct mips_cl_insn micromips_nop16_insn; 807static struct mips_cl_insn micromips_nop32_insn; 808 809/* The appropriate nop for the current mode. */ 810#define NOP_INSN (mips_opts.mips16 \ 811 ? &mips16_nop_insn \ 812 : (mips_opts.micromips \ 813 ? (mips_opts.insn32 \ 814 ? µmips_nop32_insn \ 815 : µmips_nop16_insn) \ 816 : &nop_insn)) 817 818/* The size of NOP_INSN in bytes. */ 819#define NOP_INSN_SIZE ((mips_opts.mips16 \ 820 || (mips_opts.micromips && !mips_opts.insn32)) \ 821 ? 2 : 4) 822 823/* If this is set, it points to a frag holding nop instructions which 824 were inserted before the start of a noreorder section. If those 825 nops turn out to be unnecessary, the size of the frag can be 826 decreased. */ 827static fragS *prev_nop_frag; 828 829/* The number of nop instructions we created in prev_nop_frag. */ 830static int prev_nop_frag_holds; 831 832/* The number of nop instructions that we know we need in 833 prev_nop_frag. */ 834static int prev_nop_frag_required; 835 836/* The number of instructions we've seen since prev_nop_frag. */ 837static int prev_nop_frag_since; 838 839/* Relocations against symbols are sometimes done in two parts, with a HI 840 relocation and a LO relocation. Each relocation has only 16 bits of 841 space to store an addend. This means that in order for the linker to 842 handle carries correctly, it must be able to locate both the HI and 843 the LO relocation. This means that the relocations must appear in 844 order in the relocation table. 845 846 In order to implement this, we keep track of each unmatched HI 847 relocation. We then sort them so that they immediately precede the 848 corresponding LO relocation. */ 849 850struct mips_hi_fixup 851{ 852 /* Next HI fixup. */ 853 struct mips_hi_fixup *next; 854 /* This fixup. */ 855 fixS *fixp; 856 /* The section this fixup is in. */ 857 segT seg; 858}; 859 860/* The list of unmatched HI relocs. */ 861 862static struct mips_hi_fixup *mips_hi_fixup_list; 863 864/* The frag containing the last explicit relocation operator. 865 Null if explicit relocations have not been used. */ 866 867static fragS *prev_reloc_op_frag; 868 869/* Map mips16 register numbers to normal MIPS register numbers. */ 870 871static const unsigned int mips16_to_32_reg_map[] = 872{ 873 16, 17, 2, 3, 4, 5, 6, 7 874}; 875 876/* Map microMIPS register numbers to normal MIPS register numbers. */ 877 878#define micromips_to_32_reg_d_map mips16_to_32_reg_map 879 880/* The microMIPS registers with type h. */ 881static const unsigned int micromips_to_32_reg_h_map1[] = 882{ 883 5, 5, 6, 4, 4, 4, 4, 4 884}; 885static const unsigned int micromips_to_32_reg_h_map2[] = 886{ 887 6, 7, 7, 21, 22, 5, 6, 7 888}; 889 890/* The microMIPS registers with type m. */ 891static const unsigned int micromips_to_32_reg_m_map[] = 892{ 893 0, 17, 2, 3, 16, 18, 19, 20 894}; 895 896#define micromips_to_32_reg_n_map micromips_to_32_reg_m_map 897 898/* Classifies the kind of instructions we're interested in when 899 implementing -mfix-vr4120. */ 900enum fix_vr4120_class 901{ 902 FIX_VR4120_MACC, 903 FIX_VR4120_DMACC, 904 FIX_VR4120_MULT, 905 FIX_VR4120_DMULT, 906 FIX_VR4120_DIV, 907 FIX_VR4120_MTHILO, 908 NUM_FIX_VR4120_CLASSES 909}; 910 911/* ...likewise -mfix-loongson2f-jump. */ 912static bfd_boolean mips_fix_loongson2f_jump; 913 914/* ...likewise -mfix-loongson2f-nop. */ 915static bfd_boolean mips_fix_loongson2f_nop; 916 917/* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */ 918static bfd_boolean mips_fix_loongson2f; 919 920/* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if 921 there must be at least one other instruction between an instruction 922 of type X and an instruction of type Y. */ 923static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; 924 925/* True if -mfix-vr4120 is in force. */ 926static int mips_fix_vr4120; 927 928/* ...likewise -mfix-vr4130. */ 929static int mips_fix_vr4130; 930 931/* ...likewise -mfix-24k. */ 932static int mips_fix_24k; 933 934/* ...likewise -mfix-rm7000 */ 935static int mips_fix_rm7000; 936 937/* ...likewise -mfix-cn63xxp1 */ 938static bfd_boolean mips_fix_cn63xxp1; 939 940/* We don't relax branches by default, since this causes us to expand 941 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we 942 fail to compute the offset before expanding the macro to the most 943 efficient expansion. */ 944 945static int mips_relax_branch; 946 947/* TRUE if checks are suppressed for invalid branches between ISA modes. 948 Needed for broken assembly produced by some GCC versions and some 949 sloppy code out there, where branches to data labels are present. */ 950static bfd_boolean mips_ignore_branch_isa; 951 952/* The expansion of many macros depends on the type of symbol that 953 they refer to. For example, when generating position-dependent code, 954 a macro that refers to a symbol may have two different expansions, 955 one which uses GP-relative addresses and one which uses absolute 956 addresses. When generating SVR4-style PIC, a macro may have 957 different expansions for local and global symbols. 958 959 We handle these situations by generating both sequences and putting 960 them in variant frags. In position-dependent code, the first sequence 961 will be the GP-relative one and the second sequence will be the 962 absolute one. In SVR4 PIC, the first sequence will be for global 963 symbols and the second will be for local symbols. 964 965 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and 966 SECOND are the lengths of the two sequences in bytes. These fields 967 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, 968 the subtype has the following flags: 969 970 RELAX_USE_SECOND 971 Set if it has been decided that we should use the second 972 sequence instead of the first. 973 974 RELAX_SECOND_LONGER 975 Set in the first variant frag if the macro's second implementation 976 is longer than its first. This refers to the macro as a whole, 977 not an individual relaxation. 978 979 RELAX_NOMACRO 980 Set in the first variant frag if the macro appeared in a .set nomacro 981 block and if one alternative requires a warning but the other does not. 982 983 RELAX_DELAY_SLOT 984 Like RELAX_NOMACRO, but indicates that the macro appears in a branch 985 delay slot. 986 987 RELAX_DELAY_SLOT_16BIT 988 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a 989 16-bit instruction. 990 991 RELAX_DELAY_SLOT_SIZE_FIRST 992 Like RELAX_DELAY_SLOT, but indicates that the first implementation of 993 the macro is of the wrong size for the branch delay slot. 994 995 RELAX_DELAY_SLOT_SIZE_SECOND 996 Like RELAX_DELAY_SLOT, but indicates that the second implementation of 997 the macro is of the wrong size for the branch delay slot. 998 999 The frag's "opcode" points to the first fixup for relaxable code. 1000 1001 Relaxable macros are generated using a sequence such as: 1002 1003 relax_start (SYMBOL); 1004 ... generate first expansion ... 1005 relax_switch (); 1006 ... generate second expansion ... 1007 relax_end (); 1008 1009 The code and fixups for the unwanted alternative are discarded 1010 by md_convert_frag. */ 1011#define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) 1012 1013#define RELAX_FIRST(X) (((X) >> 8) & 0xff) 1014#define RELAX_SECOND(X) ((X) & 0xff) 1015#define RELAX_USE_SECOND 0x10000 1016#define RELAX_SECOND_LONGER 0x20000 1017#define RELAX_NOMACRO 0x40000 1018#define RELAX_DELAY_SLOT 0x80000 1019#define RELAX_DELAY_SLOT_16BIT 0x100000 1020#define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000 1021#define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000 1022 1023/* Branch without likely bit. If label is out of range, we turn: 1024 1025 beq reg1, reg2, label 1026 delay slot 1027 1028 into 1029 1030 bne reg1, reg2, 0f 1031 nop 1032 j label 1033 0: delay slot 1034 1035 with the following opcode replacements: 1036 1037 beq <-> bne 1038 blez <-> bgtz 1039 bltz <-> bgez 1040 bc1f <-> bc1t 1041 1042 bltzal <-> bgezal (with jal label instead of j label) 1043 1044 Even though keeping the delay slot instruction in the delay slot of 1045 the branch would be more efficient, it would be very tricky to do 1046 correctly, because we'd have to introduce a variable frag *after* 1047 the delay slot instruction, and expand that instead. Let's do it 1048 the easy way for now, even if the branch-not-taken case now costs 1049 one additional instruction. Out-of-range branches are not supposed 1050 to be common, anyway. 1051 1052 Branch likely. If label is out of range, we turn: 1053 1054 beql reg1, reg2, label 1055 delay slot (annulled if branch not taken) 1056 1057 into 1058 1059 beql reg1, reg2, 1f 1060 nop 1061 beql $0, $0, 2f 1062 nop 1063 1: j[al] label 1064 delay slot (executed only if branch taken) 1065 2: 1066 1067 It would be possible to generate a shorter sequence by losing the 1068 likely bit, generating something like: 1069 1070 bne reg1, reg2, 0f 1071 nop 1072 j[al] label 1073 delay slot (executed only if branch taken) 1074 0: 1075 1076 beql -> bne 1077 bnel -> beq 1078 blezl -> bgtz 1079 bgtzl -> blez 1080 bltzl -> bgez 1081 bgezl -> bltz 1082 bc1fl -> bc1t 1083 bc1tl -> bc1f 1084 1085 bltzall -> bgezal (with jal label instead of j label) 1086 bgezall -> bltzal (ditto) 1087 1088 1089 but it's not clear that it would actually improve performance. */ 1090#define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \ 1091 ((relax_substateT) \ 1092 (0xc0000000 \ 1093 | ((at) & 0x1f) \ 1094 | ((toofar) ? 0x20 : 0) \ 1095 | ((link) ? 0x40 : 0) \ 1096 | ((likely) ? 0x80 : 0) \ 1097 | ((uncond) ? 0x100 : 0))) 1098#define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) 1099#define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0) 1100#define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0) 1101#define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0) 1102#define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0) 1103#define RELAX_BRANCH_AT(i) ((i) & 0x1f) 1104 1105/* For mips16 code, we use an entirely different form of relaxation. 1106 mips16 supports two versions of most instructions which take 1107 immediate values: a small one which takes some small value, and a 1108 larger one which takes a 16 bit value. Since branches also follow 1109 this pattern, relaxing these values is required. 1110 1111 We can assemble both mips16 and normal MIPS code in a single 1112 object. Therefore, we need to support this type of relaxation at 1113 the same time that we support the relaxation described above. We 1114 use the high bit of the subtype field to distinguish these cases. 1115 1116 The information we store for this type of relaxation is the 1117 argument code found in the opcode file for this relocation, whether 1118 the user explicitly requested a small or extended form, and whether 1119 the relocation is in a jump or jal delay slot. That tells us the 1120 size of the value, and how it should be stored. We also store 1121 whether the fragment is considered to be extended or not. We also 1122 store whether this is known to be a branch to a different section, 1123 whether we have tried to relax this frag yet, and whether we have 1124 ever extended a PC relative fragment because of a shift count. */ 1125#define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ 1126 (0x80000000 \ 1127 | ((type) & 0xff) \ 1128 | ((small) ? 0x100 : 0) \ 1129 | ((ext) ? 0x200 : 0) \ 1130 | ((dslot) ? 0x400 : 0) \ 1131 | ((jal_dslot) ? 0x800 : 0)) 1132#define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) 1133#define RELAX_MIPS16_TYPE(i) ((i) & 0xff) 1134#define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) 1135#define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) 1136#define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) 1137#define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) 1138#define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) 1139#define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) 1140#define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) 1141#define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) 1142#define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) 1143#define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) 1144 1145/* For microMIPS code, we use relaxation similar to one we use for 1146 MIPS16 code. Some instructions that take immediate values support 1147 two encodings: a small one which takes some small value, and a 1148 larger one which takes a 16 bit value. As some branches also follow 1149 this pattern, relaxing these values is required. 1150 1151 We can assemble both microMIPS and normal MIPS code in a single 1152 object. Therefore, we need to support this type of relaxation at 1153 the same time that we support the relaxation described above. We 1154 use one of the high bits of the subtype field to distinguish these 1155 cases. 1156 1157 The information we store for this type of relaxation is the argument 1158 code found in the opcode file for this relocation, the register 1159 selected as the assembler temporary, whether in the 32-bit 1160 instruction mode, whether the branch is unconditional, whether it is 1161 compact, whether there is no delay-slot instruction available to fill 1162 in, whether it stores the link address implicitly in $ra, whether 1163 relaxation of out-of-range 32-bit branches to a sequence of 1164 instructions is enabled, and whether the displacement of a branch is 1165 too large to fit as an immediate argument of a 16-bit and a 32-bit 1166 branch, respectively. */ 1167#define RELAX_MICROMIPS_ENCODE(type, at, insn32, \ 1168 uncond, compact, link, nods, \ 1169 relax32, toofar16, toofar32) \ 1170 (0x40000000 \ 1171 | ((type) & 0xff) \ 1172 | (((at) & 0x1f) << 8) \ 1173 | ((insn32) ? 0x2000 : 0) \ 1174 | ((uncond) ? 0x4000 : 0) \ 1175 | ((compact) ? 0x8000 : 0) \ 1176 | ((link) ? 0x10000 : 0) \ 1177 | ((nods) ? 0x20000 : 0) \ 1178 | ((relax32) ? 0x40000 : 0) \ 1179 | ((toofar16) ? 0x80000 : 0) \ 1180 | ((toofar32) ? 0x100000 : 0)) 1181#define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000) 1182#define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff) 1183#define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f) 1184#define RELAX_MICROMIPS_INSN32(i) (((i) & 0x2000) != 0) 1185#define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x4000) != 0) 1186#define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x8000) != 0) 1187#define RELAX_MICROMIPS_LINK(i) (((i) & 0x10000) != 0) 1188#define RELAX_MICROMIPS_NODS(i) (((i) & 0x20000) != 0) 1189#define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x40000) != 0) 1190 1191#define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x80000) != 0) 1192#define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x80000) 1193#define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x80000) 1194#define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x100000) != 0) 1195#define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x100000) 1196#define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x100000) 1197 1198/* Sign-extend 16-bit value X. */ 1199#define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000) 1200 1201/* Is the given value a sign-extended 32-bit value? */ 1202#define IS_SEXT_32BIT_NUM(x) \ 1203 (((x) &~ (offsetT) 0x7fffffff) == 0 \ 1204 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) 1205 1206/* Is the given value a sign-extended 16-bit value? */ 1207#define IS_SEXT_16BIT_NUM(x) \ 1208 (((x) &~ (offsetT) 0x7fff) == 0 \ 1209 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) 1210 1211/* Is the given value a sign-extended 12-bit value? */ 1212#define IS_SEXT_12BIT_NUM(x) \ 1213 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x)) 1214 1215/* Is the given value a sign-extended 9-bit value? */ 1216#define IS_SEXT_9BIT_NUM(x) \ 1217 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x)) 1218 1219/* Is the given value a zero-extended 32-bit value? Or a negated one? */ 1220#define IS_ZEXT_32BIT_NUM(x) \ 1221 (((x) &~ (offsetT) 0xffffffff) == 0 \ 1222 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) 1223 1224/* Extract bits MASK << SHIFT from STRUCT and shift them right 1225 SHIFT places. */ 1226#define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ 1227 (((STRUCT) >> (SHIFT)) & (MASK)) 1228 1229/* Extract the operand given by FIELD from mips_cl_insn INSN. */ 1230#define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \ 1231 (!(MICROMIPS) \ 1232 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \ 1233 : EXTRACT_BITS ((INSN).insn_opcode, \ 1234 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD)) 1235#define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ 1236 EXTRACT_BITS ((INSN).insn_opcode, \ 1237 MIPS16OP_MASK_##FIELD, \ 1238 MIPS16OP_SH_##FIELD) 1239 1240/* The MIPS16 EXTEND opcode, shifted left 16 places. */ 1241#define MIPS16_EXTEND (0xf000U << 16) 1242 1243/* Whether or not we are emitting a branch-likely macro. */ 1244static bfd_boolean emit_branch_likely_macro = FALSE; 1245 1246/* Global variables used when generating relaxable macros. See the 1247 comment above RELAX_ENCODE for more details about how relaxation 1248 is used. */ 1249static struct { 1250 /* 0 if we're not emitting a relaxable macro. 1251 1 if we're emitting the first of the two relaxation alternatives. 1252 2 if we're emitting the second alternative. */ 1253 int sequence; 1254 1255 /* The first relaxable fixup in the current frag. (In other words, 1256 the first fixup that refers to relaxable code.) */ 1257 fixS *first_fixup; 1258 1259 /* sizes[0] says how many bytes of the first alternative are stored in 1260 the current frag. Likewise sizes[1] for the second alternative. */ 1261 unsigned int sizes[2]; 1262 1263 /* The symbol on which the choice of sequence depends. */ 1264 symbolS *symbol; 1265} mips_relax; 1266 1267/* Global variables used to decide whether a macro needs a warning. */ 1268static struct { 1269 /* True if the macro is in a branch delay slot. */ 1270 bfd_boolean delay_slot_p; 1271 1272 /* Set to the length in bytes required if the macro is in a delay slot 1273 that requires a specific length of instruction, otherwise zero. */ 1274 unsigned int delay_slot_length; 1275 1276 /* For relaxable macros, sizes[0] is the length of the first alternative 1277 in bytes and sizes[1] is the length of the second alternative. 1278 For non-relaxable macros, both elements give the length of the 1279 macro in bytes. */ 1280 unsigned int sizes[2]; 1281 1282 /* For relaxable macros, first_insn_sizes[0] is the length of the first 1283 instruction of the first alternative in bytes and first_insn_sizes[1] 1284 is the length of the first instruction of the second alternative. 1285 For non-relaxable macros, both elements give the length of the first 1286 instruction in bytes. 1287 1288 Set to zero if we haven't yet seen the first instruction. */ 1289 unsigned int first_insn_sizes[2]; 1290 1291 /* For relaxable macros, insns[0] is the number of instructions for the 1292 first alternative and insns[1] is the number of instructions for the 1293 second alternative. 1294 1295 For non-relaxable macros, both elements give the number of 1296 instructions for the macro. */ 1297 unsigned int insns[2]; 1298 1299 /* The first variant frag for this macro. */ 1300 fragS *first_frag; 1301} mips_macro_warning; 1302 1303/* Prototypes for static functions. */ 1304 1305enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; 1306 1307static void append_insn 1308 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *, 1309 bfd_boolean expansionp); 1310static void mips_no_prev_insn (void); 1311static void macro_build (expressionS *, const char *, const char *, ...); 1312static void mips16_macro_build 1313 (expressionS *, const char *, const char *, va_list *); 1314static void load_register (int, expressionS *, int); 1315static void macro_start (void); 1316static void macro_end (void); 1317static void macro (struct mips_cl_insn *ip, char *str); 1318static void mips16_macro (struct mips_cl_insn * ip); 1319static void mips_ip (char *str, struct mips_cl_insn * ip); 1320static void mips16_ip (char *str, struct mips_cl_insn * ip); 1321static void mips16_immed 1322 (const char *, unsigned int, int, bfd_reloc_code_real_type, offsetT, 1323 unsigned int, unsigned long *); 1324static size_t my_getSmallExpression 1325 (expressionS *, bfd_reloc_code_real_type *, char *); 1326static void my_getExpression (expressionS *, char *); 1327static void s_align (int); 1328static void s_change_sec (int); 1329static void s_change_section (int); 1330static void s_cons (int); 1331static void s_float_cons (int); 1332static void s_mips_globl (int); 1333static void s_option (int); 1334static void s_mipsset (int); 1335static void s_abicalls (int); 1336static void s_cpload (int); 1337static void s_cpsetup (int); 1338static void s_cplocal (int); 1339static void s_cprestore (int); 1340static void s_cpreturn (int); 1341static void s_dtprelword (int); 1342static void s_dtpreldword (int); 1343static void s_tprelword (int); 1344static void s_tpreldword (int); 1345static void s_gpvalue (int); 1346static void s_gpword (int); 1347static void s_gpdword (int); 1348static void s_ehword (int); 1349static void s_cpadd (int); 1350static void s_insn (int); 1351static void s_nan (int); 1352static void s_module (int); 1353static void s_mips_ent (int); 1354static void s_mips_end (int); 1355static void s_mips_frame (int); 1356static void s_mips_mask (int reg_type); 1357static void s_mips_stab (int); 1358static void s_mips_weakext (int); 1359static void s_mips_file (int); 1360static void s_mips_loc (int); 1361static bfd_boolean pic_need_relax (symbolS *); 1362static int relaxed_branch_length (fragS *, asection *, int); 1363static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int); 1364static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int); 1365static void file_mips_check_options (void); 1366 1367/* Table and functions used to map between CPU/ISA names, and 1368 ISA levels, and CPU numbers. */ 1369 1370struct mips_cpu_info 1371{ 1372 const char *name; /* CPU or ISA name. */ 1373 int flags; /* MIPS_CPU_* flags. */ 1374 int ase; /* Set of ASEs implemented by the CPU. */ 1375 int isa; /* ISA level. */ 1376 int cpu; /* CPU number (default CPU if ISA). */ 1377}; 1378 1379#define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ 1380 1381static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); 1382static const struct mips_cpu_info *mips_cpu_info_from_isa (int); 1383static const struct mips_cpu_info *mips_cpu_info_from_arch (int); 1384 1385/* Command-line options. */ 1386const char *md_shortopts = "O::g::G:"; 1387 1388enum options 1389 { 1390 OPTION_MARCH = OPTION_MD_BASE, 1391 OPTION_MTUNE, 1392 OPTION_MIPS1, 1393 OPTION_MIPS2, 1394 OPTION_MIPS3, 1395 OPTION_MIPS4, 1396 OPTION_MIPS5, 1397 OPTION_MIPS32, 1398 OPTION_MIPS64, 1399 OPTION_MIPS32R2, 1400 OPTION_MIPS32R3, 1401 OPTION_MIPS32R5, 1402 OPTION_MIPS32R6, 1403 OPTION_MIPS64R2, 1404 OPTION_MIPS64R3, 1405 OPTION_MIPS64R5, 1406 OPTION_MIPS64R6, 1407 OPTION_MIPS16, 1408 OPTION_NO_MIPS16, 1409 OPTION_MIPS3D, 1410 OPTION_NO_MIPS3D, 1411 OPTION_MDMX, 1412 OPTION_NO_MDMX, 1413 OPTION_DSP, 1414 OPTION_NO_DSP, 1415 OPTION_MT, 1416 OPTION_NO_MT, 1417 OPTION_VIRT, 1418 OPTION_NO_VIRT, 1419 OPTION_MSA, 1420 OPTION_NO_MSA, 1421 OPTION_SMARTMIPS, 1422 OPTION_NO_SMARTMIPS, 1423 OPTION_DSPR2, 1424 OPTION_NO_DSPR2, 1425 OPTION_DSPR3, 1426 OPTION_NO_DSPR3, 1427 OPTION_EVA, 1428 OPTION_NO_EVA, 1429 OPTION_XPA, 1430 OPTION_NO_XPA, 1431 OPTION_MICROMIPS, 1432 OPTION_NO_MICROMIPS, 1433 OPTION_MCU, 1434 OPTION_NO_MCU, 1435 OPTION_COMPAT_ARCH_BASE, 1436 OPTION_M4650, 1437 OPTION_NO_M4650, 1438 OPTION_M4010, 1439 OPTION_NO_M4010, 1440 OPTION_M4100, 1441 OPTION_NO_M4100, 1442 OPTION_M3900, 1443 OPTION_NO_M3900, 1444 OPTION_M7000_HILO_FIX, 1445 OPTION_MNO_7000_HILO_FIX, 1446 OPTION_FIX_24K, 1447 OPTION_NO_FIX_24K, 1448 OPTION_FIX_RM7000, 1449 OPTION_NO_FIX_RM7000, 1450 OPTION_FIX_LOONGSON2F_JUMP, 1451 OPTION_NO_FIX_LOONGSON2F_JUMP, 1452 OPTION_FIX_LOONGSON2F_NOP, 1453 OPTION_NO_FIX_LOONGSON2F_NOP, 1454 OPTION_FIX_VR4120, 1455 OPTION_NO_FIX_VR4120, 1456 OPTION_FIX_VR4130, 1457 OPTION_NO_FIX_VR4130, 1458 OPTION_FIX_CN63XXP1, 1459 OPTION_NO_FIX_CN63XXP1, 1460 OPTION_TRAP, 1461 OPTION_BREAK, 1462 OPTION_EB, 1463 OPTION_EL, 1464 OPTION_FP32, 1465 OPTION_GP32, 1466 OPTION_CONSTRUCT_FLOATS, 1467 OPTION_NO_CONSTRUCT_FLOATS, 1468 OPTION_FP64, 1469 OPTION_FPXX, 1470 OPTION_GP64, 1471 OPTION_RELAX_BRANCH, 1472 OPTION_NO_RELAX_BRANCH, 1473 OPTION_IGNORE_BRANCH_ISA, 1474 OPTION_NO_IGNORE_BRANCH_ISA, 1475 OPTION_INSN32, 1476 OPTION_NO_INSN32, 1477 OPTION_MSHARED, 1478 OPTION_MNO_SHARED, 1479 OPTION_MSYM32, 1480 OPTION_MNO_SYM32, 1481 OPTION_SOFT_FLOAT, 1482 OPTION_HARD_FLOAT, 1483 OPTION_SINGLE_FLOAT, 1484 OPTION_DOUBLE_FLOAT, 1485 OPTION_32, 1486 OPTION_CALL_SHARED, 1487 OPTION_CALL_NONPIC, 1488 OPTION_NON_SHARED, 1489 OPTION_XGOT, 1490 OPTION_MABI, 1491 OPTION_N32, 1492 OPTION_64, 1493 OPTION_MDEBUG, 1494 OPTION_NO_MDEBUG, 1495 OPTION_PDR, 1496 OPTION_NO_PDR, 1497 OPTION_MVXWORKS_PIC, 1498 OPTION_NAN, 1499 OPTION_ODD_SPREG, 1500 OPTION_NO_ODD_SPREG, 1501 OPTION_END_OF_ENUM 1502 }; 1503 1504struct option md_longopts[] = 1505{ 1506 /* Options which specify architecture. */ 1507 {"march", required_argument, NULL, OPTION_MARCH}, 1508 {"mtune", required_argument, NULL, OPTION_MTUNE}, 1509 {"mips0", no_argument, NULL, OPTION_MIPS1}, 1510 {"mips1", no_argument, NULL, OPTION_MIPS1}, 1511 {"mips2", no_argument, NULL, OPTION_MIPS2}, 1512 {"mips3", no_argument, NULL, OPTION_MIPS3}, 1513 {"mips4", no_argument, NULL, OPTION_MIPS4}, 1514 {"mips5", no_argument, NULL, OPTION_MIPS5}, 1515 {"mips32", no_argument, NULL, OPTION_MIPS32}, 1516 {"mips64", no_argument, NULL, OPTION_MIPS64}, 1517 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, 1518 {"mips32r3", no_argument, NULL, OPTION_MIPS32R3}, 1519 {"mips32r5", no_argument, NULL, OPTION_MIPS32R5}, 1520 {"mips32r6", no_argument, NULL, OPTION_MIPS32R6}, 1521 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, 1522 {"mips64r3", no_argument, NULL, OPTION_MIPS64R3}, 1523 {"mips64r5", no_argument, NULL, OPTION_MIPS64R5}, 1524 {"mips64r6", no_argument, NULL, OPTION_MIPS64R6}, 1525 1526 /* Options which specify Application Specific Extensions (ASEs). */ 1527 {"mips16", no_argument, NULL, OPTION_MIPS16}, 1528 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, 1529 {"mips3d", no_argument, NULL, OPTION_MIPS3D}, 1530 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, 1531 {"mdmx", no_argument, NULL, OPTION_MDMX}, 1532 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, 1533 {"mdsp", no_argument, NULL, OPTION_DSP}, 1534 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, 1535 {"mmt", no_argument, NULL, OPTION_MT}, 1536 {"mno-mt", no_argument, NULL, OPTION_NO_MT}, 1537 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, 1538 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, 1539 {"mdspr2", no_argument, NULL, OPTION_DSPR2}, 1540 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, 1541 {"mdspr3", no_argument, NULL, OPTION_DSPR3}, 1542 {"mno-dspr3", no_argument, NULL, OPTION_NO_DSPR3}, 1543 {"meva", no_argument, NULL, OPTION_EVA}, 1544 {"mno-eva", no_argument, NULL, OPTION_NO_EVA}, 1545 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS}, 1546 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS}, 1547 {"mmcu", no_argument, NULL, OPTION_MCU}, 1548 {"mno-mcu", no_argument, NULL, OPTION_NO_MCU}, 1549 {"mvirt", no_argument, NULL, OPTION_VIRT}, 1550 {"mno-virt", no_argument, NULL, OPTION_NO_VIRT}, 1551 {"mmsa", no_argument, NULL, OPTION_MSA}, 1552 {"mno-msa", no_argument, NULL, OPTION_NO_MSA}, 1553 {"mxpa", no_argument, NULL, OPTION_XPA}, 1554 {"mno-xpa", no_argument, NULL, OPTION_NO_XPA}, 1555 1556 /* Old-style architecture options. Don't add more of these. */ 1557 {"m4650", no_argument, NULL, OPTION_M4650}, 1558 {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, 1559 {"m4010", no_argument, NULL, OPTION_M4010}, 1560 {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, 1561 {"m4100", no_argument, NULL, OPTION_M4100}, 1562 {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, 1563 {"m3900", no_argument, NULL, OPTION_M3900}, 1564 {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, 1565 1566 /* Options which enable bug fixes. */ 1567 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, 1568 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, 1569 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, 1570 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP}, 1571 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP}, 1572 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP}, 1573 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP}, 1574 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, 1575 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, 1576 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, 1577 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, 1578 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K}, 1579 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K}, 1580 {"mfix-rm7000", no_argument, NULL, OPTION_FIX_RM7000}, 1581 {"mno-fix-rm7000", no_argument, NULL, OPTION_NO_FIX_RM7000}, 1582 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1}, 1583 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1}, 1584 1585 /* Miscellaneous options. */ 1586 {"trap", no_argument, NULL, OPTION_TRAP}, 1587 {"no-break", no_argument, NULL, OPTION_TRAP}, 1588 {"break", no_argument, NULL, OPTION_BREAK}, 1589 {"no-trap", no_argument, NULL, OPTION_BREAK}, 1590 {"EB", no_argument, NULL, OPTION_EB}, 1591 {"EL", no_argument, NULL, OPTION_EL}, 1592 {"mfp32", no_argument, NULL, OPTION_FP32}, 1593 {"mgp32", no_argument, NULL, OPTION_GP32}, 1594 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, 1595 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, 1596 {"mfp64", no_argument, NULL, OPTION_FP64}, 1597 {"mfpxx", no_argument, NULL, OPTION_FPXX}, 1598 {"mgp64", no_argument, NULL, OPTION_GP64}, 1599 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, 1600 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, 1601 {"mignore-branch-isa", no_argument, NULL, OPTION_IGNORE_BRANCH_ISA}, 1602 {"mno-ignore-branch-isa", no_argument, NULL, OPTION_NO_IGNORE_BRANCH_ISA}, 1603 {"minsn32", no_argument, NULL, OPTION_INSN32}, 1604 {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32}, 1605 {"mshared", no_argument, NULL, OPTION_MSHARED}, 1606 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, 1607 {"msym32", no_argument, NULL, OPTION_MSYM32}, 1608 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, 1609 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT}, 1610 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT}, 1611 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT}, 1612 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT}, 1613 {"modd-spreg", no_argument, NULL, OPTION_ODD_SPREG}, 1614 {"mno-odd-spreg", no_argument, NULL, OPTION_NO_ODD_SPREG}, 1615 1616 /* Strictly speaking this next option is ELF specific, 1617 but we allow it for other ports as well in order to 1618 make testing easier. */ 1619 {"32", no_argument, NULL, OPTION_32}, 1620 1621 /* ELF-specific options. */ 1622 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, 1623 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, 1624 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC}, 1625 {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, 1626 {"xgot", no_argument, NULL, OPTION_XGOT}, 1627 {"mabi", required_argument, NULL, OPTION_MABI}, 1628 {"n32", no_argument, NULL, OPTION_N32}, 1629 {"64", no_argument, NULL, OPTION_64}, 1630 {"mdebug", no_argument, NULL, OPTION_MDEBUG}, 1631 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, 1632 {"mpdr", no_argument, NULL, OPTION_PDR}, 1633 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, 1634 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, 1635 {"mnan", required_argument, NULL, OPTION_NAN}, 1636 1637 {NULL, no_argument, NULL, 0} 1638}; 1639size_t md_longopts_size = sizeof (md_longopts); 1640 1641/* Information about either an Application Specific Extension or an 1642 optional architecture feature that, for simplicity, we treat in the 1643 same way as an ASE. */ 1644struct mips_ase 1645{ 1646 /* The name of the ASE, used in both the command-line and .set options. */ 1647 const char *name; 1648 1649 /* The associated ASE_* flags. If the ASE is available on both 32-bit 1650 and 64-bit architectures, the flags here refer to the subset that 1651 is available on both. */ 1652 unsigned int flags; 1653 1654 /* The ASE_* flag used for instructions that are available on 64-bit 1655 architectures but that are not included in FLAGS. */ 1656 unsigned int flags64; 1657 1658 /* The command-line options that turn the ASE on and off. */ 1659 int option_on; 1660 int option_off; 1661 1662 /* The minimum required architecture revisions for MIPS32, MIPS64, 1663 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */ 1664 int mips32_rev; 1665 int mips64_rev; 1666 int micromips32_rev; 1667 int micromips64_rev; 1668 1669 /* The architecture where the ASE was removed or -1 if the extension has not 1670 been removed. */ 1671 int rem_rev; 1672}; 1673 1674/* A table of all supported ASEs. */ 1675static const struct mips_ase mips_ases[] = { 1676 { "dsp", ASE_DSP, ASE_DSP64, 1677 OPTION_DSP, OPTION_NO_DSP, 1678 2, 2, 2, 2, 1679 -1 }, 1680 1681 { "dspr2", ASE_DSP | ASE_DSPR2, 0, 1682 OPTION_DSPR2, OPTION_NO_DSPR2, 1683 2, 2, 2, 2, 1684 -1 }, 1685 1686 { "dspr3", ASE_DSP | ASE_DSPR2 | ASE_DSPR3, 0, 1687 OPTION_DSPR3, OPTION_NO_DSPR3, 1688 6, 6, -1, -1, 1689 -1 }, 1690 1691 { "eva", ASE_EVA, 0, 1692 OPTION_EVA, OPTION_NO_EVA, 1693 2, 2, 2, 2, 1694 -1 }, 1695 1696 { "mcu", ASE_MCU, 0, 1697 OPTION_MCU, OPTION_NO_MCU, 1698 2, 2, 2, 2, 1699 -1 }, 1700 1701 /* Deprecated in MIPS64r5, but we don't implement that yet. */ 1702 { "mdmx", ASE_MDMX, 0, 1703 OPTION_MDMX, OPTION_NO_MDMX, 1704 -1, 1, -1, -1, 1705 6 }, 1706 1707 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */ 1708 { "mips3d", ASE_MIPS3D, 0, 1709 OPTION_MIPS3D, OPTION_NO_MIPS3D, 1710 2, 1, -1, -1, 1711 6 }, 1712 1713 { "mt", ASE_MT, 0, 1714 OPTION_MT, OPTION_NO_MT, 1715 2, 2, -1, -1, 1716 -1 }, 1717 1718 { "smartmips", ASE_SMARTMIPS, 0, 1719 OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS, 1720 1, -1, -1, -1, 1721 6 }, 1722 1723 { "virt", ASE_VIRT, ASE_VIRT64, 1724 OPTION_VIRT, OPTION_NO_VIRT, 1725 2, 2, 2, 2, 1726 -1 }, 1727 1728 { "msa", ASE_MSA, ASE_MSA64, 1729 OPTION_MSA, OPTION_NO_MSA, 1730 2, 2, 2, 2, 1731 -1 }, 1732 1733 { "xpa", ASE_XPA, 0, 1734 OPTION_XPA, OPTION_NO_XPA, 1735 2, 2, -1, -1, 1736 -1 }, 1737}; 1738 1739/* The set of ASEs that require -mfp64. */ 1740#define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA) 1741 1742/* Groups of ASE_* flags that represent different revisions of an ASE. */ 1743static const unsigned int mips_ase_groups[] = { 1744 ASE_DSP | ASE_DSPR2 | ASE_DSPR3 1745}; 1746 1747/* Pseudo-op table. 1748 1749 The following pseudo-ops from the Kane and Heinrich MIPS book 1750 should be defined here, but are currently unsupported: .alias, 1751 .galive, .gjaldef, .gjrlive, .livereg, .noalias. 1752 1753 The following pseudo-ops from the Kane and Heinrich MIPS book are 1754 specific to the type of debugging information being generated, and 1755 should be defined by the object format: .aent, .begin, .bend, 1756 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, 1757 .vreg. 1758 1759 The following pseudo-ops from the Kane and Heinrich MIPS book are 1760 not MIPS CPU specific, but are also not specific to the object file 1761 format. This file is probably the best place to define them, but 1762 they are not currently supported: .asm0, .endr, .lab, .struct. */ 1763 1764static const pseudo_typeS mips_pseudo_table[] = 1765{ 1766 /* MIPS specific pseudo-ops. */ 1767 {"option", s_option, 0}, 1768 {"set", s_mipsset, 0}, 1769 {"rdata", s_change_sec, 'r'}, 1770 {"sdata", s_change_sec, 's'}, 1771 {"livereg", s_ignore, 0}, 1772 {"abicalls", s_abicalls, 0}, 1773 {"cpload", s_cpload, 0}, 1774 {"cpsetup", s_cpsetup, 0}, 1775 {"cplocal", s_cplocal, 0}, 1776 {"cprestore", s_cprestore, 0}, 1777 {"cpreturn", s_cpreturn, 0}, 1778 {"dtprelword", s_dtprelword, 0}, 1779 {"dtpreldword", s_dtpreldword, 0}, 1780 {"tprelword", s_tprelword, 0}, 1781 {"tpreldword", s_tpreldword, 0}, 1782 {"gpvalue", s_gpvalue, 0}, 1783 {"gpword", s_gpword, 0}, 1784 {"gpdword", s_gpdword, 0}, 1785 {"ehword", s_ehword, 0}, 1786 {"cpadd", s_cpadd, 0}, 1787 {"insn", s_insn, 0}, 1788 {"nan", s_nan, 0}, 1789 {"module", s_module, 0}, 1790 1791 /* Relatively generic pseudo-ops that happen to be used on MIPS 1792 chips. */ 1793 {"asciiz", stringer, 8 + 1}, 1794 {"bss", s_change_sec, 'b'}, 1795 {"err", s_err, 0}, 1796 {"half", s_cons, 1}, 1797 {"dword", s_cons, 3}, 1798 {"weakext", s_mips_weakext, 0}, 1799 {"origin", s_org, 0}, 1800 {"repeat", s_rept, 0}, 1801 1802 /* For MIPS this is non-standard, but we define it for consistency. */ 1803 {"sbss", s_change_sec, 'B'}, 1804 1805 /* These pseudo-ops are defined in read.c, but must be overridden 1806 here for one reason or another. */ 1807 {"align", s_align, 0}, 1808 {"byte", s_cons, 0}, 1809 {"data", s_change_sec, 'd'}, 1810 {"double", s_float_cons, 'd'}, 1811 {"float", s_float_cons, 'f'}, 1812 {"globl", s_mips_globl, 0}, 1813 {"global", s_mips_globl, 0}, 1814 {"hword", s_cons, 1}, 1815 {"int", s_cons, 2}, 1816 {"long", s_cons, 2}, 1817 {"octa", s_cons, 4}, 1818 {"quad", s_cons, 3}, 1819 {"section", s_change_section, 0}, 1820 {"short", s_cons, 1}, 1821 {"single", s_float_cons, 'f'}, 1822 {"stabd", s_mips_stab, 'd'}, 1823 {"stabn", s_mips_stab, 'n'}, 1824 {"stabs", s_mips_stab, 's'}, 1825 {"text", s_change_sec, 't'}, 1826 {"word", s_cons, 2}, 1827 1828 { "extern", ecoff_directive_extern, 0}, 1829 1830 { NULL, NULL, 0 }, 1831}; 1832 1833static const pseudo_typeS mips_nonecoff_pseudo_table[] = 1834{ 1835 /* These pseudo-ops should be defined by the object file format. 1836 However, a.out doesn't support them, so we have versions here. */ 1837 {"aent", s_mips_ent, 1}, 1838 {"bgnb", s_ignore, 0}, 1839 {"end", s_mips_end, 0}, 1840 {"endb", s_ignore, 0}, 1841 {"ent", s_mips_ent, 0}, 1842 {"file", s_mips_file, 0}, 1843 {"fmask", s_mips_mask, 'F'}, 1844 {"frame", s_mips_frame, 0}, 1845 {"loc", s_mips_loc, 0}, 1846 {"mask", s_mips_mask, 'R'}, 1847 {"verstamp", s_ignore, 0}, 1848 { NULL, NULL, 0 }, 1849}; 1850 1851/* Export the ABI address size for use by TC_ADDRESS_BYTES for the 1852 purpose of the `.dc.a' internal pseudo-op. */ 1853 1854int 1855mips_address_bytes (void) 1856{ 1857 file_mips_check_options (); 1858 return HAVE_64BIT_ADDRESSES ? 8 : 4; 1859} 1860 1861extern void pop_insert (const pseudo_typeS *); 1862 1863void 1864mips_pop_insert (void) 1865{ 1866 pop_insert (mips_pseudo_table); 1867 if (! ECOFF_DEBUGGING) 1868 pop_insert (mips_nonecoff_pseudo_table); 1869} 1870 1871/* Symbols labelling the current insn. */ 1872 1873struct insn_label_list 1874{ 1875 struct insn_label_list *next; 1876 symbolS *label; 1877}; 1878 1879static struct insn_label_list *free_insn_labels; 1880#define label_list tc_segment_info_data.labels 1881 1882static void mips_clear_insn_labels (void); 1883static void mips_mark_labels (void); 1884static void mips_compressed_mark_labels (void); 1885 1886static inline void 1887mips_clear_insn_labels (void) 1888{ 1889 struct insn_label_list **pl; 1890 segment_info_type *si; 1891 1892 if (now_seg) 1893 { 1894 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) 1895 ; 1896 1897 si = seg_info (now_seg); 1898 *pl = si->label_list; 1899 si->label_list = NULL; 1900 } 1901} 1902 1903/* Mark instruction labels in MIPS16/microMIPS mode. */ 1904 1905static inline void 1906mips_mark_labels (void) 1907{ 1908 if (HAVE_CODE_COMPRESSION) 1909 mips_compressed_mark_labels (); 1910} 1911 1912static char *expr_end; 1913 1914/* An expression in a macro instruction. This is set by mips_ip and 1915 mips16_ip and when populated is always an O_constant. */ 1916 1917static expressionS imm_expr; 1918 1919/* The relocatable field in an instruction and the relocs associated 1920 with it. These variables are used for instructions like LUI and 1921 JAL as well as true offsets. They are also used for address 1922 operands in macros. */ 1923 1924static expressionS offset_expr; 1925static bfd_reloc_code_real_type offset_reloc[3] 1926 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; 1927 1928/* This is set to the resulting size of the instruction to be produced 1929 by mips16_ip if an explicit extension is used or by mips_ip if an 1930 explicit size is supplied. */ 1931 1932static unsigned int forced_insn_length; 1933 1934/* True if we are assembling an instruction. All dot symbols defined during 1935 this time should be treated as code labels. */ 1936 1937static bfd_boolean mips_assembling_insn; 1938 1939/* The pdr segment for per procedure frame/regmask info. Not used for 1940 ECOFF debugging. */ 1941 1942static segT pdr_seg; 1943 1944/* The default target format to use. */ 1945 1946#if defined (TE_FreeBSD) 1947#define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd" 1948#elif defined (TE_TMIPS) 1949#define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips" 1950#else 1951#define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips" 1952#endif 1953 1954const char * 1955mips_target_format (void) 1956{ 1957 switch (OUTPUT_FLAVOR) 1958 { 1959 case bfd_target_elf_flavour: 1960#ifdef TE_VXWORKS 1961 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) 1962 return (target_big_endian 1963 ? "elf32-bigmips-vxworks" 1964 : "elf32-littlemips-vxworks"); 1965#endif 1966 return (target_big_endian 1967 ? (HAVE_64BIT_OBJECTS 1968 ? ELF_TARGET ("elf64-", "big") 1969 : (HAVE_NEWABI 1970 ? ELF_TARGET ("elf32-n", "big") 1971 : ELF_TARGET ("elf32-", "big"))) 1972 : (HAVE_64BIT_OBJECTS 1973 ? ELF_TARGET ("elf64-", "little") 1974 : (HAVE_NEWABI 1975 ? ELF_TARGET ("elf32-n", "little") 1976 : ELF_TARGET ("elf32-", "little")))); 1977 default: 1978 abort (); 1979 return NULL; 1980 } 1981} 1982 1983/* Return the ISA revision that is currently in use, or 0 if we are 1984 generating code for MIPS V or below. */ 1985 1986static int 1987mips_isa_rev (void) 1988{ 1989 if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2) 1990 return 2; 1991 1992 if (mips_opts.isa == ISA_MIPS32R3 || mips_opts.isa == ISA_MIPS64R3) 1993 return 3; 1994 1995 if (mips_opts.isa == ISA_MIPS32R5 || mips_opts.isa == ISA_MIPS64R5) 1996 return 5; 1997 1998 if (mips_opts.isa == ISA_MIPS32R6 || mips_opts.isa == ISA_MIPS64R6) 1999 return 6; 2000 2001 /* microMIPS implies revision 2 or above. */ 2002 if (mips_opts.micromips) 2003 return 2; 2004 2005 if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64) 2006 return 1; 2007 2008 return 0; 2009} 2010 2011/* Return the mask of all ASEs that are revisions of those in FLAGS. */ 2012 2013static unsigned int 2014mips_ase_mask (unsigned int flags) 2015{ 2016 unsigned int i; 2017 2018 for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++) 2019 if (flags & mips_ase_groups[i]) 2020 flags |= mips_ase_groups[i]; 2021 return flags; 2022} 2023 2024/* Check whether the current ISA supports ASE. Issue a warning if 2025 appropriate. */ 2026 2027static void 2028mips_check_isa_supports_ase (const struct mips_ase *ase) 2029{ 2030 const char *base; 2031 int min_rev, size; 2032 static unsigned int warned_isa; 2033 static unsigned int warned_fp32; 2034 2035 if (ISA_HAS_64BIT_REGS (mips_opts.isa)) 2036 min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev; 2037 else 2038 min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev; 2039 if ((min_rev < 0 || mips_isa_rev () < min_rev) 2040 && (warned_isa & ase->flags) != ase->flags) 2041 { 2042 warned_isa |= ase->flags; 2043 base = mips_opts.micromips ? "microMIPS" : "MIPS"; 2044 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32; 2045 if (min_rev < 0) 2046 as_warn (_("the %d-bit %s architecture does not support the" 2047 " `%s' extension"), size, base, ase->name); 2048 else 2049 as_warn (_("the `%s' extension requires %s%d revision %d or greater"), 2050 ase->name, base, size, min_rev); 2051 } 2052 else if ((ase->rem_rev > 0 && mips_isa_rev () >= ase->rem_rev) 2053 && (warned_isa & ase->flags) != ase->flags) 2054 { 2055 warned_isa |= ase->flags; 2056 base = mips_opts.micromips ? "microMIPS" : "MIPS"; 2057 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32; 2058 as_warn (_("the `%s' extension was removed in %s%d revision %d"), 2059 ase->name, base, size, ase->rem_rev); 2060 } 2061 2062 if ((ase->flags & FP64_ASES) 2063 && mips_opts.fp != 64 2064 && (warned_fp32 & ase->flags) != ase->flags) 2065 { 2066 warned_fp32 |= ase->flags; 2067 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase->name); 2068 } 2069} 2070 2071/* Check all enabled ASEs to see whether they are supported by the 2072 chosen architecture. */ 2073 2074static void 2075mips_check_isa_supports_ases (void) 2076{ 2077 unsigned int i, mask; 2078 2079 for (i = 0; i < ARRAY_SIZE (mips_ases); i++) 2080 { 2081 mask = mips_ase_mask (mips_ases[i].flags); 2082 if ((mips_opts.ase & mask) == mips_ases[i].flags) 2083 mips_check_isa_supports_ase (&mips_ases[i]); 2084 } 2085} 2086 2087/* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags 2088 that were affected. */ 2089 2090static unsigned int 2091mips_set_ase (const struct mips_ase *ase, struct mips_set_options *opts, 2092 bfd_boolean enabled_p) 2093{ 2094 unsigned int mask; 2095 2096 mask = mips_ase_mask (ase->flags); 2097 opts->ase &= ~mask; 2098 if (enabled_p) 2099 opts->ase |= ase->flags; 2100 return mask; 2101} 2102 2103/* Return the ASE called NAME, or null if none. */ 2104 2105static const struct mips_ase * 2106mips_lookup_ase (const char *name) 2107{ 2108 unsigned int i; 2109 2110 for (i = 0; i < ARRAY_SIZE (mips_ases); i++) 2111 if (strcmp (name, mips_ases[i].name) == 0) 2112 return &mips_ases[i]; 2113 return NULL; 2114} 2115 2116/* Return the length of a microMIPS instruction in bytes. If bits of 2117 the mask beyond the low 16 are 0, then it is a 16-bit instruction, 2118 otherwise it is a 32-bit instruction. */ 2119 2120static inline unsigned int 2121micromips_insn_length (const struct mips_opcode *mo) 2122{ 2123 return mips_opcode_32bit_p (mo) ? 4 : 2; 2124} 2125 2126/* Return the length of MIPS16 instruction OPCODE. */ 2127 2128static inline unsigned int 2129mips16_opcode_length (unsigned long opcode) 2130{ 2131 return (opcode >> 16) == 0 ? 2 : 4; 2132} 2133 2134/* Return the length of instruction INSN. */ 2135 2136static inline unsigned int 2137insn_length (const struct mips_cl_insn *insn) 2138{ 2139 if (mips_opts.micromips) 2140 return micromips_insn_length (insn->insn_mo); 2141 else if (mips_opts.mips16) 2142 return mips16_opcode_length (insn->insn_opcode); 2143 else 2144 return 4; 2145} 2146 2147/* Initialise INSN from opcode entry MO. Leave its position unspecified. */ 2148 2149static void 2150create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) 2151{ 2152 size_t i; 2153 2154 insn->insn_mo = mo; 2155 insn->insn_opcode = mo->match; 2156 insn->frag = NULL; 2157 insn->where = 0; 2158 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) 2159 insn->fixp[i] = NULL; 2160 insn->fixed_p = (mips_opts.noreorder > 0); 2161 insn->noreorder_p = (mips_opts.noreorder > 0); 2162 insn->mips16_absolute_jump_p = 0; 2163 insn->complete_p = 0; 2164 insn->cleared_p = 0; 2165} 2166 2167/* Get a list of all the operands in INSN. */ 2168 2169static const struct mips_operand_array * 2170insn_operands (const struct mips_cl_insn *insn) 2171{ 2172 if (insn->insn_mo >= &mips_opcodes[0] 2173 && insn->insn_mo < &mips_opcodes[NUMOPCODES]) 2174 return &mips_operands[insn->insn_mo - &mips_opcodes[0]]; 2175 2176 if (insn->insn_mo >= &mips16_opcodes[0] 2177 && insn->insn_mo < &mips16_opcodes[bfd_mips16_num_opcodes]) 2178 return &mips16_operands[insn->insn_mo - &mips16_opcodes[0]]; 2179 2180 if (insn->insn_mo >= µmips_opcodes[0] 2181 && insn->insn_mo < µmips_opcodes[bfd_micromips_num_opcodes]) 2182 return µmips_operands[insn->insn_mo - µmips_opcodes[0]]; 2183 2184 abort (); 2185} 2186 2187/* Get a description of operand OPNO of INSN. */ 2188 2189static const struct mips_operand * 2190insn_opno (const struct mips_cl_insn *insn, unsigned opno) 2191{ 2192 const struct mips_operand_array *operands; 2193 2194 operands = insn_operands (insn); 2195 if (opno >= MAX_OPERANDS || !operands->operand[opno]) 2196 abort (); 2197 return operands->operand[opno]; 2198} 2199 2200/* Install UVAL as the value of OPERAND in INSN. */ 2201 2202static inline void 2203insn_insert_operand (struct mips_cl_insn *insn, 2204 const struct mips_operand *operand, unsigned int uval) 2205{ 2206 insn->insn_opcode = mips_insert_operand (operand, insn->insn_opcode, uval); 2207} 2208 2209/* Extract the value of OPERAND from INSN. */ 2210 2211static inline unsigned 2212insn_extract_operand (const struct mips_cl_insn *insn, 2213 const struct mips_operand *operand) 2214{ 2215 return mips_extract_operand (operand, insn->insn_opcode); 2216} 2217 2218/* Record the current MIPS16/microMIPS mode in now_seg. */ 2219 2220static void 2221mips_record_compressed_mode (void) 2222{ 2223 segment_info_type *si; 2224 2225 si = seg_info (now_seg); 2226 if (si->tc_segment_info_data.mips16 != mips_opts.mips16) 2227 si->tc_segment_info_data.mips16 = mips_opts.mips16; 2228 if (si->tc_segment_info_data.micromips != mips_opts.micromips) 2229 si->tc_segment_info_data.micromips = mips_opts.micromips; 2230} 2231 2232/* Read a standard MIPS instruction from BUF. */ 2233 2234static unsigned long 2235read_insn (char *buf) 2236{ 2237 if (target_big_endian) 2238 return bfd_getb32 ((bfd_byte *) buf); 2239 else 2240 return bfd_getl32 ((bfd_byte *) buf); 2241} 2242 2243/* Write standard MIPS instruction INSN to BUF. Return a pointer to 2244 the next byte. */ 2245 2246static char * 2247write_insn (char *buf, unsigned int insn) 2248{ 2249 md_number_to_chars (buf, insn, 4); 2250 return buf + 4; 2251} 2252 2253/* Read a microMIPS or MIPS16 opcode from BUF, given that it 2254 has length LENGTH. */ 2255 2256static unsigned long 2257read_compressed_insn (char *buf, unsigned int length) 2258{ 2259 unsigned long insn; 2260 unsigned int i; 2261 2262 insn = 0; 2263 for (i = 0; i < length; i += 2) 2264 { 2265 insn <<= 16; 2266 if (target_big_endian) 2267 insn |= bfd_getb16 ((char *) buf); 2268 else 2269 insn |= bfd_getl16 ((char *) buf); 2270 buf += 2; 2271 } 2272 return insn; 2273} 2274 2275/* Write microMIPS or MIPS16 instruction INSN to BUF, given that the 2276 instruction is LENGTH bytes long. Return a pointer to the next byte. */ 2277 2278static char * 2279write_compressed_insn (char *buf, unsigned int insn, unsigned int length) 2280{ 2281 unsigned int i; 2282 2283 for (i = 0; i < length; i += 2) 2284 md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2); 2285 return buf + length; 2286} 2287 2288/* Install INSN at the location specified by its "frag" and "where" fields. */ 2289 2290static void 2291install_insn (const struct mips_cl_insn *insn) 2292{ 2293 char *f = insn->frag->fr_literal + insn->where; 2294 if (HAVE_CODE_COMPRESSION) 2295 write_compressed_insn (f, insn->insn_opcode, insn_length (insn)); 2296 else 2297 write_insn (f, insn->insn_opcode); 2298 mips_record_compressed_mode (); 2299} 2300 2301/* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly 2302 and install the opcode in the new location. */ 2303 2304static void 2305move_insn (struct mips_cl_insn *insn, fragS *frag, long where) 2306{ 2307 size_t i; 2308 2309 insn->frag = frag; 2310 insn->where = where; 2311 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) 2312 if (insn->fixp[i] != NULL) 2313 { 2314 insn->fixp[i]->fx_frag = frag; 2315 insn->fixp[i]->fx_where = where; 2316 } 2317 install_insn (insn); 2318} 2319 2320/* Add INSN to the end of the output. */ 2321 2322static void 2323add_fixed_insn (struct mips_cl_insn *insn) 2324{ 2325 char *f = frag_more (insn_length (insn)); 2326 move_insn (insn, frag_now, f - frag_now->fr_literal); 2327} 2328 2329/* Start a variant frag and move INSN to the start of the variant part, 2330 marking it as fixed. The other arguments are as for frag_var. */ 2331 2332static void 2333add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, 2334 relax_substateT subtype, symbolS *symbol, offsetT offset) 2335{ 2336 frag_grow (max_chars); 2337 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); 2338 insn->fixed_p = 1; 2339 frag_var (rs_machine_dependent, max_chars, var, 2340 subtype, symbol, offset, NULL); 2341} 2342 2343/* Insert N copies of INSN into the history buffer, starting at 2344 position FIRST. Neither FIRST nor N need to be clipped. */ 2345 2346static void 2347insert_into_history (unsigned int first, unsigned int n, 2348 const struct mips_cl_insn *insn) 2349{ 2350 if (mips_relax.sequence != 2) 2351 { 2352 unsigned int i; 2353 2354 for (i = ARRAY_SIZE (history); i-- > first;) 2355 if (i >= first + n) 2356 history[i] = history[i - n]; 2357 else 2358 history[i] = *insn; 2359 } 2360} 2361 2362/* Clear the error in insn_error. */ 2363 2364static void 2365clear_insn_error (void) 2366{ 2367 memset (&insn_error, 0, sizeof (insn_error)); 2368} 2369 2370/* Possibly record error message MSG for the current instruction. 2371 If the error is about a particular argument, ARGNUM is the 1-based 2372 number of that argument, otherwise it is 0. FORMAT is the format 2373 of MSG. Return true if MSG was used, false if the current message 2374 was kept. */ 2375 2376static bfd_boolean 2377set_insn_error_format (int argnum, enum mips_insn_error_format format, 2378 const char *msg) 2379{ 2380 if (argnum == 0) 2381 { 2382 /* Give priority to errors against specific arguments, and to 2383 the first whole-instruction message. */ 2384 if (insn_error.msg) 2385 return FALSE; 2386 } 2387 else 2388 { 2389 /* Keep insn_error if it is against a later argument. */ 2390 if (argnum < insn_error.min_argnum) 2391 return FALSE; 2392 2393 /* If both errors are against the same argument but are different, 2394 give up on reporting a specific error for this argument. 2395 See the comment about mips_insn_error for details. */ 2396 if (argnum == insn_error.min_argnum 2397 && insn_error.msg 2398 && strcmp (insn_error.msg, msg) != 0) 2399 { 2400 insn_error.msg = 0; 2401 insn_error.min_argnum += 1; 2402 return FALSE; 2403 } 2404 } 2405 insn_error.min_argnum = argnum; 2406 insn_error.format = format; 2407 insn_error.msg = msg; 2408 return TRUE; 2409} 2410 2411/* Record an instruction error with no % format fields. ARGNUM and MSG are 2412 as for set_insn_error_format. */ 2413 2414static void 2415set_insn_error (int argnum, const char *msg) 2416{ 2417 set_insn_error_format (argnum, ERR_FMT_PLAIN, msg); 2418} 2419 2420/* Record an instruction error with one %d field I. ARGNUM and MSG are 2421 as for set_insn_error_format. */ 2422 2423static void 2424set_insn_error_i (int argnum, const char *msg, int i) 2425{ 2426 if (set_insn_error_format (argnum, ERR_FMT_I, msg)) 2427 insn_error.u.i = i; 2428} 2429 2430/* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG 2431 are as for set_insn_error_format. */ 2432 2433static void 2434set_insn_error_ss (int argnum, const char *msg, const char *s1, const char *s2) 2435{ 2436 if (set_insn_error_format (argnum, ERR_FMT_SS, msg)) 2437 { 2438 insn_error.u.ss[0] = s1; 2439 insn_error.u.ss[1] = s2; 2440 } 2441} 2442 2443/* Report the error in insn_error, which is against assembly code STR. */ 2444 2445static void 2446report_insn_error (const char *str) 2447{ 2448 const char *msg = concat (insn_error.msg, " `%s'", NULL); 2449 2450 switch (insn_error.format) 2451 { 2452 case ERR_FMT_PLAIN: 2453 as_bad (msg, str); 2454 break; 2455 2456 case ERR_FMT_I: 2457 as_bad (msg, insn_error.u.i, str); 2458 break; 2459 2460 case ERR_FMT_SS: 2461 as_bad (msg, insn_error.u.ss[0], insn_error.u.ss[1], str); 2462 break; 2463 } 2464 2465 free ((char *) msg); 2466} 2467 2468/* Initialize vr4120_conflicts. There is a bit of duplication here: 2469 the idea is to make it obvious at a glance that each errata is 2470 included. */ 2471 2472static void 2473init_vr4120_conflicts (void) 2474{ 2475#define CONFLICT(FIRST, SECOND) \ 2476 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND 2477 2478 /* Errata 21 - [D]DIV[U] after [D]MACC */ 2479 CONFLICT (MACC, DIV); 2480 CONFLICT (DMACC, DIV); 2481 2482 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ 2483 CONFLICT (DMULT, DMULT); 2484 CONFLICT (DMULT, DMACC); 2485 CONFLICT (DMACC, DMULT); 2486 CONFLICT (DMACC, DMACC); 2487 2488 /* Errata 24 - MT{LO,HI} after [D]MACC */ 2489 CONFLICT (MACC, MTHILO); 2490 CONFLICT (DMACC, MTHILO); 2491 2492 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU 2493 instruction is executed immediately after a MACC or DMACC 2494 instruction, the result of [either instruction] is incorrect." */ 2495 CONFLICT (MACC, MULT); 2496 CONFLICT (MACC, DMULT); 2497 CONFLICT (DMACC, MULT); 2498 CONFLICT (DMACC, DMULT); 2499 2500 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is 2501 executed immediately after a DMULT, DMULTU, DIV, DIVU, 2502 DDIV or DDIVU instruction, the result of the MACC or 2503 DMACC instruction is incorrect.". */ 2504 CONFLICT (DMULT, MACC); 2505 CONFLICT (DMULT, DMACC); 2506 CONFLICT (DIV, MACC); 2507 CONFLICT (DIV, DMACC); 2508 2509#undef CONFLICT 2510} 2511 2512struct regname { 2513 const char *name; 2514 unsigned int num; 2515}; 2516 2517#define RNUM_MASK 0x00000ff 2518#define RTYPE_MASK 0x0ffff00 2519#define RTYPE_NUM 0x0000100 2520#define RTYPE_FPU 0x0000200 2521#define RTYPE_FCC 0x0000400 2522#define RTYPE_VEC 0x0000800 2523#define RTYPE_GP 0x0001000 2524#define RTYPE_CP0 0x0002000 2525#define RTYPE_PC 0x0004000 2526#define RTYPE_ACC 0x0008000 2527#define RTYPE_CCC 0x0010000 2528#define RTYPE_VI 0x0020000 2529#define RTYPE_VF 0x0040000 2530#define RTYPE_R5900_I 0x0080000 2531#define RTYPE_R5900_Q 0x0100000 2532#define RTYPE_R5900_R 0x0200000 2533#define RTYPE_R5900_ACC 0x0400000 2534#define RTYPE_MSA 0x0800000 2535#define RWARN 0x8000000 2536 2537#define GENERIC_REGISTER_NUMBERS \ 2538 {"$0", RTYPE_NUM | 0}, \ 2539 {"$1", RTYPE_NUM | 1}, \ 2540 {"$2", RTYPE_NUM | 2}, \ 2541 {"$3", RTYPE_NUM | 3}, \ 2542 {"$4", RTYPE_NUM | 4}, \ 2543 {"$5", RTYPE_NUM | 5}, \ 2544 {"$6", RTYPE_NUM | 6}, \ 2545 {"$7", RTYPE_NUM | 7}, \ 2546 {"$8", RTYPE_NUM | 8}, \ 2547 {"$9", RTYPE_NUM | 9}, \ 2548 {"$10", RTYPE_NUM | 10}, \ 2549 {"$11", RTYPE_NUM | 11}, \ 2550 {"$12", RTYPE_NUM | 12}, \ 2551 {"$13", RTYPE_NUM | 13}, \ 2552 {"$14", RTYPE_NUM | 14}, \ 2553 {"$15", RTYPE_NUM | 15}, \ 2554 {"$16", RTYPE_NUM | 16}, \ 2555 {"$17", RTYPE_NUM | 17}, \ 2556 {"$18", RTYPE_NUM | 18}, \ 2557 {"$19", RTYPE_NUM | 19}, \ 2558 {"$20", RTYPE_NUM | 20}, \ 2559 {"$21", RTYPE_NUM | 21}, \ 2560 {"$22", RTYPE_NUM | 22}, \ 2561 {"$23", RTYPE_NUM | 23}, \ 2562 {"$24", RTYPE_NUM | 24}, \ 2563 {"$25", RTYPE_NUM | 25}, \ 2564 {"$26", RTYPE_NUM | 26}, \ 2565 {"$27", RTYPE_NUM | 27}, \ 2566 {"$28", RTYPE_NUM | 28}, \ 2567 {"$29", RTYPE_NUM | 29}, \ 2568 {"$30", RTYPE_NUM | 30}, \ 2569 {"$31", RTYPE_NUM | 31} 2570 2571#define FPU_REGISTER_NAMES \ 2572 {"$f0", RTYPE_FPU | 0}, \ 2573 {"$f1", RTYPE_FPU | 1}, \ 2574 {"$f2", RTYPE_FPU | 2}, \ 2575 {"$f3", RTYPE_FPU | 3}, \ 2576 {"$f4", RTYPE_FPU | 4}, \ 2577 {"$f5", RTYPE_FPU | 5}, \ 2578 {"$f6", RTYPE_FPU | 6}, \ 2579 {"$f7", RTYPE_FPU | 7}, \ 2580 {"$f8", RTYPE_FPU | 8}, \ 2581 {"$f9", RTYPE_FPU | 9}, \ 2582 {"$f10", RTYPE_FPU | 10}, \ 2583 {"$f11", RTYPE_FPU | 11}, \ 2584 {"$f12", RTYPE_FPU | 12}, \ 2585 {"$f13", RTYPE_FPU | 13}, \ 2586 {"$f14", RTYPE_FPU | 14}, \ 2587 {"$f15", RTYPE_FPU | 15}, \ 2588 {"$f16", RTYPE_FPU | 16}, \ 2589 {"$f17", RTYPE_FPU | 17}, \ 2590 {"$f18", RTYPE_FPU | 18}, \ 2591 {"$f19", RTYPE_FPU | 19}, \ 2592 {"$f20", RTYPE_FPU | 20}, \ 2593 {"$f21", RTYPE_FPU | 21}, \ 2594 {"$f22", RTYPE_FPU | 22}, \ 2595 {"$f23", RTYPE_FPU | 23}, \ 2596 {"$f24", RTYPE_FPU | 24}, \ 2597 {"$f25", RTYPE_FPU | 25}, \ 2598 {"$f26", RTYPE_FPU | 26}, \ 2599 {"$f27", RTYPE_FPU | 27}, \ 2600 {"$f28", RTYPE_FPU | 28}, \ 2601 {"$f29", RTYPE_FPU | 29}, \ 2602 {"$f30", RTYPE_FPU | 30}, \ 2603 {"$f31", RTYPE_FPU | 31} 2604 2605#define FPU_CONDITION_CODE_NAMES \ 2606 {"$fcc0", RTYPE_FCC | 0}, \ 2607 {"$fcc1", RTYPE_FCC | 1}, \ 2608 {"$fcc2", RTYPE_FCC | 2}, \ 2609 {"$fcc3", RTYPE_FCC | 3}, \ 2610 {"$fcc4", RTYPE_FCC | 4}, \ 2611 {"$fcc5", RTYPE_FCC | 5}, \ 2612 {"$fcc6", RTYPE_FCC | 6}, \ 2613 {"$fcc7", RTYPE_FCC | 7} 2614 2615#define COPROC_CONDITION_CODE_NAMES \ 2616 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ 2617 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ 2618 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ 2619 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ 2620 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ 2621 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ 2622 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ 2623 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} 2624 2625#define N32N64_SYMBOLIC_REGISTER_NAMES \ 2626 {"$a4", RTYPE_GP | 8}, \ 2627 {"$a5", RTYPE_GP | 9}, \ 2628 {"$a6", RTYPE_GP | 10}, \ 2629 {"$a7", RTYPE_GP | 11}, \ 2630 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ 2631 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ 2632 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ 2633 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ 2634 {"$t0", RTYPE_GP | 12}, \ 2635 {"$t1", RTYPE_GP | 13}, \ 2636 {"$t2", RTYPE_GP | 14}, \ 2637 {"$t3", RTYPE_GP | 15} 2638 2639#define O32_SYMBOLIC_REGISTER_NAMES \ 2640 {"$t0", RTYPE_GP | 8}, \ 2641 {"$t1", RTYPE_GP | 9}, \ 2642 {"$t2", RTYPE_GP | 10}, \ 2643 {"$t3", RTYPE_GP | 11}, \ 2644 {"$t4", RTYPE_GP | 12}, \ 2645 {"$t5", RTYPE_GP | 13}, \ 2646 {"$t6", RTYPE_GP | 14}, \ 2647 {"$t7", RTYPE_GP | 15}, \ 2648 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ 2649 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ 2650 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ 2651 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ 2652 2653/* Remaining symbolic register names */ 2654#define SYMBOLIC_REGISTER_NAMES \ 2655 {"$zero", RTYPE_GP | 0}, \ 2656 {"$at", RTYPE_GP | 1}, \ 2657 {"$AT", RTYPE_GP | 1}, \ 2658 {"$v0", RTYPE_GP | 2}, \ 2659 {"$v1", RTYPE_GP | 3}, \ 2660 {"$a0", RTYPE_GP | 4}, \ 2661 {"$a1", RTYPE_GP | 5}, \ 2662 {"$a2", RTYPE_GP | 6}, \ 2663 {"$a3", RTYPE_GP | 7}, \ 2664 {"$s0", RTYPE_GP | 16}, \ 2665 {"$s1", RTYPE_GP | 17}, \ 2666 {"$s2", RTYPE_GP | 18}, \ 2667 {"$s3", RTYPE_GP | 19}, \ 2668 {"$s4", RTYPE_GP | 20}, \ 2669 {"$s5", RTYPE_GP | 21}, \ 2670 {"$s6", RTYPE_GP | 22}, \ 2671 {"$s7", RTYPE_GP | 23}, \ 2672 {"$t8", RTYPE_GP | 24}, \ 2673 {"$t9", RTYPE_GP | 25}, \ 2674 {"$k0", RTYPE_GP | 26}, \ 2675 {"$kt0", RTYPE_GP | 26}, \ 2676 {"$k1", RTYPE_GP | 27}, \ 2677 {"$kt1", RTYPE_GP | 27}, \ 2678 {"$gp", RTYPE_GP | 28}, \ 2679 {"$sp", RTYPE_GP | 29}, \ 2680 {"$s8", RTYPE_GP | 30}, \ 2681 {"$fp", RTYPE_GP | 30}, \ 2682 {"$ra", RTYPE_GP | 31} 2683 2684#define MIPS16_SPECIAL_REGISTER_NAMES \ 2685 {"$pc", RTYPE_PC | 0} 2686 2687#define MDMX_VECTOR_REGISTER_NAMES \ 2688 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \ 2689 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \ 2690 {"$v2", RTYPE_VEC | 2}, \ 2691 {"$v3", RTYPE_VEC | 3}, \ 2692 {"$v4", RTYPE_VEC | 4}, \ 2693 {"$v5", RTYPE_VEC | 5}, \ 2694 {"$v6", RTYPE_VEC | 6}, \ 2695 {"$v7", RTYPE_VEC | 7}, \ 2696 {"$v8", RTYPE_VEC | 8}, \ 2697 {"$v9", RTYPE_VEC | 9}, \ 2698 {"$v10", RTYPE_VEC | 10}, \ 2699 {"$v11", RTYPE_VEC | 11}, \ 2700 {"$v12", RTYPE_VEC | 12}, \ 2701 {"$v13", RTYPE_VEC | 13}, \ 2702 {"$v14", RTYPE_VEC | 14}, \ 2703 {"$v15", RTYPE_VEC | 15}, \ 2704 {"$v16", RTYPE_VEC | 16}, \ 2705 {"$v17", RTYPE_VEC | 17}, \ 2706 {"$v18", RTYPE_VEC | 18}, \ 2707 {"$v19", RTYPE_VEC | 19}, \ 2708 {"$v20", RTYPE_VEC | 20}, \ 2709 {"$v21", RTYPE_VEC | 21}, \ 2710 {"$v22", RTYPE_VEC | 22}, \ 2711 {"$v23", RTYPE_VEC | 23}, \ 2712 {"$v24", RTYPE_VEC | 24}, \ 2713 {"$v25", RTYPE_VEC | 25}, \ 2714 {"$v26", RTYPE_VEC | 26}, \ 2715 {"$v27", RTYPE_VEC | 27}, \ 2716 {"$v28", RTYPE_VEC | 28}, \ 2717 {"$v29", RTYPE_VEC | 29}, \ 2718 {"$v30", RTYPE_VEC | 30}, \ 2719 {"$v31", RTYPE_VEC | 31} 2720 2721#define R5900_I_NAMES \ 2722 {"$I", RTYPE_R5900_I | 0} 2723 2724#define R5900_Q_NAMES \ 2725 {"$Q", RTYPE_R5900_Q | 0} 2726 2727#define R5900_R_NAMES \ 2728 {"$R", RTYPE_R5900_R | 0} 2729 2730#define R5900_ACC_NAMES \ 2731 {"$ACC", RTYPE_R5900_ACC | 0 } 2732 2733#define MIPS_DSP_ACCUMULATOR_NAMES \ 2734 {"$ac0", RTYPE_ACC | 0}, \ 2735 {"$ac1", RTYPE_ACC | 1}, \ 2736 {"$ac2", RTYPE_ACC | 2}, \ 2737 {"$ac3", RTYPE_ACC | 3} 2738 2739static const struct regname reg_names[] = { 2740 GENERIC_REGISTER_NUMBERS, 2741 FPU_REGISTER_NAMES, 2742 FPU_CONDITION_CODE_NAMES, 2743 COPROC_CONDITION_CODE_NAMES, 2744 2745 /* The $txx registers depends on the abi, 2746 these will be added later into the symbol table from 2747 one of the tables below once mips_abi is set after 2748 parsing of arguments from the command line. */ 2749 SYMBOLIC_REGISTER_NAMES, 2750 2751 MIPS16_SPECIAL_REGISTER_NAMES, 2752 MDMX_VECTOR_REGISTER_NAMES, 2753 R5900_I_NAMES, 2754 R5900_Q_NAMES, 2755 R5900_R_NAMES, 2756 R5900_ACC_NAMES, 2757 MIPS_DSP_ACCUMULATOR_NAMES, 2758 {0, 0} 2759}; 2760 2761static const struct regname reg_names_o32[] = { 2762 O32_SYMBOLIC_REGISTER_NAMES, 2763 {0, 0} 2764}; 2765 2766static const struct regname reg_names_n32n64[] = { 2767 N32N64_SYMBOLIC_REGISTER_NAMES, 2768 {0, 0} 2769}; 2770 2771/* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be 2772 interpreted as vector registers 0 and 1. If SYMVAL is the value of one 2773 of these register symbols, return the associated vector register, 2774 otherwise return SYMVAL itself. */ 2775 2776static unsigned int 2777mips_prefer_vec_regno (unsigned int symval) 2778{ 2779 if ((symval & -2) == (RTYPE_GP | 2)) 2780 return RTYPE_VEC | (symval & 1); 2781 return symval; 2782} 2783 2784/* Return true if string [S, E) is a valid register name, storing its 2785 symbol value in *SYMVAL_PTR if so. */ 2786 2787static bfd_boolean 2788mips_parse_register_1 (char *s, char *e, unsigned int *symval_ptr) 2789{ 2790 char save_c; 2791 symbolS *symbol; 2792 2793 /* Terminate name. */ 2794 save_c = *e; 2795 *e = '\0'; 2796 2797 /* Look up the name. */ 2798 symbol = symbol_find (s); 2799 *e = save_c; 2800 2801 if (!symbol || S_GET_SEGMENT (symbol) != reg_section) 2802 return FALSE; 2803 2804 *symval_ptr = S_GET_VALUE (symbol); 2805 return TRUE; 2806} 2807 2808/* Return true if the string at *SPTR is a valid register name. Allow it 2809 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR 2810 is nonnull. 2811 2812 When returning true, move *SPTR past the register, store the 2813 register's symbol value in *SYMVAL_PTR and the channel mask in 2814 *CHANNELS_PTR (if nonnull). The symbol value includes the register 2815 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask 2816 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */ 2817 2818static bfd_boolean 2819mips_parse_register (char **sptr, unsigned int *symval_ptr, 2820 unsigned int *channels_ptr) 2821{ 2822 char *s, *e, *m; 2823 const char *q; 2824 unsigned int channels, symval, bit; 2825 2826 /* Find end of name. */ 2827 s = e = *sptr; 2828 if (is_name_beginner (*e)) 2829 ++e; 2830 while (is_part_of_name (*e)) 2831 ++e; 2832 2833 channels = 0; 2834 if (!mips_parse_register_1 (s, e, &symval)) 2835 { 2836 if (!channels_ptr) 2837 return FALSE; 2838 2839 /* Eat characters from the end of the string that are valid 2840 channel suffixes. The preceding register must be $ACC or 2841 end with a digit, so there is no ambiguity. */ 2842 bit = 1; 2843 m = e; 2844 for (q = "wzyx"; *q; q++, bit <<= 1) 2845 if (m > s && m[-1] == *q) 2846 { 2847 --m; 2848 channels |= bit; 2849 } 2850 2851 if (channels == 0 2852 || !mips_parse_register_1 (s, m, &symval) 2853 || (symval & (RTYPE_VI | RTYPE_VF | RTYPE_R5900_ACC)) == 0) 2854 return FALSE; 2855 } 2856 2857 *sptr = e; 2858 *symval_ptr = symval; 2859 if (channels_ptr) 2860 *channels_ptr = channels; 2861 return TRUE; 2862} 2863 2864/* Check if SPTR points at a valid register specifier according to TYPES. 2865 If so, then return 1, advance S to consume the specifier and store 2866 the register's number in REGNOP, otherwise return 0. */ 2867 2868static int 2869reg_lookup (char **s, unsigned int types, unsigned int *regnop) 2870{ 2871 unsigned int regno; 2872 2873 if (mips_parse_register (s, ®no, NULL)) 2874 { 2875 if (types & RTYPE_VEC) 2876 regno = mips_prefer_vec_regno (regno); 2877 if (regno & types) 2878 regno &= RNUM_MASK; 2879 else 2880 regno = ~0; 2881 } 2882 else 2883 { 2884 if (types & RWARN) 2885 as_warn (_("unrecognized register name `%s'"), *s); 2886 regno = ~0; 2887 } 2888 if (regnop) 2889 *regnop = regno; 2890 return regno <= RNUM_MASK; 2891} 2892 2893/* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated 2894 mask in *CHANNELS. Return a pointer to the first unconsumed character. */ 2895 2896static char * 2897mips_parse_vu0_channels (char *s, unsigned int *channels) 2898{ 2899 unsigned int i; 2900 2901 *channels = 0; 2902 for (i = 0; i < 4; i++) 2903 if (*s == "xyzw"[i]) 2904 { 2905 *channels |= 1 << (3 - i); 2906 ++s; 2907 } 2908 return s; 2909} 2910 2911/* Token types for parsed operand lists. */ 2912enum mips_operand_token_type { 2913 /* A plain register, e.g. $f2. */ 2914 OT_REG, 2915 2916 /* A 4-bit XYZW channel mask. */ 2917 OT_CHANNELS, 2918 2919 /* A constant vector index, e.g. [1]. */ 2920 OT_INTEGER_INDEX, 2921 2922 /* A register vector index, e.g. [$2]. */ 2923 OT_REG_INDEX, 2924 2925 /* A continuous range of registers, e.g. $s0-$s4. */ 2926 OT_REG_RANGE, 2927 2928 /* A (possibly relocated) expression. */ 2929 OT_INTEGER, 2930 2931 /* A floating-point value. */ 2932 OT_FLOAT, 2933 2934 /* A single character. This can be '(', ')' or ',', but '(' only appears 2935 before OT_REGs. */ 2936 OT_CHAR, 2937 2938 /* A doubled character, either "--" or "++". */ 2939 OT_DOUBLE_CHAR, 2940 2941 /* The end of the operand list. */ 2942 OT_END 2943}; 2944 2945/* A parsed operand token. */ 2946struct mips_operand_token 2947{ 2948 /* The type of token. */ 2949 enum mips_operand_token_type type; 2950 union 2951 { 2952 /* The register symbol value for an OT_REG or OT_REG_INDEX. */ 2953 unsigned int regno; 2954 2955 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */ 2956 unsigned int channels; 2957 2958 /* The integer value of an OT_INTEGER_INDEX. */ 2959 addressT index; 2960 2961 /* The two register symbol values involved in an OT_REG_RANGE. */ 2962 struct { 2963 unsigned int regno1; 2964 unsigned int regno2; 2965 } reg_range; 2966 2967 /* The value of an OT_INTEGER. The value is represented as an 2968 expression and the relocation operators that were applied to 2969 that expression. The reloc entries are BFD_RELOC_UNUSED if no 2970 relocation operators were used. */ 2971 struct { 2972 expressionS value; 2973 bfd_reloc_code_real_type relocs[3]; 2974 } integer; 2975 2976 /* The binary data for an OT_FLOAT constant, and the number of bytes 2977 in the constant. */ 2978 struct { 2979 unsigned char data[8]; 2980 int length; 2981 } flt; 2982 2983 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */ 2984 char ch; 2985 } u; 2986}; 2987 2988/* An obstack used to construct lists of mips_operand_tokens. */ 2989static struct obstack mips_operand_tokens; 2990 2991/* Give TOKEN type TYPE and add it to mips_operand_tokens. */ 2992 2993static void 2994mips_add_token (struct mips_operand_token *token, 2995 enum mips_operand_token_type type) 2996{ 2997 token->type = type; 2998 obstack_grow (&mips_operand_tokens, token, sizeof (*token)); 2999} 3000 3001/* Check whether S is '(' followed by a register name. Add OT_CHAR 3002 and OT_REG tokens for them if so, and return a pointer to the first 3003 unconsumed character. Return null otherwise. */ 3004 3005static char * 3006mips_parse_base_start (char *s) 3007{ 3008 struct mips_operand_token token; 3009 unsigned int regno, channels; 3010 bfd_boolean decrement_p; 3011 3012 if (*s != '(') 3013 return 0; 3014 3015 ++s; 3016 SKIP_SPACE_TABS (s); 3017 3018 /* Only match "--" as part of a base expression. In other contexts "--X" 3019 is a double negative. */ 3020 decrement_p = (s[0] == '-' && s[1] == '-'); 3021 if (decrement_p) 3022 { 3023 s += 2; 3024 SKIP_SPACE_TABS (s); 3025 } 3026 3027 /* Allow a channel specifier because that leads to better error messages 3028 than treating something like "$vf0x++" as an expression. */ 3029 if (!mips_parse_register (&s, ®no, &channels)) 3030 return 0; 3031 3032 token.u.ch = '('; 3033 mips_add_token (&token, OT_CHAR); 3034 3035 if (decrement_p) 3036 { 3037 token.u.ch = '-'; 3038 mips_add_token (&token, OT_DOUBLE_CHAR); 3039 } 3040 3041 token.u.regno = regno; 3042 mips_add_token (&token, OT_REG); 3043 3044 if (channels) 3045 { 3046 token.u.channels = channels; 3047 mips_add_token (&token, OT_CHANNELS); 3048 } 3049 3050 /* For consistency, only match "++" as part of base expressions too. */ 3051 SKIP_SPACE_TABS (s); 3052 if (s[0] == '+' && s[1] == '+') 3053 { 3054 s += 2; 3055 token.u.ch = '+'; 3056 mips_add_token (&token, OT_DOUBLE_CHAR); 3057 } 3058 3059 return s; 3060} 3061 3062/* Parse one or more tokens from S. Return a pointer to the first 3063 unconsumed character on success. Return null if an error was found 3064 and store the error text in insn_error. FLOAT_FORMAT is as for 3065 mips_parse_arguments. */ 3066 3067static char * 3068mips_parse_argument_token (char *s, char float_format) 3069{ 3070 char *end, *save_in; 3071 const char *err; 3072 unsigned int regno1, regno2, channels; 3073 struct mips_operand_token token; 3074 3075 /* First look for "($reg", since we want to treat that as an 3076 OT_CHAR and OT_REG rather than an expression. */ 3077 end = mips_parse_base_start (s); 3078 if (end) 3079 return end; 3080 3081 /* Handle other characters that end up as OT_CHARs. */ 3082 if (*s == ')' || *s == ',') 3083 { 3084 token.u.ch = *s; 3085 mips_add_token (&token, OT_CHAR); 3086 ++s; 3087 return s; 3088 } 3089 3090 /* Handle tokens that start with a register. */ 3091 if (mips_parse_register (&s, ®no1, &channels)) 3092 { 3093 if (channels) 3094 { 3095 /* A register and a VU0 channel suffix. */ 3096 token.u.regno = regno1; 3097 mips_add_token (&token, OT_REG); 3098 3099 token.u.channels = channels; 3100 mips_add_token (&token, OT_CHANNELS); 3101 return s; 3102 } 3103 3104 SKIP_SPACE_TABS (s); 3105 if (*s == '-') 3106 { 3107 /* A register range. */ 3108 ++s; 3109 SKIP_SPACE_TABS (s); 3110 if (!mips_parse_register (&s, ®no2, NULL)) 3111 { 3112 set_insn_error (0, _("invalid register range")); 3113 return 0; 3114 } 3115 3116 token.u.reg_range.regno1 = regno1; 3117 token.u.reg_range.regno2 = regno2; 3118 mips_add_token (&token, OT_REG_RANGE); 3119 return s; 3120 } 3121 3122 /* Add the register itself. */ 3123 token.u.regno = regno1; 3124 mips_add_token (&token, OT_REG); 3125 3126 /* Check for a vector index. */ 3127 if (*s == '[') 3128 { 3129 ++s; 3130 SKIP_SPACE_TABS (s); 3131 if (mips_parse_register (&s, &token.u.regno, NULL)) 3132 mips_add_token (&token, OT_REG_INDEX); 3133 else 3134 { 3135 expressionS element; 3136 3137 my_getExpression (&element, s); 3138 if (element.X_op != O_constant) 3139 { 3140 set_insn_error (0, _("vector element must be constant")); 3141 return 0; 3142 } 3143 s = expr_end; 3144 token.u.index = element.X_add_number; 3145 mips_add_token (&token, OT_INTEGER_INDEX); 3146 } 3147 SKIP_SPACE_TABS (s); 3148 if (*s != ']') 3149 { 3150 set_insn_error (0, _("missing `]'")); 3151 return 0; 3152 } 3153 ++s; 3154 } 3155 return s; 3156 } 3157 3158 if (float_format) 3159 { 3160 /* First try to treat expressions as floats. */ 3161 save_in = input_line_pointer; 3162 input_line_pointer = s; 3163 err = md_atof (float_format, (char *) token.u.flt.data, 3164 &token.u.flt.length); 3165 end = input_line_pointer; 3166 input_line_pointer = save_in; 3167 if (err && *err) 3168 { 3169 set_insn_error (0, err); 3170 return 0; 3171 } 3172 if (s != end) 3173 { 3174 mips_add_token (&token, OT_FLOAT); 3175 return end; 3176 } 3177 } 3178 3179 /* Treat everything else as an integer expression. */ 3180 token.u.integer.relocs[0] = BFD_RELOC_UNUSED; 3181 token.u.integer.relocs[1] = BFD_RELOC_UNUSED; 3182 token.u.integer.relocs[2] = BFD_RELOC_UNUSED; 3183 my_getSmallExpression (&token.u.integer.value, token.u.integer.relocs, s); 3184 s = expr_end; 3185 mips_add_token (&token, OT_INTEGER); 3186 return s; 3187} 3188 3189/* S points to the operand list for an instruction. FLOAT_FORMAT is 'f' 3190 if expressions should be treated as 32-bit floating-point constants, 3191 'd' if they should be treated as 64-bit floating-point constants, 3192 or 0 if they should be treated as integer expressions (the usual case). 3193 3194 Return a list of tokens on success, otherwise return 0. The caller 3195 must obstack_free the list after use. */ 3196 3197static struct mips_operand_token * 3198mips_parse_arguments (char *s, char float_format) 3199{ 3200 struct mips_operand_token token; 3201 3202 SKIP_SPACE_TABS (s); 3203 while (*s) 3204 { 3205 s = mips_parse_argument_token (s, float_format); 3206 if (!s) 3207 { 3208 obstack_free (&mips_operand_tokens, 3209 obstack_finish (&mips_operand_tokens)); 3210 return 0; 3211 } 3212 SKIP_SPACE_TABS (s); 3213 } 3214 mips_add_token (&token, OT_END); 3215 return (struct mips_operand_token *) obstack_finish (&mips_operand_tokens); 3216} 3217 3218/* Return TRUE if opcode MO is valid on the currently selected ISA, ASE 3219 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */ 3220 3221static bfd_boolean 3222is_opcode_valid (const struct mips_opcode *mo) 3223{ 3224 int isa = mips_opts.isa; 3225 int ase = mips_opts.ase; 3226 int fp_s, fp_d; 3227 unsigned int i; 3228 3229 if (ISA_HAS_64BIT_REGS (isa)) 3230 for (i = 0; i < ARRAY_SIZE (mips_ases); i++) 3231 if ((ase & mips_ases[i].flags) == mips_ases[i].flags) 3232 ase |= mips_ases[i].flags64; 3233 3234 if (!opcode_is_member (mo, isa, ase, mips_opts.arch)) 3235 return FALSE; 3236 3237 /* Check whether the instruction or macro requires single-precision or 3238 double-precision floating-point support. Note that this information is 3239 stored differently in the opcode table for insns and macros. */ 3240 if (mo->pinfo == INSN_MACRO) 3241 { 3242 fp_s = mo->pinfo2 & INSN2_M_FP_S; 3243 fp_d = mo->pinfo2 & INSN2_M_FP_D; 3244 } 3245 else 3246 { 3247 fp_s = mo->pinfo & FP_S; 3248 fp_d = mo->pinfo & FP_D; 3249 } 3250 3251 if (fp_d && (mips_opts.soft_float || mips_opts.single_float)) 3252 return FALSE; 3253 3254 if (fp_s && mips_opts.soft_float) 3255 return FALSE; 3256 3257 return TRUE; 3258} 3259 3260/* Return TRUE if the MIPS16 opcode MO is valid on the currently 3261 selected ISA and architecture. */ 3262 3263static bfd_boolean 3264is_opcode_valid_16 (const struct mips_opcode *mo) 3265{ 3266 return opcode_is_member (mo, mips_opts.isa, 0, mips_opts.arch); 3267} 3268 3269/* Return TRUE if the size of the microMIPS opcode MO matches one 3270 explicitly requested. Always TRUE in the standard MIPS mode. 3271 Use is_size_valid_16 for MIPS16 opcodes. */ 3272 3273static bfd_boolean 3274is_size_valid (const struct mips_opcode *mo) 3275{ 3276 if (!mips_opts.micromips) 3277 return TRUE; 3278 3279 if (mips_opts.insn32) 3280 { 3281 if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4) 3282 return FALSE; 3283 if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0) 3284 return FALSE; 3285 } 3286 if (!forced_insn_length) 3287 return TRUE; 3288 if (mo->pinfo == INSN_MACRO) 3289 return FALSE; 3290 return forced_insn_length == micromips_insn_length (mo); 3291} 3292 3293/* Return TRUE if the size of the MIPS16 opcode MO matches one 3294 explicitly requested. */ 3295 3296static bfd_boolean 3297is_size_valid_16 (const struct mips_opcode *mo) 3298{ 3299 if (!forced_insn_length) 3300 return TRUE; 3301 if (mo->pinfo == INSN_MACRO) 3302 return FALSE; 3303 if (forced_insn_length == 2 && mips_opcode_32bit_p (mo)) 3304 return FALSE; 3305 if (forced_insn_length == 4 && (mo->pinfo2 & INSN2_SHORT_ONLY)) 3306 return FALSE; 3307 return TRUE; 3308} 3309 3310/* Return TRUE if the microMIPS opcode MO is valid for the delay slot 3311 of the preceding instruction. Always TRUE in the standard MIPS mode. 3312 3313 We don't accept macros in 16-bit delay slots to avoid a case where 3314 a macro expansion fails because it relies on a preceding 32-bit real 3315 instruction to have matched and does not handle the operands correctly. 3316 The only macros that may expand to 16-bit instructions are JAL that 3317 cannot be placed in a delay slot anyway, and corner cases of BALIGN 3318 and BGT (that likewise cannot be placed in a delay slot) that decay to 3319 a NOP. In all these cases the macros precede any corresponding real 3320 instruction definitions in the opcode table, so they will match in the 3321 second pass where the size of the delay slot is ignored and therefore 3322 produce correct code. */ 3323 3324static bfd_boolean 3325is_delay_slot_valid (const struct mips_opcode *mo) 3326{ 3327 if (!mips_opts.micromips) 3328 return TRUE; 3329 3330 if (mo->pinfo == INSN_MACRO) 3331 return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0; 3332 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 3333 && micromips_insn_length (mo) != 4) 3334 return FALSE; 3335 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 3336 && micromips_insn_length (mo) != 2) 3337 return FALSE; 3338 3339 return TRUE; 3340} 3341 3342/* For consistency checking, verify that all bits of OPCODE are specified 3343 either by the match/mask part of the instruction definition, or by the 3344 operand list. Also build up a list of operands in OPERANDS. 3345 3346 INSN_BITS says which bits of the instruction are significant. 3347 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND 3348 provides the mips_operand description of each operand. DECODE_OPERAND 3349 is null for MIPS16 instructions. */ 3350 3351static int 3352validate_mips_insn (const struct mips_opcode *opcode, 3353 unsigned long insn_bits, 3354 const struct mips_operand *(*decode_operand) (const char *), 3355 struct mips_operand_array *operands) 3356{ 3357 const char *s; 3358 unsigned long used_bits, doubled, undefined, opno, mask; 3359 const struct mips_operand *operand; 3360 3361 mask = (opcode->pinfo == INSN_MACRO ? 0 : opcode->mask); 3362 if ((mask & opcode->match) != opcode->match) 3363 { 3364 as_bad (_("internal: bad mips opcode (mask error): %s %s"), 3365 opcode->name, opcode->args); 3366 return 0; 3367 } 3368 used_bits = 0; 3369 opno = 0; 3370 if (opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) 3371 used_bits = mips_insert_operand (&mips_vu0_channel_mask, used_bits, -1); 3372 for (s = opcode->args; *s; ++s) 3373 switch (*s) 3374 { 3375 case ',': 3376 case '(': 3377 case ')': 3378 break; 3379 3380 case '#': 3381 s++; 3382 break; 3383 3384 default: 3385 if (!decode_operand) 3386 operand = decode_mips16_operand (*s, mips_opcode_32bit_p (opcode)); 3387 else 3388 operand = decode_operand (s); 3389 if (!operand && opcode->pinfo != INSN_MACRO) 3390 { 3391 as_bad (_("internal: unknown operand type: %s %s"), 3392 opcode->name, opcode->args); 3393 return 0; 3394 } 3395 gas_assert (opno < MAX_OPERANDS); 3396 operands->operand[opno] = operand; 3397 if (operand && operand->type != OP_VU0_MATCH_SUFFIX) 3398 { 3399 used_bits = mips_insert_operand (operand, used_bits, -1); 3400 if (operand->type == OP_MDMX_IMM_REG) 3401 /* Bit 5 is the format selector (OB vs QH). The opcode table 3402 has separate entries for each format. */ 3403 used_bits &= ~(1 << (operand->lsb + 5)); 3404 if (operand->type == OP_ENTRY_EXIT_LIST) 3405 used_bits &= ~(mask & 0x700); 3406 } 3407 /* Skip prefix characters. */ 3408 if (decode_operand && (*s == '+' || *s == 'm' || *s == '-')) 3409 ++s; 3410 opno += 1; 3411 break; 3412 } 3413 doubled = used_bits & mask & insn_bits; 3414 if (doubled) 3415 { 3416 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):" 3417 " %s %s"), doubled, opcode->name, opcode->args); 3418 return 0; 3419 } 3420 used_bits |= mask; 3421 undefined = ~used_bits & insn_bits; 3422 if (opcode->pinfo != INSN_MACRO && undefined) 3423 { 3424 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"), 3425 undefined, opcode->name, opcode->args); 3426 return 0; 3427 } 3428 used_bits &= ~insn_bits; 3429 if (used_bits) 3430 { 3431 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"), 3432 used_bits, opcode->name, opcode->args); 3433 return 0; 3434 } 3435 return 1; 3436} 3437 3438/* The MIPS16 version of validate_mips_insn. */ 3439 3440static int 3441validate_mips16_insn (const struct mips_opcode *opcode, 3442 struct mips_operand_array *operands) 3443{ 3444 unsigned long insn_bits = mips_opcode_32bit_p (opcode) ? 0xffffffff : 0xffff; 3445 3446 return validate_mips_insn (opcode, insn_bits, 0, operands); 3447} 3448 3449/* The microMIPS version of validate_mips_insn. */ 3450 3451static int 3452validate_micromips_insn (const struct mips_opcode *opc, 3453 struct mips_operand_array *operands) 3454{ 3455 unsigned long insn_bits; 3456 unsigned long major; 3457 unsigned int length; 3458 3459 if (opc->pinfo == INSN_MACRO) 3460 return validate_mips_insn (opc, 0xffffffff, decode_micromips_operand, 3461 operands); 3462 3463 length = micromips_insn_length (opc); 3464 if (length != 2 && length != 4) 3465 { 3466 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): " 3467 "%s %s"), length, opc->name, opc->args); 3468 return 0; 3469 } 3470 major = opc->match >> (10 + 8 * (length - 2)); 3471 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2) 3472 || (length == 4 && (major & 7) != 0 && (major & 4) != 4)) 3473 { 3474 as_bad (_("internal error: bad microMIPS opcode " 3475 "(opcode/length mismatch): %s %s"), opc->name, opc->args); 3476 return 0; 3477 } 3478 3479 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */ 3480 insn_bits = 1 << 4 * length; 3481 insn_bits <<= 4 * length; 3482 insn_bits -= 1; 3483 return validate_mips_insn (opc, insn_bits, decode_micromips_operand, 3484 operands); 3485} 3486 3487/* This function is called once, at assembler startup time. It should set up 3488 all the tables, etc. that the MD part of the assembler will need. */ 3489 3490void 3491md_begin (void) 3492{ 3493 const char *retval = NULL; 3494 int i = 0; 3495 int broken = 0; 3496 3497 if (mips_pic != NO_PIC) 3498 { 3499 if (g_switch_seen && g_switch_value != 0) 3500 as_bad (_("-G may not be used in position-independent code")); 3501 g_switch_value = 0; 3502 } 3503 else if (mips_abicalls) 3504 { 3505 if (g_switch_seen && g_switch_value != 0) 3506 as_bad (_("-G may not be used with abicalls")); 3507 g_switch_value = 0; 3508 } 3509 3510 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch)) 3511 as_warn (_("could not set architecture and machine")); 3512 3513 op_hash = hash_new (); 3514 3515 mips_operands = XCNEWVEC (struct mips_operand_array, NUMOPCODES); 3516 for (i = 0; i < NUMOPCODES;) 3517 { 3518 const char *name = mips_opcodes[i].name; 3519 3520 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); 3521 if (retval != NULL) 3522 { 3523 fprintf (stderr, _("internal error: can't hash `%s': %s\n"), 3524 mips_opcodes[i].name, retval); 3525 /* Probably a memory allocation problem? Give up now. */ 3526 as_fatal (_("broken assembler, no assembly attempted")); 3527 } 3528 do 3529 { 3530 if (!validate_mips_insn (&mips_opcodes[i], 0xffffffff, 3531 decode_mips_operand, &mips_operands[i])) 3532 broken = 1; 3533 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) 3534 { 3535 create_insn (&nop_insn, mips_opcodes + i); 3536 if (mips_fix_loongson2f_nop) 3537 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN; 3538 nop_insn.fixed_p = 1; 3539 } 3540 ++i; 3541 } 3542 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); 3543 } 3544 3545 mips16_op_hash = hash_new (); 3546 mips16_operands = XCNEWVEC (struct mips_operand_array, 3547 bfd_mips16_num_opcodes); 3548 3549 i = 0; 3550 while (i < bfd_mips16_num_opcodes) 3551 { 3552 const char *name = mips16_opcodes[i].name; 3553 3554 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); 3555 if (retval != NULL) 3556 as_fatal (_("internal: can't hash `%s': %s"), 3557 mips16_opcodes[i].name, retval); 3558 do 3559 { 3560 if (!validate_mips16_insn (&mips16_opcodes[i], &mips16_operands[i])) 3561 broken = 1; 3562 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) 3563 { 3564 create_insn (&mips16_nop_insn, mips16_opcodes + i); 3565 mips16_nop_insn.fixed_p = 1; 3566 } 3567 ++i; 3568 } 3569 while (i < bfd_mips16_num_opcodes 3570 && strcmp (mips16_opcodes[i].name, name) == 0); 3571 } 3572 3573 micromips_op_hash = hash_new (); 3574 micromips_operands = XCNEWVEC (struct mips_operand_array, 3575 bfd_micromips_num_opcodes); 3576 3577 i = 0; 3578 while (i < bfd_micromips_num_opcodes) 3579 { 3580 const char *name = micromips_opcodes[i].name; 3581 3582 retval = hash_insert (micromips_op_hash, name, 3583 (void *) µmips_opcodes[i]); 3584 if (retval != NULL) 3585 as_fatal (_("internal: can't hash `%s': %s"), 3586 micromips_opcodes[i].name, retval); 3587 do 3588 { 3589 struct mips_cl_insn *micromips_nop_insn; 3590 3591 if (!validate_micromips_insn (µmips_opcodes[i], 3592 µmips_operands[i])) 3593 broken = 1; 3594 3595 if (micromips_opcodes[i].pinfo != INSN_MACRO) 3596 { 3597 if (micromips_insn_length (micromips_opcodes + i) == 2) 3598 micromips_nop_insn = µmips_nop16_insn; 3599 else if (micromips_insn_length (micromips_opcodes + i) == 4) 3600 micromips_nop_insn = µmips_nop32_insn; 3601 else 3602 continue; 3603 3604 if (micromips_nop_insn->insn_mo == NULL 3605 && strcmp (name, "nop") == 0) 3606 { 3607 create_insn (micromips_nop_insn, micromips_opcodes + i); 3608 micromips_nop_insn->fixed_p = 1; 3609 } 3610 } 3611 } 3612 while (++i < bfd_micromips_num_opcodes 3613 && strcmp (micromips_opcodes[i].name, name) == 0); 3614 } 3615 3616 if (broken) 3617 as_fatal (_("broken assembler, no assembly attempted")); 3618 3619 /* We add all the general register names to the symbol table. This 3620 helps us detect invalid uses of them. */ 3621 for (i = 0; reg_names[i].name; i++) 3622 symbol_table_insert (symbol_new (reg_names[i].name, reg_section, 3623 reg_names[i].num, /* & RNUM_MASK, */ 3624 &zero_address_frag)); 3625 if (HAVE_NEWABI) 3626 for (i = 0; reg_names_n32n64[i].name; i++) 3627 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, 3628 reg_names_n32n64[i].num, /* & RNUM_MASK, */ 3629 &zero_address_frag)); 3630 else 3631 for (i = 0; reg_names_o32[i].name; i++) 3632 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, 3633 reg_names_o32[i].num, /* & RNUM_MASK, */ 3634 &zero_address_frag)); 3635 3636 for (i = 0; i < 32; i++) 3637 { 3638 char regname[6]; 3639 3640 /* R5900 VU0 floating-point register. */ 3641 sprintf (regname, "$vf%d", i); 3642 symbol_table_insert (symbol_new (regname, reg_section, 3643 RTYPE_VF | i, &zero_address_frag)); 3644 3645 /* R5900 VU0 integer register. */ 3646 sprintf (regname, "$vi%d", i); 3647 symbol_table_insert (symbol_new (regname, reg_section, 3648 RTYPE_VI | i, &zero_address_frag)); 3649 3650 /* MSA register. */ 3651 sprintf (regname, "$w%d", i); 3652 symbol_table_insert (symbol_new (regname, reg_section, 3653 RTYPE_MSA | i, &zero_address_frag)); 3654 } 3655 3656 obstack_init (&mips_operand_tokens); 3657 3658 mips_no_prev_insn (); 3659 3660 mips_gprmask = 0; 3661 mips_cprmask[0] = 0; 3662 mips_cprmask[1] = 0; 3663 mips_cprmask[2] = 0; 3664 mips_cprmask[3] = 0; 3665 3666 /* set the default alignment for the text section (2**2) */ 3667 record_alignment (text_section, 2); 3668 3669 bfd_set_gp_size (stdoutput, g_switch_value); 3670 3671 /* On a native system other than VxWorks, sections must be aligned 3672 to 16 byte boundaries. When configured for an embedded ELF 3673 target, we don't bother. */ 3674 if (strncmp (TARGET_OS, "elf", 3) != 0 3675 && strncmp (TARGET_OS, "vxworks", 7) != 0) 3676 { 3677 (void) bfd_set_section_alignment (stdoutput, text_section, 4); 3678 (void) bfd_set_section_alignment (stdoutput, data_section, 4); 3679 (void) bfd_set_section_alignment (stdoutput, bss_section, 4); 3680 } 3681 3682 /* Create a .reginfo section for register masks and a .mdebug 3683 section for debugging information. */ 3684 { 3685 segT seg; 3686 subsegT subseg; 3687 flagword flags; 3688 segT sec; 3689 3690 seg = now_seg; 3691 subseg = now_subseg; 3692 3693 /* The ABI says this section should be loaded so that the 3694 running program can access it. However, we don't load it 3695 if we are configured for an embedded target */ 3696 flags = SEC_READONLY | SEC_DATA; 3697 if (strncmp (TARGET_OS, "elf", 3) != 0) 3698 flags |= SEC_ALLOC | SEC_LOAD; 3699 3700 if (mips_abi != N64_ABI) 3701 { 3702 sec = subseg_new (".reginfo", (subsegT) 0); 3703 3704 bfd_set_section_flags (stdoutput, sec, flags); 3705 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); 3706 3707 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); 3708 } 3709 else 3710 { 3711 /* The 64-bit ABI uses a .MIPS.options section rather than 3712 .reginfo section. */ 3713 sec = subseg_new (".MIPS.options", (subsegT) 0); 3714 bfd_set_section_flags (stdoutput, sec, flags); 3715 bfd_set_section_alignment (stdoutput, sec, 3); 3716 3717 /* Set up the option header. */ 3718 { 3719 Elf_Internal_Options opthdr; 3720 char *f; 3721 3722 opthdr.kind = ODK_REGINFO; 3723 opthdr.size = (sizeof (Elf_External_Options) 3724 + sizeof (Elf64_External_RegInfo)); 3725 opthdr.section = 0; 3726 opthdr.info = 0; 3727 f = frag_more (sizeof (Elf_External_Options)); 3728 bfd_mips_elf_swap_options_out (stdoutput, &opthdr, 3729 (Elf_External_Options *) f); 3730 3731 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); 3732 } 3733 } 3734 3735 sec = subseg_new (".MIPS.abiflags", (subsegT) 0); 3736 bfd_set_section_flags (stdoutput, sec, 3737 SEC_READONLY | SEC_DATA | SEC_ALLOC | SEC_LOAD); 3738 bfd_set_section_alignment (stdoutput, sec, 3); 3739 mips_flags_frag = frag_more (sizeof (Elf_External_ABIFlags_v0)); 3740 3741 if (ECOFF_DEBUGGING) 3742 { 3743 sec = subseg_new (".mdebug", (subsegT) 0); 3744 (void) bfd_set_section_flags (stdoutput, sec, 3745 SEC_HAS_CONTENTS | SEC_READONLY); 3746 (void) bfd_set_section_alignment (stdoutput, sec, 2); 3747 } 3748 else if (mips_flag_pdr) 3749 { 3750 pdr_seg = subseg_new (".pdr", (subsegT) 0); 3751 (void) bfd_set_section_flags (stdoutput, pdr_seg, 3752 SEC_READONLY | SEC_RELOC 3753 | SEC_DEBUGGING); 3754 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); 3755 } 3756 3757 subseg_set (seg, subseg); 3758 } 3759 3760 if (mips_fix_vr4120) 3761 init_vr4120_conflicts (); 3762} 3763 3764static inline void 3765fpabi_incompatible_with (int fpabi, const char *what) 3766{ 3767 as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"), 3768 Tag_GNU_MIPS_ABI_FP, fpabi, what); 3769} 3770 3771static inline void 3772fpabi_requires (int fpabi, const char *what) 3773{ 3774 as_warn (_(".gnu_attribute %d,%d requires `%s'"), 3775 Tag_GNU_MIPS_ABI_FP, fpabi, what); 3776} 3777 3778/* Check -mabi and register sizes against the specified FP ABI. */ 3779static void 3780check_fpabi (int fpabi) 3781{ 3782 switch (fpabi) 3783 { 3784 case Val_GNU_MIPS_ABI_FP_DOUBLE: 3785 if (file_mips_opts.soft_float) 3786 fpabi_incompatible_with (fpabi, "softfloat"); 3787 else if (file_mips_opts.single_float) 3788 fpabi_incompatible_with (fpabi, "singlefloat"); 3789 if (file_mips_opts.gp == 64 && file_mips_opts.fp == 32) 3790 fpabi_incompatible_with (fpabi, "gp=64 fp=32"); 3791 else if (file_mips_opts.gp == 32 && file_mips_opts.fp == 64) 3792 fpabi_incompatible_with (fpabi, "gp=32 fp=64"); 3793 break; 3794 3795 case Val_GNU_MIPS_ABI_FP_XX: 3796 if (mips_abi != O32_ABI) 3797 fpabi_requires (fpabi, "-mabi=32"); 3798 else if (file_mips_opts.soft_float) 3799 fpabi_incompatible_with (fpabi, "softfloat"); 3800 else if (file_mips_opts.single_float) 3801 fpabi_incompatible_with (fpabi, "singlefloat"); 3802 else if (file_mips_opts.fp != 0) 3803 fpabi_requires (fpabi, "fp=xx"); 3804 break; 3805 3806 case Val_GNU_MIPS_ABI_FP_64A: 3807 case Val_GNU_MIPS_ABI_FP_64: 3808 if (mips_abi != O32_ABI) 3809 fpabi_requires (fpabi, "-mabi=32"); 3810 else if (file_mips_opts.soft_float) 3811 fpabi_incompatible_with (fpabi, "softfloat"); 3812 else if (file_mips_opts.single_float) 3813 fpabi_incompatible_with (fpabi, "singlefloat"); 3814 else if (file_mips_opts.fp != 64) 3815 fpabi_requires (fpabi, "fp=64"); 3816 else if (fpabi == Val_GNU_MIPS_ABI_FP_64 && !file_mips_opts.oddspreg) 3817 fpabi_incompatible_with (fpabi, "nooddspreg"); 3818 else if (fpabi == Val_GNU_MIPS_ABI_FP_64A && file_mips_opts.oddspreg) 3819 fpabi_requires (fpabi, "nooddspreg"); 3820 break; 3821 3822 case Val_GNU_MIPS_ABI_FP_SINGLE: 3823 if (file_mips_opts.soft_float) 3824 fpabi_incompatible_with (fpabi, "softfloat"); 3825 else if (!file_mips_opts.single_float) 3826 fpabi_requires (fpabi, "singlefloat"); 3827 break; 3828 3829 case Val_GNU_MIPS_ABI_FP_SOFT: 3830 if (!file_mips_opts.soft_float) 3831 fpabi_requires (fpabi, "softfloat"); 3832 break; 3833 3834 case Val_GNU_MIPS_ABI_FP_OLD_64: 3835 as_warn (_(".gnu_attribute %d,%d is no longer supported"), 3836 Tag_GNU_MIPS_ABI_FP, fpabi); 3837 break; 3838 3839 case Val_GNU_MIPS_ABI_FP_NAN2008: 3840 /* Silently ignore compatibility value. */ 3841 break; 3842 3843 default: 3844 as_warn (_(".gnu_attribute %d,%d is not a recognized" 3845 " floating-point ABI"), Tag_GNU_MIPS_ABI_FP, fpabi); 3846 break; 3847 } 3848} 3849 3850/* Perform consistency checks on the current options. */ 3851 3852static void 3853mips_check_options (struct mips_set_options *opts, bfd_boolean abi_checks) 3854{ 3855 /* Check the size of integer registers agrees with the ABI and ISA. */ 3856 if (opts->gp == 64 && !ISA_HAS_64BIT_REGS (opts->isa)) 3857 as_bad (_("`gp=64' used with a 32-bit processor")); 3858 else if (abi_checks 3859 && opts->gp == 32 && ABI_NEEDS_64BIT_REGS (mips_abi)) 3860 as_bad (_("`gp=32' used with a 64-bit ABI")); 3861 else if (abi_checks 3862 && opts->gp == 64 && ABI_NEEDS_32BIT_REGS (mips_abi)) 3863 as_bad (_("`gp=64' used with a 32-bit ABI")); 3864 3865 /* Check the size of the float registers agrees with the ABI and ISA. */ 3866 switch (opts->fp) 3867 { 3868 case 0: 3869 if (!CPU_HAS_LDC1_SDC1 (opts->arch)) 3870 as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions")); 3871 else if (opts->single_float == 1) 3872 as_bad (_("`fp=xx' cannot be used with `singlefloat'")); 3873 break; 3874 case 64: 3875 if (!ISA_HAS_64BIT_FPRS (opts->isa)) 3876 as_bad (_("`fp=64' used with a 32-bit fpu")); 3877 else if (abi_checks 3878 && ABI_NEEDS_32BIT_REGS (mips_abi) 3879 && !ISA_HAS_MXHC1 (opts->isa)) 3880 as_warn (_("`fp=64' used with a 32-bit ABI")); 3881 break; 3882 case 32: 3883 if (abi_checks 3884 && ABI_NEEDS_64BIT_REGS (mips_abi)) 3885 as_warn (_("`fp=32' used with a 64-bit ABI")); 3886 if (ISA_IS_R6 (opts->isa) && opts->single_float == 0) 3887 as_bad (_("`fp=32' used with a MIPS R6 cpu")); 3888 break; 3889 default: 3890 as_bad (_("Unknown size of floating point registers")); 3891 break; 3892 } 3893 3894 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !opts->oddspreg) 3895 as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI")); 3896 3897 if (opts->micromips == 1 && opts->mips16 == 1) 3898 as_bad (_("`%s' cannot be used with `%s'"), "mips16", "micromips"); 3899 else if (ISA_IS_R6 (opts->isa) 3900 && (opts->micromips == 1 3901 || opts->mips16 == 1)) 3902 as_fatal (_("`%s' cannot be used with `%s'"), 3903 opts->micromips ? "micromips" : "mips16", 3904 mips_cpu_info_from_isa (opts->isa)->name); 3905 3906 if (ISA_IS_R6 (opts->isa) && mips_relax_branch) 3907 as_fatal (_("branch relaxation is not supported in `%s'"), 3908 mips_cpu_info_from_isa (opts->isa)->name); 3909} 3910 3911/* Perform consistency checks on the module level options exactly once. 3912 This is a deferred check that happens: 3913 at the first .set directive 3914 or, at the first pseudo op that generates code (inc .dc.a) 3915 or, at the first instruction 3916 or, at the end. */ 3917 3918static void 3919file_mips_check_options (void) 3920{ 3921 const struct mips_cpu_info *arch_info = 0; 3922 3923 if (file_mips_opts_checked) 3924 return; 3925 3926 /* The following code determines the register size. 3927 Similar code was added to GCC 3.3 (see override_options() in 3928 config/mips/mips.c). The GAS and GCC code should be kept in sync 3929 as much as possible. */ 3930 3931 if (file_mips_opts.gp < 0) 3932 { 3933 /* Infer the integer register size from the ABI and processor. 3934 Restrict ourselves to 32-bit registers if that's all the 3935 processor has, or if the ABI cannot handle 64-bit registers. */ 3936 file_mips_opts.gp = (ABI_NEEDS_32BIT_REGS (mips_abi) 3937 || !ISA_HAS_64BIT_REGS (file_mips_opts.isa)) 3938 ? 32 : 64; 3939 } 3940 3941 if (file_mips_opts.fp < 0) 3942 { 3943 /* No user specified float register size. 3944 ??? GAS treats single-float processors as though they had 64-bit 3945 float registers (although it complains when double-precision 3946 instructions are used). As things stand, saying they have 32-bit 3947 registers would lead to spurious "register must be even" messages. 3948 So here we assume float registers are never smaller than the 3949 integer ones. */ 3950 if (file_mips_opts.gp == 64) 3951 /* 64-bit integer registers implies 64-bit float registers. */ 3952 file_mips_opts.fp = 64; 3953 else if ((file_mips_opts.ase & FP64_ASES) 3954 && ISA_HAS_64BIT_FPRS (file_mips_opts.isa)) 3955 /* Handle ASEs that require 64-bit float registers, if possible. */ 3956 file_mips_opts.fp = 64; 3957 else if (ISA_IS_R6 (mips_opts.isa)) 3958 /* R6 implies 64-bit float registers. */ 3959 file_mips_opts.fp = 64; 3960 else 3961 /* 32-bit float registers. */ 3962 file_mips_opts.fp = 32; 3963 } 3964 3965 arch_info = mips_cpu_info_from_arch (file_mips_opts.arch); 3966 3967 /* Disable operations on odd-numbered floating-point registers by default 3968 when using the FPXX ABI. */ 3969 if (file_mips_opts.oddspreg < 0) 3970 { 3971 if (file_mips_opts.fp == 0) 3972 file_mips_opts.oddspreg = 0; 3973 else 3974 file_mips_opts.oddspreg = 1; 3975 } 3976 3977 /* End of GCC-shared inference code. */ 3978 3979 /* This flag is set when we have a 64-bit capable CPU but use only 3980 32-bit wide registers. Note that EABI does not use it. */ 3981 if (ISA_HAS_64BIT_REGS (file_mips_opts.isa) 3982 && ((mips_abi == NO_ABI && file_mips_opts.gp == 32) 3983 || mips_abi == O32_ABI)) 3984 mips_32bitmode = 1; 3985 3986 if (file_mips_opts.isa == ISA_MIPS1 && mips_trap) 3987 as_bad (_("trap exception not supported at ISA 1")); 3988 3989 /* If the selected architecture includes support for ASEs, enable 3990 generation of code for them. */ 3991 if (file_mips_opts.mips16 == -1) 3992 file_mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_opts.arch)) ? 1 : 0; 3993 if (file_mips_opts.micromips == -1) 3994 file_mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_opts.arch)) 3995 ? 1 : 0; 3996 3997 if (mips_nan2008 == -1) 3998 mips_nan2008 = (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) ? 0 : 1; 3999 else if (!ISA_HAS_LEGACY_NAN (file_mips_opts.isa) && mips_nan2008 == 0) 4000 as_fatal (_("`%s' does not support legacy NaN"), 4001 mips_cpu_info_from_arch (file_mips_opts.arch)->name); 4002 4003 /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from 4004 being selected implicitly. */ 4005 if (file_mips_opts.fp != 64) 4006 file_ase_explicit |= ASE_MIPS3D | ASE_MDMX | ASE_MSA; 4007 4008 /* If the user didn't explicitly select or deselect a particular ASE, 4009 use the default setting for the CPU. */ 4010 file_mips_opts.ase |= (arch_info->ase & ~file_ase_explicit); 4011 4012 /* Set up the current options. These may change throughout assembly. */ 4013 mips_opts = file_mips_opts; 4014 4015 mips_check_isa_supports_ases (); 4016 mips_check_options (&file_mips_opts, TRUE); 4017 file_mips_opts_checked = TRUE; 4018 4019 if (!bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch)) 4020 as_warn (_("could not set architecture and machine")); 4021} 4022 4023void 4024md_assemble (char *str) 4025{ 4026 struct mips_cl_insn insn; 4027 bfd_reloc_code_real_type unused_reloc[3] 4028 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; 4029 4030 file_mips_check_options (); 4031 4032 imm_expr.X_op = O_absent; 4033 offset_expr.X_op = O_absent; 4034 offset_reloc[0] = BFD_RELOC_UNUSED; 4035 offset_reloc[1] = BFD_RELOC_UNUSED; 4036 offset_reloc[2] = BFD_RELOC_UNUSED; 4037 4038 mips_mark_labels (); 4039 mips_assembling_insn = TRUE; 4040 clear_insn_error (); 4041 4042 if (mips_opts.mips16) 4043 mips16_ip (str, &insn); 4044 else 4045 { 4046 mips_ip (str, &insn); 4047 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), 4048 str, insn.insn_opcode)); 4049 } 4050 4051 if (insn_error.msg) 4052 report_insn_error (str); 4053 else if (insn.insn_mo->pinfo == INSN_MACRO) 4054 { 4055 macro_start (); 4056 if (mips_opts.mips16) 4057 mips16_macro (&insn); 4058 else 4059 macro (&insn, str); 4060 macro_end (); 4061 } 4062 else 4063 { 4064 if (offset_expr.X_op != O_absent) 4065 append_insn (&insn, &offset_expr, offset_reloc, FALSE); 4066 else 4067 append_insn (&insn, NULL, unused_reloc, FALSE); 4068 } 4069 4070 mips_assembling_insn = FALSE; 4071} 4072 4073/* Convenience functions for abstracting away the differences between 4074 MIPS16 and non-MIPS16 relocations. */ 4075 4076static inline bfd_boolean 4077mips16_reloc_p (bfd_reloc_code_real_type reloc) 4078{ 4079 switch (reloc) 4080 { 4081 case BFD_RELOC_MIPS16_JMP: 4082 case BFD_RELOC_MIPS16_GPREL: 4083 case BFD_RELOC_MIPS16_GOT16: 4084 case BFD_RELOC_MIPS16_CALL16: 4085 case BFD_RELOC_MIPS16_HI16_S: 4086 case BFD_RELOC_MIPS16_HI16: 4087 case BFD_RELOC_MIPS16_LO16: 4088 case BFD_RELOC_MIPS16_16_PCREL_S1: 4089 return TRUE; 4090 4091 default: 4092 return FALSE; 4093 } 4094} 4095 4096static inline bfd_boolean 4097micromips_reloc_p (bfd_reloc_code_real_type reloc) 4098{ 4099 switch (reloc) 4100 { 4101 case BFD_RELOC_MICROMIPS_7_PCREL_S1: 4102 case BFD_RELOC_MICROMIPS_10_PCREL_S1: 4103 case BFD_RELOC_MICROMIPS_16_PCREL_S1: 4104 case BFD_RELOC_MICROMIPS_GPREL16: 4105 case BFD_RELOC_MICROMIPS_JMP: 4106 case BFD_RELOC_MICROMIPS_HI16: 4107 case BFD_RELOC_MICROMIPS_HI16_S: 4108 case BFD_RELOC_MICROMIPS_LO16: 4109 case BFD_RELOC_MICROMIPS_LITERAL: 4110 case BFD_RELOC_MICROMIPS_GOT16: 4111 case BFD_RELOC_MICROMIPS_CALL16: 4112 case BFD_RELOC_MICROMIPS_GOT_HI16: 4113 case BFD_RELOC_MICROMIPS_GOT_LO16: 4114 case BFD_RELOC_MICROMIPS_CALL_HI16: 4115 case BFD_RELOC_MICROMIPS_CALL_LO16: 4116 case BFD_RELOC_MICROMIPS_SUB: 4117 case BFD_RELOC_MICROMIPS_GOT_PAGE: 4118 case BFD_RELOC_MICROMIPS_GOT_OFST: 4119 case BFD_RELOC_MICROMIPS_GOT_DISP: 4120 case BFD_RELOC_MICROMIPS_HIGHEST: 4121 case BFD_RELOC_MICROMIPS_HIGHER: 4122 case BFD_RELOC_MICROMIPS_SCN_DISP: 4123 case BFD_RELOC_MICROMIPS_JALR: 4124 return TRUE; 4125 4126 default: 4127 return FALSE; 4128 } 4129} 4130 4131static inline bfd_boolean 4132jmp_reloc_p (bfd_reloc_code_real_type reloc) 4133{ 4134 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP; 4135} 4136 4137static inline bfd_boolean 4138b_reloc_p (bfd_reloc_code_real_type reloc) 4139{ 4140 return (reloc == BFD_RELOC_MIPS_26_PCREL_S2 4141 || reloc == BFD_RELOC_MIPS_21_PCREL_S2 4142 || reloc == BFD_RELOC_16_PCREL_S2 4143 || reloc == BFD_RELOC_MIPS16_16_PCREL_S1 4144 || reloc == BFD_RELOC_MICROMIPS_16_PCREL_S1 4145 || reloc == BFD_RELOC_MICROMIPS_10_PCREL_S1 4146 || reloc == BFD_RELOC_MICROMIPS_7_PCREL_S1); 4147} 4148 4149static inline bfd_boolean 4150got16_reloc_p (bfd_reloc_code_real_type reloc) 4151{ 4152 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16 4153 || reloc == BFD_RELOC_MICROMIPS_GOT16); 4154} 4155 4156static inline bfd_boolean 4157hi16_reloc_p (bfd_reloc_code_real_type reloc) 4158{ 4159 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S 4160 || reloc == BFD_RELOC_MICROMIPS_HI16_S); 4161} 4162 4163static inline bfd_boolean 4164lo16_reloc_p (bfd_reloc_code_real_type reloc) 4165{ 4166 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16 4167 || reloc == BFD_RELOC_MICROMIPS_LO16); 4168} 4169 4170static inline bfd_boolean 4171jalr_reloc_p (bfd_reloc_code_real_type reloc) 4172{ 4173 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR; 4174} 4175 4176static inline bfd_boolean 4177gprel16_reloc_p (bfd_reloc_code_real_type reloc) 4178{ 4179 return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL 4180 || reloc == BFD_RELOC_MICROMIPS_GPREL16); 4181} 4182 4183/* Return true if RELOC is a PC-relative relocation that does not have 4184 full address range. */ 4185 4186static inline bfd_boolean 4187limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc) 4188{ 4189 switch (reloc) 4190 { 4191 case BFD_RELOC_16_PCREL_S2: 4192 case BFD_RELOC_MIPS16_16_PCREL_S1: 4193 case BFD_RELOC_MICROMIPS_7_PCREL_S1: 4194 case BFD_RELOC_MICROMIPS_10_PCREL_S1: 4195 case BFD_RELOC_MICROMIPS_16_PCREL_S1: 4196 case BFD_RELOC_MIPS_21_PCREL_S2: 4197 case BFD_RELOC_MIPS_26_PCREL_S2: 4198 case BFD_RELOC_MIPS_18_PCREL_S3: 4199 case BFD_RELOC_MIPS_19_PCREL_S2: 4200 return TRUE; 4201 4202 case BFD_RELOC_32_PCREL: 4203 case BFD_RELOC_HI16_S_PCREL: 4204 case BFD_RELOC_LO16_PCREL: 4205 return HAVE_64BIT_ADDRESSES; 4206 4207 default: 4208 return FALSE; 4209 } 4210} 4211 4212/* Return true if the given relocation might need a matching %lo(). 4213 This is only "might" because SVR4 R_MIPS_GOT16 relocations only 4214 need a matching %lo() when applied to local symbols. */ 4215 4216static inline bfd_boolean 4217reloc_needs_lo_p (bfd_reloc_code_real_type reloc) 4218{ 4219 return (HAVE_IN_PLACE_ADDENDS 4220 && (hi16_reloc_p (reloc) 4221 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); 4222 all GOT16 relocations evaluate to "G". */ 4223 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC))); 4224} 4225 4226/* Return the type of %lo() reloc needed by RELOC, given that 4227 reloc_needs_lo_p. */ 4228 4229static inline bfd_reloc_code_real_type 4230matching_lo_reloc (bfd_reloc_code_real_type reloc) 4231{ 4232 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 4233 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16 4234 : BFD_RELOC_LO16)); 4235} 4236 4237/* Return true if the given fixup is followed by a matching R_MIPS_LO16 4238 relocation. */ 4239 4240static inline bfd_boolean 4241fixup_has_matching_lo_p (fixS *fixp) 4242{ 4243 return (fixp->fx_next != NULL 4244 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type) 4245 && fixp->fx_addsy == fixp->fx_next->fx_addsy 4246 && fixp->fx_offset == fixp->fx_next->fx_offset); 4247} 4248 4249/* Move all labels in LABELS to the current insertion point. TEXT_P 4250 says whether the labels refer to text or data. */ 4251 4252static void 4253mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p) 4254{ 4255 struct insn_label_list *l; 4256 valueT val; 4257 4258 for (l = labels; l != NULL; l = l->next) 4259 { 4260 gas_assert (S_GET_SEGMENT (l->label) == now_seg); 4261 symbol_set_frag (l->label, frag_now); 4262 val = (valueT) frag_now_fix (); 4263 /* MIPS16/microMIPS text labels are stored as odd. */ 4264 if (text_p && HAVE_CODE_COMPRESSION) 4265 ++val; 4266 S_SET_VALUE (l->label, val); 4267 } 4268} 4269 4270/* Move all labels in insn_labels to the current insertion point 4271 and treat them as text labels. */ 4272 4273static void 4274mips_move_text_labels (void) 4275{ 4276 mips_move_labels (seg_info (now_seg)->label_list, TRUE); 4277} 4278 4279/* Duplicate the test for LINK_ONCE sections as in `adjust_reloc_syms'. */ 4280 4281static bfd_boolean 4282s_is_linkonce (symbolS *sym, segT from_seg) 4283{ 4284 bfd_boolean linkonce = FALSE; 4285 segT symseg = S_GET_SEGMENT (sym); 4286 4287 if (symseg != from_seg && !S_IS_LOCAL (sym)) 4288 { 4289 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE)) 4290 linkonce = TRUE; 4291 /* The GNU toolchain uses an extension for ELF: a section 4292 beginning with the magic string .gnu.linkonce is a 4293 linkonce section. */ 4294 if (strncmp (segment_name (symseg), ".gnu.linkonce", 4295 sizeof ".gnu.linkonce" - 1) == 0) 4296 linkonce = TRUE; 4297 } 4298 return linkonce; 4299} 4300 4301/* Mark MIPS16 or microMIPS instruction label LABEL. This permits the 4302 linker to handle them specially, such as generating jalx instructions 4303 when needed. We also make them odd for the duration of the assembly, 4304 in order to generate the right sort of code. We will make them even 4305 in the adjust_symtab routine, while leaving them marked. This is 4306 convenient for the debugger and the disassembler. The linker knows 4307 to make them odd again. */ 4308 4309static void 4310mips_compressed_mark_label (symbolS *label) 4311{ 4312 gas_assert (HAVE_CODE_COMPRESSION); 4313 4314 if (mips_opts.mips16) 4315 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label))); 4316 else 4317 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label))); 4318 if ((S_GET_VALUE (label) & 1) == 0 4319 /* Don't adjust the address if the label is global or weak, or 4320 in a link-once section, since we'll be emitting symbol reloc 4321 references to it which will be patched up by the linker, and 4322 the final value of the symbol may or may not be MIPS16/microMIPS. */ 4323 && !S_IS_WEAK (label) 4324 && !S_IS_EXTERNAL (label) 4325 && !s_is_linkonce (label, now_seg)) 4326 S_SET_VALUE (label, S_GET_VALUE (label) | 1); 4327} 4328 4329/* Mark preceding MIPS16 or microMIPS instruction labels. */ 4330 4331static void 4332mips_compressed_mark_labels (void) 4333{ 4334 struct insn_label_list *l; 4335 4336 for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next) 4337 mips_compressed_mark_label (l->label); 4338} 4339 4340/* End the current frag. Make it a variant frag and record the 4341 relaxation info. */ 4342 4343static void 4344relax_close_frag (void) 4345{ 4346 mips_macro_warning.first_frag = frag_now; 4347 frag_var (rs_machine_dependent, 0, 0, 4348 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), 4349 mips_relax.symbol, 0, (char *) mips_relax.first_fixup); 4350 4351 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); 4352 mips_relax.first_fixup = 0; 4353} 4354 4355/* Start a new relaxation sequence whose expansion depends on SYMBOL. 4356 See the comment above RELAX_ENCODE for more details. */ 4357 4358static void 4359relax_start (symbolS *symbol) 4360{ 4361 gas_assert (mips_relax.sequence == 0); 4362 mips_relax.sequence = 1; 4363 mips_relax.symbol = symbol; 4364} 4365 4366/* Start generating the second version of a relaxable sequence. 4367 See the comment above RELAX_ENCODE for more details. */ 4368 4369static void 4370relax_switch (void) 4371{ 4372 gas_assert (mips_relax.sequence == 1); 4373 mips_relax.sequence = 2; 4374} 4375 4376/* End the current relaxable sequence. */ 4377 4378static void 4379relax_end (void) 4380{ 4381 gas_assert (mips_relax.sequence == 2); 4382 relax_close_frag (); 4383 mips_relax.sequence = 0; 4384} 4385 4386/* Return true if IP is a delayed branch or jump. */ 4387 4388static inline bfd_boolean 4389delayed_branch_p (const struct mips_cl_insn *ip) 4390{ 4391 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY 4392 | INSN_COND_BRANCH_DELAY 4393 | INSN_COND_BRANCH_LIKELY)) != 0; 4394} 4395 4396/* Return true if IP is a compact branch or jump. */ 4397 4398static inline bfd_boolean 4399compact_branch_p (const struct mips_cl_insn *ip) 4400{ 4401 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH 4402 | INSN2_COND_BRANCH)) != 0; 4403} 4404 4405/* Return true if IP is an unconditional branch or jump. */ 4406 4407static inline bfd_boolean 4408uncond_branch_p (const struct mips_cl_insn *ip) 4409{ 4410 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0 4411 || (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0); 4412} 4413 4414/* Return true if IP is a branch-likely instruction. */ 4415 4416static inline bfd_boolean 4417branch_likely_p (const struct mips_cl_insn *ip) 4418{ 4419 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0; 4420} 4421 4422/* Return the type of nop that should be used to fill the delay slot 4423 of delayed branch IP. */ 4424 4425static struct mips_cl_insn * 4426get_delay_slot_nop (const struct mips_cl_insn *ip) 4427{ 4428 if (mips_opts.micromips 4429 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) 4430 return µmips_nop32_insn; 4431 return NOP_INSN; 4432} 4433 4434/* Return a mask that has bit N set if OPCODE reads the register(s) 4435 in operand N. */ 4436 4437static unsigned int 4438insn_read_mask (const struct mips_opcode *opcode) 4439{ 4440 return (opcode->pinfo & INSN_READ_ALL) >> INSN_READ_SHIFT; 4441} 4442 4443/* Return a mask that has bit N set if OPCODE writes to the register(s) 4444 in operand N. */ 4445 4446static unsigned int 4447insn_write_mask (const struct mips_opcode *opcode) 4448{ 4449 return (opcode->pinfo & INSN_WRITE_ALL) >> INSN_WRITE_SHIFT; 4450} 4451 4452/* Return a mask of the registers specified by operand OPERAND of INSN. 4453 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK 4454 is set. */ 4455 4456static unsigned int 4457operand_reg_mask (const struct mips_cl_insn *insn, 4458 const struct mips_operand *operand, 4459 unsigned int type_mask) 4460{ 4461 unsigned int uval, vsel; 4462 4463 switch (operand->type) 4464 { 4465 case OP_INT: 4466 case OP_MAPPED_INT: 4467 case OP_MSB: 4468 case OP_PCREL: 4469 case OP_PERF_REG: 4470 case OP_ADDIUSP_INT: 4471 case OP_ENTRY_EXIT_LIST: 4472 case OP_REPEAT_DEST_REG: 4473 case OP_REPEAT_PREV_REG: 4474 case OP_PC: 4475 case OP_VU0_SUFFIX: 4476 case OP_VU0_MATCH_SUFFIX: 4477 case OP_IMM_INDEX: 4478 abort (); 4479 4480 case OP_REG: 4481 case OP_OPTIONAL_REG: 4482 { 4483 const struct mips_reg_operand *reg_op; 4484 4485 reg_op = (const struct mips_reg_operand *) operand; 4486 if (!(type_mask & (1 << reg_op->reg_type))) 4487 return 0; 4488 uval = insn_extract_operand (insn, operand); 4489 return 1 << mips_decode_reg_operand (reg_op, uval); 4490 } 4491 4492 case OP_REG_PAIR: 4493 { 4494 const struct mips_reg_pair_operand *pair_op; 4495 4496 pair_op = (const struct mips_reg_pair_operand *) operand; 4497 if (!(type_mask & (1 << pair_op->reg_type))) 4498 return 0; 4499 uval = insn_extract_operand (insn, operand); 4500 return (1 << pair_op->reg1_map[uval]) | (1 << pair_op->reg2_map[uval]); 4501 } 4502 4503 case OP_CLO_CLZ_DEST: 4504 if (!(type_mask & (1 << OP_REG_GP))) 4505 return 0; 4506 uval = insn_extract_operand (insn, operand); 4507 return (1 << (uval & 31)) | (1 << (uval >> 5)); 4508 4509 case OP_SAME_RS_RT: 4510 if (!(type_mask & (1 << OP_REG_GP))) 4511 return 0; 4512 uval = insn_extract_operand (insn, operand); 4513 gas_assert ((uval & 31) == (uval >> 5)); 4514 return 1 << (uval & 31); 4515 4516 case OP_CHECK_PREV: 4517 case OP_NON_ZERO_REG: 4518 if (!(type_mask & (1 << OP_REG_GP))) 4519 return 0; 4520 uval = insn_extract_operand (insn, operand); 4521 return 1 << (uval & 31); 4522 4523 case OP_LWM_SWM_LIST: 4524 abort (); 4525 4526 case OP_SAVE_RESTORE_LIST: 4527 abort (); 4528 4529 case OP_MDMX_IMM_REG: 4530 if (!(type_mask & (1 << OP_REG_VEC))) 4531 return 0; 4532 uval = insn_extract_operand (insn, operand); 4533 vsel = uval >> 5; 4534 if ((vsel & 0x18) == 0x18) 4535 return 0; 4536 return 1 << (uval & 31); 4537 4538 case OP_REG_INDEX: 4539 if (!(type_mask & (1 << OP_REG_GP))) 4540 return 0; 4541 return 1 << insn_extract_operand (insn, operand); 4542 } 4543 abort (); 4544} 4545 4546/* Return a mask of the registers specified by operands OPNO_MASK of INSN, 4547 where bit N of OPNO_MASK is set if operand N should be included. 4548 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK 4549 is set. */ 4550 4551static unsigned int 4552insn_reg_mask (const struct mips_cl_insn *insn, 4553 unsigned int type_mask, unsigned int opno_mask) 4554{ 4555 unsigned int opno, reg_mask; 4556 4557 opno = 0; 4558 reg_mask = 0; 4559 while (opno_mask != 0) 4560 { 4561 if (opno_mask & 1) 4562 reg_mask |= operand_reg_mask (insn, insn_opno (insn, opno), type_mask); 4563 opno_mask >>= 1; 4564 opno += 1; 4565 } 4566 return reg_mask; 4567} 4568 4569/* Return the mask of core registers that IP reads. */ 4570 4571static unsigned int 4572gpr_read_mask (const struct mips_cl_insn *ip) 4573{ 4574 unsigned long pinfo, pinfo2; 4575 unsigned int mask; 4576 4577 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_read_mask (ip->insn_mo)); 4578 pinfo = ip->insn_mo->pinfo; 4579 pinfo2 = ip->insn_mo->pinfo2; 4580 if (pinfo & INSN_UDI) 4581 { 4582 /* UDI instructions have traditionally been assumed to read RS 4583 and RT. */ 4584 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); 4585 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); 4586 } 4587 if (pinfo & INSN_READ_GPR_24) 4588 mask |= 1 << 24; 4589 if (pinfo2 & INSN2_READ_GPR_16) 4590 mask |= 1 << 16; 4591 if (pinfo2 & INSN2_READ_SP) 4592 mask |= 1 << SP; 4593 if (pinfo2 & INSN2_READ_GPR_31) 4594 mask |= 1 << 31; 4595 /* Don't include register 0. */ 4596 return mask & ~1; 4597} 4598 4599/* Return the mask of core registers that IP writes. */ 4600 4601static unsigned int 4602gpr_write_mask (const struct mips_cl_insn *ip) 4603{ 4604 unsigned long pinfo, pinfo2; 4605 unsigned int mask; 4606 4607 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_write_mask (ip->insn_mo)); 4608 pinfo = ip->insn_mo->pinfo; 4609 pinfo2 = ip->insn_mo->pinfo2; 4610 if (pinfo & INSN_WRITE_GPR_24) 4611 mask |= 1 << 24; 4612 if (pinfo & INSN_WRITE_GPR_31) 4613 mask |= 1 << 31; 4614 if (pinfo & INSN_UDI) 4615 /* UDI instructions have traditionally been assumed to write to RD. */ 4616 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); 4617 if (pinfo2 & INSN2_WRITE_SP) 4618 mask |= 1 << SP; 4619 /* Don't include register 0. */ 4620 return mask & ~1; 4621} 4622 4623/* Return the mask of floating-point registers that IP reads. */ 4624 4625static unsigned int 4626fpr_read_mask (const struct mips_cl_insn *ip) 4627{ 4628 unsigned long pinfo; 4629 unsigned int mask; 4630 4631 mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC) 4632 | (1 << OP_REG_MSA)), 4633 insn_read_mask (ip->insn_mo)); 4634 pinfo = ip->insn_mo->pinfo; 4635 /* Conservatively treat all operands to an FP_D instruction are doubles. 4636 (This is overly pessimistic for things like cvt.d.s.) */ 4637 if (FPR_SIZE != 64 && (pinfo & FP_D)) 4638 mask |= mask << 1; 4639 return mask; 4640} 4641 4642/* Return the mask of floating-point registers that IP writes. */ 4643 4644static unsigned int 4645fpr_write_mask (const struct mips_cl_insn *ip) 4646{ 4647 unsigned long pinfo; 4648 unsigned int mask; 4649 4650 mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC) 4651 | (1 << OP_REG_MSA)), 4652 insn_write_mask (ip->insn_mo)); 4653 pinfo = ip->insn_mo->pinfo; 4654 /* Conservatively treat all operands to an FP_D instruction are doubles. 4655 (This is overly pessimistic for things like cvt.s.d.) */ 4656 if (FPR_SIZE != 64 && (pinfo & FP_D)) 4657 mask |= mask << 1; 4658 return mask; 4659} 4660 4661/* Operand OPNUM of INSN is an odd-numbered floating-point register. 4662 Check whether that is allowed. */ 4663 4664static bfd_boolean 4665mips_oddfpreg_ok (const struct mips_opcode *insn, int opnum) 4666{ 4667 const char *s = insn->name; 4668 bfd_boolean oddspreg = (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa, mips_opts.arch) 4669 || FPR_SIZE == 64) 4670 && mips_opts.oddspreg; 4671 4672 if (insn->pinfo == INSN_MACRO) 4673 /* Let a macro pass, we'll catch it later when it is expanded. */ 4674 return TRUE; 4675 4676 /* Single-precision coprocessor loads and moves are OK for 32-bit registers, 4677 otherwise it depends on oddspreg. */ 4678 if ((insn->pinfo & FP_S) 4679 && (insn->pinfo & (INSN_LOAD_MEMORY | INSN_STORE_MEMORY 4680 | INSN_LOAD_COPROC | INSN_COPROC_MOVE))) 4681 return FPR_SIZE == 32 || oddspreg; 4682 4683 /* Allow odd registers for single-precision ops and double-precision if the 4684 floating-point registers are 64-bit wide. */ 4685 switch (insn->pinfo & (FP_S | FP_D)) 4686 { 4687 case FP_S: 4688 case 0: 4689 return oddspreg; 4690 case FP_D: 4691 return FPR_SIZE == 64; 4692 default: 4693 break; 4694 } 4695 4696 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ 4697 s = strchr (insn->name, '.'); 4698 if (s != NULL && opnum == 2) 4699 s = strchr (s + 1, '.'); 4700 if (s != NULL && (s[1] == 'w' || s[1] == 's')) 4701 return oddspreg; 4702 4703 return FPR_SIZE == 64; 4704} 4705 4706/* Information about an instruction argument that we're trying to match. */ 4707struct mips_arg_info 4708{ 4709 /* The instruction so far. */ 4710 struct mips_cl_insn *insn; 4711 4712 /* The first unconsumed operand token. */ 4713 struct mips_operand_token *token; 4714 4715 /* The 1-based operand number, in terms of insn->insn_mo->args. */ 4716 int opnum; 4717 4718 /* The 1-based argument number, for error reporting. This does not 4719 count elided optional registers, etc.. */ 4720 int argnum; 4721 4722 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */ 4723 unsigned int last_regno; 4724 4725 /* If the first operand was an OP_REG, this is the register that it 4726 specified, otherwise it is ILLEGAL_REG. */ 4727 unsigned int dest_regno; 4728 4729 /* The value of the last OP_INT operand. Only used for OP_MSB, 4730 where it gives the lsb position. */ 4731 unsigned int last_op_int; 4732 4733 /* If true, match routines should assume that no later instruction 4734 alternative matches and should therefore be as accommodating as 4735 possible. Match routines should not report errors if something 4736 is only invalid for !LAX_MATCH. */ 4737 bfd_boolean lax_match; 4738 4739 /* True if a reference to the current AT register was seen. */ 4740 bfd_boolean seen_at; 4741}; 4742 4743/* Record that the argument is out of range. */ 4744 4745static void 4746match_out_of_range (struct mips_arg_info *arg) 4747{ 4748 set_insn_error_i (arg->argnum, _("operand %d out of range"), arg->argnum); 4749} 4750 4751/* Record that the argument isn't constant but needs to be. */ 4752 4753static void 4754match_not_constant (struct mips_arg_info *arg) 4755{ 4756 set_insn_error_i (arg->argnum, _("operand %d must be constant"), 4757 arg->argnum); 4758} 4759 4760/* Try to match an OT_CHAR token for character CH. Consume the token 4761 and return true on success, otherwise return false. */ 4762 4763static bfd_boolean 4764match_char (struct mips_arg_info *arg, char ch) 4765{ 4766 if (arg->token->type == OT_CHAR && arg->token->u.ch == ch) 4767 { 4768 ++arg->token; 4769 if (ch == ',') 4770 arg->argnum += 1; 4771 return TRUE; 4772 } 4773 return FALSE; 4774} 4775 4776/* Try to get an expression from the next tokens in ARG. Consume the 4777 tokens and return true on success, storing the expression value in 4778 VALUE and relocation types in R. */ 4779 4780static bfd_boolean 4781match_expression (struct mips_arg_info *arg, expressionS *value, 4782 bfd_reloc_code_real_type *r) 4783{ 4784 /* If the next token is a '(' that was parsed as being part of a base 4785 expression, assume we have an elided offset. The later match will fail 4786 if this turns out to be wrong. */ 4787 if (arg->token->type == OT_CHAR && arg->token->u.ch == '(') 4788 { 4789 value->X_op = O_constant; 4790 value->X_add_number = 0; 4791 r[0] = r[1] = r[2] = BFD_RELOC_UNUSED; 4792 return TRUE; 4793 } 4794 4795 /* Reject register-based expressions such as "0+$2" and "(($2))". 4796 For plain registers the default error seems more appropriate. */ 4797 if (arg->token->type == OT_INTEGER 4798 && arg->token->u.integer.value.X_op == O_register) 4799 { 4800 set_insn_error (arg->argnum, _("register value used as expression")); 4801 return FALSE; 4802 } 4803 4804 if (arg->token->type == OT_INTEGER) 4805 { 4806 *value = arg->token->u.integer.value; 4807 memcpy (r, arg->token->u.integer.relocs, 3 * sizeof (*r)); 4808 ++arg->token; 4809 return TRUE; 4810 } 4811 4812 set_insn_error_i 4813 (arg->argnum, _("operand %d must be an immediate expression"), 4814 arg->argnum); 4815 return FALSE; 4816} 4817 4818/* Try to get a constant expression from the next tokens in ARG. Consume 4819 the tokens and return return true on success, storing the constant value 4820 in *VALUE. Use FALLBACK as the value if the match succeeded with an 4821 error. */ 4822 4823static bfd_boolean 4824match_const_int (struct mips_arg_info *arg, offsetT *value) 4825{ 4826 expressionS ex; 4827 bfd_reloc_code_real_type r[3]; 4828 4829 if (!match_expression (arg, &ex, r)) 4830 return FALSE; 4831 4832 if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_constant) 4833 *value = ex.X_add_number; 4834 else 4835 { 4836 match_not_constant (arg); 4837 return FALSE; 4838 } 4839 return TRUE; 4840} 4841 4842/* Return the RTYPE_* flags for a register operand of type TYPE that 4843 appears in instruction OPCODE. */ 4844 4845static unsigned int 4846convert_reg_type (const struct mips_opcode *opcode, 4847 enum mips_reg_operand_type type) 4848{ 4849 switch (type) 4850 { 4851 case OP_REG_GP: 4852 return RTYPE_NUM | RTYPE_GP; 4853 4854 case OP_REG_FP: 4855 /* Allow vector register names for MDMX if the instruction is a 64-bit 4856 FPR load, store or move (including moves to and from GPRs). */ 4857 if ((mips_opts.ase & ASE_MDMX) 4858 && (opcode->pinfo & FP_D) 4859 && (opcode->pinfo & (INSN_COPROC_MOVE 4860 | INSN_COPROC_MEMORY_DELAY 4861 | INSN_LOAD_COPROC 4862 | INSN_LOAD_MEMORY 4863 | INSN_STORE_MEMORY))) 4864 return RTYPE_FPU | RTYPE_VEC; 4865 return RTYPE_FPU; 4866 4867 case OP_REG_CCC: 4868 if (opcode->pinfo & (FP_D | FP_S)) 4869 return RTYPE_CCC | RTYPE_FCC; 4870 return RTYPE_CCC; 4871 4872 case OP_REG_VEC: 4873 if (opcode->membership & INSN_5400) 4874 return RTYPE_FPU; 4875 return RTYPE_FPU | RTYPE_VEC; 4876 4877 case OP_REG_ACC: 4878 return RTYPE_ACC; 4879 4880 case OP_REG_COPRO: 4881 if (opcode->name[strlen (opcode->name) - 1] == '0') 4882 return RTYPE_NUM | RTYPE_CP0; 4883 return RTYPE_NUM; 4884 4885 case OP_REG_HW: 4886 return RTYPE_NUM; 4887 4888 case OP_REG_VI: 4889 return RTYPE_NUM | RTYPE_VI; 4890 4891 case OP_REG_VF: 4892 return RTYPE_NUM | RTYPE_VF; 4893 4894 case OP_REG_R5900_I: 4895 return RTYPE_R5900_I; 4896 4897 case OP_REG_R5900_Q: 4898 return RTYPE_R5900_Q; 4899 4900 case OP_REG_R5900_R: 4901 return RTYPE_R5900_R; 4902 4903 case OP_REG_R5900_ACC: 4904 return RTYPE_R5900_ACC; 4905 4906 case OP_REG_MSA: 4907 return RTYPE_MSA; 4908 4909 case OP_REG_MSA_CTRL: 4910 return RTYPE_NUM; 4911 } 4912 abort (); 4913} 4914 4915/* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */ 4916 4917static void 4918check_regno (struct mips_arg_info *arg, 4919 enum mips_reg_operand_type type, unsigned int regno) 4920{ 4921 if (AT && type == OP_REG_GP && regno == AT) 4922 arg->seen_at = TRUE; 4923 4924 if (type == OP_REG_FP 4925 && (regno & 1) != 0 4926 && !mips_oddfpreg_ok (arg->insn->insn_mo, arg->opnum)) 4927 { 4928 /* This was a warning prior to introducing O32 FPXX and FP64 support 4929 so maintain a warning for FP32 but raise an error for the new 4930 cases. */ 4931 if (FPR_SIZE == 32) 4932 as_warn (_("float register should be even, was %d"), regno); 4933 else 4934 as_bad (_("float register should be even, was %d"), regno); 4935 } 4936 4937 if (type == OP_REG_CCC) 4938 { 4939 const char *name; 4940 size_t length; 4941 4942 name = arg->insn->insn_mo->name; 4943 length = strlen (name); 4944 if ((regno & 1) != 0 4945 && ((length >= 3 && strcmp (name + length - 3, ".ps") == 0) 4946 || (length >= 5 && strncmp (name + length - 5, "any2", 4) == 0))) 4947 as_warn (_("condition code register should be even for %s, was %d"), 4948 name, regno); 4949 4950 if ((regno & 3) != 0 4951 && (length >= 5 && strncmp (name + length - 5, "any4", 4) == 0)) 4952 as_warn (_("condition code register should be 0 or 4 for %s, was %d"), 4953 name, regno); 4954 } 4955} 4956 4957/* ARG is a register with symbol value SYMVAL. Try to interpret it as 4958 a register of type TYPE. Return true on success, storing the register 4959 number in *REGNO and warning about any dubious uses. */ 4960 4961static bfd_boolean 4962match_regno (struct mips_arg_info *arg, enum mips_reg_operand_type type, 4963 unsigned int symval, unsigned int *regno) 4964{ 4965 if (type == OP_REG_VEC) 4966 symval = mips_prefer_vec_regno (symval); 4967 if (!(symval & convert_reg_type (arg->insn->insn_mo, type))) 4968 return FALSE; 4969 4970 *regno = symval & RNUM_MASK; 4971 check_regno (arg, type, *regno); 4972 return TRUE; 4973} 4974 4975/* Try to interpret the next token in ARG as a register of type TYPE. 4976 Consume the token and return true on success, storing the register 4977 number in *REGNO. Return false on failure. */ 4978 4979static bfd_boolean 4980match_reg (struct mips_arg_info *arg, enum mips_reg_operand_type type, 4981 unsigned int *regno) 4982{ 4983 if (arg->token->type == OT_REG 4984 && match_regno (arg, type, arg->token->u.regno, regno)) 4985 { 4986 ++arg->token; 4987 return TRUE; 4988 } 4989 return FALSE; 4990} 4991 4992/* Try to interpret the next token in ARG as a range of registers of type TYPE. 4993 Consume the token and return true on success, storing the register numbers 4994 in *REGNO1 and *REGNO2. Return false on failure. */ 4995 4996static bfd_boolean 4997match_reg_range (struct mips_arg_info *arg, enum mips_reg_operand_type type, 4998 unsigned int *regno1, unsigned int *regno2) 4999{ 5000 if (match_reg (arg, type, regno1)) 5001 { 5002 *regno2 = *regno1; 5003 return TRUE; 5004 } 5005 if (arg->token->type == OT_REG_RANGE 5006 && match_regno (arg, type, arg->token->u.reg_range.regno1, regno1) 5007 && match_regno (arg, type, arg->token->u.reg_range.regno2, regno2) 5008 && *regno1 <= *regno2) 5009 { 5010 ++arg->token; 5011 return TRUE; 5012 } 5013 return FALSE; 5014} 5015 5016/* OP_INT matcher. */ 5017 5018static bfd_boolean 5019match_int_operand (struct mips_arg_info *arg, 5020 const struct mips_operand *operand_base) 5021{ 5022 const struct mips_int_operand *operand; 5023 unsigned int uval; 5024 int min_val, max_val, factor; 5025 offsetT sval; 5026 5027 operand = (const struct mips_int_operand *) operand_base; 5028 factor = 1 << operand->shift; 5029 min_val = mips_int_operand_min (operand); 5030 max_val = mips_int_operand_max (operand); 5031 5032 if (operand_base->lsb == 0 5033 && operand_base->size == 16 5034 && operand->shift == 0 5035 && operand->bias == 0 5036 && (operand->max_val == 32767 || operand->max_val == 65535)) 5037 { 5038 /* The operand can be relocated. */ 5039 if (!match_expression (arg, &offset_expr, offset_reloc)) 5040 return FALSE; 5041 5042 if (offset_reloc[0] != BFD_RELOC_UNUSED) 5043 /* Relocation operators were used. Accept the arguent and 5044 leave the relocation value in offset_expr and offset_relocs 5045 for the caller to process. */ 5046 return TRUE; 5047 5048 if (offset_expr.X_op != O_constant) 5049 { 5050 /* Accept non-constant operands if no later alternative matches, 5051 leaving it for the caller to process. */ 5052 if (!arg->lax_match) 5053 return FALSE; 5054 offset_reloc[0] = BFD_RELOC_LO16; 5055 return TRUE; 5056 } 5057 5058 /* Clear the global state; we're going to install the operand 5059 ourselves. */ 5060 sval = offset_expr.X_add_number; 5061 offset_expr.X_op = O_absent; 5062 5063 /* For compatibility with older assemblers, we accept 5064 0x8000-0xffff as signed 16-bit numbers when only 5065 signed numbers are allowed. */ 5066 if (sval > max_val) 5067 { 5068 max_val = ((1 << operand_base->size) - 1) << operand->shift; 5069 if (!arg->lax_match && sval <= max_val) 5070 return FALSE; 5071 } 5072 } 5073 else 5074 { 5075 if (!match_const_int (arg, &sval)) 5076 return FALSE; 5077 } 5078 5079 arg->last_op_int = sval; 5080 5081 if (sval < min_val || sval > max_val || sval % factor) 5082 { 5083 match_out_of_range (arg); 5084 return FALSE; 5085 } 5086 5087 uval = (unsigned int) sval >> operand->shift; 5088 uval -= operand->bias; 5089 5090 /* Handle -mfix-cn63xxp1. */ 5091 if (arg->opnum == 1 5092 && mips_fix_cn63xxp1 5093 && !mips_opts.micromips 5094 && strcmp ("pref", arg->insn->insn_mo->name) == 0) 5095 switch (uval) 5096 { 5097 case 5: 5098 case 25: 5099 case 26: 5100 case 27: 5101 case 28: 5102 case 29: 5103 case 30: 5104 case 31: 5105 /* These are ok. */ 5106 break; 5107 5108 default: 5109 /* The rest must be changed to 28. */ 5110 uval = 28; 5111 break; 5112 } 5113 5114 insn_insert_operand (arg->insn, operand_base, uval); 5115 return TRUE; 5116} 5117 5118/* OP_MAPPED_INT matcher. */ 5119 5120static bfd_boolean 5121match_mapped_int_operand (struct mips_arg_info *arg, 5122 const struct mips_operand *operand_base) 5123{ 5124 const struct mips_mapped_int_operand *operand; 5125 unsigned int uval, num_vals; 5126 offsetT sval; 5127 5128 operand = (const struct mips_mapped_int_operand *) operand_base; 5129 if (!match_const_int (arg, &sval)) 5130 return FALSE; 5131 5132 num_vals = 1 << operand_base->size; 5133 for (uval = 0; uval < num_vals; uval++) 5134 if (operand->int_map[uval] == sval) 5135 break; 5136 if (uval == num_vals) 5137 { 5138 match_out_of_range (arg); 5139 return FALSE; 5140 } 5141 5142 insn_insert_operand (arg->insn, operand_base, uval); 5143 return TRUE; 5144} 5145 5146/* OP_MSB matcher. */ 5147 5148static bfd_boolean 5149match_msb_operand (struct mips_arg_info *arg, 5150 const struct mips_operand *operand_base) 5151{ 5152 const struct mips_msb_operand *operand; 5153 int min_val, max_val, max_high; 5154 offsetT size, sval, high; 5155 5156 operand = (const struct mips_msb_operand *) operand_base; 5157 min_val = operand->bias; 5158 max_val = min_val + (1 << operand_base->size) - 1; 5159 max_high = operand->opsize; 5160 5161 if (!match_const_int (arg, &size)) 5162 return FALSE; 5163 5164 high = size + arg->last_op_int; 5165 sval = operand->add_lsb ? high : size; 5166 5167 if (size < 0 || high > max_high || sval < min_val || sval > max_val) 5168 { 5169 match_out_of_range (arg); 5170 return FALSE; 5171 } 5172 insn_insert_operand (arg->insn, operand_base, sval - min_val); 5173 return TRUE; 5174} 5175 5176/* OP_REG matcher. */ 5177 5178static bfd_boolean 5179match_reg_operand (struct mips_arg_info *arg, 5180 const struct mips_operand *operand_base) 5181{ 5182 const struct mips_reg_operand *operand; 5183 unsigned int regno, uval, num_vals; 5184 5185 operand = (const struct mips_reg_operand *) operand_base; 5186 if (!match_reg (arg, operand->reg_type, ®no)) 5187 return FALSE; 5188 5189 if (operand->reg_map) 5190 { 5191 num_vals = 1 << operand->root.size; 5192 for (uval = 0; uval < num_vals; uval++) 5193 if (operand->reg_map[uval] == regno) 5194 break; 5195 if (num_vals == uval) 5196 return FALSE; 5197 } 5198 else 5199 uval = regno; 5200 5201 arg->last_regno = regno; 5202 if (arg->opnum == 1) 5203 arg->dest_regno = regno; 5204 insn_insert_operand (arg->insn, operand_base, uval); 5205 return TRUE; 5206} 5207 5208/* OP_REG_PAIR matcher. */ 5209 5210static bfd_boolean 5211match_reg_pair_operand (struct mips_arg_info *arg, 5212 const struct mips_operand *operand_base) 5213{ 5214 const struct mips_reg_pair_operand *operand; 5215 unsigned int regno1, regno2, uval, num_vals; 5216 5217 operand = (const struct mips_reg_pair_operand *) operand_base; 5218 if (!match_reg (arg, operand->reg_type, ®no1) 5219 || !match_char (arg, ',') 5220 || !match_reg (arg, operand->reg_type, ®no2)) 5221 return FALSE; 5222 5223 num_vals = 1 << operand_base->size; 5224 for (uval = 0; uval < num_vals; uval++) 5225 if (operand->reg1_map[uval] == regno1 && operand->reg2_map[uval] == regno2) 5226 break; 5227 if (uval == num_vals) 5228 return FALSE; 5229 5230 insn_insert_operand (arg->insn, operand_base, uval); 5231 return TRUE; 5232} 5233 5234/* OP_PCREL matcher. The caller chooses the relocation type. */ 5235 5236static bfd_boolean 5237match_pcrel_operand (struct mips_arg_info *arg) 5238{ 5239 bfd_reloc_code_real_type r[3]; 5240 5241 return match_expression (arg, &offset_expr, r) && r[0] == BFD_RELOC_UNUSED; 5242} 5243 5244/* OP_PERF_REG matcher. */ 5245 5246static bfd_boolean 5247match_perf_reg_operand (struct mips_arg_info *arg, 5248 const struct mips_operand *operand) 5249{ 5250 offsetT sval; 5251 5252 if (!match_const_int (arg, &sval)) 5253 return FALSE; 5254 5255 if (sval != 0 5256 && (sval != 1 5257 || (mips_opts.arch == CPU_R5900 5258 && (strcmp (arg->insn->insn_mo->name, "mfps") == 0 5259 || strcmp (arg->insn->insn_mo->name, "mtps") == 0)))) 5260 { 5261 set_insn_error (arg->argnum, _("invalid performance register")); 5262 return FALSE; 5263 } 5264 5265 insn_insert_operand (arg->insn, operand, sval); 5266 return TRUE; 5267} 5268 5269/* OP_ADDIUSP matcher. */ 5270 5271static bfd_boolean 5272match_addiusp_operand (struct mips_arg_info *arg, 5273 const struct mips_operand *operand) 5274{ 5275 offsetT sval; 5276 unsigned int uval; 5277 5278 if (!match_const_int (arg, &sval)) 5279 return FALSE; 5280 5281 if (sval % 4) 5282 { 5283 match_out_of_range (arg); 5284 return FALSE; 5285 } 5286 5287 sval /= 4; 5288 if (!(sval >= -258 && sval <= 257) || (sval >= -2 && sval <= 1)) 5289 { 5290 match_out_of_range (arg); 5291 return FALSE; 5292 } 5293 5294 uval = (unsigned int) sval; 5295 uval = ((uval >> 1) & ~0xff) | (uval & 0xff); 5296 insn_insert_operand (arg->insn, operand, uval); 5297 return TRUE; 5298} 5299 5300/* OP_CLO_CLZ_DEST matcher. */ 5301 5302static bfd_boolean 5303match_clo_clz_dest_operand (struct mips_arg_info *arg, 5304 const struct mips_operand *operand) 5305{ 5306 unsigned int regno; 5307 5308 if (!match_reg (arg, OP_REG_GP, ®no)) 5309 return FALSE; 5310 5311 insn_insert_operand (arg->insn, operand, regno | (regno << 5)); 5312 return TRUE; 5313} 5314 5315/* OP_CHECK_PREV matcher. */ 5316 5317static bfd_boolean 5318match_check_prev_operand (struct mips_arg_info *arg, 5319 const struct mips_operand *operand_base) 5320{ 5321 const struct mips_check_prev_operand *operand; 5322 unsigned int regno; 5323 5324 operand = (const struct mips_check_prev_operand *) operand_base; 5325 5326 if (!match_reg (arg, OP_REG_GP, ®no)) 5327 return FALSE; 5328 5329 if (!operand->zero_ok && regno == 0) 5330 return FALSE; 5331 5332 if ((operand->less_than_ok && regno < arg->last_regno) 5333 || (operand->greater_than_ok && regno > arg->last_regno) 5334 || (operand->equal_ok && regno == arg->last_regno)) 5335 { 5336 arg->last_regno = regno; 5337 insn_insert_operand (arg->insn, operand_base, regno); 5338 return TRUE; 5339 } 5340 5341 return FALSE; 5342} 5343 5344/* OP_SAME_RS_RT matcher. */ 5345 5346static bfd_boolean 5347match_same_rs_rt_operand (struct mips_arg_info *arg, 5348 const struct mips_operand *operand) 5349{ 5350 unsigned int regno; 5351 5352 if (!match_reg (arg, OP_REG_GP, ®no)) 5353 return FALSE; 5354 5355 if (regno == 0) 5356 { 5357 set_insn_error (arg->argnum, _("the source register must not be $0")); 5358 return FALSE; 5359 } 5360 5361 arg->last_regno = regno; 5362 5363 insn_insert_operand (arg->insn, operand, regno | (regno << 5)); 5364 return TRUE; 5365} 5366 5367/* OP_LWM_SWM_LIST matcher. */ 5368 5369static bfd_boolean 5370match_lwm_swm_list_operand (struct mips_arg_info *arg, 5371 const struct mips_operand *operand) 5372{ 5373 unsigned int reglist, sregs, ra, regno1, regno2; 5374 struct mips_arg_info reset; 5375 5376 reglist = 0; 5377 if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) 5378 return FALSE; 5379 do 5380 { 5381 if (regno2 == FP && regno1 >= S0 && regno1 <= S7) 5382 { 5383 reglist |= 1 << FP; 5384 regno2 = S7; 5385 } 5386 reglist |= ((1U << regno2 << 1) - 1) & -(1U << regno1); 5387 reset = *arg; 5388 } 5389 while (match_char (arg, ',') 5390 && match_reg_range (arg, OP_REG_GP, ®no1, ®no2)); 5391 *arg = reset; 5392 5393 if (operand->size == 2) 5394 { 5395 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.: 5396 5397 s0, ra 5398 s0, s1, ra, s2, s3 5399 s0-s2, ra 5400 5401 and any permutations of these. */ 5402 if ((reglist & 0xfff1ffff) != 0x80010000) 5403 return FALSE; 5404 5405 sregs = (reglist >> 17) & 7; 5406 ra = 0; 5407 } 5408 else 5409 { 5410 /* The list must include at least one of ra and s0-sN, 5411 for 0 <= N <= 8. (Note that there is a gap between s7 and s8, 5412 which are $23 and $30 respectively.) E.g.: 5413 5414 ra 5415 s0 5416 ra, s0, s1, s2 5417 s0-s8 5418 s0-s5, ra 5419 5420 and any permutations of these. */ 5421 if ((reglist & 0x3f00ffff) != 0) 5422 return FALSE; 5423 5424 ra = (reglist >> 27) & 0x10; 5425 sregs = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff); 5426 } 5427 sregs += 1; 5428 if ((sregs & -sregs) != sregs) 5429 return FALSE; 5430 5431 insn_insert_operand (arg->insn, operand, (ffs (sregs) - 1) | ra); 5432 return TRUE; 5433} 5434 5435/* OP_ENTRY_EXIT_LIST matcher. */ 5436 5437static unsigned int 5438match_entry_exit_operand (struct mips_arg_info *arg, 5439 const struct mips_operand *operand) 5440{ 5441 unsigned int mask; 5442 bfd_boolean is_exit; 5443 5444 /* The format is the same for both ENTRY and EXIT, but the constraints 5445 are different. */ 5446 is_exit = strcmp (arg->insn->insn_mo->name, "exit") == 0; 5447 mask = (is_exit ? 7 << 3 : 0); 5448 do 5449 { 5450 unsigned int regno1, regno2; 5451 bfd_boolean is_freg; 5452 5453 if (match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) 5454 is_freg = FALSE; 5455 else if (match_reg_range (arg, OP_REG_FP, ®no1, ®no2)) 5456 is_freg = TRUE; 5457 else 5458 return FALSE; 5459 5460 if (is_exit && is_freg && regno1 == 0 && regno2 < 2) 5461 { 5462 mask &= ~(7 << 3); 5463 mask |= (5 + regno2) << 3; 5464 } 5465 else if (!is_exit && regno1 == 4 && regno2 >= 4 && regno2 <= 7) 5466 mask |= (regno2 - 3) << 3; 5467 else if (regno1 == 16 && regno2 >= 16 && regno2 <= 17) 5468 mask |= (regno2 - 15) << 1; 5469 else if (regno1 == RA && regno2 == RA) 5470 mask |= 1; 5471 else 5472 return FALSE; 5473 } 5474 while (match_char (arg, ',')); 5475 5476 insn_insert_operand (arg->insn, operand, mask); 5477 return TRUE; 5478} 5479 5480/* OP_SAVE_RESTORE_LIST matcher. */ 5481 5482static bfd_boolean 5483match_save_restore_list_operand (struct mips_arg_info *arg) 5484{ 5485 unsigned int opcode, args, statics, sregs; 5486 unsigned int num_frame_sizes, num_args, num_statics, num_sregs; 5487 offsetT frame_size; 5488 5489 opcode = arg->insn->insn_opcode; 5490 frame_size = 0; 5491 num_frame_sizes = 0; 5492 args = 0; 5493 statics = 0; 5494 sregs = 0; 5495 do 5496 { 5497 unsigned int regno1, regno2; 5498 5499 if (arg->token->type == OT_INTEGER) 5500 { 5501 /* Handle the frame size. */ 5502 if (!match_const_int (arg, &frame_size)) 5503 return FALSE; 5504 num_frame_sizes += 1; 5505 } 5506 else 5507 { 5508 if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) 5509 return FALSE; 5510 5511 while (regno1 <= regno2) 5512 { 5513 if (regno1 >= 4 && regno1 <= 7) 5514 { 5515 if (num_frame_sizes == 0) 5516 /* args $a0-$a3 */ 5517 args |= 1 << (regno1 - 4); 5518 else 5519 /* statics $a0-$a3 */ 5520 statics |= 1 << (regno1 - 4); 5521 } 5522 else if (regno1 >= 16 && regno1 <= 23) 5523 /* $s0-$s7 */ 5524 sregs |= 1 << (regno1 - 16); 5525 else if (regno1 == 30) 5526 /* $s8 */ 5527 sregs |= 1 << 8; 5528 else if (regno1 == 31) 5529 /* Add $ra to insn. */ 5530 opcode |= 0x40; 5531 else 5532 return FALSE; 5533 regno1 += 1; 5534 if (regno1 == 24) 5535 regno1 = 30; 5536 } 5537 } 5538 } 5539 while (match_char (arg, ',')); 5540 5541 /* Encode args/statics combination. */ 5542 if (args & statics) 5543 return FALSE; 5544 else if (args == 0xf) 5545 /* All $a0-$a3 are args. */ 5546 opcode |= MIPS16_ALL_ARGS << 16; 5547 else if (statics == 0xf) 5548 /* All $a0-$a3 are statics. */ 5549 opcode |= MIPS16_ALL_STATICS << 16; 5550 else 5551 { 5552 /* Count arg registers. */ 5553 num_args = 0; 5554 while (args & 0x1) 5555 { 5556 args >>= 1; 5557 num_args += 1; 5558 } 5559 if (args != 0) 5560 return FALSE; 5561 5562 /* Count static registers. */ 5563 num_statics = 0; 5564 while (statics & 0x8) 5565 { 5566 statics = (statics << 1) & 0xf; 5567 num_statics += 1; 5568 } 5569 if (statics != 0) 5570 return FALSE; 5571 5572 /* Encode args/statics. */ 5573 opcode |= ((num_args << 2) | num_statics) << 16; 5574 } 5575 5576 /* Encode $s0/$s1. */ 5577 if (sregs & (1 << 0)) /* $s0 */ 5578 opcode |= 0x20; 5579 if (sregs & (1 << 1)) /* $s1 */ 5580 opcode |= 0x10; 5581 sregs >>= 2; 5582 5583 /* Encode $s2-$s8. */ 5584 num_sregs = 0; 5585 while (sregs & 1) 5586 { 5587 sregs >>= 1; 5588 num_sregs += 1; 5589 } 5590 if (sregs != 0) 5591 return FALSE; 5592 opcode |= num_sregs << 24; 5593 5594 /* Encode frame size. */ 5595 if (num_frame_sizes == 0) 5596 { 5597 set_insn_error (arg->argnum, _("missing frame size")); 5598 return FALSE; 5599 } 5600 if (num_frame_sizes > 1) 5601 { 5602 set_insn_error (arg->argnum, _("frame size specified twice")); 5603 return FALSE; 5604 } 5605 if ((frame_size & 7) != 0 || frame_size < 0 || frame_size > 0xff * 8) 5606 { 5607 set_insn_error (arg->argnum, _("invalid frame size")); 5608 return FALSE; 5609 } 5610 if (frame_size != 128 || (opcode >> 16) != 0) 5611 { 5612 frame_size /= 8; 5613 opcode |= (((frame_size & 0xf0) << 16) 5614 | (frame_size & 0x0f)); 5615 } 5616 5617 /* Finally build the instruction. */ 5618 if ((opcode >> 16) != 0 || frame_size == 0) 5619 opcode |= MIPS16_EXTEND; 5620 arg->insn->insn_opcode = opcode; 5621 return TRUE; 5622} 5623 5624/* OP_MDMX_IMM_REG matcher. */ 5625 5626static bfd_boolean 5627match_mdmx_imm_reg_operand (struct mips_arg_info *arg, 5628 const struct mips_operand *operand) 5629{ 5630 unsigned int regno, uval; 5631 bfd_boolean is_qh; 5632 const struct mips_opcode *opcode; 5633 5634 /* The mips_opcode records whether this is an octobyte or quadhalf 5635 instruction. Start out with that bit in place. */ 5636 opcode = arg->insn->insn_mo; 5637 uval = mips_extract_operand (operand, opcode->match); 5638 is_qh = (uval != 0); 5639 5640 if (arg->token->type == OT_REG) 5641 { 5642 if ((opcode->membership & INSN_5400) 5643 && strcmp (opcode->name, "rzu.ob") == 0) 5644 { 5645 set_insn_error_i (arg->argnum, _("operand %d must be an immediate"), 5646 arg->argnum); 5647 return FALSE; 5648 } 5649 5650 if (!match_regno (arg, OP_REG_VEC, arg->token->u.regno, ®no)) 5651 return FALSE; 5652 ++arg->token; 5653 5654 /* Check whether this is a vector register or a broadcast of 5655 a single element. */ 5656 if (arg->token->type == OT_INTEGER_INDEX) 5657 { 5658 if (arg->token->u.index > (is_qh ? 3 : 7)) 5659 { 5660 set_insn_error (arg->argnum, _("invalid element selector")); 5661 return FALSE; 5662 } 5663 uval |= arg->token->u.index << (is_qh ? 2 : 1) << 5; 5664 ++arg->token; 5665 } 5666 else 5667 { 5668 /* A full vector. */ 5669 if ((opcode->membership & INSN_5400) 5670 && (strcmp (opcode->name, "sll.ob") == 0 5671 || strcmp (opcode->name, "srl.ob") == 0)) 5672 { 5673 set_insn_error_i (arg->argnum, _("operand %d must be scalar"), 5674 arg->argnum); 5675 return FALSE; 5676 } 5677 5678 if (is_qh) 5679 uval |= MDMX_FMTSEL_VEC_QH << 5; 5680 else 5681 uval |= MDMX_FMTSEL_VEC_OB << 5; 5682 } 5683 uval |= regno; 5684 } 5685 else 5686 { 5687 offsetT sval; 5688 5689 if (!match_const_int (arg, &sval)) 5690 return FALSE; 5691 if (sval < 0 || sval > 31) 5692 { 5693 match_out_of_range (arg); 5694 return FALSE; 5695 } 5696 uval |= (sval & 31); 5697 if (is_qh) 5698 uval |= MDMX_FMTSEL_IMM_QH << 5; 5699 else 5700 uval |= MDMX_FMTSEL_IMM_OB << 5; 5701 } 5702 insn_insert_operand (arg->insn, operand, uval); 5703 return TRUE; 5704} 5705 5706/* OP_IMM_INDEX matcher. */ 5707 5708static bfd_boolean 5709match_imm_index_operand (struct mips_arg_info *arg, 5710 const struct mips_operand *operand) 5711{ 5712 unsigned int max_val; 5713 5714 if (arg->token->type != OT_INTEGER_INDEX) 5715 return FALSE; 5716 5717 max_val = (1 << operand->size) - 1; 5718 if (arg->token->u.index > max_val) 5719 { 5720 match_out_of_range (arg); 5721 return FALSE; 5722 } 5723 insn_insert_operand (arg->insn, operand, arg->token->u.index); 5724 ++arg->token; 5725 return TRUE; 5726} 5727 5728/* OP_REG_INDEX matcher. */ 5729 5730static bfd_boolean 5731match_reg_index_operand (struct mips_arg_info *arg, 5732 const struct mips_operand *operand) 5733{ 5734 unsigned int regno; 5735 5736 if (arg->token->type != OT_REG_INDEX) 5737 return FALSE; 5738 5739 if (!match_regno (arg, OP_REG_GP, arg->token->u.regno, ®no)) 5740 return FALSE; 5741 5742 insn_insert_operand (arg->insn, operand, regno); 5743 ++arg->token; 5744 return TRUE; 5745} 5746 5747/* OP_PC matcher. */ 5748 5749static bfd_boolean 5750match_pc_operand (struct mips_arg_info *arg) 5751{ 5752 if (arg->token->type == OT_REG && (arg->token->u.regno & RTYPE_PC)) 5753 { 5754 ++arg->token; 5755 return TRUE; 5756 } 5757 return FALSE; 5758} 5759 5760/* OP_NON_ZERO_REG matcher. */ 5761 5762static bfd_boolean 5763match_non_zero_reg_operand (struct mips_arg_info *arg, 5764 const struct mips_operand *operand) 5765{ 5766 unsigned int regno; 5767 5768 if (!match_reg (arg, OP_REG_GP, ®no)) 5769 return FALSE; 5770 5771 if (regno == 0) 5772 return FALSE; 5773 5774 arg->last_regno = regno; 5775 insn_insert_operand (arg->insn, operand, regno); 5776 return TRUE; 5777} 5778 5779/* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the 5780 register that we need to match. */ 5781 5782static bfd_boolean 5783match_tied_reg_operand (struct mips_arg_info *arg, unsigned int other_regno) 5784{ 5785 unsigned int regno; 5786 5787 return match_reg (arg, OP_REG_GP, ®no) && regno == other_regno; 5788} 5789 5790/* Read a floating-point constant from S for LI.S or LI.D. LENGTH is 5791 the length of the value in bytes (4 for float, 8 for double) and 5792 USING_GPRS says whether the destination is a GPR rather than an FPR. 5793 5794 Return the constant in IMM and OFFSET as follows: 5795 5796 - If the constant should be loaded via memory, set IMM to O_absent and 5797 OFFSET to the memory address. 5798 5799 - Otherwise, if the constant should be loaded into two 32-bit registers, 5800 set IMM to the O_constant to load into the high register and OFFSET 5801 to the corresponding value for the low register. 5802 5803 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent. 5804 5805 These constants only appear as the last operand in an instruction, 5806 and every instruction that accepts them in any variant accepts them 5807 in all variants. This means we don't have to worry about backing out 5808 any changes if the instruction does not match. We just match 5809 unconditionally and report an error if the constant is invalid. */ 5810 5811static bfd_boolean 5812match_float_constant (struct mips_arg_info *arg, expressionS *imm, 5813 expressionS *offset, int length, bfd_boolean using_gprs) 5814{ 5815 char *p; 5816 segT seg, new_seg; 5817 subsegT subseg; 5818 const char *newname; 5819 unsigned char *data; 5820 5821 /* Where the constant is placed is based on how the MIPS assembler 5822 does things: 5823 5824 length == 4 && using_gprs -- immediate value only 5825 length == 8 && using_gprs -- .rdata or immediate value 5826 length == 4 && !using_gprs -- .lit4 or immediate value 5827 length == 8 && !using_gprs -- .lit8 or immediate value 5828 5829 The .lit4 and .lit8 sections are only used if permitted by the 5830 -G argument. */ 5831 if (arg->token->type != OT_FLOAT) 5832 { 5833 set_insn_error (arg->argnum, _("floating-point expression required")); 5834 return FALSE; 5835 } 5836 5837 gas_assert (arg->token->u.flt.length == length); 5838 data = arg->token->u.flt.data; 5839 ++arg->token; 5840 5841 /* Handle 32-bit constants for which an immediate value is best. */ 5842 if (length == 4 5843 && (using_gprs 5844 || g_switch_value < 4 5845 || (data[0] == 0 && data[1] == 0) 5846 || (data[2] == 0 && data[3] == 0))) 5847 { 5848 imm->X_op = O_constant; 5849 if (!target_big_endian) 5850 imm->X_add_number = bfd_getl32 (data); 5851 else 5852 imm->X_add_number = bfd_getb32 (data); 5853 offset->X_op = O_absent; 5854 return TRUE; 5855 } 5856 5857 /* Handle 64-bit constants for which an immediate value is best. */ 5858 if (length == 8 5859 && !mips_disable_float_construction 5860 /* Constants can only be constructed in GPRs and copied to FPRs if the 5861 GPRs are at least as wide as the FPRs or MTHC1 is available. 5862 Unlike most tests for 32-bit floating-point registers this check 5863 specifically looks for GPR_SIZE == 32 as the FPXX ABI does not 5864 permit 64-bit moves without MXHC1. 5865 Force the constant into memory otherwise. */ 5866 && (using_gprs 5867 || GPR_SIZE == 64 5868 || ISA_HAS_MXHC1 (mips_opts.isa) 5869 || FPR_SIZE == 32) 5870 && ((data[0] == 0 && data[1] == 0) 5871 || (data[2] == 0 && data[3] == 0)) 5872 && ((data[4] == 0 && data[5] == 0) 5873 || (data[6] == 0 && data[7] == 0))) 5874 { 5875 /* The value is simple enough to load with a couple of instructions. 5876 If using 32-bit registers, set IMM to the high order 32 bits and 5877 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire 5878 64 bit constant. */ 5879 if (GPR_SIZE == 32 || (!using_gprs && FPR_SIZE != 64)) 5880 { 5881 imm->X_op = O_constant; 5882 offset->X_op = O_constant; 5883 if (!target_big_endian) 5884 { 5885 imm->X_add_number = bfd_getl32 (data + 4); 5886 offset->X_add_number = bfd_getl32 (data); 5887 } 5888 else 5889 { 5890 imm->X_add_number = bfd_getb32 (data); 5891 offset->X_add_number = bfd_getb32 (data + 4); 5892 } 5893 if (offset->X_add_number == 0) 5894 offset->X_op = O_absent; 5895 } 5896 else 5897 { 5898 imm->X_op = O_constant; 5899 if (!target_big_endian) 5900 imm->X_add_number = bfd_getl64 (data); 5901 else 5902 imm->X_add_number = bfd_getb64 (data); 5903 offset->X_op = O_absent; 5904 } 5905 return TRUE; 5906 } 5907 5908 /* Switch to the right section. */ 5909 seg = now_seg; 5910 subseg = now_subseg; 5911 if (length == 4) 5912 { 5913 gas_assert (!using_gprs && g_switch_value >= 4); 5914 newname = ".lit4"; 5915 } 5916 else 5917 { 5918 if (using_gprs || g_switch_value < 8) 5919 newname = RDATA_SECTION_NAME; 5920 else 5921 newname = ".lit8"; 5922 } 5923 5924 new_seg = subseg_new (newname, (subsegT) 0); 5925 bfd_set_section_flags (stdoutput, new_seg, 5926 SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_DATA); 5927 frag_align (length == 4 ? 2 : 3, 0, 0); 5928 if (strncmp (TARGET_OS, "elf", 3) != 0) 5929 record_alignment (new_seg, 4); 5930 else 5931 record_alignment (new_seg, length == 4 ? 2 : 3); 5932 if (seg == now_seg) 5933 as_bad (_("cannot use `%s' in this section"), arg->insn->insn_mo->name); 5934 5935 /* Set the argument to the current address in the section. */ 5936 imm->X_op = O_absent; 5937 offset->X_op = O_symbol; 5938 offset->X_add_symbol = symbol_temp_new_now (); 5939 offset->X_add_number = 0; 5940 5941 /* Put the floating point number into the section. */ 5942 p = frag_more (length); 5943 memcpy (p, data, length); 5944 5945 /* Switch back to the original section. */ 5946 subseg_set (seg, subseg); 5947 return TRUE; 5948} 5949 5950/* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between 5951 them. */ 5952 5953static bfd_boolean 5954match_vu0_suffix_operand (struct mips_arg_info *arg, 5955 const struct mips_operand *operand, 5956 bfd_boolean match_p) 5957{ 5958 unsigned int uval; 5959 5960 /* The operand can be an XYZW mask or a single 2-bit channel index 5961 (with X being 0). */ 5962 gas_assert (operand->size == 2 || operand->size == 4); 5963 5964 /* The suffix can be omitted when it is already part of the opcode. */ 5965 if (arg->token->type != OT_CHANNELS) 5966 return match_p; 5967 5968 uval = arg->token->u.channels; 5969 if (operand->size == 2) 5970 { 5971 /* Check that a single bit is set and convert it into a 2-bit index. */ 5972 if ((uval & -uval) != uval) 5973 return FALSE; 5974 uval = 4 - ffs (uval); 5975 } 5976 5977 if (match_p && insn_extract_operand (arg->insn, operand) != uval) 5978 return FALSE; 5979 5980 ++arg->token; 5981 if (!match_p) 5982 insn_insert_operand (arg->insn, operand, uval); 5983 return TRUE; 5984} 5985 5986/* S is the text seen for ARG. Match it against OPERAND. Return the end 5987 of the argument text if the match is successful, otherwise return null. */ 5988 5989static bfd_boolean 5990match_operand (struct mips_arg_info *arg, 5991 const struct mips_operand *operand) 5992{ 5993 switch (operand->type) 5994 { 5995 case OP_INT: 5996 return match_int_operand (arg, operand); 5997 5998 case OP_MAPPED_INT: 5999 return match_mapped_int_operand (arg, operand); 6000 6001 case OP_MSB: 6002 return match_msb_operand (arg, operand); 6003 6004 case OP_REG: 6005 case OP_OPTIONAL_REG: 6006 return match_reg_operand (arg, operand); 6007 6008 case OP_REG_PAIR: 6009 return match_reg_pair_operand (arg, operand); 6010 6011 case OP_PCREL: 6012 return match_pcrel_operand (arg); 6013 6014 case OP_PERF_REG: 6015 return match_perf_reg_operand (arg, operand); 6016 6017 case OP_ADDIUSP_INT: 6018 return match_addiusp_operand (arg, operand); 6019 6020 case OP_CLO_CLZ_DEST: 6021 return match_clo_clz_dest_operand (arg, operand); 6022 6023 case OP_LWM_SWM_LIST: 6024 return match_lwm_swm_list_operand (arg, operand); 6025 6026 case OP_ENTRY_EXIT_LIST: 6027 return match_entry_exit_operand (arg, operand); 6028 6029 case OP_SAVE_RESTORE_LIST: 6030 return match_save_restore_list_operand (arg); 6031 6032 case OP_MDMX_IMM_REG: 6033 return match_mdmx_imm_reg_operand (arg, operand); 6034 6035 case OP_REPEAT_DEST_REG: 6036 return match_tied_reg_operand (arg, arg->dest_regno); 6037 6038 case OP_REPEAT_PREV_REG: 6039 return match_tied_reg_operand (arg, arg->last_regno); 6040 6041 case OP_PC: 6042 return match_pc_operand (arg); 6043 6044 case OP_VU0_SUFFIX: 6045 return match_vu0_suffix_operand (arg, operand, FALSE); 6046 6047 case OP_VU0_MATCH_SUFFIX: 6048 return match_vu0_suffix_operand (arg, operand, TRUE); 6049 6050 case OP_IMM_INDEX: 6051 return match_imm_index_operand (arg, operand); 6052 6053 case OP_REG_INDEX: 6054 return match_reg_index_operand (arg, operand); 6055 6056 case OP_SAME_RS_RT: 6057 return match_same_rs_rt_operand (arg, operand); 6058 6059 case OP_CHECK_PREV: 6060 return match_check_prev_operand (arg, operand); 6061 6062 case OP_NON_ZERO_REG: 6063 return match_non_zero_reg_operand (arg, operand); 6064 } 6065 abort (); 6066} 6067 6068/* ARG is the state after successfully matching an instruction. 6069 Issue any queued-up warnings. */ 6070 6071static void 6072check_completed_insn (struct mips_arg_info *arg) 6073{ 6074 if (arg->seen_at) 6075 { 6076 if (AT == ATREG) 6077 as_warn (_("used $at without \".set noat\"")); 6078 else 6079 as_warn (_("used $%u with \".set at=$%u\""), AT, AT); 6080 } 6081} 6082 6083/* Return true if modifying general-purpose register REG needs a delay. */ 6084 6085static bfd_boolean 6086reg_needs_delay (unsigned int reg) 6087{ 6088 unsigned long prev_pinfo; 6089 6090 prev_pinfo = history[0].insn_mo->pinfo; 6091 if (!mips_opts.noreorder 6092 && (((prev_pinfo & INSN_LOAD_MEMORY) && !gpr_interlocks) 6093 || ((prev_pinfo & INSN_LOAD_COPROC) && !cop_interlocks)) 6094 && (gpr_write_mask (&history[0]) & (1 << reg))) 6095 return TRUE; 6096 6097 return FALSE; 6098} 6099 6100/* Classify an instruction according to the FIX_VR4120_* enumeration. 6101 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected 6102 by VR4120 errata. */ 6103 6104static unsigned int 6105classify_vr4120_insn (const char *name) 6106{ 6107 if (strncmp (name, "macc", 4) == 0) 6108 return FIX_VR4120_MACC; 6109 if (strncmp (name, "dmacc", 5) == 0) 6110 return FIX_VR4120_DMACC; 6111 if (strncmp (name, "mult", 4) == 0) 6112 return FIX_VR4120_MULT; 6113 if (strncmp (name, "dmult", 5) == 0) 6114 return FIX_VR4120_DMULT; 6115 if (strstr (name, "div")) 6116 return FIX_VR4120_DIV; 6117 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) 6118 return FIX_VR4120_MTHILO; 6119 return NUM_FIX_VR4120_CLASSES; 6120} 6121 6122#define INSN_ERET 0x42000018 6123#define INSN_DERET 0x4200001f 6124#define INSN_DMULT 0x1c 6125#define INSN_DMULTU 0x1d 6126 6127/* Return the number of instructions that must separate INSN1 and INSN2, 6128 where INSN1 is the earlier instruction. Return the worst-case value 6129 for any INSN2 if INSN2 is null. */ 6130 6131static unsigned int 6132insns_between (const struct mips_cl_insn *insn1, 6133 const struct mips_cl_insn *insn2) 6134{ 6135 unsigned long pinfo1, pinfo2; 6136 unsigned int mask; 6137 6138 /* If INFO2 is null, pessimistically assume that all flags are set for 6139 the second instruction. */ 6140 pinfo1 = insn1->insn_mo->pinfo; 6141 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; 6142 6143 /* For most targets, write-after-read dependencies on the HI and LO 6144 registers must be separated by at least two instructions. */ 6145 if (!hilo_interlocks) 6146 { 6147 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) 6148 return 2; 6149 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) 6150 return 2; 6151 } 6152 6153 /* If we're working around r7000 errata, there must be two instructions 6154 between an mfhi or mflo and any instruction that uses the result. */ 6155 if (mips_7000_hilo_fix 6156 && !mips_opts.micromips 6157 && MF_HILO_INSN (pinfo1) 6158 && (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1)))) 6159 return 2; 6160 6161 /* If we're working around 24K errata, one instruction is required 6162 if an ERET or DERET is followed by a branch instruction. */ 6163 if (mips_fix_24k && !mips_opts.micromips) 6164 { 6165 if (insn1->insn_opcode == INSN_ERET 6166 || insn1->insn_opcode == INSN_DERET) 6167 { 6168 if (insn2 == NULL 6169 || insn2->insn_opcode == INSN_ERET 6170 || insn2->insn_opcode == INSN_DERET 6171 || delayed_branch_p (insn2)) 6172 return 1; 6173 } 6174 } 6175 6176 /* If we're working around PMC RM7000 errata, there must be three 6177 nops between a dmult and a load instruction. */ 6178 if (mips_fix_rm7000 && !mips_opts.micromips) 6179 { 6180 if ((insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULT 6181 || (insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULTU) 6182 { 6183 if (pinfo2 & INSN_LOAD_MEMORY) 6184 return 3; 6185 } 6186 } 6187 6188 /* If working around VR4120 errata, check for combinations that need 6189 a single intervening instruction. */ 6190 if (mips_fix_vr4120 && !mips_opts.micromips) 6191 { 6192 unsigned int class1, class2; 6193 6194 class1 = classify_vr4120_insn (insn1->insn_mo->name); 6195 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) 6196 { 6197 if (insn2 == NULL) 6198 return 1; 6199 class2 = classify_vr4120_insn (insn2->insn_mo->name); 6200 if (vr4120_conflicts[class1] & (1 << class2)) 6201 return 1; 6202 } 6203 } 6204 6205 if (!HAVE_CODE_COMPRESSION) 6206 { 6207 /* Check for GPR or coprocessor load delays. All such delays 6208 are on the RT register. */ 6209 /* Itbl support may require additional care here. */ 6210 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY)) 6211 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC))) 6212 { 6213 if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1))) 6214 return 1; 6215 } 6216 6217 /* Check for generic coprocessor hazards. 6218 6219 This case is not handled very well. There is no special 6220 knowledge of CP0 handling, and the coprocessors other than 6221 the floating point unit are not distinguished at all. */ 6222 /* Itbl support may require additional care here. FIXME! 6223 Need to modify this to include knowledge about 6224 user specified delays! */ 6225 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE)) 6226 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) 6227 { 6228 /* Handle cases where INSN1 writes to a known general coprocessor 6229 register. There must be a one instruction delay before INSN2 6230 if INSN2 reads that register, otherwise no delay is needed. */ 6231 mask = fpr_write_mask (insn1); 6232 if (mask != 0) 6233 { 6234 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0) 6235 return 1; 6236 } 6237 else 6238 { 6239 /* Read-after-write dependencies on the control registers 6240 require a two-instruction gap. */ 6241 if ((pinfo1 & INSN_WRITE_COND_CODE) 6242 && (pinfo2 & INSN_READ_COND_CODE)) 6243 return 2; 6244 6245 /* We don't know exactly what INSN1 does. If INSN2 is 6246 also a coprocessor instruction, assume there must be 6247 a one instruction gap. */ 6248 if (pinfo2 & INSN_COP) 6249 return 1; 6250 } 6251 } 6252 6253 /* Check for read-after-write dependencies on the coprocessor 6254 control registers in cases where INSN1 does not need a general 6255 coprocessor delay. This means that INSN1 is a floating point 6256 comparison instruction. */ 6257 /* Itbl support may require additional care here. */ 6258 else if (!cop_interlocks 6259 && (pinfo1 & INSN_WRITE_COND_CODE) 6260 && (pinfo2 & INSN_READ_COND_CODE)) 6261 return 1; 6262 } 6263 6264 /* Forbidden slots can not contain Control Transfer Instructions (CTIs) 6265 CTIs include all branches and jumps, nal, eret, eretnc, deret, wait 6266 and pause. */ 6267 if ((insn1->insn_mo->pinfo2 & INSN2_FORBIDDEN_SLOT) 6268 && ((pinfo2 & INSN_NO_DELAY_SLOT) 6269 || (insn2 && delayed_branch_p (insn2)))) 6270 return 1; 6271 6272 return 0; 6273} 6274 6275/* Return the number of nops that would be needed to work around the 6276 VR4130 mflo/mfhi errata if instruction INSN immediately followed 6277 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards 6278 that are contained within the first IGNORE instructions of HIST. */ 6279 6280static int 6281nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist, 6282 const struct mips_cl_insn *insn) 6283{ 6284 int i, j; 6285 unsigned int mask; 6286 6287 /* Check if the instruction writes to HI or LO. MTHI and MTLO 6288 are not affected by the errata. */ 6289 if (insn != 0 6290 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 6291 || strcmp (insn->insn_mo->name, "mtlo") == 0 6292 || strcmp (insn->insn_mo->name, "mthi") == 0)) 6293 return 0; 6294 6295 /* Search for the first MFLO or MFHI. */ 6296 for (i = 0; i < MAX_VR4130_NOPS; i++) 6297 if (MF_HILO_INSN (hist[i].insn_mo->pinfo)) 6298 { 6299 /* Extract the destination register. */ 6300 mask = gpr_write_mask (&hist[i]); 6301 6302 /* No nops are needed if INSN reads that register. */ 6303 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0) 6304 return 0; 6305 6306 /* ...or if any of the intervening instructions do. */ 6307 for (j = 0; j < i; j++) 6308 if (gpr_read_mask (&hist[j]) & mask) 6309 return 0; 6310 6311 if (i >= ignore) 6312 return MAX_VR4130_NOPS - i; 6313 } 6314 return 0; 6315} 6316 6317#define BASE_REG_EQ(INSN1, INSN2) \ 6318 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \ 6319 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS)) 6320 6321/* Return the minimum alignment for this store instruction. */ 6322 6323static int 6324fix_24k_align_to (const struct mips_opcode *mo) 6325{ 6326 if (strcmp (mo->name, "sh") == 0) 6327 return 2; 6328 6329 if (strcmp (mo->name, "swc1") == 0 6330 || strcmp (mo->name, "swc2") == 0 6331 || strcmp (mo->name, "sw") == 0 6332 || strcmp (mo->name, "sc") == 0 6333 || strcmp (mo->name, "s.s") == 0) 6334 return 4; 6335 6336 if (strcmp (mo->name, "sdc1") == 0 6337 || strcmp (mo->name, "sdc2") == 0 6338 || strcmp (mo->name, "s.d") == 0) 6339 return 8; 6340 6341 /* sb, swl, swr */ 6342 return 1; 6343} 6344 6345struct fix_24k_store_info 6346 { 6347 /* Immediate offset, if any, for this store instruction. */ 6348 short off; 6349 /* Alignment required by this store instruction. */ 6350 int align_to; 6351 /* True for register offsets. */ 6352 int register_offset; 6353 }; 6354 6355/* Comparison function used by qsort. */ 6356 6357static int 6358fix_24k_sort (const void *a, const void *b) 6359{ 6360 const struct fix_24k_store_info *pos1 = a; 6361 const struct fix_24k_store_info *pos2 = b; 6362 6363 return (pos1->off - pos2->off); 6364} 6365 6366/* INSN is a store instruction. Try to record the store information 6367 in STINFO. Return false if the information isn't known. */ 6368 6369static bfd_boolean 6370fix_24k_record_store_info (struct fix_24k_store_info *stinfo, 6371 const struct mips_cl_insn *insn) 6372{ 6373 /* The instruction must have a known offset. */ 6374 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o(")) 6375 return FALSE; 6376 6377 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE; 6378 stinfo->align_to = fix_24k_align_to (insn->insn_mo); 6379 return TRUE; 6380} 6381 6382/* Return the number of nops that would be needed to work around the 24k 6383 "lost data on stores during refill" errata if instruction INSN 6384 immediately followed the 2 instructions described by HIST. 6385 Ignore hazards that are contained within the first IGNORE 6386 instructions of HIST. 6387 6388 Problem: The FSB (fetch store buffer) acts as an intermediate buffer 6389 for the data cache refills and store data. The following describes 6390 the scenario where the store data could be lost. 6391 6392 * A data cache miss, due to either a load or a store, causing fill 6393 data to be supplied by the memory subsystem 6394 * The first three doublewords of fill data are returned and written 6395 into the cache 6396 * A sequence of four stores occurs in consecutive cycles around the 6397 final doubleword of the fill: 6398 * Store A 6399 * Store B 6400 * Store C 6401 * Zero, One or more instructions 6402 * Store D 6403 6404 The four stores A-D must be to different doublewords of the line that 6405 is being filled. The fourth instruction in the sequence above permits 6406 the fill of the final doubleword to be transferred from the FSB into 6407 the cache. In the sequence above, the stores may be either integer 6408 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2, 6409 swxc1, sdxc1, suxc1) stores, as long as the four stores are to 6410 different doublewords on the line. If the floating point unit is 6411 running in 1:2 mode, it is not possible to create the sequence above 6412 using only floating point store instructions. 6413 6414 In this case, the cache line being filled is incorrectly marked 6415 invalid, thereby losing the data from any store to the line that 6416 occurs between the original miss and the completion of the five 6417 cycle sequence shown above. 6418 6419 The workarounds are: 6420 6421 * Run the data cache in write-through mode. 6422 * Insert a non-store instruction between 6423 Store A and Store B or Store B and Store C. */ 6424 6425static int 6426nops_for_24k (int ignore, const struct mips_cl_insn *hist, 6427 const struct mips_cl_insn *insn) 6428{ 6429 struct fix_24k_store_info pos[3]; 6430 int align, i, base_offset; 6431 6432 if (ignore >= 2) 6433 return 0; 6434 6435 /* If the previous instruction wasn't a store, there's nothing to 6436 worry about. */ 6437 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) 6438 return 0; 6439 6440 /* If the instructions after the previous one are unknown, we have 6441 to assume the worst. */ 6442 if (!insn) 6443 return 1; 6444 6445 /* Check whether we are dealing with three consecutive stores. */ 6446 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0 6447 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) 6448 return 0; 6449 6450 /* If we don't know the relationship between the store addresses, 6451 assume the worst. */ 6452 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode) 6453 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode)) 6454 return 1; 6455 6456 if (!fix_24k_record_store_info (&pos[0], insn) 6457 || !fix_24k_record_store_info (&pos[1], &hist[0]) 6458 || !fix_24k_record_store_info (&pos[2], &hist[1])) 6459 return 1; 6460 6461 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort); 6462 6463 /* Pick a value of ALIGN and X such that all offsets are adjusted by 6464 X bytes and such that the base register + X is known to be aligned 6465 to align bytes. */ 6466 6467 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP) 6468 align = 8; 6469 else 6470 { 6471 align = pos[0].align_to; 6472 base_offset = pos[0].off; 6473 for (i = 1; i < 3; i++) 6474 if (align < pos[i].align_to) 6475 { 6476 align = pos[i].align_to; 6477 base_offset = pos[i].off; 6478 } 6479 for (i = 0; i < 3; i++) 6480 pos[i].off -= base_offset; 6481 } 6482 6483 pos[0].off &= ~align + 1; 6484 pos[1].off &= ~align + 1; 6485 pos[2].off &= ~align + 1; 6486 6487 /* If any two stores write to the same chunk, they also write to the 6488 same doubleword. The offsets are still sorted at this point. */ 6489 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off) 6490 return 0; 6491 6492 /* A range of at least 9 bytes is needed for the stores to be in 6493 non-overlapping doublewords. */ 6494 if (pos[2].off - pos[0].off <= 8) 6495 return 0; 6496 6497 if (pos[2].off - pos[1].off >= 24 6498 || pos[1].off - pos[0].off >= 24 6499 || pos[2].off - pos[0].off >= 32) 6500 return 0; 6501 6502 return 1; 6503} 6504 6505/* Return the number of nops that would be needed if instruction INSN 6506 immediately followed the MAX_NOPS instructions given by HIST, 6507 where HIST[0] is the most recent instruction. Ignore hazards 6508 between INSN and the first IGNORE instructions in HIST. 6509 6510 If INSN is null, return the worse-case number of nops for any 6511 instruction. */ 6512 6513static int 6514nops_for_insn (int ignore, const struct mips_cl_insn *hist, 6515 const struct mips_cl_insn *insn) 6516{ 6517 int i, nops, tmp_nops; 6518 6519 nops = 0; 6520 for (i = ignore; i < MAX_DELAY_NOPS; i++) 6521 { 6522 tmp_nops = insns_between (hist + i, insn) - i; 6523 if (tmp_nops > nops) 6524 nops = tmp_nops; 6525 } 6526 6527 if (mips_fix_vr4130 && !mips_opts.micromips) 6528 { 6529 tmp_nops = nops_for_vr4130 (ignore, hist, insn); 6530 if (tmp_nops > nops) 6531 nops = tmp_nops; 6532 } 6533 6534 if (mips_fix_24k && !mips_opts.micromips) 6535 { 6536 tmp_nops = nops_for_24k (ignore, hist, insn); 6537 if (tmp_nops > nops) 6538 nops = tmp_nops; 6539 } 6540 6541 return nops; 6542} 6543 6544/* The variable arguments provide NUM_INSNS extra instructions that 6545 might be added to HIST. Return the largest number of nops that 6546 would be needed after the extended sequence, ignoring hazards 6547 in the first IGNORE instructions. */ 6548 6549static int 6550nops_for_sequence (int num_insns, int ignore, 6551 const struct mips_cl_insn *hist, ...) 6552{ 6553 va_list args; 6554 struct mips_cl_insn buffer[MAX_NOPS]; 6555 struct mips_cl_insn *cursor; 6556 int nops; 6557 6558 va_start (args, hist); 6559 cursor = buffer + num_insns; 6560 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor)); 6561 while (cursor > buffer) 6562 *--cursor = *va_arg (args, const struct mips_cl_insn *); 6563 6564 nops = nops_for_insn (ignore, buffer, NULL); 6565 va_end (args); 6566 return nops; 6567} 6568 6569/* Like nops_for_insn, but if INSN is a branch, take into account the 6570 worst-case delay for the branch target. */ 6571 6572static int 6573nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist, 6574 const struct mips_cl_insn *insn) 6575{ 6576 int nops, tmp_nops; 6577 6578 nops = nops_for_insn (ignore, hist, insn); 6579 if (delayed_branch_p (insn)) 6580 { 6581 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0, 6582 hist, insn, get_delay_slot_nop (insn)); 6583 if (tmp_nops > nops) 6584 nops = tmp_nops; 6585 } 6586 else if (compact_branch_p (insn)) 6587 { 6588 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn); 6589 if (tmp_nops > nops) 6590 nops = tmp_nops; 6591 } 6592 return nops; 6593} 6594 6595/* Fix NOP issue: Replace nops by "or at,at,zero". */ 6596 6597static void 6598fix_loongson2f_nop (struct mips_cl_insn * ip) 6599{ 6600 gas_assert (!HAVE_CODE_COMPRESSION); 6601 if (strcmp (ip->insn_mo->name, "nop") == 0) 6602 ip->insn_opcode = LOONGSON2F_NOP_INSN; 6603} 6604 6605/* Fix Jump Issue: Eliminate instruction fetch from outside 256M region 6606 jr target pc &= 'hffff_ffff_cfff_ffff. */ 6607 6608static void 6609fix_loongson2f_jump (struct mips_cl_insn * ip) 6610{ 6611 gas_assert (!HAVE_CODE_COMPRESSION); 6612 if (strcmp (ip->insn_mo->name, "j") == 0 6613 || strcmp (ip->insn_mo->name, "jr") == 0 6614 || strcmp (ip->insn_mo->name, "jalr") == 0) 6615 { 6616 int sreg; 6617 expressionS ep; 6618 6619 if (! mips_opts.at) 6620 return; 6621 6622 sreg = EXTRACT_OPERAND (0, RS, *ip); 6623 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG) 6624 return; 6625 6626 ep.X_op = O_constant; 6627 ep.X_add_number = 0xcfff0000; 6628 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16); 6629 ep.X_add_number = 0xffff; 6630 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16); 6631 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG); 6632 } 6633} 6634 6635static void 6636fix_loongson2f (struct mips_cl_insn * ip) 6637{ 6638 if (mips_fix_loongson2f_nop) 6639 fix_loongson2f_nop (ip); 6640 6641 if (mips_fix_loongson2f_jump) 6642 fix_loongson2f_jump (ip); 6643} 6644 6645/* IP is a branch that has a delay slot, and we need to fill it 6646 automatically. Return true if we can do that by swapping IP 6647 with the previous instruction. 6648 ADDRESS_EXPR is an operand of the instruction to be used with 6649 RELOC_TYPE. */ 6650 6651static bfd_boolean 6652can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr, 6653 bfd_reloc_code_real_type *reloc_type) 6654{ 6655 unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2; 6656 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write; 6657 unsigned int fpr_read, prev_fpr_write; 6658 6659 /* -O2 and above is required for this optimization. */ 6660 if (mips_optimize < 2) 6661 return FALSE; 6662 6663 /* If we have seen .set volatile or .set nomove, don't optimize. */ 6664 if (mips_opts.nomove) 6665 return FALSE; 6666 6667 /* We can't swap if the previous instruction's position is fixed. */ 6668 if (history[0].fixed_p) 6669 return FALSE; 6670 6671 /* If the previous previous insn was in a .set noreorder, we can't 6672 swap. Actually, the MIPS assembler will swap in this situation. 6673 However, gcc configured -with-gnu-as will generate code like 6674 6675 .set noreorder 6676 lw $4,XXX 6677 .set reorder 6678 INSN 6679 bne $4,$0,foo 6680 6681 in which we can not swap the bne and INSN. If gcc is not configured 6682 -with-gnu-as, it does not output the .set pseudo-ops. */ 6683 if (history[1].noreorder_p) 6684 return FALSE; 6685 6686 /* If the previous instruction had a fixup in mips16 mode, we can not swap. 6687 This means that the previous instruction was a 4-byte one anyhow. */ 6688 if (mips_opts.mips16 && history[0].fixp[0]) 6689 return FALSE; 6690 6691 /* If the branch is itself the target of a branch, we can not swap. 6692 We cheat on this; all we check for is whether there is a label on 6693 this instruction. If there are any branches to anything other than 6694 a label, users must use .set noreorder. */ 6695 if (seg_info (now_seg)->label_list) 6696 return FALSE; 6697 6698 /* If the previous instruction is in a variant frag other than this 6699 branch's one, we cannot do the swap. This does not apply to 6700 MIPS16 code, which uses variant frags for different purposes. */ 6701 if (!mips_opts.mips16 6702 && history[0].frag 6703 && history[0].frag->fr_type == rs_machine_dependent) 6704 return FALSE; 6705 6706 /* We do not swap with instructions that cannot architecturally 6707 be placed in a branch delay slot, such as SYNC or ERET. We 6708 also refrain from swapping with a trap instruction, since it 6709 complicates trap handlers to have the trap instruction be in 6710 a delay slot. */ 6711 prev_pinfo = history[0].insn_mo->pinfo; 6712 if (prev_pinfo & INSN_NO_DELAY_SLOT) 6713 return FALSE; 6714 6715 /* Check for conflicts between the branch and the instructions 6716 before the candidate delay slot. */ 6717 if (nops_for_insn (0, history + 1, ip) > 0) 6718 return FALSE; 6719 6720 /* Check for conflicts between the swapped sequence and the 6721 target of the branch. */ 6722 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0) 6723 return FALSE; 6724 6725 /* If the branch reads a register that the previous 6726 instruction sets, we can not swap. */ 6727 gpr_read = gpr_read_mask (ip); 6728 prev_gpr_write = gpr_write_mask (&history[0]); 6729 if (gpr_read & prev_gpr_write) 6730 return FALSE; 6731 6732 fpr_read = fpr_read_mask (ip); 6733 prev_fpr_write = fpr_write_mask (&history[0]); 6734 if (fpr_read & prev_fpr_write) 6735 return FALSE; 6736 6737 /* If the branch writes a register that the previous 6738 instruction sets, we can not swap. */ 6739 gpr_write = gpr_write_mask (ip); 6740 if (gpr_write & prev_gpr_write) 6741 return FALSE; 6742 6743 /* If the branch writes a register that the previous 6744 instruction reads, we can not swap. */ 6745 prev_gpr_read = gpr_read_mask (&history[0]); 6746 if (gpr_write & prev_gpr_read) 6747 return FALSE; 6748 6749 /* If one instruction sets a condition code and the 6750 other one uses a condition code, we can not swap. */ 6751 pinfo = ip->insn_mo->pinfo; 6752 if ((pinfo & INSN_READ_COND_CODE) 6753 && (prev_pinfo & INSN_WRITE_COND_CODE)) 6754 return FALSE; 6755 if ((pinfo & INSN_WRITE_COND_CODE) 6756 && (prev_pinfo & INSN_READ_COND_CODE)) 6757 return FALSE; 6758 6759 /* If the previous instruction uses the PC, we can not swap. */ 6760 prev_pinfo2 = history[0].insn_mo->pinfo2; 6761 if (prev_pinfo2 & INSN2_READ_PC) 6762 return FALSE; 6763 6764 /* If the previous instruction has an incorrect size for a fixed 6765 branch delay slot in microMIPS mode, we cannot swap. */ 6766 pinfo2 = ip->insn_mo->pinfo2; 6767 if (mips_opts.micromips 6768 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT) 6769 && insn_length (history) != 2) 6770 return FALSE; 6771 if (mips_opts.micromips 6772 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT) 6773 && insn_length (history) != 4) 6774 return FALSE; 6775 6776 /* On R5900 short loops need to be fixed by inserting a nop in 6777 the branch delay slots. 6778 A short loop can be terminated too early. */ 6779 if (mips_opts.arch == CPU_R5900 6780 /* Check if instruction has a parameter, ignore "j $31". */ 6781 && (address_expr != NULL) 6782 /* Parameter must be 16 bit. */ 6783 && (*reloc_type == BFD_RELOC_16_PCREL_S2) 6784 /* Branch to same segment. */ 6785 && (S_GET_SEGMENT (address_expr->X_add_symbol) == now_seg) 6786 /* Branch to same code fragment. */ 6787 && (symbol_get_frag (address_expr->X_add_symbol) == frag_now) 6788 /* Can only calculate branch offset if value is known. */ 6789 && symbol_constant_p (address_expr->X_add_symbol) 6790 /* Check if branch is really conditional. */ 6791 && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */ 6792 || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */ 6793 || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */ 6794 { 6795 int distance; 6796 /* Check if loop is shorter than 6 instructions including 6797 branch and delay slot. */ 6798 distance = frag_now_fix () - S_GET_VALUE (address_expr->X_add_symbol); 6799 if (distance <= 20) 6800 { 6801 int i; 6802 int rv; 6803 6804 rv = FALSE; 6805 /* When the loop includes branches or jumps, 6806 it is not a short loop. */ 6807 for (i = 0; i < (distance / 4); i++) 6808 { 6809 if ((history[i].cleared_p) 6810 || delayed_branch_p (&history[i])) 6811 { 6812 rv = TRUE; 6813 break; 6814 } 6815 } 6816 if (rv == FALSE) 6817 { 6818 /* Insert nop after branch to fix short loop. */ 6819 return FALSE; 6820 } 6821 } 6822 } 6823 6824 return TRUE; 6825} 6826 6827/* Decide how we should add IP to the instruction stream. 6828 ADDRESS_EXPR is an operand of the instruction to be used with 6829 RELOC_TYPE. */ 6830 6831static enum append_method 6832get_append_method (struct mips_cl_insn *ip, expressionS *address_expr, 6833 bfd_reloc_code_real_type *reloc_type) 6834{ 6835 /* The relaxed version of a macro sequence must be inherently 6836 hazard-free. */ 6837 if (mips_relax.sequence == 2) 6838 return APPEND_ADD; 6839 6840 /* We must not dabble with instructions in a ".set noreorder" block. */ 6841 if (mips_opts.noreorder) 6842 return APPEND_ADD; 6843 6844 /* Otherwise, it's our responsibility to fill branch delay slots. */ 6845 if (delayed_branch_p (ip)) 6846 { 6847 if (!branch_likely_p (ip) 6848 && can_swap_branch_p (ip, address_expr, reloc_type)) 6849 return APPEND_SWAP; 6850 6851 if (mips_opts.mips16 6852 && ISA_SUPPORTS_MIPS16E 6853 && gpr_read_mask (ip) != 0) 6854 return APPEND_ADD_COMPACT; 6855 6856 if (mips_opts.micromips 6857 && ((ip->insn_opcode & 0xffe0) == 0x4580 6858 || (!forced_insn_length 6859 && ((ip->insn_opcode & 0xfc00) == 0xcc00 6860 || (ip->insn_opcode & 0xdc00) == 0x8c00)) 6861 || (ip->insn_opcode & 0xdfe00000) == 0x94000000 6862 || (ip->insn_opcode & 0xdc1f0000) == 0x94000000)) 6863 return APPEND_ADD_COMPACT; 6864 6865 return APPEND_ADD_WITH_NOP; 6866 } 6867 6868 return APPEND_ADD; 6869} 6870 6871/* IP is an instruction whose opcode we have just changed, END points 6872 to the end of the opcode table processed. Point IP->insn_mo to the 6873 new opcode's definition. */ 6874 6875static void 6876find_altered_opcode (struct mips_cl_insn *ip, const struct mips_opcode *end) 6877{ 6878 const struct mips_opcode *mo; 6879 6880 for (mo = ip->insn_mo; mo < end; mo++) 6881 if (mo->pinfo != INSN_MACRO 6882 && (ip->insn_opcode & mo->mask) == mo->match) 6883 { 6884 ip->insn_mo = mo; 6885 return; 6886 } 6887 abort (); 6888} 6889 6890/* IP is a MIPS16 instruction whose opcode we have just changed. 6891 Point IP->insn_mo to the new opcode's definition. */ 6892 6893static void 6894find_altered_mips16_opcode (struct mips_cl_insn *ip) 6895{ 6896 find_altered_opcode (ip, &mips16_opcodes[bfd_mips16_num_opcodes]); 6897} 6898 6899/* IP is a microMIPS instruction whose opcode we have just changed. 6900 Point IP->insn_mo to the new opcode's definition. */ 6901 6902static void 6903find_altered_micromips_opcode (struct mips_cl_insn *ip) 6904{ 6905 find_altered_opcode (ip, µmips_opcodes[bfd_micromips_num_opcodes]); 6906} 6907 6908/* For microMIPS macros, we need to generate a local number label 6909 as the target of branches. */ 6910#define MICROMIPS_LABEL_CHAR '\037' 6911static unsigned long micromips_target_label; 6912static char micromips_target_name[32]; 6913 6914static char * 6915micromips_label_name (void) 6916{ 6917 char *p = micromips_target_name; 6918 char symbol_name_temporary[24]; 6919 unsigned long l; 6920 int i; 6921 6922 if (*p) 6923 return p; 6924 6925 i = 0; 6926 l = micromips_target_label; 6927#ifdef LOCAL_LABEL_PREFIX 6928 *p++ = LOCAL_LABEL_PREFIX; 6929#endif 6930 *p++ = 'L'; 6931 *p++ = MICROMIPS_LABEL_CHAR; 6932 do 6933 { 6934 symbol_name_temporary[i++] = l % 10 + '0'; 6935 l /= 10; 6936 } 6937 while (l != 0); 6938 while (i > 0) 6939 *p++ = symbol_name_temporary[--i]; 6940 *p = '\0'; 6941 6942 return micromips_target_name; 6943} 6944 6945static void 6946micromips_label_expr (expressionS *label_expr) 6947{ 6948 label_expr->X_op = O_symbol; 6949 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ()); 6950 label_expr->X_add_number = 0; 6951} 6952 6953static void 6954micromips_label_inc (void) 6955{ 6956 micromips_target_label++; 6957 *micromips_target_name = '\0'; 6958} 6959 6960static void 6961micromips_add_label (void) 6962{ 6963 symbolS *s; 6964 6965 s = colon (micromips_label_name ()); 6966 micromips_label_inc (); 6967 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s))); 6968} 6969 6970/* If assembling microMIPS code, then return the microMIPS reloc 6971 corresponding to the requested one if any. Otherwise return 6972 the reloc unchanged. */ 6973 6974static bfd_reloc_code_real_type 6975micromips_map_reloc (bfd_reloc_code_real_type reloc) 6976{ 6977 static const bfd_reloc_code_real_type relocs[][2] = 6978 { 6979 /* Keep sorted incrementally by the left-hand key. */ 6980 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 }, 6981 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 }, 6982 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP }, 6983 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 }, 6984 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S }, 6985 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 }, 6986 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL }, 6987 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 }, 6988 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 }, 6989 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 }, 6990 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 }, 6991 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 }, 6992 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 }, 6993 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB }, 6994 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE }, 6995 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST }, 6996 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP }, 6997 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST }, 6998 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER }, 6999 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP }, 7000 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD }, 7001 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM }, 7002 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 }, 7003 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 }, 7004 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL }, 7005 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 }, 7006 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 } 7007 }; 7008 bfd_reloc_code_real_type r; 7009 size_t i; 7010 7011 if (!mips_opts.micromips) 7012 return reloc; 7013 for (i = 0; i < ARRAY_SIZE (relocs); i++) 7014 { 7015 r = relocs[i][0]; 7016 if (r > reloc) 7017 return reloc; 7018 if (r == reloc) 7019 return relocs[i][1]; 7020 } 7021 return reloc; 7022} 7023 7024/* Try to resolve relocation RELOC against constant OPERAND at assembly time. 7025 Return true on success, storing the resolved value in RESULT. */ 7026 7027static bfd_boolean 7028calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand, 7029 offsetT *result) 7030{ 7031 switch (reloc) 7032 { 7033 case BFD_RELOC_MIPS_HIGHEST: 7034 case BFD_RELOC_MICROMIPS_HIGHEST: 7035 *result = ((operand + 0x800080008000ull) >> 48) & 0xffff; 7036 return TRUE; 7037 7038 case BFD_RELOC_MIPS_HIGHER: 7039 case BFD_RELOC_MICROMIPS_HIGHER: 7040 *result = ((operand + 0x80008000ull) >> 32) & 0xffff; 7041 return TRUE; 7042 7043 case BFD_RELOC_HI16_S: 7044 case BFD_RELOC_HI16_S_PCREL: 7045 case BFD_RELOC_MICROMIPS_HI16_S: 7046 case BFD_RELOC_MIPS16_HI16_S: 7047 *result = ((operand + 0x8000) >> 16) & 0xffff; 7048 return TRUE; 7049 7050 case BFD_RELOC_HI16: 7051 case BFD_RELOC_MICROMIPS_HI16: 7052 case BFD_RELOC_MIPS16_HI16: 7053 *result = (operand >> 16) & 0xffff; 7054 return TRUE; 7055 7056 case BFD_RELOC_LO16: 7057 case BFD_RELOC_LO16_PCREL: 7058 case BFD_RELOC_MICROMIPS_LO16: 7059 case BFD_RELOC_MIPS16_LO16: 7060 *result = operand & 0xffff; 7061 return TRUE; 7062 7063 case BFD_RELOC_UNUSED: 7064 *result = operand; 7065 return TRUE; 7066 7067 default: 7068 return FALSE; 7069 } 7070} 7071 7072/* Output an instruction. IP is the instruction information. 7073 ADDRESS_EXPR is an operand of the instruction to be used with 7074 RELOC_TYPE. EXPANSIONP is true if the instruction is part of 7075 a macro expansion. */ 7076 7077static void 7078append_insn (struct mips_cl_insn *ip, expressionS *address_expr, 7079 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp) 7080{ 7081 unsigned long prev_pinfo2, pinfo; 7082 bfd_boolean relaxed_branch = FALSE; 7083 enum append_method method; 7084 bfd_boolean relax32; 7085 int branch_disp; 7086 7087 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION) 7088 fix_loongson2f (ip); 7089 7090 file_ase_mips16 |= mips_opts.mips16; 7091 file_ase_micromips |= mips_opts.micromips; 7092 7093 prev_pinfo2 = history[0].insn_mo->pinfo2; 7094 pinfo = ip->insn_mo->pinfo; 7095 7096 /* Don't raise alarm about `nods' frags as they'll fill in the right 7097 kind of nop in relaxation if required. */ 7098 if (mips_opts.micromips 7099 && !expansionp 7100 && !(history[0].frag 7101 && history[0].frag->fr_type == rs_machine_dependent 7102 && RELAX_MICROMIPS_P (history[0].frag->fr_subtype) 7103 && RELAX_MICROMIPS_NODS (history[0].frag->fr_subtype)) 7104 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 7105 && micromips_insn_length (ip->insn_mo) != 2) 7106 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 7107 && micromips_insn_length (ip->insn_mo) != 4))) 7108 as_warn (_("wrong size instruction in a %u-bit branch delay slot"), 7109 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32); 7110 7111 if (address_expr == NULL) 7112 ip->complete_p = 1; 7113 else if (reloc_type[0] <= BFD_RELOC_UNUSED 7114 && reloc_type[1] == BFD_RELOC_UNUSED 7115 && reloc_type[2] == BFD_RELOC_UNUSED 7116 && address_expr->X_op == O_constant) 7117 { 7118 switch (*reloc_type) 7119 { 7120 case BFD_RELOC_MIPS_JMP: 7121 { 7122 int shift; 7123 7124 /* Shift is 2, unusually, for microMIPS JALX. */ 7125 shift = (mips_opts.micromips 7126 && strcmp (ip->insn_mo->name, "jalx") != 0) ? 1 : 2; 7127 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) 7128 as_bad (_("jump to misaligned address (0x%lx)"), 7129 (unsigned long) address_expr->X_add_number); 7130 ip->insn_opcode |= ((address_expr->X_add_number >> shift) 7131 & 0x3ffffff); 7132 ip->complete_p = 1; 7133 } 7134 break; 7135 7136 case BFD_RELOC_MIPS16_JMP: 7137 if ((address_expr->X_add_number & 3) != 0) 7138 as_bad (_("jump to misaligned address (0x%lx)"), 7139 (unsigned long) address_expr->X_add_number); 7140 ip->insn_opcode |= 7141 (((address_expr->X_add_number & 0x7c0000) << 3) 7142 | ((address_expr->X_add_number & 0xf800000) >> 7) 7143 | ((address_expr->X_add_number & 0x3fffc) >> 2)); 7144 ip->complete_p = 1; 7145 break; 7146 7147 case BFD_RELOC_16_PCREL_S2: 7148 { 7149 int shift; 7150 7151 shift = mips_opts.micromips ? 1 : 2; 7152 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) 7153 as_bad (_("branch to misaligned address (0x%lx)"), 7154 (unsigned long) address_expr->X_add_number); 7155 if (!mips_relax_branch) 7156 { 7157 if ((address_expr->X_add_number + (1 << (shift + 15))) 7158 & ~((1 << (shift + 16)) - 1)) 7159 as_bad (_("branch address range overflow (0x%lx)"), 7160 (unsigned long) address_expr->X_add_number); 7161 ip->insn_opcode |= ((address_expr->X_add_number >> shift) 7162 & 0xffff); 7163 } 7164 } 7165 break; 7166 7167 case BFD_RELOC_MIPS_21_PCREL_S2: 7168 { 7169 int shift; 7170 7171 shift = 2; 7172 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) 7173 as_bad (_("branch to misaligned address (0x%lx)"), 7174 (unsigned long) address_expr->X_add_number); 7175 if ((address_expr->X_add_number + (1 << (shift + 20))) 7176 & ~((1 << (shift + 21)) - 1)) 7177 as_bad (_("branch address range overflow (0x%lx)"), 7178 (unsigned long) address_expr->X_add_number); 7179 ip->insn_opcode |= ((address_expr->X_add_number >> shift) 7180 & 0x1fffff); 7181 } 7182 break; 7183 7184 case BFD_RELOC_MIPS_26_PCREL_S2: 7185 { 7186 int shift; 7187 7188 shift = 2; 7189 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) 7190 as_bad (_("branch to misaligned address (0x%lx)"), 7191 (unsigned long) address_expr->X_add_number); 7192 if ((address_expr->X_add_number + (1 << (shift + 25))) 7193 & ~((1 << (shift + 26)) - 1)) 7194 as_bad (_("branch address range overflow (0x%lx)"), 7195 (unsigned long) address_expr->X_add_number); 7196 ip->insn_opcode |= ((address_expr->X_add_number >> shift) 7197 & 0x3ffffff); 7198 } 7199 break; 7200 7201 default: 7202 { 7203 offsetT value; 7204 7205 if (calculate_reloc (*reloc_type, address_expr->X_add_number, 7206 &value)) 7207 { 7208 ip->insn_opcode |= value & 0xffff; 7209 ip->complete_p = 1; 7210 } 7211 } 7212 break; 7213 } 7214 } 7215 7216 if (mips_relax.sequence != 2 && !mips_opts.noreorder) 7217 { 7218 /* There are a lot of optimizations we could do that we don't. 7219 In particular, we do not, in general, reorder instructions. 7220 If you use gcc with optimization, it will reorder 7221 instructions and generally do much more optimization then we 7222 do here; repeating all that work in the assembler would only 7223 benefit hand written assembly code, and does not seem worth 7224 it. */ 7225 int nops = (mips_optimize == 0 7226 ? nops_for_insn (0, history, NULL) 7227 : nops_for_insn_or_target (0, history, ip)); 7228 if (nops > 0) 7229 { 7230 fragS *old_frag; 7231 unsigned long old_frag_offset; 7232 int i; 7233 7234 old_frag = frag_now; 7235 old_frag_offset = frag_now_fix (); 7236 7237 for (i = 0; i < nops; i++) 7238 add_fixed_insn (NOP_INSN); 7239 insert_into_history (0, nops, NOP_INSN); 7240 7241 if (listing) 7242 { 7243 listing_prev_line (); 7244 /* We may be at the start of a variant frag. In case we 7245 are, make sure there is enough space for the frag 7246 after the frags created by listing_prev_line. The 7247 argument to frag_grow here must be at least as large 7248 as the argument to all other calls to frag_grow in 7249 this file. We don't have to worry about being in the 7250 middle of a variant frag, because the variants insert 7251 all needed nop instructions themselves. */ 7252 frag_grow (40); 7253 } 7254 7255 mips_move_text_labels (); 7256 7257#ifndef NO_ECOFF_DEBUGGING 7258 if (ECOFF_DEBUGGING) 7259 ecoff_fix_loc (old_frag, old_frag_offset); 7260#endif 7261 } 7262 } 7263 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) 7264 { 7265 int nops; 7266 7267 /* Work out how many nops in prev_nop_frag are needed by IP, 7268 ignoring hazards generated by the first prev_nop_frag_since 7269 instructions. */ 7270 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip); 7271 gas_assert (nops <= prev_nop_frag_holds); 7272 7273 /* Enforce NOPS as a minimum. */ 7274 if (nops > prev_nop_frag_required) 7275 prev_nop_frag_required = nops; 7276 7277 if (prev_nop_frag_holds == prev_nop_frag_required) 7278 { 7279 /* Settle for the current number of nops. Update the history 7280 accordingly (for the benefit of any future .set reorder code). */ 7281 prev_nop_frag = NULL; 7282 insert_into_history (prev_nop_frag_since, 7283 prev_nop_frag_holds, NOP_INSN); 7284 } 7285 else 7286 { 7287 /* Allow this instruction to replace one of the nops that was 7288 tentatively added to prev_nop_frag. */ 7289 prev_nop_frag->fr_fix -= NOP_INSN_SIZE; 7290 prev_nop_frag_holds--; 7291 prev_nop_frag_since++; 7292 } 7293 } 7294 7295 method = get_append_method (ip, address_expr, reloc_type); 7296 branch_disp = method == APPEND_SWAP ? insn_length (history) : 0; 7297 7298 dwarf2_emit_insn (0); 7299 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses, 7300 so "move" the instruction address accordingly. 7301 7302 Also, it doesn't seem appropriate for the assembler to reorder .loc 7303 entries. If this instruction is a branch that we are going to swap 7304 with the previous instruction, the two instructions should be 7305 treated as a unit, and the debug information for both instructions 7306 should refer to the start of the branch sequence. Using the 7307 current position is certainly wrong when swapping a 32-bit branch 7308 and a 16-bit delay slot, since the current position would then be 7309 in the middle of a branch. */ 7310 dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp); 7311 7312 relax32 = (mips_relax_branch 7313 /* Don't try branch relaxation within .set nomacro, or within 7314 .set noat if we use $at for PIC computations. If it turns 7315 out that the branch was out-of-range, we'll get an error. */ 7316 && !mips_opts.warn_about_macros 7317 && (mips_opts.at || mips_pic == NO_PIC) 7318 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F 7319 as they have no complementing branches. */ 7320 && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP))); 7321 7322 if (!HAVE_CODE_COMPRESSION 7323 && address_expr 7324 && relax32 7325 && *reloc_type == BFD_RELOC_16_PCREL_S2 7326 && delayed_branch_p (ip)) 7327 { 7328 relaxed_branch = TRUE; 7329 add_relaxed_insn (ip, (relaxed_branch_length 7330 (NULL, NULL, 7331 uncond_branch_p (ip) ? -1 7332 : branch_likely_p (ip) ? 1 7333 : 0)), 4, 7334 RELAX_BRANCH_ENCODE 7335 (AT, 7336 uncond_branch_p (ip), 7337 branch_likely_p (ip), 7338 pinfo & INSN_WRITE_GPR_31, 7339 0), 7340 address_expr->X_add_symbol, 7341 address_expr->X_add_number); 7342 *reloc_type = BFD_RELOC_UNUSED; 7343 } 7344 else if (mips_opts.micromips 7345 && address_expr 7346 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2) 7347 || *reloc_type > BFD_RELOC_UNUSED) 7348 && (delayed_branch_p (ip) || compact_branch_p (ip)) 7349 /* Don't try branch relaxation when users specify 7350 16-bit/32-bit instructions. */ 7351 && !forced_insn_length) 7352 { 7353 bfd_boolean relax16 = (method != APPEND_ADD_COMPACT 7354 && *reloc_type > BFD_RELOC_UNUSED); 7355 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0; 7356 int uncond = uncond_branch_p (ip) ? -1 : 0; 7357 int compact = compact_branch_p (ip) || method == APPEND_ADD_COMPACT; 7358 int nods = method == APPEND_ADD_WITH_NOP; 7359 int al = pinfo & INSN_WRITE_GPR_31; 7360 int length32 = nods ? 8 : 4; 7361 7362 gas_assert (address_expr != NULL); 7363 gas_assert (!mips_relax.sequence); 7364 7365 relaxed_branch = TRUE; 7366 if (nods) 7367 method = APPEND_ADD; 7368 if (relax32) 7369 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond); 7370 add_relaxed_insn (ip, length32, relax16 ? 2 : 4, 7371 RELAX_MICROMIPS_ENCODE (type, AT, mips_opts.insn32, 7372 uncond, compact, al, nods, 7373 relax32, 0, 0), 7374 address_expr->X_add_symbol, 7375 address_expr->X_add_number); 7376 *reloc_type = BFD_RELOC_UNUSED; 7377 } 7378 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED) 7379 { 7380 bfd_boolean require_unextended; 7381 bfd_boolean require_extended; 7382 symbolS *symbol; 7383 offsetT offset; 7384 7385 if (forced_insn_length != 0) 7386 { 7387 require_unextended = forced_insn_length == 2; 7388 require_extended = forced_insn_length == 4; 7389 } 7390 else 7391 { 7392 require_unextended = (mips_opts.noautoextend 7393 && !mips_opcode_32bit_p (ip->insn_mo)); 7394 require_extended = 0; 7395 } 7396 7397 /* We need to set up a variant frag. */ 7398 gas_assert (address_expr != NULL); 7399 /* Pass any `O_symbol' expression unchanged as an `expr_section' 7400 symbol created by `make_expr_symbol' may not get a necessary 7401 external relocation produced. */ 7402 if (address_expr->X_op == O_symbol) 7403 { 7404 symbol = address_expr->X_add_symbol; 7405 offset = address_expr->X_add_number; 7406 } 7407 else 7408 { 7409 symbol = make_expr_symbol (address_expr); 7410 offset = 0; 7411 } 7412 add_relaxed_insn (ip, 4, 0, 7413 RELAX_MIPS16_ENCODE 7414 (*reloc_type - BFD_RELOC_UNUSED, 7415 require_unextended, require_extended, 7416 delayed_branch_p (&history[0]), 7417 history[0].mips16_absolute_jump_p), 7418 symbol, offset); 7419 } 7420 else if (mips_opts.mips16 && insn_length (ip) == 2) 7421 { 7422 if (!delayed_branch_p (ip)) 7423 /* Make sure there is enough room to swap this instruction with 7424 a following jump instruction. */ 7425 frag_grow (6); 7426 add_fixed_insn (ip); 7427 } 7428 else 7429 { 7430 if (mips_opts.mips16 7431 && mips_opts.noreorder 7432 && delayed_branch_p (&history[0])) 7433 as_warn (_("extended instruction in delay slot")); 7434 7435 if (mips_relax.sequence) 7436 { 7437 /* If we've reached the end of this frag, turn it into a variant 7438 frag and record the information for the instructions we've 7439 written so far. */ 7440 if (frag_room () < 4) 7441 relax_close_frag (); 7442 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip); 7443 } 7444 7445 if (mips_relax.sequence != 2) 7446 { 7447 if (mips_macro_warning.first_insn_sizes[0] == 0) 7448 mips_macro_warning.first_insn_sizes[0] = insn_length (ip); 7449 mips_macro_warning.sizes[0] += insn_length (ip); 7450 mips_macro_warning.insns[0]++; 7451 } 7452 if (mips_relax.sequence != 1) 7453 { 7454 if (mips_macro_warning.first_insn_sizes[1] == 0) 7455 mips_macro_warning.first_insn_sizes[1] = insn_length (ip); 7456 mips_macro_warning.sizes[1] += insn_length (ip); 7457 mips_macro_warning.insns[1]++; 7458 } 7459 7460 if (mips_opts.mips16) 7461 { 7462 ip->fixed_p = 1; 7463 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); 7464 } 7465 add_fixed_insn (ip); 7466 } 7467 7468 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED) 7469 { 7470 bfd_reloc_code_real_type final_type[3]; 7471 reloc_howto_type *howto0; 7472 reloc_howto_type *howto; 7473 int i; 7474 7475 /* Perform any necessary conversion to microMIPS relocations 7476 and find out how many relocations there actually are. */ 7477 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++) 7478 final_type[i] = micromips_map_reloc (reloc_type[i]); 7479 7480 /* In a compound relocation, it is the final (outermost) 7481 operator that determines the relocated field. */ 7482 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]); 7483 if (!howto) 7484 abort (); 7485 7486 if (i > 1) 7487 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]); 7488 ip->fixp[0] = fix_new_exp (ip->frag, ip->where, 7489 bfd_get_reloc_size (howto), 7490 address_expr, 7491 howto0 && howto0->pc_relative, 7492 final_type[0]); 7493 7494 /* Tag symbols that have a R_MIPS16_26 relocation against them. */ 7495 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy) 7496 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1; 7497 7498 /* These relocations can have an addend that won't fit in 7499 4 octets for 64bit assembly. */ 7500 if (GPR_SIZE == 64 7501 && ! howto->partial_inplace 7502 && (reloc_type[0] == BFD_RELOC_16 7503 || reloc_type[0] == BFD_RELOC_32 7504 || reloc_type[0] == BFD_RELOC_MIPS_JMP 7505 || reloc_type[0] == BFD_RELOC_GPREL16 7506 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL 7507 || reloc_type[0] == BFD_RELOC_GPREL32 7508 || reloc_type[0] == BFD_RELOC_64 7509 || reloc_type[0] == BFD_RELOC_CTOR 7510 || reloc_type[0] == BFD_RELOC_MIPS_SUB 7511 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST 7512 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER 7513 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP 7514 || reloc_type[0] == BFD_RELOC_MIPS_REL16 7515 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT 7516 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL 7517 || hi16_reloc_p (reloc_type[0]) 7518 || lo16_reloc_p (reloc_type[0]))) 7519 ip->fixp[0]->fx_no_overflow = 1; 7520 7521 /* These relocations can have an addend that won't fit in 2 octets. */ 7522 if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1 7523 || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1) 7524 ip->fixp[0]->fx_no_overflow = 1; 7525 7526 if (mips_relax.sequence) 7527 { 7528 if (mips_relax.first_fixup == 0) 7529 mips_relax.first_fixup = ip->fixp[0]; 7530 } 7531 else if (reloc_needs_lo_p (*reloc_type)) 7532 { 7533 struct mips_hi_fixup *hi_fixup; 7534 7535 /* Reuse the last entry if it already has a matching %lo. */ 7536 hi_fixup = mips_hi_fixup_list; 7537 if (hi_fixup == 0 7538 || !fixup_has_matching_lo_p (hi_fixup->fixp)) 7539 { 7540 hi_fixup = XNEW (struct mips_hi_fixup); 7541 hi_fixup->next = mips_hi_fixup_list; 7542 mips_hi_fixup_list = hi_fixup; 7543 } 7544 hi_fixup->fixp = ip->fixp[0]; 7545 hi_fixup->seg = now_seg; 7546 } 7547 7548 /* Add fixups for the second and third relocations, if given. 7549 Note that the ABI allows the second relocation to be 7550 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the 7551 moment we only use RSS_UNDEF, but we could add support 7552 for the others if it ever becomes necessary. */ 7553 for (i = 1; i < 3; i++) 7554 if (reloc_type[i] != BFD_RELOC_UNUSED) 7555 { 7556 ip->fixp[i] = fix_new (ip->frag, ip->where, 7557 ip->fixp[0]->fx_size, NULL, 0, 7558 FALSE, final_type[i]); 7559 7560 /* Use fx_tcbit to mark compound relocs. */ 7561 ip->fixp[0]->fx_tcbit = 1; 7562 ip->fixp[i]->fx_tcbit = 1; 7563 } 7564 } 7565 7566 /* Update the register mask information. */ 7567 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip); 7568 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip); 7569 7570 switch (method) 7571 { 7572 case APPEND_ADD: 7573 insert_into_history (0, 1, ip); 7574 break; 7575 7576 case APPEND_ADD_WITH_NOP: 7577 { 7578 struct mips_cl_insn *nop; 7579 7580 insert_into_history (0, 1, ip); 7581 nop = get_delay_slot_nop (ip); 7582 add_fixed_insn (nop); 7583 insert_into_history (0, 1, nop); 7584 if (mips_relax.sequence) 7585 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop); 7586 } 7587 break; 7588 7589 case APPEND_ADD_COMPACT: 7590 /* Convert MIPS16 jr/jalr into a "compact" jump. */ 7591 if (mips_opts.mips16) 7592 { 7593 ip->insn_opcode |= 0x0080; 7594 find_altered_mips16_opcode (ip); 7595 } 7596 /* Convert microMIPS instructions. */ 7597 else if (mips_opts.micromips) 7598 { 7599 /* jr16->jrc */ 7600 if ((ip->insn_opcode & 0xffe0) == 0x4580) 7601 ip->insn_opcode |= 0x0020; 7602 /* b16->bc */ 7603 else if ((ip->insn_opcode & 0xfc00) == 0xcc00) 7604 ip->insn_opcode = 0x40e00000; 7605 /* beqz16->beqzc, bnez16->bnezc */ 7606 else if ((ip->insn_opcode & 0xdc00) == 0x8c00) 7607 { 7608 unsigned long regno; 7609 7610 regno = ip->insn_opcode >> MICROMIPSOP_SH_MD; 7611 regno &= MICROMIPSOP_MASK_MD; 7612 regno = micromips_to_32_reg_d_map[regno]; 7613 ip->insn_opcode = (((ip->insn_opcode << 9) & 0x00400000) 7614 | (regno << MICROMIPSOP_SH_RS) 7615 | 0x40a00000) ^ 0x00400000; 7616 } 7617 /* beqz->beqzc, bnez->bnezc */ 7618 else if ((ip->insn_opcode & 0xdfe00000) == 0x94000000) 7619 ip->insn_opcode = ((ip->insn_opcode & 0x001f0000) 7620 | ((ip->insn_opcode >> 7) & 0x00400000) 7621 | 0x40a00000) ^ 0x00400000; 7622 /* beq $0->beqzc, bne $0->bnezc */ 7623 else if ((ip->insn_opcode & 0xdc1f0000) == 0x94000000) 7624 ip->insn_opcode = (((ip->insn_opcode >> 7625 (MICROMIPSOP_SH_RT - MICROMIPSOP_SH_RS)) 7626 & (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS)) 7627 | ((ip->insn_opcode >> 7) & 0x00400000) 7628 | 0x40a00000) ^ 0x00400000; 7629 else 7630 abort (); 7631 find_altered_micromips_opcode (ip); 7632 } 7633 else 7634 abort (); 7635 install_insn (ip); 7636 insert_into_history (0, 1, ip); 7637 break; 7638 7639 case APPEND_SWAP: 7640 { 7641 struct mips_cl_insn delay = history[0]; 7642 7643 if (relaxed_branch || delay.frag != ip->frag) 7644 { 7645 /* Add the delay slot instruction to the end of the 7646 current frag and shrink the fixed part of the 7647 original frag. If the branch occupies the tail of 7648 the latter, move it backwards to cover the gap. */ 7649 delay.frag->fr_fix -= branch_disp; 7650 if (delay.frag == ip->frag) 7651 move_insn (ip, ip->frag, ip->where - branch_disp); 7652 add_fixed_insn (&delay); 7653 } 7654 else 7655 { 7656 /* If this is not a relaxed branch and we are in the 7657 same frag, then just swap the instructions. */ 7658 move_insn (ip, delay.frag, delay.where); 7659 move_insn (&delay, ip->frag, ip->where + insn_length (ip)); 7660 } 7661 history[0] = *ip; 7662 delay.fixed_p = 1; 7663 insert_into_history (0, 1, &delay); 7664 } 7665 break; 7666 } 7667 7668 /* If we have just completed an unconditional branch, clear the history. */ 7669 if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1])) 7670 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0]))) 7671 { 7672 unsigned int i; 7673 7674 mips_no_prev_insn (); 7675 7676 for (i = 0; i < ARRAY_SIZE (history); i++) 7677 history[i].cleared_p = 1; 7678 } 7679 7680 /* We need to emit a label at the end of branch-likely macros. */ 7681 if (emit_branch_likely_macro) 7682 { 7683 emit_branch_likely_macro = FALSE; 7684 micromips_add_label (); 7685 } 7686 7687 /* We just output an insn, so the next one doesn't have a label. */ 7688 mips_clear_insn_labels (); 7689} 7690 7691/* Forget that there was any previous instruction or label. 7692 When BRANCH is true, the branch history is also flushed. */ 7693 7694static void 7695mips_no_prev_insn (void) 7696{ 7697 prev_nop_frag = NULL; 7698 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); 7699 mips_clear_insn_labels (); 7700} 7701 7702/* This function must be called before we emit something other than 7703 instructions. It is like mips_no_prev_insn except that it inserts 7704 any NOPS that might be needed by previous instructions. */ 7705 7706void 7707mips_emit_delays (void) 7708{ 7709 if (! mips_opts.noreorder) 7710 { 7711 int nops = nops_for_insn (0, history, NULL); 7712 if (nops > 0) 7713 { 7714 while (nops-- > 0) 7715 add_fixed_insn (NOP_INSN); 7716 mips_move_text_labels (); 7717 } 7718 } 7719 mips_no_prev_insn (); 7720} 7721 7722/* Start a (possibly nested) noreorder block. */ 7723 7724static void 7725start_noreorder (void) 7726{ 7727 if (mips_opts.noreorder == 0) 7728 { 7729 unsigned int i; 7730 int nops; 7731 7732 /* None of the instructions before the .set noreorder can be moved. */ 7733 for (i = 0; i < ARRAY_SIZE (history); i++) 7734 history[i].fixed_p = 1; 7735 7736 /* Insert any nops that might be needed between the .set noreorder 7737 block and the previous instructions. We will later remove any 7738 nops that turn out not to be needed. */ 7739 nops = nops_for_insn (0, history, NULL); 7740 if (nops > 0) 7741 { 7742 if (mips_optimize != 0) 7743 { 7744 /* Record the frag which holds the nop instructions, so 7745 that we can remove them if we don't need them. */ 7746 frag_grow (nops * NOP_INSN_SIZE); 7747 prev_nop_frag = frag_now; 7748 prev_nop_frag_holds = nops; 7749 prev_nop_frag_required = 0; 7750 prev_nop_frag_since = 0; 7751 } 7752 7753 for (; nops > 0; --nops) 7754 add_fixed_insn (NOP_INSN); 7755 7756 /* Move on to a new frag, so that it is safe to simply 7757 decrease the size of prev_nop_frag. */ 7758 frag_wane (frag_now); 7759 frag_new (0); 7760 mips_move_text_labels (); 7761 } 7762 mips_mark_labels (); 7763 mips_clear_insn_labels (); 7764 } 7765 mips_opts.noreorder++; 7766 mips_any_noreorder = 1; 7767} 7768 7769/* End a nested noreorder block. */ 7770 7771static void 7772end_noreorder (void) 7773{ 7774 mips_opts.noreorder--; 7775 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) 7776 { 7777 /* Commit to inserting prev_nop_frag_required nops and go back to 7778 handling nop insertion the .set reorder way. */ 7779 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) 7780 * NOP_INSN_SIZE); 7781 insert_into_history (prev_nop_frag_since, 7782 prev_nop_frag_required, NOP_INSN); 7783 prev_nop_frag = NULL; 7784 } 7785} 7786 7787/* Sign-extend 32-bit mode constants that have bit 31 set and all 7788 higher bits unset. */ 7789 7790static void 7791normalize_constant_expr (expressionS *ex) 7792{ 7793 if (ex->X_op == O_constant 7794 && IS_ZEXT_32BIT_NUM (ex->X_add_number)) 7795 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) 7796 - 0x80000000); 7797} 7798 7799/* Sign-extend 32-bit mode address offsets that have bit 31 set and 7800 all higher bits unset. */ 7801 7802static void 7803normalize_address_expr (expressionS *ex) 7804{ 7805 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) 7806 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) 7807 && IS_ZEXT_32BIT_NUM (ex->X_add_number)) 7808 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) 7809 - 0x80000000); 7810} 7811 7812/* Try to match TOKENS against OPCODE, storing the result in INSN. 7813 Return true if the match was successful. 7814 7815 OPCODE_EXTRA is a value that should be ORed into the opcode 7816 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if 7817 there are more alternatives after OPCODE and SOFT_MATCH is 7818 as for mips_arg_info. */ 7819 7820static bfd_boolean 7821match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode, 7822 struct mips_operand_token *tokens, unsigned int opcode_extra, 7823 bfd_boolean lax_match, bfd_boolean complete_p) 7824{ 7825 const char *args; 7826 struct mips_arg_info arg; 7827 const struct mips_operand *operand; 7828 char c; 7829 7830 imm_expr.X_op = O_absent; 7831 offset_expr.X_op = O_absent; 7832 offset_reloc[0] = BFD_RELOC_UNUSED; 7833 offset_reloc[1] = BFD_RELOC_UNUSED; 7834 offset_reloc[2] = BFD_RELOC_UNUSED; 7835 7836 create_insn (insn, opcode); 7837 /* When no opcode suffix is specified, assume ".xyzw". */ 7838 if ((opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0 && opcode_extra == 0) 7839 insn->insn_opcode |= 0xf << mips_vu0_channel_mask.lsb; 7840 else 7841 insn->insn_opcode |= opcode_extra; 7842 memset (&arg, 0, sizeof (arg)); 7843 arg.insn = insn; 7844 arg.token = tokens; 7845 arg.argnum = 1; 7846 arg.last_regno = ILLEGAL_REG; 7847 arg.dest_regno = ILLEGAL_REG; 7848 arg.lax_match = lax_match; 7849 for (args = opcode->args;; ++args) 7850 { 7851 if (arg.token->type == OT_END) 7852 { 7853 /* Handle unary instructions in which only one operand is given. 7854 The source is then the same as the destination. */ 7855 if (arg.opnum == 1 && *args == ',') 7856 { 7857 operand = (mips_opts.micromips 7858 ? decode_micromips_operand (args + 1) 7859 : decode_mips_operand (args + 1)); 7860 if (operand && mips_optional_operand_p (operand)) 7861 { 7862 arg.token = tokens; 7863 arg.argnum = 1; 7864 continue; 7865 } 7866 } 7867 7868 /* Treat elided base registers as $0. */ 7869 if (strcmp (args, "(b)") == 0) 7870 args += 3; 7871 7872 if (args[0] == '+') 7873 switch (args[1]) 7874 { 7875 case 'K': 7876 case 'N': 7877 /* The register suffix is optional. */ 7878 args += 2; 7879 break; 7880 } 7881 7882 /* Fail the match if there were too few operands. */ 7883 if (*args) 7884 return FALSE; 7885 7886 /* Successful match. */ 7887 if (!complete_p) 7888 return TRUE; 7889 clear_insn_error (); 7890 if (arg.dest_regno == arg.last_regno 7891 && strncmp (insn->insn_mo->name, "jalr", 4) == 0) 7892 { 7893 if (arg.opnum == 2) 7894 set_insn_error 7895 (0, _("source and destination must be different")); 7896 else if (arg.last_regno == 31) 7897 set_insn_error 7898 (0, _("a destination register must be supplied")); 7899 } 7900 else if (arg.last_regno == 31 7901 && (strncmp (insn->insn_mo->name, "bltzal", 6) == 0 7902 || strncmp (insn->insn_mo->name, "bgezal", 6) == 0)) 7903 set_insn_error (0, _("the source register must not be $31")); 7904 check_completed_insn (&arg); 7905 return TRUE; 7906 } 7907 7908 /* Fail the match if the line has too many operands. */ 7909 if (*args == 0) 7910 return FALSE; 7911 7912 /* Handle characters that need to match exactly. */ 7913 if (*args == '(' || *args == ')' || *args == ',') 7914 { 7915 if (match_char (&arg, *args)) 7916 continue; 7917 return FALSE; 7918 } 7919 if (*args == '#') 7920 { 7921 ++args; 7922 if (arg.token->type == OT_DOUBLE_CHAR 7923 && arg.token->u.ch == *args) 7924 { 7925 ++arg.token; 7926 continue; 7927 } 7928 return FALSE; 7929 } 7930 7931 /* Handle special macro operands. Work out the properties of 7932 other operands. */ 7933 arg.opnum += 1; 7934 switch (*args) 7935 { 7936 case '-': 7937 switch (args[1]) 7938 { 7939 case 'A': 7940 *offset_reloc = BFD_RELOC_MIPS_19_PCREL_S2; 7941 break; 7942 7943 case 'B': 7944 *offset_reloc = BFD_RELOC_MIPS_18_PCREL_S3; 7945 break; 7946 } 7947 break; 7948 7949 case '+': 7950 switch (args[1]) 7951 { 7952 case 'i': 7953 *offset_reloc = BFD_RELOC_MIPS_JMP; 7954 break; 7955 7956 case '\'': 7957 *offset_reloc = BFD_RELOC_MIPS_26_PCREL_S2; 7958 break; 7959 7960 case '\"': 7961 *offset_reloc = BFD_RELOC_MIPS_21_PCREL_S2; 7962 break; 7963 } 7964 break; 7965 7966 case 'I': 7967 if (!match_const_int (&arg, &imm_expr.X_add_number)) 7968 return FALSE; 7969 imm_expr.X_op = O_constant; 7970 if (GPR_SIZE == 32) 7971 normalize_constant_expr (&imm_expr); 7972 continue; 7973 7974 case 'A': 7975 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(') 7976 { 7977 /* Assume that the offset has been elided and that what 7978 we saw was a base register. The match will fail later 7979 if that assumption turns out to be wrong. */ 7980 offset_expr.X_op = O_constant; 7981 offset_expr.X_add_number = 0; 7982 } 7983 else 7984 { 7985 if (!match_expression (&arg, &offset_expr, offset_reloc)) 7986 return FALSE; 7987 normalize_address_expr (&offset_expr); 7988 } 7989 continue; 7990 7991 case 'F': 7992 if (!match_float_constant (&arg, &imm_expr, &offset_expr, 7993 8, TRUE)) 7994 return FALSE; 7995 continue; 7996 7997 case 'L': 7998 if (!match_float_constant (&arg, &imm_expr, &offset_expr, 7999 8, FALSE)) 8000 return FALSE; 8001 continue; 8002 8003 case 'f': 8004 if (!match_float_constant (&arg, &imm_expr, &offset_expr, 8005 4, TRUE)) 8006 return FALSE; 8007 continue; 8008 8009 case 'l': 8010 if (!match_float_constant (&arg, &imm_expr, &offset_expr, 8011 4, FALSE)) 8012 return FALSE; 8013 continue; 8014 8015 case 'p': 8016 *offset_reloc = BFD_RELOC_16_PCREL_S2; 8017 break; 8018 8019 case 'a': 8020 *offset_reloc = BFD_RELOC_MIPS_JMP; 8021 break; 8022 8023 case 'm': 8024 gas_assert (mips_opts.micromips); 8025 c = args[1]; 8026 switch (c) 8027 { 8028 case 'D': 8029 case 'E': 8030 if (!forced_insn_length) 8031 *offset_reloc = (int) BFD_RELOC_UNUSED + c; 8032 else if (c == 'D') 8033 *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1; 8034 else 8035 *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1; 8036 break; 8037 } 8038 break; 8039 } 8040 8041 operand = (mips_opts.micromips 8042 ? decode_micromips_operand (args) 8043 : decode_mips_operand (args)); 8044 if (!operand) 8045 abort (); 8046 8047 /* Skip prefixes. */ 8048 if (*args == '+' || *args == 'm' || *args == '-') 8049 args++; 8050 8051 if (mips_optional_operand_p (operand) 8052 && args[1] == ',' 8053 && (arg.token[0].type != OT_REG 8054 || arg.token[1].type == OT_END)) 8055 { 8056 /* Assume that the register has been elided and is the 8057 same as the first operand. */ 8058 arg.token = tokens; 8059 arg.argnum = 1; 8060 } 8061 8062 if (!match_operand (&arg, operand)) 8063 return FALSE; 8064 } 8065} 8066 8067/* Like match_insn, but for MIPS16. */ 8068 8069static bfd_boolean 8070match_mips16_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode, 8071 struct mips_operand_token *tokens) 8072{ 8073 const char *args; 8074 const struct mips_operand *operand; 8075 const struct mips_operand *ext_operand; 8076 int required_insn_length; 8077 struct mips_arg_info arg; 8078 int relax_char; 8079 8080 if (forced_insn_length) 8081 required_insn_length = forced_insn_length; 8082 else if (mips_opts.noautoextend && !mips_opcode_32bit_p (opcode)) 8083 required_insn_length = 2; 8084 else 8085 required_insn_length = 0; 8086 8087 create_insn (insn, opcode); 8088 imm_expr.X_op = O_absent; 8089 offset_expr.X_op = O_absent; 8090 offset_reloc[0] = BFD_RELOC_UNUSED; 8091 offset_reloc[1] = BFD_RELOC_UNUSED; 8092 offset_reloc[2] = BFD_RELOC_UNUSED; 8093 relax_char = 0; 8094 8095 memset (&arg, 0, sizeof (arg)); 8096 arg.insn = insn; 8097 arg.token = tokens; 8098 arg.argnum = 1; 8099 arg.last_regno = ILLEGAL_REG; 8100 arg.dest_regno = ILLEGAL_REG; 8101 relax_char = 0; 8102 for (args = opcode->args;; ++args) 8103 { 8104 int c; 8105 8106 if (arg.token->type == OT_END) 8107 { 8108 offsetT value; 8109 8110 /* Handle unary instructions in which only one operand is given. 8111 The source is then the same as the destination. */ 8112 if (arg.opnum == 1 && *args == ',') 8113 { 8114 operand = decode_mips16_operand (args[1], FALSE); 8115 if (operand && mips_optional_operand_p (operand)) 8116 { 8117 arg.token = tokens; 8118 arg.argnum = 1; 8119 continue; 8120 } 8121 } 8122 8123 /* Fail the match if there were too few operands. */ 8124 if (*args) 8125 return FALSE; 8126 8127 /* Successful match. Stuff the immediate value in now, if 8128 we can. */ 8129 clear_insn_error (); 8130 if (opcode->pinfo == INSN_MACRO) 8131 { 8132 gas_assert (relax_char == 0 || relax_char == 'p'); 8133 gas_assert (*offset_reloc == BFD_RELOC_UNUSED); 8134 } 8135 else if (relax_char 8136 && offset_expr.X_op == O_constant 8137 && calculate_reloc (*offset_reloc, 8138 offset_expr.X_add_number, 8139 &value)) 8140 { 8141 mips16_immed (NULL, 0, relax_char, *offset_reloc, value, 8142 required_insn_length, &insn->insn_opcode); 8143 offset_expr.X_op = O_absent; 8144 *offset_reloc = BFD_RELOC_UNUSED; 8145 } 8146 else if (relax_char && *offset_reloc != BFD_RELOC_UNUSED) 8147 { 8148 if (required_insn_length == 2) 8149 set_insn_error (0, _("invalid unextended operand value")); 8150 else 8151 { 8152 forced_insn_length = 4; 8153 insn->insn_opcode |= MIPS16_EXTEND; 8154 } 8155 } 8156 else if (relax_char) 8157 *offset_reloc = (int) BFD_RELOC_UNUSED + relax_char; 8158 8159 check_completed_insn (&arg); 8160 return TRUE; 8161 } 8162 8163 /* Fail the match if the line has too many operands. */ 8164 if (*args == 0) 8165 return FALSE; 8166 8167 /* Handle characters that need to match exactly. */ 8168 if (*args == '(' || *args == ')' || *args == ',') 8169 { 8170 if (match_char (&arg, *args)) 8171 continue; 8172 return FALSE; 8173 } 8174 8175 arg.opnum += 1; 8176 c = *args; 8177 switch (c) 8178 { 8179 case 'p': 8180 case 'q': 8181 case 'A': 8182 case 'B': 8183 case 'E': 8184 relax_char = c; 8185 break; 8186 8187 case 'I': 8188 if (!match_const_int (&arg, &imm_expr.X_add_number)) 8189 return FALSE; 8190 imm_expr.X_op = O_constant; 8191 if (GPR_SIZE == 32) 8192 normalize_constant_expr (&imm_expr); 8193 continue; 8194 8195 case 'a': 8196 case 'i': 8197 *offset_reloc = BFD_RELOC_MIPS16_JMP; 8198 break; 8199 } 8200 8201 operand = decode_mips16_operand (c, mips_opcode_32bit_p (opcode)); 8202 if (!operand) 8203 abort (); 8204 8205 if (operand->type != OP_PCREL) 8206 { 8207 ext_operand = decode_mips16_operand (c, TRUE); 8208 if (operand != ext_operand) 8209 { 8210 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(') 8211 { 8212 offset_expr.X_op = O_constant; 8213 offset_expr.X_add_number = 0; 8214 relax_char = c; 8215 continue; 8216 } 8217 8218 /* We need the OT_INTEGER check because some MIPS16 8219 immediate variants are listed before the register ones. */ 8220 if (arg.token->type != OT_INTEGER 8221 || !match_expression (&arg, &offset_expr, offset_reloc)) 8222 return FALSE; 8223 8224 /* '8' is used for SLTI(U) and has traditionally not 8225 been allowed to take relocation operators. */ 8226 if (offset_reloc[0] != BFD_RELOC_UNUSED 8227 && (ext_operand->size != 16 || c == '8')) 8228 return FALSE; 8229 8230 relax_char = c; 8231 continue; 8232 } 8233 } 8234 8235 if (mips_optional_operand_p (operand) 8236 && args[1] == ',' 8237 && (arg.token[0].type != OT_REG 8238 || arg.token[1].type == OT_END)) 8239 { 8240 /* Assume that the register has been elided and is the 8241 same as the first operand. */ 8242 arg.token = tokens; 8243 arg.argnum = 1; 8244 } 8245 8246 if (!match_operand (&arg, operand)) 8247 return FALSE; 8248 } 8249} 8250 8251/* Record that the current instruction is invalid for the current ISA. */ 8252 8253static void 8254match_invalid_for_isa (void) 8255{ 8256 set_insn_error_ss 8257 (0, _("opcode not supported on this processor: %s (%s)"), 8258 mips_cpu_info_from_arch (mips_opts.arch)->name, 8259 mips_cpu_info_from_isa (mips_opts.isa)->name); 8260} 8261 8262/* Try to match TOKENS against a series of opcode entries, starting at FIRST. 8263 Return true if a definite match or failure was found, storing any match 8264 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode 8265 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already 8266 tried and failed to match under normal conditions and now want to try a 8267 more relaxed match. */ 8268 8269static bfd_boolean 8270match_insns (struct mips_cl_insn *insn, const struct mips_opcode *first, 8271 const struct mips_opcode *past, struct mips_operand_token *tokens, 8272 int opcode_extra, bfd_boolean lax_match) 8273{ 8274 const struct mips_opcode *opcode; 8275 const struct mips_opcode *invalid_delay_slot; 8276 bfd_boolean seen_valid_for_isa, seen_valid_for_size; 8277 8278 /* Search for a match, ignoring alternatives that don't satisfy the 8279 current ISA or forced_length. */ 8280 invalid_delay_slot = 0; 8281 seen_valid_for_isa = FALSE; 8282 seen_valid_for_size = FALSE; 8283 opcode = first; 8284 do 8285 { 8286 gas_assert (strcmp (opcode->name, first->name) == 0); 8287 if (is_opcode_valid (opcode)) 8288 { 8289 seen_valid_for_isa = TRUE; 8290 if (is_size_valid (opcode)) 8291 { 8292 bfd_boolean delay_slot_ok; 8293 8294 seen_valid_for_size = TRUE; 8295 delay_slot_ok = is_delay_slot_valid (opcode); 8296 if (match_insn (insn, opcode, tokens, opcode_extra, 8297 lax_match, delay_slot_ok)) 8298 { 8299 if (!delay_slot_ok) 8300 { 8301 if (!invalid_delay_slot) 8302 invalid_delay_slot = opcode; 8303 } 8304 else 8305 return TRUE; 8306 } 8307 } 8308 } 8309 ++opcode; 8310 } 8311 while (opcode < past && strcmp (opcode->name, first->name) == 0); 8312 8313 /* If the only matches we found had the wrong length for the delay slot, 8314 pick the first such match. We'll issue an appropriate warning later. */ 8315 if (invalid_delay_slot) 8316 { 8317 if (match_insn (insn, invalid_delay_slot, tokens, opcode_extra, 8318 lax_match, TRUE)) 8319 return TRUE; 8320 abort (); 8321 } 8322 8323 /* Handle the case where we didn't try to match an instruction because 8324 all the alternatives were incompatible with the current ISA. */ 8325 if (!seen_valid_for_isa) 8326 { 8327 match_invalid_for_isa (); 8328 return TRUE; 8329 } 8330 8331 /* Handle the case where we didn't try to match an instruction because 8332 all the alternatives were of the wrong size. */ 8333 if (!seen_valid_for_size) 8334 { 8335 if (mips_opts.insn32) 8336 set_insn_error (0, _("opcode not supported in the `insn32' mode")); 8337 else 8338 set_insn_error_i 8339 (0, _("unrecognized %d-bit version of microMIPS opcode"), 8340 8 * forced_insn_length); 8341 return TRUE; 8342 } 8343 8344 return FALSE; 8345} 8346 8347/* Like match_insns, but for MIPS16. */ 8348 8349static bfd_boolean 8350match_mips16_insns (struct mips_cl_insn *insn, const struct mips_opcode *first, 8351 struct mips_operand_token *tokens) 8352{ 8353 const struct mips_opcode *opcode; 8354 bfd_boolean seen_valid_for_isa; 8355 bfd_boolean seen_valid_for_size; 8356 8357 /* Search for a match, ignoring alternatives that don't satisfy the 8358 current ISA. There are no separate entries for extended forms so 8359 we deal with forced_length later. */ 8360 seen_valid_for_isa = FALSE; 8361 seen_valid_for_size = FALSE; 8362 opcode = first; 8363 do 8364 { 8365 gas_assert (strcmp (opcode->name, first->name) == 0); 8366 if (is_opcode_valid_16 (opcode)) 8367 { 8368 seen_valid_for_isa = TRUE; 8369 if (is_size_valid_16 (opcode)) 8370 { 8371 seen_valid_for_size = TRUE; 8372 if (match_mips16_insn (insn, opcode, tokens)) 8373 return TRUE; 8374 } 8375 } 8376 ++opcode; 8377 } 8378 while (opcode < &mips16_opcodes[bfd_mips16_num_opcodes] 8379 && strcmp (opcode->name, first->name) == 0); 8380 8381 /* Handle the case where we didn't try to match an instruction because 8382 all the alternatives were incompatible with the current ISA. */ 8383 if (!seen_valid_for_isa) 8384 { 8385 match_invalid_for_isa (); 8386 return TRUE; 8387 } 8388 8389 /* Handle the case where we didn't try to match an instruction because 8390 all the alternatives were of the wrong size. */ 8391 if (!seen_valid_for_size) 8392 { 8393 if (forced_insn_length == 2) 8394 set_insn_error 8395 (0, _("unrecognized unextended version of MIPS16 opcode")); 8396 else 8397 set_insn_error 8398 (0, _("unrecognized extended version of MIPS16 opcode")); 8399 return TRUE; 8400 } 8401 8402 return FALSE; 8403} 8404 8405/* Set up global variables for the start of a new macro. */ 8406 8407static void 8408macro_start (void) 8409{ 8410 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); 8411 memset (&mips_macro_warning.first_insn_sizes, 0, 8412 sizeof (mips_macro_warning.first_insn_sizes)); 8413 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns)); 8414 mips_macro_warning.delay_slot_p = (mips_opts.noreorder 8415 && delayed_branch_p (&history[0])); 8416 if (history[0].frag 8417 && history[0].frag->fr_type == rs_machine_dependent 8418 && RELAX_MICROMIPS_P (history[0].frag->fr_subtype) 8419 && RELAX_MICROMIPS_NODS (history[0].frag->fr_subtype)) 8420 mips_macro_warning.delay_slot_length = 0; 8421 else 8422 switch (history[0].insn_mo->pinfo2 8423 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT)) 8424 { 8425 case INSN2_BRANCH_DELAY_32BIT: 8426 mips_macro_warning.delay_slot_length = 4; 8427 break; 8428 case INSN2_BRANCH_DELAY_16BIT: 8429 mips_macro_warning.delay_slot_length = 2; 8430 break; 8431 default: 8432 mips_macro_warning.delay_slot_length = 0; 8433 break; 8434 } 8435 mips_macro_warning.first_frag = NULL; 8436} 8437 8438/* Given that a macro is longer than one instruction or of the wrong size, 8439 return the appropriate warning for it. Return null if no warning is 8440 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT, 8441 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND, 8442 and RELAX_NOMACRO. */ 8443 8444static const char * 8445macro_warning (relax_substateT subtype) 8446{ 8447 if (subtype & RELAX_DELAY_SLOT) 8448 return _("macro instruction expanded into multiple instructions" 8449 " in a branch delay slot"); 8450 else if (subtype & RELAX_NOMACRO) 8451 return _("macro instruction expanded into multiple instructions"); 8452 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST 8453 | RELAX_DELAY_SLOT_SIZE_SECOND)) 8454 return ((subtype & RELAX_DELAY_SLOT_16BIT) 8455 ? _("macro instruction expanded into a wrong size instruction" 8456 " in a 16-bit branch delay slot") 8457 : _("macro instruction expanded into a wrong size instruction" 8458 " in a 32-bit branch delay slot")); 8459 else 8460 return 0; 8461} 8462 8463/* Finish up a macro. Emit warnings as appropriate. */ 8464 8465static void 8466macro_end (void) 8467{ 8468 /* Relaxation warning flags. */ 8469 relax_substateT subtype = 0; 8470 8471 /* Check delay slot size requirements. */ 8472 if (mips_macro_warning.delay_slot_length == 2) 8473 subtype |= RELAX_DELAY_SLOT_16BIT; 8474 if (mips_macro_warning.delay_slot_length != 0) 8475 { 8476 if (mips_macro_warning.delay_slot_length 8477 != mips_macro_warning.first_insn_sizes[0]) 8478 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST; 8479 if (mips_macro_warning.delay_slot_length 8480 != mips_macro_warning.first_insn_sizes[1]) 8481 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND; 8482 } 8483 8484 /* Check instruction count requirements. */ 8485 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1) 8486 { 8487 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0]) 8488 subtype |= RELAX_SECOND_LONGER; 8489 if (mips_opts.warn_about_macros) 8490 subtype |= RELAX_NOMACRO; 8491 if (mips_macro_warning.delay_slot_p) 8492 subtype |= RELAX_DELAY_SLOT; 8493 } 8494 8495 /* If both alternatives fail to fill a delay slot correctly, 8496 emit the warning now. */ 8497 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0 8498 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0) 8499 { 8500 relax_substateT s; 8501 const char *msg; 8502 8503 s = subtype & (RELAX_DELAY_SLOT_16BIT 8504 | RELAX_DELAY_SLOT_SIZE_FIRST 8505 | RELAX_DELAY_SLOT_SIZE_SECOND); 8506 msg = macro_warning (s); 8507 if (msg != NULL) 8508 as_warn ("%s", msg); 8509 subtype &= ~s; 8510 } 8511 8512 /* If both implementations are longer than 1 instruction, then emit the 8513 warning now. */ 8514 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1) 8515 { 8516 relax_substateT s; 8517 const char *msg; 8518 8519 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT); 8520 msg = macro_warning (s); 8521 if (msg != NULL) 8522 as_warn ("%s", msg); 8523 subtype &= ~s; 8524 } 8525 8526 /* If any flags still set, then one implementation might need a warning 8527 and the other either will need one of a different kind or none at all. 8528 Pass any remaining flags over to relaxation. */ 8529 if (mips_macro_warning.first_frag != NULL) 8530 mips_macro_warning.first_frag->fr_subtype |= subtype; 8531} 8532 8533/* Instruction operand formats used in macros that vary between 8534 standard MIPS and microMIPS code. */ 8535 8536static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } }; 8537static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" }; 8538static const char * const jalr_fmt[2] = { "d,s", "t,s" }; 8539static const char * const lui_fmt[2] = { "t,u", "s,u" }; 8540static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" }; 8541static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } }; 8542static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" }; 8543static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" }; 8544 8545#define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32]) 8546#define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \ 8547 : cop12_fmt[mips_opts.micromips]) 8548#define JALR_FMT (jalr_fmt[mips_opts.micromips]) 8549#define LUI_FMT (lui_fmt[mips_opts.micromips]) 8550#define MEM12_FMT (mem12_fmt[mips_opts.micromips]) 8551#define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \ 8552 : mem12_fmt[mips_opts.micromips]) 8553#define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32]) 8554#define SHFT_FMT (shft_fmt[mips_opts.micromips]) 8555#define TRAP_FMT (trap_fmt[mips_opts.micromips]) 8556 8557/* Read a macro's relocation codes from *ARGS and store them in *R. 8558 The first argument in *ARGS will be either the code for a single 8559 relocation or -1 followed by the three codes that make up a 8560 composite relocation. */ 8561 8562static void 8563macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) 8564{ 8565 int i, next; 8566 8567 next = va_arg (*args, int); 8568 if (next >= 0) 8569 r[0] = (bfd_reloc_code_real_type) next; 8570 else 8571 { 8572 for (i = 0; i < 3; i++) 8573 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); 8574 /* This function is only used for 16-bit relocation fields. 8575 To make the macro code simpler, treat an unrelocated value 8576 in the same way as BFD_RELOC_LO16. */ 8577 if (r[0] == BFD_RELOC_UNUSED) 8578 r[0] = BFD_RELOC_LO16; 8579 } 8580} 8581 8582/* Build an instruction created by a macro expansion. This is passed 8583 a pointer to the count of instructions created so far, an 8584 expression, the name of the instruction to build, an operand format 8585 string, and corresponding arguments. */ 8586 8587static void 8588macro_build (expressionS *ep, const char *name, const char *fmt, ...) 8589{ 8590 const struct mips_opcode *mo = NULL; 8591 bfd_reloc_code_real_type r[3]; 8592 const struct mips_opcode *amo; 8593 const struct mips_operand *operand; 8594 struct hash_control *hash; 8595 struct mips_cl_insn insn; 8596 va_list args; 8597 unsigned int uval; 8598 8599 va_start (args, fmt); 8600 8601 if (mips_opts.mips16) 8602 { 8603 mips16_macro_build (ep, name, fmt, &args); 8604 va_end (args); 8605 return; 8606 } 8607 8608 r[0] = BFD_RELOC_UNUSED; 8609 r[1] = BFD_RELOC_UNUSED; 8610 r[2] = BFD_RELOC_UNUSED; 8611 hash = mips_opts.micromips ? micromips_op_hash : op_hash; 8612 amo = (struct mips_opcode *) hash_find (hash, name); 8613 gas_assert (amo); 8614 gas_assert (strcmp (name, amo->name) == 0); 8615 8616 do 8617 { 8618 /* Search until we get a match for NAME. It is assumed here that 8619 macros will never generate MDMX, MIPS-3D, or MT instructions. 8620 We try to match an instruction that fulfils the branch delay 8621 slot instruction length requirement (if any) of the previous 8622 instruction. While doing this we record the first instruction 8623 seen that matches all the other conditions and use it anyway 8624 if the requirement cannot be met; we will issue an appropriate 8625 warning later on. */ 8626 if (strcmp (fmt, amo->args) == 0 8627 && amo->pinfo != INSN_MACRO 8628 && is_opcode_valid (amo) 8629 && is_size_valid (amo)) 8630 { 8631 if (is_delay_slot_valid (amo)) 8632 { 8633 mo = amo; 8634 break; 8635 } 8636 else if (!mo) 8637 mo = amo; 8638 } 8639 8640 ++amo; 8641 gas_assert (amo->name); 8642 } 8643 while (strcmp (name, amo->name) == 0); 8644 8645 gas_assert (mo); 8646 create_insn (&insn, mo); 8647 for (; *fmt; ++fmt) 8648 { 8649 switch (*fmt) 8650 { 8651 case ',': 8652 case '(': 8653 case ')': 8654 case 'z': 8655 break; 8656 8657 case 'i': 8658 case 'j': 8659 macro_read_relocs (&args, r); 8660 gas_assert (*r == BFD_RELOC_GPREL16 8661 || *r == BFD_RELOC_MIPS_HIGHER 8662 || *r == BFD_RELOC_HI16_S 8663 || *r == BFD_RELOC_LO16 8664 || *r == BFD_RELOC_MIPS_GOT_OFST); 8665 break; 8666 8667 case 'o': 8668 macro_read_relocs (&args, r); 8669 break; 8670 8671 case 'u': 8672 macro_read_relocs (&args, r); 8673 gas_assert (ep != NULL 8674 && (ep->X_op == O_constant 8675 || (ep->X_op == O_symbol 8676 && (*r == BFD_RELOC_MIPS_HIGHEST 8677 || *r == BFD_RELOC_HI16_S 8678 || *r == BFD_RELOC_HI16 8679 || *r == BFD_RELOC_GPREL16 8680 || *r == BFD_RELOC_MIPS_GOT_HI16 8681 || *r == BFD_RELOC_MIPS_CALL_HI16)))); 8682 break; 8683 8684 case 'p': 8685 gas_assert (ep != NULL); 8686 8687 /* 8688 * This allows macro() to pass an immediate expression for 8689 * creating short branches without creating a symbol. 8690 * 8691 * We don't allow branch relaxation for these branches, as 8692 * they should only appear in ".set nomacro" anyway. 8693 */ 8694 if (ep->X_op == O_constant) 8695 { 8696 /* For microMIPS we always use relocations for branches. 8697 So we should not resolve immediate values. */ 8698 gas_assert (!mips_opts.micromips); 8699 8700 if ((ep->X_add_number & 3) != 0) 8701 as_bad (_("branch to misaligned address (0x%lx)"), 8702 (unsigned long) ep->X_add_number); 8703 if ((ep->X_add_number + 0x20000) & ~0x3ffff) 8704 as_bad (_("branch address range overflow (0x%lx)"), 8705 (unsigned long) ep->X_add_number); 8706 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; 8707 ep = NULL; 8708 } 8709 else 8710 *r = BFD_RELOC_16_PCREL_S2; 8711 break; 8712 8713 case 'a': 8714 gas_assert (ep != NULL); 8715 *r = BFD_RELOC_MIPS_JMP; 8716 break; 8717 8718 default: 8719 operand = (mips_opts.micromips 8720 ? decode_micromips_operand (fmt) 8721 : decode_mips_operand (fmt)); 8722 if (!operand) 8723 abort (); 8724 8725 uval = va_arg (args, int); 8726 if (operand->type == OP_CLO_CLZ_DEST) 8727 uval |= (uval << 5); 8728 insn_insert_operand (&insn, operand, uval); 8729 8730 if (*fmt == '+' || *fmt == 'm' || *fmt == '-') 8731 ++fmt; 8732 break; 8733 } 8734 } 8735 va_end (args); 8736 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); 8737 8738 append_insn (&insn, ep, r, TRUE); 8739} 8740 8741static void 8742mips16_macro_build (expressionS *ep, const char *name, const char *fmt, 8743 va_list *args) 8744{ 8745 struct mips_opcode *mo; 8746 struct mips_cl_insn insn; 8747 const struct mips_operand *operand; 8748 bfd_reloc_code_real_type r[3] 8749 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; 8750 8751 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); 8752 gas_assert (mo); 8753 gas_assert (strcmp (name, mo->name) == 0); 8754 8755 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) 8756 { 8757 ++mo; 8758 gas_assert (mo->name); 8759 gas_assert (strcmp (name, mo->name) == 0); 8760 } 8761 8762 create_insn (&insn, mo); 8763 for (; *fmt; ++fmt) 8764 { 8765 int c; 8766 8767 c = *fmt; 8768 switch (c) 8769 { 8770 case ',': 8771 case '(': 8772 case ')': 8773 break; 8774 8775 case '.': 8776 case 'S': 8777 case 'P': 8778 case 'R': 8779 break; 8780 8781 case '<': 8782 case '5': 8783 case 'F': 8784 case 'H': 8785 case 'W': 8786 case 'D': 8787 case 'j': 8788 case '8': 8789 case 'V': 8790 case 'C': 8791 case 'U': 8792 case 'k': 8793 case 'K': 8794 case 'p': 8795 case 'q': 8796 { 8797 offsetT value; 8798 8799 gas_assert (ep != NULL); 8800 8801 if (ep->X_op != O_constant) 8802 *r = (int) BFD_RELOC_UNUSED + c; 8803 else if (calculate_reloc (*r, ep->X_add_number, &value)) 8804 { 8805 mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode); 8806 ep = NULL; 8807 *r = BFD_RELOC_UNUSED; 8808 } 8809 } 8810 break; 8811 8812 default: 8813 operand = decode_mips16_operand (c, FALSE); 8814 if (!operand) 8815 abort (); 8816 8817 insn_insert_operand (&insn, operand, va_arg (*args, int)); 8818 break; 8819 } 8820 } 8821 8822 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); 8823 8824 append_insn (&insn, ep, r, TRUE); 8825} 8826 8827/* 8828 * Generate a "jalr" instruction with a relocation hint to the called 8829 * function. This occurs in NewABI PIC code. 8830 */ 8831static void 8832macro_build_jalr (expressionS *ep, int cprestore) 8833{ 8834 static const bfd_reloc_code_real_type jalr_relocs[2] 8835 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR }; 8836 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips]; 8837 const char *jalr; 8838 char *f = NULL; 8839 8840 if (MIPS_JALR_HINT_P (ep)) 8841 { 8842 frag_grow (8); 8843 f = frag_more (0); 8844 } 8845 if (mips_opts.micromips) 8846 { 8847 jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32 8848 ? "jalr" : "jalrs"); 8849 if (MIPS_JALR_HINT_P (ep) 8850 || mips_opts.insn32 8851 || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) 8852 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG); 8853 else 8854 macro_build (NULL, jalr, "mj", PIC_CALL_REG); 8855 } 8856 else 8857 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); 8858 if (MIPS_JALR_HINT_P (ep)) 8859 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc); 8860} 8861 8862/* 8863 * Generate a "lui" instruction. 8864 */ 8865static void 8866macro_build_lui (expressionS *ep, int regnum) 8867{ 8868 gas_assert (! mips_opts.mips16); 8869 8870 if (ep->X_op != O_constant) 8871 { 8872 gas_assert (ep->X_op == O_symbol); 8873 /* _gp_disp is a special case, used from s_cpload. 8874 __gnu_local_gp is used if mips_no_shared. */ 8875 gas_assert (mips_pic == NO_PIC 8876 || (! HAVE_NEWABI 8877 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) 8878 || (! mips_in_shared 8879 && strcmp (S_GET_NAME (ep->X_add_symbol), 8880 "__gnu_local_gp") == 0)); 8881 } 8882 8883 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S); 8884} 8885 8886/* Generate a sequence of instructions to do a load or store from a constant 8887 offset off of a base register (breg) into/from a target register (treg), 8888 using AT if necessary. */ 8889static void 8890macro_build_ldst_constoffset (expressionS *ep, const char *op, 8891 int treg, int breg, int dbl) 8892{ 8893 gas_assert (ep->X_op == O_constant); 8894 8895 /* Sign-extending 32-bit constants makes their handling easier. */ 8896 if (!dbl) 8897 normalize_constant_expr (ep); 8898 8899 /* Right now, this routine can only handle signed 32-bit constants. */ 8900 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) 8901 as_warn (_("operand overflow")); 8902 8903 if (IS_SEXT_16BIT_NUM(ep->X_add_number)) 8904 { 8905 /* Signed 16-bit offset will fit in the op. Easy! */ 8906 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); 8907 } 8908 else 8909 { 8910 /* 32-bit offset, need multiple instructions and AT, like: 8911 lui $tempreg,const_hi (BFD_RELOC_HI16_S) 8912 addu $tempreg,$tempreg,$breg 8913 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) 8914 to handle the complete offset. */ 8915 macro_build_lui (ep, AT); 8916 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); 8917 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); 8918 8919 if (!mips_opts.at) 8920 as_bad (_("macro used $at after \".set noat\"")); 8921 } 8922} 8923 8924/* set_at() 8925 * Generates code to set the $at register to true (one) 8926 * if reg is less than the immediate expression. 8927 */ 8928static void 8929set_at (int reg, int unsignedp) 8930{ 8931 if (imm_expr.X_add_number >= -0x8000 8932 && imm_expr.X_add_number < 0x8000) 8933 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", 8934 AT, reg, BFD_RELOC_LO16); 8935 else 8936 { 8937 load_register (AT, &imm_expr, GPR_SIZE == 64); 8938 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); 8939 } 8940} 8941 8942/* Count the leading zeroes by performing a binary chop. This is a 8943 bulky bit of source, but performance is a LOT better for the 8944 majority of values than a simple loop to count the bits: 8945 for (lcnt = 0; (lcnt < 32); lcnt++) 8946 if ((v) & (1 << (31 - lcnt))) 8947 break; 8948 However it is not code size friendly, and the gain will drop a bit 8949 on certain cached systems. 8950*/ 8951#define COUNT_TOP_ZEROES(v) \ 8952 (((v) & ~0xffff) == 0 \ 8953 ? ((v) & ~0xff) == 0 \ 8954 ? ((v) & ~0xf) == 0 \ 8955 ? ((v) & ~0x3) == 0 \ 8956 ? ((v) & ~0x1) == 0 \ 8957 ? !(v) \ 8958 ? 32 \ 8959 : 31 \ 8960 : 30 \ 8961 : ((v) & ~0x7) == 0 \ 8962 ? 29 \ 8963 : 28 \ 8964 : ((v) & ~0x3f) == 0 \ 8965 ? ((v) & ~0x1f) == 0 \ 8966 ? 27 \ 8967 : 26 \ 8968 : ((v) & ~0x7f) == 0 \ 8969 ? 25 \ 8970 : 24 \ 8971 : ((v) & ~0xfff) == 0 \ 8972 ? ((v) & ~0x3ff) == 0 \ 8973 ? ((v) & ~0x1ff) == 0 \ 8974 ? 23 \ 8975 : 22 \ 8976 : ((v) & ~0x7ff) == 0 \ 8977 ? 21 \ 8978 : 20 \ 8979 : ((v) & ~0x3fff) == 0 \ 8980 ? ((v) & ~0x1fff) == 0 \ 8981 ? 19 \ 8982 : 18 \ 8983 : ((v) & ~0x7fff) == 0 \ 8984 ? 17 \ 8985 : 16 \ 8986 : ((v) & ~0xffffff) == 0 \ 8987 ? ((v) & ~0xfffff) == 0 \ 8988 ? ((v) & ~0x3ffff) == 0 \ 8989 ? ((v) & ~0x1ffff) == 0 \ 8990 ? 15 \ 8991 : 14 \ 8992 : ((v) & ~0x7ffff) == 0 \ 8993 ? 13 \ 8994 : 12 \ 8995 : ((v) & ~0x3fffff) == 0 \ 8996 ? ((v) & ~0x1fffff) == 0 \ 8997 ? 11 \ 8998 : 10 \ 8999 : ((v) & ~0x7fffff) == 0 \ 9000 ? 9 \ 9001 : 8 \ 9002 : ((v) & ~0xfffffff) == 0 \ 9003 ? ((v) & ~0x3ffffff) == 0 \ 9004 ? ((v) & ~0x1ffffff) == 0 \ 9005 ? 7 \ 9006 : 6 \ 9007 : ((v) & ~0x7ffffff) == 0 \ 9008 ? 5 \ 9009 : 4 \ 9010 : ((v) & ~0x3fffffff) == 0 \ 9011 ? ((v) & ~0x1fffffff) == 0 \ 9012 ? 3 \ 9013 : 2 \ 9014 : ((v) & ~0x7fffffff) == 0 \ 9015 ? 1 \ 9016 : 0) 9017 9018/* load_register() 9019 * This routine generates the least number of instructions necessary to load 9020 * an absolute expression value into a register. 9021 */ 9022static void 9023load_register (int reg, expressionS *ep, int dbl) 9024{ 9025 int freg; 9026 expressionS hi32, lo32; 9027 9028 if (ep->X_op != O_big) 9029 { 9030 gas_assert (ep->X_op == O_constant); 9031 9032 /* Sign-extending 32-bit constants makes their handling easier. */ 9033 if (!dbl) 9034 normalize_constant_expr (ep); 9035 9036 if (IS_SEXT_16BIT_NUM (ep->X_add_number)) 9037 { 9038 /* We can handle 16 bit signed values with an addiu to 9039 $zero. No need to ever use daddiu here, since $zero and 9040 the result are always correct in 32 bit mode. */ 9041 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); 9042 return; 9043 } 9044 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) 9045 { 9046 /* We can handle 16 bit unsigned values with an ori to 9047 $zero. */ 9048 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); 9049 return; 9050 } 9051 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) 9052 { 9053 /* 32 bit values require an lui. */ 9054 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16); 9055 if ((ep->X_add_number & 0xffff) != 0) 9056 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); 9057 return; 9058 } 9059 } 9060 9061 /* The value is larger than 32 bits. */ 9062 9063 if (!dbl || GPR_SIZE == 32) 9064 { 9065 char value[32]; 9066 9067 sprintf_vma (value, ep->X_add_number); 9068 as_bad (_("number (0x%s) larger than 32 bits"), value); 9069 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); 9070 return; 9071 } 9072 9073 if (ep->X_op != O_big) 9074 { 9075 hi32 = *ep; 9076 hi32.X_add_number = (valueT) hi32.X_add_number >> 16; 9077 hi32.X_add_number = (valueT) hi32.X_add_number >> 16; 9078 hi32.X_add_number &= 0xffffffff; 9079 lo32 = *ep; 9080 lo32.X_add_number &= 0xffffffff; 9081 } 9082 else 9083 { 9084 gas_assert (ep->X_add_number > 2); 9085 if (ep->X_add_number == 3) 9086 generic_bignum[3] = 0; 9087 else if (ep->X_add_number > 4) 9088 as_bad (_("number larger than 64 bits")); 9089 lo32.X_op = O_constant; 9090 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); 9091 hi32.X_op = O_constant; 9092 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); 9093 } 9094 9095 if (hi32.X_add_number == 0) 9096 freg = 0; 9097 else 9098 { 9099 int shift, bit; 9100 unsigned long hi, lo; 9101 9102 if (hi32.X_add_number == (offsetT) 0xffffffff) 9103 { 9104 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) 9105 { 9106 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); 9107 return; 9108 } 9109 if (lo32.X_add_number & 0x80000000) 9110 { 9111 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); 9112 if (lo32.X_add_number & 0xffff) 9113 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); 9114 return; 9115 } 9116 } 9117 9118 /* Check for 16bit shifted constant. We know that hi32 is 9119 non-zero, so start the mask on the first bit of the hi32 9120 value. */ 9121 shift = 17; 9122 do 9123 { 9124 unsigned long himask, lomask; 9125 9126 if (shift < 32) 9127 { 9128 himask = 0xffff >> (32 - shift); 9129 lomask = (0xffff << shift) & 0xffffffff; 9130 } 9131 else 9132 { 9133 himask = 0xffff << (shift - 32); 9134 lomask = 0; 9135 } 9136 if ((hi32.X_add_number & ~(offsetT) himask) == 0 9137 && (lo32.X_add_number & ~(offsetT) lomask) == 0) 9138 { 9139 expressionS tmp; 9140 9141 tmp.X_op = O_constant; 9142 if (shift < 32) 9143 tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) 9144 | (lo32.X_add_number >> shift)); 9145 else 9146 tmp.X_add_number = hi32.X_add_number >> (shift - 32); 9147 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); 9148 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT, 9149 reg, reg, (shift >= 32) ? shift - 32 : shift); 9150 return; 9151 } 9152 ++shift; 9153 } 9154 while (shift <= (64 - 16)); 9155 9156 /* Find the bit number of the lowest one bit, and store the 9157 shifted value in hi/lo. */ 9158 hi = (unsigned long) (hi32.X_add_number & 0xffffffff); 9159 lo = (unsigned long) (lo32.X_add_number & 0xffffffff); 9160 if (lo != 0) 9161 { 9162 bit = 0; 9163 while ((lo & 1) == 0) 9164 { 9165 lo >>= 1; 9166 ++bit; 9167 } 9168 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); 9169 hi >>= bit; 9170 } 9171 else 9172 { 9173 bit = 32; 9174 while ((hi & 1) == 0) 9175 { 9176 hi >>= 1; 9177 ++bit; 9178 } 9179 lo = hi; 9180 hi = 0; 9181 } 9182 9183 /* Optimize if the shifted value is a (power of 2) - 1. */ 9184 if ((hi == 0 && ((lo + 1) & lo) == 0) 9185 || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) 9186 { 9187 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); 9188 if (shift != 0) 9189 { 9190 expressionS tmp; 9191 9192 /* This instruction will set the register to be all 9193 ones. */ 9194 tmp.X_op = O_constant; 9195 tmp.X_add_number = (offsetT) -1; 9196 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); 9197 if (bit != 0) 9198 { 9199 bit += shift; 9200 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT, 9201 reg, reg, (bit >= 32) ? bit - 32 : bit); 9202 } 9203 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT, 9204 reg, reg, (shift >= 32) ? shift - 32 : shift); 9205 return; 9206 } 9207 } 9208 9209 /* Sign extend hi32 before calling load_register, because we can 9210 generally get better code when we load a sign extended value. */ 9211 if ((hi32.X_add_number & 0x80000000) != 0) 9212 hi32.X_add_number |= ~(offsetT) 0xffffffff; 9213 load_register (reg, &hi32, 0); 9214 freg = reg; 9215 } 9216 if ((lo32.X_add_number & 0xffff0000) == 0) 9217 { 9218 if (freg != 0) 9219 { 9220 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0); 9221 freg = reg; 9222 } 9223 } 9224 else 9225 { 9226 expressionS mid16; 9227 9228 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) 9229 { 9230 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); 9231 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0); 9232 return; 9233 } 9234 9235 if (freg != 0) 9236 { 9237 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16); 9238 freg = reg; 9239 } 9240 mid16 = lo32; 9241 mid16.X_add_number >>= 16; 9242 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); 9243 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); 9244 freg = reg; 9245 } 9246 if ((lo32.X_add_number & 0xffff) != 0) 9247 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); 9248} 9249 9250static inline void 9251load_delay_nop (void) 9252{ 9253 if (!gpr_interlocks) 9254 macro_build (NULL, "nop", ""); 9255} 9256 9257/* Load an address into a register. */ 9258 9259static void 9260load_address (int reg, expressionS *ep, int *used_at) 9261{ 9262 if (ep->X_op != O_constant 9263 && ep->X_op != O_symbol) 9264 { 9265 as_bad (_("expression too complex")); 9266 ep->X_op = O_constant; 9267 } 9268 9269 if (ep->X_op == O_constant) 9270 { 9271 load_register (reg, ep, HAVE_64BIT_ADDRESSES); 9272 return; 9273 } 9274 9275 if (mips_pic == NO_PIC) 9276 { 9277 /* If this is a reference to a GP relative symbol, we want 9278 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) 9279 Otherwise we want 9280 lui $reg,<sym> (BFD_RELOC_HI16_S) 9281 addiu $reg,$reg,<sym> (BFD_RELOC_LO16) 9282 If we have an addend, we always use the latter form. 9283 9284 With 64bit address space and a usable $at we want 9285 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) 9286 lui $at,<sym> (BFD_RELOC_HI16_S) 9287 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) 9288 daddiu $at,<sym> (BFD_RELOC_LO16) 9289 dsll32 $reg,0 9290 daddu $reg,$reg,$at 9291 9292 If $at is already in use, we use a path which is suboptimal 9293 on superscalar processors. 9294 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) 9295 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) 9296 dsll $reg,16 9297 daddiu $reg,<sym> (BFD_RELOC_HI16_S) 9298 dsll $reg,16 9299 daddiu $reg,<sym> (BFD_RELOC_LO16) 9300 9301 For GP relative symbols in 64bit address space we can use 9302 the same sequence as in 32bit address space. */ 9303 if (HAVE_64BIT_SYMBOLS) 9304 { 9305 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET 9306 && !nopic_need_relax (ep->X_add_symbol, 1)) 9307 { 9308 relax_start (ep->X_add_symbol); 9309 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, 9310 mips_gp_register, BFD_RELOC_GPREL16); 9311 relax_switch (); 9312 } 9313 9314 if (*used_at == 0 && mips_opts.at) 9315 { 9316 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); 9317 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S); 9318 macro_build (ep, "daddiu", "t,r,j", reg, reg, 9319 BFD_RELOC_MIPS_HIGHER); 9320 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); 9321 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0); 9322 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); 9323 *used_at = 1; 9324 } 9325 else 9326 { 9327 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); 9328 macro_build (ep, "daddiu", "t,r,j", reg, reg, 9329 BFD_RELOC_MIPS_HIGHER); 9330 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); 9331 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); 9332 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); 9333 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); 9334 } 9335 9336 if (mips_relax.sequence) 9337 relax_end (); 9338 } 9339 else 9340 { 9341 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET 9342 && !nopic_need_relax (ep->X_add_symbol, 1)) 9343 { 9344 relax_start (ep->X_add_symbol); 9345 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, 9346 mips_gp_register, BFD_RELOC_GPREL16); 9347 relax_switch (); 9348 } 9349 macro_build_lui (ep, reg); 9350 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", 9351 reg, reg, BFD_RELOC_LO16); 9352 if (mips_relax.sequence) 9353 relax_end (); 9354 } 9355 } 9356 else if (!mips_big_got) 9357 { 9358 expressionS ex; 9359 9360 /* If this is a reference to an external symbol, we want 9361 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 9362 Otherwise we want 9363 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 9364 nop 9365 addiu $reg,$reg,<sym> (BFD_RELOC_LO16) 9366 If there is a constant, it must be added in after. 9367 9368 If we have NewABI, we want 9369 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) 9370 unless we're referencing a global symbol with a non-zero 9371 offset, in which case cst must be added separately. */ 9372 if (HAVE_NEWABI) 9373 { 9374 if (ep->X_add_number) 9375 { 9376 ex.X_add_number = ep->X_add_number; 9377 ep->X_add_number = 0; 9378 relax_start (ep->X_add_symbol); 9379 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, 9380 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); 9381 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) 9382 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 9383 ex.X_op = O_constant; 9384 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", 9385 reg, reg, BFD_RELOC_LO16); 9386 ep->X_add_number = ex.X_add_number; 9387 relax_switch (); 9388 } 9389 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, 9390 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); 9391 if (mips_relax.sequence) 9392 relax_end (); 9393 } 9394 else 9395 { 9396 ex.X_add_number = ep->X_add_number; 9397 ep->X_add_number = 0; 9398 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, 9399 BFD_RELOC_MIPS_GOT16, mips_gp_register); 9400 load_delay_nop (); 9401 relax_start (ep->X_add_symbol); 9402 relax_switch (); 9403 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, 9404 BFD_RELOC_LO16); 9405 relax_end (); 9406 9407 if (ex.X_add_number != 0) 9408 { 9409 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) 9410 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 9411 ex.X_op = O_constant; 9412 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", 9413 reg, reg, BFD_RELOC_LO16); 9414 } 9415 } 9416 } 9417 else if (mips_big_got) 9418 { 9419 expressionS ex; 9420 9421 /* This is the large GOT case. If this is a reference to an 9422 external symbol, we want 9423 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 9424 addu $reg,$reg,$gp 9425 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) 9426 9427 Otherwise, for a reference to a local symbol in old ABI, we want 9428 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 9429 nop 9430 addiu $reg,$reg,<sym> (BFD_RELOC_LO16) 9431 If there is a constant, it must be added in after. 9432 9433 In the NewABI, for local symbols, with or without offsets, we want: 9434 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) 9435 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) 9436 */ 9437 if (HAVE_NEWABI) 9438 { 9439 ex.X_add_number = ep->X_add_number; 9440 ep->X_add_number = 0; 9441 relax_start (ep->X_add_symbol); 9442 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); 9443 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 9444 reg, reg, mips_gp_register); 9445 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", 9446 reg, BFD_RELOC_MIPS_GOT_LO16, reg); 9447 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) 9448 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 9449 else if (ex.X_add_number) 9450 { 9451 ex.X_op = O_constant; 9452 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, 9453 BFD_RELOC_LO16); 9454 } 9455 9456 ep->X_add_number = ex.X_add_number; 9457 relax_switch (); 9458 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, 9459 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); 9460 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, 9461 BFD_RELOC_MIPS_GOT_OFST); 9462 relax_end (); 9463 } 9464 else 9465 { 9466 ex.X_add_number = ep->X_add_number; 9467 ep->X_add_number = 0; 9468 relax_start (ep->X_add_symbol); 9469 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); 9470 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 9471 reg, reg, mips_gp_register); 9472 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", 9473 reg, BFD_RELOC_MIPS_GOT_LO16, reg); 9474 relax_switch (); 9475 if (reg_needs_delay (mips_gp_register)) 9476 { 9477 /* We need a nop before loading from $gp. This special 9478 check is required because the lui which starts the main 9479 instruction stream does not refer to $gp, and so will not 9480 insert the nop which may be required. */ 9481 macro_build (NULL, "nop", ""); 9482 } 9483 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, 9484 BFD_RELOC_MIPS_GOT16, mips_gp_register); 9485 load_delay_nop (); 9486 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, 9487 BFD_RELOC_LO16); 9488 relax_end (); 9489 9490 if (ex.X_add_number != 0) 9491 { 9492 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) 9493 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 9494 ex.X_op = O_constant; 9495 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, 9496 BFD_RELOC_LO16); 9497 } 9498 } 9499 } 9500 else 9501 abort (); 9502 9503 if (!mips_opts.at && *used_at == 1) 9504 as_bad (_("macro used $at after \".set noat\"")); 9505} 9506 9507/* Move the contents of register SOURCE into register DEST. */ 9508 9509static void 9510move_register (int dest, int source) 9511{ 9512 /* Prefer to use a 16-bit microMIPS instruction unless the previous 9513 instruction specifically requires a 32-bit one. */ 9514 if (mips_opts.micromips 9515 && !mips_opts.insn32 9516 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) 9517 macro_build (NULL, "move", "mp,mj", dest, source); 9518 else 9519 macro_build (NULL, "or", "d,v,t", dest, source, 0); 9520} 9521 9522/* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where 9523 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. 9524 The two alternatives are: 9525 9526 Global symbol Local sybmol 9527 ------------- ------------ 9528 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) 9529 ... ... 9530 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) 9531 9532 load_got_offset emits the first instruction and add_got_offset 9533 emits the second for a 16-bit offset or add_got_offset_hilo emits 9534 a sequence to add a 32-bit offset using a scratch register. */ 9535 9536static void 9537load_got_offset (int dest, expressionS *local) 9538{ 9539 expressionS global; 9540 9541 global = *local; 9542 global.X_add_number = 0; 9543 9544 relax_start (local->X_add_symbol); 9545 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, 9546 BFD_RELOC_MIPS_GOT16, mips_gp_register); 9547 relax_switch (); 9548 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, 9549 BFD_RELOC_MIPS_GOT16, mips_gp_register); 9550 relax_end (); 9551} 9552 9553static void 9554add_got_offset (int dest, expressionS *local) 9555{ 9556 expressionS global; 9557 9558 global.X_op = O_constant; 9559 global.X_op_symbol = NULL; 9560 global.X_add_symbol = NULL; 9561 global.X_add_number = local->X_add_number; 9562 9563 relax_start (local->X_add_symbol); 9564 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", 9565 dest, dest, BFD_RELOC_LO16); 9566 relax_switch (); 9567 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); 9568 relax_end (); 9569} 9570 9571static void 9572add_got_offset_hilo (int dest, expressionS *local, int tmp) 9573{ 9574 expressionS global; 9575 int hold_mips_optimize; 9576 9577 global.X_op = O_constant; 9578 global.X_op_symbol = NULL; 9579 global.X_add_symbol = NULL; 9580 global.X_add_number = local->X_add_number; 9581 9582 relax_start (local->X_add_symbol); 9583 load_register (tmp, &global, HAVE_64BIT_ADDRESSES); 9584 relax_switch (); 9585 /* Set mips_optimize around the lui instruction to avoid 9586 inserting an unnecessary nop after the lw. */ 9587 hold_mips_optimize = mips_optimize; 9588 mips_optimize = 2; 9589 macro_build_lui (&global, tmp); 9590 mips_optimize = hold_mips_optimize; 9591 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); 9592 relax_end (); 9593 9594 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); 9595} 9596 9597/* Emit a sequence of instructions to emulate a branch likely operation. 9598 BR is an ordinary branch corresponding to one to be emulated. BRNEG 9599 is its complementing branch with the original condition negated. 9600 CALL is set if the original branch specified the link operation. 9601 EP, FMT, SREG and TREG specify the usual macro_build() parameters. 9602 9603 Code like this is produced in the noreorder mode: 9604 9605 BRNEG <args>, 1f 9606 nop 9607 b <sym> 9608 delay slot (executed only if branch taken) 9609 1: 9610 9611 or, if CALL is set: 9612 9613 BRNEG <args>, 1f 9614 nop 9615 bal <sym> 9616 delay slot (executed only if branch taken) 9617 1: 9618 9619 In the reorder mode the delay slot would be filled with a nop anyway, 9620 so code produced is simply: 9621 9622 BR <args>, <sym> 9623 nop 9624 9625 This function is used when producing code for the microMIPS ASE that 9626 does not implement branch likely instructions in hardware. */ 9627 9628static void 9629macro_build_branch_likely (const char *br, const char *brneg, 9630 int call, expressionS *ep, const char *fmt, 9631 unsigned int sreg, unsigned int treg) 9632{ 9633 int noreorder = mips_opts.noreorder; 9634 expressionS expr1; 9635 9636 gas_assert (mips_opts.micromips); 9637 start_noreorder (); 9638 if (noreorder) 9639 { 9640 micromips_label_expr (&expr1); 9641 macro_build (&expr1, brneg, fmt, sreg, treg); 9642 macro_build (NULL, "nop", ""); 9643 macro_build (ep, call ? "bal" : "b", "p"); 9644 9645 /* Set to true so that append_insn adds a label. */ 9646 emit_branch_likely_macro = TRUE; 9647 } 9648 else 9649 { 9650 macro_build (ep, br, fmt, sreg, treg); 9651 macro_build (NULL, "nop", ""); 9652 } 9653 end_noreorder (); 9654} 9655 9656/* Emit a coprocessor branch-likely macro specified by TYPE, using CC as 9657 the condition code tested. EP specifies the branch target. */ 9658 9659static void 9660macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc) 9661{ 9662 const int call = 0; 9663 const char *brneg; 9664 const char *br; 9665 9666 switch (type) 9667 { 9668 case M_BC1FL: 9669 br = "bc1f"; 9670 brneg = "bc1t"; 9671 break; 9672 case M_BC1TL: 9673 br = "bc1t"; 9674 brneg = "bc1f"; 9675 break; 9676 case M_BC2FL: 9677 br = "bc2f"; 9678 brneg = "bc2t"; 9679 break; 9680 case M_BC2TL: 9681 br = "bc2t"; 9682 brneg = "bc2f"; 9683 break; 9684 default: 9685 abort (); 9686 } 9687 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO); 9688} 9689 9690/* Emit a two-argument branch macro specified by TYPE, using SREG as 9691 the register tested. EP specifies the branch target. */ 9692 9693static void 9694macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg) 9695{ 9696 const char *brneg = NULL; 9697 const char *br; 9698 int call = 0; 9699 9700 switch (type) 9701 { 9702 case M_BGEZ: 9703 br = "bgez"; 9704 break; 9705 case M_BGEZL: 9706 br = mips_opts.micromips ? "bgez" : "bgezl"; 9707 brneg = "bltz"; 9708 break; 9709 case M_BGEZALL: 9710 gas_assert (mips_opts.micromips); 9711 br = mips_opts.insn32 ? "bgezal" : "bgezals"; 9712 brneg = "bltz"; 9713 call = 1; 9714 break; 9715 case M_BGTZ: 9716 br = "bgtz"; 9717 break; 9718 case M_BGTZL: 9719 br = mips_opts.micromips ? "bgtz" : "bgtzl"; 9720 brneg = "blez"; 9721 break; 9722 case M_BLEZ: 9723 br = "blez"; 9724 break; 9725 case M_BLEZL: 9726 br = mips_opts.micromips ? "blez" : "blezl"; 9727 brneg = "bgtz"; 9728 break; 9729 case M_BLTZ: 9730 br = "bltz"; 9731 break; 9732 case M_BLTZL: 9733 br = mips_opts.micromips ? "bltz" : "bltzl"; 9734 brneg = "bgez"; 9735 break; 9736 case M_BLTZALL: 9737 gas_assert (mips_opts.micromips); 9738 br = mips_opts.insn32 ? "bltzal" : "bltzals"; 9739 brneg = "bgez"; 9740 call = 1; 9741 break; 9742 default: 9743 abort (); 9744 } 9745 if (mips_opts.micromips && brneg) 9746 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO); 9747 else 9748 macro_build (ep, br, "s,p", sreg); 9749} 9750 9751/* Emit a three-argument branch macro specified by TYPE, using SREG and 9752 TREG as the registers tested. EP specifies the branch target. */ 9753 9754static void 9755macro_build_branch_rsrt (int type, expressionS *ep, 9756 unsigned int sreg, unsigned int treg) 9757{ 9758 const char *brneg = NULL; 9759 const int call = 0; 9760 const char *br; 9761 9762 switch (type) 9763 { 9764 case M_BEQ: 9765 case M_BEQ_I: 9766 br = "beq"; 9767 break; 9768 case M_BEQL: 9769 case M_BEQL_I: 9770 br = mips_opts.micromips ? "beq" : "beql"; 9771 brneg = "bne"; 9772 break; 9773 case M_BNE: 9774 case M_BNE_I: 9775 br = "bne"; 9776 break; 9777 case M_BNEL: 9778 case M_BNEL_I: 9779 br = mips_opts.micromips ? "bne" : "bnel"; 9780 brneg = "beq"; 9781 break; 9782 default: 9783 abort (); 9784 } 9785 if (mips_opts.micromips && brneg) 9786 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg); 9787 else 9788 macro_build (ep, br, "s,t,p", sreg, treg); 9789} 9790 9791/* Return the high part that should be loaded in order to make the low 9792 part of VALUE accessible using an offset of OFFBITS bits. */ 9793 9794static offsetT 9795offset_high_part (offsetT value, unsigned int offbits) 9796{ 9797 offsetT bias; 9798 addressT low_mask; 9799 9800 if (offbits == 0) 9801 return value; 9802 bias = 1 << (offbits - 1); 9803 low_mask = bias * 2 - 1; 9804 return (value + bias) & ~low_mask; 9805} 9806 9807/* Return true if the value stored in offset_expr and offset_reloc 9808 fits into a signed offset of OFFBITS bits. RANGE is the maximum 9809 amount that the caller wants to add without inducing overflow 9810 and ALIGN is the known alignment of the value in bytes. */ 9811 9812static bfd_boolean 9813small_offset_p (unsigned int range, unsigned int align, unsigned int offbits) 9814{ 9815 if (offbits == 16) 9816 { 9817 /* Accept any relocation operator if overflow isn't a concern. */ 9818 if (range < align && *offset_reloc != BFD_RELOC_UNUSED) 9819 return TRUE; 9820 9821 /* These relocations are guaranteed not to overflow in correct links. */ 9822 if (*offset_reloc == BFD_RELOC_MIPS_LITERAL 9823 || gprel16_reloc_p (*offset_reloc)) 9824 return TRUE; 9825 } 9826 if (offset_expr.X_op == O_constant 9827 && offset_high_part (offset_expr.X_add_number, offbits) == 0 9828 && offset_high_part (offset_expr.X_add_number + range, offbits) == 0) 9829 return TRUE; 9830 return FALSE; 9831} 9832 9833/* 9834 * Build macros 9835 * This routine implements the seemingly endless macro or synthesized 9836 * instructions and addressing modes in the mips assembly language. Many 9837 * of these macros are simple and are similar to each other. These could 9838 * probably be handled by some kind of table or grammar approach instead of 9839 * this verbose method. Others are not simple macros but are more like 9840 * optimizing code generation. 9841 * One interesting optimization is when several store macros appear 9842 * consecutively that would load AT with the upper half of the same address. 9843 * The ensuing load upper instructions are omitted. This implies some kind 9844 * of global optimization. We currently only optimize within a single macro. 9845 * For many of the load and store macros if the address is specified as a 9846 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we 9847 * first load register 'at' with zero and use it as the base register. The 9848 * mips assembler simply uses register $zero. Just one tiny optimization 9849 * we're missing. 9850 */ 9851static void 9852macro (struct mips_cl_insn *ip, char *str) 9853{ 9854 const struct mips_operand_array *operands; 9855 unsigned int breg, i; 9856 unsigned int tempreg; 9857 int mask; 9858 int used_at = 0; 9859 expressionS label_expr; 9860 expressionS expr1; 9861 expressionS *ep; 9862 const char *s; 9863 const char *s2; 9864 const char *fmt; 9865 int likely = 0; 9866 int coproc = 0; 9867 int offbits = 16; 9868 int call = 0; 9869 int jals = 0; 9870 int dbl = 0; 9871 int imm = 0; 9872 int ust = 0; 9873 int lp = 0; 9874 bfd_boolean large_offset; 9875 int off; 9876 int hold_mips_optimize; 9877 unsigned int align; 9878 unsigned int op[MAX_OPERANDS]; 9879 9880 gas_assert (! mips_opts.mips16); 9881 9882 operands = insn_operands (ip); 9883 for (i = 0; i < MAX_OPERANDS; i++) 9884 if (operands->operand[i]) 9885 op[i] = insn_extract_operand (ip, operands->operand[i]); 9886 else 9887 op[i] = -1; 9888 9889 mask = ip->insn_mo->mask; 9890 9891 label_expr.X_op = O_constant; 9892 label_expr.X_op_symbol = NULL; 9893 label_expr.X_add_symbol = NULL; 9894 label_expr.X_add_number = 0; 9895 9896 expr1.X_op = O_constant; 9897 expr1.X_op_symbol = NULL; 9898 expr1.X_add_symbol = NULL; 9899 expr1.X_add_number = 1; 9900 align = 1; 9901 9902 switch (mask) 9903 { 9904 case M_DABS: 9905 dbl = 1; 9906 /* Fall through. */ 9907 case M_ABS: 9908 /* bgez $a0,1f 9909 move v0,$a0 9910 sub v0,$zero,$a0 9911 1: 9912 */ 9913 9914 start_noreorder (); 9915 9916 if (mips_opts.micromips) 9917 micromips_label_expr (&label_expr); 9918 else 9919 label_expr.X_add_number = 8; 9920 macro_build (&label_expr, "bgez", "s,p", op[1]); 9921 if (op[0] == op[1]) 9922 macro_build (NULL, "nop", ""); 9923 else 9924 move_register (op[0], op[1]); 9925 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", op[0], 0, op[1]); 9926 if (mips_opts.micromips) 9927 micromips_add_label (); 9928 9929 end_noreorder (); 9930 break; 9931 9932 case M_ADD_I: 9933 s = "addi"; 9934 s2 = "add"; 9935 goto do_addi; 9936 case M_ADDU_I: 9937 s = "addiu"; 9938 s2 = "addu"; 9939 goto do_addi; 9940 case M_DADD_I: 9941 dbl = 1; 9942 s = "daddi"; 9943 s2 = "dadd"; 9944 if (!mips_opts.micromips) 9945 goto do_addi; 9946 if (imm_expr.X_add_number >= -0x200 9947 && imm_expr.X_add_number < 0x200) 9948 { 9949 macro_build (NULL, s, "t,r,.", op[0], op[1], 9950 (int) imm_expr.X_add_number); 9951 break; 9952 } 9953 goto do_addi_i; 9954 case M_DADDU_I: 9955 dbl = 1; 9956 s = "daddiu"; 9957 s2 = "daddu"; 9958 do_addi: 9959 if (imm_expr.X_add_number >= -0x8000 9960 && imm_expr.X_add_number < 0x8000) 9961 { 9962 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16); 9963 break; 9964 } 9965 do_addi_i: 9966 used_at = 1; 9967 load_register (AT, &imm_expr, dbl); 9968 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); 9969 break; 9970 9971 case M_AND_I: 9972 s = "andi"; 9973 s2 = "and"; 9974 goto do_bit; 9975 case M_OR_I: 9976 s = "ori"; 9977 s2 = "or"; 9978 goto do_bit; 9979 case M_NOR_I: 9980 s = ""; 9981 s2 = "nor"; 9982 goto do_bit; 9983 case M_XOR_I: 9984 s = "xori"; 9985 s2 = "xor"; 9986 do_bit: 9987 if (imm_expr.X_add_number >= 0 9988 && imm_expr.X_add_number < 0x10000) 9989 { 9990 if (mask != M_NOR_I) 9991 macro_build (&imm_expr, s, "t,r,i", op[0], op[1], BFD_RELOC_LO16); 9992 else 9993 { 9994 macro_build (&imm_expr, "ori", "t,r,i", 9995 op[0], op[1], BFD_RELOC_LO16); 9996 macro_build (NULL, "nor", "d,v,t", op[0], op[0], 0); 9997 } 9998 break; 9999 } 10000 10001 used_at = 1; 10002 load_register (AT, &imm_expr, GPR_SIZE == 64); 10003 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); 10004 break; 10005 10006 case M_BALIGN: 10007 switch (imm_expr.X_add_number) 10008 { 10009 case 0: 10010 macro_build (NULL, "nop", ""); 10011 break; 10012 case 2: 10013 macro_build (NULL, "packrl.ph", "d,s,t", op[0], op[0], op[1]); 10014 break; 10015 case 1: 10016 case 3: 10017 macro_build (NULL, "balign", "t,s,2", op[0], op[1], 10018 (int) imm_expr.X_add_number); 10019 break; 10020 default: 10021 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"), 10022 (unsigned long) imm_expr.X_add_number); 10023 break; 10024 } 10025 break; 10026 10027 case M_BC1FL: 10028 case M_BC1TL: 10029 case M_BC2FL: 10030 case M_BC2TL: 10031 gas_assert (mips_opts.micromips); 10032 macro_build_branch_ccl (mask, &offset_expr, 10033 EXTRACT_OPERAND (1, BCC, *ip)); 10034 break; 10035 10036 case M_BEQ_I: 10037 case M_BEQL_I: 10038 case M_BNE_I: 10039 case M_BNEL_I: 10040 if (imm_expr.X_add_number == 0) 10041 op[1] = 0; 10042 else 10043 { 10044 op[1] = AT; 10045 used_at = 1; 10046 load_register (op[1], &imm_expr, GPR_SIZE == 64); 10047 } 10048 /* Fall through. */ 10049 case M_BEQL: 10050 case M_BNEL: 10051 macro_build_branch_rsrt (mask, &offset_expr, op[0], op[1]); 10052 break; 10053 10054 case M_BGEL: 10055 likely = 1; 10056 /* Fall through. */ 10057 case M_BGE: 10058 if (op[1] == 0) 10059 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[0]); 10060 else if (op[0] == 0) 10061 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[1]); 10062 else 10063 { 10064 used_at = 1; 10065 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]); 10066 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, 10067 &offset_expr, AT, ZERO); 10068 } 10069 break; 10070 10071 case M_BGEZL: 10072 case M_BGEZALL: 10073 case M_BGTZL: 10074 case M_BLEZL: 10075 case M_BLTZL: 10076 case M_BLTZALL: 10077 macro_build_branch_rs (mask, &offset_expr, op[0]); 10078 break; 10079 10080 case M_BGTL_I: 10081 likely = 1; 10082 /* Fall through. */ 10083 case M_BGT_I: 10084 /* Check for > max integer. */ 10085 if (imm_expr.X_add_number >= GPR_SMAX) 10086 { 10087 do_false: 10088 /* Result is always false. */ 10089 if (! likely) 10090 macro_build (NULL, "nop", ""); 10091 else 10092 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO); 10093 break; 10094 } 10095 ++imm_expr.X_add_number; 10096 /* FALLTHROUGH */ 10097 case M_BGE_I: 10098 case M_BGEL_I: 10099 if (mask == M_BGEL_I) 10100 likely = 1; 10101 if (imm_expr.X_add_number == 0) 10102 { 10103 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, 10104 &offset_expr, op[0]); 10105 break; 10106 } 10107 if (imm_expr.X_add_number == 1) 10108 { 10109 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, 10110 &offset_expr, op[0]); 10111 break; 10112 } 10113 if (imm_expr.X_add_number <= GPR_SMIN) 10114 { 10115 do_true: 10116 /* result is always true */ 10117 as_warn (_("branch %s is always true"), ip->insn_mo->name); 10118 macro_build (&offset_expr, "b", "p"); 10119 break; 10120 } 10121 used_at = 1; 10122 set_at (op[0], 0); 10123 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, 10124 &offset_expr, AT, ZERO); 10125 break; 10126 10127 case M_BGEUL: 10128 likely = 1; 10129 /* Fall through. */ 10130 case M_BGEU: 10131 if (op[1] == 0) 10132 goto do_true; 10133 else if (op[0] == 0) 10134 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, 10135 &offset_expr, ZERO, op[1]); 10136 else 10137 { 10138 used_at = 1; 10139 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]); 10140 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, 10141 &offset_expr, AT, ZERO); 10142 } 10143 break; 10144 10145 case M_BGTUL_I: 10146 likely = 1; 10147 /* Fall through. */ 10148 case M_BGTU_I: 10149 if (op[0] == 0 10150 || (GPR_SIZE == 32 10151 && imm_expr.X_add_number == -1)) 10152 goto do_false; 10153 ++imm_expr.X_add_number; 10154 /* FALLTHROUGH */ 10155 case M_BGEU_I: 10156 case M_BGEUL_I: 10157 if (mask == M_BGEUL_I) 10158 likely = 1; 10159 if (imm_expr.X_add_number == 0) 10160 goto do_true; 10161 else if (imm_expr.X_add_number == 1) 10162 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, 10163 &offset_expr, op[0], ZERO); 10164 else 10165 { 10166 used_at = 1; 10167 set_at (op[0], 1); 10168 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, 10169 &offset_expr, AT, ZERO); 10170 } 10171 break; 10172 10173 case M_BGTL: 10174 likely = 1; 10175 /* Fall through. */ 10176 case M_BGT: 10177 if (op[1] == 0) 10178 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[0]); 10179 else if (op[0] == 0) 10180 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[1]); 10181 else 10182 { 10183 used_at = 1; 10184 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]); 10185 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, 10186 &offset_expr, AT, ZERO); 10187 } 10188 break; 10189 10190 case M_BGTUL: 10191 likely = 1; 10192 /* Fall through. */ 10193 case M_BGTU: 10194 if (op[1] == 0) 10195 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, 10196 &offset_expr, op[0], ZERO); 10197 else if (op[0] == 0) 10198 goto do_false; 10199 else 10200 { 10201 used_at = 1; 10202 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]); 10203 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, 10204 &offset_expr, AT, ZERO); 10205 } 10206 break; 10207 10208 case M_BLEL: 10209 likely = 1; 10210 /* Fall through. */ 10211 case M_BLE: 10212 if (op[1] == 0) 10213 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]); 10214 else if (op[0] == 0) 10215 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[1]); 10216 else 10217 { 10218 used_at = 1; 10219 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]); 10220 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, 10221 &offset_expr, AT, ZERO); 10222 } 10223 break; 10224 10225 case M_BLEL_I: 10226 likely = 1; 10227 /* Fall through. */ 10228 case M_BLE_I: 10229 if (imm_expr.X_add_number >= GPR_SMAX) 10230 goto do_true; 10231 ++imm_expr.X_add_number; 10232 /* FALLTHROUGH */ 10233 case M_BLT_I: 10234 case M_BLTL_I: 10235 if (mask == M_BLTL_I) 10236 likely = 1; 10237 if (imm_expr.X_add_number == 0) 10238 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]); 10239 else if (imm_expr.X_add_number == 1) 10240 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]); 10241 else 10242 { 10243 used_at = 1; 10244 set_at (op[0], 0); 10245 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, 10246 &offset_expr, AT, ZERO); 10247 } 10248 break; 10249 10250 case M_BLEUL: 10251 likely = 1; 10252 /* Fall through. */ 10253 case M_BLEU: 10254 if (op[1] == 0) 10255 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, 10256 &offset_expr, op[0], ZERO); 10257 else if (op[0] == 0) 10258 goto do_true; 10259 else 10260 { 10261 used_at = 1; 10262 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]); 10263 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, 10264 &offset_expr, AT, ZERO); 10265 } 10266 break; 10267 10268 case M_BLEUL_I: 10269 likely = 1; 10270 /* Fall through. */ 10271 case M_BLEU_I: 10272 if (op[0] == 0 10273 || (GPR_SIZE == 32 10274 && imm_expr.X_add_number == -1)) 10275 goto do_true; 10276 ++imm_expr.X_add_number; 10277 /* FALLTHROUGH */ 10278 case M_BLTU_I: 10279 case M_BLTUL_I: 10280 if (mask == M_BLTUL_I) 10281 likely = 1; 10282 if (imm_expr.X_add_number == 0) 10283 goto do_false; 10284 else if (imm_expr.X_add_number == 1) 10285 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, 10286 &offset_expr, op[0], ZERO); 10287 else 10288 { 10289 used_at = 1; 10290 set_at (op[0], 1); 10291 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, 10292 &offset_expr, AT, ZERO); 10293 } 10294 break; 10295 10296 case M_BLTL: 10297 likely = 1; 10298 /* Fall through. */ 10299 case M_BLT: 10300 if (op[1] == 0) 10301 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]); 10302 else if (op[0] == 0) 10303 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[1]); 10304 else 10305 { 10306 used_at = 1; 10307 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]); 10308 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, 10309 &offset_expr, AT, ZERO); 10310 } 10311 break; 10312 10313 case M_BLTUL: 10314 likely = 1; 10315 /* Fall through. */ 10316 case M_BLTU: 10317 if (op[1] == 0) 10318 goto do_false; 10319 else if (op[0] == 0) 10320 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, 10321 &offset_expr, ZERO, op[1]); 10322 else 10323 { 10324 used_at = 1; 10325 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]); 10326 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, 10327 &offset_expr, AT, ZERO); 10328 } 10329 break; 10330 10331 case M_DDIV_3: 10332 dbl = 1; 10333 /* Fall through. */ 10334 case M_DIV_3: 10335 s = "mflo"; 10336 goto do_div3; 10337 case M_DREM_3: 10338 dbl = 1; 10339 /* Fall through. */ 10340 case M_REM_3: 10341 s = "mfhi"; 10342 do_div3: 10343 if (op[2] == 0) 10344 { 10345 as_warn (_("divide by zero")); 10346 if (mips_trap) 10347 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); 10348 else 10349 macro_build (NULL, "break", BRK_FMT, 7); 10350 break; 10351 } 10352 10353 start_noreorder (); 10354 if (mips_trap) 10355 { 10356 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7); 10357 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]); 10358 } 10359 else 10360 { 10361 if (mips_opts.micromips) 10362 micromips_label_expr (&label_expr); 10363 else 10364 label_expr.X_add_number = 8; 10365 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO); 10366 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]); 10367 macro_build (NULL, "break", BRK_FMT, 7); 10368 if (mips_opts.micromips) 10369 micromips_add_label (); 10370 } 10371 expr1.X_add_number = -1; 10372 used_at = 1; 10373 load_register (AT, &expr1, dbl); 10374 if (mips_opts.micromips) 10375 micromips_label_expr (&label_expr); 10376 else 10377 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); 10378 macro_build (&label_expr, "bne", "s,t,p", op[2], AT); 10379 if (dbl) 10380 { 10381 expr1.X_add_number = 1; 10382 load_register (AT, &expr1, dbl); 10383 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31); 10384 } 10385 else 10386 { 10387 expr1.X_add_number = 0x80000000; 10388 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16); 10389 } 10390 if (mips_trap) 10391 { 10392 macro_build (NULL, "teq", TRAP_FMT, op[1], AT, 6); 10393 /* We want to close the noreorder block as soon as possible, so 10394 that later insns are available for delay slot filling. */ 10395 end_noreorder (); 10396 } 10397 else 10398 { 10399 if (mips_opts.micromips) 10400 micromips_label_expr (&label_expr); 10401 else 10402 label_expr.X_add_number = 8; 10403 macro_build (&label_expr, "bne", "s,t,p", op[1], AT); 10404 macro_build (NULL, "nop", ""); 10405 10406 /* We want to close the noreorder block as soon as possible, so 10407 that later insns are available for delay slot filling. */ 10408 end_noreorder (); 10409 10410 macro_build (NULL, "break", BRK_FMT, 6); 10411 } 10412 if (mips_opts.micromips) 10413 micromips_add_label (); 10414 macro_build (NULL, s, MFHL_FMT, op[0]); 10415 break; 10416 10417 case M_DIV_3I: 10418 s = "div"; 10419 s2 = "mflo"; 10420 goto do_divi; 10421 case M_DIVU_3I: 10422 s = "divu"; 10423 s2 = "mflo"; 10424 goto do_divi; 10425 case M_REM_3I: 10426 s = "div"; 10427 s2 = "mfhi"; 10428 goto do_divi; 10429 case M_REMU_3I: 10430 s = "divu"; 10431 s2 = "mfhi"; 10432 goto do_divi; 10433 case M_DDIV_3I: 10434 dbl = 1; 10435 s = "ddiv"; 10436 s2 = "mflo"; 10437 goto do_divi; 10438 case M_DDIVU_3I: 10439 dbl = 1; 10440 s = "ddivu"; 10441 s2 = "mflo"; 10442 goto do_divi; 10443 case M_DREM_3I: 10444 dbl = 1; 10445 s = "ddiv"; 10446 s2 = "mfhi"; 10447 goto do_divi; 10448 case M_DREMU_3I: 10449 dbl = 1; 10450 s = "ddivu"; 10451 s2 = "mfhi"; 10452 do_divi: 10453 if (imm_expr.X_add_number == 0) 10454 { 10455 as_warn (_("divide by zero")); 10456 if (mips_trap) 10457 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); 10458 else 10459 macro_build (NULL, "break", BRK_FMT, 7); 10460 break; 10461 } 10462 if (imm_expr.X_add_number == 1) 10463 { 10464 if (strcmp (s2, "mflo") == 0) 10465 move_register (op[0], op[1]); 10466 else 10467 move_register (op[0], ZERO); 10468 break; 10469 } 10470 if (imm_expr.X_add_number == -1 && s[strlen (s) - 1] != 'u') 10471 { 10472 if (strcmp (s2, "mflo") == 0) 10473 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", op[0], op[1]); 10474 else 10475 move_register (op[0], ZERO); 10476 break; 10477 } 10478 10479 used_at = 1; 10480 load_register (AT, &imm_expr, dbl); 10481 macro_build (NULL, s, "z,s,t", op[1], AT); 10482 macro_build (NULL, s2, MFHL_FMT, op[0]); 10483 break; 10484 10485 case M_DIVU_3: 10486 s = "divu"; 10487 s2 = "mflo"; 10488 goto do_divu3; 10489 case M_REMU_3: 10490 s = "divu"; 10491 s2 = "mfhi"; 10492 goto do_divu3; 10493 case M_DDIVU_3: 10494 s = "ddivu"; 10495 s2 = "mflo"; 10496 goto do_divu3; 10497 case M_DREMU_3: 10498 s = "ddivu"; 10499 s2 = "mfhi"; 10500 do_divu3: 10501 start_noreorder (); 10502 if (mips_trap) 10503 { 10504 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7); 10505 macro_build (NULL, s, "z,s,t", op[1], op[2]); 10506 /* We want to close the noreorder block as soon as possible, so 10507 that later insns are available for delay slot filling. */ 10508 end_noreorder (); 10509 } 10510 else 10511 { 10512 if (mips_opts.micromips) 10513 micromips_label_expr (&label_expr); 10514 else 10515 label_expr.X_add_number = 8; 10516 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO); 10517 macro_build (NULL, s, "z,s,t", op[1], op[2]); 10518 10519 /* We want to close the noreorder block as soon as possible, so 10520 that later insns are available for delay slot filling. */ 10521 end_noreorder (); 10522 macro_build (NULL, "break", BRK_FMT, 7); 10523 if (mips_opts.micromips) 10524 micromips_add_label (); 10525 } 10526 macro_build (NULL, s2, MFHL_FMT, op[0]); 10527 break; 10528 10529 case M_DLCA_AB: 10530 dbl = 1; 10531 /* Fall through. */ 10532 case M_LCA_AB: 10533 call = 1; 10534 goto do_la; 10535 case M_DLA_AB: 10536 dbl = 1; 10537 /* Fall through. */ 10538 case M_LA_AB: 10539 do_la: 10540 /* Load the address of a symbol into a register. If breg is not 10541 zero, we then add a base register to it. */ 10542 10543 breg = op[2]; 10544 if (dbl && GPR_SIZE == 32) 10545 as_warn (_("dla used to load 32-bit register; recommend using la " 10546 "instead")); 10547 10548 if (!dbl && HAVE_64BIT_OBJECTS) 10549 as_warn (_("la used to load 64-bit address; recommend using dla " 10550 "instead")); 10551 10552 if (small_offset_p (0, align, 16)) 10553 { 10554 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", op[0], breg, 10555 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]); 10556 break; 10557 } 10558 10559 if (mips_opts.at && (op[0] == breg)) 10560 { 10561 tempreg = AT; 10562 used_at = 1; 10563 } 10564 else 10565 tempreg = op[0]; 10566 10567 if (offset_expr.X_op != O_symbol 10568 && offset_expr.X_op != O_constant) 10569 { 10570 as_bad (_("expression too complex")); 10571 offset_expr.X_op = O_constant; 10572 } 10573 10574 if (offset_expr.X_op == O_constant) 10575 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); 10576 else if (mips_pic == NO_PIC) 10577 { 10578 /* If this is a reference to a GP relative symbol, we want 10579 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) 10580 Otherwise we want 10581 lui $tempreg,<sym> (BFD_RELOC_HI16_S) 10582 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) 10583 If we have a constant, we need two instructions anyhow, 10584 so we may as well always use the latter form. 10585 10586 With 64bit address space and a usable $at we want 10587 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) 10588 lui $at,<sym> (BFD_RELOC_HI16_S) 10589 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) 10590 daddiu $at,<sym> (BFD_RELOC_LO16) 10591 dsll32 $tempreg,0 10592 daddu $tempreg,$tempreg,$at 10593 10594 If $at is already in use, we use a path which is suboptimal 10595 on superscalar processors. 10596 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) 10597 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) 10598 dsll $tempreg,16 10599 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) 10600 dsll $tempreg,16 10601 daddiu $tempreg,<sym> (BFD_RELOC_LO16) 10602 10603 For GP relative symbols in 64bit address space we can use 10604 the same sequence as in 32bit address space. */ 10605 if (HAVE_64BIT_SYMBOLS) 10606 { 10607 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET 10608 && !nopic_need_relax (offset_expr.X_add_symbol, 1)) 10609 { 10610 relax_start (offset_expr.X_add_symbol); 10611 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 10612 tempreg, mips_gp_register, BFD_RELOC_GPREL16); 10613 relax_switch (); 10614 } 10615 10616 if (used_at == 0 && mips_opts.at) 10617 { 10618 macro_build (&offset_expr, "lui", LUI_FMT, 10619 tempreg, BFD_RELOC_MIPS_HIGHEST); 10620 macro_build (&offset_expr, "lui", LUI_FMT, 10621 AT, BFD_RELOC_HI16_S); 10622 macro_build (&offset_expr, "daddiu", "t,r,j", 10623 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); 10624 macro_build (&offset_expr, "daddiu", "t,r,j", 10625 AT, AT, BFD_RELOC_LO16); 10626 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); 10627 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); 10628 used_at = 1; 10629 } 10630 else 10631 { 10632 macro_build (&offset_expr, "lui", LUI_FMT, 10633 tempreg, BFD_RELOC_MIPS_HIGHEST); 10634 macro_build (&offset_expr, "daddiu", "t,r,j", 10635 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); 10636 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); 10637 macro_build (&offset_expr, "daddiu", "t,r,j", 10638 tempreg, tempreg, BFD_RELOC_HI16_S); 10639 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); 10640 macro_build (&offset_expr, "daddiu", "t,r,j", 10641 tempreg, tempreg, BFD_RELOC_LO16); 10642 } 10643 10644 if (mips_relax.sequence) 10645 relax_end (); 10646 } 10647 else 10648 { 10649 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET 10650 && !nopic_need_relax (offset_expr.X_add_symbol, 1)) 10651 { 10652 relax_start (offset_expr.X_add_symbol); 10653 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 10654 tempreg, mips_gp_register, BFD_RELOC_GPREL16); 10655 relax_switch (); 10656 } 10657 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) 10658 as_bad (_("offset too large")); 10659 macro_build_lui (&offset_expr, tempreg); 10660 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 10661 tempreg, tempreg, BFD_RELOC_LO16); 10662 if (mips_relax.sequence) 10663 relax_end (); 10664 } 10665 } 10666 else if (!mips_big_got && !HAVE_NEWABI) 10667 { 10668 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; 10669 10670 /* If this is a reference to an external symbol, and there 10671 is no constant, we want 10672 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 10673 or for lca or if tempreg is PIC_CALL_REG 10674 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) 10675 For a local symbol, we want 10676 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 10677 nop 10678 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) 10679 10680 If we have a small constant, and this is a reference to 10681 an external symbol, we want 10682 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 10683 nop 10684 addiu $tempreg,$tempreg,<constant> 10685 For a local symbol, we want the same instruction 10686 sequence, but we output a BFD_RELOC_LO16 reloc on the 10687 addiu instruction. 10688 10689 If we have a large constant, and this is a reference to 10690 an external symbol, we want 10691 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 10692 lui $at,<hiconstant> 10693 addiu $at,$at,<loconstant> 10694 addu $tempreg,$tempreg,$at 10695 For a local symbol, we want the same instruction 10696 sequence, but we output a BFD_RELOC_LO16 reloc on the 10697 addiu instruction. 10698 */ 10699 10700 if (offset_expr.X_add_number == 0) 10701 { 10702 if (mips_pic == SVR4_PIC 10703 && breg == 0 10704 && (call || tempreg == PIC_CALL_REG)) 10705 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; 10706 10707 relax_start (offset_expr.X_add_symbol); 10708 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 10709 lw_reloc_type, mips_gp_register); 10710 if (breg != 0) 10711 { 10712 /* We're going to put in an addu instruction using 10713 tempreg, so we may as well insert the nop right 10714 now. */ 10715 load_delay_nop (); 10716 } 10717 relax_switch (); 10718 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 10719 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); 10720 load_delay_nop (); 10721 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 10722 tempreg, tempreg, BFD_RELOC_LO16); 10723 relax_end (); 10724 /* FIXME: If breg == 0, and the next instruction uses 10725 $tempreg, then if this variant case is used an extra 10726 nop will be generated. */ 10727 } 10728 else if (offset_expr.X_add_number >= -0x8000 10729 && offset_expr.X_add_number < 0x8000) 10730 { 10731 load_got_offset (tempreg, &offset_expr); 10732 load_delay_nop (); 10733 add_got_offset (tempreg, &offset_expr); 10734 } 10735 else 10736 { 10737 expr1.X_add_number = offset_expr.X_add_number; 10738 offset_expr.X_add_number = 10739 SEXT_16BIT (offset_expr.X_add_number); 10740 load_got_offset (tempreg, &offset_expr); 10741 offset_expr.X_add_number = expr1.X_add_number; 10742 /* If we are going to add in a base register, and the 10743 target register and the base register are the same, 10744 then we are using AT as a temporary register. Since 10745 we want to load the constant into AT, we add our 10746 current AT (from the global offset table) and the 10747 register into the register now, and pretend we were 10748 not using a base register. */ 10749 if (breg == op[0]) 10750 { 10751 load_delay_nop (); 10752 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 10753 op[0], AT, breg); 10754 breg = 0; 10755 tempreg = op[0]; 10756 } 10757 add_got_offset_hilo (tempreg, &offset_expr, AT); 10758 used_at = 1; 10759 } 10760 } 10761 else if (!mips_big_got && HAVE_NEWABI) 10762 { 10763 int add_breg_early = 0; 10764 10765 /* If this is a reference to an external, and there is no 10766 constant, or local symbol (*), with or without a 10767 constant, we want 10768 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) 10769 or for lca or if tempreg is PIC_CALL_REG 10770 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) 10771 10772 If we have a small constant, and this is a reference to 10773 an external symbol, we want 10774 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) 10775 addiu $tempreg,$tempreg,<constant> 10776 10777 If we have a large constant, and this is a reference to 10778 an external symbol, we want 10779 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) 10780 lui $at,<hiconstant> 10781 addiu $at,$at,<loconstant> 10782 addu $tempreg,$tempreg,$at 10783 10784 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for 10785 local symbols, even though it introduces an additional 10786 instruction. */ 10787 10788 if (offset_expr.X_add_number) 10789 { 10790 expr1.X_add_number = offset_expr.X_add_number; 10791 offset_expr.X_add_number = 0; 10792 10793 relax_start (offset_expr.X_add_symbol); 10794 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 10795 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); 10796 10797 if (expr1.X_add_number >= -0x8000 10798 && expr1.X_add_number < 0x8000) 10799 { 10800 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", 10801 tempreg, tempreg, BFD_RELOC_LO16); 10802 } 10803 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) 10804 { 10805 unsigned int dreg; 10806 10807 /* If we are going to add in a base register, and the 10808 target register and the base register are the same, 10809 then we are using AT as a temporary register. Since 10810 we want to load the constant into AT, we add our 10811 current AT (from the global offset table) and the 10812 register into the register now, and pretend we were 10813 not using a base register. */ 10814 if (breg != op[0]) 10815 dreg = tempreg; 10816 else 10817 { 10818 gas_assert (tempreg == AT); 10819 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 10820 op[0], AT, breg); 10821 dreg = op[0]; 10822 add_breg_early = 1; 10823 } 10824 10825 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); 10826 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 10827 dreg, dreg, AT); 10828 10829 used_at = 1; 10830 } 10831 else 10832 as_bad (_("PIC code offset overflow (max 32 signed bits)")); 10833 10834 relax_switch (); 10835 offset_expr.X_add_number = expr1.X_add_number; 10836 10837 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 10838 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); 10839 if (add_breg_early) 10840 { 10841 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 10842 op[0], tempreg, breg); 10843 breg = 0; 10844 tempreg = op[0]; 10845 } 10846 relax_end (); 10847 } 10848 else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) 10849 { 10850 relax_start (offset_expr.X_add_symbol); 10851 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 10852 BFD_RELOC_MIPS_CALL16, mips_gp_register); 10853 relax_switch (); 10854 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 10855 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); 10856 relax_end (); 10857 } 10858 else 10859 { 10860 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 10861 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); 10862 } 10863 } 10864 else if (mips_big_got && !HAVE_NEWABI) 10865 { 10866 int gpdelay; 10867 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; 10868 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; 10869 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; 10870 10871 /* This is the large GOT case. If this is a reference to an 10872 external symbol, and there is no constant, we want 10873 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 10874 addu $tempreg,$tempreg,$gp 10875 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 10876 or for lca or if tempreg is PIC_CALL_REG 10877 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) 10878 addu $tempreg,$tempreg,$gp 10879 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) 10880 For a local symbol, we want 10881 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 10882 nop 10883 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) 10884 10885 If we have a small constant, and this is a reference to 10886 an external symbol, we want 10887 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 10888 addu $tempreg,$tempreg,$gp 10889 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 10890 nop 10891 addiu $tempreg,$tempreg,<constant> 10892 For a local symbol, we want 10893 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 10894 nop 10895 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) 10896 10897 If we have a large constant, and this is a reference to 10898 an external symbol, we want 10899 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 10900 addu $tempreg,$tempreg,$gp 10901 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 10902 lui $at,<hiconstant> 10903 addiu $at,$at,<loconstant> 10904 addu $tempreg,$tempreg,$at 10905 For a local symbol, we want 10906 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 10907 lui $at,<hiconstant> 10908 addiu $at,$at,<loconstant> (BFD_RELOC_LO16) 10909 addu $tempreg,$tempreg,$at 10910 */ 10911 10912 expr1.X_add_number = offset_expr.X_add_number; 10913 offset_expr.X_add_number = 0; 10914 relax_start (offset_expr.X_add_symbol); 10915 gpdelay = reg_needs_delay (mips_gp_register); 10916 if (expr1.X_add_number == 0 && breg == 0 10917 && (call || tempreg == PIC_CALL_REG)) 10918 { 10919 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; 10920 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; 10921 } 10922 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); 10923 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 10924 tempreg, tempreg, mips_gp_register); 10925 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 10926 tempreg, lw_reloc_type, tempreg); 10927 if (expr1.X_add_number == 0) 10928 { 10929 if (breg != 0) 10930 { 10931 /* We're going to put in an addu instruction using 10932 tempreg, so we may as well insert the nop right 10933 now. */ 10934 load_delay_nop (); 10935 } 10936 } 10937 else if (expr1.X_add_number >= -0x8000 10938 && expr1.X_add_number < 0x8000) 10939 { 10940 load_delay_nop (); 10941 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", 10942 tempreg, tempreg, BFD_RELOC_LO16); 10943 } 10944 else 10945 { 10946 unsigned int dreg; 10947 10948 /* If we are going to add in a base register, and the 10949 target register and the base register are the same, 10950 then we are using AT as a temporary register. Since 10951 we want to load the constant into AT, we add our 10952 current AT (from the global offset table) and the 10953 register into the register now, and pretend we were 10954 not using a base register. */ 10955 if (breg != op[0]) 10956 dreg = tempreg; 10957 else 10958 { 10959 gas_assert (tempreg == AT); 10960 load_delay_nop (); 10961 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 10962 op[0], AT, breg); 10963 dreg = op[0]; 10964 } 10965 10966 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); 10967 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); 10968 10969 used_at = 1; 10970 } 10971 offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number); 10972 relax_switch (); 10973 10974 if (gpdelay) 10975 { 10976 /* This is needed because this instruction uses $gp, but 10977 the first instruction on the main stream does not. */ 10978 macro_build (NULL, "nop", ""); 10979 } 10980 10981 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 10982 local_reloc_type, mips_gp_register); 10983 if (expr1.X_add_number >= -0x8000 10984 && expr1.X_add_number < 0x8000) 10985 { 10986 load_delay_nop (); 10987 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 10988 tempreg, tempreg, BFD_RELOC_LO16); 10989 /* FIXME: If add_number is 0, and there was no base 10990 register, the external symbol case ended with a load, 10991 so if the symbol turns out to not be external, and 10992 the next instruction uses tempreg, an unnecessary nop 10993 will be inserted. */ 10994 } 10995 else 10996 { 10997 if (breg == op[0]) 10998 { 10999 /* We must add in the base register now, as in the 11000 external symbol case. */ 11001 gas_assert (tempreg == AT); 11002 load_delay_nop (); 11003 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 11004 op[0], AT, breg); 11005 tempreg = op[0]; 11006 /* We set breg to 0 because we have arranged to add 11007 it in in both cases. */ 11008 breg = 0; 11009 } 11010 11011 macro_build_lui (&expr1, AT); 11012 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 11013 AT, AT, BFD_RELOC_LO16); 11014 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 11015 tempreg, tempreg, AT); 11016 used_at = 1; 11017 } 11018 relax_end (); 11019 } 11020 else if (mips_big_got && HAVE_NEWABI) 11021 { 11022 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; 11023 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; 11024 int add_breg_early = 0; 11025 11026 /* This is the large GOT case. If this is a reference to an 11027 external symbol, and there is no constant, we want 11028 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 11029 add $tempreg,$tempreg,$gp 11030 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 11031 or for lca or if tempreg is PIC_CALL_REG 11032 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) 11033 add $tempreg,$tempreg,$gp 11034 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) 11035 11036 If we have a small constant, and this is a reference to 11037 an external symbol, we want 11038 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 11039 add $tempreg,$tempreg,$gp 11040 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 11041 addi $tempreg,$tempreg,<constant> 11042 11043 If we have a large constant, and this is a reference to 11044 an external symbol, we want 11045 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 11046 addu $tempreg,$tempreg,$gp 11047 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 11048 lui $at,<hiconstant> 11049 addi $at,$at,<loconstant> 11050 add $tempreg,$tempreg,$at 11051 11052 If we have NewABI, and we know it's a local symbol, we want 11053 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) 11054 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) 11055 otherwise we have to resort to GOT_HI16/GOT_LO16. */ 11056 11057 relax_start (offset_expr.X_add_symbol); 11058 11059 expr1.X_add_number = offset_expr.X_add_number; 11060 offset_expr.X_add_number = 0; 11061 11062 if (expr1.X_add_number == 0 && breg == 0 11063 && (call || tempreg == PIC_CALL_REG)) 11064 { 11065 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; 11066 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; 11067 } 11068 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); 11069 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 11070 tempreg, tempreg, mips_gp_register); 11071 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 11072 tempreg, lw_reloc_type, tempreg); 11073 11074 if (expr1.X_add_number == 0) 11075 ; 11076 else if (expr1.X_add_number >= -0x8000 11077 && expr1.X_add_number < 0x8000) 11078 { 11079 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", 11080 tempreg, tempreg, BFD_RELOC_LO16); 11081 } 11082 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) 11083 { 11084 unsigned int dreg; 11085 11086 /* If we are going to add in a base register, and the 11087 target register and the base register are the same, 11088 then we are using AT as a temporary register. Since 11089 we want to load the constant into AT, we add our 11090 current AT (from the global offset table) and the 11091 register into the register now, and pretend we were 11092 not using a base register. */ 11093 if (breg != op[0]) 11094 dreg = tempreg; 11095 else 11096 { 11097 gas_assert (tempreg == AT); 11098 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 11099 op[0], AT, breg); 11100 dreg = op[0]; 11101 add_breg_early = 1; 11102 } 11103 11104 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); 11105 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); 11106 11107 used_at = 1; 11108 } 11109 else 11110 as_bad (_("PIC code offset overflow (max 32 signed bits)")); 11111 11112 relax_switch (); 11113 offset_expr.X_add_number = expr1.X_add_number; 11114 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 11115 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); 11116 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, 11117 tempreg, BFD_RELOC_MIPS_GOT_OFST); 11118 if (add_breg_early) 11119 { 11120 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 11121 op[0], tempreg, breg); 11122 breg = 0; 11123 tempreg = op[0]; 11124 } 11125 relax_end (); 11126 } 11127 else 11128 abort (); 11129 11130 if (breg != 0) 11131 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", op[0], tempreg, breg); 11132 break; 11133 11134 case M_MSGSND: 11135 gas_assert (!mips_opts.micromips); 11136 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x01); 11137 break; 11138 11139 case M_MSGLD: 11140 gas_assert (!mips_opts.micromips); 11141 macro_build (NULL, "c2", "C", 0x02); 11142 break; 11143 11144 case M_MSGLD_T: 11145 gas_assert (!mips_opts.micromips); 11146 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x02); 11147 break; 11148 11149 case M_MSGWAIT: 11150 gas_assert (!mips_opts.micromips); 11151 macro_build (NULL, "c2", "C", 3); 11152 break; 11153 11154 case M_MSGWAIT_T: 11155 gas_assert (!mips_opts.micromips); 11156 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x03); 11157 break; 11158 11159 case M_J_A: 11160 /* The j instruction may not be used in PIC code, since it 11161 requires an absolute address. We convert it to a b 11162 instruction. */ 11163 if (mips_pic == NO_PIC) 11164 macro_build (&offset_expr, "j", "a"); 11165 else 11166 macro_build (&offset_expr, "b", "p"); 11167 break; 11168 11169 /* The jal instructions must be handled as macros because when 11170 generating PIC code they expand to multi-instruction 11171 sequences. Normally they are simple instructions. */ 11172 case M_JALS_1: 11173 op[1] = op[0]; 11174 op[0] = RA; 11175 /* Fall through. */ 11176 case M_JALS_2: 11177 gas_assert (mips_opts.micromips); 11178 if (mips_opts.insn32) 11179 { 11180 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str); 11181 break; 11182 } 11183 jals = 1; 11184 goto jal; 11185 case M_JAL_1: 11186 op[1] = op[0]; 11187 op[0] = RA; 11188 /* Fall through. */ 11189 case M_JAL_2: 11190 jal: 11191 if (mips_pic == NO_PIC) 11192 { 11193 s = jals ? "jalrs" : "jalr"; 11194 if (mips_opts.micromips 11195 && !mips_opts.insn32 11196 && op[0] == RA 11197 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) 11198 macro_build (NULL, s, "mj", op[1]); 11199 else 11200 macro_build (NULL, s, JALR_FMT, op[0], op[1]); 11201 } 11202 else 11203 { 11204 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI 11205 && mips_cprestore_offset >= 0); 11206 11207 if (op[1] != PIC_CALL_REG) 11208 as_warn (_("MIPS PIC call to register other than $25")); 11209 11210 s = ((mips_opts.micromips 11211 && !mips_opts.insn32 11212 && (!mips_opts.noreorder || cprestore)) 11213 ? "jalrs" : "jalr"); 11214 if (mips_opts.micromips 11215 && !mips_opts.insn32 11216 && op[0] == RA 11217 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) 11218 macro_build (NULL, s, "mj", op[1]); 11219 else 11220 macro_build (NULL, s, JALR_FMT, op[0], op[1]); 11221 if (mips_pic == SVR4_PIC && !HAVE_NEWABI) 11222 { 11223 if (mips_cprestore_offset < 0) 11224 as_warn (_("no .cprestore pseudo-op used in PIC code")); 11225 else 11226 { 11227 if (!mips_frame_reg_valid) 11228 { 11229 as_warn (_("no .frame pseudo-op used in PIC code")); 11230 /* Quiet this warning. */ 11231 mips_frame_reg_valid = 1; 11232 } 11233 if (!mips_cprestore_valid) 11234 { 11235 as_warn (_("no .cprestore pseudo-op used in PIC code")); 11236 /* Quiet this warning. */ 11237 mips_cprestore_valid = 1; 11238 } 11239 if (mips_opts.noreorder) 11240 macro_build (NULL, "nop", ""); 11241 expr1.X_add_number = mips_cprestore_offset; 11242 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, 11243 mips_gp_register, 11244 mips_frame_reg, 11245 HAVE_64BIT_ADDRESSES); 11246 } 11247 } 11248 } 11249 11250 break; 11251 11252 case M_JALS_A: 11253 gas_assert (mips_opts.micromips); 11254 if (mips_opts.insn32) 11255 { 11256 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str); 11257 break; 11258 } 11259 jals = 1; 11260 /* Fall through. */ 11261 case M_JAL_A: 11262 if (mips_pic == NO_PIC) 11263 macro_build (&offset_expr, jals ? "jals" : "jal", "a"); 11264 else if (mips_pic == SVR4_PIC) 11265 { 11266 /* If this is a reference to an external symbol, and we are 11267 using a small GOT, we want 11268 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) 11269 nop 11270 jalr $ra,$25 11271 nop 11272 lw $gp,cprestore($sp) 11273 The cprestore value is set using the .cprestore 11274 pseudo-op. If we are using a big GOT, we want 11275 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) 11276 addu $25,$25,$gp 11277 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) 11278 nop 11279 jalr $ra,$25 11280 nop 11281 lw $gp,cprestore($sp) 11282 If the symbol is not external, we want 11283 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 11284 nop 11285 addiu $25,$25,<sym> (BFD_RELOC_LO16) 11286 jalr $ra,$25 11287 nop 11288 lw $gp,cprestore($sp) 11289 11290 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 11291 sequences above, minus nops, unless the symbol is local, 11292 which enables us to use GOT_PAGE/GOT_OFST (big got) or 11293 GOT_DISP. */ 11294 if (HAVE_NEWABI) 11295 { 11296 if (!mips_big_got) 11297 { 11298 relax_start (offset_expr.X_add_symbol); 11299 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 11300 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, 11301 mips_gp_register); 11302 relax_switch (); 11303 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 11304 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, 11305 mips_gp_register); 11306 relax_end (); 11307 } 11308 else 11309 { 11310 relax_start (offset_expr.X_add_symbol); 11311 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, 11312 BFD_RELOC_MIPS_CALL_HI16); 11313 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, 11314 PIC_CALL_REG, mips_gp_register); 11315 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 11316 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, 11317 PIC_CALL_REG); 11318 relax_switch (); 11319 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 11320 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, 11321 mips_gp_register); 11322 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 11323 PIC_CALL_REG, PIC_CALL_REG, 11324 BFD_RELOC_MIPS_GOT_OFST); 11325 relax_end (); 11326 } 11327 11328 macro_build_jalr (&offset_expr, 0); 11329 } 11330 else 11331 { 11332 relax_start (offset_expr.X_add_symbol); 11333 if (!mips_big_got) 11334 { 11335 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 11336 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, 11337 mips_gp_register); 11338 load_delay_nop (); 11339 relax_switch (); 11340 } 11341 else 11342 { 11343 int gpdelay; 11344 11345 gpdelay = reg_needs_delay (mips_gp_register); 11346 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, 11347 BFD_RELOC_MIPS_CALL_HI16); 11348 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, 11349 PIC_CALL_REG, mips_gp_register); 11350 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 11351 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, 11352 PIC_CALL_REG); 11353 load_delay_nop (); 11354 relax_switch (); 11355 if (gpdelay) 11356 macro_build (NULL, "nop", ""); 11357 } 11358 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 11359 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, 11360 mips_gp_register); 11361 load_delay_nop (); 11362 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 11363 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); 11364 relax_end (); 11365 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0); 11366 11367 if (mips_cprestore_offset < 0) 11368 as_warn (_("no .cprestore pseudo-op used in PIC code")); 11369 else 11370 { 11371 if (!mips_frame_reg_valid) 11372 { 11373 as_warn (_("no .frame pseudo-op used in PIC code")); 11374 /* Quiet this warning. */ 11375 mips_frame_reg_valid = 1; 11376 } 11377 if (!mips_cprestore_valid) 11378 { 11379 as_warn (_("no .cprestore pseudo-op used in PIC code")); 11380 /* Quiet this warning. */ 11381 mips_cprestore_valid = 1; 11382 } 11383 if (mips_opts.noreorder) 11384 macro_build (NULL, "nop", ""); 11385 expr1.X_add_number = mips_cprestore_offset; 11386 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, 11387 mips_gp_register, 11388 mips_frame_reg, 11389 HAVE_64BIT_ADDRESSES); 11390 } 11391 } 11392 } 11393 else if (mips_pic == VXWORKS_PIC) 11394 as_bad (_("non-PIC jump used in PIC library")); 11395 else 11396 abort (); 11397 11398 break; 11399 11400 case M_LBUE_AB: 11401 s = "lbue"; 11402 fmt = "t,+j(b)"; 11403 offbits = 9; 11404 goto ld_st; 11405 case M_LHUE_AB: 11406 s = "lhue"; 11407 fmt = "t,+j(b)"; 11408 offbits = 9; 11409 goto ld_st; 11410 case M_LBE_AB: 11411 s = "lbe"; 11412 fmt = "t,+j(b)"; 11413 offbits = 9; 11414 goto ld_st; 11415 case M_LHE_AB: 11416 s = "lhe"; 11417 fmt = "t,+j(b)"; 11418 offbits = 9; 11419 goto ld_st; 11420 case M_LLE_AB: 11421 s = "lle"; 11422 fmt = "t,+j(b)"; 11423 offbits = 9; 11424 goto ld_st; 11425 case M_LWE_AB: 11426 s = "lwe"; 11427 fmt = "t,+j(b)"; 11428 offbits = 9; 11429 goto ld_st; 11430 case M_LWLE_AB: 11431 s = "lwle"; 11432 fmt = "t,+j(b)"; 11433 offbits = 9; 11434 goto ld_st; 11435 case M_LWRE_AB: 11436 s = "lwre"; 11437 fmt = "t,+j(b)"; 11438 offbits = 9; 11439 goto ld_st; 11440 case M_SBE_AB: 11441 s = "sbe"; 11442 fmt = "t,+j(b)"; 11443 offbits = 9; 11444 goto ld_st; 11445 case M_SCE_AB: 11446 s = "sce"; 11447 fmt = "t,+j(b)"; 11448 offbits = 9; 11449 goto ld_st; 11450 case M_SHE_AB: 11451 s = "she"; 11452 fmt = "t,+j(b)"; 11453 offbits = 9; 11454 goto ld_st; 11455 case M_SWE_AB: 11456 s = "swe"; 11457 fmt = "t,+j(b)"; 11458 offbits = 9; 11459 goto ld_st; 11460 case M_SWLE_AB: 11461 s = "swle"; 11462 fmt = "t,+j(b)"; 11463 offbits = 9; 11464 goto ld_st; 11465 case M_SWRE_AB: 11466 s = "swre"; 11467 fmt = "t,+j(b)"; 11468 offbits = 9; 11469 goto ld_st; 11470 case M_ACLR_AB: 11471 s = "aclr"; 11472 fmt = "\\,~(b)"; 11473 offbits = 12; 11474 goto ld_st; 11475 case M_ASET_AB: 11476 s = "aset"; 11477 fmt = "\\,~(b)"; 11478 offbits = 12; 11479 goto ld_st; 11480 case M_LB_AB: 11481 s = "lb"; 11482 fmt = "t,o(b)"; 11483 goto ld; 11484 case M_LBU_AB: 11485 s = "lbu"; 11486 fmt = "t,o(b)"; 11487 goto ld; 11488 case M_LH_AB: 11489 s = "lh"; 11490 fmt = "t,o(b)"; 11491 goto ld; 11492 case M_LHU_AB: 11493 s = "lhu"; 11494 fmt = "t,o(b)"; 11495 goto ld; 11496 case M_LW_AB: 11497 s = "lw"; 11498 fmt = "t,o(b)"; 11499 goto ld; 11500 case M_LWC0_AB: 11501 gas_assert (!mips_opts.micromips); 11502 s = "lwc0"; 11503 fmt = "E,o(b)"; 11504 /* Itbl support may require additional care here. */ 11505 coproc = 1; 11506 goto ld_st; 11507 case M_LWC1_AB: 11508 s = "lwc1"; 11509 fmt = "T,o(b)"; 11510 /* Itbl support may require additional care here. */ 11511 coproc = 1; 11512 goto ld_st; 11513 case M_LWC2_AB: 11514 s = "lwc2"; 11515 fmt = COP12_FMT; 11516 offbits = (mips_opts.micromips ? 12 11517 : ISA_IS_R6 (mips_opts.isa) ? 11 11518 : 16); 11519 /* Itbl support may require additional care here. */ 11520 coproc = 1; 11521 goto ld_st; 11522 case M_LWC3_AB: 11523 gas_assert (!mips_opts.micromips); 11524 s = "lwc3"; 11525 fmt = "E,o(b)"; 11526 /* Itbl support may require additional care here. */ 11527 coproc = 1; 11528 goto ld_st; 11529 case M_LWL_AB: 11530 s = "lwl"; 11531 fmt = MEM12_FMT; 11532 offbits = (mips_opts.micromips ? 12 : 16); 11533 goto ld_st; 11534 case M_LWR_AB: 11535 s = "lwr"; 11536 fmt = MEM12_FMT; 11537 offbits = (mips_opts.micromips ? 12 : 16); 11538 goto ld_st; 11539 case M_LDC1_AB: 11540 s = "ldc1"; 11541 fmt = "T,o(b)"; 11542 /* Itbl support may require additional care here. */ 11543 coproc = 1; 11544 goto ld_st; 11545 case M_LDC2_AB: 11546 s = "ldc2"; 11547 fmt = COP12_FMT; 11548 offbits = (mips_opts.micromips ? 12 11549 : ISA_IS_R6 (mips_opts.isa) ? 11 11550 : 16); 11551 /* Itbl support may require additional care here. */ 11552 coproc = 1; 11553 goto ld_st; 11554 case M_LQC2_AB: 11555 s = "lqc2"; 11556 fmt = "+7,o(b)"; 11557 /* Itbl support may require additional care here. */ 11558 coproc = 1; 11559 goto ld_st; 11560 case M_LDC3_AB: 11561 s = "ldc3"; 11562 fmt = "E,o(b)"; 11563 /* Itbl support may require additional care here. */ 11564 coproc = 1; 11565 goto ld_st; 11566 case M_LDL_AB: 11567 s = "ldl"; 11568 fmt = MEM12_FMT; 11569 offbits = (mips_opts.micromips ? 12 : 16); 11570 goto ld_st; 11571 case M_LDR_AB: 11572 s = "ldr"; 11573 fmt = MEM12_FMT; 11574 offbits = (mips_opts.micromips ? 12 : 16); 11575 goto ld_st; 11576 case M_LL_AB: 11577 s = "ll"; 11578 fmt = LL_SC_FMT; 11579 offbits = (mips_opts.micromips ? 12 11580 : ISA_IS_R6 (mips_opts.isa) ? 9 11581 : 16); 11582 goto ld; 11583 case M_LLD_AB: 11584 s = "lld"; 11585 fmt = LL_SC_FMT; 11586 offbits = (mips_opts.micromips ? 12 11587 : ISA_IS_R6 (mips_opts.isa) ? 9 11588 : 16); 11589 goto ld; 11590 case M_LWU_AB: 11591 s = "lwu"; 11592 fmt = MEM12_FMT; 11593 offbits = (mips_opts.micromips ? 12 : 16); 11594 goto ld; 11595 case M_LWP_AB: 11596 gas_assert (mips_opts.micromips); 11597 s = "lwp"; 11598 fmt = "t,~(b)"; 11599 offbits = 12; 11600 lp = 1; 11601 goto ld; 11602 case M_LDP_AB: 11603 gas_assert (mips_opts.micromips); 11604 s = "ldp"; 11605 fmt = "t,~(b)"; 11606 offbits = 12; 11607 lp = 1; 11608 goto ld; 11609 case M_LWM_AB: 11610 gas_assert (mips_opts.micromips); 11611 s = "lwm"; 11612 fmt = "n,~(b)"; 11613 offbits = 12; 11614 goto ld_st; 11615 case M_LDM_AB: 11616 gas_assert (mips_opts.micromips); 11617 s = "ldm"; 11618 fmt = "n,~(b)"; 11619 offbits = 12; 11620 goto ld_st; 11621 11622 ld: 11623 /* We don't want to use $0 as tempreg. */ 11624 if (op[2] == op[0] + lp || op[0] + lp == ZERO) 11625 goto ld_st; 11626 else 11627 tempreg = op[0] + lp; 11628 goto ld_noat; 11629 11630 case M_SB_AB: 11631 s = "sb"; 11632 fmt = "t,o(b)"; 11633 goto ld_st; 11634 case M_SH_AB: 11635 s = "sh"; 11636 fmt = "t,o(b)"; 11637 goto ld_st; 11638 case M_SW_AB: 11639 s = "sw"; 11640 fmt = "t,o(b)"; 11641 goto ld_st; 11642 case M_SWC0_AB: 11643 gas_assert (!mips_opts.micromips); 11644 s = "swc0"; 11645 fmt = "E,o(b)"; 11646 /* Itbl support may require additional care here. */ 11647 coproc = 1; 11648 goto ld_st; 11649 case M_SWC1_AB: 11650 s = "swc1"; 11651 fmt = "T,o(b)"; 11652 /* Itbl support may require additional care here. */ 11653 coproc = 1; 11654 goto ld_st; 11655 case M_SWC2_AB: 11656 s = "swc2"; 11657 fmt = COP12_FMT; 11658 offbits = (mips_opts.micromips ? 12 11659 : ISA_IS_R6 (mips_opts.isa) ? 11 11660 : 16); 11661 /* Itbl support may require additional care here. */ 11662 coproc = 1; 11663 goto ld_st; 11664 case M_SWC3_AB: 11665 gas_assert (!mips_opts.micromips); 11666 s = "swc3"; 11667 fmt = "E,o(b)"; 11668 /* Itbl support may require additional care here. */ 11669 coproc = 1; 11670 goto ld_st; 11671 case M_SWL_AB: 11672 s = "swl"; 11673 fmt = MEM12_FMT; 11674 offbits = (mips_opts.micromips ? 12 : 16); 11675 goto ld_st; 11676 case M_SWR_AB: 11677 s = "swr"; 11678 fmt = MEM12_FMT; 11679 offbits = (mips_opts.micromips ? 12 : 16); 11680 goto ld_st; 11681 case M_SC_AB: 11682 s = "sc"; 11683 fmt = LL_SC_FMT; 11684 offbits = (mips_opts.micromips ? 12 11685 : ISA_IS_R6 (mips_opts.isa) ? 9 11686 : 16); 11687 goto ld_st; 11688 case M_SCD_AB: 11689 s = "scd"; 11690 fmt = LL_SC_FMT; 11691 offbits = (mips_opts.micromips ? 12 11692 : ISA_IS_R6 (mips_opts.isa) ? 9 11693 : 16); 11694 goto ld_st; 11695 case M_CACHE_AB: 11696 s = "cache"; 11697 fmt = (mips_opts.micromips ? "k,~(b)" 11698 : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)" 11699 : "k,o(b)"); 11700 offbits = (mips_opts.micromips ? 12 11701 : ISA_IS_R6 (mips_opts.isa) ? 9 11702 : 16); 11703 goto ld_st; 11704 case M_CACHEE_AB: 11705 s = "cachee"; 11706 fmt = "k,+j(b)"; 11707 offbits = 9; 11708 goto ld_st; 11709 case M_PREF_AB: 11710 s = "pref"; 11711 fmt = (mips_opts.micromips ? "k,~(b)" 11712 : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)" 11713 : "k,o(b)"); 11714 offbits = (mips_opts.micromips ? 12 11715 : ISA_IS_R6 (mips_opts.isa) ? 9 11716 : 16); 11717 goto ld_st; 11718 case M_PREFE_AB: 11719 s = "prefe"; 11720 fmt = "k,+j(b)"; 11721 offbits = 9; 11722 goto ld_st; 11723 case M_SDC1_AB: 11724 s = "sdc1"; 11725 fmt = "T,o(b)"; 11726 coproc = 1; 11727 /* Itbl support may require additional care here. */ 11728 goto ld_st; 11729 case M_SDC2_AB: 11730 s = "sdc2"; 11731 fmt = COP12_FMT; 11732 offbits = (mips_opts.micromips ? 12 11733 : ISA_IS_R6 (mips_opts.isa) ? 11 11734 : 16); 11735 /* Itbl support may require additional care here. */ 11736 coproc = 1; 11737 goto ld_st; 11738 case M_SQC2_AB: 11739 s = "sqc2"; 11740 fmt = "+7,o(b)"; 11741 /* Itbl support may require additional care here. */ 11742 coproc = 1; 11743 goto ld_st; 11744 case M_SDC3_AB: 11745 gas_assert (!mips_opts.micromips); 11746 s = "sdc3"; 11747 fmt = "E,o(b)"; 11748 /* Itbl support may require additional care here. */ 11749 coproc = 1; 11750 goto ld_st; 11751 case M_SDL_AB: 11752 s = "sdl"; 11753 fmt = MEM12_FMT; 11754 offbits = (mips_opts.micromips ? 12 : 16); 11755 goto ld_st; 11756 case M_SDR_AB: 11757 s = "sdr"; 11758 fmt = MEM12_FMT; 11759 offbits = (mips_opts.micromips ? 12 : 16); 11760 goto ld_st; 11761 case M_SWP_AB: 11762 gas_assert (mips_opts.micromips); 11763 s = "swp"; 11764 fmt = "t,~(b)"; 11765 offbits = 12; 11766 goto ld_st; 11767 case M_SDP_AB: 11768 gas_assert (mips_opts.micromips); 11769 s = "sdp"; 11770 fmt = "t,~(b)"; 11771 offbits = 12; 11772 goto ld_st; 11773 case M_SWM_AB: 11774 gas_assert (mips_opts.micromips); 11775 s = "swm"; 11776 fmt = "n,~(b)"; 11777 offbits = 12; 11778 goto ld_st; 11779 case M_SDM_AB: 11780 gas_assert (mips_opts.micromips); 11781 s = "sdm"; 11782 fmt = "n,~(b)"; 11783 offbits = 12; 11784 11785 ld_st: 11786 tempreg = AT; 11787 ld_noat: 11788 breg = op[2]; 11789 if (small_offset_p (0, align, 16)) 11790 { 11791 /* The first case exists for M_LD_AB and M_SD_AB, which are 11792 macros for o32 but which should act like normal instructions 11793 otherwise. */ 11794 if (offbits == 16) 11795 macro_build (&offset_expr, s, fmt, op[0], -1, offset_reloc[0], 11796 offset_reloc[1], offset_reloc[2], breg); 11797 else if (small_offset_p (0, align, offbits)) 11798 { 11799 if (offbits == 0) 11800 macro_build (NULL, s, fmt, op[0], breg); 11801 else 11802 macro_build (NULL, s, fmt, op[0], 11803 (int) offset_expr.X_add_number, breg); 11804 } 11805 else 11806 { 11807 if (tempreg == AT) 11808 used_at = 1; 11809 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 11810 tempreg, breg, -1, offset_reloc[0], 11811 offset_reloc[1], offset_reloc[2]); 11812 if (offbits == 0) 11813 macro_build (NULL, s, fmt, op[0], tempreg); 11814 else 11815 macro_build (NULL, s, fmt, op[0], 0, tempreg); 11816 } 11817 break; 11818 } 11819 11820 if (tempreg == AT) 11821 used_at = 1; 11822 11823 if (offset_expr.X_op != O_constant 11824 && offset_expr.X_op != O_symbol) 11825 { 11826 as_bad (_("expression too complex")); 11827 offset_expr.X_op = O_constant; 11828 } 11829 11830 if (HAVE_32BIT_ADDRESSES 11831 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) 11832 { 11833 char value [32]; 11834 11835 sprintf_vma (value, offset_expr.X_add_number); 11836 as_bad (_("number (0x%s) larger than 32 bits"), value); 11837 } 11838 11839 /* A constant expression in PIC code can be handled just as it 11840 is in non PIC code. */ 11841 if (offset_expr.X_op == O_constant) 11842 { 11843 expr1.X_add_number = offset_high_part (offset_expr.X_add_number, 11844 offbits == 0 ? 16 : offbits); 11845 offset_expr.X_add_number -= expr1.X_add_number; 11846 11847 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); 11848 if (breg != 0) 11849 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 11850 tempreg, tempreg, breg); 11851 if (offbits == 0) 11852 { 11853 if (offset_expr.X_add_number != 0) 11854 macro_build (&offset_expr, ADDRESS_ADDI_INSN, 11855 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16); 11856 macro_build (NULL, s, fmt, op[0], tempreg); 11857 } 11858 else if (offbits == 16) 11859 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, tempreg); 11860 else 11861 macro_build (NULL, s, fmt, op[0], 11862 (int) offset_expr.X_add_number, tempreg); 11863 } 11864 else if (offbits != 16) 11865 { 11866 /* The offset field is too narrow to be used for a low-part 11867 relocation, so load the whole address into the auxiliary 11868 register. */ 11869 load_address (tempreg, &offset_expr, &used_at); 11870 if (breg != 0) 11871 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 11872 tempreg, tempreg, breg); 11873 if (offbits == 0) 11874 macro_build (NULL, s, fmt, op[0], tempreg); 11875 else 11876 macro_build (NULL, s, fmt, op[0], 0, tempreg); 11877 } 11878 else if (mips_pic == NO_PIC) 11879 { 11880 /* If this is a reference to a GP relative symbol, and there 11881 is no base register, we want 11882 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16) 11883 Otherwise, if there is no base register, we want 11884 lui $tempreg,<sym> (BFD_RELOC_HI16_S) 11885 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) 11886 If we have a constant, we need two instructions anyhow, 11887 so we always use the latter form. 11888 11889 If we have a base register, and this is a reference to a 11890 GP relative symbol, we want 11891 addu $tempreg,$breg,$gp 11892 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16) 11893 Otherwise we want 11894 lui $tempreg,<sym> (BFD_RELOC_HI16_S) 11895 addu $tempreg,$tempreg,$breg 11896 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) 11897 With a constant we always use the latter case. 11898 11899 With 64bit address space and no base register and $at usable, 11900 we want 11901 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) 11902 lui $at,<sym> (BFD_RELOC_HI16_S) 11903 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) 11904 dsll32 $tempreg,0 11905 daddu $tempreg,$at 11906 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) 11907 If we have a base register, we want 11908 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) 11909 lui $at,<sym> (BFD_RELOC_HI16_S) 11910 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) 11911 daddu $at,$breg 11912 dsll32 $tempreg,0 11913 daddu $tempreg,$at 11914 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) 11915 11916 Without $at we can't generate the optimal path for superscalar 11917 processors here since this would require two temporary registers. 11918 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) 11919 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) 11920 dsll $tempreg,16 11921 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) 11922 dsll $tempreg,16 11923 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) 11924 If we have a base register, we want 11925 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) 11926 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) 11927 dsll $tempreg,16 11928 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) 11929 dsll $tempreg,16 11930 daddu $tempreg,$tempreg,$breg 11931 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) 11932 11933 For GP relative symbols in 64bit address space we can use 11934 the same sequence as in 32bit address space. */ 11935 if (HAVE_64BIT_SYMBOLS) 11936 { 11937 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET 11938 && !nopic_need_relax (offset_expr.X_add_symbol, 1)) 11939 { 11940 relax_start (offset_expr.X_add_symbol); 11941 if (breg == 0) 11942 { 11943 macro_build (&offset_expr, s, fmt, op[0], 11944 BFD_RELOC_GPREL16, mips_gp_register); 11945 } 11946 else 11947 { 11948 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 11949 tempreg, breg, mips_gp_register); 11950 macro_build (&offset_expr, s, fmt, op[0], 11951 BFD_RELOC_GPREL16, tempreg); 11952 } 11953 relax_switch (); 11954 } 11955 11956 if (used_at == 0 && mips_opts.at) 11957 { 11958 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, 11959 BFD_RELOC_MIPS_HIGHEST); 11960 macro_build (&offset_expr, "lui", LUI_FMT, AT, 11961 BFD_RELOC_HI16_S); 11962 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, 11963 tempreg, BFD_RELOC_MIPS_HIGHER); 11964 if (breg != 0) 11965 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); 11966 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); 11967 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); 11968 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, 11969 tempreg); 11970 used_at = 1; 11971 } 11972 else 11973 { 11974 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, 11975 BFD_RELOC_MIPS_HIGHEST); 11976 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, 11977 tempreg, BFD_RELOC_MIPS_HIGHER); 11978 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); 11979 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, 11980 tempreg, BFD_RELOC_HI16_S); 11981 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); 11982 if (breg != 0) 11983 macro_build (NULL, "daddu", "d,v,t", 11984 tempreg, tempreg, breg); 11985 macro_build (&offset_expr, s, fmt, op[0], 11986 BFD_RELOC_LO16, tempreg); 11987 } 11988 11989 if (mips_relax.sequence) 11990 relax_end (); 11991 break; 11992 } 11993 11994 if (breg == 0) 11995 { 11996 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET 11997 && !nopic_need_relax (offset_expr.X_add_symbol, 1)) 11998 { 11999 relax_start (offset_expr.X_add_symbol); 12000 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_GPREL16, 12001 mips_gp_register); 12002 relax_switch (); 12003 } 12004 macro_build_lui (&offset_expr, tempreg); 12005 macro_build (&offset_expr, s, fmt, op[0], 12006 BFD_RELOC_LO16, tempreg); 12007 if (mips_relax.sequence) 12008 relax_end (); 12009 } 12010 else 12011 { 12012 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET 12013 && !nopic_need_relax (offset_expr.X_add_symbol, 1)) 12014 { 12015 relax_start (offset_expr.X_add_symbol); 12016 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 12017 tempreg, breg, mips_gp_register); 12018 macro_build (&offset_expr, s, fmt, op[0], 12019 BFD_RELOC_GPREL16, tempreg); 12020 relax_switch (); 12021 } 12022 macro_build_lui (&offset_expr, tempreg); 12023 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 12024 tempreg, tempreg, breg); 12025 macro_build (&offset_expr, s, fmt, op[0], 12026 BFD_RELOC_LO16, tempreg); 12027 if (mips_relax.sequence) 12028 relax_end (); 12029 } 12030 } 12031 else if (!mips_big_got) 12032 { 12033 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; 12034 12035 /* If this is a reference to an external symbol, we want 12036 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 12037 nop 12038 <op> op[0],0($tempreg) 12039 Otherwise we want 12040 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 12041 nop 12042 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) 12043 <op> op[0],0($tempreg) 12044 12045 For NewABI, we want 12046 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) 12047 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) 12048 12049 If there is a base register, we add it to $tempreg before 12050 the <op>. If there is a constant, we stick it in the 12051 <op> instruction. We don't handle constants larger than 12052 16 bits, because we have no way to load the upper 16 bits 12053 (actually, we could handle them for the subset of cases 12054 in which we are not using $at). */ 12055 gas_assert (offset_expr.X_op == O_symbol); 12056 if (HAVE_NEWABI) 12057 { 12058 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 12059 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); 12060 if (breg != 0) 12061 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 12062 tempreg, tempreg, breg); 12063 macro_build (&offset_expr, s, fmt, op[0], 12064 BFD_RELOC_MIPS_GOT_OFST, tempreg); 12065 break; 12066 } 12067 expr1.X_add_number = offset_expr.X_add_number; 12068 offset_expr.X_add_number = 0; 12069 if (expr1.X_add_number < -0x8000 12070 || expr1.X_add_number >= 0x8000) 12071 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 12072 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 12073 lw_reloc_type, mips_gp_register); 12074 load_delay_nop (); 12075 relax_start (offset_expr.X_add_symbol); 12076 relax_switch (); 12077 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, 12078 tempreg, BFD_RELOC_LO16); 12079 relax_end (); 12080 if (breg != 0) 12081 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 12082 tempreg, tempreg, breg); 12083 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); 12084 } 12085 else if (mips_big_got && !HAVE_NEWABI) 12086 { 12087 int gpdelay; 12088 12089 /* If this is a reference to an external symbol, we want 12090 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 12091 addu $tempreg,$tempreg,$gp 12092 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 12093 <op> op[0],0($tempreg) 12094 Otherwise we want 12095 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 12096 nop 12097 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) 12098 <op> op[0],0($tempreg) 12099 If there is a base register, we add it to $tempreg before 12100 the <op>. If there is a constant, we stick it in the 12101 <op> instruction. We don't handle constants larger than 12102 16 bits, because we have no way to load the upper 16 bits 12103 (actually, we could handle them for the subset of cases 12104 in which we are not using $at). */ 12105 gas_assert (offset_expr.X_op == O_symbol); 12106 expr1.X_add_number = offset_expr.X_add_number; 12107 offset_expr.X_add_number = 0; 12108 if (expr1.X_add_number < -0x8000 12109 || expr1.X_add_number >= 0x8000) 12110 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 12111 gpdelay = reg_needs_delay (mips_gp_register); 12112 relax_start (offset_expr.X_add_symbol); 12113 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, 12114 BFD_RELOC_MIPS_GOT_HI16); 12115 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, 12116 mips_gp_register); 12117 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 12118 BFD_RELOC_MIPS_GOT_LO16, tempreg); 12119 relax_switch (); 12120 if (gpdelay) 12121 macro_build (NULL, "nop", ""); 12122 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 12123 BFD_RELOC_MIPS_GOT16, mips_gp_register); 12124 load_delay_nop (); 12125 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, 12126 tempreg, BFD_RELOC_LO16); 12127 relax_end (); 12128 12129 if (breg != 0) 12130 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 12131 tempreg, tempreg, breg); 12132 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); 12133 } 12134 else if (mips_big_got && HAVE_NEWABI) 12135 { 12136 /* If this is a reference to an external symbol, we want 12137 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 12138 add $tempreg,$tempreg,$gp 12139 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 12140 <op> op[0],<ofst>($tempreg) 12141 Otherwise, for local symbols, we want: 12142 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) 12143 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ 12144 gas_assert (offset_expr.X_op == O_symbol); 12145 expr1.X_add_number = offset_expr.X_add_number; 12146 offset_expr.X_add_number = 0; 12147 if (expr1.X_add_number < -0x8000 12148 || expr1.X_add_number >= 0x8000) 12149 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 12150 relax_start (offset_expr.X_add_symbol); 12151 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, 12152 BFD_RELOC_MIPS_GOT_HI16); 12153 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, 12154 mips_gp_register); 12155 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 12156 BFD_RELOC_MIPS_GOT_LO16, tempreg); 12157 if (breg != 0) 12158 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 12159 tempreg, tempreg, breg); 12160 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); 12161 12162 relax_switch (); 12163 offset_expr.X_add_number = expr1.X_add_number; 12164 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 12165 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); 12166 if (breg != 0) 12167 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 12168 tempreg, tempreg, breg); 12169 macro_build (&offset_expr, s, fmt, op[0], 12170 BFD_RELOC_MIPS_GOT_OFST, tempreg); 12171 relax_end (); 12172 } 12173 else 12174 abort (); 12175 12176 break; 12177 12178 case M_JRADDIUSP: 12179 gas_assert (mips_opts.micromips); 12180 gas_assert (mips_opts.insn32); 12181 start_noreorder (); 12182 macro_build (NULL, "jr", "s", RA); 12183 expr1.X_add_number = op[0] << 2; 12184 macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16); 12185 end_noreorder (); 12186 break; 12187 12188 case M_JRC: 12189 gas_assert (mips_opts.micromips); 12190 gas_assert (mips_opts.insn32); 12191 macro_build (NULL, "jr", "s", op[0]); 12192 if (mips_opts.noreorder) 12193 macro_build (NULL, "nop", ""); 12194 break; 12195 12196 case M_LI: 12197 case M_LI_S: 12198 load_register (op[0], &imm_expr, 0); 12199 break; 12200 12201 case M_DLI: 12202 load_register (op[0], &imm_expr, 1); 12203 break; 12204 12205 case M_LI_SS: 12206 if (imm_expr.X_op == O_constant) 12207 { 12208 used_at = 1; 12209 load_register (AT, &imm_expr, 0); 12210 macro_build (NULL, "mtc1", "t,G", AT, op[0]); 12211 break; 12212 } 12213 else 12214 { 12215 gas_assert (imm_expr.X_op == O_absent 12216 && offset_expr.X_op == O_symbol 12217 && strcmp (segment_name (S_GET_SEGMENT 12218 (offset_expr.X_add_symbol)), 12219 ".lit4") == 0 12220 && offset_expr.X_add_number == 0); 12221 macro_build (&offset_expr, "lwc1", "T,o(b)", op[0], 12222 BFD_RELOC_MIPS_LITERAL, mips_gp_register); 12223 break; 12224 } 12225 12226 case M_LI_D: 12227 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits 12228 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high 12229 order 32 bits of the value and the low order 32 bits are either 12230 zero or in OFFSET_EXPR. */ 12231 if (imm_expr.X_op == O_constant) 12232 { 12233 if (GPR_SIZE == 64) 12234 load_register (op[0], &imm_expr, 1); 12235 else 12236 { 12237 int hreg, lreg; 12238 12239 if (target_big_endian) 12240 { 12241 hreg = op[0]; 12242 lreg = op[0] + 1; 12243 } 12244 else 12245 { 12246 hreg = op[0] + 1; 12247 lreg = op[0]; 12248 } 12249 12250 if (hreg <= 31) 12251 load_register (hreg, &imm_expr, 0); 12252 if (lreg <= 31) 12253 { 12254 if (offset_expr.X_op == O_absent) 12255 move_register (lreg, 0); 12256 else 12257 { 12258 gas_assert (offset_expr.X_op == O_constant); 12259 load_register (lreg, &offset_expr, 0); 12260 } 12261 } 12262 } 12263 break; 12264 } 12265 gas_assert (imm_expr.X_op == O_absent); 12266 12267 /* We know that sym is in the .rdata section. First we get the 12268 upper 16 bits of the address. */ 12269 if (mips_pic == NO_PIC) 12270 { 12271 macro_build_lui (&offset_expr, AT); 12272 used_at = 1; 12273 } 12274 else 12275 { 12276 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, 12277 BFD_RELOC_MIPS_GOT16, mips_gp_register); 12278 used_at = 1; 12279 } 12280 12281 /* Now we load the register(s). */ 12282 if (GPR_SIZE == 64) 12283 { 12284 used_at = 1; 12285 macro_build (&offset_expr, "ld", "t,o(b)", op[0], 12286 BFD_RELOC_LO16, AT); 12287 } 12288 else 12289 { 12290 used_at = 1; 12291 macro_build (&offset_expr, "lw", "t,o(b)", op[0], 12292 BFD_RELOC_LO16, AT); 12293 if (op[0] != RA) 12294 { 12295 /* FIXME: How in the world do we deal with the possible 12296 overflow here? */ 12297 offset_expr.X_add_number += 4; 12298 macro_build (&offset_expr, "lw", "t,o(b)", 12299 op[0] + 1, BFD_RELOC_LO16, AT); 12300 } 12301 } 12302 break; 12303 12304 case M_LI_DD: 12305 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits 12306 wide, IMM_EXPR is the entire value and the GPRs are known to be 64 12307 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of 12308 the value and the low order 32 bits are either zero or in 12309 OFFSET_EXPR. */ 12310 if (imm_expr.X_op == O_constant) 12311 { 12312 used_at = 1; 12313 load_register (AT, &imm_expr, FPR_SIZE == 64); 12314 if (FPR_SIZE == 64 && GPR_SIZE == 64) 12315 macro_build (NULL, "dmtc1", "t,S", AT, op[0]); 12316 else 12317 { 12318 if (ISA_HAS_MXHC1 (mips_opts.isa)) 12319 macro_build (NULL, "mthc1", "t,G", AT, op[0]); 12320 else if (FPR_SIZE != 32) 12321 as_bad (_("Unable to generate `%s' compliant code " 12322 "without mthc1"), 12323 (FPR_SIZE == 64) ? "fp64" : "fpxx"); 12324 else 12325 macro_build (NULL, "mtc1", "t,G", AT, op[0] + 1); 12326 if (offset_expr.X_op == O_absent) 12327 macro_build (NULL, "mtc1", "t,G", 0, op[0]); 12328 else 12329 { 12330 gas_assert (offset_expr.X_op == O_constant); 12331 load_register (AT, &offset_expr, 0); 12332 macro_build (NULL, "mtc1", "t,G", AT, op[0]); 12333 } 12334 } 12335 break; 12336 } 12337 12338 gas_assert (imm_expr.X_op == O_absent 12339 && offset_expr.X_op == O_symbol 12340 && offset_expr.X_add_number == 0); 12341 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); 12342 if (strcmp (s, ".lit8") == 0) 12343 { 12344 op[2] = mips_gp_register; 12345 offset_reloc[0] = BFD_RELOC_MIPS_LITERAL; 12346 offset_reloc[1] = BFD_RELOC_UNUSED; 12347 offset_reloc[2] = BFD_RELOC_UNUSED; 12348 } 12349 else 12350 { 12351 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0); 12352 used_at = 1; 12353 if (mips_pic != NO_PIC) 12354 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, 12355 BFD_RELOC_MIPS_GOT16, mips_gp_register); 12356 else 12357 { 12358 /* FIXME: This won't work for a 64 bit address. */ 12359 macro_build_lui (&offset_expr, AT); 12360 } 12361 12362 op[2] = AT; 12363 offset_reloc[0] = BFD_RELOC_LO16; 12364 offset_reloc[1] = BFD_RELOC_UNUSED; 12365 offset_reloc[2] = BFD_RELOC_UNUSED; 12366 } 12367 align = 8; 12368 /* Fall through */ 12369 12370 case M_L_DAB: 12371 /* 12372 * The MIPS assembler seems to check for X_add_number not 12373 * being double aligned and generating: 12374 * lui at,%hi(foo+1) 12375 * addu at,at,v1 12376 * addiu at,at,%lo(foo+1) 12377 * lwc1 f2,0(at) 12378 * lwc1 f3,4(at) 12379 * But, the resulting address is the same after relocation so why 12380 * generate the extra instruction? 12381 */ 12382 /* Itbl support may require additional care here. */ 12383 coproc = 1; 12384 fmt = "T,o(b)"; 12385 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) 12386 { 12387 s = "ldc1"; 12388 goto ld_st; 12389 } 12390 s = "lwc1"; 12391 goto ldd_std; 12392 12393 case M_S_DAB: 12394 gas_assert (!mips_opts.micromips); 12395 /* Itbl support may require additional care here. */ 12396 coproc = 1; 12397 fmt = "T,o(b)"; 12398 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) 12399 { 12400 s = "sdc1"; 12401 goto ld_st; 12402 } 12403 s = "swc1"; 12404 goto ldd_std; 12405 12406 case M_LQ_AB: 12407 fmt = "t,o(b)"; 12408 s = "lq"; 12409 goto ld; 12410 12411 case M_SQ_AB: 12412 fmt = "t,o(b)"; 12413 s = "sq"; 12414 goto ld_st; 12415 12416 case M_LD_AB: 12417 fmt = "t,o(b)"; 12418 if (GPR_SIZE == 64) 12419 { 12420 s = "ld"; 12421 goto ld; 12422 } 12423 s = "lw"; 12424 goto ldd_std; 12425 12426 case M_SD_AB: 12427 fmt = "t,o(b)"; 12428 if (GPR_SIZE == 64) 12429 { 12430 s = "sd"; 12431 goto ld_st; 12432 } 12433 s = "sw"; 12434 12435 ldd_std: 12436 /* Even on a big endian machine $fn comes before $fn+1. We have 12437 to adjust when loading from memory. We set coproc if we must 12438 load $fn+1 first. */ 12439 /* Itbl support may require additional care here. */ 12440 if (!target_big_endian) 12441 coproc = 0; 12442 12443 breg = op[2]; 12444 if (small_offset_p (0, align, 16)) 12445 { 12446 ep = &offset_expr; 12447 if (!small_offset_p (4, align, 16)) 12448 { 12449 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, breg, 12450 -1, offset_reloc[0], offset_reloc[1], 12451 offset_reloc[2]); 12452 expr1.X_add_number = 0; 12453 ep = &expr1; 12454 breg = AT; 12455 used_at = 1; 12456 offset_reloc[0] = BFD_RELOC_LO16; 12457 offset_reloc[1] = BFD_RELOC_UNUSED; 12458 offset_reloc[2] = BFD_RELOC_UNUSED; 12459 } 12460 if (strcmp (s, "lw") == 0 && op[0] == breg) 12461 { 12462 ep->X_add_number += 4; 12463 macro_build (ep, s, fmt, op[0] + 1, -1, offset_reloc[0], 12464 offset_reloc[1], offset_reloc[2], breg); 12465 ep->X_add_number -= 4; 12466 macro_build (ep, s, fmt, op[0], -1, offset_reloc[0], 12467 offset_reloc[1], offset_reloc[2], breg); 12468 } 12469 else 12470 { 12471 macro_build (ep, s, fmt, coproc ? op[0] + 1 : op[0], -1, 12472 offset_reloc[0], offset_reloc[1], offset_reloc[2], 12473 breg); 12474 ep->X_add_number += 4; 12475 macro_build (ep, s, fmt, coproc ? op[0] : op[0] + 1, -1, 12476 offset_reloc[0], offset_reloc[1], offset_reloc[2], 12477 breg); 12478 } 12479 break; 12480 } 12481 12482 if (offset_expr.X_op != O_symbol 12483 && offset_expr.X_op != O_constant) 12484 { 12485 as_bad (_("expression too complex")); 12486 offset_expr.X_op = O_constant; 12487 } 12488 12489 if (HAVE_32BIT_ADDRESSES 12490 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) 12491 { 12492 char value [32]; 12493 12494 sprintf_vma (value, offset_expr.X_add_number); 12495 as_bad (_("number (0x%s) larger than 32 bits"), value); 12496 } 12497 12498 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant) 12499 { 12500 /* If this is a reference to a GP relative symbol, we want 12501 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16) 12502 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16) 12503 If we have a base register, we use this 12504 addu $at,$breg,$gp 12505 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16) 12506 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16) 12507 If this is not a GP relative symbol, we want 12508 lui $at,<sym> (BFD_RELOC_HI16_S) 12509 <op> op[0],<sym>($at) (BFD_RELOC_LO16) 12510 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) 12511 If there is a base register, we add it to $at after the 12512 lui instruction. If there is a constant, we always use 12513 the last case. */ 12514 if (offset_expr.X_op == O_symbol 12515 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET 12516 && !nopic_need_relax (offset_expr.X_add_symbol, 1)) 12517 { 12518 relax_start (offset_expr.X_add_symbol); 12519 if (breg == 0) 12520 { 12521 tempreg = mips_gp_register; 12522 } 12523 else 12524 { 12525 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 12526 AT, breg, mips_gp_register); 12527 tempreg = AT; 12528 used_at = 1; 12529 } 12530 12531 /* Itbl support may require additional care here. */ 12532 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], 12533 BFD_RELOC_GPREL16, tempreg); 12534 offset_expr.X_add_number += 4; 12535 12536 /* Set mips_optimize to 2 to avoid inserting an 12537 undesired nop. */ 12538 hold_mips_optimize = mips_optimize; 12539 mips_optimize = 2; 12540 /* Itbl support may require additional care here. */ 12541 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, 12542 BFD_RELOC_GPREL16, tempreg); 12543 mips_optimize = hold_mips_optimize; 12544 12545 relax_switch (); 12546 12547 offset_expr.X_add_number -= 4; 12548 } 12549 used_at = 1; 12550 if (offset_high_part (offset_expr.X_add_number, 16) 12551 != offset_high_part (offset_expr.X_add_number + 4, 16)) 12552 { 12553 load_address (AT, &offset_expr, &used_at); 12554 offset_expr.X_op = O_constant; 12555 offset_expr.X_add_number = 0; 12556 } 12557 else 12558 macro_build_lui (&offset_expr, AT); 12559 if (breg != 0) 12560 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); 12561 /* Itbl support may require additional care here. */ 12562 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], 12563 BFD_RELOC_LO16, AT); 12564 /* FIXME: How do we handle overflow here? */ 12565 offset_expr.X_add_number += 4; 12566 /* Itbl support may require additional care here. */ 12567 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, 12568 BFD_RELOC_LO16, AT); 12569 if (mips_relax.sequence) 12570 relax_end (); 12571 } 12572 else if (!mips_big_got) 12573 { 12574 /* If this is a reference to an external symbol, we want 12575 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 12576 nop 12577 <op> op[0],0($at) 12578 <op> op[0]+1,4($at) 12579 Otherwise we want 12580 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 12581 nop 12582 <op> op[0],<sym>($at) (BFD_RELOC_LO16) 12583 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) 12584 If there is a base register we add it to $at before the 12585 lwc1 instructions. If there is a constant we include it 12586 in the lwc1 instructions. */ 12587 used_at = 1; 12588 expr1.X_add_number = offset_expr.X_add_number; 12589 if (expr1.X_add_number < -0x8000 12590 || expr1.X_add_number >= 0x8000 - 4) 12591 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 12592 load_got_offset (AT, &offset_expr); 12593 load_delay_nop (); 12594 if (breg != 0) 12595 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); 12596 12597 /* Set mips_optimize to 2 to avoid inserting an undesired 12598 nop. */ 12599 hold_mips_optimize = mips_optimize; 12600 mips_optimize = 2; 12601 12602 /* Itbl support may require additional care here. */ 12603 relax_start (offset_expr.X_add_symbol); 12604 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0], 12605 BFD_RELOC_LO16, AT); 12606 expr1.X_add_number += 4; 12607 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1, 12608 BFD_RELOC_LO16, AT); 12609 relax_switch (); 12610 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], 12611 BFD_RELOC_LO16, AT); 12612 offset_expr.X_add_number += 4; 12613 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, 12614 BFD_RELOC_LO16, AT); 12615 relax_end (); 12616 12617 mips_optimize = hold_mips_optimize; 12618 } 12619 else if (mips_big_got) 12620 { 12621 int gpdelay; 12622 12623 /* If this is a reference to an external symbol, we want 12624 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) 12625 addu $at,$at,$gp 12626 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) 12627 nop 12628 <op> op[0],0($at) 12629 <op> op[0]+1,4($at) 12630 Otherwise we want 12631 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 12632 nop 12633 <op> op[0],<sym>($at) (BFD_RELOC_LO16) 12634 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) 12635 If there is a base register we add it to $at before the 12636 lwc1 instructions. If there is a constant we include it 12637 in the lwc1 instructions. */ 12638 used_at = 1; 12639 expr1.X_add_number = offset_expr.X_add_number; 12640 offset_expr.X_add_number = 0; 12641 if (expr1.X_add_number < -0x8000 12642 || expr1.X_add_number >= 0x8000 - 4) 12643 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 12644 gpdelay = reg_needs_delay (mips_gp_register); 12645 relax_start (offset_expr.X_add_symbol); 12646 macro_build (&offset_expr, "lui", LUI_FMT, 12647 AT, BFD_RELOC_MIPS_GOT_HI16); 12648 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 12649 AT, AT, mips_gp_register); 12650 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 12651 AT, BFD_RELOC_MIPS_GOT_LO16, AT); 12652 load_delay_nop (); 12653 if (breg != 0) 12654 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); 12655 /* Itbl support may require additional care here. */ 12656 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0], 12657 BFD_RELOC_LO16, AT); 12658 expr1.X_add_number += 4; 12659 12660 /* Set mips_optimize to 2 to avoid inserting an undesired 12661 nop. */ 12662 hold_mips_optimize = mips_optimize; 12663 mips_optimize = 2; 12664 /* Itbl support may require additional care here. */ 12665 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1, 12666 BFD_RELOC_LO16, AT); 12667 mips_optimize = hold_mips_optimize; 12668 expr1.X_add_number -= 4; 12669 12670 relax_switch (); 12671 offset_expr.X_add_number = expr1.X_add_number; 12672 if (gpdelay) 12673 macro_build (NULL, "nop", ""); 12674 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, 12675 BFD_RELOC_MIPS_GOT16, mips_gp_register); 12676 load_delay_nop (); 12677 if (breg != 0) 12678 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); 12679 /* Itbl support may require additional care here. */ 12680 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], 12681 BFD_RELOC_LO16, AT); 12682 offset_expr.X_add_number += 4; 12683 12684 /* Set mips_optimize to 2 to avoid inserting an undesired 12685 nop. */ 12686 hold_mips_optimize = mips_optimize; 12687 mips_optimize = 2; 12688 /* Itbl support may require additional care here. */ 12689 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, 12690 BFD_RELOC_LO16, AT); 12691 mips_optimize = hold_mips_optimize; 12692 relax_end (); 12693 } 12694 else 12695 abort (); 12696 12697 break; 12698 12699 case M_SAA_AB: 12700 s = "saa"; 12701 goto saa_saad; 12702 case M_SAAD_AB: 12703 s = "saad"; 12704 saa_saad: 12705 gas_assert (!mips_opts.micromips); 12706 offbits = 0; 12707 fmt = "t,(b)"; 12708 goto ld_st; 12709 12710 /* New code added to support COPZ instructions. 12711 This code builds table entries out of the macros in mip_opcodes. 12712 R4000 uses interlocks to handle coproc delays. 12713 Other chips (like the R3000) require nops to be inserted for delays. 12714 12715 FIXME: Currently, we require that the user handle delays. 12716 In order to fill delay slots for non-interlocked chips, 12717 we must have a way to specify delays based on the coprocessor. 12718 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. 12719 What are the side-effects of the cop instruction? 12720 What cache support might we have and what are its effects? 12721 Both coprocessor & memory require delays. how long??? 12722 What registers are read/set/modified? 12723 12724 If an itbl is provided to interpret cop instructions, 12725 this knowledge can be encoded in the itbl spec. */ 12726 12727 case M_COP0: 12728 s = "c0"; 12729 goto copz; 12730 case M_COP1: 12731 s = "c1"; 12732 goto copz; 12733 case M_COP2: 12734 s = "c2"; 12735 goto copz; 12736 case M_COP3: 12737 s = "c3"; 12738 copz: 12739 gas_assert (!mips_opts.micromips); 12740 /* For now we just do C (same as Cz). The parameter will be 12741 stored in insn_opcode by mips_ip. */ 12742 macro_build (NULL, s, "C", (int) ip->insn_opcode); 12743 break; 12744 12745 case M_MOVE: 12746 move_register (op[0], op[1]); 12747 break; 12748 12749 case M_MOVEP: 12750 gas_assert (mips_opts.micromips); 12751 gas_assert (mips_opts.insn32); 12752 move_register (micromips_to_32_reg_h_map1[op[0]], 12753 micromips_to_32_reg_m_map[op[1]]); 12754 move_register (micromips_to_32_reg_h_map2[op[0]], 12755 micromips_to_32_reg_n_map[op[2]]); 12756 break; 12757 12758 case M_DMUL: 12759 dbl = 1; 12760 /* Fall through. */ 12761 case M_MUL: 12762 if (mips_opts.arch == CPU_R5900) 12763 macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", op[0], op[1], 12764 op[2]); 12765 else 12766 { 12767 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", op[1], op[2]); 12768 macro_build (NULL, "mflo", MFHL_FMT, op[0]); 12769 } 12770 break; 12771 12772 case M_DMUL_I: 12773 dbl = 1; 12774 /* Fall through. */ 12775 case M_MUL_I: 12776 /* The MIPS assembler some times generates shifts and adds. I'm 12777 not trying to be that fancy. GCC should do this for us 12778 anyway. */ 12779 used_at = 1; 12780 load_register (AT, &imm_expr, dbl); 12781 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", op[1], AT); 12782 macro_build (NULL, "mflo", MFHL_FMT, op[0]); 12783 break; 12784 12785 case M_DMULO_I: 12786 dbl = 1; 12787 /* Fall through. */ 12788 case M_MULO_I: 12789 imm = 1; 12790 goto do_mulo; 12791 12792 case M_DMULO: 12793 dbl = 1; 12794 /* Fall through. */ 12795 case M_MULO: 12796 do_mulo: 12797 start_noreorder (); 12798 used_at = 1; 12799 if (imm) 12800 load_register (AT, &imm_expr, dbl); 12801 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", 12802 op[1], imm ? AT : op[2]); 12803 macro_build (NULL, "mflo", MFHL_FMT, op[0]); 12804 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, op[0], op[0], 31); 12805 macro_build (NULL, "mfhi", MFHL_FMT, AT); 12806 if (mips_trap) 12807 macro_build (NULL, "tne", TRAP_FMT, op[0], AT, 6); 12808 else 12809 { 12810 if (mips_opts.micromips) 12811 micromips_label_expr (&label_expr); 12812 else 12813 label_expr.X_add_number = 8; 12814 macro_build (&label_expr, "beq", "s,t,p", op[0], AT); 12815 macro_build (NULL, "nop", ""); 12816 macro_build (NULL, "break", BRK_FMT, 6); 12817 if (mips_opts.micromips) 12818 micromips_add_label (); 12819 } 12820 end_noreorder (); 12821 macro_build (NULL, "mflo", MFHL_FMT, op[0]); 12822 break; 12823 12824 case M_DMULOU_I: 12825 dbl = 1; 12826 /* Fall through. */ 12827 case M_MULOU_I: 12828 imm = 1; 12829 goto do_mulou; 12830 12831 case M_DMULOU: 12832 dbl = 1; 12833 /* Fall through. */ 12834 case M_MULOU: 12835 do_mulou: 12836 start_noreorder (); 12837 used_at = 1; 12838 if (imm) 12839 load_register (AT, &imm_expr, dbl); 12840 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", 12841 op[1], imm ? AT : op[2]); 12842 macro_build (NULL, "mfhi", MFHL_FMT, AT); 12843 macro_build (NULL, "mflo", MFHL_FMT, op[0]); 12844 if (mips_trap) 12845 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6); 12846 else 12847 { 12848 if (mips_opts.micromips) 12849 micromips_label_expr (&label_expr); 12850 else 12851 label_expr.X_add_number = 8; 12852 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO); 12853 macro_build (NULL, "nop", ""); 12854 macro_build (NULL, "break", BRK_FMT, 6); 12855 if (mips_opts.micromips) 12856 micromips_add_label (); 12857 } 12858 end_noreorder (); 12859 break; 12860 12861 case M_DROL: 12862 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) 12863 { 12864 if (op[0] == op[1]) 12865 { 12866 tempreg = AT; 12867 used_at = 1; 12868 } 12869 else 12870 tempreg = op[0]; 12871 macro_build (NULL, "dnegu", "d,w", tempreg, op[2]); 12872 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], tempreg); 12873 break; 12874 } 12875 used_at = 1; 12876 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]); 12877 macro_build (NULL, "dsrlv", "d,t,s", AT, op[1], AT); 12878 macro_build (NULL, "dsllv", "d,t,s", op[0], op[1], op[2]); 12879 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); 12880 break; 12881 12882 case M_ROL: 12883 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) 12884 { 12885 if (op[0] == op[1]) 12886 { 12887 tempreg = AT; 12888 used_at = 1; 12889 } 12890 else 12891 tempreg = op[0]; 12892 macro_build (NULL, "negu", "d,w", tempreg, op[2]); 12893 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], tempreg); 12894 break; 12895 } 12896 used_at = 1; 12897 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]); 12898 macro_build (NULL, "srlv", "d,t,s", AT, op[1], AT); 12899 macro_build (NULL, "sllv", "d,t,s", op[0], op[1], op[2]); 12900 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); 12901 break; 12902 12903 case M_DROL_I: 12904 { 12905 unsigned int rot; 12906 const char *l; 12907 const char *rr; 12908 12909 rot = imm_expr.X_add_number & 0x3f; 12910 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) 12911 { 12912 rot = (64 - rot) & 0x3f; 12913 if (rot >= 32) 12914 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32); 12915 else 12916 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot); 12917 break; 12918 } 12919 if (rot == 0) 12920 { 12921 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0); 12922 break; 12923 } 12924 l = (rot < 0x20) ? "dsll" : "dsll32"; 12925 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; 12926 rot &= 0x1f; 12927 used_at = 1; 12928 macro_build (NULL, l, SHFT_FMT, AT, op[1], rot); 12929 macro_build (NULL, rr, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); 12930 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); 12931 } 12932 break; 12933 12934 case M_ROL_I: 12935 { 12936 unsigned int rot; 12937 12938 rot = imm_expr.X_add_number & 0x1f; 12939 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) 12940 { 12941 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], 12942 (32 - rot) & 0x1f); 12943 break; 12944 } 12945 if (rot == 0) 12946 { 12947 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0); 12948 break; 12949 } 12950 used_at = 1; 12951 macro_build (NULL, "sll", SHFT_FMT, AT, op[1], rot); 12952 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); 12953 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); 12954 } 12955 break; 12956 12957 case M_DROR: 12958 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) 12959 { 12960 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], op[2]); 12961 break; 12962 } 12963 used_at = 1; 12964 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]); 12965 macro_build (NULL, "dsllv", "d,t,s", AT, op[1], AT); 12966 macro_build (NULL, "dsrlv", "d,t,s", op[0], op[1], op[2]); 12967 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); 12968 break; 12969 12970 case M_ROR: 12971 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) 12972 { 12973 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], op[2]); 12974 break; 12975 } 12976 used_at = 1; 12977 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]); 12978 macro_build (NULL, "sllv", "d,t,s", AT, op[1], AT); 12979 macro_build (NULL, "srlv", "d,t,s", op[0], op[1], op[2]); 12980 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); 12981 break; 12982 12983 case M_DROR_I: 12984 { 12985 unsigned int rot; 12986 const char *l; 12987 const char *rr; 12988 12989 rot = imm_expr.X_add_number & 0x3f; 12990 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) 12991 { 12992 if (rot >= 32) 12993 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32); 12994 else 12995 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot); 12996 break; 12997 } 12998 if (rot == 0) 12999 { 13000 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0); 13001 break; 13002 } 13003 rr = (rot < 0x20) ? "dsrl" : "dsrl32"; 13004 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; 13005 rot &= 0x1f; 13006 used_at = 1; 13007 macro_build (NULL, rr, SHFT_FMT, AT, op[1], rot); 13008 macro_build (NULL, l, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); 13009 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); 13010 } 13011 break; 13012 13013 case M_ROR_I: 13014 { 13015 unsigned int rot; 13016 13017 rot = imm_expr.X_add_number & 0x1f; 13018 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) 13019 { 13020 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], rot); 13021 break; 13022 } 13023 if (rot == 0) 13024 { 13025 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0); 13026 break; 13027 } 13028 used_at = 1; 13029 macro_build (NULL, "srl", SHFT_FMT, AT, op[1], rot); 13030 macro_build (NULL, "sll", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); 13031 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); 13032 } 13033 break; 13034 13035 case M_SEQ: 13036 if (op[1] == 0) 13037 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[2], BFD_RELOC_LO16); 13038 else if (op[2] == 0) 13039 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16); 13040 else 13041 { 13042 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]); 13043 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16); 13044 } 13045 break; 13046 13047 case M_SEQ_I: 13048 if (imm_expr.X_add_number == 0) 13049 { 13050 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16); 13051 break; 13052 } 13053 if (op[1] == 0) 13054 { 13055 as_warn (_("instruction %s: result is always false"), 13056 ip->insn_mo->name); 13057 move_register (op[0], 0); 13058 break; 13059 } 13060 if (CPU_HAS_SEQ (mips_opts.arch) 13061 && -512 <= imm_expr.X_add_number 13062 && imm_expr.X_add_number < 512) 13063 { 13064 macro_build (NULL, "seqi", "t,r,+Q", op[0], op[1], 13065 (int) imm_expr.X_add_number); 13066 break; 13067 } 13068 if (imm_expr.X_add_number >= 0 13069 && imm_expr.X_add_number < 0x10000) 13070 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], BFD_RELOC_LO16); 13071 else if (imm_expr.X_add_number > -0x8000 13072 && imm_expr.X_add_number < 0) 13073 { 13074 imm_expr.X_add_number = -imm_expr.X_add_number; 13075 macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu", 13076 "t,r,j", op[0], op[1], BFD_RELOC_LO16); 13077 } 13078 else if (CPU_HAS_SEQ (mips_opts.arch)) 13079 { 13080 used_at = 1; 13081 load_register (AT, &imm_expr, GPR_SIZE == 64); 13082 macro_build (NULL, "seq", "d,v,t", op[0], op[1], AT); 13083 break; 13084 } 13085 else 13086 { 13087 load_register (AT, &imm_expr, GPR_SIZE == 64); 13088 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT); 13089 used_at = 1; 13090 } 13091 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16); 13092 break; 13093 13094 case M_SGE: /* X >= Y <==> not (X < Y) */ 13095 s = "slt"; 13096 goto sge; 13097 case M_SGEU: 13098 s = "sltu"; 13099 sge: 13100 macro_build (NULL, s, "d,v,t", op[0], op[1], op[2]); 13101 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); 13102 break; 13103 13104 case M_SGE_I: /* X >= I <==> not (X < I) */ 13105 case M_SGEU_I: 13106 if (imm_expr.X_add_number >= -0x8000 13107 && imm_expr.X_add_number < 0x8000) 13108 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", 13109 op[0], op[1], BFD_RELOC_LO16); 13110 else 13111 { 13112 load_register (AT, &imm_expr, GPR_SIZE == 64); 13113 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", 13114 op[0], op[1], AT); 13115 used_at = 1; 13116 } 13117 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); 13118 break; 13119 13120 case M_SGT: /* X > Y <==> Y < X */ 13121 s = "slt"; 13122 goto sgt; 13123 case M_SGTU: 13124 s = "sltu"; 13125 sgt: 13126 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]); 13127 break; 13128 13129 case M_SGT_I: /* X > I <==> I < X */ 13130 s = "slt"; 13131 goto sgti; 13132 case M_SGTU_I: 13133 s = "sltu"; 13134 sgti: 13135 used_at = 1; 13136 load_register (AT, &imm_expr, GPR_SIZE == 64); 13137 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]); 13138 break; 13139 13140 case M_SLE: /* X <= Y <==> Y >= X <==> not (Y < X) */ 13141 s = "slt"; 13142 goto sle; 13143 case M_SLEU: 13144 s = "sltu"; 13145 sle: 13146 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]); 13147 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); 13148 break; 13149 13150 case M_SLE_I: /* X <= I <==> I >= X <==> not (I < X) */ 13151 s = "slt"; 13152 goto slei; 13153 case M_SLEU_I: 13154 s = "sltu"; 13155 slei: 13156 used_at = 1; 13157 load_register (AT, &imm_expr, GPR_SIZE == 64); 13158 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]); 13159 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); 13160 break; 13161 13162 case M_SLT_I: 13163 if (imm_expr.X_add_number >= -0x8000 13164 && imm_expr.X_add_number < 0x8000) 13165 { 13166 macro_build (&imm_expr, "slti", "t,r,j", op[0], op[1], 13167 BFD_RELOC_LO16); 13168 break; 13169 } 13170 used_at = 1; 13171 load_register (AT, &imm_expr, GPR_SIZE == 64); 13172 macro_build (NULL, "slt", "d,v,t", op[0], op[1], AT); 13173 break; 13174 13175 case M_SLTU_I: 13176 if (imm_expr.X_add_number >= -0x8000 13177 && imm_expr.X_add_number < 0x8000) 13178 { 13179 macro_build (&imm_expr, "sltiu", "t,r,j", op[0], op[1], 13180 BFD_RELOC_LO16); 13181 break; 13182 } 13183 used_at = 1; 13184 load_register (AT, &imm_expr, GPR_SIZE == 64); 13185 macro_build (NULL, "sltu", "d,v,t", op[0], op[1], AT); 13186 break; 13187 13188 case M_SNE: 13189 if (op[1] == 0) 13190 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[2]); 13191 else if (op[2] == 0) 13192 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]); 13193 else 13194 { 13195 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]); 13196 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]); 13197 } 13198 break; 13199 13200 case M_SNE_I: 13201 if (imm_expr.X_add_number == 0) 13202 { 13203 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]); 13204 break; 13205 } 13206 if (op[1] == 0) 13207 { 13208 as_warn (_("instruction %s: result is always true"), 13209 ip->insn_mo->name); 13210 macro_build (&expr1, GPR_SIZE == 32 ? "addiu" : "daddiu", "t,r,j", 13211 op[0], 0, BFD_RELOC_LO16); 13212 break; 13213 } 13214 if (CPU_HAS_SEQ (mips_opts.arch) 13215 && -512 <= imm_expr.X_add_number 13216 && imm_expr.X_add_number < 512) 13217 { 13218 macro_build (NULL, "snei", "t,r,+Q", op[0], op[1], 13219 (int) imm_expr.X_add_number); 13220 break; 13221 } 13222 if (imm_expr.X_add_number >= 0 13223 && imm_expr.X_add_number < 0x10000) 13224 { 13225 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], 13226 BFD_RELOC_LO16); 13227 } 13228 else if (imm_expr.X_add_number > -0x8000 13229 && imm_expr.X_add_number < 0) 13230 { 13231 imm_expr.X_add_number = -imm_expr.X_add_number; 13232 macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu", 13233 "t,r,j", op[0], op[1], BFD_RELOC_LO16); 13234 } 13235 else if (CPU_HAS_SEQ (mips_opts.arch)) 13236 { 13237 used_at = 1; 13238 load_register (AT, &imm_expr, GPR_SIZE == 64); 13239 macro_build (NULL, "sne", "d,v,t", op[0], op[1], AT); 13240 break; 13241 } 13242 else 13243 { 13244 load_register (AT, &imm_expr, GPR_SIZE == 64); 13245 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT); 13246 used_at = 1; 13247 } 13248 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]); 13249 break; 13250 13251 case M_SUB_I: 13252 s = "addi"; 13253 s2 = "sub"; 13254 goto do_subi; 13255 case M_SUBU_I: 13256 s = "addiu"; 13257 s2 = "subu"; 13258 goto do_subi; 13259 case M_DSUB_I: 13260 dbl = 1; 13261 s = "daddi"; 13262 s2 = "dsub"; 13263 if (!mips_opts.micromips) 13264 goto do_subi; 13265 if (imm_expr.X_add_number > -0x200 13266 && imm_expr.X_add_number <= 0x200) 13267 { 13268 macro_build (NULL, s, "t,r,.", op[0], op[1], 13269 (int) -imm_expr.X_add_number); 13270 break; 13271 } 13272 goto do_subi_i; 13273 case M_DSUBU_I: 13274 dbl = 1; 13275 s = "daddiu"; 13276 s2 = "dsubu"; 13277 do_subi: 13278 if (imm_expr.X_add_number > -0x8000 13279 && imm_expr.X_add_number <= 0x8000) 13280 { 13281 imm_expr.X_add_number = -imm_expr.X_add_number; 13282 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16); 13283 break; 13284 } 13285 do_subi_i: 13286 used_at = 1; 13287 load_register (AT, &imm_expr, dbl); 13288 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); 13289 break; 13290 13291 case M_TEQ_I: 13292 s = "teq"; 13293 goto trap; 13294 case M_TGE_I: 13295 s = "tge"; 13296 goto trap; 13297 case M_TGEU_I: 13298 s = "tgeu"; 13299 goto trap; 13300 case M_TLT_I: 13301 s = "tlt"; 13302 goto trap; 13303 case M_TLTU_I: 13304 s = "tltu"; 13305 goto trap; 13306 case M_TNE_I: 13307 s = "tne"; 13308 trap: 13309 used_at = 1; 13310 load_register (AT, &imm_expr, GPR_SIZE == 64); 13311 macro_build (NULL, s, "s,t", op[0], AT); 13312 break; 13313 13314 case M_TRUNCWS: 13315 case M_TRUNCWD: 13316 gas_assert (!mips_opts.micromips); 13317 gas_assert (mips_opts.isa == ISA_MIPS1); 13318 used_at = 1; 13319 13320 /* 13321 * Is the double cfc1 instruction a bug in the mips assembler; 13322 * or is there a reason for it? 13323 */ 13324 start_noreorder (); 13325 macro_build (NULL, "cfc1", "t,G", op[2], RA); 13326 macro_build (NULL, "cfc1", "t,G", op[2], RA); 13327 macro_build (NULL, "nop", ""); 13328 expr1.X_add_number = 3; 13329 macro_build (&expr1, "ori", "t,r,i", AT, op[2], BFD_RELOC_LO16); 13330 expr1.X_add_number = 2; 13331 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); 13332 macro_build (NULL, "ctc1", "t,G", AT, RA); 13333 macro_build (NULL, "nop", ""); 13334 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", 13335 op[0], op[1]); 13336 macro_build (NULL, "ctc1", "t,G", op[2], RA); 13337 macro_build (NULL, "nop", ""); 13338 end_noreorder (); 13339 break; 13340 13341 case M_ULH_AB: 13342 s = "lb"; 13343 s2 = "lbu"; 13344 off = 1; 13345 goto uld_st; 13346 case M_ULHU_AB: 13347 s = "lbu"; 13348 s2 = "lbu"; 13349 off = 1; 13350 goto uld_st; 13351 case M_ULW_AB: 13352 s = "lwl"; 13353 s2 = "lwr"; 13354 offbits = (mips_opts.micromips ? 12 : 16); 13355 off = 3; 13356 goto uld_st; 13357 case M_ULD_AB: 13358 s = "ldl"; 13359 s2 = "ldr"; 13360 offbits = (mips_opts.micromips ? 12 : 16); 13361 off = 7; 13362 goto uld_st; 13363 case M_USH_AB: 13364 s = "sb"; 13365 s2 = "sb"; 13366 off = 1; 13367 ust = 1; 13368 goto uld_st; 13369 case M_USW_AB: 13370 s = "swl"; 13371 s2 = "swr"; 13372 offbits = (mips_opts.micromips ? 12 : 16); 13373 off = 3; 13374 ust = 1; 13375 goto uld_st; 13376 case M_USD_AB: 13377 s = "sdl"; 13378 s2 = "sdr"; 13379 offbits = (mips_opts.micromips ? 12 : 16); 13380 off = 7; 13381 ust = 1; 13382 13383 uld_st: 13384 breg = op[2]; 13385 large_offset = !small_offset_p (off, align, offbits); 13386 ep = &offset_expr; 13387 expr1.X_add_number = 0; 13388 if (large_offset) 13389 { 13390 used_at = 1; 13391 tempreg = AT; 13392 if (small_offset_p (0, align, 16)) 13393 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, -1, 13394 offset_reloc[0], offset_reloc[1], offset_reloc[2]); 13395 else 13396 { 13397 load_address (tempreg, ep, &used_at); 13398 if (breg != 0) 13399 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 13400 tempreg, tempreg, breg); 13401 } 13402 offset_reloc[0] = BFD_RELOC_LO16; 13403 offset_reloc[1] = BFD_RELOC_UNUSED; 13404 offset_reloc[2] = BFD_RELOC_UNUSED; 13405 breg = tempreg; 13406 tempreg = op[0]; 13407 ep = &expr1; 13408 } 13409 else if (!ust && op[0] == breg) 13410 { 13411 used_at = 1; 13412 tempreg = AT; 13413 } 13414 else 13415 tempreg = op[0]; 13416 13417 if (off == 1) 13418 goto ulh_sh; 13419 13420 if (!target_big_endian) 13421 ep->X_add_number += off; 13422 if (offbits == 12) 13423 macro_build (NULL, s, "t,~(b)", tempreg, (int) ep->X_add_number, breg); 13424 else 13425 macro_build (ep, s, "t,o(b)", tempreg, -1, 13426 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); 13427 13428 if (!target_big_endian) 13429 ep->X_add_number -= off; 13430 else 13431 ep->X_add_number += off; 13432 if (offbits == 12) 13433 macro_build (NULL, s2, "t,~(b)", 13434 tempreg, (int) ep->X_add_number, breg); 13435 else 13436 macro_build (ep, s2, "t,o(b)", tempreg, -1, 13437 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); 13438 13439 /* If necessary, move the result in tempreg to the final destination. */ 13440 if (!ust && op[0] != tempreg) 13441 { 13442 /* Protect second load's delay slot. */ 13443 load_delay_nop (); 13444 move_register (op[0], tempreg); 13445 } 13446 break; 13447 13448 ulh_sh: 13449 used_at = 1; 13450 if (target_big_endian == ust) 13451 ep->X_add_number += off; 13452 tempreg = ust || large_offset ? op[0] : AT; 13453 macro_build (ep, s, "t,o(b)", tempreg, -1, 13454 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); 13455 13456 /* For halfword transfers we need a temporary register to shuffle 13457 bytes. Unfortunately for M_USH_A we have none available before 13458 the next store as AT holds the base address. We deal with this 13459 case by clobbering TREG and then restoring it as with ULH. */ 13460 tempreg = ust == large_offset ? op[0] : AT; 13461 if (ust) 13462 macro_build (NULL, "srl", SHFT_FMT, tempreg, op[0], 8); 13463 13464 if (target_big_endian == ust) 13465 ep->X_add_number -= off; 13466 else 13467 ep->X_add_number += off; 13468 macro_build (ep, s2, "t,o(b)", tempreg, -1, 13469 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); 13470 13471 /* For M_USH_A re-retrieve the LSB. */ 13472 if (ust && large_offset) 13473 { 13474 if (target_big_endian) 13475 ep->X_add_number += off; 13476 else 13477 ep->X_add_number -= off; 13478 macro_build (&expr1, "lbu", "t,o(b)", AT, -1, 13479 offset_reloc[0], offset_reloc[1], offset_reloc[2], AT); 13480 } 13481 /* For ULH and M_USH_A OR the LSB in. */ 13482 if (!ust || large_offset) 13483 { 13484 tempreg = !large_offset ? AT : op[0]; 13485 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8); 13486 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); 13487 } 13488 break; 13489 13490 default: 13491 /* FIXME: Check if this is one of the itbl macros, since they 13492 are added dynamically. */ 13493 as_bad (_("macro %s not implemented yet"), ip->insn_mo->name); 13494 break; 13495 } 13496 if (!mips_opts.at && used_at) 13497 as_bad (_("macro used $at after \".set noat\"")); 13498} 13499 13500/* Implement macros in mips16 mode. */ 13501 13502static void 13503mips16_macro (struct mips_cl_insn *ip) 13504{ 13505 const struct mips_operand_array *operands; 13506 int mask; 13507 int tmp; 13508 expressionS expr1; 13509 int dbl; 13510 const char *s, *s2, *s3; 13511 unsigned int op[MAX_OPERANDS]; 13512 unsigned int i; 13513 13514 mask = ip->insn_mo->mask; 13515 13516 operands = insn_operands (ip); 13517 for (i = 0; i < MAX_OPERANDS; i++) 13518 if (operands->operand[i]) 13519 op[i] = insn_extract_operand (ip, operands->operand[i]); 13520 else 13521 op[i] = -1; 13522 13523 expr1.X_op = O_constant; 13524 expr1.X_op_symbol = NULL; 13525 expr1.X_add_symbol = NULL; 13526 expr1.X_add_number = 1; 13527 13528 dbl = 0; 13529 13530 switch (mask) 13531 { 13532 default: 13533 abort (); 13534 13535 case M_DDIV_3: 13536 dbl = 1; 13537 /* Fall through. */ 13538 case M_DIV_3: 13539 s = "mflo"; 13540 goto do_div3; 13541 case M_DREM_3: 13542 dbl = 1; 13543 /* Fall through. */ 13544 case M_REM_3: 13545 s = "mfhi"; 13546 do_div3: 13547 start_noreorder (); 13548 macro_build (NULL, dbl ? "ddiv" : "div", ".,x,y", op[1], op[2]); 13549 expr1.X_add_number = 2; 13550 macro_build (&expr1, "bnez", "x,p", op[2]); 13551 macro_build (NULL, "break", "6", 7); 13552 13553 /* FIXME: The normal code checks for of -1 / -0x80000000 here, 13554 since that causes an overflow. We should do that as well, 13555 but I don't see how to do the comparisons without a temporary 13556 register. */ 13557 end_noreorder (); 13558 macro_build (NULL, s, "x", op[0]); 13559 break; 13560 13561 case M_DIVU_3: 13562 s = "divu"; 13563 s2 = "mflo"; 13564 goto do_divu3; 13565 case M_REMU_3: 13566 s = "divu"; 13567 s2 = "mfhi"; 13568 goto do_divu3; 13569 case M_DDIVU_3: 13570 s = "ddivu"; 13571 s2 = "mflo"; 13572 goto do_divu3; 13573 case M_DREMU_3: 13574 s = "ddivu"; 13575 s2 = "mfhi"; 13576 do_divu3: 13577 start_noreorder (); 13578 macro_build (NULL, s, ".,x,y", op[1], op[2]); 13579 expr1.X_add_number = 2; 13580 macro_build (&expr1, "bnez", "x,p", op[2]); 13581 macro_build (NULL, "break", "6", 7); 13582 end_noreorder (); 13583 macro_build (NULL, s2, "x", op[0]); 13584 break; 13585 13586 case M_DMUL: 13587 dbl = 1; 13588 /* Fall through. */ 13589 case M_MUL: 13590 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", op[1], op[2]); 13591 macro_build (NULL, "mflo", "x", op[0]); 13592 break; 13593 13594 case M_DSUBU_I: 13595 dbl = 1; 13596 goto do_subu; 13597 case M_SUBU_I: 13598 do_subu: 13599 imm_expr.X_add_number = -imm_expr.X_add_number; 13600 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,F", op[0], op[1]); 13601 break; 13602 13603 case M_SUBU_I_2: 13604 imm_expr.X_add_number = -imm_expr.X_add_number; 13605 macro_build (&imm_expr, "addiu", "x,k", op[0]); 13606 break; 13607 13608 case M_DSUBU_I_2: 13609 imm_expr.X_add_number = -imm_expr.X_add_number; 13610 macro_build (&imm_expr, "daddiu", "y,j", op[0]); 13611 break; 13612 13613 case M_BEQ: 13614 s = "cmp"; 13615 s2 = "bteqz"; 13616 goto do_branch; 13617 case M_BNE: 13618 s = "cmp"; 13619 s2 = "btnez"; 13620 goto do_branch; 13621 case M_BLT: 13622 s = "slt"; 13623 s2 = "btnez"; 13624 goto do_branch; 13625 case M_BLTU: 13626 s = "sltu"; 13627 s2 = "btnez"; 13628 goto do_branch; 13629 case M_BLE: 13630 s = "slt"; 13631 s2 = "bteqz"; 13632 goto do_reverse_branch; 13633 case M_BLEU: 13634 s = "sltu"; 13635 s2 = "bteqz"; 13636 goto do_reverse_branch; 13637 case M_BGE: 13638 s = "slt"; 13639 s2 = "bteqz"; 13640 goto do_branch; 13641 case M_BGEU: 13642 s = "sltu"; 13643 s2 = "bteqz"; 13644 goto do_branch; 13645 case M_BGT: 13646 s = "slt"; 13647 s2 = "btnez"; 13648 goto do_reverse_branch; 13649 case M_BGTU: 13650 s = "sltu"; 13651 s2 = "btnez"; 13652 13653 do_reverse_branch: 13654 tmp = op[1]; 13655 op[1] = op[0]; 13656 op[0] = tmp; 13657 13658 do_branch: 13659 macro_build (NULL, s, "x,y", op[0], op[1]); 13660 macro_build (&offset_expr, s2, "p"); 13661 break; 13662 13663 case M_BEQ_I: 13664 s = "cmpi"; 13665 s2 = "bteqz"; 13666 s3 = "x,U"; 13667 goto do_branch_i; 13668 case M_BNE_I: 13669 s = "cmpi"; 13670 s2 = "btnez"; 13671 s3 = "x,U"; 13672 goto do_branch_i; 13673 case M_BLT_I: 13674 s = "slti"; 13675 s2 = "btnez"; 13676 s3 = "x,8"; 13677 goto do_branch_i; 13678 case M_BLTU_I: 13679 s = "sltiu"; 13680 s2 = "btnez"; 13681 s3 = "x,8"; 13682 goto do_branch_i; 13683 case M_BLE_I: 13684 s = "slti"; 13685 s2 = "btnez"; 13686 s3 = "x,8"; 13687 goto do_addone_branch_i; 13688 case M_BLEU_I: 13689 s = "sltiu"; 13690 s2 = "btnez"; 13691 s3 = "x,8"; 13692 goto do_addone_branch_i; 13693 case M_BGE_I: 13694 s = "slti"; 13695 s2 = "bteqz"; 13696 s3 = "x,8"; 13697 goto do_branch_i; 13698 case M_BGEU_I: 13699 s = "sltiu"; 13700 s2 = "bteqz"; 13701 s3 = "x,8"; 13702 goto do_branch_i; 13703 case M_BGT_I: 13704 s = "slti"; 13705 s2 = "bteqz"; 13706 s3 = "x,8"; 13707 goto do_addone_branch_i; 13708 case M_BGTU_I: 13709 s = "sltiu"; 13710 s2 = "bteqz"; 13711 s3 = "x,8"; 13712 13713 do_addone_branch_i: 13714 ++imm_expr.X_add_number; 13715 13716 do_branch_i: 13717 macro_build (&imm_expr, s, s3, op[0]); 13718 macro_build (&offset_expr, s2, "p"); 13719 break; 13720 13721 case M_ABS: 13722 expr1.X_add_number = 0; 13723 macro_build (&expr1, "slti", "x,8", op[1]); 13724 if (op[0] != op[1]) 13725 macro_build (NULL, "move", "y,X", op[0], mips16_to_32_reg_map[op[1]]); 13726 expr1.X_add_number = 2; 13727 macro_build (&expr1, "bteqz", "p"); 13728 macro_build (NULL, "neg", "x,w", op[0], op[0]); 13729 break; 13730 } 13731} 13732 13733/* Look up instruction [START, START + LENGTH) in HASH. Record any extra 13734 opcode bits in *OPCODE_EXTRA. */ 13735 13736static struct mips_opcode * 13737mips_lookup_insn (struct hash_control *hash, const char *start, 13738 ssize_t length, unsigned int *opcode_extra) 13739{ 13740 char *name, *dot, *p; 13741 unsigned int mask, suffix; 13742 ssize_t opend; 13743 struct mips_opcode *insn; 13744 13745 /* Make a copy of the instruction so that we can fiddle with it. */ 13746 name = xstrndup (start, length); 13747 13748 /* Look up the instruction as-is. */ 13749 insn = (struct mips_opcode *) hash_find (hash, name); 13750 if (insn) 13751 goto end; 13752 13753 dot = strchr (name, '.'); 13754 if (dot && dot[1]) 13755 { 13756 /* Try to interpret the text after the dot as a VU0 channel suffix. */ 13757 p = mips_parse_vu0_channels (dot + 1, &mask); 13758 if (*p == 0 && mask != 0) 13759 { 13760 *dot = 0; 13761 insn = (struct mips_opcode *) hash_find (hash, name); 13762 *dot = '.'; 13763 if (insn && (insn->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0) 13764 { 13765 *opcode_extra |= mask << mips_vu0_channel_mask.lsb; 13766 goto end; 13767 } 13768 } 13769 } 13770 13771 if (mips_opts.micromips) 13772 { 13773 /* See if there's an instruction size override suffix, 13774 either `16' or `32', at the end of the mnemonic proper, 13775 that defines the operation, i.e. before the first `.' 13776 character if any. Strip it and retry. */ 13777 opend = dot != NULL ? dot - name : length; 13778 if (opend >= 3 && name[opend - 2] == '1' && name[opend - 1] == '6') 13779 suffix = 2; 13780 else if (name[opend - 2] == '3' && name[opend - 1] == '2') 13781 suffix = 4; 13782 else 13783 suffix = 0; 13784 if (suffix) 13785 { 13786 memcpy (name + opend - 2, name + opend, length - opend + 1); 13787 insn = (struct mips_opcode *) hash_find (hash, name); 13788 if (insn) 13789 { 13790 forced_insn_length = suffix; 13791 goto end; 13792 } 13793 } 13794 } 13795 13796 insn = NULL; 13797 end: 13798 free (name); 13799 return insn; 13800} 13801 13802/* Assemble an instruction into its binary format. If the instruction 13803 is a macro, set imm_expr and offset_expr to the values associated 13804 with "I" and "A" operands respectively. Otherwise store the value 13805 of the relocatable field (if any) in offset_expr. In both cases 13806 set offset_reloc to the relocation operators applied to offset_expr. */ 13807 13808static void 13809mips_ip (char *str, struct mips_cl_insn *insn) 13810{ 13811 const struct mips_opcode *first, *past; 13812 struct hash_control *hash; 13813 char format; 13814 size_t end; 13815 struct mips_operand_token *tokens; 13816 unsigned int opcode_extra; 13817 13818 if (mips_opts.micromips) 13819 { 13820 hash = micromips_op_hash; 13821 past = µmips_opcodes[bfd_micromips_num_opcodes]; 13822 } 13823 else 13824 { 13825 hash = op_hash; 13826 past = &mips_opcodes[NUMOPCODES]; 13827 } 13828 forced_insn_length = 0; 13829 opcode_extra = 0; 13830 13831 /* We first try to match an instruction up to a space or to the end. */ 13832 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++) 13833 continue; 13834 13835 first = mips_lookup_insn (hash, str, end, &opcode_extra); 13836 if (first == NULL) 13837 { 13838 set_insn_error (0, _("unrecognized opcode")); 13839 return; 13840 } 13841 13842 if (strcmp (first->name, "li.s") == 0) 13843 format = 'f'; 13844 else if (strcmp (first->name, "li.d") == 0) 13845 format = 'd'; 13846 else 13847 format = 0; 13848 tokens = mips_parse_arguments (str + end, format); 13849 if (!tokens) 13850 return; 13851 13852 if (!match_insns (insn, first, past, tokens, opcode_extra, FALSE) 13853 && !match_insns (insn, first, past, tokens, opcode_extra, TRUE)) 13854 set_insn_error (0, _("invalid operands")); 13855 13856 obstack_free (&mips_operand_tokens, tokens); 13857} 13858 13859/* As for mips_ip, but used when assembling MIPS16 code. 13860 Also set forced_insn_length to the resulting instruction size in 13861 bytes if the user explicitly requested a small or extended instruction. */ 13862 13863static void 13864mips16_ip (char *str, struct mips_cl_insn *insn) 13865{ 13866 char *end, *s, c; 13867 struct mips_opcode *first; 13868 struct mips_operand_token *tokens; 13869 unsigned int l; 13870 13871 for (s = str; ISLOWER (*s); ++s) 13872 ; 13873 end = s; 13874 c = *end; 13875 13876 l = 0; 13877 switch (c) 13878 { 13879 case '\0': 13880 break; 13881 13882 case ' ': 13883 s++; 13884 break; 13885 13886 case '.': 13887 s++; 13888 if (*s == 't') 13889 { 13890 l = 2; 13891 s++; 13892 } 13893 else if (*s == 'e') 13894 { 13895 l = 4; 13896 s++; 13897 } 13898 if (*s == '\0') 13899 break; 13900 else if (*s++ == ' ') 13901 break; 13902 /* Fall through. */ 13903 default: 13904 set_insn_error (0, _("unrecognized opcode")); 13905 return; 13906 } 13907 forced_insn_length = l; 13908 13909 *end = 0; 13910 first = (struct mips_opcode *) hash_find (mips16_op_hash, str); 13911 *end = c; 13912 13913 if (!first) 13914 { 13915 set_insn_error (0, _("unrecognized opcode")); 13916 return; 13917 } 13918 13919 tokens = mips_parse_arguments (s, 0); 13920 if (!tokens) 13921 return; 13922 13923 if (!match_mips16_insns (insn, first, tokens)) 13924 set_insn_error (0, _("invalid operands")); 13925 13926 obstack_free (&mips_operand_tokens, tokens); 13927} 13928 13929/* Marshal immediate value VAL for an extended MIPS16 instruction. 13930 NBITS is the number of significant bits in VAL. */ 13931 13932static unsigned long 13933mips16_immed_extend (offsetT val, unsigned int nbits) 13934{ 13935 int extval; 13936 if (nbits == 16) 13937 { 13938 extval = ((val >> 11) & 0x1f) | (val & 0x7e0); 13939 val &= 0x1f; 13940 } 13941 else if (nbits == 15) 13942 { 13943 extval = ((val >> 11) & 0xf) | (val & 0x7f0); 13944 val &= 0xf; 13945 } 13946 else 13947 { 13948 extval = ((val & 0x1f) << 6) | (val & 0x20); 13949 val = 0; 13950 } 13951 return (extval << 16) | val; 13952} 13953 13954/* Like decode_mips16_operand, but require the operand to be defined and 13955 require it to be an integer. */ 13956 13957static const struct mips_int_operand * 13958mips16_immed_operand (int type, bfd_boolean extended_p) 13959{ 13960 const struct mips_operand *operand; 13961 13962 operand = decode_mips16_operand (type, extended_p); 13963 if (!operand || (operand->type != OP_INT && operand->type != OP_PCREL)) 13964 abort (); 13965 return (const struct mips_int_operand *) operand; 13966} 13967 13968/* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */ 13969 13970static bfd_boolean 13971mips16_immed_in_range_p (const struct mips_int_operand *operand, 13972 bfd_reloc_code_real_type reloc, offsetT sval) 13973{ 13974 int min_val, max_val; 13975 13976 min_val = mips_int_operand_min (operand); 13977 max_val = mips_int_operand_max (operand); 13978 if (reloc != BFD_RELOC_UNUSED) 13979 { 13980 if (min_val < 0) 13981 sval = SEXT_16BIT (sval); 13982 else 13983 sval &= 0xffff; 13984 } 13985 13986 return (sval >= min_val 13987 && sval <= max_val 13988 && (sval & ((1 << operand->shift) - 1)) == 0); 13989} 13990 13991/* Install immediate value VAL into MIPS16 instruction *INSN, 13992 extending it if necessary. The instruction in *INSN may 13993 already be extended. 13994 13995 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED 13996 if none. In the former case, VAL is a 16-bit number with no 13997 defined signedness. 13998 13999 TYPE is the type of the immediate field. USER_INSN_LENGTH 14000 is the length that the user requested, or 0 if none. */ 14001 14002static void 14003mips16_immed (const char *file, unsigned int line, int type, 14004 bfd_reloc_code_real_type reloc, offsetT val, 14005 unsigned int user_insn_length, unsigned long *insn) 14006{ 14007 const struct mips_int_operand *operand; 14008 unsigned int uval, length; 14009 14010 operand = mips16_immed_operand (type, FALSE); 14011 if (!mips16_immed_in_range_p (operand, reloc, val)) 14012 { 14013 /* We need an extended instruction. */ 14014 if (user_insn_length == 2) 14015 as_bad_where (file, line, _("invalid unextended operand value")); 14016 else 14017 *insn |= MIPS16_EXTEND; 14018 } 14019 else if (user_insn_length == 4) 14020 { 14021 /* The operand doesn't force an unextended instruction to be extended. 14022 Warn if the user wanted an extended instruction anyway. */ 14023 *insn |= MIPS16_EXTEND; 14024 as_warn_where (file, line, 14025 _("extended operand requested but not required")); 14026 } 14027 14028 length = mips16_opcode_length (*insn); 14029 if (length == 4) 14030 { 14031 operand = mips16_immed_operand (type, TRUE); 14032 if (!mips16_immed_in_range_p (operand, reloc, val)) 14033 as_bad_where (file, line, 14034 _("operand value out of range for instruction")); 14035 } 14036 uval = ((unsigned int) val >> operand->shift) - operand->bias; 14037 if (length == 2 || operand->root.lsb != 0) 14038 *insn = mips_insert_operand (&operand->root, *insn, uval); 14039 else 14040 *insn |= mips16_immed_extend (uval, operand->root.size); 14041} 14042 14043struct percent_op_match 14044{ 14045 const char *str; 14046 bfd_reloc_code_real_type reloc; 14047}; 14048 14049static const struct percent_op_match mips_percent_op[] = 14050{ 14051 {"%lo", BFD_RELOC_LO16}, 14052 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, 14053 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, 14054 {"%call16", BFD_RELOC_MIPS_CALL16}, 14055 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, 14056 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, 14057 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, 14058 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, 14059 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, 14060 {"%got", BFD_RELOC_MIPS_GOT16}, 14061 {"%gp_rel", BFD_RELOC_GPREL16}, 14062 {"%half", BFD_RELOC_16}, 14063 {"%highest", BFD_RELOC_MIPS_HIGHEST}, 14064 {"%higher", BFD_RELOC_MIPS_HIGHER}, 14065 {"%neg", BFD_RELOC_MIPS_SUB}, 14066 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, 14067 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, 14068 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, 14069 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, 14070 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, 14071 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, 14072 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, 14073 {"%hi", BFD_RELOC_HI16_S}, 14074 {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL}, 14075 {"%pcrel_lo", BFD_RELOC_LO16_PCREL} 14076}; 14077 14078static const struct percent_op_match mips16_percent_op[] = 14079{ 14080 {"%lo", BFD_RELOC_MIPS16_LO16}, 14081 {"%gprel", BFD_RELOC_MIPS16_GPREL}, 14082 {"%got", BFD_RELOC_MIPS16_GOT16}, 14083 {"%call16", BFD_RELOC_MIPS16_CALL16}, 14084 {"%hi", BFD_RELOC_MIPS16_HI16_S}, 14085 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD}, 14086 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM}, 14087 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16}, 14088 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16}, 14089 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16}, 14090 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16}, 14091 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL} 14092}; 14093 14094 14095/* Return true if *STR points to a relocation operator. When returning true, 14096 move *STR over the operator and store its relocation code in *RELOC. 14097 Leave both *STR and *RELOC alone when returning false. */ 14098 14099static bfd_boolean 14100parse_relocation (char **str, bfd_reloc_code_real_type *reloc) 14101{ 14102 const struct percent_op_match *percent_op; 14103 size_t limit, i; 14104 14105 if (mips_opts.mips16) 14106 { 14107 percent_op = mips16_percent_op; 14108 limit = ARRAY_SIZE (mips16_percent_op); 14109 } 14110 else 14111 { 14112 percent_op = mips_percent_op; 14113 limit = ARRAY_SIZE (mips_percent_op); 14114 } 14115 14116 for (i = 0; i < limit; i++) 14117 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) 14118 { 14119 int len = strlen (percent_op[i].str); 14120 14121 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') 14122 continue; 14123 14124 *str += strlen (percent_op[i].str); 14125 *reloc = percent_op[i].reloc; 14126 14127 /* Check whether the output BFD supports this relocation. 14128 If not, issue an error and fall back on something safe. */ 14129 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) 14130 { 14131 as_bad (_("relocation %s isn't supported by the current ABI"), 14132 percent_op[i].str); 14133 *reloc = BFD_RELOC_UNUSED; 14134 } 14135 return TRUE; 14136 } 14137 return FALSE; 14138} 14139 14140 14141/* Parse string STR as a 16-bit relocatable operand. Store the 14142 expression in *EP and the relocations in the array starting 14143 at RELOC. Return the number of relocation operators used. 14144 14145 On exit, EXPR_END points to the first character after the expression. */ 14146 14147static size_t 14148my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, 14149 char *str) 14150{ 14151 bfd_reloc_code_real_type reversed_reloc[3]; 14152 size_t reloc_index, i; 14153 int crux_depth, str_depth; 14154 char *crux; 14155 14156 /* Search for the start of the main expression, recoding relocations 14157 in REVERSED_RELOC. End the loop with CRUX pointing to the start 14158 of the main expression and with CRUX_DEPTH containing the number 14159 of open brackets at that point. */ 14160 reloc_index = -1; 14161 str_depth = 0; 14162 do 14163 { 14164 reloc_index++; 14165 crux = str; 14166 crux_depth = str_depth; 14167 14168 /* Skip over whitespace and brackets, keeping count of the number 14169 of brackets. */ 14170 while (*str == ' ' || *str == '\t' || *str == '(') 14171 if (*str++ == '(') 14172 str_depth++; 14173 } 14174 while (*str == '%' 14175 && reloc_index < (HAVE_NEWABI ? 3 : 1) 14176 && parse_relocation (&str, &reversed_reloc[reloc_index])); 14177 14178 my_getExpression (ep, crux); 14179 str = expr_end; 14180 14181 /* Match every open bracket. */ 14182 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) 14183 if (*str++ == ')') 14184 crux_depth--; 14185 14186 if (crux_depth > 0) 14187 as_bad (_("unclosed '('")); 14188 14189 expr_end = str; 14190 14191 if (reloc_index != 0) 14192 { 14193 prev_reloc_op_frag = frag_now; 14194 for (i = 0; i < reloc_index; i++) 14195 reloc[i] = reversed_reloc[reloc_index - 1 - i]; 14196 } 14197 14198 return reloc_index; 14199} 14200 14201static void 14202my_getExpression (expressionS *ep, char *str) 14203{ 14204 char *save_in; 14205 14206 save_in = input_line_pointer; 14207 input_line_pointer = str; 14208 expression (ep); 14209 expr_end = input_line_pointer; 14210 input_line_pointer = save_in; 14211} 14212 14213const char * 14214md_atof (int type, char *litP, int *sizeP) 14215{ 14216 return ieee_md_atof (type, litP, sizeP, target_big_endian); 14217} 14218 14219void 14220md_number_to_chars (char *buf, valueT val, int n) 14221{ 14222 if (target_big_endian) 14223 number_to_chars_bigendian (buf, val, n); 14224 else 14225 number_to_chars_littleendian (buf, val, n); 14226} 14227 14228static int support_64bit_objects(void) 14229{ 14230 const char **list, **l; 14231 int yes; 14232 14233 list = bfd_target_list (); 14234 for (l = list; *l != NULL; l++) 14235 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0 14236 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0) 14237 break; 14238 yes = (*l != NULL); 14239 free (list); 14240 return yes; 14241} 14242 14243/* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to 14244 NEW_VALUE. Warn if another value was already specified. Note: 14245 we have to defer parsing the -march and -mtune arguments in order 14246 to handle 'from-abi' correctly, since the ABI might be specified 14247 in a later argument. */ 14248 14249static void 14250mips_set_option_string (const char **string_ptr, const char *new_value) 14251{ 14252 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) 14253 as_warn (_("a different %s was already specified, is now %s"), 14254 string_ptr == &mips_arch_string ? "-march" : "-mtune", 14255 new_value); 14256 14257 *string_ptr = new_value; 14258} 14259 14260int 14261md_parse_option (int c, const char *arg) 14262{ 14263 unsigned int i; 14264 14265 for (i = 0; i < ARRAY_SIZE (mips_ases); i++) 14266 if (c == mips_ases[i].option_on || c == mips_ases[i].option_off) 14267 { 14268 file_ase_explicit |= mips_set_ase (&mips_ases[i], &file_mips_opts, 14269 c == mips_ases[i].option_on); 14270 return 1; 14271 } 14272 14273 switch (c) 14274 { 14275 case OPTION_CONSTRUCT_FLOATS: 14276 mips_disable_float_construction = 0; 14277 break; 14278 14279 case OPTION_NO_CONSTRUCT_FLOATS: 14280 mips_disable_float_construction = 1; 14281 break; 14282 14283 case OPTION_TRAP: 14284 mips_trap = 1; 14285 break; 14286 14287 case OPTION_BREAK: 14288 mips_trap = 0; 14289 break; 14290 14291 case OPTION_EB: 14292 target_big_endian = 1; 14293 break; 14294 14295 case OPTION_EL: 14296 target_big_endian = 0; 14297 break; 14298 14299 case 'O': 14300 if (arg == NULL) 14301 mips_optimize = 1; 14302 else if (arg[0] == '0') 14303 mips_optimize = 0; 14304 else if (arg[0] == '1') 14305 mips_optimize = 1; 14306 else 14307 mips_optimize = 2; 14308 break; 14309 14310 case 'g': 14311 if (arg == NULL) 14312 mips_debug = 2; 14313 else 14314 mips_debug = atoi (arg); 14315 break; 14316 14317 case OPTION_MIPS1: 14318 file_mips_opts.isa = ISA_MIPS1; 14319 break; 14320 14321 case OPTION_MIPS2: 14322 file_mips_opts.isa = ISA_MIPS2; 14323 break; 14324 14325 case OPTION_MIPS3: 14326 file_mips_opts.isa = ISA_MIPS3; 14327 break; 14328 14329 case OPTION_MIPS4: 14330 file_mips_opts.isa = ISA_MIPS4; 14331 break; 14332 14333 case OPTION_MIPS5: 14334 file_mips_opts.isa = ISA_MIPS5; 14335 break; 14336 14337 case OPTION_MIPS32: 14338 file_mips_opts.isa = ISA_MIPS32; 14339 break; 14340 14341 case OPTION_MIPS32R2: 14342 file_mips_opts.isa = ISA_MIPS32R2; 14343 break; 14344 14345 case OPTION_MIPS32R3: 14346 file_mips_opts.isa = ISA_MIPS32R3; 14347 break; 14348 14349 case OPTION_MIPS32R5: 14350 file_mips_opts.isa = ISA_MIPS32R5; 14351 break; 14352 14353 case OPTION_MIPS32R6: 14354 file_mips_opts.isa = ISA_MIPS32R6; 14355 break; 14356 14357 case OPTION_MIPS64R2: 14358 file_mips_opts.isa = ISA_MIPS64R2; 14359 break; 14360 14361 case OPTION_MIPS64R3: 14362 file_mips_opts.isa = ISA_MIPS64R3; 14363 break; 14364 14365 case OPTION_MIPS64R5: 14366 file_mips_opts.isa = ISA_MIPS64R5; 14367 break; 14368 14369 case OPTION_MIPS64R6: 14370 file_mips_opts.isa = ISA_MIPS64R6; 14371 break; 14372 14373 case OPTION_MIPS64: 14374 file_mips_opts.isa = ISA_MIPS64; 14375 break; 14376 14377 case OPTION_MTUNE: 14378 mips_set_option_string (&mips_tune_string, arg); 14379 break; 14380 14381 case OPTION_MARCH: 14382 mips_set_option_string (&mips_arch_string, arg); 14383 break; 14384 14385 case OPTION_M4650: 14386 mips_set_option_string (&mips_arch_string, "4650"); 14387 mips_set_option_string (&mips_tune_string, "4650"); 14388 break; 14389 14390 case OPTION_NO_M4650: 14391 break; 14392 14393 case OPTION_M4010: 14394 mips_set_option_string (&mips_arch_string, "4010"); 14395 mips_set_option_string (&mips_tune_string, "4010"); 14396 break; 14397 14398 case OPTION_NO_M4010: 14399 break; 14400 14401 case OPTION_M4100: 14402 mips_set_option_string (&mips_arch_string, "4100"); 14403 mips_set_option_string (&mips_tune_string, "4100"); 14404 break; 14405 14406 case OPTION_NO_M4100: 14407 break; 14408 14409 case OPTION_M3900: 14410 mips_set_option_string (&mips_arch_string, "3900"); 14411 mips_set_option_string (&mips_tune_string, "3900"); 14412 break; 14413 14414 case OPTION_NO_M3900: 14415 break; 14416 14417 case OPTION_MICROMIPS: 14418 if (file_mips_opts.mips16 == 1) 14419 { 14420 as_bad (_("-mmicromips cannot be used with -mips16")); 14421 return 0; 14422 } 14423 file_mips_opts.micromips = 1; 14424 mips_no_prev_insn (); 14425 break; 14426 14427 case OPTION_NO_MICROMIPS: 14428 file_mips_opts.micromips = 0; 14429 mips_no_prev_insn (); 14430 break; 14431 14432 case OPTION_MIPS16: 14433 if (file_mips_opts.micromips == 1) 14434 { 14435 as_bad (_("-mips16 cannot be used with -micromips")); 14436 return 0; 14437 } 14438 file_mips_opts.mips16 = 1; 14439 mips_no_prev_insn (); 14440 break; 14441 14442 case OPTION_NO_MIPS16: 14443 file_mips_opts.mips16 = 0; 14444 mips_no_prev_insn (); 14445 break; 14446 14447 case OPTION_FIX_24K: 14448 mips_fix_24k = 1; 14449 break; 14450 14451 case OPTION_NO_FIX_24K: 14452 mips_fix_24k = 0; 14453 break; 14454 14455 case OPTION_FIX_RM7000: 14456 mips_fix_rm7000 = 1; 14457 break; 14458 14459 case OPTION_NO_FIX_RM7000: 14460 mips_fix_rm7000 = 0; 14461 break; 14462 14463 case OPTION_FIX_LOONGSON2F_JUMP: 14464 mips_fix_loongson2f_jump = TRUE; 14465 break; 14466 14467 case OPTION_NO_FIX_LOONGSON2F_JUMP: 14468 mips_fix_loongson2f_jump = FALSE; 14469 break; 14470 14471 case OPTION_FIX_LOONGSON2F_NOP: 14472 mips_fix_loongson2f_nop = TRUE; 14473 break; 14474 14475 case OPTION_NO_FIX_LOONGSON2F_NOP: 14476 mips_fix_loongson2f_nop = FALSE; 14477 break; 14478 14479 case OPTION_FIX_VR4120: 14480 mips_fix_vr4120 = 1; 14481 break; 14482 14483 case OPTION_NO_FIX_VR4120: 14484 mips_fix_vr4120 = 0; 14485 break; 14486 14487 case OPTION_FIX_VR4130: 14488 mips_fix_vr4130 = 1; 14489 break; 14490 14491 case OPTION_NO_FIX_VR4130: 14492 mips_fix_vr4130 = 0; 14493 break; 14494 14495 case OPTION_FIX_CN63XXP1: 14496 mips_fix_cn63xxp1 = TRUE; 14497 break; 14498 14499 case OPTION_NO_FIX_CN63XXP1: 14500 mips_fix_cn63xxp1 = FALSE; 14501 break; 14502 14503 case OPTION_RELAX_BRANCH: 14504 mips_relax_branch = 1; 14505 break; 14506 14507 case OPTION_NO_RELAX_BRANCH: 14508 mips_relax_branch = 0; 14509 break; 14510 14511 case OPTION_IGNORE_BRANCH_ISA: 14512 mips_ignore_branch_isa = TRUE; 14513 break; 14514 14515 case OPTION_NO_IGNORE_BRANCH_ISA: 14516 mips_ignore_branch_isa = FALSE; 14517 break; 14518 14519 case OPTION_INSN32: 14520 file_mips_opts.insn32 = TRUE; 14521 break; 14522 14523 case OPTION_NO_INSN32: 14524 file_mips_opts.insn32 = FALSE; 14525 break; 14526 14527 case OPTION_MSHARED: 14528 mips_in_shared = TRUE; 14529 break; 14530 14531 case OPTION_MNO_SHARED: 14532 mips_in_shared = FALSE; 14533 break; 14534 14535 case OPTION_MSYM32: 14536 file_mips_opts.sym32 = TRUE; 14537 break; 14538 14539 case OPTION_MNO_SYM32: 14540 file_mips_opts.sym32 = FALSE; 14541 break; 14542 14543 /* When generating ELF code, we permit -KPIC and -call_shared to 14544 select SVR4_PIC, and -non_shared to select no PIC. This is 14545 intended to be compatible with Irix 5. */ 14546 case OPTION_CALL_SHARED: 14547 mips_pic = SVR4_PIC; 14548 mips_abicalls = TRUE; 14549 break; 14550 14551 case OPTION_CALL_NONPIC: 14552 mips_pic = NO_PIC; 14553 mips_abicalls = TRUE; 14554 break; 14555 14556 case OPTION_NON_SHARED: 14557 mips_pic = NO_PIC; 14558 mips_abicalls = FALSE; 14559 break; 14560 14561 /* The -xgot option tells the assembler to use 32 bit offsets 14562 when accessing the got in SVR4_PIC mode. It is for Irix 14563 compatibility. */ 14564 case OPTION_XGOT: 14565 mips_big_got = 1; 14566 break; 14567 14568 case 'G': 14569 g_switch_value = atoi (arg); 14570 g_switch_seen = 1; 14571 break; 14572 14573 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 14574 and -mabi=64. */ 14575 case OPTION_32: 14576 mips_abi = O32_ABI; 14577 break; 14578 14579 case OPTION_N32: 14580 mips_abi = N32_ABI; 14581 break; 14582 14583 case OPTION_64: 14584 mips_abi = N64_ABI; 14585 if (!support_64bit_objects()) 14586 as_fatal (_("no compiled in support for 64 bit object file format")); 14587 break; 14588 14589 case OPTION_GP32: 14590 file_mips_opts.gp = 32; 14591 break; 14592 14593 case OPTION_GP64: 14594 file_mips_opts.gp = 64; 14595 break; 14596 14597 case OPTION_FP32: 14598 file_mips_opts.fp = 32; 14599 break; 14600 14601 case OPTION_FPXX: 14602 file_mips_opts.fp = 0; 14603 break; 14604 14605 case OPTION_FP64: 14606 file_mips_opts.fp = 64; 14607 break; 14608 14609 case OPTION_ODD_SPREG: 14610 file_mips_opts.oddspreg = 1; 14611 break; 14612 14613 case OPTION_NO_ODD_SPREG: 14614 file_mips_opts.oddspreg = 0; 14615 break; 14616 14617 case OPTION_SINGLE_FLOAT: 14618 file_mips_opts.single_float = 1; 14619 break; 14620 14621 case OPTION_DOUBLE_FLOAT: 14622 file_mips_opts.single_float = 0; 14623 break; 14624 14625 case OPTION_SOFT_FLOAT: 14626 file_mips_opts.soft_float = 1; 14627 break; 14628 14629 case OPTION_HARD_FLOAT: 14630 file_mips_opts.soft_float = 0; 14631 break; 14632 14633 case OPTION_MABI: 14634 if (strcmp (arg, "32") == 0) 14635 mips_abi = O32_ABI; 14636 else if (strcmp (arg, "o64") == 0) 14637 mips_abi = O64_ABI; 14638 else if (strcmp (arg, "n32") == 0) 14639 mips_abi = N32_ABI; 14640 else if (strcmp (arg, "64") == 0) 14641 { 14642 mips_abi = N64_ABI; 14643 if (! support_64bit_objects()) 14644 as_fatal (_("no compiled in support for 64 bit object file " 14645 "format")); 14646 } 14647 else if (strcmp (arg, "eabi") == 0) 14648 mips_abi = EABI_ABI; 14649 else 14650 { 14651 as_fatal (_("invalid abi -mabi=%s"), arg); 14652 return 0; 14653 } 14654 break; 14655 14656 case OPTION_M7000_HILO_FIX: 14657 mips_7000_hilo_fix = TRUE; 14658 break; 14659 14660 case OPTION_MNO_7000_HILO_FIX: 14661 mips_7000_hilo_fix = FALSE; 14662 break; 14663 14664 case OPTION_MDEBUG: 14665 mips_flag_mdebug = TRUE; 14666 break; 14667 14668 case OPTION_NO_MDEBUG: 14669 mips_flag_mdebug = FALSE; 14670 break; 14671 14672 case OPTION_PDR: 14673 mips_flag_pdr = TRUE; 14674 break; 14675 14676 case OPTION_NO_PDR: 14677 mips_flag_pdr = FALSE; 14678 break; 14679 14680 case OPTION_MVXWORKS_PIC: 14681 mips_pic = VXWORKS_PIC; 14682 break; 14683 14684 case OPTION_NAN: 14685 if (strcmp (arg, "2008") == 0) 14686 mips_nan2008 = 1; 14687 else if (strcmp (arg, "legacy") == 0) 14688 mips_nan2008 = 0; 14689 else 14690 { 14691 as_fatal (_("invalid NaN setting -mnan=%s"), arg); 14692 return 0; 14693 } 14694 break; 14695 14696 default: 14697 return 0; 14698 } 14699 14700 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump; 14701 14702 return 1; 14703} 14704 14705/* Set up globals to tune for the ISA or processor described by INFO. */ 14706 14707static void 14708mips_set_tune (const struct mips_cpu_info *info) 14709{ 14710 if (info != 0) 14711 mips_tune = info->cpu; 14712} 14713 14714 14715void 14716mips_after_parse_args (void) 14717{ 14718 const struct mips_cpu_info *arch_info = 0; 14719 const struct mips_cpu_info *tune_info = 0; 14720 14721 /* GP relative stuff not working for PE */ 14722 if (strncmp (TARGET_OS, "pe", 2) == 0) 14723 { 14724 if (g_switch_seen && g_switch_value != 0) 14725 as_bad (_("-G not supported in this configuration")); 14726 g_switch_value = 0; 14727 } 14728 14729 if (mips_abi == NO_ABI) 14730 mips_abi = MIPS_DEFAULT_ABI; 14731 14732 /* The following code determines the architecture. 14733 Similar code was added to GCC 3.3 (see override_options() in 14734 config/mips/mips.c). The GAS and GCC code should be kept in sync 14735 as much as possible. */ 14736 14737 if (mips_arch_string != 0) 14738 arch_info = mips_parse_cpu ("-march", mips_arch_string); 14739 14740 if (file_mips_opts.isa != ISA_UNKNOWN) 14741 { 14742 /* Handle -mipsN. At this point, file_mips_opts.isa contains the 14743 ISA level specified by -mipsN, while arch_info->isa contains 14744 the -march selection (if any). */ 14745 if (arch_info != 0) 14746 { 14747 /* -march takes precedence over -mipsN, since it is more descriptive. 14748 There's no harm in specifying both as long as the ISA levels 14749 are the same. */ 14750 if (file_mips_opts.isa != arch_info->isa) 14751 as_bad (_("-%s conflicts with the other architecture options," 14752 " which imply -%s"), 14753 mips_cpu_info_from_isa (file_mips_opts.isa)->name, 14754 mips_cpu_info_from_isa (arch_info->isa)->name); 14755 } 14756 else 14757 arch_info = mips_cpu_info_from_isa (file_mips_opts.isa); 14758 } 14759 14760 if (arch_info == 0) 14761 { 14762 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); 14763 gas_assert (arch_info); 14764 } 14765 14766 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) 14767 as_bad (_("-march=%s is not compatible with the selected ABI"), 14768 arch_info->name); 14769 14770 file_mips_opts.arch = arch_info->cpu; 14771 file_mips_opts.isa = arch_info->isa; 14772 14773 /* Set up initial mips_opts state. */ 14774 mips_opts = file_mips_opts; 14775 14776 /* The register size inference code is now placed in 14777 file_mips_check_options. */ 14778 14779 /* Optimize for file_mips_opts.arch, unless -mtune selects a different 14780 processor. */ 14781 if (mips_tune_string != 0) 14782 tune_info = mips_parse_cpu ("-mtune", mips_tune_string); 14783 14784 if (tune_info == 0) 14785 mips_set_tune (arch_info); 14786 else 14787 mips_set_tune (tune_info); 14788 14789 if (mips_flag_mdebug < 0) 14790 mips_flag_mdebug = 0; 14791} 14792 14793void 14794mips_init_after_args (void) 14795{ 14796 /* initialize opcodes */ 14797 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; 14798 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; 14799} 14800 14801long 14802md_pcrel_from (fixS *fixP) 14803{ 14804 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; 14805 switch (fixP->fx_r_type) 14806 { 14807 case BFD_RELOC_MICROMIPS_7_PCREL_S1: 14808 case BFD_RELOC_MICROMIPS_10_PCREL_S1: 14809 /* Return the address of the delay slot. */ 14810 return addr + 2; 14811 14812 case BFD_RELOC_MICROMIPS_16_PCREL_S1: 14813 case BFD_RELOC_MICROMIPS_JMP: 14814 case BFD_RELOC_MIPS16_16_PCREL_S1: 14815 case BFD_RELOC_16_PCREL_S2: 14816 case BFD_RELOC_MIPS_21_PCREL_S2: 14817 case BFD_RELOC_MIPS_26_PCREL_S2: 14818 case BFD_RELOC_MIPS_JMP: 14819 /* Return the address of the delay slot. */ 14820 return addr + 4; 14821 14822 case BFD_RELOC_MIPS_18_PCREL_S3: 14823 /* Return the aligned address of the doubleword containing 14824 the instruction. */ 14825 return addr & ~7; 14826 14827 default: 14828 return addr; 14829 } 14830} 14831 14832/* This is called before the symbol table is processed. In order to 14833 work with gcc when using mips-tfile, we must keep all local labels. 14834 However, in other cases, we want to discard them. If we were 14835 called with -g, but we didn't see any debugging information, it may 14836 mean that gcc is smuggling debugging information through to 14837 mips-tfile, in which case we must generate all local labels. */ 14838 14839void 14840mips_frob_file_before_adjust (void) 14841{ 14842#ifndef NO_ECOFF_DEBUGGING 14843 if (ECOFF_DEBUGGING 14844 && mips_debug != 0 14845 && ! ecoff_debugging_seen) 14846 flag_keep_locals = 1; 14847#endif 14848} 14849 14850/* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede 14851 the corresponding LO16 reloc. This is called before md_apply_fix and 14852 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit 14853 relocation operators. 14854 14855 For our purposes, a %lo() expression matches a %got() or %hi() 14856 expression if: 14857 14858 (a) it refers to the same symbol; and 14859 (b) the offset applied in the %lo() expression is no lower than 14860 the offset applied in the %got() or %hi(). 14861 14862 (b) allows us to cope with code like: 14863 14864 lui $4,%hi(foo) 14865 lh $4,%lo(foo+2)($4) 14866 14867 ...which is legal on RELA targets, and has a well-defined behaviour 14868 if the user knows that adding 2 to "foo" will not induce a carry to 14869 the high 16 bits. 14870 14871 When several %lo()s match a particular %got() or %hi(), we use the 14872 following rules to distinguish them: 14873 14874 (1) %lo()s with smaller offsets are a better match than %lo()s with 14875 higher offsets. 14876 14877 (2) %lo()s with no matching %got() or %hi() are better than those 14878 that already have a matching %got() or %hi(). 14879 14880 (3) later %lo()s are better than earlier %lo()s. 14881 14882 These rules are applied in order. 14883 14884 (1) means, among other things, that %lo()s with identical offsets are 14885 chosen if they exist. 14886 14887 (2) means that we won't associate several high-part relocations with 14888 the same low-part relocation unless there's no alternative. Having 14889 several high parts for the same low part is a GNU extension; this rule 14890 allows careful users to avoid it. 14891 14892 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, 14893 with the last high-part relocation being at the front of the list. 14894 It therefore makes sense to choose the last matching low-part 14895 relocation, all other things being equal. It's also easier 14896 to code that way. */ 14897 14898void 14899mips_frob_file (void) 14900{ 14901 struct mips_hi_fixup *l; 14902 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED; 14903 14904 for (l = mips_hi_fixup_list; l != NULL; l = l->next) 14905 { 14906 segment_info_type *seginfo; 14907 bfd_boolean matched_lo_p; 14908 fixS **hi_pos, **lo_pos, **pos; 14909 14910 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type)); 14911 14912 /* If a GOT16 relocation turns out to be against a global symbol, 14913 there isn't supposed to be a matching LO. Ignore %gots against 14914 constants; we'll report an error for those later. */ 14915 if (got16_reloc_p (l->fixp->fx_r_type) 14916 && !(l->fixp->fx_addsy 14917 && pic_need_relax (l->fixp->fx_addsy))) 14918 continue; 14919 14920 /* Check quickly whether the next fixup happens to be a matching %lo. */ 14921 if (fixup_has_matching_lo_p (l->fixp)) 14922 continue; 14923 14924 seginfo = seg_info (l->seg); 14925 14926 /* Set HI_POS to the position of this relocation in the chain. 14927 Set LO_POS to the position of the chosen low-part relocation. 14928 MATCHED_LO_P is true on entry to the loop if *POS is a low-part 14929 relocation that matches an immediately-preceding high-part 14930 relocation. */ 14931 hi_pos = NULL; 14932 lo_pos = NULL; 14933 matched_lo_p = FALSE; 14934 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type); 14935 14936 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) 14937 { 14938 if (*pos == l->fixp) 14939 hi_pos = pos; 14940 14941 if ((*pos)->fx_r_type == looking_for_rtype 14942 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy) 14943 && (*pos)->fx_offset >= l->fixp->fx_offset 14944 && (lo_pos == NULL 14945 || (*pos)->fx_offset < (*lo_pos)->fx_offset 14946 || (!matched_lo_p 14947 && (*pos)->fx_offset == (*lo_pos)->fx_offset))) 14948 lo_pos = pos; 14949 14950 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) 14951 && fixup_has_matching_lo_p (*pos)); 14952 } 14953 14954 /* If we found a match, remove the high-part relocation from its 14955 current position and insert it before the low-part relocation. 14956 Make the offsets match so that fixup_has_matching_lo_p() 14957 will return true. 14958 14959 We don't warn about unmatched high-part relocations since some 14960 versions of gcc have been known to emit dead "lui ...%hi(...)" 14961 instructions. */ 14962 if (lo_pos != NULL) 14963 { 14964 l->fixp->fx_offset = (*lo_pos)->fx_offset; 14965 if (l->fixp->fx_next != *lo_pos) 14966 { 14967 *hi_pos = l->fixp->fx_next; 14968 l->fixp->fx_next = *lo_pos; 14969 *lo_pos = l->fixp; 14970 } 14971 } 14972 } 14973} 14974 14975int 14976mips_force_relocation (fixS *fixp) 14977{ 14978 if (generic_force_reloc (fixp)) 14979 return 1; 14980 14981 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation, 14982 so that the linker relaxation can update targets. */ 14983 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 14984 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 14985 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1) 14986 return 1; 14987 14988 /* We want to keep BFD_RELOC_16_PCREL_S2 BFD_RELOC_MIPS_21_PCREL_S2 14989 and BFD_RELOC_MIPS_26_PCREL_S2 relocations against MIPS16 and 14990 microMIPS symbols so that we can do cross-mode branch diagnostics 14991 and BAL to JALX conversion by the linker. */ 14992 if ((fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 14993 || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2 14994 || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2) 14995 && fixp->fx_addsy 14996 && ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixp->fx_addsy))) 14997 return 1; 14998 14999 /* We want all PC-relative relocations to be kept for R6 relaxation. */ 15000 if (ISA_IS_R6 (file_mips_opts.isa) 15001 && (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 15002 || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2 15003 || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2 15004 || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3 15005 || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2 15006 || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL 15007 || fixp->fx_r_type == BFD_RELOC_LO16_PCREL)) 15008 return 1; 15009 15010 return 0; 15011} 15012 15013/* Implement TC_FORCE_RELOCATION_ABS. */ 15014 15015bfd_boolean 15016mips_force_relocation_abs (fixS *fixp) 15017{ 15018 if (generic_force_reloc (fixp)) 15019 return TRUE; 15020 15021 /* These relocations do not have enough bits in the in-place addend 15022 to hold an arbitrary absolute section's offset. */ 15023 if (HAVE_IN_PLACE_ADDENDS && limited_pcrel_reloc_p (fixp->fx_r_type)) 15024 return TRUE; 15025 15026 return FALSE; 15027} 15028 15029/* Read the instruction associated with RELOC from BUF. */ 15030 15031static unsigned int 15032read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc) 15033{ 15034 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) 15035 return read_compressed_insn (buf, 4); 15036 else 15037 return read_insn (buf); 15038} 15039 15040/* Write instruction INSN to BUF, given that it has been relocated 15041 by RELOC. */ 15042 15043static void 15044write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc, 15045 unsigned long insn) 15046{ 15047 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) 15048 write_compressed_insn (buf, insn, 4); 15049 else 15050 write_insn (buf, insn); 15051} 15052 15053/* Return TRUE if the instruction pointed to by FIXP is an invalid jump 15054 to a symbol in another ISA mode, which cannot be converted to JALX. */ 15055 15056static bfd_boolean 15057fix_bad_cross_mode_jump_p (fixS *fixP) 15058{ 15059 unsigned long opcode; 15060 int other; 15061 char *buf; 15062 15063 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) 15064 return FALSE; 15065 15066 other = S_GET_OTHER (fixP->fx_addsy); 15067 buf = fixP->fx_frag->fr_literal + fixP->fx_where; 15068 opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 26; 15069 switch (fixP->fx_r_type) 15070 { 15071 case BFD_RELOC_MIPS_JMP: 15072 return opcode != 0x1d && opcode != 0x03 && ELF_ST_IS_COMPRESSED (other); 15073 case BFD_RELOC_MICROMIPS_JMP: 15074 return opcode != 0x3c && opcode != 0x3d && !ELF_ST_IS_MICROMIPS (other); 15075 default: 15076 return FALSE; 15077 } 15078} 15079 15080/* Return TRUE if the instruction pointed to by FIXP is an invalid JALX 15081 jump to a symbol in the same ISA mode. */ 15082 15083static bfd_boolean 15084fix_bad_same_mode_jalx_p (fixS *fixP) 15085{ 15086 unsigned long opcode; 15087 int other; 15088 char *buf; 15089 15090 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) 15091 return FALSE; 15092 15093 other = S_GET_OTHER (fixP->fx_addsy); 15094 buf = fixP->fx_frag->fr_literal + fixP->fx_where; 15095 opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 26; 15096 switch (fixP->fx_r_type) 15097 { 15098 case BFD_RELOC_MIPS_JMP: 15099 return opcode == 0x1d && !ELF_ST_IS_COMPRESSED (other); 15100 case BFD_RELOC_MIPS16_JMP: 15101 return opcode == 0x07 && ELF_ST_IS_COMPRESSED (other); 15102 case BFD_RELOC_MICROMIPS_JMP: 15103 return opcode == 0x3c && ELF_ST_IS_COMPRESSED (other); 15104 default: 15105 return FALSE; 15106 } 15107} 15108 15109/* Return TRUE if the instruction pointed to by FIXP is an invalid jump 15110 to a symbol whose value plus addend is not aligned according to the 15111 ultimate (after linker relaxation) jump instruction's immediate field 15112 requirement, either to (1 << SHIFT), or, for jumps from microMIPS to 15113 regular MIPS code, to (1 << 2). */ 15114 15115static bfd_boolean 15116fix_bad_misaligned_jump_p (fixS *fixP, int shift) 15117{ 15118 bfd_boolean micro_to_mips_p; 15119 valueT val; 15120 int other; 15121 15122 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) 15123 return FALSE; 15124 15125 other = S_GET_OTHER (fixP->fx_addsy); 15126 val = S_GET_VALUE (fixP->fx_addsy) | ELF_ST_IS_COMPRESSED (other); 15127 val += fixP->fx_offset; 15128 micro_to_mips_p = (fixP->fx_r_type == BFD_RELOC_MICROMIPS_JMP 15129 && !ELF_ST_IS_MICROMIPS (other)); 15130 return ((val & ((1 << (micro_to_mips_p ? 2 : shift)) - 1)) 15131 != ELF_ST_IS_COMPRESSED (other)); 15132} 15133 15134/* Return TRUE if the instruction pointed to by FIXP is an invalid branch 15135 to a symbol whose annotation indicates another ISA mode. For absolute 15136 symbols check the ISA bit instead. 15137 15138 We accept BFD_RELOC_16_PCREL_S2 relocations against MIPS16 and microMIPS 15139 symbols or BFD_RELOC_MICROMIPS_16_PCREL_S1 relocations against regular 15140 MIPS symbols and associated with BAL instructions as these instructions 15141 may be be converted to JALX by the linker. */ 15142 15143static bfd_boolean 15144fix_bad_cross_mode_branch_p (fixS *fixP) 15145{ 15146 bfd_boolean absolute_p; 15147 unsigned long opcode; 15148 asection *symsec; 15149 valueT val; 15150 int other; 15151 char *buf; 15152 15153 if (mips_ignore_branch_isa) 15154 return FALSE; 15155 15156 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) 15157 return FALSE; 15158 15159 symsec = S_GET_SEGMENT (fixP->fx_addsy); 15160 absolute_p = bfd_is_abs_section (symsec); 15161 15162 val = S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset; 15163 other = S_GET_OTHER (fixP->fx_addsy); 15164 15165 buf = fixP->fx_frag->fr_literal + fixP->fx_where; 15166 opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 16; 15167 switch (fixP->fx_r_type) 15168 { 15169 case BFD_RELOC_16_PCREL_S2: 15170 return ((absolute_p ? val & 1 : ELF_ST_IS_COMPRESSED (other)) 15171 && opcode != 0x0411); 15172 case BFD_RELOC_MICROMIPS_16_PCREL_S1: 15173 return ((absolute_p ? !(val & 1) : !ELF_ST_IS_MICROMIPS (other)) 15174 && opcode != 0x4060); 15175 case BFD_RELOC_MIPS_21_PCREL_S2: 15176 case BFD_RELOC_MIPS_26_PCREL_S2: 15177 return absolute_p ? val & 1 : ELF_ST_IS_COMPRESSED (other); 15178 case BFD_RELOC_MIPS16_16_PCREL_S1: 15179 return absolute_p ? !(val & 1) : !ELF_ST_IS_MIPS16 (other); 15180 case BFD_RELOC_MICROMIPS_7_PCREL_S1: 15181 case BFD_RELOC_MICROMIPS_10_PCREL_S1: 15182 return absolute_p ? !(val & 1) : !ELF_ST_IS_MICROMIPS (other); 15183 default: 15184 abort (); 15185 } 15186} 15187 15188/* Return TRUE if the symbol plus addend associated with a regular MIPS 15189 branch instruction pointed to by FIXP is not aligned according to the 15190 branch instruction's immediate field requirement. We need the addend 15191 to preserve the ISA bit and also the sum must not have bit 2 set. We 15192 must explicitly OR in the ISA bit from symbol annotation as the bit 15193 won't be set in the symbol's value then. */ 15194 15195static bfd_boolean 15196fix_bad_misaligned_branch_p (fixS *fixP) 15197{ 15198 bfd_boolean absolute_p; 15199 asection *symsec; 15200 valueT isa_bit; 15201 valueT val; 15202 valueT off; 15203 int other; 15204 15205 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) 15206 return FALSE; 15207 15208 symsec = S_GET_SEGMENT (fixP->fx_addsy); 15209 absolute_p = bfd_is_abs_section (symsec); 15210 15211 val = S_GET_VALUE (fixP->fx_addsy); 15212 other = S_GET_OTHER (fixP->fx_addsy); 15213 off = fixP->fx_offset; 15214 15215 isa_bit = absolute_p ? (val + off) & 1 : ELF_ST_IS_COMPRESSED (other); 15216 val |= ELF_ST_IS_COMPRESSED (other); 15217 val += off; 15218 return (val & 0x3) != isa_bit; 15219} 15220 15221/* Make the necessary checks on a regular MIPS branch pointed to by FIXP 15222 and its calculated value VAL. */ 15223 15224static void 15225fix_validate_branch (fixS *fixP, valueT val) 15226{ 15227 if (fixP->fx_done && (val & 0x3) != 0) 15228 as_bad_where (fixP->fx_file, fixP->fx_line, 15229 _("branch to misaligned address (0x%lx)"), 15230 (long) (val + md_pcrel_from (fixP))); 15231 else if (fix_bad_cross_mode_branch_p (fixP)) 15232 as_bad_where (fixP->fx_file, fixP->fx_line, 15233 _("branch to a symbol in another ISA mode")); 15234 else if (fix_bad_misaligned_branch_p (fixP)) 15235 as_bad_where (fixP->fx_file, fixP->fx_line, 15236 _("branch to misaligned address (0x%lx)"), 15237 (long) (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset)); 15238 else if (HAVE_IN_PLACE_ADDENDS && (fixP->fx_offset & 0x3) != 0) 15239 as_bad_where (fixP->fx_file, fixP->fx_line, 15240 _("cannot encode misaligned addend " 15241 "in the relocatable field (0x%lx)"), 15242 (long) fixP->fx_offset); 15243} 15244 15245/* Apply a fixup to the object file. */ 15246 15247void 15248md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) 15249{ 15250 char *buf; 15251 unsigned long insn; 15252 reloc_howto_type *howto; 15253 15254 if (fixP->fx_pcrel) 15255 switch (fixP->fx_r_type) 15256 { 15257 case BFD_RELOC_16_PCREL_S2: 15258 case BFD_RELOC_MIPS16_16_PCREL_S1: 15259 case BFD_RELOC_MICROMIPS_7_PCREL_S1: 15260 case BFD_RELOC_MICROMIPS_10_PCREL_S1: 15261 case BFD_RELOC_MICROMIPS_16_PCREL_S1: 15262 case BFD_RELOC_32_PCREL: 15263 case BFD_RELOC_MIPS_21_PCREL_S2: 15264 case BFD_RELOC_MIPS_26_PCREL_S2: 15265 case BFD_RELOC_MIPS_18_PCREL_S3: 15266 case BFD_RELOC_MIPS_19_PCREL_S2: 15267 case BFD_RELOC_HI16_S_PCREL: 15268 case BFD_RELOC_LO16_PCREL: 15269 break; 15270 15271 case BFD_RELOC_32: 15272 fixP->fx_r_type = BFD_RELOC_32_PCREL; 15273 break; 15274 15275 default: 15276 as_bad_where (fixP->fx_file, fixP->fx_line, 15277 _("PC-relative reference to a different section")); 15278 break; 15279 } 15280 15281 /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations 15282 that have no MIPS ELF equivalent. */ 15283 if (fixP->fx_r_type != BFD_RELOC_8) 15284 { 15285 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); 15286 if (!howto) 15287 return; 15288 } 15289 15290 gas_assert (fixP->fx_size == 2 15291 || fixP->fx_size == 4 15292 || fixP->fx_r_type == BFD_RELOC_8 15293 || fixP->fx_r_type == BFD_RELOC_16 15294 || fixP->fx_r_type == BFD_RELOC_64 15295 || fixP->fx_r_type == BFD_RELOC_CTOR 15296 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB 15297 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB 15298 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 15299 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY 15300 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64 15301 || fixP->fx_r_type == BFD_RELOC_NONE); 15302 15303 buf = fixP->fx_frag->fr_literal + fixP->fx_where; 15304 15305 /* Don't treat parts of a composite relocation as done. There are two 15306 reasons for this: 15307 15308 (1) The second and third parts will be against 0 (RSS_UNDEF) but 15309 should nevertheless be emitted if the first part is. 15310 15311 (2) In normal usage, composite relocations are never assembly-time 15312 constants. The easiest way of dealing with the pathological 15313 exceptions is to generate a relocation against STN_UNDEF and 15314 leave everything up to the linker. */ 15315 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) 15316 fixP->fx_done = 1; 15317 15318 switch (fixP->fx_r_type) 15319 { 15320 case BFD_RELOC_MIPS_TLS_GD: 15321 case BFD_RELOC_MIPS_TLS_LDM: 15322 case BFD_RELOC_MIPS_TLS_DTPREL32: 15323 case BFD_RELOC_MIPS_TLS_DTPREL64: 15324 case BFD_RELOC_MIPS_TLS_DTPREL_HI16: 15325 case BFD_RELOC_MIPS_TLS_DTPREL_LO16: 15326 case BFD_RELOC_MIPS_TLS_GOTTPREL: 15327 case BFD_RELOC_MIPS_TLS_TPREL32: 15328 case BFD_RELOC_MIPS_TLS_TPREL64: 15329 case BFD_RELOC_MIPS_TLS_TPREL_HI16: 15330 case BFD_RELOC_MIPS_TLS_TPREL_LO16: 15331 case BFD_RELOC_MICROMIPS_TLS_GD: 15332 case BFD_RELOC_MICROMIPS_TLS_LDM: 15333 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16: 15334 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16: 15335 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL: 15336 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16: 15337 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16: 15338 case BFD_RELOC_MIPS16_TLS_GD: 15339 case BFD_RELOC_MIPS16_TLS_LDM: 15340 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16: 15341 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16: 15342 case BFD_RELOC_MIPS16_TLS_GOTTPREL: 15343 case BFD_RELOC_MIPS16_TLS_TPREL_HI16: 15344 case BFD_RELOC_MIPS16_TLS_TPREL_LO16: 15345 if (fixP->fx_addsy) 15346 S_SET_THREAD_LOCAL (fixP->fx_addsy); 15347 else 15348 as_bad_where (fixP->fx_file, fixP->fx_line, 15349 _("TLS relocation against a constant")); 15350 break; 15351 15352 case BFD_RELOC_MIPS_JMP: 15353 case BFD_RELOC_MIPS16_JMP: 15354 case BFD_RELOC_MICROMIPS_JMP: 15355 { 15356 int shift; 15357 15358 gas_assert (!fixP->fx_done); 15359 15360 /* Shift is 2, unusually, for microMIPS JALX. */ 15361 if (fixP->fx_r_type == BFD_RELOC_MICROMIPS_JMP 15362 && (read_compressed_insn (buf, 4) >> 26) != 0x3c) 15363 shift = 1; 15364 else 15365 shift = 2; 15366 15367 if (fix_bad_cross_mode_jump_p (fixP)) 15368 as_bad_where (fixP->fx_file, fixP->fx_line, 15369 _("jump to a symbol in another ISA mode")); 15370 else if (fix_bad_same_mode_jalx_p (fixP)) 15371 as_bad_where (fixP->fx_file, fixP->fx_line, 15372 _("JALX to a symbol in the same ISA mode")); 15373 else if (fix_bad_misaligned_jump_p (fixP, shift)) 15374 as_bad_where (fixP->fx_file, fixP->fx_line, 15375 _("jump to misaligned address (0x%lx)"), 15376 (long) (S_GET_VALUE (fixP->fx_addsy) 15377 + fixP->fx_offset)); 15378 else if (HAVE_IN_PLACE_ADDENDS 15379 && (fixP->fx_offset & ((1 << shift) - 1)) != 0) 15380 as_bad_where (fixP->fx_file, fixP->fx_line, 15381 _("cannot encode misaligned addend " 15382 "in the relocatable field (0x%lx)"), 15383 (long) fixP->fx_offset); 15384 } 15385 /* Fall through. */ 15386 15387 case BFD_RELOC_MIPS_SHIFT5: 15388 case BFD_RELOC_MIPS_SHIFT6: 15389 case BFD_RELOC_MIPS_GOT_DISP: 15390 case BFD_RELOC_MIPS_GOT_PAGE: 15391 case BFD_RELOC_MIPS_GOT_OFST: 15392 case BFD_RELOC_MIPS_SUB: 15393 case BFD_RELOC_MIPS_INSERT_A: 15394 case BFD_RELOC_MIPS_INSERT_B: 15395 case BFD_RELOC_MIPS_DELETE: 15396 case BFD_RELOC_MIPS_HIGHEST: 15397 case BFD_RELOC_MIPS_HIGHER: 15398 case BFD_RELOC_MIPS_SCN_DISP: 15399 case BFD_RELOC_MIPS_REL16: 15400 case BFD_RELOC_MIPS_RELGOT: 15401 case BFD_RELOC_MIPS_JALR: 15402 case BFD_RELOC_HI16: 15403 case BFD_RELOC_HI16_S: 15404 case BFD_RELOC_LO16: 15405 case BFD_RELOC_GPREL16: 15406 case BFD_RELOC_MIPS_LITERAL: 15407 case BFD_RELOC_MIPS_CALL16: 15408 case BFD_RELOC_MIPS_GOT16: 15409 case BFD_RELOC_GPREL32: 15410 case BFD_RELOC_MIPS_GOT_HI16: 15411 case BFD_RELOC_MIPS_GOT_LO16: 15412 case BFD_RELOC_MIPS_CALL_HI16: 15413 case BFD_RELOC_MIPS_CALL_LO16: 15414 case BFD_RELOC_HI16_S_PCREL: 15415 case BFD_RELOC_LO16_PCREL: 15416 case BFD_RELOC_MIPS16_GPREL: 15417 case BFD_RELOC_MIPS16_GOT16: 15418 case BFD_RELOC_MIPS16_CALL16: 15419 case BFD_RELOC_MIPS16_HI16: 15420 case BFD_RELOC_MIPS16_HI16_S: 15421 case BFD_RELOC_MIPS16_LO16: 15422 case BFD_RELOC_MICROMIPS_GOT_DISP: 15423 case BFD_RELOC_MICROMIPS_GOT_PAGE: 15424 case BFD_RELOC_MICROMIPS_GOT_OFST: 15425 case BFD_RELOC_MICROMIPS_SUB: 15426 case BFD_RELOC_MICROMIPS_HIGHEST: 15427 case BFD_RELOC_MICROMIPS_HIGHER: 15428 case BFD_RELOC_MICROMIPS_SCN_DISP: 15429 case BFD_RELOC_MICROMIPS_JALR: 15430 case BFD_RELOC_MICROMIPS_HI16: 15431 case BFD_RELOC_MICROMIPS_HI16_S: 15432 case BFD_RELOC_MICROMIPS_LO16: 15433 case BFD_RELOC_MICROMIPS_GPREL16: 15434 case BFD_RELOC_MICROMIPS_LITERAL: 15435 case BFD_RELOC_MICROMIPS_CALL16: 15436 case BFD_RELOC_MICROMIPS_GOT16: 15437 case BFD_RELOC_MICROMIPS_GOT_HI16: 15438 case BFD_RELOC_MICROMIPS_GOT_LO16: 15439 case BFD_RELOC_MICROMIPS_CALL_HI16: 15440 case BFD_RELOC_MICROMIPS_CALL_LO16: 15441 case BFD_RELOC_MIPS_EH: 15442 if (fixP->fx_done) 15443 { 15444 offsetT value; 15445 15446 if (calculate_reloc (fixP->fx_r_type, *valP, &value)) 15447 { 15448 insn = read_reloc_insn (buf, fixP->fx_r_type); 15449 if (mips16_reloc_p (fixP->fx_r_type)) 15450 insn |= mips16_immed_extend (value, 16); 15451 else 15452 insn |= (value & 0xffff); 15453 write_reloc_insn (buf, fixP->fx_r_type, insn); 15454 } 15455 else 15456 as_bad_where (fixP->fx_file, fixP->fx_line, 15457 _("unsupported constant in relocation")); 15458 } 15459 break; 15460 15461 case BFD_RELOC_64: 15462 /* This is handled like BFD_RELOC_32, but we output a sign 15463 extended value if we are only 32 bits. */ 15464 if (fixP->fx_done) 15465 { 15466 if (8 <= sizeof (valueT)) 15467 md_number_to_chars (buf, *valP, 8); 15468 else 15469 { 15470 valueT hiv; 15471 15472 if ((*valP & 0x80000000) != 0) 15473 hiv = 0xffffffff; 15474 else 15475 hiv = 0; 15476 md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4); 15477 md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4); 15478 } 15479 } 15480 break; 15481 15482 case BFD_RELOC_RVA: 15483 case BFD_RELOC_32: 15484 case BFD_RELOC_32_PCREL: 15485 case BFD_RELOC_16: 15486 case BFD_RELOC_8: 15487 /* If we are deleting this reloc entry, we must fill in the 15488 value now. This can happen if we have a .word which is not 15489 resolved when it appears but is later defined. */ 15490 if (fixP->fx_done) 15491 md_number_to_chars (buf, *valP, fixP->fx_size); 15492 break; 15493 15494 case BFD_RELOC_MIPS_21_PCREL_S2: 15495 fix_validate_branch (fixP, *valP); 15496 if (!fixP->fx_done) 15497 break; 15498 15499 if (*valP + 0x400000 <= 0x7fffff) 15500 { 15501 insn = read_insn (buf); 15502 insn |= (*valP >> 2) & 0x1fffff; 15503 write_insn (buf, insn); 15504 } 15505 else 15506 as_bad_where (fixP->fx_file, fixP->fx_line, 15507 _("branch out of range")); 15508 break; 15509 15510 case BFD_RELOC_MIPS_26_PCREL_S2: 15511 fix_validate_branch (fixP, *valP); 15512 if (!fixP->fx_done) 15513 break; 15514 15515 if (*valP + 0x8000000 <= 0xfffffff) 15516 { 15517 insn = read_insn (buf); 15518 insn |= (*valP >> 2) & 0x3ffffff; 15519 write_insn (buf, insn); 15520 } 15521 else 15522 as_bad_where (fixP->fx_file, fixP->fx_line, 15523 _("branch out of range")); 15524 break; 15525 15526 case BFD_RELOC_MIPS_18_PCREL_S3: 15527 if (fixP->fx_addsy && (S_GET_VALUE (fixP->fx_addsy) & 0x7) != 0) 15528 as_bad_where (fixP->fx_file, fixP->fx_line, 15529 _("PC-relative access using misaligned symbol (%lx)"), 15530 (long) S_GET_VALUE (fixP->fx_addsy)); 15531 if ((fixP->fx_offset & 0x7) != 0) 15532 as_bad_where (fixP->fx_file, fixP->fx_line, 15533 _("PC-relative access using misaligned offset (%lx)"), 15534 (long) fixP->fx_offset); 15535 if (!fixP->fx_done) 15536 break; 15537 15538 if (*valP + 0x100000 <= 0x1fffff) 15539 { 15540 insn = read_insn (buf); 15541 insn |= (*valP >> 3) & 0x3ffff; 15542 write_insn (buf, insn); 15543 } 15544 else 15545 as_bad_where (fixP->fx_file, fixP->fx_line, 15546 _("PC-relative access out of range")); 15547 break; 15548 15549 case BFD_RELOC_MIPS_19_PCREL_S2: 15550 if ((*valP & 0x3) != 0) 15551 as_bad_where (fixP->fx_file, fixP->fx_line, 15552 _("PC-relative access to misaligned address (%lx)"), 15553 (long) *valP); 15554 if (!fixP->fx_done) 15555 break; 15556 15557 if (*valP + 0x100000 <= 0x1fffff) 15558 { 15559 insn = read_insn (buf); 15560 insn |= (*valP >> 2) & 0x7ffff; 15561 write_insn (buf, insn); 15562 } 15563 else 15564 as_bad_where (fixP->fx_file, fixP->fx_line, 15565 _("PC-relative access out of range")); 15566 break; 15567 15568 case BFD_RELOC_16_PCREL_S2: 15569 fix_validate_branch (fixP, *valP); 15570 15571 /* We need to save the bits in the instruction since fixup_segment() 15572 might be deleting the relocation entry (i.e., a branch within 15573 the current segment). */ 15574 if (! fixP->fx_done) 15575 break; 15576 15577 /* Update old instruction data. */ 15578 insn = read_insn (buf); 15579 15580 if (*valP + 0x20000 <= 0x3ffff) 15581 { 15582 insn |= (*valP >> 2) & 0xffff; 15583 write_insn (buf, insn); 15584 } 15585 else if (mips_pic == NO_PIC 15586 && fixP->fx_done 15587 && fixP->fx_frag->fr_address >= text_section->vma 15588 && (fixP->fx_frag->fr_address 15589 < text_section->vma + bfd_get_section_size (text_section)) 15590 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ 15591 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ 15592 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ 15593 { 15594 /* The branch offset is too large. If this is an 15595 unconditional branch, and we are not generating PIC code, 15596 we can convert it to an absolute jump instruction. */ 15597 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ 15598 insn = 0x0c000000; /* jal */ 15599 else 15600 insn = 0x08000000; /* j */ 15601 fixP->fx_r_type = BFD_RELOC_MIPS_JMP; 15602 fixP->fx_done = 0; 15603 fixP->fx_addsy = section_symbol (text_section); 15604 *valP += md_pcrel_from (fixP); 15605 write_insn (buf, insn); 15606 } 15607 else 15608 { 15609 /* If we got here, we have branch-relaxation disabled, 15610 and there's nothing we can do to fix this instruction 15611 without turning it into a longer sequence. */ 15612 as_bad_where (fixP->fx_file, fixP->fx_line, 15613 _("branch out of range")); 15614 } 15615 break; 15616 15617 case BFD_RELOC_MIPS16_16_PCREL_S1: 15618 case BFD_RELOC_MICROMIPS_7_PCREL_S1: 15619 case BFD_RELOC_MICROMIPS_10_PCREL_S1: 15620 case BFD_RELOC_MICROMIPS_16_PCREL_S1: 15621 gas_assert (!fixP->fx_done); 15622 if (fix_bad_cross_mode_branch_p (fixP)) 15623 as_bad_where (fixP->fx_file, fixP->fx_line, 15624 _("branch to a symbol in another ISA mode")); 15625 else if (fixP->fx_addsy 15626 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) 15627 && !bfd_is_abs_section (S_GET_SEGMENT (fixP->fx_addsy)) 15628 && (fixP->fx_offset & 0x1) != 0) 15629 as_bad_where (fixP->fx_file, fixP->fx_line, 15630 _("branch to misaligned address (0x%lx)"), 15631 (long) (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset)); 15632 else if (HAVE_IN_PLACE_ADDENDS && (fixP->fx_offset & 0x1) != 0) 15633 as_bad_where (fixP->fx_file, fixP->fx_line, 15634 _("cannot encode misaligned addend " 15635 "in the relocatable field (0x%lx)"), 15636 (long) fixP->fx_offset); 15637 break; 15638 15639 case BFD_RELOC_VTABLE_INHERIT: 15640 fixP->fx_done = 0; 15641 if (fixP->fx_addsy 15642 && !S_IS_DEFINED (fixP->fx_addsy) 15643 && !S_IS_WEAK (fixP->fx_addsy)) 15644 S_SET_WEAK (fixP->fx_addsy); 15645 break; 15646 15647 case BFD_RELOC_NONE: 15648 case BFD_RELOC_VTABLE_ENTRY: 15649 fixP->fx_done = 0; 15650 break; 15651 15652 default: 15653 abort (); 15654 } 15655 15656 /* Remember value for tc_gen_reloc. */ 15657 fixP->fx_addnumber = *valP; 15658} 15659 15660static symbolS * 15661get_symbol (void) 15662{ 15663 int c; 15664 char *name; 15665 symbolS *p; 15666 15667 c = get_symbol_name (&name); 15668 p = (symbolS *) symbol_find_or_make (name); 15669 (void) restore_line_pointer (c); 15670 return p; 15671} 15672 15673/* Align the current frag to a given power of two. If a particular 15674 fill byte should be used, FILL points to an integer that contains 15675 that byte, otherwise FILL is null. 15676 15677 This function used to have the comment: 15678 15679 The MIPS assembler also automatically adjusts any preceding label. 15680 15681 The implementation therefore applied the adjustment to a maximum of 15682 one label. However, other label adjustments are applied to batches 15683 of labels, and adjusting just one caused problems when new labels 15684 were added for the sake of debugging or unwind information. 15685 We therefore adjust all preceding labels (given as LABELS) instead. */ 15686 15687static void 15688mips_align (int to, int *fill, struct insn_label_list *labels) 15689{ 15690 mips_emit_delays (); 15691 mips_record_compressed_mode (); 15692 if (fill == NULL && subseg_text_p (now_seg)) 15693 frag_align_code (to, 0); 15694 else 15695 frag_align (to, fill ? *fill : 0, 0); 15696 record_alignment (now_seg, to); 15697 mips_move_labels (labels, FALSE); 15698} 15699 15700/* Align to a given power of two. .align 0 turns off the automatic 15701 alignment used by the data creating pseudo-ops. */ 15702 15703static void 15704s_align (int x ATTRIBUTE_UNUSED) 15705{ 15706 int temp, fill_value, *fill_ptr; 15707 long max_alignment = 28; 15708 15709 /* o Note that the assembler pulls down any immediately preceding label 15710 to the aligned address. 15711 o It's not documented but auto alignment is reinstated by 15712 a .align pseudo instruction. 15713 o Note also that after auto alignment is turned off the mips assembler 15714 issues an error on attempt to assemble an improperly aligned data item. 15715 We don't. */ 15716 15717 temp = get_absolute_expression (); 15718 if (temp > max_alignment) 15719 as_bad (_("alignment too large, %d assumed"), temp = max_alignment); 15720 else if (temp < 0) 15721 { 15722 as_warn (_("alignment negative, 0 assumed")); 15723 temp = 0; 15724 } 15725 if (*input_line_pointer == ',') 15726 { 15727 ++input_line_pointer; 15728 fill_value = get_absolute_expression (); 15729 fill_ptr = &fill_value; 15730 } 15731 else 15732 fill_ptr = 0; 15733 if (temp) 15734 { 15735 segment_info_type *si = seg_info (now_seg); 15736 struct insn_label_list *l = si->label_list; 15737 /* Auto alignment should be switched on by next section change. */ 15738 auto_align = 1; 15739 mips_align (temp, fill_ptr, l); 15740 } 15741 else 15742 { 15743 auto_align = 0; 15744 } 15745 15746 demand_empty_rest_of_line (); 15747} 15748 15749static void 15750s_change_sec (int sec) 15751{ 15752 segT seg; 15753 15754 /* The ELF backend needs to know that we are changing sections, so 15755 that .previous works correctly. We could do something like check 15756 for an obj_section_change_hook macro, but that might be confusing 15757 as it would not be appropriate to use it in the section changing 15758 functions in read.c, since obj-elf.c intercepts those. FIXME: 15759 This should be cleaner, somehow. */ 15760 obj_elf_section_change_hook (); 15761 15762 mips_emit_delays (); 15763 15764 switch (sec) 15765 { 15766 case 't': 15767 s_text (0); 15768 break; 15769 case 'd': 15770 s_data (0); 15771 break; 15772 case 'b': 15773 subseg_set (bss_section, (subsegT) get_absolute_expression ()); 15774 demand_empty_rest_of_line (); 15775 break; 15776 15777 case 'r': 15778 seg = subseg_new (RDATA_SECTION_NAME, 15779 (subsegT) get_absolute_expression ()); 15780 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD 15781 | SEC_READONLY | SEC_RELOC 15782 | SEC_DATA)); 15783 if (strncmp (TARGET_OS, "elf", 3) != 0) 15784 record_alignment (seg, 4); 15785 demand_empty_rest_of_line (); 15786 break; 15787 15788 case 's': 15789 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); 15790 bfd_set_section_flags (stdoutput, seg, 15791 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); 15792 if (strncmp (TARGET_OS, "elf", 3) != 0) 15793 record_alignment (seg, 4); 15794 demand_empty_rest_of_line (); 15795 break; 15796 15797 case 'B': 15798 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ()); 15799 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC); 15800 if (strncmp (TARGET_OS, "elf", 3) != 0) 15801 record_alignment (seg, 4); 15802 demand_empty_rest_of_line (); 15803 break; 15804 } 15805 15806 auto_align = 1; 15807} 15808 15809void 15810s_change_section (int ignore ATTRIBUTE_UNUSED) 15811{ 15812 char *saved_ilp; 15813 char *section_name; 15814 char c, endc; 15815 char next_c = 0; 15816 int section_type; 15817 int section_flag; 15818 int section_entry_size; 15819 int section_alignment; 15820 15821 saved_ilp = input_line_pointer; 15822 endc = get_symbol_name (§ion_name); 15823 c = (endc == '"' ? input_line_pointer[1] : endc); 15824 if (c) 15825 next_c = input_line_pointer [(endc == '"' ? 2 : 1)]; 15826 15827 /* Do we have .section Name<,"flags">? */ 15828 if (c != ',' || (c == ',' && next_c == '"')) 15829 { 15830 /* Just after name is now '\0'. */ 15831 (void) restore_line_pointer (endc); 15832 input_line_pointer = saved_ilp; 15833 obj_elf_section (ignore); 15834 return; 15835 } 15836 15837 section_name = xstrdup (section_name); 15838 c = restore_line_pointer (endc); 15839 15840 input_line_pointer++; 15841 15842 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ 15843 if (c == ',') 15844 section_type = get_absolute_expression (); 15845 else 15846 section_type = 0; 15847 15848 if (*input_line_pointer++ == ',') 15849 section_flag = get_absolute_expression (); 15850 else 15851 section_flag = 0; 15852 15853 if (*input_line_pointer++ == ',') 15854 section_entry_size = get_absolute_expression (); 15855 else 15856 section_entry_size = 0; 15857 15858 if (*input_line_pointer++ == ',') 15859 section_alignment = get_absolute_expression (); 15860 else 15861 section_alignment = 0; 15862 15863 /* FIXME: really ignore? */ 15864 (void) section_alignment; 15865 15866 /* When using the generic form of .section (as implemented by obj-elf.c), 15867 there's no way to set the section type to SHT_MIPS_DWARF. Users have 15868 traditionally had to fall back on the more common @progbits instead. 15869 15870 There's nothing really harmful in this, since bfd will correct 15871 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it 15872 means that, for backwards compatibility, the special_section entries 15873 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. 15874 15875 Even so, we shouldn't force users of the MIPS .section syntax to 15876 incorrectly label the sections as SHT_PROGBITS. The best compromise 15877 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the 15878 generic type-checking code. */ 15879 if (section_type == SHT_MIPS_DWARF) 15880 section_type = SHT_PROGBITS; 15881 15882 obj_elf_change_section (section_name, section_type, section_flag, 15883 section_entry_size, 0, 0, 0); 15884 15885 if (now_seg->name != section_name) 15886 free (section_name); 15887} 15888 15889void 15890mips_enable_auto_align (void) 15891{ 15892 auto_align = 1; 15893} 15894 15895static void 15896s_cons (int log_size) 15897{ 15898 segment_info_type *si = seg_info (now_seg); 15899 struct insn_label_list *l = si->label_list; 15900 15901 mips_emit_delays (); 15902 if (log_size > 0 && auto_align) 15903 mips_align (log_size, 0, l); 15904 cons (1 << log_size); 15905 mips_clear_insn_labels (); 15906} 15907 15908static void 15909s_float_cons (int type) 15910{ 15911 segment_info_type *si = seg_info (now_seg); 15912 struct insn_label_list *l = si->label_list; 15913 15914 mips_emit_delays (); 15915 15916 if (auto_align) 15917 { 15918 if (type == 'd') 15919 mips_align (3, 0, l); 15920 else 15921 mips_align (2, 0, l); 15922 } 15923 15924 float_cons (type); 15925 mips_clear_insn_labels (); 15926} 15927 15928/* Handle .globl. We need to override it because on Irix 5 you are 15929 permitted to say 15930 .globl foo .text 15931 where foo is an undefined symbol, to mean that foo should be 15932 considered to be the address of a function. */ 15933 15934static void 15935s_mips_globl (int x ATTRIBUTE_UNUSED) 15936{ 15937 char *name; 15938 int c; 15939 symbolS *symbolP; 15940 flagword flag; 15941 15942 do 15943 { 15944 c = get_symbol_name (&name); 15945 symbolP = symbol_find_or_make (name); 15946 S_SET_EXTERNAL (symbolP); 15947 15948 *input_line_pointer = c; 15949 SKIP_WHITESPACE_AFTER_NAME (); 15950 15951 /* On Irix 5, every global symbol that is not explicitly labelled as 15952 being a function is apparently labelled as being an object. */ 15953 flag = BSF_OBJECT; 15954 15955 if (!is_end_of_line[(unsigned char) *input_line_pointer] 15956 && (*input_line_pointer != ',')) 15957 { 15958 char *secname; 15959 asection *sec; 15960 15961 c = get_symbol_name (&secname); 15962 sec = bfd_get_section_by_name (stdoutput, secname); 15963 if (sec == NULL) 15964 as_bad (_("%s: no such section"), secname); 15965 (void) restore_line_pointer (c); 15966 15967 if (sec != NULL && (sec->flags & SEC_CODE) != 0) 15968 flag = BSF_FUNCTION; 15969 } 15970 15971 symbol_get_bfdsym (symbolP)->flags |= flag; 15972 15973 c = *input_line_pointer; 15974 if (c == ',') 15975 { 15976 input_line_pointer++; 15977 SKIP_WHITESPACE (); 15978 if (is_end_of_line[(unsigned char) *input_line_pointer]) 15979 c = '\n'; 15980 } 15981 } 15982 while (c == ','); 15983 15984 demand_empty_rest_of_line (); 15985} 15986 15987static void 15988s_option (int x ATTRIBUTE_UNUSED) 15989{ 15990 char *opt; 15991 char c; 15992 15993 c = get_symbol_name (&opt); 15994 15995 if (*opt == 'O') 15996 { 15997 /* FIXME: What does this mean? */ 15998 } 15999 else if (strncmp (opt, "pic", 3) == 0 && ISDIGIT (opt[3]) && opt[4] == '\0') 16000 { 16001 int i; 16002 16003 i = atoi (opt + 3); 16004 if (i != 0 && i != 2) 16005 as_bad (_(".option pic%d not supported"), i); 16006 else if (mips_pic == VXWORKS_PIC) 16007 as_bad (_(".option pic%d not supported in VxWorks PIC mode"), i); 16008 else if (i == 0) 16009 mips_pic = NO_PIC; 16010 else if (i == 2) 16011 { 16012 mips_pic = SVR4_PIC; 16013 mips_abicalls = TRUE; 16014 } 16015 16016 if (mips_pic == SVR4_PIC) 16017 { 16018 if (g_switch_seen && g_switch_value != 0) 16019 as_warn (_("-G may not be used with SVR4 PIC code")); 16020 g_switch_value = 0; 16021 bfd_set_gp_size (stdoutput, 0); 16022 } 16023 } 16024 else 16025 as_warn (_("unrecognized option \"%s\""), opt); 16026 16027 (void) restore_line_pointer (c); 16028 demand_empty_rest_of_line (); 16029} 16030 16031/* This structure is used to hold a stack of .set values. */ 16032 16033struct mips_option_stack 16034{ 16035 struct mips_option_stack *next; 16036 struct mips_set_options options; 16037}; 16038 16039static struct mips_option_stack *mips_opts_stack; 16040 16041/* Return status for .set/.module option handling. */ 16042 16043enum code_option_type 16044{ 16045 /* Unrecognized option. */ 16046 OPTION_TYPE_BAD = -1, 16047 16048 /* Ordinary option. */ 16049 OPTION_TYPE_NORMAL, 16050 16051 /* ISA changing option. */ 16052 OPTION_TYPE_ISA 16053}; 16054 16055/* Handle common .set/.module options. Return status indicating option 16056 type. */ 16057 16058static enum code_option_type 16059parse_code_option (char * name) 16060{ 16061 bfd_boolean isa_set = FALSE; 16062 const struct mips_ase *ase; 16063 16064 if (strncmp (name, "at=", 3) == 0) 16065 { 16066 char *s = name + 3; 16067 16068 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at)) 16069 as_bad (_("unrecognized register name `%s'"), s); 16070 } 16071 else if (strcmp (name, "at") == 0) 16072 mips_opts.at = ATREG; 16073 else if (strcmp (name, "noat") == 0) 16074 mips_opts.at = ZERO; 16075 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) 16076 mips_opts.nomove = 0; 16077 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) 16078 mips_opts.nomove = 1; 16079 else if (strcmp (name, "bopt") == 0) 16080 mips_opts.nobopt = 0; 16081 else if (strcmp (name, "nobopt") == 0) 16082 mips_opts.nobopt = 1; 16083 else if (strcmp (name, "gp=32") == 0) 16084 mips_opts.gp = 32; 16085 else if (strcmp (name, "gp=64") == 0) 16086 mips_opts.gp = 64; 16087 else if (strcmp (name, "fp=32") == 0) 16088 mips_opts.fp = 32; 16089 else if (strcmp (name, "fp=xx") == 0) 16090 mips_opts.fp = 0; 16091 else if (strcmp (name, "fp=64") == 0) 16092 mips_opts.fp = 64; 16093 else if (strcmp (name, "softfloat") == 0) 16094 mips_opts.soft_float = 1; 16095 else if (strcmp (name, "hardfloat") == 0) 16096 mips_opts.soft_float = 0; 16097 else if (strcmp (name, "singlefloat") == 0) 16098 mips_opts.single_float = 1; 16099 else if (strcmp (name, "doublefloat") == 0) 16100 mips_opts.single_float = 0; 16101 else if (strcmp (name, "nooddspreg") == 0) 16102 mips_opts.oddspreg = 0; 16103 else if (strcmp (name, "oddspreg") == 0) 16104 mips_opts.oddspreg = 1; 16105 else if (strcmp (name, "mips16") == 0 16106 || strcmp (name, "MIPS-16") == 0) 16107 mips_opts.mips16 = 1; 16108 else if (strcmp (name, "nomips16") == 0 16109 || strcmp (name, "noMIPS-16") == 0) 16110 mips_opts.mips16 = 0; 16111 else if (strcmp (name, "micromips") == 0) 16112 mips_opts.micromips = 1; 16113 else if (strcmp (name, "nomicromips") == 0) 16114 mips_opts.micromips = 0; 16115 else if (name[0] == 'n' 16116 && name[1] == 'o' 16117 && (ase = mips_lookup_ase (name + 2))) 16118 mips_set_ase (ase, &mips_opts, FALSE); 16119 else if ((ase = mips_lookup_ase (name))) 16120 mips_set_ase (ase, &mips_opts, TRUE); 16121 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) 16122 { 16123 /* Permit the user to change the ISA and architecture on the fly. 16124 Needless to say, misuse can cause serious problems. */ 16125 if (strncmp (name, "arch=", 5) == 0) 16126 { 16127 const struct mips_cpu_info *p; 16128 16129 p = mips_parse_cpu ("internal use", name + 5); 16130 if (!p) 16131 as_bad (_("unknown architecture %s"), name + 5); 16132 else 16133 { 16134 mips_opts.arch = p->cpu; 16135 mips_opts.isa = p->isa; 16136 isa_set = TRUE; 16137 } 16138 } 16139 else if (strncmp (name, "mips", 4) == 0) 16140 { 16141 const struct mips_cpu_info *p; 16142 16143 p = mips_parse_cpu ("internal use", name); 16144 if (!p) 16145 as_bad (_("unknown ISA level %s"), name + 4); 16146 else 16147 { 16148 mips_opts.arch = p->cpu; 16149 mips_opts.isa = p->isa; 16150 isa_set = TRUE; 16151 } 16152 } 16153 else 16154 as_bad (_("unknown ISA or architecture %s"), name); 16155 } 16156 else if (strcmp (name, "autoextend") == 0) 16157 mips_opts.noautoextend = 0; 16158 else if (strcmp (name, "noautoextend") == 0) 16159 mips_opts.noautoextend = 1; 16160 else if (strcmp (name, "insn32") == 0) 16161 mips_opts.insn32 = TRUE; 16162 else if (strcmp (name, "noinsn32") == 0) 16163 mips_opts.insn32 = FALSE; 16164 else if (strcmp (name, "sym32") == 0) 16165 mips_opts.sym32 = TRUE; 16166 else if (strcmp (name, "nosym32") == 0) 16167 mips_opts.sym32 = FALSE; 16168 else 16169 return OPTION_TYPE_BAD; 16170 16171 return isa_set ? OPTION_TYPE_ISA : OPTION_TYPE_NORMAL; 16172} 16173 16174/* Handle the .set pseudo-op. */ 16175 16176static void 16177s_mipsset (int x ATTRIBUTE_UNUSED) 16178{ 16179 enum code_option_type type = OPTION_TYPE_NORMAL; 16180 char *name = input_line_pointer, ch; 16181 16182 file_mips_check_options (); 16183 16184 while (!is_end_of_line[(unsigned char) *input_line_pointer]) 16185 ++input_line_pointer; 16186 ch = *input_line_pointer; 16187 *input_line_pointer = '\0'; 16188 16189 if (strchr (name, ',')) 16190 { 16191 /* Generic ".set" directive; use the generic handler. */ 16192 *input_line_pointer = ch; 16193 input_line_pointer = name; 16194 s_set (0); 16195 return; 16196 } 16197 16198 if (strcmp (name, "reorder") == 0) 16199 { 16200 if (mips_opts.noreorder) 16201 end_noreorder (); 16202 } 16203 else if (strcmp (name, "noreorder") == 0) 16204 { 16205 if (!mips_opts.noreorder) 16206 start_noreorder (); 16207 } 16208 else if (strcmp (name, "macro") == 0) 16209 mips_opts.warn_about_macros = 0; 16210 else if (strcmp (name, "nomacro") == 0) 16211 { 16212 if (mips_opts.noreorder == 0) 16213 as_bad (_("`noreorder' must be set before `nomacro'")); 16214 mips_opts.warn_about_macros = 1; 16215 } 16216 else if (strcmp (name, "gp=default") == 0) 16217 mips_opts.gp = file_mips_opts.gp; 16218 else if (strcmp (name, "fp=default") == 0) 16219 mips_opts.fp = file_mips_opts.fp; 16220 else if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) 16221 { 16222 mips_opts.isa = file_mips_opts.isa; 16223 mips_opts.arch = file_mips_opts.arch; 16224 mips_opts.gp = file_mips_opts.gp; 16225 mips_opts.fp = file_mips_opts.fp; 16226 } 16227 else if (strcmp (name, "push") == 0) 16228 { 16229 struct mips_option_stack *s; 16230 16231 s = XNEW (struct mips_option_stack); 16232 s->next = mips_opts_stack; 16233 s->options = mips_opts; 16234 mips_opts_stack = s; 16235 } 16236 else if (strcmp (name, "pop") == 0) 16237 { 16238 struct mips_option_stack *s; 16239 16240 s = mips_opts_stack; 16241 if (s == NULL) 16242 as_bad (_(".set pop with no .set push")); 16243 else 16244 { 16245 /* If we're changing the reorder mode we need to handle 16246 delay slots correctly. */ 16247 if (s->options.noreorder && ! mips_opts.noreorder) 16248 start_noreorder (); 16249 else if (! s->options.noreorder && mips_opts.noreorder) 16250 end_noreorder (); 16251 16252 mips_opts = s->options; 16253 mips_opts_stack = s->next; 16254 free (s); 16255 } 16256 } 16257 else 16258 { 16259 type = parse_code_option (name); 16260 if (type == OPTION_TYPE_BAD) 16261 as_warn (_("tried to set unrecognized symbol: %s\n"), name); 16262 } 16263 16264 /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp 16265 registers based on what is supported by the arch/cpu. */ 16266 if (type == OPTION_TYPE_ISA) 16267 { 16268 switch (mips_opts.isa) 16269 { 16270 case 0: 16271 break; 16272 case ISA_MIPS1: 16273 /* MIPS I cannot support FPXX. */ 16274 mips_opts.fp = 32; 16275 /* fall-through. */ 16276 case ISA_MIPS2: 16277 case ISA_MIPS32: 16278 case ISA_MIPS32R2: 16279 case ISA_MIPS32R3: 16280 case ISA_MIPS32R5: 16281 mips_opts.gp = 32; 16282 if (mips_opts.fp != 0) 16283 mips_opts.fp = 32; 16284 break; 16285 case ISA_MIPS32R6: 16286 mips_opts.gp = 32; 16287 mips_opts.fp = 64; 16288 break; 16289 case ISA_MIPS3: 16290 case ISA_MIPS4: 16291 case ISA_MIPS5: 16292 case ISA_MIPS64: 16293 case ISA_MIPS64R2: 16294 case ISA_MIPS64R3: 16295 case ISA_MIPS64R5: 16296 case ISA_MIPS64R6: 16297 mips_opts.gp = 64; 16298 if (mips_opts.fp != 0) 16299 { 16300 if (mips_opts.arch == CPU_R5900) 16301 mips_opts.fp = 32; 16302 else 16303 mips_opts.fp = 64; 16304 } 16305 break; 16306 default: 16307 as_bad (_("unknown ISA level %s"), name + 4); 16308 break; 16309 } 16310 } 16311 16312 mips_check_options (&mips_opts, FALSE); 16313 16314 mips_check_isa_supports_ases (); 16315 *input_line_pointer = ch; 16316 demand_empty_rest_of_line (); 16317} 16318 16319/* Handle the .module pseudo-op. */ 16320 16321static void 16322s_module (int ignore ATTRIBUTE_UNUSED) 16323{ 16324 char *name = input_line_pointer, ch; 16325 16326 while (!is_end_of_line[(unsigned char) *input_line_pointer]) 16327 ++input_line_pointer; 16328 ch = *input_line_pointer; 16329 *input_line_pointer = '\0'; 16330 16331 if (!file_mips_opts_checked) 16332 { 16333 if (parse_code_option (name) == OPTION_TYPE_BAD) 16334 as_bad (_(".module used with unrecognized symbol: %s\n"), name); 16335 16336 /* Update module level settings from mips_opts. */ 16337 file_mips_opts = mips_opts; 16338 } 16339 else 16340 as_bad (_(".module is not permitted after generating code")); 16341 16342 *input_line_pointer = ch; 16343 demand_empty_rest_of_line (); 16344} 16345 16346/* Handle the .abicalls pseudo-op. I believe this is equivalent to 16347 .option pic2. It means to generate SVR4 PIC calls. */ 16348 16349static void 16350s_abicalls (int ignore ATTRIBUTE_UNUSED) 16351{ 16352 mips_pic = SVR4_PIC; 16353 mips_abicalls = TRUE; 16354 16355 if (g_switch_seen && g_switch_value != 0) 16356 as_warn (_("-G may not be used with SVR4 PIC code")); 16357 g_switch_value = 0; 16358 16359 bfd_set_gp_size (stdoutput, 0); 16360 demand_empty_rest_of_line (); 16361} 16362 16363/* Handle the .cpload pseudo-op. This is used when generating SVR4 16364 PIC code. It sets the $gp register for the function based on the 16365 function address, which is in the register named in the argument. 16366 This uses a relocation against _gp_disp, which is handled specially 16367 by the linker. The result is: 16368 lui $gp,%hi(_gp_disp) 16369 addiu $gp,$gp,%lo(_gp_disp) 16370 addu $gp,$gp,.cpload argument 16371 The .cpload argument is normally $25 == $t9. 16372 16373 The -mno-shared option changes this to: 16374 lui $gp,%hi(__gnu_local_gp) 16375 addiu $gp,$gp,%lo(__gnu_local_gp) 16376 and the argument is ignored. This saves an instruction, but the 16377 resulting code is not position independent; it uses an absolute 16378 address for __gnu_local_gp. Thus code assembled with -mno-shared 16379 can go into an ordinary executable, but not into a shared library. */ 16380 16381static void 16382s_cpload (int ignore ATTRIBUTE_UNUSED) 16383{ 16384 expressionS ex; 16385 int reg; 16386 int in_shared; 16387 16388 file_mips_check_options (); 16389 16390 /* If we are not generating SVR4 PIC code, or if this is NewABI code, 16391 .cpload is ignored. */ 16392 if (mips_pic != SVR4_PIC || HAVE_NEWABI) 16393 { 16394 s_ignore (0); 16395 return; 16396 } 16397 16398 if (mips_opts.mips16) 16399 { 16400 as_bad (_("%s not supported in MIPS16 mode"), ".cpload"); 16401 ignore_rest_of_line (); 16402 return; 16403 } 16404 16405 /* .cpload should be in a .set noreorder section. */ 16406 if (mips_opts.noreorder == 0) 16407 as_warn (_(".cpload not in noreorder section")); 16408 16409 reg = tc_get_register (0); 16410 16411 /* If we need to produce a 64-bit address, we are better off using 16412 the default instruction sequence. */ 16413 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; 16414 16415 ex.X_op = O_symbol; 16416 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : 16417 "__gnu_local_gp"); 16418 ex.X_op_symbol = NULL; 16419 ex.X_add_number = 0; 16420 16421 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ 16422 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; 16423 16424 mips_mark_labels (); 16425 mips_assembling_insn = TRUE; 16426 16427 macro_start (); 16428 macro_build_lui (&ex, mips_gp_register); 16429 macro_build (&ex, "addiu", "t,r,j", mips_gp_register, 16430 mips_gp_register, BFD_RELOC_LO16); 16431 if (in_shared) 16432 macro_build (NULL, "addu", "d,v,t", mips_gp_register, 16433 mips_gp_register, reg); 16434 macro_end (); 16435 16436 mips_assembling_insn = FALSE; 16437 demand_empty_rest_of_line (); 16438} 16439 16440/* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: 16441 .cpsetup $reg1, offset|$reg2, label 16442 16443 If offset is given, this results in: 16444 sd $gp, offset($sp) 16445 lui $gp, %hi(%neg(%gp_rel(label))) 16446 addiu $gp, $gp, %lo(%neg(%gp_rel(label))) 16447 daddu $gp, $gp, $reg1 16448 16449 If $reg2 is given, this results in: 16450 or $reg2, $gp, $0 16451 lui $gp, %hi(%neg(%gp_rel(label))) 16452 addiu $gp, $gp, %lo(%neg(%gp_rel(label))) 16453 daddu $gp, $gp, $reg1 16454 $reg1 is normally $25 == $t9. 16455 16456 The -mno-shared option replaces the last three instructions with 16457 lui $gp,%hi(_gp) 16458 addiu $gp,$gp,%lo(_gp) */ 16459 16460static void 16461s_cpsetup (int ignore ATTRIBUTE_UNUSED) 16462{ 16463 expressionS ex_off; 16464 expressionS ex_sym; 16465 int reg1; 16466 16467 file_mips_check_options (); 16468 16469 /* If we are not generating SVR4 PIC code, .cpsetup is ignored. 16470 We also need NewABI support. */ 16471 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) 16472 { 16473 s_ignore (0); 16474 return; 16475 } 16476 16477 if (mips_opts.mips16) 16478 { 16479 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup"); 16480 ignore_rest_of_line (); 16481 return; 16482 } 16483 16484 reg1 = tc_get_register (0); 16485 SKIP_WHITESPACE (); 16486 if (*input_line_pointer != ',') 16487 { 16488 as_bad (_("missing argument separator ',' for .cpsetup")); 16489 return; 16490 } 16491 else 16492 ++input_line_pointer; 16493 SKIP_WHITESPACE (); 16494 if (*input_line_pointer == '$') 16495 { 16496 mips_cpreturn_register = tc_get_register (0); 16497 mips_cpreturn_offset = -1; 16498 } 16499 else 16500 { 16501 mips_cpreturn_offset = get_absolute_expression (); 16502 mips_cpreturn_register = -1; 16503 } 16504 SKIP_WHITESPACE (); 16505 if (*input_line_pointer != ',') 16506 { 16507 as_bad (_("missing argument separator ',' for .cpsetup")); 16508 return; 16509 } 16510 else 16511 ++input_line_pointer; 16512 SKIP_WHITESPACE (); 16513 expression (&ex_sym); 16514 16515 mips_mark_labels (); 16516 mips_assembling_insn = TRUE; 16517 16518 macro_start (); 16519 if (mips_cpreturn_register == -1) 16520 { 16521 ex_off.X_op = O_constant; 16522 ex_off.X_add_symbol = NULL; 16523 ex_off.X_op_symbol = NULL; 16524 ex_off.X_add_number = mips_cpreturn_offset; 16525 16526 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, 16527 BFD_RELOC_LO16, SP); 16528 } 16529 else 16530 move_register (mips_cpreturn_register, mips_gp_register); 16531 16532 if (mips_in_shared || HAVE_64BIT_SYMBOLS) 16533 { 16534 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register, 16535 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, 16536 BFD_RELOC_HI16_S); 16537 16538 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, 16539 mips_gp_register, -1, BFD_RELOC_GPREL16, 16540 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); 16541 16542 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, 16543 mips_gp_register, reg1); 16544 } 16545 else 16546 { 16547 expressionS ex; 16548 16549 ex.X_op = O_symbol; 16550 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); 16551 ex.X_op_symbol = NULL; 16552 ex.X_add_number = 0; 16553 16554 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ 16555 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; 16556 16557 macro_build_lui (&ex, mips_gp_register); 16558 macro_build (&ex, "addiu", "t,r,j", mips_gp_register, 16559 mips_gp_register, BFD_RELOC_LO16); 16560 } 16561 16562 macro_end (); 16563 16564 mips_assembling_insn = FALSE; 16565 demand_empty_rest_of_line (); 16566} 16567 16568static void 16569s_cplocal (int ignore ATTRIBUTE_UNUSED) 16570{ 16571 file_mips_check_options (); 16572 16573 /* If we are not generating SVR4 PIC code, or if this is not NewABI code, 16574 .cplocal is ignored. */ 16575 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) 16576 { 16577 s_ignore (0); 16578 return; 16579 } 16580 16581 if (mips_opts.mips16) 16582 { 16583 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal"); 16584 ignore_rest_of_line (); 16585 return; 16586 } 16587 16588 mips_gp_register = tc_get_register (0); 16589 demand_empty_rest_of_line (); 16590} 16591 16592/* Handle the .cprestore pseudo-op. This stores $gp into a given 16593 offset from $sp. The offset is remembered, and after making a PIC 16594 call $gp is restored from that location. */ 16595 16596static void 16597s_cprestore (int ignore ATTRIBUTE_UNUSED) 16598{ 16599 expressionS ex; 16600 16601 file_mips_check_options (); 16602 16603 /* If we are not generating SVR4 PIC code, or if this is NewABI code, 16604 .cprestore is ignored. */ 16605 if (mips_pic != SVR4_PIC || HAVE_NEWABI) 16606 { 16607 s_ignore (0); 16608 return; 16609 } 16610 16611 if (mips_opts.mips16) 16612 { 16613 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore"); 16614 ignore_rest_of_line (); 16615 return; 16616 } 16617 16618 mips_cprestore_offset = get_absolute_expression (); 16619 mips_cprestore_valid = 1; 16620 16621 ex.X_op = O_constant; 16622 ex.X_add_symbol = NULL; 16623 ex.X_op_symbol = NULL; 16624 ex.X_add_number = mips_cprestore_offset; 16625 16626 mips_mark_labels (); 16627 mips_assembling_insn = TRUE; 16628 16629 macro_start (); 16630 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, 16631 SP, HAVE_64BIT_ADDRESSES); 16632 macro_end (); 16633 16634 mips_assembling_insn = FALSE; 16635 demand_empty_rest_of_line (); 16636} 16637 16638/* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset 16639 was given in the preceding .cpsetup, it results in: 16640 ld $gp, offset($sp) 16641 16642 If a register $reg2 was given there, it results in: 16643 or $gp, $reg2, $0 */ 16644 16645static void 16646s_cpreturn (int ignore ATTRIBUTE_UNUSED) 16647{ 16648 expressionS ex; 16649 16650 file_mips_check_options (); 16651 16652 /* If we are not generating SVR4 PIC code, .cpreturn is ignored. 16653 We also need NewABI support. */ 16654 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) 16655 { 16656 s_ignore (0); 16657 return; 16658 } 16659 16660 if (mips_opts.mips16) 16661 { 16662 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn"); 16663 ignore_rest_of_line (); 16664 return; 16665 } 16666 16667 mips_mark_labels (); 16668 mips_assembling_insn = TRUE; 16669 16670 macro_start (); 16671 if (mips_cpreturn_register == -1) 16672 { 16673 ex.X_op = O_constant; 16674 ex.X_add_symbol = NULL; 16675 ex.X_op_symbol = NULL; 16676 ex.X_add_number = mips_cpreturn_offset; 16677 16678 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); 16679 } 16680 else 16681 move_register (mips_gp_register, mips_cpreturn_register); 16682 16683 macro_end (); 16684 16685 mips_assembling_insn = FALSE; 16686 demand_empty_rest_of_line (); 16687} 16688 16689/* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword 16690 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size 16691 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF 16692 debug information or MIPS16 TLS. */ 16693 16694static void 16695s_tls_rel_directive (const size_t bytes, const char *dirstr, 16696 bfd_reloc_code_real_type rtype) 16697{ 16698 expressionS ex; 16699 char *p; 16700 16701 expression (&ex); 16702 16703 if (ex.X_op != O_symbol) 16704 { 16705 as_bad (_("unsupported use of %s"), dirstr); 16706 ignore_rest_of_line (); 16707 } 16708 16709 p = frag_more (bytes); 16710 md_number_to_chars (p, 0, bytes); 16711 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype); 16712 demand_empty_rest_of_line (); 16713 mips_clear_insn_labels (); 16714} 16715 16716/* Handle .dtprelword. */ 16717 16718static void 16719s_dtprelword (int ignore ATTRIBUTE_UNUSED) 16720{ 16721 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32); 16722} 16723 16724/* Handle .dtpreldword. */ 16725 16726static void 16727s_dtpreldword (int ignore ATTRIBUTE_UNUSED) 16728{ 16729 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64); 16730} 16731 16732/* Handle .tprelword. */ 16733 16734static void 16735s_tprelword (int ignore ATTRIBUTE_UNUSED) 16736{ 16737 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32); 16738} 16739 16740/* Handle .tpreldword. */ 16741 16742static void 16743s_tpreldword (int ignore ATTRIBUTE_UNUSED) 16744{ 16745 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64); 16746} 16747 16748/* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC 16749 code. It sets the offset to use in gp_rel relocations. */ 16750 16751static void 16752s_gpvalue (int ignore ATTRIBUTE_UNUSED) 16753{ 16754 /* If we are not generating SVR4 PIC code, .gpvalue is ignored. 16755 We also need NewABI support. */ 16756 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) 16757 { 16758 s_ignore (0); 16759 return; 16760 } 16761 16762 mips_gprel_offset = get_absolute_expression (); 16763 16764 demand_empty_rest_of_line (); 16765} 16766 16767/* Handle the .gpword pseudo-op. This is used when generating PIC 16768 code. It generates a 32 bit GP relative reloc. */ 16769 16770static void 16771s_gpword (int ignore ATTRIBUTE_UNUSED) 16772{ 16773 segment_info_type *si; 16774 struct insn_label_list *l; 16775 expressionS ex; 16776 char *p; 16777 16778 /* When not generating PIC code, this is treated as .word. */ 16779 if (mips_pic != SVR4_PIC) 16780 { 16781 s_cons (2); 16782 return; 16783 } 16784 16785 si = seg_info (now_seg); 16786 l = si->label_list; 16787 mips_emit_delays (); 16788 if (auto_align) 16789 mips_align (2, 0, l); 16790 16791 expression (&ex); 16792 mips_clear_insn_labels (); 16793 16794 if (ex.X_op != O_symbol || ex.X_add_number != 0) 16795 { 16796 as_bad (_("unsupported use of .gpword")); 16797 ignore_rest_of_line (); 16798 } 16799 16800 p = frag_more (4); 16801 md_number_to_chars (p, 0, 4); 16802 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, 16803 BFD_RELOC_GPREL32); 16804 16805 demand_empty_rest_of_line (); 16806} 16807 16808static void 16809s_gpdword (int ignore ATTRIBUTE_UNUSED) 16810{ 16811 segment_info_type *si; 16812 struct insn_label_list *l; 16813 expressionS ex; 16814 char *p; 16815 16816 /* When not generating PIC code, this is treated as .dword. */ 16817 if (mips_pic != SVR4_PIC) 16818 { 16819 s_cons (3); 16820 return; 16821 } 16822 16823 si = seg_info (now_seg); 16824 l = si->label_list; 16825 mips_emit_delays (); 16826 if (auto_align) 16827 mips_align (3, 0, l); 16828 16829 expression (&ex); 16830 mips_clear_insn_labels (); 16831 16832 if (ex.X_op != O_symbol || ex.X_add_number != 0) 16833 { 16834 as_bad (_("unsupported use of .gpdword")); 16835 ignore_rest_of_line (); 16836 } 16837 16838 p = frag_more (8); 16839 md_number_to_chars (p, 0, 8); 16840 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, 16841 BFD_RELOC_GPREL32)->fx_tcbit = 1; 16842 16843 /* GPREL32 composed with 64 gives a 64-bit GP offset. */ 16844 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, 16845 FALSE, BFD_RELOC_64)->fx_tcbit = 1; 16846 16847 demand_empty_rest_of_line (); 16848} 16849 16850/* Handle the .ehword pseudo-op. This is used when generating unwinding 16851 tables. It generates a R_MIPS_EH reloc. */ 16852 16853static void 16854s_ehword (int ignore ATTRIBUTE_UNUSED) 16855{ 16856 expressionS ex; 16857 char *p; 16858 16859 mips_emit_delays (); 16860 16861 expression (&ex); 16862 mips_clear_insn_labels (); 16863 16864 if (ex.X_op != O_symbol || ex.X_add_number != 0) 16865 { 16866 as_bad (_("unsupported use of .ehword")); 16867 ignore_rest_of_line (); 16868 } 16869 16870 p = frag_more (4); 16871 md_number_to_chars (p, 0, 4); 16872 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, 16873 BFD_RELOC_32_PCREL); 16874 16875 demand_empty_rest_of_line (); 16876} 16877 16878/* Handle the .cpadd pseudo-op. This is used when dealing with switch 16879 tables in SVR4 PIC code. */ 16880 16881static void 16882s_cpadd (int ignore ATTRIBUTE_UNUSED) 16883{ 16884 int reg; 16885 16886 file_mips_check_options (); 16887 16888 /* This is ignored when not generating SVR4 PIC code. */ 16889 if (mips_pic != SVR4_PIC) 16890 { 16891 s_ignore (0); 16892 return; 16893 } 16894 16895 mips_mark_labels (); 16896 mips_assembling_insn = TRUE; 16897 16898 /* Add $gp to the register named as an argument. */ 16899 macro_start (); 16900 reg = tc_get_register (0); 16901 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); 16902 macro_end (); 16903 16904 mips_assembling_insn = FALSE; 16905 demand_empty_rest_of_line (); 16906} 16907 16908/* Handle the .insn pseudo-op. This marks instruction labels in 16909 mips16/micromips mode. This permits the linker to handle them specially, 16910 such as generating jalx instructions when needed. We also make 16911 them odd for the duration of the assembly, in order to generate the 16912 right sort of code. We will make them even in the adjust_symtab 16913 routine, while leaving them marked. This is convenient for the 16914 debugger and the disassembler. The linker knows to make them odd 16915 again. */ 16916 16917static void 16918s_insn (int ignore ATTRIBUTE_UNUSED) 16919{ 16920 file_mips_check_options (); 16921 file_ase_mips16 |= mips_opts.mips16; 16922 file_ase_micromips |= mips_opts.micromips; 16923 16924 mips_mark_labels (); 16925 16926 demand_empty_rest_of_line (); 16927} 16928 16929/* Handle the .nan pseudo-op. */ 16930 16931static void 16932s_nan (int ignore ATTRIBUTE_UNUSED) 16933{ 16934 static const char str_legacy[] = "legacy"; 16935 static const char str_2008[] = "2008"; 16936 size_t i; 16937 16938 for (i = 0; !is_end_of_line[(unsigned char) input_line_pointer[i]]; i++); 16939 16940 if (i == sizeof (str_2008) - 1 16941 && memcmp (input_line_pointer, str_2008, i) == 0) 16942 mips_nan2008 = 1; 16943 else if (i == sizeof (str_legacy) - 1 16944 && memcmp (input_line_pointer, str_legacy, i) == 0) 16945 { 16946 if (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) 16947 mips_nan2008 = 0; 16948 else 16949 as_bad (_("`%s' does not support legacy NaN"), 16950 mips_cpu_info_from_isa (file_mips_opts.isa)->name); 16951 } 16952 else 16953 as_bad (_("bad .nan directive")); 16954 16955 input_line_pointer += i; 16956 demand_empty_rest_of_line (); 16957} 16958 16959/* Handle a .stab[snd] directive. Ideally these directives would be 16960 implemented in a transparent way, so that removing them would not 16961 have any effect on the generated instructions. However, s_stab 16962 internally changes the section, so in practice we need to decide 16963 now whether the preceding label marks compressed code. We do not 16964 support changing the compression mode of a label after a .stab* 16965 directive, such as in: 16966 16967 foo: 16968 .stabs ... 16969 .set mips16 16970 16971 so the current mode wins. */ 16972 16973static void 16974s_mips_stab (int type) 16975{ 16976 mips_mark_labels (); 16977 s_stab (type); 16978} 16979 16980/* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ 16981 16982static void 16983s_mips_weakext (int ignore ATTRIBUTE_UNUSED) 16984{ 16985 char *name; 16986 int c; 16987 symbolS *symbolP; 16988 expressionS exp; 16989 16990 c = get_symbol_name (&name); 16991 symbolP = symbol_find_or_make (name); 16992 S_SET_WEAK (symbolP); 16993 *input_line_pointer = c; 16994 16995 SKIP_WHITESPACE_AFTER_NAME (); 16996 16997 if (! is_end_of_line[(unsigned char) *input_line_pointer]) 16998 { 16999 if (S_IS_DEFINED (symbolP)) 17000 { 17001 as_bad (_("ignoring attempt to redefine symbol %s"), 17002 S_GET_NAME (symbolP)); 17003 ignore_rest_of_line (); 17004 return; 17005 } 17006 17007 if (*input_line_pointer == ',') 17008 { 17009 ++input_line_pointer; 17010 SKIP_WHITESPACE (); 17011 } 17012 17013 expression (&exp); 17014 if (exp.X_op != O_symbol) 17015 { 17016 as_bad (_("bad .weakext directive")); 17017 ignore_rest_of_line (); 17018 return; 17019 } 17020 symbol_set_value_expression (symbolP, &exp); 17021 } 17022 17023 demand_empty_rest_of_line (); 17024} 17025 17026/* Parse a register string into a number. Called from the ECOFF code 17027 to parse .frame. The argument is non-zero if this is the frame 17028 register, so that we can record it in mips_frame_reg. */ 17029 17030int 17031tc_get_register (int frame) 17032{ 17033 unsigned int reg; 17034 17035 SKIP_WHITESPACE (); 17036 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) 17037 reg = 0; 17038 if (frame) 17039 { 17040 mips_frame_reg = reg != 0 ? reg : SP; 17041 mips_frame_reg_valid = 1; 17042 mips_cprestore_valid = 0; 17043 } 17044 return reg; 17045} 17046 17047valueT 17048md_section_align (asection *seg, valueT addr) 17049{ 17050 int align = bfd_get_section_alignment (stdoutput, seg); 17051 17052 /* We don't need to align ELF sections to the full alignment. 17053 However, Irix 5 may prefer that we align them at least to a 16 17054 byte boundary. We don't bother to align the sections if we 17055 are targeted for an embedded system. */ 17056 if (strncmp (TARGET_OS, "elf", 3) == 0) 17057 return addr; 17058 if (align > 4) 17059 align = 4; 17060 17061 return ((addr + (1 << align) - 1) & -(1 << align)); 17062} 17063 17064/* Utility routine, called from above as well. If called while the 17065 input file is still being read, it's only an approximation. (For 17066 example, a symbol may later become defined which appeared to be 17067 undefined earlier.) */ 17068 17069static int 17070nopic_need_relax (symbolS *sym, int before_relaxing) 17071{ 17072 if (sym == 0) 17073 return 0; 17074 17075 if (g_switch_value > 0) 17076 { 17077 const char *symname; 17078 int change; 17079 17080 /* Find out whether this symbol can be referenced off the $gp 17081 register. It can be if it is smaller than the -G size or if 17082 it is in the .sdata or .sbss section. Certain symbols can 17083 not be referenced off the $gp, although it appears as though 17084 they can. */ 17085 symname = S_GET_NAME (sym); 17086 if (symname != (const char *) NULL 17087 && (strcmp (symname, "eprol") == 0 17088 || strcmp (symname, "etext") == 0 17089 || strcmp (symname, "_gp") == 0 17090 || strcmp (symname, "edata") == 0 17091 || strcmp (symname, "_fbss") == 0 17092 || strcmp (symname, "_fdata") == 0 17093 || strcmp (symname, "_ftext") == 0 17094 || strcmp (symname, "end") == 0 17095 || strcmp (symname, "_gp_disp") == 0)) 17096 change = 1; 17097 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) 17098 && (0 17099#ifndef NO_ECOFF_DEBUGGING 17100 || (symbol_get_obj (sym)->ecoff_extern_size != 0 17101 && (symbol_get_obj (sym)->ecoff_extern_size 17102 <= g_switch_value)) 17103#endif 17104 /* We must defer this decision until after the whole 17105 file has been read, since there might be a .extern 17106 after the first use of this symbol. */ 17107 || (before_relaxing 17108#ifndef NO_ECOFF_DEBUGGING 17109 && symbol_get_obj (sym)->ecoff_extern_size == 0 17110#endif 17111 && S_GET_VALUE (sym) == 0) 17112 || (S_GET_VALUE (sym) != 0 17113 && S_GET_VALUE (sym) <= g_switch_value))) 17114 change = 0; 17115 else 17116 { 17117 const char *segname; 17118 17119 segname = segment_name (S_GET_SEGMENT (sym)); 17120 gas_assert (strcmp (segname, ".lit8") != 0 17121 && strcmp (segname, ".lit4") != 0); 17122 change = (strcmp (segname, ".sdata") != 0 17123 && strcmp (segname, ".sbss") != 0 17124 && strncmp (segname, ".sdata.", 7) != 0 17125 && strncmp (segname, ".sbss.", 6) != 0 17126 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 17127 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); 17128 } 17129 return change; 17130 } 17131 else 17132 /* We are not optimizing for the $gp register. */ 17133 return 1; 17134} 17135 17136 17137/* Return true if the given symbol should be considered local for SVR4 PIC. */ 17138 17139static bfd_boolean 17140pic_need_relax (symbolS *sym) 17141{ 17142 asection *symsec; 17143 17144 /* Handle the case of a symbol equated to another symbol. */ 17145 while (symbol_equated_reloc_p (sym)) 17146 { 17147 symbolS *n; 17148 17149 /* It's possible to get a loop here in a badly written program. */ 17150 n = symbol_get_value_expression (sym)->X_add_symbol; 17151 if (n == sym) 17152 break; 17153 sym = n; 17154 } 17155 17156 if (symbol_section_p (sym)) 17157 return TRUE; 17158 17159 symsec = S_GET_SEGMENT (sym); 17160 17161 /* This must duplicate the test in adjust_reloc_syms. */ 17162 return (!bfd_is_und_section (symsec) 17163 && !bfd_is_abs_section (symsec) 17164 && !bfd_is_com_section (symsec) 17165 /* A global or weak symbol is treated as external. */ 17166 && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym))); 17167} 17168 17169 17170/* Given a mips16 variant frag FRAGP, return non-zero if it needs an 17171 extended opcode. SEC is the section the frag is in. */ 17172 17173static int 17174mips16_extended_frag (fragS *fragp, asection *sec, long stretch) 17175{ 17176 int type; 17177 const struct mips_int_operand *operand; 17178 offsetT val; 17179 segT symsec; 17180 fragS *sym_frag; 17181 17182 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) 17183 return 0; 17184 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) 17185 return 1; 17186 17187 symsec = S_GET_SEGMENT (fragp->fr_symbol); 17188 type = RELAX_MIPS16_TYPE (fragp->fr_subtype); 17189 operand = mips16_immed_operand (type, FALSE); 17190 if (S_FORCE_RELOC (fragp->fr_symbol, TRUE) 17191 || (operand->root.type == OP_PCREL 17192 ? sec != symsec 17193 : !bfd_is_abs_section (symsec))) 17194 return 1; 17195 17196 sym_frag = symbol_get_frag (fragp->fr_symbol); 17197 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; 17198 17199 if (operand->root.type == OP_PCREL) 17200 { 17201 const struct mips_pcrel_operand *pcrel_op; 17202 addressT addr; 17203 offsetT maxtiny; 17204 17205 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) 17206 return 1; 17207 17208 pcrel_op = (const struct mips_pcrel_operand *) operand; 17209 17210 /* If the relax_marker of the symbol fragment differs from the 17211 relax_marker of this fragment, we have not yet adjusted the 17212 symbol fragment fr_address. We want to add in STRETCH in 17213 order to get a better estimate of the address. This 17214 particularly matters because of the shift bits. */ 17215 if (stretch != 0 17216 && sym_frag->relax_marker != fragp->relax_marker) 17217 { 17218 fragS *f; 17219 17220 /* Adjust stretch for any alignment frag. Note that if have 17221 been expanding the earlier code, the symbol may be 17222 defined in what appears to be an earlier frag. FIXME: 17223 This doesn't handle the fr_subtype field, which specifies 17224 a maximum number of bytes to skip when doing an 17225 alignment. */ 17226 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) 17227 { 17228 if (f->fr_type == rs_align || f->fr_type == rs_align_code) 17229 { 17230 if (stretch < 0) 17231 stretch = - ((- stretch) 17232 & ~ ((1 << (int) f->fr_offset) - 1)); 17233 else 17234 stretch &= ~ ((1 << (int) f->fr_offset) - 1); 17235 if (stretch == 0) 17236 break; 17237 } 17238 } 17239 if (f != NULL) 17240 val += stretch; 17241 } 17242 17243 addr = fragp->fr_address + fragp->fr_fix; 17244 17245 /* The base address rules are complicated. The base address of 17246 a branch is the following instruction. The base address of a 17247 PC relative load or add is the instruction itself, but if it 17248 is in a delay slot (in which case it can not be extended) use 17249 the address of the instruction whose delay slot it is in. */ 17250 if (pcrel_op->include_isa_bit) 17251 { 17252 addr += 2; 17253 17254 /* If we are currently assuming that this frag should be 17255 extended, then, the current address is two bytes 17256 higher. */ 17257 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) 17258 addr += 2; 17259 17260 /* Ignore the low bit in the target, since it will be set 17261 for a text label. */ 17262 val &= -2; 17263 } 17264 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) 17265 addr -= 4; 17266 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) 17267 addr -= 2; 17268 17269 val -= addr & -(1 << pcrel_op->align_log2); 17270 17271 /* If any of the shifted bits are set, we must use an extended 17272 opcode. If the address depends on the size of this 17273 instruction, this can lead to a loop, so we arrange to always 17274 use an extended opcode. */ 17275 if ((val & ((1 << operand->shift) - 1)) != 0) 17276 { 17277 fragp->fr_subtype = 17278 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); 17279 return 1; 17280 } 17281 17282 /* If we are about to mark a frag as extended because the value 17283 is precisely the next value above maxtiny, then there is a 17284 chance of an infinite loop as in the following code: 17285 la $4,foo 17286 .skip 1020 17287 .align 2 17288 foo: 17289 In this case when the la is extended, foo is 0x3fc bytes 17290 away, so the la can be shrunk, but then foo is 0x400 away, so 17291 the la must be extended. To avoid this loop, we mark the 17292 frag as extended if it was small, and is about to become 17293 extended with the next value above maxtiny. */ 17294 maxtiny = mips_int_operand_max (operand); 17295 if (val == maxtiny + (1 << operand->shift) 17296 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) 17297 { 17298 fragp->fr_subtype = 17299 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); 17300 return 1; 17301 } 17302 } 17303 17304 return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val); 17305} 17306 17307/* Compute the length of a branch sequence, and adjust the 17308 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the 17309 worst-case length is computed, with UPDATE being used to indicate 17310 whether an unconditional (-1), branch-likely (+1) or regular (0) 17311 branch is to be computed. */ 17312static int 17313relaxed_branch_length (fragS *fragp, asection *sec, int update) 17314{ 17315 bfd_boolean toofar; 17316 int length; 17317 17318 if (fragp 17319 && S_IS_DEFINED (fragp->fr_symbol) 17320 && !S_IS_WEAK (fragp->fr_symbol) 17321 && sec == S_GET_SEGMENT (fragp->fr_symbol)) 17322 { 17323 addressT addr; 17324 offsetT val; 17325 17326 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; 17327 17328 addr = fragp->fr_address + fragp->fr_fix + 4; 17329 17330 val -= addr; 17331 17332 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); 17333 } 17334 else 17335 /* If the symbol is not defined or it's in a different segment, 17336 we emit the long sequence. */ 17337 toofar = TRUE; 17338 17339 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) 17340 fragp->fr_subtype 17341 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype), 17342 RELAX_BRANCH_UNCOND (fragp->fr_subtype), 17343 RELAX_BRANCH_LIKELY (fragp->fr_subtype), 17344 RELAX_BRANCH_LINK (fragp->fr_subtype), 17345 toofar); 17346 17347 length = 4; 17348 if (toofar) 17349 { 17350 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) 17351 length += 8; 17352 17353 if (mips_pic != NO_PIC) 17354 { 17355 /* Additional space for PIC loading of target address. */ 17356 length += 8; 17357 if (mips_opts.isa == ISA_MIPS1) 17358 /* Additional space for $at-stabilizing nop. */ 17359 length += 4; 17360 } 17361 17362 /* If branch is conditional. */ 17363 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) 17364 length += 8; 17365 } 17366 17367 return length; 17368} 17369 17370/* Get a FRAG's branch instruction delay slot size, either from the 17371 short-delay-slot bit of a branch-and-link instruction if AL is TRUE, 17372 or SHORT_INSN_SIZE otherwise. */ 17373 17374static int 17375frag_branch_delay_slot_size (fragS *fragp, bfd_boolean al, int short_insn_size) 17376{ 17377 char *buf = fragp->fr_literal + fragp->fr_fix; 17378 17379 if (al) 17380 return (read_compressed_insn (buf, 4) & 0x02000000) ? 2 : 4; 17381 else 17382 return short_insn_size; 17383} 17384 17385/* Compute the length of a branch sequence, and adjust the 17386 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the 17387 worst-case length is computed, with UPDATE being used to indicate 17388 whether an unconditional (-1), or regular (0) branch is to be 17389 computed. */ 17390 17391static int 17392relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update) 17393{ 17394 bfd_boolean insn32 = TRUE; 17395 bfd_boolean nods = TRUE; 17396 bfd_boolean al = TRUE; 17397 int short_insn_size; 17398 bfd_boolean toofar; 17399 int length; 17400 17401 if (fragp) 17402 { 17403 insn32 = RELAX_MICROMIPS_INSN32 (fragp->fr_subtype); 17404 nods = RELAX_MICROMIPS_NODS (fragp->fr_subtype); 17405 al = RELAX_MICROMIPS_LINK (fragp->fr_subtype); 17406 } 17407 short_insn_size = insn32 ? 4 : 2; 17408 17409 if (fragp 17410 && S_IS_DEFINED (fragp->fr_symbol) 17411 && !S_IS_WEAK (fragp->fr_symbol) 17412 && sec == S_GET_SEGMENT (fragp->fr_symbol)) 17413 { 17414 addressT addr; 17415 offsetT val; 17416 17417 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; 17418 /* Ignore the low bit in the target, since it will be set 17419 for a text label. */ 17420 if ((val & 1) != 0) 17421 --val; 17422 17423 addr = fragp->fr_address + fragp->fr_fix + 4; 17424 17425 val -= addr; 17426 17427 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1); 17428 } 17429 else 17430 /* If the symbol is not defined or it's in a different segment, 17431 we emit the long sequence. */ 17432 toofar = TRUE; 17433 17434 if (fragp && update 17435 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) 17436 fragp->fr_subtype = (toofar 17437 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype) 17438 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype)); 17439 17440 length = 4; 17441 if (toofar) 17442 { 17443 bfd_boolean compact_known = fragp != NULL; 17444 bfd_boolean compact = FALSE; 17445 bfd_boolean uncond; 17446 17447 if (fragp) 17448 { 17449 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); 17450 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype); 17451 } 17452 else 17453 uncond = update < 0; 17454 17455 /* If label is out of range, we turn branch <br>: 17456 17457 <br> label # 4 bytes 17458 0: 17459 17460 into: 17461 17462 j label # 4 bytes 17463 nop # 2/4 bytes if 17464 # compact && (!PIC || insn32) 17465 0: 17466 */ 17467 if ((mips_pic == NO_PIC || insn32) && (!compact_known || compact)) 17468 length += short_insn_size; 17469 17470 /* If assembling PIC code, we further turn: 17471 17472 j label # 4 bytes 17473 17474 into: 17475 17476 lw/ld at, %got(label)(gp) # 4 bytes 17477 d/addiu at, %lo(label) # 4 bytes 17478 jr/c at # 2/4 bytes 17479 */ 17480 if (mips_pic != NO_PIC) 17481 length += 4 + short_insn_size; 17482 17483 /* Add an extra nop if the jump has no compact form and we need 17484 to fill the delay slot. */ 17485 if ((mips_pic == NO_PIC || al) && nods) 17486 length += (fragp 17487 ? frag_branch_delay_slot_size (fragp, al, short_insn_size) 17488 : short_insn_size); 17489 17490 /* If branch <br> is conditional, we prepend negated branch <brneg>: 17491 17492 <brneg> 0f # 4 bytes 17493 nop # 2/4 bytes if !compact 17494 */ 17495 if (!uncond) 17496 length += (compact_known && compact) ? 4 : 4 + short_insn_size; 17497 } 17498 else if (nods) 17499 { 17500 /* Add an extra nop to fill the delay slot. */ 17501 gas_assert (fragp); 17502 length += frag_branch_delay_slot_size (fragp, al, short_insn_size); 17503 } 17504 17505 return length; 17506} 17507 17508/* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16 17509 bit accordingly. */ 17510 17511static int 17512relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update) 17513{ 17514 bfd_boolean toofar; 17515 17516 if (fragp 17517 && S_IS_DEFINED (fragp->fr_symbol) 17518 && !S_IS_WEAK (fragp->fr_symbol) 17519 && sec == S_GET_SEGMENT (fragp->fr_symbol)) 17520 { 17521 addressT addr; 17522 offsetT val; 17523 int type; 17524 17525 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; 17526 /* Ignore the low bit in the target, since it will be set 17527 for a text label. */ 17528 if ((val & 1) != 0) 17529 --val; 17530 17531 /* Assume this is a 2-byte branch. */ 17532 addr = fragp->fr_address + fragp->fr_fix + 2; 17533 17534 /* We try to avoid the infinite loop by not adding 2 more bytes for 17535 long branches. */ 17536 17537 val -= addr; 17538 17539 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); 17540 if (type == 'D') 17541 toofar = val < - (0x200 << 1) || val >= (0x200 << 1); 17542 else if (type == 'E') 17543 toofar = val < - (0x40 << 1) || val >= (0x40 << 1); 17544 else 17545 abort (); 17546 } 17547 else 17548 /* If the symbol is not defined or it's in a different segment, 17549 we emit a normal 32-bit branch. */ 17550 toofar = TRUE; 17551 17552 if (fragp && update 17553 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) 17554 fragp->fr_subtype 17555 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype) 17556 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype); 17557 17558 if (toofar) 17559 return 4; 17560 17561 return 2; 17562} 17563 17564/* Estimate the size of a frag before relaxing. Unless this is the 17565 mips16, we are not really relaxing here, and the final size is 17566 encoded in the subtype information. For the mips16, we have to 17567 decide whether we are using an extended opcode or not. */ 17568 17569int 17570md_estimate_size_before_relax (fragS *fragp, asection *segtype) 17571{ 17572 int change; 17573 17574 if (RELAX_BRANCH_P (fragp->fr_subtype)) 17575 { 17576 17577 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); 17578 17579 return fragp->fr_var; 17580 } 17581 17582 if (RELAX_MIPS16_P (fragp->fr_subtype)) 17583 /* We don't want to modify the EXTENDED bit here; it might get us 17584 into infinite loops. We change it only in mips_relax_frag(). */ 17585 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); 17586 17587 if (RELAX_MICROMIPS_P (fragp->fr_subtype)) 17588 { 17589 int length = 4; 17590 17591 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) 17592 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE); 17593 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) 17594 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE); 17595 fragp->fr_var = length; 17596 17597 return length; 17598 } 17599 17600 if (mips_pic == NO_PIC) 17601 change = nopic_need_relax (fragp->fr_symbol, 0); 17602 else if (mips_pic == SVR4_PIC) 17603 change = pic_need_relax (fragp->fr_symbol); 17604 else if (mips_pic == VXWORKS_PIC) 17605 /* For vxworks, GOT16 relocations never have a corresponding LO16. */ 17606 change = 0; 17607 else 17608 abort (); 17609 17610 if (change) 17611 { 17612 fragp->fr_subtype |= RELAX_USE_SECOND; 17613 return -RELAX_FIRST (fragp->fr_subtype); 17614 } 17615 else 17616 return -RELAX_SECOND (fragp->fr_subtype); 17617} 17618 17619/* This is called to see whether a reloc against a defined symbol 17620 should be converted into a reloc against a section. */ 17621 17622int 17623mips_fix_adjustable (fixS *fixp) 17624{ 17625 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT 17626 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 17627 return 0; 17628 17629 if (fixp->fx_addsy == NULL) 17630 return 1; 17631 17632 /* Allow relocs used for EH tables. */ 17633 if (fixp->fx_r_type == BFD_RELOC_32_PCREL) 17634 return 1; 17635 17636 /* If symbol SYM is in a mergeable section, relocations of the form 17637 SYM + 0 can usually be made section-relative. The mergeable data 17638 is then identified by the section offset rather than by the symbol. 17639 17640 However, if we're generating REL LO16 relocations, the offset is split 17641 between the LO16 and parterning high part relocation. The linker will 17642 need to recalculate the complete offset in order to correctly identify 17643 the merge data. 17644 17645 The linker has traditionally not looked for the parterning high part 17646 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be 17647 placed anywhere. Rather than break backwards compatibility by changing 17648 this, it seems better not to force the issue, and instead keep the 17649 original symbol. This will work with either linker behavior. */ 17650 if ((lo16_reloc_p (fixp->fx_r_type) 17651 || reloc_needs_lo_p (fixp->fx_r_type)) 17652 && HAVE_IN_PLACE_ADDENDS 17653 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) 17654 return 0; 17655 17656 /* There is no place to store an in-place offset for JALR relocations. */ 17657 if (jalr_reloc_p (fixp->fx_r_type) && HAVE_IN_PLACE_ADDENDS) 17658 return 0; 17659 17660 /* Likewise an in-range offset of limited PC-relative relocations may 17661 overflow the in-place relocatable field if recalculated against the 17662 start address of the symbol's containing section. 17663 17664 Also, PC relative relocations for MIPS R6 need to be symbol rather than 17665 section relative to allow linker relaxations to be performed later on. */ 17666 if (limited_pcrel_reloc_p (fixp->fx_r_type) 17667 && (HAVE_IN_PLACE_ADDENDS || ISA_IS_R6 (file_mips_opts.isa))) 17668 return 0; 17669 17670 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve 17671 to a floating-point stub. The same is true for non-R_MIPS16_26 17672 relocations against MIPS16 functions; in this case, the stub becomes 17673 the function's canonical address. 17674 17675 Floating-point stubs are stored in unique .mips16.call.* or 17676 .mips16.fn.* sections. If a stub T for function F is in section S, 17677 the first relocation in section S must be against F; this is how the 17678 linker determines the target function. All relocations that might 17679 resolve to T must also be against F. We therefore have the following 17680 restrictions, which are given in an intentionally-redundant way: 17681 17682 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16 17683 symbols. 17684 17685 2. We cannot reduce a stub's relocations against non-MIPS16 symbols 17686 if that stub might be used. 17687 17688 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16 17689 symbols. 17690 17691 4. We cannot reduce a stub's relocations against MIPS16 symbols if 17692 that stub might be used. 17693 17694 There is a further restriction: 17695 17696 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or 17697 R_MICROMIPS_26_S1) or branch relocations (R_MIPS_PC26_S2, 17698 R_MIPS_PC21_S2, R_MIPS_PC16, R_MIPS16_PC16_S1, 17699 R_MICROMIPS_PC16_S1, R_MICROMIPS_PC10_S1 or R_MICROMIPS_PC7_S1) 17700 against MIPS16 or microMIPS symbols because we need to keep the 17701 MIPS16 or microMIPS symbol for the purpose of mode mismatch 17702 detection and JAL or BAL to JALX instruction conversion in the 17703 linker. 17704 17705 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation 17706 against a MIPS16 symbol. We deal with (5) by additionally leaving 17707 alone any jump and branch relocations against a microMIPS symbol. 17708 17709 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26 17710 relocation against some symbol R, no relocation against R may be 17711 reduced. (Note that this deals with (2) as well as (1) because 17712 relocations against global symbols will never be reduced on ELF 17713 targets.) This approach is a little simpler than trying to detect 17714 stub sections, and gives the "all or nothing" per-symbol consistency 17715 that we have for MIPS16 symbols. */ 17716 if (fixp->fx_subsy == NULL 17717 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy)) 17718 || (ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy)) 17719 && (jmp_reloc_p (fixp->fx_r_type) 17720 || b_reloc_p (fixp->fx_r_type))) 17721 || *symbol_get_tc (fixp->fx_addsy))) 17722 return 0; 17723 17724 return 1; 17725} 17726 17727/* Translate internal representation of relocation info to BFD target 17728 format. */ 17729 17730arelent ** 17731tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) 17732{ 17733 static arelent *retval[4]; 17734 arelent *reloc; 17735 bfd_reloc_code_real_type code; 17736 17737 memset (retval, 0, sizeof(retval)); 17738 reloc = retval[0] = XCNEW (arelent); 17739 reloc->sym_ptr_ptr = XNEW (asymbol *); 17740 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 17741 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 17742 17743 if (fixp->fx_pcrel) 17744 { 17745 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 17746 || fixp->fx_r_type == BFD_RELOC_MIPS16_16_PCREL_S1 17747 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 17748 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 17749 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1 17750 || fixp->fx_r_type == BFD_RELOC_32_PCREL 17751 || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2 17752 || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2 17753 || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3 17754 || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2 17755 || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL 17756 || fixp->fx_r_type == BFD_RELOC_LO16_PCREL); 17757 17758 /* At this point, fx_addnumber is "symbol offset - pcrel address". 17759 Relocations want only the symbol offset. */ 17760 switch (fixp->fx_r_type) 17761 { 17762 case BFD_RELOC_MIPS_18_PCREL_S3: 17763 reloc->addend = fixp->fx_addnumber + (reloc->address & ~7); 17764 break; 17765 default: 17766 reloc->addend = fixp->fx_addnumber + reloc->address; 17767 break; 17768 } 17769 } 17770 else if (HAVE_IN_PLACE_ADDENDS 17771 && fixp->fx_r_type == BFD_RELOC_MICROMIPS_JMP 17772 && (read_compressed_insn (fixp->fx_frag->fr_literal 17773 + fixp->fx_where, 4) >> 26) == 0x3c) 17774 { 17775 /* Shift is 2, unusually, for microMIPS JALX. Adjust the in-place 17776 addend accordingly. */ 17777 reloc->addend = fixp->fx_addnumber >> 1; 17778 } 17779 else 17780 reloc->addend = fixp->fx_addnumber; 17781 17782 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable 17783 entry to be used in the relocation's section offset. */ 17784 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 17785 { 17786 reloc->address = reloc->addend; 17787 reloc->addend = 0; 17788 } 17789 17790 code = fixp->fx_r_type; 17791 17792 reloc->howto = bfd_reloc_type_lookup (stdoutput, code); 17793 if (reloc->howto == NULL) 17794 { 17795 as_bad_where (fixp->fx_file, fixp->fx_line, 17796 _("cannot represent %s relocation in this object file" 17797 " format"), 17798 bfd_get_reloc_code_name (code)); 17799 retval[0] = NULL; 17800 } 17801 17802 return retval; 17803} 17804 17805/* Relax a machine dependent frag. This returns the amount by which 17806 the current size of the frag should change. */ 17807 17808int 17809mips_relax_frag (asection *sec, fragS *fragp, long stretch) 17810{ 17811 if (RELAX_BRANCH_P (fragp->fr_subtype)) 17812 { 17813 offsetT old_var = fragp->fr_var; 17814 17815 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); 17816 17817 return fragp->fr_var - old_var; 17818 } 17819 17820 if (RELAX_MICROMIPS_P (fragp->fr_subtype)) 17821 { 17822 offsetT old_var = fragp->fr_var; 17823 offsetT new_var = 4; 17824 17825 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) 17826 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE); 17827 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) 17828 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE); 17829 fragp->fr_var = new_var; 17830 17831 return new_var - old_var; 17832 } 17833 17834 if (! RELAX_MIPS16_P (fragp->fr_subtype)) 17835 return 0; 17836 17837 if (mips16_extended_frag (fragp, sec, stretch)) 17838 { 17839 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) 17840 return 0; 17841 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); 17842 return 2; 17843 } 17844 else 17845 { 17846 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) 17847 return 0; 17848 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); 17849 return -2; 17850 } 17851 17852 return 0; 17853} 17854 17855/* Convert a machine dependent frag. */ 17856 17857void 17858md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) 17859{ 17860 if (RELAX_BRANCH_P (fragp->fr_subtype)) 17861 { 17862 char *buf; 17863 unsigned long insn; 17864 expressionS exp; 17865 fixS *fixp; 17866 17867 buf = fragp->fr_literal + fragp->fr_fix; 17868 insn = read_insn (buf); 17869 17870 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) 17871 { 17872 /* We generate a fixup instead of applying it right now 17873 because, if there are linker relaxations, we're going to 17874 need the relocations. */ 17875 exp.X_op = O_symbol; 17876 exp.X_add_symbol = fragp->fr_symbol; 17877 exp.X_add_number = fragp->fr_offset; 17878 17879 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE, 17880 BFD_RELOC_16_PCREL_S2); 17881 fixp->fx_file = fragp->fr_file; 17882 fixp->fx_line = fragp->fr_line; 17883 17884 buf = write_insn (buf, insn); 17885 } 17886 else 17887 { 17888 int i; 17889 17890 as_warn_where (fragp->fr_file, fragp->fr_line, 17891 _("relaxed out-of-range branch into a jump")); 17892 17893 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) 17894 goto uncond; 17895 17896 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) 17897 { 17898 /* Reverse the branch. */ 17899 switch ((insn >> 28) & 0xf) 17900 { 17901 case 4: 17902 if ((insn & 0xff000000) == 0x47000000 17903 || (insn & 0xff600000) == 0x45600000) 17904 { 17905 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition 17906 reversed by tweaking bit 23. */ 17907 insn ^= 0x00800000; 17908 } 17909 else 17910 { 17911 /* bc[0-3][tf]l? instructions can have the condition 17912 reversed by tweaking a single TF bit, and their 17913 opcodes all have 0x4???????. */ 17914 gas_assert ((insn & 0xf3e00000) == 0x41000000); 17915 insn ^= 0x00010000; 17916 } 17917 break; 17918 17919 case 0: 17920 /* bltz 0x04000000 bgez 0x04010000 17921 bltzal 0x04100000 bgezal 0x04110000 */ 17922 gas_assert ((insn & 0xfc0e0000) == 0x04000000); 17923 insn ^= 0x00010000; 17924 break; 17925 17926 case 1: 17927 /* beq 0x10000000 bne 0x14000000 17928 blez 0x18000000 bgtz 0x1c000000 */ 17929 insn ^= 0x04000000; 17930 break; 17931 17932 default: 17933 abort (); 17934 } 17935 } 17936 17937 if (RELAX_BRANCH_LINK (fragp->fr_subtype)) 17938 { 17939 /* Clear the and-link bit. */ 17940 gas_assert ((insn & 0xfc1c0000) == 0x04100000); 17941 17942 /* bltzal 0x04100000 bgezal 0x04110000 17943 bltzall 0x04120000 bgezall 0x04130000 */ 17944 insn &= ~0x00100000; 17945 } 17946 17947 /* Branch over the branch (if the branch was likely) or the 17948 full jump (not likely case). Compute the offset from the 17949 current instruction to branch to. */ 17950 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) 17951 i = 16; 17952 else 17953 { 17954 /* How many bytes in instructions we've already emitted? */ 17955 i = buf - fragp->fr_literal - fragp->fr_fix; 17956 /* How many bytes in instructions from here to the end? */ 17957 i = fragp->fr_var - i; 17958 } 17959 /* Convert to instruction count. */ 17960 i >>= 2; 17961 /* Branch counts from the next instruction. */ 17962 i--; 17963 insn |= i; 17964 /* Branch over the jump. */ 17965 buf = write_insn (buf, insn); 17966 17967 /* nop */ 17968 buf = write_insn (buf, 0); 17969 17970 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) 17971 { 17972 /* beql $0, $0, 2f */ 17973 insn = 0x50000000; 17974 /* Compute the PC offset from the current instruction to 17975 the end of the variable frag. */ 17976 /* How many bytes in instructions we've already emitted? */ 17977 i = buf - fragp->fr_literal - fragp->fr_fix; 17978 /* How many bytes in instructions from here to the end? */ 17979 i = fragp->fr_var - i; 17980 /* Convert to instruction count. */ 17981 i >>= 2; 17982 /* Don't decrement i, because we want to branch over the 17983 delay slot. */ 17984 insn |= i; 17985 17986 buf = write_insn (buf, insn); 17987 buf = write_insn (buf, 0); 17988 } 17989 17990 uncond: 17991 if (mips_pic == NO_PIC) 17992 { 17993 /* j or jal. */ 17994 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) 17995 ? 0x0c000000 : 0x08000000); 17996 exp.X_op = O_symbol; 17997 exp.X_add_symbol = fragp->fr_symbol; 17998 exp.X_add_number = fragp->fr_offset; 17999 18000 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, 18001 FALSE, BFD_RELOC_MIPS_JMP); 18002 fixp->fx_file = fragp->fr_file; 18003 fixp->fx_line = fragp->fr_line; 18004 18005 buf = write_insn (buf, insn); 18006 } 18007 else 18008 { 18009 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype); 18010 18011 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ 18012 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000; 18013 insn |= at << OP_SH_RT; 18014 exp.X_op = O_symbol; 18015 exp.X_add_symbol = fragp->fr_symbol; 18016 exp.X_add_number = fragp->fr_offset; 18017 18018 if (fragp->fr_offset) 18019 { 18020 exp.X_add_symbol = make_expr_symbol (&exp); 18021 exp.X_add_number = 0; 18022 } 18023 18024 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, 18025 FALSE, BFD_RELOC_MIPS_GOT16); 18026 fixp->fx_file = fragp->fr_file; 18027 fixp->fx_line = fragp->fr_line; 18028 18029 buf = write_insn (buf, insn); 18030 18031 if (mips_opts.isa == ISA_MIPS1) 18032 /* nop */ 18033 buf = write_insn (buf, 0); 18034 18035 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ 18036 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000; 18037 insn |= at << OP_SH_RS | at << OP_SH_RT; 18038 18039 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, 18040 FALSE, BFD_RELOC_LO16); 18041 fixp->fx_file = fragp->fr_file; 18042 fixp->fx_line = fragp->fr_line; 18043 18044 buf = write_insn (buf, insn); 18045 18046 /* j(al)r $at. */ 18047 if (RELAX_BRANCH_LINK (fragp->fr_subtype)) 18048 insn = 0x0000f809; 18049 else 18050 insn = 0x00000008; 18051 insn |= at << OP_SH_RS; 18052 18053 buf = write_insn (buf, insn); 18054 } 18055 } 18056 18057 fragp->fr_fix += fragp->fr_var; 18058 gas_assert (buf == fragp->fr_literal + fragp->fr_fix); 18059 return; 18060 } 18061 18062 /* Relax microMIPS branches. */ 18063 if (RELAX_MICROMIPS_P (fragp->fr_subtype)) 18064 { 18065 char *buf = fragp->fr_literal + fragp->fr_fix; 18066 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); 18067 bfd_boolean insn32 = RELAX_MICROMIPS_INSN32 (fragp->fr_subtype); 18068 bfd_boolean nods = RELAX_MICROMIPS_NODS (fragp->fr_subtype); 18069 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype); 18070 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); 18071 bfd_boolean short_ds; 18072 unsigned long insn; 18073 expressionS exp; 18074 fixS *fixp; 18075 18076 exp.X_op = O_symbol; 18077 exp.X_add_symbol = fragp->fr_symbol; 18078 exp.X_add_number = fragp->fr_offset; 18079 18080 fragp->fr_fix += fragp->fr_var; 18081 18082 /* Handle 16-bit branches that fit or are forced to fit. */ 18083 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) 18084 { 18085 /* We generate a fixup instead of applying it right now, 18086 because if there is linker relaxation, we're going to 18087 need the relocations. */ 18088 if (type == 'D') 18089 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE, 18090 BFD_RELOC_MICROMIPS_10_PCREL_S1); 18091 else if (type == 'E') 18092 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE, 18093 BFD_RELOC_MICROMIPS_7_PCREL_S1); 18094 else 18095 abort (); 18096 18097 fixp->fx_file = fragp->fr_file; 18098 fixp->fx_line = fragp->fr_line; 18099 18100 /* These relocations can have an addend that won't fit in 18101 2 octets. */ 18102 fixp->fx_no_overflow = 1; 18103 18104 return; 18105 } 18106 18107 /* Handle 32-bit branches that fit or are forced to fit. */ 18108 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) 18109 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) 18110 { 18111 /* We generate a fixup instead of applying it right now, 18112 because if there is linker relaxation, we're going to 18113 need the relocations. */ 18114 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE, 18115 BFD_RELOC_MICROMIPS_16_PCREL_S1); 18116 fixp->fx_file = fragp->fr_file; 18117 fixp->fx_line = fragp->fr_line; 18118 18119 if (type == 0) 18120 { 18121 insn = read_compressed_insn (buf, 4); 18122 buf += 4; 18123 18124 if (nods) 18125 { 18126 /* Check the short-delay-slot bit. */ 18127 if (!al || (insn & 0x02000000) != 0) 18128 buf = write_compressed_insn (buf, 0x0c00, 2); 18129 else 18130 buf = write_compressed_insn (buf, 0x00000000, 4); 18131 } 18132 18133 gas_assert (buf == fragp->fr_literal + fragp->fr_fix); 18134 return; 18135 } 18136 } 18137 18138 /* Relax 16-bit branches to 32-bit branches. */ 18139 if (type != 0) 18140 { 18141 insn = read_compressed_insn (buf, 2); 18142 18143 if ((insn & 0xfc00) == 0xcc00) /* b16 */ 18144 insn = 0x94000000; /* beq */ 18145 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */ 18146 { 18147 unsigned long regno; 18148 18149 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD; 18150 regno = micromips_to_32_reg_d_map [regno]; 18151 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */ 18152 insn |= regno << MICROMIPSOP_SH_RS; 18153 } 18154 else 18155 abort (); 18156 18157 /* Nothing else to do, just write it out. */ 18158 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) 18159 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) 18160 { 18161 buf = write_compressed_insn (buf, insn, 4); 18162 if (nods) 18163 buf = write_compressed_insn (buf, 0x0c00, 2); 18164 gas_assert (buf == fragp->fr_literal + fragp->fr_fix); 18165 return; 18166 } 18167 } 18168 else 18169 insn = read_compressed_insn (buf, 4); 18170 18171 /* Relax 32-bit branches to a sequence of instructions. */ 18172 as_warn_where (fragp->fr_file, fragp->fr_line, 18173 _("relaxed out-of-range branch into a jump")); 18174 18175 /* Set the short-delay-slot bit. */ 18176 short_ds = !al || (insn & 0x02000000) != 0; 18177 18178 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype)) 18179 { 18180 symbolS *l; 18181 18182 /* Reverse the branch. */ 18183 if ((insn & 0xfc000000) == 0x94000000 /* beq */ 18184 || (insn & 0xfc000000) == 0xb4000000) /* bne */ 18185 insn ^= 0x20000000; 18186 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */ 18187 || (insn & 0xffe00000) == 0x40400000 /* bgez */ 18188 || (insn & 0xffe00000) == 0x40800000 /* blez */ 18189 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */ 18190 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */ 18191 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */ 18192 || (insn & 0xffe00000) == 0x40200000 /* bltzal */ 18193 || (insn & 0xffe00000) == 0x40600000 /* bgezal */ 18194 || (insn & 0xffe00000) == 0x42200000 /* bltzals */ 18195 || (insn & 0xffe00000) == 0x42600000) /* bgezals */ 18196 insn ^= 0x00400000; 18197 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */ 18198 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */ 18199 || (insn & 0xffe30000) == 0x42800000 /* bc2f */ 18200 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */ 18201 insn ^= 0x00200000; 18202 else if ((insn & 0xff000000) == 0x83000000 /* BZ.df 18203 BNZ.df */ 18204 || (insn & 0xff600000) == 0x81600000) /* BZ.V 18205 BNZ.V */ 18206 insn ^= 0x00800000; 18207 else 18208 abort (); 18209 18210 if (al) 18211 { 18212 /* Clear the and-link and short-delay-slot bits. */ 18213 gas_assert ((insn & 0xfda00000) == 0x40200000); 18214 18215 /* bltzal 0x40200000 bgezal 0x40600000 */ 18216 /* bltzals 0x42200000 bgezals 0x42600000 */ 18217 insn &= ~0x02200000; 18218 } 18219 18220 /* Make a label at the end for use with the branch. */ 18221 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp); 18222 micromips_label_inc (); 18223 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l))); 18224 18225 /* Refer to it. */ 18226 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE, 18227 BFD_RELOC_MICROMIPS_16_PCREL_S1); 18228 fixp->fx_file = fragp->fr_file; 18229 fixp->fx_line = fragp->fr_line; 18230 18231 /* Branch over the jump. */ 18232 buf = write_compressed_insn (buf, insn, 4); 18233 18234 if (!compact) 18235 { 18236 /* nop */ 18237 if (insn32) 18238 buf = write_compressed_insn (buf, 0x00000000, 4); 18239 else 18240 buf = write_compressed_insn (buf, 0x0c00, 2); 18241 } 18242 } 18243 18244 if (mips_pic == NO_PIC) 18245 { 18246 unsigned long jal = (short_ds || nods 18247 ? 0x74000000 : 0xf4000000); /* jal/s */ 18248 18249 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */ 18250 insn = al ? jal : 0xd4000000; 18251 18252 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, 18253 BFD_RELOC_MICROMIPS_JMP); 18254 fixp->fx_file = fragp->fr_file; 18255 fixp->fx_line = fragp->fr_line; 18256 18257 buf = write_compressed_insn (buf, insn, 4); 18258 18259 if (compact || nods) 18260 { 18261 /* nop */ 18262 if (insn32) 18263 buf = write_compressed_insn (buf, 0x00000000, 4); 18264 else 18265 buf = write_compressed_insn (buf, 0x0c00, 2); 18266 } 18267 } 18268 else 18269 { 18270 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype); 18271 18272 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */ 18273 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000; 18274 insn |= at << MICROMIPSOP_SH_RT; 18275 18276 if (exp.X_add_number) 18277 { 18278 exp.X_add_symbol = make_expr_symbol (&exp); 18279 exp.X_add_number = 0; 18280 } 18281 18282 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, 18283 BFD_RELOC_MICROMIPS_GOT16); 18284 fixp->fx_file = fragp->fr_file; 18285 fixp->fx_line = fragp->fr_line; 18286 18287 buf = write_compressed_insn (buf, insn, 4); 18288 18289 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */ 18290 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000; 18291 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS; 18292 18293 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, 18294 BFD_RELOC_MICROMIPS_LO16); 18295 fixp->fx_file = fragp->fr_file; 18296 fixp->fx_line = fragp->fr_line; 18297 18298 buf = write_compressed_insn (buf, insn, 4); 18299 18300 if (insn32) 18301 { 18302 /* jr/jalr $at */ 18303 insn = 0x00000f3c | (al ? RA : ZERO) << MICROMIPSOP_SH_RT; 18304 insn |= at << MICROMIPSOP_SH_RS; 18305 18306 buf = write_compressed_insn (buf, insn, 4); 18307 18308 if (compact || nods) 18309 /* nop */ 18310 buf = write_compressed_insn (buf, 0x00000000, 4); 18311 } 18312 else 18313 { 18314 /* jr/jrc/jalr/jalrs $at */ 18315 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */ 18316 unsigned long jr = compact || nods ? 0x45a0 : 0x4580; /* jr/c */ 18317 18318 insn = al ? jalr : jr; 18319 insn |= at << MICROMIPSOP_SH_MJ; 18320 18321 buf = write_compressed_insn (buf, insn, 2); 18322 if (al && nods) 18323 { 18324 /* nop */ 18325 if (short_ds) 18326 buf = write_compressed_insn (buf, 0x0c00, 2); 18327 else 18328 buf = write_compressed_insn (buf, 0x00000000, 4); 18329 } 18330 } 18331 } 18332 18333 gas_assert (buf == fragp->fr_literal + fragp->fr_fix); 18334 return; 18335 } 18336 18337 if (RELAX_MIPS16_P (fragp->fr_subtype)) 18338 { 18339 int type; 18340 const struct mips_int_operand *operand; 18341 offsetT val; 18342 char *buf; 18343 unsigned int user_length, length; 18344 bfd_boolean need_reloc; 18345 unsigned long insn; 18346 bfd_boolean ext; 18347 segT symsec; 18348 18349 type = RELAX_MIPS16_TYPE (fragp->fr_subtype); 18350 operand = mips16_immed_operand (type, FALSE); 18351 18352 ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype); 18353 val = resolve_symbol_value (fragp->fr_symbol) + fragp->fr_offset; 18354 18355 symsec = S_GET_SEGMENT (fragp->fr_symbol); 18356 need_reloc = (S_FORCE_RELOC (fragp->fr_symbol, TRUE) 18357 || (operand->root.type == OP_PCREL 18358 ? asec != symsec 18359 : !bfd_is_abs_section (symsec))); 18360 18361 if (operand->root.type == OP_PCREL) 18362 { 18363 const struct mips_pcrel_operand *pcrel_op; 18364 addressT addr; 18365 18366 pcrel_op = (const struct mips_pcrel_operand *) operand; 18367 addr = fragp->fr_address + fragp->fr_fix; 18368 18369 /* The rules for the base address of a PC relative reloc are 18370 complicated; see mips16_extended_frag. */ 18371 if (pcrel_op->include_isa_bit) 18372 { 18373 if (!need_reloc) 18374 { 18375 if (!ELF_ST_IS_MIPS16 (S_GET_OTHER (fragp->fr_symbol))) 18376 as_bad_where (fragp->fr_file, fragp->fr_line, 18377 _("branch to a symbol in another ISA mode")); 18378 else if ((fragp->fr_offset & 0x1) != 0) 18379 as_bad_where (fragp->fr_file, fragp->fr_line, 18380 _("branch to misaligned address (0x%lx)"), 18381 (long) val); 18382 } 18383 addr += 2; 18384 if (ext) 18385 addr += 2; 18386 /* Ignore the low bit in the target, since it will be 18387 set for a text label. */ 18388 val &= -2; 18389 } 18390 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) 18391 addr -= 4; 18392 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) 18393 addr -= 2; 18394 18395 addr &= -(1 << pcrel_op->align_log2); 18396 val -= addr; 18397 18398 /* Make sure the section winds up with the alignment we have 18399 assumed. */ 18400 if (operand->shift > 0) 18401 record_alignment (asec, operand->shift); 18402 } 18403 18404 if (ext 18405 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) 18406 || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) 18407 as_warn_where (fragp->fr_file, fragp->fr_line, 18408 _("extended instruction in delay slot")); 18409 18410 buf = fragp->fr_literal + fragp->fr_fix; 18411 18412 insn = read_compressed_insn (buf, 2); 18413 if (ext) 18414 insn |= MIPS16_EXTEND; 18415 18416 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) 18417 user_length = 4; 18418 else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) 18419 user_length = 2; 18420 else 18421 user_length = 0; 18422 18423 if (need_reloc) 18424 { 18425 bfd_reloc_code_real_type reloc = BFD_RELOC_NONE; 18426 expressionS exp; 18427 fixS *fixp; 18428 18429 switch (type) 18430 { 18431 case 'p': 18432 case 'q': 18433 reloc = BFD_RELOC_MIPS16_16_PCREL_S1; 18434 break; 18435 default: 18436 as_bad_where (fragp->fr_file, fragp->fr_line, 18437 _("unsupported relocation")); 18438 break; 18439 } 18440 if (reloc == BFD_RELOC_NONE) 18441 ; 18442 else if (ext) 18443 { 18444 exp.X_op = O_symbol; 18445 exp.X_add_symbol = fragp->fr_symbol; 18446 exp.X_add_number = fragp->fr_offset; 18447 18448 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, 18449 TRUE, reloc); 18450 18451 fixp->fx_file = fragp->fr_file; 18452 fixp->fx_line = fragp->fr_line; 18453 18454 /* These relocations can have an addend that won't fit 18455 in 2 octets. */ 18456 fixp->fx_no_overflow = 1; 18457 } 18458 else 18459 as_bad_where (fragp->fr_file, fragp->fr_line, 18460 _("invalid unextended operand value")); 18461 } 18462 else 18463 mips16_immed (fragp->fr_file, fragp->fr_line, type, 18464 BFD_RELOC_UNUSED, val, user_length, &insn); 18465 18466 length = (ext ? 4 : 2); 18467 gas_assert (mips16_opcode_length (insn) == length); 18468 write_compressed_insn (buf, insn, length); 18469 fragp->fr_fix += length; 18470 } 18471 else 18472 { 18473 relax_substateT subtype = fragp->fr_subtype; 18474 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0; 18475 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0; 18476 int first, second; 18477 fixS *fixp; 18478 18479 first = RELAX_FIRST (subtype); 18480 second = RELAX_SECOND (subtype); 18481 fixp = (fixS *) fragp->fr_opcode; 18482 18483 /* If the delay slot chosen does not match the size of the instruction, 18484 then emit a warning. */ 18485 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0) 18486 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)) 18487 { 18488 relax_substateT s; 18489 const char *msg; 18490 18491 s = subtype & (RELAX_DELAY_SLOT_16BIT 18492 | RELAX_DELAY_SLOT_SIZE_FIRST 18493 | RELAX_DELAY_SLOT_SIZE_SECOND); 18494 msg = macro_warning (s); 18495 if (msg != NULL) 18496 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); 18497 subtype &= ~s; 18498 } 18499 18500 /* Possibly emit a warning if we've chosen the longer option. */ 18501 if (use_second == second_longer) 18502 { 18503 relax_substateT s; 18504 const char *msg; 18505 18506 s = (subtype 18507 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT)); 18508 msg = macro_warning (s); 18509 if (msg != NULL) 18510 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); 18511 subtype &= ~s; 18512 } 18513 18514 /* Go through all the fixups for the first sequence. Disable them 18515 (by marking them as done) if we're going to use the second 18516 sequence instead. */ 18517 while (fixp 18518 && fixp->fx_frag == fragp 18519 && fixp->fx_where < fragp->fr_fix - second) 18520 { 18521 if (subtype & RELAX_USE_SECOND) 18522 fixp->fx_done = 1; 18523 fixp = fixp->fx_next; 18524 } 18525 18526 /* Go through the fixups for the second sequence. Disable them if 18527 we're going to use the first sequence, otherwise adjust their 18528 addresses to account for the relaxation. */ 18529 while (fixp && fixp->fx_frag == fragp) 18530 { 18531 if (subtype & RELAX_USE_SECOND) 18532 fixp->fx_where -= first; 18533 else 18534 fixp->fx_done = 1; 18535 fixp = fixp->fx_next; 18536 } 18537 18538 /* Now modify the frag contents. */ 18539 if (subtype & RELAX_USE_SECOND) 18540 { 18541 char *start; 18542 18543 start = fragp->fr_literal + fragp->fr_fix - first - second; 18544 memmove (start, start + first, second); 18545 fragp->fr_fix -= first; 18546 } 18547 else 18548 fragp->fr_fix -= second; 18549 } 18550} 18551 18552/* This function is called after the relocs have been generated. 18553 We've been storing mips16 text labels as odd. Here we convert them 18554 back to even for the convenience of the debugger. */ 18555 18556void 18557mips_frob_file_after_relocs (void) 18558{ 18559 asymbol **syms; 18560 unsigned int count, i; 18561 18562 syms = bfd_get_outsymbols (stdoutput); 18563 count = bfd_get_symcount (stdoutput); 18564 for (i = 0; i < count; i++, syms++) 18565 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other) 18566 && ((*syms)->value & 1) != 0) 18567 { 18568 (*syms)->value &= ~1; 18569 /* If the symbol has an odd size, it was probably computed 18570 incorrectly, so adjust that as well. */ 18571 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) 18572 ++elf_symbol (*syms)->internal_elf_sym.st_size; 18573 } 18574} 18575 18576/* This function is called whenever a label is defined, including fake 18577 labels instantiated off the dot special symbol. It is used when 18578 handling branch delays; if a branch has a label, we assume we cannot 18579 move it. This also bumps the value of the symbol by 1 in compressed 18580 code. */ 18581 18582static void 18583mips_record_label (symbolS *sym) 18584{ 18585 segment_info_type *si = seg_info (now_seg); 18586 struct insn_label_list *l; 18587 18588 if (free_insn_labels == NULL) 18589 l = XNEW (struct insn_label_list); 18590 else 18591 { 18592 l = free_insn_labels; 18593 free_insn_labels = l->next; 18594 } 18595 18596 l->label = sym; 18597 l->next = si->label_list; 18598 si->label_list = l; 18599} 18600 18601/* This function is called as tc_frob_label() whenever a label is defined 18602 and adds a DWARF-2 record we only want for true labels. */ 18603 18604void 18605mips_define_label (symbolS *sym) 18606{ 18607 mips_record_label (sym); 18608 dwarf2_emit_label (sym); 18609} 18610 18611/* This function is called by tc_new_dot_label whenever a new dot symbol 18612 is defined. */ 18613 18614void 18615mips_add_dot_label (symbolS *sym) 18616{ 18617 mips_record_label (sym); 18618 if (mips_assembling_insn && HAVE_CODE_COMPRESSION) 18619 mips_compressed_mark_label (sym); 18620} 18621 18622/* Converting ASE flags from internal to .MIPS.abiflags values. */ 18623static unsigned int 18624mips_convert_ase_flags (int ase) 18625{ 18626 unsigned int ext_ases = 0; 18627 18628 if (ase & ASE_DSP) 18629 ext_ases |= AFL_ASE_DSP; 18630 if (ase & ASE_DSPR2) 18631 ext_ases |= AFL_ASE_DSPR2; 18632 if (ase & ASE_DSPR3) 18633 ext_ases |= AFL_ASE_DSPR3; 18634 if (ase & ASE_EVA) 18635 ext_ases |= AFL_ASE_EVA; 18636 if (ase & ASE_MCU) 18637 ext_ases |= AFL_ASE_MCU; 18638 if (ase & ASE_MDMX) 18639 ext_ases |= AFL_ASE_MDMX; 18640 if (ase & ASE_MIPS3D) 18641 ext_ases |= AFL_ASE_MIPS3D; 18642 if (ase & ASE_MT) 18643 ext_ases |= AFL_ASE_MT; 18644 if (ase & ASE_SMARTMIPS) 18645 ext_ases |= AFL_ASE_SMARTMIPS; 18646 if (ase & ASE_VIRT) 18647 ext_ases |= AFL_ASE_VIRT; 18648 if (ase & ASE_MSA) 18649 ext_ases |= AFL_ASE_MSA; 18650 if (ase & ASE_XPA) 18651 ext_ases |= AFL_ASE_XPA; 18652 18653 return ext_ases; 18654} 18655/* Some special processing for a MIPS ELF file. */ 18656 18657void 18658mips_elf_final_processing (void) 18659{ 18660 int fpabi; 18661 Elf_Internal_ABIFlags_v0 flags; 18662 18663 flags.version = 0; 18664 flags.isa_rev = 0; 18665 switch (file_mips_opts.isa) 18666 { 18667 case INSN_ISA1: 18668 flags.isa_level = 1; 18669 break; 18670 case INSN_ISA2: 18671 flags.isa_level = 2; 18672 break; 18673 case INSN_ISA3: 18674 flags.isa_level = 3; 18675 break; 18676 case INSN_ISA4: 18677 flags.isa_level = 4; 18678 break; 18679 case INSN_ISA5: 18680 flags.isa_level = 5; 18681 break; 18682 case INSN_ISA32: 18683 flags.isa_level = 32; 18684 flags.isa_rev = 1; 18685 break; 18686 case INSN_ISA32R2: 18687 flags.isa_level = 32; 18688 flags.isa_rev = 2; 18689 break; 18690 case INSN_ISA32R3: 18691 flags.isa_level = 32; 18692 flags.isa_rev = 3; 18693 break; 18694 case INSN_ISA32R5: 18695 flags.isa_level = 32; 18696 flags.isa_rev = 5; 18697 break; 18698 case INSN_ISA32R6: 18699 flags.isa_level = 32; 18700 flags.isa_rev = 6; 18701 break; 18702 case INSN_ISA64: 18703 flags.isa_level = 64; 18704 flags.isa_rev = 1; 18705 break; 18706 case INSN_ISA64R2: 18707 flags.isa_level = 64; 18708 flags.isa_rev = 2; 18709 break; 18710 case INSN_ISA64R3: 18711 flags.isa_level = 64; 18712 flags.isa_rev = 3; 18713 break; 18714 case INSN_ISA64R5: 18715 flags.isa_level = 64; 18716 flags.isa_rev = 5; 18717 break; 18718 case INSN_ISA64R6: 18719 flags.isa_level = 64; 18720 flags.isa_rev = 6; 18721 break; 18722 } 18723 18724 flags.gpr_size = file_mips_opts.gp == 32 ? AFL_REG_32 : AFL_REG_64; 18725 flags.cpr1_size = file_mips_opts.soft_float ? AFL_REG_NONE 18726 : (file_mips_opts.ase & ASE_MSA) ? AFL_REG_128 18727 : (file_mips_opts.fp == 64) ? AFL_REG_64 18728 : AFL_REG_32; 18729 flags.cpr2_size = AFL_REG_NONE; 18730 flags.fp_abi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, 18731 Tag_GNU_MIPS_ABI_FP); 18732 flags.isa_ext = bfd_mips_isa_ext (stdoutput); 18733 flags.ases = mips_convert_ase_flags (file_mips_opts.ase); 18734 if (file_ase_mips16) 18735 flags.ases |= AFL_ASE_MIPS16; 18736 if (file_ase_micromips) 18737 flags.ases |= AFL_ASE_MICROMIPS; 18738 flags.flags1 = 0; 18739 if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts.isa, file_mips_opts.arch) 18740 || file_mips_opts.fp == 64) 18741 && file_mips_opts.oddspreg) 18742 flags.flags1 |= AFL_FLAGS1_ODDSPREG; 18743 flags.flags2 = 0; 18744 18745 bfd_mips_elf_swap_abiflags_v0_out (stdoutput, &flags, 18746 ((Elf_External_ABIFlags_v0 *) 18747 mips_flags_frag)); 18748 18749 /* Write out the register information. */ 18750 if (mips_abi != N64_ABI) 18751 { 18752 Elf32_RegInfo s; 18753 18754 s.ri_gprmask = mips_gprmask; 18755 s.ri_cprmask[0] = mips_cprmask[0]; 18756 s.ri_cprmask[1] = mips_cprmask[1]; 18757 s.ri_cprmask[2] = mips_cprmask[2]; 18758 s.ri_cprmask[3] = mips_cprmask[3]; 18759 /* The gp_value field is set by the MIPS ELF backend. */ 18760 18761 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, 18762 ((Elf32_External_RegInfo *) 18763 mips_regmask_frag)); 18764 } 18765 else 18766 { 18767 Elf64_Internal_RegInfo s; 18768 18769 s.ri_gprmask = mips_gprmask; 18770 s.ri_pad = 0; 18771 s.ri_cprmask[0] = mips_cprmask[0]; 18772 s.ri_cprmask[1] = mips_cprmask[1]; 18773 s.ri_cprmask[2] = mips_cprmask[2]; 18774 s.ri_cprmask[3] = mips_cprmask[3]; 18775 /* The gp_value field is set by the MIPS ELF backend. */ 18776 18777 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, 18778 ((Elf64_External_RegInfo *) 18779 mips_regmask_frag)); 18780 } 18781 18782 /* Set the MIPS ELF flag bits. FIXME: There should probably be some 18783 sort of BFD interface for this. */ 18784 if (mips_any_noreorder) 18785 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; 18786 if (mips_pic != NO_PIC) 18787 { 18788 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; 18789 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; 18790 } 18791 if (mips_abicalls) 18792 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; 18793 18794 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags 18795 defined at present; this might need to change in future. */ 18796 if (file_ase_mips16) 18797 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; 18798 if (file_ase_micromips) 18799 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS; 18800 if (file_mips_opts.ase & ASE_MDMX) 18801 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; 18802 18803 /* Set the MIPS ELF ABI flags. */ 18804 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) 18805 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; 18806 else if (mips_abi == O64_ABI) 18807 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; 18808 else if (mips_abi == EABI_ABI) 18809 { 18810 if (file_mips_opts.gp == 64) 18811 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; 18812 else 18813 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; 18814 } 18815 else if (mips_abi == N32_ABI) 18816 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; 18817 18818 /* Nothing to do for N64_ABI. */ 18819 18820 if (mips_32bitmode) 18821 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; 18822 18823 if (mips_nan2008 == 1) 18824 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008; 18825 18826 /* 32 bit code with 64 bit FP registers. */ 18827 fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, 18828 Tag_GNU_MIPS_ABI_FP); 18829 if (fpabi == Val_GNU_MIPS_ABI_FP_OLD_64) 18830 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_FP64; 18831} 18832 18833typedef struct proc { 18834 symbolS *func_sym; 18835 symbolS *func_end_sym; 18836 unsigned long reg_mask; 18837 unsigned long reg_offset; 18838 unsigned long fpreg_mask; 18839 unsigned long fpreg_offset; 18840 unsigned long frame_offset; 18841 unsigned long frame_reg; 18842 unsigned long pc_reg; 18843} procS; 18844 18845static procS cur_proc; 18846static procS *cur_proc_ptr; 18847static int numprocs; 18848 18849/* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop 18850 as "2", and a normal nop as "0". */ 18851 18852#define NOP_OPCODE_MIPS 0 18853#define NOP_OPCODE_MIPS16 1 18854#define NOP_OPCODE_MICROMIPS 2 18855 18856char 18857mips_nop_opcode (void) 18858{ 18859 if (seg_info (now_seg)->tc_segment_info_data.micromips) 18860 return NOP_OPCODE_MICROMIPS; 18861 else if (seg_info (now_seg)->tc_segment_info_data.mips16) 18862 return NOP_OPCODE_MIPS16; 18863 else 18864 return NOP_OPCODE_MIPS; 18865} 18866 18867/* Fill in an rs_align_code fragment. Unlike elsewhere we want to use 18868 32-bit microMIPS NOPs here (if applicable). */ 18869 18870void 18871mips_handle_align (fragS *fragp) 18872{ 18873 char nop_opcode; 18874 char *p; 18875 int bytes, size, excess; 18876 valueT opcode; 18877 18878 if (fragp->fr_type != rs_align_code) 18879 return; 18880 18881 p = fragp->fr_literal + fragp->fr_fix; 18882 nop_opcode = *p; 18883 switch (nop_opcode) 18884 { 18885 case NOP_OPCODE_MICROMIPS: 18886 opcode = micromips_nop32_insn.insn_opcode; 18887 size = 4; 18888 break; 18889 case NOP_OPCODE_MIPS16: 18890 opcode = mips16_nop_insn.insn_opcode; 18891 size = 2; 18892 break; 18893 case NOP_OPCODE_MIPS: 18894 default: 18895 opcode = nop_insn.insn_opcode; 18896 size = 4; 18897 break; 18898 } 18899 18900 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; 18901 excess = bytes % size; 18902 18903 /* Handle the leading part if we're not inserting a whole number of 18904 instructions, and make it the end of the fixed part of the frag. 18905 Try to fit in a short microMIPS NOP if applicable and possible, 18906 and use zeroes otherwise. */ 18907 gas_assert (excess < 4); 18908 fragp->fr_fix += excess; 18909 switch (excess) 18910 { 18911 case 3: 18912 *p++ = '\0'; 18913 /* Fall through. */ 18914 case 2: 18915 if (nop_opcode == NOP_OPCODE_MICROMIPS && !mips_opts.insn32) 18916 { 18917 p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2); 18918 break; 18919 } 18920 *p++ = '\0'; 18921 /* Fall through. */ 18922 case 1: 18923 *p++ = '\0'; 18924 /* Fall through. */ 18925 case 0: 18926 break; 18927 } 18928 18929 md_number_to_chars (p, opcode, size); 18930 fragp->fr_var = size; 18931} 18932 18933static long 18934get_number (void) 18935{ 18936 int negative = 0; 18937 long val = 0; 18938 18939 if (*input_line_pointer == '-') 18940 { 18941 ++input_line_pointer; 18942 negative = 1; 18943 } 18944 if (!ISDIGIT (*input_line_pointer)) 18945 as_bad (_("expected simple number")); 18946 if (input_line_pointer[0] == '0') 18947 { 18948 if (input_line_pointer[1] == 'x') 18949 { 18950 input_line_pointer += 2; 18951 while (ISXDIGIT (*input_line_pointer)) 18952 { 18953 val <<= 4; 18954 val |= hex_value (*input_line_pointer++); 18955 } 18956 return negative ? -val : val; 18957 } 18958 else 18959 { 18960 ++input_line_pointer; 18961 while (ISDIGIT (*input_line_pointer)) 18962 { 18963 val <<= 3; 18964 val |= *input_line_pointer++ - '0'; 18965 } 18966 return negative ? -val : val; 18967 } 18968 } 18969 if (!ISDIGIT (*input_line_pointer)) 18970 { 18971 printf (_(" *input_line_pointer == '%c' 0x%02x\n"), 18972 *input_line_pointer, *input_line_pointer); 18973 as_warn (_("invalid number")); 18974 return -1; 18975 } 18976 while (ISDIGIT (*input_line_pointer)) 18977 { 18978 val *= 10; 18979 val += *input_line_pointer++ - '0'; 18980 } 18981 return negative ? -val : val; 18982} 18983 18984/* The .file directive; just like the usual .file directive, but there 18985 is an initial number which is the ECOFF file index. In the non-ECOFF 18986 case .file implies DWARF-2. */ 18987 18988static void 18989s_mips_file (int x ATTRIBUTE_UNUSED) 18990{ 18991 static int first_file_directive = 0; 18992 18993 if (ECOFF_DEBUGGING) 18994 { 18995 get_number (); 18996 s_app_file (0); 18997 } 18998 else 18999 { 19000 char *filename; 19001 19002 filename = dwarf2_directive_file (0); 19003 19004 /* Versions of GCC up to 3.1 start files with a ".file" 19005 directive even for stabs output. Make sure that this 19006 ".file" is handled. Note that you need a version of GCC 19007 after 3.1 in order to support DWARF-2 on MIPS. */ 19008 if (filename != NULL && ! first_file_directive) 19009 { 19010 (void) new_logical_line (filename, -1); 19011 s_app_file_string (filename, 0); 19012 } 19013 first_file_directive = 1; 19014 } 19015} 19016 19017/* The .loc directive, implying DWARF-2. */ 19018 19019static void 19020s_mips_loc (int x ATTRIBUTE_UNUSED) 19021{ 19022 if (!ECOFF_DEBUGGING) 19023 dwarf2_directive_loc (0); 19024} 19025 19026/* The .end directive. */ 19027 19028static void 19029s_mips_end (int x ATTRIBUTE_UNUSED) 19030{ 19031 symbolS *p; 19032 19033 /* Following functions need their own .frame and .cprestore directives. */ 19034 mips_frame_reg_valid = 0; 19035 mips_cprestore_valid = 0; 19036 19037 if (!is_end_of_line[(unsigned char) *input_line_pointer]) 19038 { 19039 p = get_symbol (); 19040 demand_empty_rest_of_line (); 19041 } 19042 else 19043 p = NULL; 19044 19045 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) 19046 as_warn (_(".end not in text section")); 19047 19048 if (!cur_proc_ptr) 19049 { 19050 as_warn (_(".end directive without a preceding .ent directive")); 19051 demand_empty_rest_of_line (); 19052 return; 19053 } 19054 19055 if (p != NULL) 19056 { 19057 gas_assert (S_GET_NAME (p)); 19058 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) 19059 as_warn (_(".end symbol does not match .ent symbol")); 19060 19061 if (debug_type == DEBUG_STABS) 19062 stabs_generate_asm_endfunc (S_GET_NAME (p), 19063 S_GET_NAME (p)); 19064 } 19065 else 19066 as_warn (_(".end directive missing or unknown symbol")); 19067 19068 /* Create an expression to calculate the size of the function. */ 19069 if (p && cur_proc_ptr) 19070 { 19071 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); 19072 expressionS *exp = XNEW (expressionS); 19073 19074 obj->size = exp; 19075 exp->X_op = O_subtract; 19076 exp->X_add_symbol = symbol_temp_new_now (); 19077 exp->X_op_symbol = p; 19078 exp->X_add_number = 0; 19079 19080 cur_proc_ptr->func_end_sym = exp->X_add_symbol; 19081 } 19082 19083 /* Generate a .pdr section. */ 19084 if (!ECOFF_DEBUGGING && mips_flag_pdr) 19085 { 19086 segT saved_seg = now_seg; 19087 subsegT saved_subseg = now_subseg; 19088 expressionS exp; 19089 char *fragp; 19090 19091#ifdef md_flush_pending_output 19092 md_flush_pending_output (); 19093#endif 19094 19095 gas_assert (pdr_seg); 19096 subseg_set (pdr_seg, 0); 19097 19098 /* Write the symbol. */ 19099 exp.X_op = O_symbol; 19100 exp.X_add_symbol = p; 19101 exp.X_add_number = 0; 19102 emit_expr (&exp, 4); 19103 19104 fragp = frag_more (7 * 4); 19105 19106 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); 19107 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); 19108 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); 19109 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); 19110 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); 19111 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); 19112 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); 19113 19114 subseg_set (saved_seg, saved_subseg); 19115 } 19116 19117 cur_proc_ptr = NULL; 19118} 19119 19120/* The .aent and .ent directives. */ 19121 19122static void 19123s_mips_ent (int aent) 19124{ 19125 symbolS *symbolP; 19126 19127 symbolP = get_symbol (); 19128 if (*input_line_pointer == ',') 19129 ++input_line_pointer; 19130 SKIP_WHITESPACE (); 19131 if (ISDIGIT (*input_line_pointer) 19132 || *input_line_pointer == '-') 19133 get_number (); 19134 19135 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) 19136 as_warn (_(".ent or .aent not in text section")); 19137 19138 if (!aent && cur_proc_ptr) 19139 as_warn (_("missing .end")); 19140 19141 if (!aent) 19142 { 19143 /* This function needs its own .frame and .cprestore directives. */ 19144 mips_frame_reg_valid = 0; 19145 mips_cprestore_valid = 0; 19146 19147 cur_proc_ptr = &cur_proc; 19148 memset (cur_proc_ptr, '\0', sizeof (procS)); 19149 19150 cur_proc_ptr->func_sym = symbolP; 19151 19152 ++numprocs; 19153 19154 if (debug_type == DEBUG_STABS) 19155 stabs_generate_asm_func (S_GET_NAME (symbolP), 19156 S_GET_NAME (symbolP)); 19157 } 19158 19159 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; 19160 19161 demand_empty_rest_of_line (); 19162} 19163 19164/* The .frame directive. If the mdebug section is present (IRIX 5 native) 19165 then ecoff.c (ecoff_directive_frame) is used. For embedded targets, 19166 s_mips_frame is used so that we can set the PDR information correctly. 19167 We can't use the ecoff routines because they make reference to the ecoff 19168 symbol table (in the mdebug section). */ 19169 19170static void 19171s_mips_frame (int ignore ATTRIBUTE_UNUSED) 19172{ 19173 if (ECOFF_DEBUGGING) 19174 s_ignore (ignore); 19175 else 19176 { 19177 long val; 19178 19179 if (cur_proc_ptr == (procS *) NULL) 19180 { 19181 as_warn (_(".frame outside of .ent")); 19182 demand_empty_rest_of_line (); 19183 return; 19184 } 19185 19186 cur_proc_ptr->frame_reg = tc_get_register (1); 19187 19188 SKIP_WHITESPACE (); 19189 if (*input_line_pointer++ != ',' 19190 || get_absolute_expression_and_terminator (&val) != ',') 19191 { 19192 as_warn (_("bad .frame directive")); 19193 --input_line_pointer; 19194 demand_empty_rest_of_line (); 19195 return; 19196 } 19197 19198 cur_proc_ptr->frame_offset = val; 19199 cur_proc_ptr->pc_reg = tc_get_register (0); 19200 19201 demand_empty_rest_of_line (); 19202 } 19203} 19204 19205/* The .fmask and .mask directives. If the mdebug section is present 19206 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For 19207 embedded targets, s_mips_mask is used so that we can set the PDR 19208 information correctly. We can't use the ecoff routines because they 19209 make reference to the ecoff symbol table (in the mdebug section). */ 19210 19211static void 19212s_mips_mask (int reg_type) 19213{ 19214 if (ECOFF_DEBUGGING) 19215 s_ignore (reg_type); 19216 else 19217 { 19218 long mask, off; 19219 19220 if (cur_proc_ptr == (procS *) NULL) 19221 { 19222 as_warn (_(".mask/.fmask outside of .ent")); 19223 demand_empty_rest_of_line (); 19224 return; 19225 } 19226 19227 if (get_absolute_expression_and_terminator (&mask) != ',') 19228 { 19229 as_warn (_("bad .mask/.fmask directive")); 19230 --input_line_pointer; 19231 demand_empty_rest_of_line (); 19232 return; 19233 } 19234 19235 off = get_absolute_expression (); 19236 19237 if (reg_type == 'F') 19238 { 19239 cur_proc_ptr->fpreg_mask = mask; 19240 cur_proc_ptr->fpreg_offset = off; 19241 } 19242 else 19243 { 19244 cur_proc_ptr->reg_mask = mask; 19245 cur_proc_ptr->reg_offset = off; 19246 } 19247 19248 demand_empty_rest_of_line (); 19249 } 19250} 19251 19252/* A table describing all the processors gas knows about. Names are 19253 matched in the order listed. 19254 19255 To ease comparison, please keep this table in the same order as 19256 gcc's mips_cpu_info_table[]. */ 19257static const struct mips_cpu_info mips_cpu_info_table[] = 19258{ 19259 /* Entries for generic ISAs */ 19260 { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 }, 19261 { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 }, 19262 { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 }, 19263 { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 }, 19264 { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 }, 19265 { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 }, 19266 { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 19267 { "mips32r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R3, CPU_MIPS32R3 }, 19268 { "mips32r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R5, CPU_MIPS32R5 }, 19269 { "mips32r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R6, CPU_MIPS32R6 }, 19270 { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 }, 19271 { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 }, 19272 { "mips64r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R3, CPU_MIPS64R3 }, 19273 { "mips64r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R5, CPU_MIPS64R5 }, 19274 { "mips64r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R6, CPU_MIPS64R6 }, 19275 19276 /* MIPS I */ 19277 { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 }, 19278 { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 }, 19279 { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 }, 19280 19281 /* MIPS II */ 19282 { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 }, 19283 19284 /* MIPS III */ 19285 { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 }, 19286 { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 }, 19287 { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 }, 19288 { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 }, 19289 { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 }, 19290 { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 }, 19291 { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 }, 19292 { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 }, 19293 { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 }, 19294 { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 }, 19295 { "orion", 0, 0, ISA_MIPS3, CPU_R4600 }, 19296 { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 }, 19297 { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 }, 19298 /* ST Microelectronics Loongson 2E and 2F cores */ 19299 { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E }, 19300 { "loongson2f", 0, 0, ISA_MIPS3, CPU_LOONGSON_2F }, 19301 19302 /* MIPS IV */ 19303 { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 }, 19304 { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 }, 19305 { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 }, 19306 { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 }, 19307 { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 }, 19308 { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 }, 19309 { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 }, 19310 { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 }, 19311 { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 }, 19312 { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 }, 19313 { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 }, 19314 { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 }, 19315 { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 }, 19316 { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 }, 19317 { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 }, 19318 19319 /* MIPS 32 */ 19320 { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 }, 19321 { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 }, 19322 { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 }, 19323 { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, 19324 19325 /* MIPS 32 Release 2 */ 19326 { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 19327 { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 19328 { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 19329 { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, 19330 { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 19331 { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 19332 { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, 19333 { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, 19334 { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU, 19335 ISA_MIPS32R2, CPU_MIPS32R2 }, 19336 { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU, 19337 ISA_MIPS32R2, CPU_MIPS32R2 }, 19338 { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 19339 { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 19340 { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 19341 { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 19342 /* Deprecated forms of the above. */ 19343 { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 19344 { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 19345 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ 19346 { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, 19347 { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, 19348 { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, 19349 { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, 19350 /* Deprecated forms of the above. */ 19351 { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, 19352 { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, 19353 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ 19354 { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, 19355 { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, 19356 { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, 19357 { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, 19358 /* Deprecated forms of the above. */ 19359 { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, 19360 { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, 19361 /* 34Kn is a 34kc without DSP. */ 19362 { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, 19363 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ 19364 { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, 19365 { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, 19366 { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, 19367 { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, 19368 { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, 19369 /* Deprecated forms of the above. */ 19370 { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, 19371 { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, 19372 /* 1004K cores are multiprocessor versions of the 34K. */ 19373 { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, 19374 { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, 19375 { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, 19376 { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, 19377 /* interaptiv is the new name for 1004kf */ 19378 { "interaptiv", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, 19379 /* M5100 family */ 19380 { "m5100", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 }, 19381 { "m5101", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 }, 19382 /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */ 19383 { "p5600", 0, ASE_VIRT | ASE_EVA | ASE_XPA, ISA_MIPS32R5, CPU_MIPS32R5 }, 19384 19385 /* MIPS 64 */ 19386 { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 }, 19387 { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 }, 19388 { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, 19389 { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, 19390 19391 /* Broadcom SB-1 CPU core */ 19392 { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 }, 19393 /* Broadcom SB-1A CPU core */ 19394 { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 }, 19395 19396 { "loongson3a", 0, 0, ISA_MIPS64R2, CPU_LOONGSON_3A }, 19397 19398 /* MIPS 64 Release 2 */ 19399 19400 /* Cavium Networks Octeon CPU core */ 19401 { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON }, 19402 { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP }, 19403 { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 }, 19404 { "octeon3", 0, ASE_VIRT | ASE_VIRT64, ISA_MIPS64R5, CPU_OCTEON3 }, 19405 19406 /* RMI Xlr */ 19407 { "xlr", 0, 0, ISA_MIPS64, CPU_XLR }, 19408 19409 /* Broadcom XLP. 19410 XLP is mostly like XLR, with the prominent exception that it is 19411 MIPS64R2 rather than MIPS64. */ 19412 { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR }, 19413 19414 /* MIPS 64 Release 6 */ 19415 { "i6400", 0, ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6}, 19416 { "p6600", 0, ASE_VIRT | ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6}, 19417 19418 /* End marker */ 19419 { NULL, 0, 0, 0, 0 } 19420}; 19421 19422 19423/* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL 19424 with a final "000" replaced by "k". Ignore case. 19425 19426 Note: this function is shared between GCC and GAS. */ 19427 19428static bfd_boolean 19429mips_strict_matching_cpu_name_p (const char *canonical, const char *given) 19430{ 19431 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) 19432 given++, canonical++; 19433 19434 return ((*given == 0 && *canonical == 0) 19435 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); 19436} 19437 19438 19439/* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied 19440 CPU name. We've traditionally allowed a lot of variation here. 19441 19442 Note: this function is shared between GCC and GAS. */ 19443 19444static bfd_boolean 19445mips_matching_cpu_name_p (const char *canonical, const char *given) 19446{ 19447 /* First see if the name matches exactly, or with a final "000" 19448 turned into "k". */ 19449 if (mips_strict_matching_cpu_name_p (canonical, given)) 19450 return TRUE; 19451 19452 /* If not, try comparing based on numerical designation alone. 19453 See if GIVEN is an unadorned number, or 'r' followed by a number. */ 19454 if (TOLOWER (*given) == 'r') 19455 given++; 19456 if (!ISDIGIT (*given)) 19457 return FALSE; 19458 19459 /* Skip over some well-known prefixes in the canonical name, 19460 hoping to find a number there too. */ 19461 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') 19462 canonical += 2; 19463 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') 19464 canonical += 2; 19465 else if (TOLOWER (canonical[0]) == 'r') 19466 canonical += 1; 19467 19468 return mips_strict_matching_cpu_name_p (canonical, given); 19469} 19470 19471 19472/* Parse an option that takes the name of a processor as its argument. 19473 OPTION is the name of the option and CPU_STRING is the argument. 19474 Return the corresponding processor enumeration if the CPU_STRING is 19475 recognized, otherwise report an error and return null. 19476 19477 A similar function exists in GCC. */ 19478 19479static const struct mips_cpu_info * 19480mips_parse_cpu (const char *option, const char *cpu_string) 19481{ 19482 const struct mips_cpu_info *p; 19483 19484 /* 'from-abi' selects the most compatible architecture for the given 19485 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the 19486 EABIs, we have to decide whether we're using the 32-bit or 64-bit 19487 version. Look first at the -mgp options, if given, otherwise base 19488 the choice on MIPS_DEFAULT_64BIT. 19489 19490 Treat NO_ABI like the EABIs. One reason to do this is that the 19491 plain 'mips' and 'mips64' configs have 'from-abi' as their default 19492 architecture. This code picks MIPS I for 'mips' and MIPS III for 19493 'mips64', just as we did in the days before 'from-abi'. */ 19494 if (strcasecmp (cpu_string, "from-abi") == 0) 19495 { 19496 if (ABI_NEEDS_32BIT_REGS (mips_abi)) 19497 return mips_cpu_info_from_isa (ISA_MIPS1); 19498 19499 if (ABI_NEEDS_64BIT_REGS (mips_abi)) 19500 return mips_cpu_info_from_isa (ISA_MIPS3); 19501 19502 if (file_mips_opts.gp >= 0) 19503 return mips_cpu_info_from_isa (file_mips_opts.gp == 32 19504 ? ISA_MIPS1 : ISA_MIPS3); 19505 19506 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT 19507 ? ISA_MIPS3 19508 : ISA_MIPS1); 19509 } 19510 19511 /* 'default' has traditionally been a no-op. Probably not very useful. */ 19512 if (strcasecmp (cpu_string, "default") == 0) 19513 return 0; 19514 19515 for (p = mips_cpu_info_table; p->name != 0; p++) 19516 if (mips_matching_cpu_name_p (p->name, cpu_string)) 19517 return p; 19518 19519 as_bad (_("bad value (%s) for %s"), cpu_string, option); 19520 return 0; 19521} 19522 19523/* Return the canonical processor information for ISA (a member of the 19524 ISA_MIPS* enumeration). */ 19525 19526static const struct mips_cpu_info * 19527mips_cpu_info_from_isa (int isa) 19528{ 19529 int i; 19530 19531 for (i = 0; mips_cpu_info_table[i].name != NULL; i++) 19532 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) 19533 && isa == mips_cpu_info_table[i].isa) 19534 return (&mips_cpu_info_table[i]); 19535 19536 return NULL; 19537} 19538 19539static const struct mips_cpu_info * 19540mips_cpu_info_from_arch (int arch) 19541{ 19542 int i; 19543 19544 for (i = 0; mips_cpu_info_table[i].name != NULL; i++) 19545 if (arch == mips_cpu_info_table[i].cpu) 19546 return (&mips_cpu_info_table[i]); 19547 19548 return NULL; 19549} 19550 19551static void 19552show (FILE *stream, const char *string, int *col_p, int *first_p) 19553{ 19554 if (*first_p) 19555 { 19556 fprintf (stream, "%24s", ""); 19557 *col_p = 24; 19558 } 19559 else 19560 { 19561 fprintf (stream, ", "); 19562 *col_p += 2; 19563 } 19564 19565 if (*col_p + strlen (string) > 72) 19566 { 19567 fprintf (stream, "\n%24s", ""); 19568 *col_p = 24; 19569 } 19570 19571 fprintf (stream, "%s", string); 19572 *col_p += strlen (string); 19573 19574 *first_p = 0; 19575} 19576 19577void 19578md_show_usage (FILE *stream) 19579{ 19580 int column, first; 19581 size_t i; 19582 19583 fprintf (stream, _("\ 19584MIPS options:\n\ 19585-EB generate big endian output\n\ 19586-EL generate little endian output\n\ 19587-g, -g2 do not remove unneeded NOPs or swap branches\n\ 19588-G NUM allow referencing objects up to NUM bytes\n\ 19589 implicitly with the gp register [default 8]\n")); 19590 fprintf (stream, _("\ 19591-mips1 generate MIPS ISA I instructions\n\ 19592-mips2 generate MIPS ISA II instructions\n\ 19593-mips3 generate MIPS ISA III instructions\n\ 19594-mips4 generate MIPS ISA IV instructions\n\ 19595-mips5 generate MIPS ISA V instructions\n\ 19596-mips32 generate MIPS32 ISA instructions\n\ 19597-mips32r2 generate MIPS32 release 2 ISA instructions\n\ 19598-mips32r3 generate MIPS32 release 3 ISA instructions\n\ 19599-mips32r5 generate MIPS32 release 5 ISA instructions\n\ 19600-mips32r6 generate MIPS32 release 6 ISA instructions\n\ 19601-mips64 generate MIPS64 ISA instructions\n\ 19602-mips64r2 generate MIPS64 release 2 ISA instructions\n\ 19603-mips64r3 generate MIPS64 release 3 ISA instructions\n\ 19604-mips64r5 generate MIPS64 release 5 ISA instructions\n\ 19605-mips64r6 generate MIPS64 release 6 ISA instructions\n\ 19606-march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); 19607 19608 first = 1; 19609 19610 for (i = 0; mips_cpu_info_table[i].name != NULL; i++) 19611 show (stream, mips_cpu_info_table[i].name, &column, &first); 19612 show (stream, "from-abi", &column, &first); 19613 fputc ('\n', stream); 19614 19615 fprintf (stream, _("\ 19616-mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ 19617-no-mCPU don't generate code specific to CPU.\n\ 19618 For -mCPU and -no-mCPU, CPU must be one of:\n")); 19619 19620 first = 1; 19621 19622 show (stream, "3900", &column, &first); 19623 show (stream, "4010", &column, &first); 19624 show (stream, "4100", &column, &first); 19625 show (stream, "4650", &column, &first); 19626 fputc ('\n', stream); 19627 19628 fprintf (stream, _("\ 19629-mips16 generate mips16 instructions\n\ 19630-no-mips16 do not generate mips16 instructions\n")); 19631 fprintf (stream, _("\ 19632-mmicromips generate microMIPS instructions\n\ 19633-mno-micromips do not generate microMIPS instructions\n")); 19634 fprintf (stream, _("\ 19635-msmartmips generate smartmips instructions\n\ 19636-mno-smartmips do not generate smartmips instructions\n")); 19637 fprintf (stream, _("\ 19638-mdsp generate DSP instructions\n\ 19639-mno-dsp do not generate DSP instructions\n")); 19640 fprintf (stream, _("\ 19641-mdspr2 generate DSP R2 instructions\n\ 19642-mno-dspr2 do not generate DSP R2 instructions\n")); 19643 fprintf (stream, _("\ 19644-mdspr3 generate DSP R3 instructions\n\ 19645-mno-dspr3 do not generate DSP R3 instructions\n")); 19646 fprintf (stream, _("\ 19647-mmt generate MT instructions\n\ 19648-mno-mt do not generate MT instructions\n")); 19649 fprintf (stream, _("\ 19650-mmcu generate MCU instructions\n\ 19651-mno-mcu do not generate MCU instructions\n")); 19652 fprintf (stream, _("\ 19653-mmsa generate MSA instructions\n\ 19654-mno-msa do not generate MSA instructions\n")); 19655 fprintf (stream, _("\ 19656-mxpa generate eXtended Physical Address (XPA) instructions\n\ 19657-mno-xpa do not generate eXtended Physical Address (XPA) instructions\n")); 19658 fprintf (stream, _("\ 19659-mvirt generate Virtualization instructions\n\ 19660-mno-virt do not generate Virtualization instructions\n")); 19661 fprintf (stream, _("\ 19662-minsn32 only generate 32-bit microMIPS instructions\n\ 19663-mno-insn32 generate all microMIPS instructions\n")); 19664 fprintf (stream, _("\ 19665-mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\ 19666-mfix-loongson2f-nop work around Loongson2F NOP errata\n\ 19667-mfix-vr4120 work around certain VR4120 errata\n\ 19668-mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ 19669-mfix-24k insert a nop after ERET and DERET instructions\n\ 19670-mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\ 19671-mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ 19672-mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ 19673-msym32 assume all symbols have 32-bit values\n\ 19674-O0 remove unneeded NOPs, do not swap branches\n\ 19675-O remove unneeded NOPs and swap branches\n\ 19676--trap, --no-break trap exception on div by 0 and mult overflow\n\ 19677--break, --no-trap break exception on div by 0 and mult overflow\n")); 19678 fprintf (stream, _("\ 19679-mhard-float allow floating-point instructions\n\ 19680-msoft-float do not allow floating-point instructions\n\ 19681-msingle-float only allow 32-bit floating-point operations\n\ 19682-mdouble-float allow 32-bit and 64-bit floating-point operations\n\ 19683--[no-]construct-floats [dis]allow floating point values to be constructed\n\ 19684--[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\ 19685-mignore-branch-isa accept invalid branches requiring an ISA mode switch\n\ 19686-mno-ignore-branch-isa reject invalid branches requiring an ISA mode switch\n\ 19687-mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n")); 19688 19689 first = 1; 19690 19691 show (stream, "legacy", &column, &first); 19692 show (stream, "2008", &column, &first); 19693 19694 fputc ('\n', stream); 19695 19696 fprintf (stream, _("\ 19697-KPIC, -call_shared generate SVR4 position independent code\n\ 19698-call_nonpic generate non-PIC code that can operate with DSOs\n\ 19699-mvxworks-pic generate VxWorks position independent code\n\ 19700-non_shared do not generate code that can operate with DSOs\n\ 19701-xgot assume a 32 bit GOT\n\ 19702-mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ 19703-mshared, -mno-shared disable/enable .cpload optimization for\n\ 19704 position dependent (non shared) code\n\ 19705-mabi=ABI create ABI conformant object file for:\n")); 19706 19707 first = 1; 19708 19709 show (stream, "32", &column, &first); 19710 show (stream, "o64", &column, &first); 19711 show (stream, "n32", &column, &first); 19712 show (stream, "64", &column, &first); 19713 show (stream, "eabi", &column, &first); 19714 19715 fputc ('\n', stream); 19716 19717 fprintf (stream, _("\ 19718-32 create o32 ABI object file (default)\n\ 19719-n32 create n32 ABI object file\n\ 19720-64 create 64 ABI object file\n")); 19721} 19722 19723#ifdef TE_IRIX 19724enum dwarf2_format 19725mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED) 19726{ 19727 if (HAVE_64BIT_SYMBOLS) 19728 return dwarf2_format_64bit_irix; 19729 else 19730 return dwarf2_format_32bit; 19731} 19732#endif 19733 19734int 19735mips_dwarf2_addr_size (void) 19736{ 19737 if (HAVE_64BIT_OBJECTS) 19738 return 8; 19739 else 19740 return 4; 19741} 19742 19743/* Standard calling conventions leave the CFA at SP on entry. */ 19744void 19745mips_cfi_frame_initial_instructions (void) 19746{ 19747 cfi_add_CFA_def_cfa_register (SP); 19748} 19749 19750int 19751tc_mips_regname_to_dw2regnum (char *regname) 19752{ 19753 unsigned int regnum = -1; 19754 unsigned int reg; 19755 19756 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) 19757 regnum = reg; 19758 19759 return regnum; 19760} 19761 19762/* Implement CONVERT_SYMBOLIC_ATTRIBUTE. 19763 Given a symbolic attribute NAME, return the proper integer value. 19764 Returns -1 if the attribute is not known. */ 19765 19766int 19767mips_convert_symbolic_attribute (const char *name) 19768{ 19769 static const struct 19770 { 19771 const char * name; 19772 const int tag; 19773 } 19774 attribute_table[] = 19775 { 19776#define T(tag) {#tag, tag} 19777 T (Tag_GNU_MIPS_ABI_FP), 19778 T (Tag_GNU_MIPS_ABI_MSA), 19779#undef T 19780 }; 19781 unsigned int i; 19782 19783 if (name == NULL) 19784 return -1; 19785 19786 for (i = 0; i < ARRAY_SIZE (attribute_table); i++) 19787 if (streq (name, attribute_table[i].name)) 19788 return attribute_table[i].tag; 19789 19790 return -1; 19791} 19792 19793void 19794md_mips_end (void) 19795{ 19796 int fpabi = Val_GNU_MIPS_ABI_FP_ANY; 19797 19798 mips_emit_delays (); 19799 if (cur_proc_ptr) 19800 as_warn (_("missing .end at end of assembly")); 19801 19802 /* Just in case no code was emitted, do the consistency check. */ 19803 file_mips_check_options (); 19804 19805 /* Set a floating-point ABI if the user did not. */ 19806 if (obj_elf_seen_attribute (OBJ_ATTR_GNU, Tag_GNU_MIPS_ABI_FP)) 19807 { 19808 /* Perform consistency checks on the floating-point ABI. */ 19809 fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, 19810 Tag_GNU_MIPS_ABI_FP); 19811 if (fpabi != Val_GNU_MIPS_ABI_FP_ANY) 19812 check_fpabi (fpabi); 19813 } 19814 else 19815 { 19816 /* Soft-float gets precedence over single-float, the two options should 19817 not be used together so this should not matter. */ 19818 if (file_mips_opts.soft_float == 1) 19819 fpabi = Val_GNU_MIPS_ABI_FP_SOFT; 19820 /* Single-float gets precedence over all double_float cases. */ 19821 else if (file_mips_opts.single_float == 1) 19822 fpabi = Val_GNU_MIPS_ABI_FP_SINGLE; 19823 else 19824 { 19825 switch (file_mips_opts.fp) 19826 { 19827 case 32: 19828 if (file_mips_opts.gp == 32) 19829 fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE; 19830 break; 19831 case 0: 19832 fpabi = Val_GNU_MIPS_ABI_FP_XX; 19833 break; 19834 case 64: 19835 if (file_mips_opts.gp == 32 && !file_mips_opts.oddspreg) 19836 fpabi = Val_GNU_MIPS_ABI_FP_64A; 19837 else if (file_mips_opts.gp == 32) 19838 fpabi = Val_GNU_MIPS_ABI_FP_64; 19839 else 19840 fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE; 19841 break; 19842 } 19843 } 19844 19845 bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, 19846 Tag_GNU_MIPS_ABI_FP, fpabi); 19847 } 19848} 19849 19850/* Returns the relocation type required for a particular CFI encoding. */ 19851 19852bfd_reloc_code_real_type 19853mips_cfi_reloc_for_encoding (int encoding) 19854{ 19855 if (encoding == (DW_EH_PE_sdata4 | DW_EH_PE_pcrel)) 19856 return BFD_RELOC_32_PCREL; 19857 else return BFD_RELOC_NONE; 19858} 19859