1/* tc-i386.c -- Assemble code for the Intel 80386 2 Copyright (C) 1989-2017 Free Software Foundation, Inc. 3 4 This file is part of GAS, the GNU Assembler. 5 6 GAS is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 GAS is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GAS; see the file COPYING. If not, write to the Free 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 19 02110-1301, USA. */ 20 21/* Intel 80386 machine specific gas. 22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu). 23 x86_64 support by Jan Hubicka (jh@suse.cz) 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz) 25 Bugs & suggestions are completely welcome. This is free software. 26 Please help us make it better. */ 27 28#include "as.h" 29#include "safe-ctype.h" 30#include "subsegs.h" 31#include "dwarf2dbg.h" 32#include "dw2gencfi.h" 33#include "elf/x86-64.h" 34#include "opcodes/i386-init.h" 35 36#ifndef REGISTER_WARNINGS 37#define REGISTER_WARNINGS 1 38#endif 39 40#ifndef INFER_ADDR_PREFIX 41#define INFER_ADDR_PREFIX 1 42#endif 43 44#ifndef DEFAULT_ARCH 45#define DEFAULT_ARCH "i386" 46#endif 47 48#ifndef INLINE 49#if __GNUC__ >= 2 50#define INLINE __inline__ 51#else 52#define INLINE 53#endif 54#endif 55 56/* Prefixes will be emitted in the order defined below. 57 WAIT_PREFIX must be the first prefix since FWAIT is really is an 58 instruction, and so must come before any prefixes. 59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX, 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */ 61#define WAIT_PREFIX 0 62#define SEG_PREFIX 1 63#define ADDR_PREFIX 2 64#define DATA_PREFIX 3 65#define REP_PREFIX 4 66#define HLE_PREFIX REP_PREFIX 67#define BND_PREFIX REP_PREFIX 68#define LOCK_PREFIX 5 69#define REX_PREFIX 6 /* must come last. */ 70#define MAX_PREFIXES 7 /* max prefixes per opcode */ 71 72/* we define the syntax here (modulo base,index,scale syntax) */ 73#define REGISTER_PREFIX '%' 74#define IMMEDIATE_PREFIX '$' 75#define ABSOLUTE_PREFIX '*' 76 77/* these are the instruction mnemonic suffixes in AT&T syntax or 78 memory operand size in Intel syntax. */ 79#define WORD_MNEM_SUFFIX 'w' 80#define BYTE_MNEM_SUFFIX 'b' 81#define SHORT_MNEM_SUFFIX 's' 82#define LONG_MNEM_SUFFIX 'l' 83#define QWORD_MNEM_SUFFIX 'q' 84#define XMMWORD_MNEM_SUFFIX 'x' 85#define YMMWORD_MNEM_SUFFIX 'y' 86#define ZMMWORD_MNEM_SUFFIX 'z' 87/* Intel Syntax. Use a non-ascii letter since since it never appears 88 in instructions. */ 89#define LONG_DOUBLE_MNEM_SUFFIX '\1' 90 91#define END_OF_INSN '\0' 92 93/* 94 'templates' is for grouping together 'template' structures for opcodes 95 of the same name. This is only used for storing the insns in the grand 96 ole hash table of insns. 97 The templates themselves start at START and range up to (but not including) 98 END. 99 */ 100typedef struct 101{ 102 const insn_template *start; 103 const insn_template *end; 104} 105templates; 106 107/* 386 operand encoding bytes: see 386 book for details of this. */ 108typedef struct 109{ 110 unsigned int regmem; /* codes register or memory operand */ 111 unsigned int reg; /* codes register operand (or extended opcode) */ 112 unsigned int mode; /* how to interpret regmem & reg */ 113} 114modrm_byte; 115 116/* x86-64 extension prefix. */ 117typedef int rex_byte; 118 119/* 386 opcode byte to code indirect addressing. */ 120typedef struct 121{ 122 unsigned base; 123 unsigned index; 124 unsigned scale; 125} 126sib_byte; 127 128/* x86 arch names, types and features */ 129typedef struct 130{ 131 const char *name; /* arch name */ 132 unsigned int len; /* arch string length */ 133 enum processor_type type; /* arch type */ 134 i386_cpu_flags flags; /* cpu feature flags */ 135 unsigned int skip; /* show_arch should skip this. */ 136} 137arch_entry; 138 139/* Used to turn off indicated flags. */ 140typedef struct 141{ 142 const char *name; /* arch name */ 143 unsigned int len; /* arch string length */ 144 i386_cpu_flags flags; /* cpu feature flags */ 145} 146noarch_entry; 147 148static void update_code_flag (int, int); 149static void set_code_flag (int); 150static void set_16bit_gcc_code_flag (int); 151static void set_intel_syntax (int); 152static void set_intel_mnemonic (int); 153static void set_allow_index_reg (int); 154static void set_check (int); 155static void set_cpu_arch (int); 156#ifdef TE_PE 157static void pe_directive_secrel (int); 158#endif 159static void signed_cons (int); 160static char *output_invalid (int c); 161static int i386_finalize_immediate (segT, expressionS *, i386_operand_type, 162 const char *); 163static int i386_finalize_displacement (segT, expressionS *, i386_operand_type, 164 const char *); 165static int i386_att_operand (char *); 166static int i386_intel_operand (char *, int); 167static int i386_intel_simplify (expressionS *); 168static int i386_intel_parse_name (const char *, expressionS *); 169static const reg_entry *parse_register (char *, char **); 170static char *parse_insn (char *, char *); 171static char *parse_operands (char *, const char *); 172static void swap_operands (void); 173static void swap_2_operands (int, int); 174static void optimize_imm (void); 175static void optimize_disp (void); 176static const insn_template *match_template (char); 177static int check_string (void); 178static int process_suffix (void); 179static int check_byte_reg (void); 180static int check_long_reg (void); 181static int check_qword_reg (void); 182static int check_word_reg (void); 183static int finalize_imm (void); 184static int process_operands (void); 185static const seg_entry *build_modrm_byte (void); 186static void output_insn (void); 187static void output_imm (fragS *, offsetT); 188static void output_disp (fragS *, offsetT); 189#ifndef I386COFF 190static void s_bss (int); 191#endif 192#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 193static void handle_large_common (int small ATTRIBUTE_UNUSED); 194#endif 195 196static const char *default_arch = DEFAULT_ARCH; 197 198/* This struct describes rounding control and SAE in the instruction. */ 199struct RC_Operation 200{ 201 enum rc_type 202 { 203 rne = 0, 204 rd, 205 ru, 206 rz, 207 saeonly 208 } type; 209 int operand; 210}; 211 212static struct RC_Operation rc_op; 213 214/* The struct describes masking, applied to OPERAND in the instruction. 215 MASK is a pointer to the corresponding mask register. ZEROING tells 216 whether merging or zeroing mask is used. */ 217struct Mask_Operation 218{ 219 const reg_entry *mask; 220 unsigned int zeroing; 221 /* The operand where this operation is associated. */ 222 int operand; 223}; 224 225static struct Mask_Operation mask_op; 226 227/* The struct describes broadcasting, applied to OPERAND. FACTOR is 228 broadcast factor. */ 229struct Broadcast_Operation 230{ 231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */ 232 int type; 233 234 /* Index of broadcasted operand. */ 235 int operand; 236}; 237 238static struct Broadcast_Operation broadcast_op; 239 240/* VEX prefix. */ 241typedef struct 242{ 243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */ 244 unsigned char bytes[4]; 245 unsigned int length; 246 /* Destination or source register specifier. */ 247 const reg_entry *register_specifier; 248} vex_prefix; 249 250/* 'md_assemble ()' gathers together information and puts it into a 251 i386_insn. */ 252 253union i386_op 254 { 255 expressionS *disps; 256 expressionS *imms; 257 const reg_entry *regs; 258 }; 259 260enum i386_error 261 { 262 operand_size_mismatch, 263 operand_type_mismatch, 264 register_type_mismatch, 265 number_of_operands_mismatch, 266 invalid_instruction_suffix, 267 bad_imm4, 268 old_gcc_only, 269 unsupported_with_intel_mnemonic, 270 unsupported_syntax, 271 unsupported, 272 invalid_vsib_address, 273 invalid_vector_register_set, 274 unsupported_vector_index_register, 275 unsupported_broadcast, 276 broadcast_not_on_src_operand, 277 broadcast_needed, 278 unsupported_masking, 279 mask_not_on_destination, 280 no_default_mask, 281 unsupported_rc_sae, 282 rc_sae_operand_not_last_imm, 283 invalid_register_operand, 284 try_vector_disp8 285 }; 286 287struct _i386_insn 288 { 289 /* TM holds the template for the insn were currently assembling. */ 290 insn_template tm; 291 292 /* SUFFIX holds the instruction size suffix for byte, word, dword 293 or qword, if given. */ 294 char suffix; 295 296 /* OPERANDS gives the number of given operands. */ 297 unsigned int operands; 298 299 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number 300 of given register, displacement, memory operands and immediate 301 operands. */ 302 unsigned int reg_operands, disp_operands, mem_operands, imm_operands; 303 304 /* TYPES [i] is the type (see above #defines) which tells us how to 305 use OP[i] for the corresponding operand. */ 306 i386_operand_type types[MAX_OPERANDS]; 307 308 /* Displacement expression, immediate expression, or register for each 309 operand. */ 310 union i386_op op[MAX_OPERANDS]; 311 312 /* Flags for operands. */ 313 unsigned int flags[MAX_OPERANDS]; 314#define Operand_PCrel 1 315 316 /* Relocation type for operand */ 317 enum bfd_reloc_code_real reloc[MAX_OPERANDS]; 318 319 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode 320 the base index byte below. */ 321 const reg_entry *base_reg; 322 const reg_entry *index_reg; 323 unsigned int log2_scale_factor; 324 325 /* SEG gives the seg_entries of this insn. They are zero unless 326 explicit segment overrides are given. */ 327 const seg_entry *seg[2]; 328 329 /* Copied first memory operand string, for re-checking. */ 330 char *memop1_string; 331 332 /* PREFIX holds all the given prefix opcodes (usually null). 333 PREFIXES is the number of prefix opcodes. */ 334 unsigned int prefixes; 335 unsigned char prefix[MAX_PREFIXES]; 336 337 /* RM and SIB are the modrm byte and the sib byte where the 338 addressing modes of this insn are encoded. */ 339 modrm_byte rm; 340 rex_byte rex; 341 rex_byte vrex; 342 sib_byte sib; 343 vex_prefix vex; 344 345 /* Masking attributes. */ 346 struct Mask_Operation *mask; 347 348 /* Rounding control and SAE attributes. */ 349 struct RC_Operation *rounding; 350 351 /* Broadcasting attributes. */ 352 struct Broadcast_Operation *broadcast; 353 354 /* Compressed disp8*N attribute. */ 355 unsigned int memshift; 356 357 /* Swap operand in encoding. */ 358 unsigned int swap_operand; 359 360 /* Prefer 8bit or 32bit displacement in encoding. */ 361 enum 362 { 363 disp_encoding_default = 0, 364 disp_encoding_8bit, 365 disp_encoding_32bit 366 } disp_encoding; 367 368 /* REP prefix. */ 369 const char *rep_prefix; 370 371 /* HLE prefix. */ 372 const char *hle_prefix; 373 374 /* Have BND prefix. */ 375 const char *bnd_prefix; 376 377 /* Need VREX to support upper 16 registers. */ 378 int need_vrex; 379 380 /* Error message. */ 381 enum i386_error error; 382 }; 383 384typedef struct _i386_insn i386_insn; 385 386/* Link RC type with corresponding string, that'll be looked for in 387 asm. */ 388struct RC_name 389{ 390 enum rc_type type; 391 const char *name; 392 unsigned int len; 393}; 394 395static const struct RC_name RC_NamesTable[] = 396{ 397 { rne, STRING_COMMA_LEN ("rn-sae") }, 398 { rd, STRING_COMMA_LEN ("rd-sae") }, 399 { ru, STRING_COMMA_LEN ("ru-sae") }, 400 { rz, STRING_COMMA_LEN ("rz-sae") }, 401 { saeonly, STRING_COMMA_LEN ("sae") }, 402}; 403 404/* List of chars besides those in app.c:symbol_chars that can start an 405 operand. Used to prevent the scrubber eating vital white-space. */ 406const char extra_symbol_chars[] = "*%-([{" 407#ifdef LEX_AT 408 "@" 409#endif 410#ifdef LEX_QM 411 "?" 412#endif 413 ; 414 415#if (defined (TE_I386AIX) \ 416 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ 417 && !defined (TE_GNU) \ 418 && !defined (TE_LINUX) \ 419 && !defined (TE_NACL) \ 420 && !defined (TE_NETWARE) \ 421 && !defined (TE_FreeBSD) \ 422 && !defined (TE_DragonFly) \ 423 && !defined (TE_NetBSD) \ 424 && !defined (TE_BeOS))) 425/* This array holds the chars that always start a comment. If the 426 pre-processor is disabled, these aren't very useful. The option 427 --divide will remove '/' from this list. */ 428const char *i386_comment_chars = "#/"; 429#define SVR4_COMMENT_CHARS 1 430#define PREFIX_SEPARATOR '\\' 431 432#else 433const char *i386_comment_chars = "#"; 434#define PREFIX_SEPARATOR '/' 435#endif 436 437/* This array holds the chars that only start a comment at the beginning of 438 a line. If the line seems to have the form '# 123 filename' 439 .line and .file directives will appear in the pre-processed output. 440 Note that input_file.c hand checks for '#' at the beginning of the 441 first line of the input file. This is because the compiler outputs 442 #NO_APP at the beginning of its output. 443 Also note that comments started like this one will always work if 444 '/' isn't otherwise defined. */ 445const char line_comment_chars[] = "#/"; 446 447const char line_separator_chars[] = ";"; 448 449/* Chars that can be used to separate mant from exp in floating point 450 nums. */ 451const char EXP_CHARS[] = "eE"; 452 453/* Chars that mean this number is a floating point constant 454 As in 0f12.456 455 or 0d1.2345e12. */ 456const char FLT_CHARS[] = "fFdDxX"; 457 458/* Tables for lexical analysis. */ 459static char mnemonic_chars[256]; 460static char register_chars[256]; 461static char operand_chars[256]; 462static char identifier_chars[256]; 463static char digit_chars[256]; 464 465/* Lexical macros. */ 466#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) 467#define is_operand_char(x) (operand_chars[(unsigned char) x]) 468#define is_register_char(x) (register_chars[(unsigned char) x]) 469#define is_space_char(x) ((x) == ' ') 470#define is_identifier_char(x) (identifier_chars[(unsigned char) x]) 471#define is_digit_char(x) (digit_chars[(unsigned char) x]) 472 473/* All non-digit non-letter characters that may occur in an operand. */ 474static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; 475 476/* md_assemble() always leaves the strings it's passed unaltered. To 477 effect this we maintain a stack of saved characters that we've smashed 478 with '\0's (indicating end of strings for various sub-fields of the 479 assembler instruction). */ 480static char save_stack[32]; 481static char *save_stack_p; 482#define END_STRING_AND_SAVE(s) \ 483 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) 484#define RESTORE_END_STRING(s) \ 485 do { *(s) = *--save_stack_p; } while (0) 486 487/* The instruction we're assembling. */ 488static i386_insn i; 489 490/* Possible templates for current insn. */ 491static const templates *current_templates; 492 493/* Per instruction expressionS buffers: max displacements & immediates. */ 494static expressionS disp_expressions[MAX_MEMORY_OPERANDS]; 495static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS]; 496 497/* Current operand we are working on. */ 498static int this_operand = -1; 499 500/* We support four different modes. FLAG_CODE variable is used to distinguish 501 these. */ 502 503enum flag_code { 504 CODE_32BIT, 505 CODE_16BIT, 506 CODE_64BIT }; 507 508static enum flag_code flag_code; 509static unsigned int object_64bit; 510static unsigned int disallow_64bit_reloc; 511static int use_rela_relocations = 0; 512 513#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ 514 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ 515 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) 516 517/* The ELF ABI to use. */ 518enum x86_elf_abi 519{ 520 I386_ABI, 521 X86_64_ABI, 522 X86_64_X32_ABI 523}; 524 525static enum x86_elf_abi x86_elf_abi = I386_ABI; 526#endif 527 528#if defined (TE_PE) || defined (TE_PEP) 529/* Use big object file format. */ 530static int use_big_obj = 0; 531#endif 532 533#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 534/* 1 if generating code for a shared library. */ 535static int shared = 0; 536#endif 537 538/* 1 for intel syntax, 539 0 if att syntax. */ 540static int intel_syntax = 0; 541 542/* 1 for Intel64 ISA, 543 0 if AMD64 ISA. */ 544static int intel64; 545 546/* 1 for intel mnemonic, 547 0 if att mnemonic. */ 548static int intel_mnemonic = !SYSV386_COMPAT; 549 550/* 1 if support old (<= 2.8.1) versions of gcc. */ 551static int old_gcc = OLDGCC_COMPAT; 552 553/* 1 if pseudo registers are permitted. */ 554static int allow_pseudo_reg = 0; 555 556/* 1 if register prefix % not required. */ 557static int allow_naked_reg = 0; 558 559/* 1 if the assembler should add BND prefix for all control-tranferring 560 instructions supporting it, even if this prefix wasn't specified 561 explicitly. */ 562static int add_bnd_prefix = 0; 563 564/* 1 if pseudo index register, eiz/riz, is allowed . */ 565static int allow_index_reg = 0; 566 567/* 1 if the assembler should ignore LOCK prefix, even if it was 568 specified explicitly. */ 569static int omit_lock_prefix = 0; 570 571/* 1 if the assembler should encode lfence, mfence, and sfence as 572 "lock addl $0, (%{re}sp)". */ 573static int avoid_fence = 0; 574 575/* 1 if the assembler should generate relax relocations. */ 576 577static int generate_relax_relocations 578 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS; 579 580static enum check_kind 581 { 582 check_none = 0, 583 check_warning, 584 check_error 585 } 586sse_check, operand_check = check_warning; 587 588/* Register prefix used for error message. */ 589static const char *register_prefix = "%"; 590 591/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, 592 leave, push, and pop instructions so that gcc has the same stack 593 frame as in 32 bit mode. */ 594static char stackop_size = '\0'; 595 596/* Non-zero to optimize code alignment. */ 597int optimize_align_code = 1; 598 599/* Non-zero to quieten some warnings. */ 600static int quiet_warnings = 0; 601 602/* CPU name. */ 603static const char *cpu_arch_name = NULL; 604static char *cpu_sub_arch_name = NULL; 605 606/* CPU feature flags. */ 607static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS; 608 609/* If we have selected a cpu we are generating instructions for. */ 610static int cpu_arch_tune_set = 0; 611 612/* Cpu we are generating instructions for. */ 613enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN; 614 615/* CPU feature flags of cpu we are generating instructions for. */ 616static i386_cpu_flags cpu_arch_tune_flags; 617 618/* CPU instruction set architecture used. */ 619enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN; 620 621/* CPU feature flags of instruction set architecture used. */ 622i386_cpu_flags cpu_arch_isa_flags; 623 624/* If set, conditional jumps are not automatically promoted to handle 625 larger than a byte offset. */ 626static unsigned int no_cond_jump_promotion = 0; 627 628/* Encode SSE instructions with VEX prefix. */ 629static unsigned int sse2avx; 630 631/* Encode scalar AVX instructions with specific vector length. */ 632static enum 633 { 634 vex128 = 0, 635 vex256 636 } avxscalar; 637 638/* Encode scalar EVEX LIG instructions with specific vector length. */ 639static enum 640 { 641 evexl128 = 0, 642 evexl256, 643 evexl512 644 } evexlig; 645 646/* Encode EVEX WIG instructions with specific evex.w. */ 647static enum 648 { 649 evexw0 = 0, 650 evexw1 651 } evexwig; 652 653/* Value to encode in EVEX RC bits, for SAE-only instructions. */ 654static enum rc_type evexrcig = rne; 655 656/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ 657static symbolS *GOT_symbol; 658 659/* The dwarf2 return column, adjusted for 32 or 64 bit. */ 660unsigned int x86_dwarf2_return_column; 661 662/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ 663int x86_cie_data_alignment; 664 665/* Interface to relax_segment. 666 There are 3 major relax states for 386 jump insns because the 667 different types of jumps add different sizes to frags when we're 668 figuring out what sort of jump to choose to reach a given label. */ 669 670/* Types. */ 671#define UNCOND_JUMP 0 672#define COND_JUMP 1 673#define COND_JUMP86 2 674 675/* Sizes. */ 676#define CODE16 1 677#define SMALL 0 678#define SMALL16 (SMALL | CODE16) 679#define BIG 2 680#define BIG16 (BIG | CODE16) 681 682#ifndef INLINE 683#ifdef __GNUC__ 684#define INLINE __inline__ 685#else 686#define INLINE 687#endif 688#endif 689 690#define ENCODE_RELAX_STATE(type, size) \ 691 ((relax_substateT) (((type) << 2) | (size))) 692#define TYPE_FROM_RELAX_STATE(s) \ 693 ((s) >> 2) 694#define DISP_SIZE_FROM_RELAX_STATE(s) \ 695 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) 696 697/* This table is used by relax_frag to promote short jumps to long 698 ones where necessary. SMALL (short) jumps may be promoted to BIG 699 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We 700 don't allow a short jump in a 32 bit code segment to be promoted to 701 a 16 bit offset jump because it's slower (requires data size 702 prefix), and doesn't work, unless the destination is in the bottom 703 64k of the code segment (The top 16 bits of eip are zeroed). */ 704 705const relax_typeS md_relax_table[] = 706{ 707 /* The fields are: 708 1) most positive reach of this state, 709 2) most negative reach of this state, 710 3) how many bytes this mode will have in the variable part of the frag 711 4) which index into the table to try if we can't fit into this one. */ 712 713 /* UNCOND_JUMP states. */ 714 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, 715 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, 716 /* dword jmp adds 4 bytes to frag: 717 0 extra opcode bytes, 4 displacement bytes. */ 718 {0, 0, 4, 0}, 719 /* word jmp adds 2 byte2 to frag: 720 0 extra opcode bytes, 2 displacement bytes. */ 721 {0, 0, 2, 0}, 722 723 /* COND_JUMP states. */ 724 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, 725 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, 726 /* dword conditionals adds 5 bytes to frag: 727 1 extra opcode byte, 4 displacement bytes. */ 728 {0, 0, 5, 0}, 729 /* word conditionals add 3 bytes to frag: 730 1 extra opcode byte, 2 displacement bytes. */ 731 {0, 0, 3, 0}, 732 733 /* COND_JUMP86 states. */ 734 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, 735 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, 736 /* dword conditionals adds 5 bytes to frag: 737 1 extra opcode byte, 4 displacement bytes. */ 738 {0, 0, 5, 0}, 739 /* word conditionals add 4 bytes to frag: 740 1 displacement byte and a 3 byte long branch insn. */ 741 {0, 0, 4, 0} 742}; 743 744static const arch_entry cpu_arch[] = 745{ 746 /* Do not replace the first two entries - i386_target_format() 747 relies on them being there in this order. */ 748 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32, 749 CPU_GENERIC32_FLAGS, 0 }, 750 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64, 751 CPU_GENERIC64_FLAGS, 0 }, 752 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN, 753 CPU_NONE_FLAGS, 0 }, 754 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN, 755 CPU_I186_FLAGS, 0 }, 756 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN, 757 CPU_I286_FLAGS, 0 }, 758 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386, 759 CPU_I386_FLAGS, 0 }, 760 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486, 761 CPU_I486_FLAGS, 0 }, 762 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM, 763 CPU_I586_FLAGS, 0 }, 764 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO, 765 CPU_I686_FLAGS, 0 }, 766 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM, 767 CPU_I586_FLAGS, 0 }, 768 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO, 769 CPU_PENTIUMPRO_FLAGS, 0 }, 770 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO, 771 CPU_P2_FLAGS, 0 }, 772 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO, 773 CPU_P3_FLAGS, 0 }, 774 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4, 775 CPU_P4_FLAGS, 0 }, 776 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA, 777 CPU_CORE_FLAGS, 0 }, 778 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA, 779 CPU_NOCONA_FLAGS, 0 }, 780 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE, 781 CPU_CORE_FLAGS, 1 }, 782 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE, 783 CPU_CORE_FLAGS, 0 }, 784 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2, 785 CPU_CORE2_FLAGS, 1 }, 786 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2, 787 CPU_CORE2_FLAGS, 0 }, 788 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7, 789 CPU_COREI7_FLAGS, 0 }, 790 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM, 791 CPU_L1OM_FLAGS, 0 }, 792 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM, 793 CPU_K1OM_FLAGS, 0 }, 794 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU, 795 CPU_IAMCU_FLAGS, 0 }, 796 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6, 797 CPU_K6_FLAGS, 0 }, 798 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6, 799 CPU_K6_2_FLAGS, 0 }, 800 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON, 801 CPU_ATHLON_FLAGS, 0 }, 802 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8, 803 CPU_K8_FLAGS, 1 }, 804 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8, 805 CPU_K8_FLAGS, 0 }, 806 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8, 807 CPU_K8_FLAGS, 0 }, 808 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10, 809 CPU_AMDFAM10_FLAGS, 0 }, 810 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD, 811 CPU_BDVER1_FLAGS, 0 }, 812 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD, 813 CPU_BDVER2_FLAGS, 0 }, 814 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD, 815 CPU_BDVER3_FLAGS, 0 }, 816 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD, 817 CPU_BDVER4_FLAGS, 0 }, 818 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER, 819 CPU_ZNVER1_FLAGS, 0 }, 820 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT, 821 CPU_BTVER1_FLAGS, 0 }, 822 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT, 823 CPU_BTVER2_FLAGS, 0 }, 824 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN, 825 CPU_8087_FLAGS, 0 }, 826 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN, 827 CPU_287_FLAGS, 0 }, 828 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN, 829 CPU_387_FLAGS, 0 }, 830 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN, 831 CPU_687_FLAGS, 0 }, 832 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN, 833 CPU_MMX_FLAGS, 0 }, 834 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN, 835 CPU_SSE_FLAGS, 0 }, 836 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN, 837 CPU_SSE2_FLAGS, 0 }, 838 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN, 839 CPU_SSE3_FLAGS, 0 }, 840 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN, 841 CPU_SSSE3_FLAGS, 0 }, 842 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN, 843 CPU_SSE4_1_FLAGS, 0 }, 844 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN, 845 CPU_SSE4_2_FLAGS, 0 }, 846 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN, 847 CPU_SSE4_2_FLAGS, 0 }, 848 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN, 849 CPU_AVX_FLAGS, 0 }, 850 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN, 851 CPU_AVX2_FLAGS, 0 }, 852 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN, 853 CPU_AVX512F_FLAGS, 0 }, 854 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN, 855 CPU_AVX512CD_FLAGS, 0 }, 856 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN, 857 CPU_AVX512ER_FLAGS, 0 }, 858 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN, 859 CPU_AVX512PF_FLAGS, 0 }, 860 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN, 861 CPU_AVX512DQ_FLAGS, 0 }, 862 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN, 863 CPU_AVX512BW_FLAGS, 0 }, 864 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN, 865 CPU_AVX512VL_FLAGS, 0 }, 866 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN, 867 CPU_VMX_FLAGS, 0 }, 868 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN, 869 CPU_VMFUNC_FLAGS, 0 }, 870 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN, 871 CPU_SMX_FLAGS, 0 }, 872 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN, 873 CPU_XSAVE_FLAGS, 0 }, 874 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN, 875 CPU_XSAVEOPT_FLAGS, 0 }, 876 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN, 877 CPU_XSAVEC_FLAGS, 0 }, 878 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN, 879 CPU_XSAVES_FLAGS, 0 }, 880 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN, 881 CPU_AES_FLAGS, 0 }, 882 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN, 883 CPU_PCLMUL_FLAGS, 0 }, 884 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN, 885 CPU_PCLMUL_FLAGS, 1 }, 886 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN, 887 CPU_FSGSBASE_FLAGS, 0 }, 888 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN, 889 CPU_RDRND_FLAGS, 0 }, 890 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN, 891 CPU_F16C_FLAGS, 0 }, 892 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN, 893 CPU_BMI2_FLAGS, 0 }, 894 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN, 895 CPU_FMA_FLAGS, 0 }, 896 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN, 897 CPU_FMA4_FLAGS, 0 }, 898 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN, 899 CPU_XOP_FLAGS, 0 }, 900 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN, 901 CPU_LWP_FLAGS, 0 }, 902 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN, 903 CPU_MOVBE_FLAGS, 0 }, 904 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN, 905 CPU_CX16_FLAGS, 0 }, 906 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN, 907 CPU_EPT_FLAGS, 0 }, 908 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN, 909 CPU_LZCNT_FLAGS, 0 }, 910 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN, 911 CPU_HLE_FLAGS, 0 }, 912 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN, 913 CPU_RTM_FLAGS, 0 }, 914 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN, 915 CPU_INVPCID_FLAGS, 0 }, 916 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN, 917 CPU_CLFLUSH_FLAGS, 0 }, 918 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN, 919 CPU_NOP_FLAGS, 0 }, 920 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN, 921 CPU_SYSCALL_FLAGS, 0 }, 922 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN, 923 CPU_RDTSCP_FLAGS, 0 }, 924 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN, 925 CPU_3DNOW_FLAGS, 0 }, 926 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN, 927 CPU_3DNOWA_FLAGS, 0 }, 928 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN, 929 CPU_PADLOCK_FLAGS, 0 }, 930 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN, 931 CPU_SVME_FLAGS, 1 }, 932 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN, 933 CPU_SVME_FLAGS, 0 }, 934 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN, 935 CPU_SSE4A_FLAGS, 0 }, 936 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN, 937 CPU_ABM_FLAGS, 0 }, 938 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN, 939 CPU_BMI_FLAGS, 0 }, 940 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN, 941 CPU_TBM_FLAGS, 0 }, 942 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN, 943 CPU_ADX_FLAGS, 0 }, 944 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN, 945 CPU_RDSEED_FLAGS, 0 }, 946 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN, 947 CPU_PRFCHW_FLAGS, 0 }, 948 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN, 949 CPU_SMAP_FLAGS, 0 }, 950 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN, 951 CPU_MPX_FLAGS, 0 }, 952 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN, 953 CPU_SHA_FLAGS, 0 }, 954 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN, 955 CPU_CLFLUSHOPT_FLAGS, 0 }, 956 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN, 957 CPU_PREFETCHWT1_FLAGS, 0 }, 958 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN, 959 CPU_SE1_FLAGS, 0 }, 960 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN, 961 CPU_CLWB_FLAGS, 0 }, 962 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN, 963 CPU_AVX512IFMA_FLAGS, 0 }, 964 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN, 965 CPU_AVX512VBMI_FLAGS, 0 }, 966 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN, 967 CPU_AVX512_4FMAPS_FLAGS, 0 }, 968 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN, 969 CPU_AVX512_4VNNIW_FLAGS, 0 }, 970 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN, 971 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 }, 972 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN, 973 CPU_CLZERO_FLAGS, 0 }, 974 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN, 975 CPU_MWAITX_FLAGS, 0 }, 976 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN, 977 CPU_OSPKE_FLAGS, 0 }, 978 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN, 979 CPU_RDPID_FLAGS, 0 }, 980 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN, 981 CPU_PTWRITE_FLAGS, 0 }, 982}; 983 984static const noarch_entry cpu_noarch[] = 985{ 986 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS }, 987 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS }, 988 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS }, 989 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS }, 990 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS }, 991 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS }, 992 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS }, 993 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS }, 994 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS }, 995 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS }, 996 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS }, 997 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS }, 998 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS }, 999 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS }, 1000 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS }, 1001 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS }, 1002 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS }, 1003 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS }, 1004 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS }, 1005 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS }, 1006 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS }, 1007 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS }, 1008 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS }, 1009 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS }, 1010 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS }, 1011 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS }, 1012}; 1013 1014#ifdef I386COFF 1015/* Like s_lcomm_internal in gas/read.c but the alignment string 1016 is allowed to be optional. */ 1017 1018static symbolS * 1019pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size) 1020{ 1021 addressT align = 0; 1022 1023 SKIP_WHITESPACE (); 1024 1025 if (needs_align 1026 && *input_line_pointer == ',') 1027 { 1028 align = parse_align (needs_align - 1); 1029 1030 if (align == (addressT) -1) 1031 return NULL; 1032 } 1033 else 1034 { 1035 if (size >= 8) 1036 align = 3; 1037 else if (size >= 4) 1038 align = 2; 1039 else if (size >= 2) 1040 align = 1; 1041 else 1042 align = 0; 1043 } 1044 1045 bss_alloc (symbolP, size, align); 1046 return symbolP; 1047} 1048 1049static void 1050pe_lcomm (int needs_align) 1051{ 1052 s_comm_internal (needs_align * 2, pe_lcomm_internal); 1053} 1054#endif 1055 1056const pseudo_typeS md_pseudo_table[] = 1057{ 1058#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) 1059 {"align", s_align_bytes, 0}, 1060#else 1061 {"align", s_align_ptwo, 0}, 1062#endif 1063 {"arch", set_cpu_arch, 0}, 1064#ifndef I386COFF 1065 {"bss", s_bss, 0}, 1066#else 1067 {"lcomm", pe_lcomm, 1}, 1068#endif 1069 {"ffloat", float_cons, 'f'}, 1070 {"dfloat", float_cons, 'd'}, 1071 {"tfloat", float_cons, 'x'}, 1072 {"value", cons, 2}, 1073 {"slong", signed_cons, 4}, 1074 {"noopt", s_ignore, 0}, 1075 {"optim", s_ignore, 0}, 1076 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, 1077 {"code16", set_code_flag, CODE_16BIT}, 1078 {"code32", set_code_flag, CODE_32BIT}, 1079 {"code64", set_code_flag, CODE_64BIT}, 1080 {"intel_syntax", set_intel_syntax, 1}, 1081 {"att_syntax", set_intel_syntax, 0}, 1082 {"intel_mnemonic", set_intel_mnemonic, 1}, 1083 {"att_mnemonic", set_intel_mnemonic, 0}, 1084 {"allow_index_reg", set_allow_index_reg, 1}, 1085 {"disallow_index_reg", set_allow_index_reg, 0}, 1086 {"sse_check", set_check, 0}, 1087 {"operand_check", set_check, 1}, 1088#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 1089 {"largecomm", handle_large_common, 0}, 1090#else 1091 {"file", (void (*) (int)) dwarf2_directive_file, 0}, 1092 {"loc", dwarf2_directive_loc, 0}, 1093 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0}, 1094#endif 1095#ifdef TE_PE 1096 {"secrel32", pe_directive_secrel, 0}, 1097#endif 1098 {0, 0, 0} 1099}; 1100 1101/* For interface with expression (). */ 1102extern char *input_line_pointer; 1103 1104/* Hash table for instruction mnemonic lookup. */ 1105static struct hash_control *op_hash; 1106 1107/* Hash table for register lookup. */ 1108static struct hash_control *reg_hash; 1109 1110void 1111i386_align_code (fragS *fragP, int count) 1112{ 1113 /* Various efficient no-op patterns for aligning code labels. 1114 Note: Don't try to assemble the instructions in the comments. 1115 0L and 0w are not legal. */ 1116 static const unsigned char f32_1[] = 1117 {0x90}; /* nop */ 1118 static const unsigned char f32_2[] = 1119 {0x66,0x90}; /* xchg %ax,%ax */ 1120 static const unsigned char f32_3[] = 1121 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ 1122 static const unsigned char f32_4[] = 1123 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ 1124 static const unsigned char f32_5[] = 1125 {0x90, /* nop */ 1126 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ 1127 static const unsigned char f32_6[] = 1128 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ 1129 static const unsigned char f32_7[] = 1130 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ 1131 static const unsigned char f32_8[] = 1132 {0x90, /* nop */ 1133 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ 1134 static const unsigned char f32_9[] = 1135 {0x89,0xf6, /* movl %esi,%esi */ 1136 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ 1137 static const unsigned char f32_10[] = 1138 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */ 1139 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ 1140 static const unsigned char f32_11[] = 1141 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */ 1142 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ 1143 static const unsigned char f32_12[] = 1144 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ 1145 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */ 1146 static const unsigned char f32_13[] = 1147 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ 1148 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ 1149 static const unsigned char f32_14[] = 1150 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */ 1151 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ 1152 static const unsigned char f16_3[] = 1153 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */ 1154 static const unsigned char f16_4[] = 1155 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ 1156 static const unsigned char f16_5[] = 1157 {0x90, /* nop */ 1158 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ 1159 static const unsigned char f16_6[] = 1160 {0x89,0xf6, /* mov %si,%si */ 1161 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ 1162 static const unsigned char f16_7[] = 1163 {0x8d,0x74,0x00, /* lea 0(%si),%si */ 1164 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ 1165 static const unsigned char f16_8[] = 1166 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */ 1167 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ 1168 static const unsigned char jump_31[] = 1169 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */ 1170 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90, 1171 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90, 1172 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90}; 1173 static const unsigned char *const f32_patt[] = { 1174 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8, 1175 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14 1176 }; 1177 static const unsigned char *const f16_patt[] = { 1178 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8 1179 }; 1180 /* nopl (%[re]ax) */ 1181 static const unsigned char alt_3[] = 1182 {0x0f,0x1f,0x00}; 1183 /* nopl 0(%[re]ax) */ 1184 static const unsigned char alt_4[] = 1185 {0x0f,0x1f,0x40,0x00}; 1186 /* nopl 0(%[re]ax,%[re]ax,1) */ 1187 static const unsigned char alt_5[] = 1188 {0x0f,0x1f,0x44,0x00,0x00}; 1189 /* nopw 0(%[re]ax,%[re]ax,1) */ 1190 static const unsigned char alt_6[] = 1191 {0x66,0x0f,0x1f,0x44,0x00,0x00}; 1192 /* nopl 0L(%[re]ax) */ 1193 static const unsigned char alt_7[] = 1194 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; 1195 /* nopl 0L(%[re]ax,%[re]ax,1) */ 1196 static const unsigned char alt_8[] = 1197 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; 1198 /* nopw 0L(%[re]ax,%[re]ax,1) */ 1199 static const unsigned char alt_9[] = 1200 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; 1201 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */ 1202 static const unsigned char alt_10[] = 1203 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; 1204 static const unsigned char *const alt_patt[] = { 1205 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, 1206 alt_9, alt_10 1207 }; 1208 1209 /* Only align for at least a positive non-zero boundary. */ 1210 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE) 1211 return; 1212 1213 /* We need to decide which NOP sequence to use for 32bit and 1214 64bit. When -mtune= is used: 1215 1216 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and 1217 PROCESSOR_GENERIC32, f32_patt will be used. 1218 2. For the rest, alt_patt will be used. 1219 1220 When -mtune= isn't used, alt_patt will be used if 1221 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will 1222 be used. 1223 1224 When -march= or .arch is used, we can't use anything beyond 1225 cpu_arch_isa_flags. */ 1226 1227 if (flag_code == CODE_16BIT) 1228 { 1229 if (count > 8) 1230 { 1231 memcpy (fragP->fr_literal + fragP->fr_fix, 1232 jump_31, count); 1233 /* Adjust jump offset. */ 1234 fragP->fr_literal[fragP->fr_fix + 1] = count - 2; 1235 } 1236 else 1237 memcpy (fragP->fr_literal + fragP->fr_fix, 1238 f16_patt[count - 1], count); 1239 } 1240 else 1241 { 1242 const unsigned char *const *patt = NULL; 1243 1244 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN) 1245 { 1246 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */ 1247 switch (cpu_arch_tune) 1248 { 1249 case PROCESSOR_UNKNOWN: 1250 /* We use cpu_arch_isa_flags to check if we SHOULD 1251 optimize with nops. */ 1252 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) 1253 patt = alt_patt; 1254 else 1255 patt = f32_patt; 1256 break; 1257 case PROCESSOR_PENTIUM4: 1258 case PROCESSOR_NOCONA: 1259 case PROCESSOR_CORE: 1260 case PROCESSOR_CORE2: 1261 case PROCESSOR_COREI7: 1262 case PROCESSOR_L1OM: 1263 case PROCESSOR_K1OM: 1264 case PROCESSOR_GENERIC64: 1265 case PROCESSOR_K6: 1266 case PROCESSOR_ATHLON: 1267 case PROCESSOR_K8: 1268 case PROCESSOR_AMDFAM10: 1269 case PROCESSOR_BD: 1270 case PROCESSOR_ZNVER: 1271 case PROCESSOR_BT: 1272 patt = alt_patt; 1273 break; 1274 case PROCESSOR_I386: 1275 case PROCESSOR_I486: 1276 case PROCESSOR_PENTIUM: 1277 case PROCESSOR_PENTIUMPRO: 1278 case PROCESSOR_IAMCU: 1279 case PROCESSOR_GENERIC32: 1280 patt = f32_patt; 1281 break; 1282 } 1283 } 1284 else 1285 { 1286 switch (fragP->tc_frag_data.tune) 1287 { 1288 case PROCESSOR_UNKNOWN: 1289 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be 1290 PROCESSOR_UNKNOWN. */ 1291 abort (); 1292 break; 1293 1294 case PROCESSOR_I386: 1295 case PROCESSOR_I486: 1296 case PROCESSOR_PENTIUM: 1297 case PROCESSOR_IAMCU: 1298 case PROCESSOR_K6: 1299 case PROCESSOR_ATHLON: 1300 case PROCESSOR_K8: 1301 case PROCESSOR_AMDFAM10: 1302 case PROCESSOR_BD: 1303 case PROCESSOR_ZNVER: 1304 case PROCESSOR_BT: 1305 case PROCESSOR_GENERIC32: 1306 /* We use cpu_arch_isa_flags to check if we CAN optimize 1307 with nops. */ 1308 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) 1309 patt = alt_patt; 1310 else 1311 patt = f32_patt; 1312 break; 1313 case PROCESSOR_PENTIUMPRO: 1314 case PROCESSOR_PENTIUM4: 1315 case PROCESSOR_NOCONA: 1316 case PROCESSOR_CORE: 1317 case PROCESSOR_CORE2: 1318 case PROCESSOR_COREI7: 1319 case PROCESSOR_L1OM: 1320 case PROCESSOR_K1OM: 1321 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) 1322 patt = alt_patt; 1323 else 1324 patt = f32_patt; 1325 break; 1326 case PROCESSOR_GENERIC64: 1327 patt = alt_patt; 1328 break; 1329 } 1330 } 1331 1332 if (patt == f32_patt) 1333 { 1334 /* If the padding is less than 15 bytes, we use the normal 1335 ones. Otherwise, we use a jump instruction and adjust 1336 its offset. */ 1337 int limit; 1338 1339 /* For 64bit, the limit is 3 bytes. */ 1340 if (flag_code == CODE_64BIT 1341 && fragP->tc_frag_data.isa_flags.bitfield.cpulm) 1342 limit = 3; 1343 else 1344 limit = 15; 1345 if (count < limit) 1346 memcpy (fragP->fr_literal + fragP->fr_fix, 1347 patt[count - 1], count); 1348 else 1349 { 1350 memcpy (fragP->fr_literal + fragP->fr_fix, 1351 jump_31, count); 1352 /* Adjust jump offset. */ 1353 fragP->fr_literal[fragP->fr_fix + 1] = count - 2; 1354 } 1355 } 1356 else 1357 { 1358 /* Maximum length of an instruction is 10 byte. If the 1359 padding is greater than 10 bytes and we don't use jump, 1360 we have to break it into smaller pieces. */ 1361 int padding = count; 1362 while (padding > 10) 1363 { 1364 padding -= 10; 1365 memcpy (fragP->fr_literal + fragP->fr_fix + padding, 1366 patt [9], 10); 1367 } 1368 1369 if (padding) 1370 memcpy (fragP->fr_literal + fragP->fr_fix, 1371 patt [padding - 1], padding); 1372 } 1373 } 1374 fragP->fr_var = count; 1375} 1376 1377static INLINE int 1378operand_type_all_zero (const union i386_operand_type *x) 1379{ 1380 switch (ARRAY_SIZE(x->array)) 1381 { 1382 case 3: 1383 if (x->array[2]) 1384 return 0; 1385 /* Fall through. */ 1386 case 2: 1387 if (x->array[1]) 1388 return 0; 1389 /* Fall through. */ 1390 case 1: 1391 return !x->array[0]; 1392 default: 1393 abort (); 1394 } 1395} 1396 1397static INLINE void 1398operand_type_set (union i386_operand_type *x, unsigned int v) 1399{ 1400 switch (ARRAY_SIZE(x->array)) 1401 { 1402 case 3: 1403 x->array[2] = v; 1404 /* Fall through. */ 1405 case 2: 1406 x->array[1] = v; 1407 /* Fall through. */ 1408 case 1: 1409 x->array[0] = v; 1410 /* Fall through. */ 1411 break; 1412 default: 1413 abort (); 1414 } 1415} 1416 1417static INLINE int 1418operand_type_equal (const union i386_operand_type *x, 1419 const union i386_operand_type *y) 1420{ 1421 switch (ARRAY_SIZE(x->array)) 1422 { 1423 case 3: 1424 if (x->array[2] != y->array[2]) 1425 return 0; 1426 /* Fall through. */ 1427 case 2: 1428 if (x->array[1] != y->array[1]) 1429 return 0; 1430 /* Fall through. */ 1431 case 1: 1432 return x->array[0] == y->array[0]; 1433 break; 1434 default: 1435 abort (); 1436 } 1437} 1438 1439static INLINE int 1440cpu_flags_all_zero (const union i386_cpu_flags *x) 1441{ 1442 switch (ARRAY_SIZE(x->array)) 1443 { 1444 case 3: 1445 if (x->array[2]) 1446 return 0; 1447 /* Fall through. */ 1448 case 2: 1449 if (x->array[1]) 1450 return 0; 1451 /* Fall through. */ 1452 case 1: 1453 return !x->array[0]; 1454 default: 1455 abort (); 1456 } 1457} 1458 1459static INLINE int 1460cpu_flags_equal (const union i386_cpu_flags *x, 1461 const union i386_cpu_flags *y) 1462{ 1463 switch (ARRAY_SIZE(x->array)) 1464 { 1465 case 3: 1466 if (x->array[2] != y->array[2]) 1467 return 0; 1468 /* Fall through. */ 1469 case 2: 1470 if (x->array[1] != y->array[1]) 1471 return 0; 1472 /* Fall through. */ 1473 case 1: 1474 return x->array[0] == y->array[0]; 1475 break; 1476 default: 1477 abort (); 1478 } 1479} 1480 1481static INLINE int 1482cpu_flags_check_cpu64 (i386_cpu_flags f) 1483{ 1484 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64) 1485 || (flag_code != CODE_64BIT && f.bitfield.cpu64)); 1486} 1487 1488static INLINE i386_cpu_flags 1489cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y) 1490{ 1491 switch (ARRAY_SIZE (x.array)) 1492 { 1493 case 3: 1494 x.array [2] &= y.array [2]; 1495 /* Fall through. */ 1496 case 2: 1497 x.array [1] &= y.array [1]; 1498 /* Fall through. */ 1499 case 1: 1500 x.array [0] &= y.array [0]; 1501 break; 1502 default: 1503 abort (); 1504 } 1505 return x; 1506} 1507 1508static INLINE i386_cpu_flags 1509cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y) 1510{ 1511 switch (ARRAY_SIZE (x.array)) 1512 { 1513 case 3: 1514 x.array [2] |= y.array [2]; 1515 /* Fall through. */ 1516 case 2: 1517 x.array [1] |= y.array [1]; 1518 /* Fall through. */ 1519 case 1: 1520 x.array [0] |= y.array [0]; 1521 break; 1522 default: 1523 abort (); 1524 } 1525 return x; 1526} 1527 1528static INLINE i386_cpu_flags 1529cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y) 1530{ 1531 switch (ARRAY_SIZE (x.array)) 1532 { 1533 case 3: 1534 x.array [2] &= ~y.array [2]; 1535 /* Fall through. */ 1536 case 2: 1537 x.array [1] &= ~y.array [1]; 1538 /* Fall through. */ 1539 case 1: 1540 x.array [0] &= ~y.array [0]; 1541 break; 1542 default: 1543 abort (); 1544 } 1545 return x; 1546} 1547 1548#define CPU_FLAGS_ARCH_MATCH 0x1 1549#define CPU_FLAGS_64BIT_MATCH 0x2 1550#define CPU_FLAGS_AES_MATCH 0x4 1551#define CPU_FLAGS_PCLMUL_MATCH 0x8 1552#define CPU_FLAGS_AVX_MATCH 0x10 1553 1554#define CPU_FLAGS_32BIT_MATCH \ 1555 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \ 1556 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH) 1557#define CPU_FLAGS_PERFECT_MATCH \ 1558 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH) 1559 1560/* Return CPU flags match bits. */ 1561 1562static int 1563cpu_flags_match (const insn_template *t) 1564{ 1565 i386_cpu_flags x = t->cpu_flags; 1566 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0; 1567 1568 x.bitfield.cpu64 = 0; 1569 x.bitfield.cpuno64 = 0; 1570 1571 if (cpu_flags_all_zero (&x)) 1572 { 1573 /* This instruction is available on all archs. */ 1574 match |= CPU_FLAGS_32BIT_MATCH; 1575 } 1576 else 1577 { 1578 /* This instruction is available only on some archs. */ 1579 i386_cpu_flags cpu = cpu_arch_flags; 1580 1581 cpu = cpu_flags_and (x, cpu); 1582 if (!cpu_flags_all_zero (&cpu)) 1583 { 1584 if (x.bitfield.cpuavx) 1585 { 1586 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */ 1587 if (cpu.bitfield.cpuavx) 1588 { 1589 /* Check SSE2AVX. */ 1590 if (!t->opcode_modifier.sse2avx|| sse2avx) 1591 { 1592 match |= (CPU_FLAGS_ARCH_MATCH 1593 | CPU_FLAGS_AVX_MATCH); 1594 /* Check AES. */ 1595 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes) 1596 match |= CPU_FLAGS_AES_MATCH; 1597 /* Check PCLMUL. */ 1598 if (!x.bitfield.cpupclmul 1599 || cpu.bitfield.cpupclmul) 1600 match |= CPU_FLAGS_PCLMUL_MATCH; 1601 } 1602 } 1603 else 1604 match |= CPU_FLAGS_ARCH_MATCH; 1605 } 1606 else if (x.bitfield.cpuavx512vl) 1607 { 1608 /* Match AVX512VL. */ 1609 if (cpu.bitfield.cpuavx512vl) 1610 { 1611 /* Need another match. */ 1612 cpu.bitfield.cpuavx512vl = 0; 1613 if (!cpu_flags_all_zero (&cpu)) 1614 match |= CPU_FLAGS_32BIT_MATCH; 1615 else 1616 match |= CPU_FLAGS_ARCH_MATCH; 1617 } 1618 else 1619 match |= CPU_FLAGS_ARCH_MATCH; 1620 } 1621 else 1622 match |= CPU_FLAGS_32BIT_MATCH; 1623 } 1624 } 1625 return match; 1626} 1627 1628static INLINE i386_operand_type 1629operand_type_and (i386_operand_type x, i386_operand_type y) 1630{ 1631 switch (ARRAY_SIZE (x.array)) 1632 { 1633 case 3: 1634 x.array [2] &= y.array [2]; 1635 /* Fall through. */ 1636 case 2: 1637 x.array [1] &= y.array [1]; 1638 /* Fall through. */ 1639 case 1: 1640 x.array [0] &= y.array [0]; 1641 break; 1642 default: 1643 abort (); 1644 } 1645 return x; 1646} 1647 1648static INLINE i386_operand_type 1649operand_type_or (i386_operand_type x, i386_operand_type y) 1650{ 1651 switch (ARRAY_SIZE (x.array)) 1652 { 1653 case 3: 1654 x.array [2] |= y.array [2]; 1655 /* Fall through. */ 1656 case 2: 1657 x.array [1] |= y.array [1]; 1658 /* Fall through. */ 1659 case 1: 1660 x.array [0] |= y.array [0]; 1661 break; 1662 default: 1663 abort (); 1664 } 1665 return x; 1666} 1667 1668static INLINE i386_operand_type 1669operand_type_xor (i386_operand_type x, i386_operand_type y) 1670{ 1671 switch (ARRAY_SIZE (x.array)) 1672 { 1673 case 3: 1674 x.array [2] ^= y.array [2]; 1675 /* Fall through. */ 1676 case 2: 1677 x.array [1] ^= y.array [1]; 1678 /* Fall through. */ 1679 case 1: 1680 x.array [0] ^= y.array [0]; 1681 break; 1682 default: 1683 abort (); 1684 } 1685 return x; 1686} 1687 1688static const i386_operand_type acc32 = OPERAND_TYPE_ACC32; 1689static const i386_operand_type acc64 = OPERAND_TYPE_ACC64; 1690static const i386_operand_type control = OPERAND_TYPE_CONTROL; 1691static const i386_operand_type inoutportreg 1692 = OPERAND_TYPE_INOUTPORTREG; 1693static const i386_operand_type reg16_inoutportreg 1694 = OPERAND_TYPE_REG16_INOUTPORTREG; 1695static const i386_operand_type disp16 = OPERAND_TYPE_DISP16; 1696static const i386_operand_type disp32 = OPERAND_TYPE_DISP32; 1697static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S; 1698static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32; 1699static const i386_operand_type anydisp 1700 = OPERAND_TYPE_ANYDISP; 1701static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM; 1702static const i386_operand_type regymm = OPERAND_TYPE_REGYMM; 1703static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM; 1704static const i386_operand_type regmask = OPERAND_TYPE_REGMASK; 1705static const i386_operand_type imm8 = OPERAND_TYPE_IMM8; 1706static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S; 1707static const i386_operand_type imm16 = OPERAND_TYPE_IMM16; 1708static const i386_operand_type imm32 = OPERAND_TYPE_IMM32; 1709static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S; 1710static const i386_operand_type imm64 = OPERAND_TYPE_IMM64; 1711static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32; 1712static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S; 1713static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S; 1714static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4; 1715 1716enum operand_type 1717{ 1718 reg, 1719 imm, 1720 disp, 1721 anymem 1722}; 1723 1724static INLINE int 1725operand_type_check (i386_operand_type t, enum operand_type c) 1726{ 1727 switch (c) 1728 { 1729 case reg: 1730 return (t.bitfield.reg8 1731 || t.bitfield.reg16 1732 || t.bitfield.reg32 1733 || t.bitfield.reg64); 1734 1735 case imm: 1736 return (t.bitfield.imm8 1737 || t.bitfield.imm8s 1738 || t.bitfield.imm16 1739 || t.bitfield.imm32 1740 || t.bitfield.imm32s 1741 || t.bitfield.imm64); 1742 1743 case disp: 1744 return (t.bitfield.disp8 1745 || t.bitfield.disp16 1746 || t.bitfield.disp32 1747 || t.bitfield.disp32s 1748 || t.bitfield.disp64); 1749 1750 case anymem: 1751 return (t.bitfield.disp8 1752 || t.bitfield.disp16 1753 || t.bitfield.disp32 1754 || t.bitfield.disp32s 1755 || t.bitfield.disp64 1756 || t.bitfield.baseindex); 1757 1758 default: 1759 abort (); 1760 } 1761 1762 return 0; 1763} 1764 1765/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on 1766 operand J for instruction template T. */ 1767 1768static INLINE int 1769match_reg_size (const insn_template *t, unsigned int j) 1770{ 1771 return !((i.types[j].bitfield.byte 1772 && !t->operand_types[j].bitfield.byte) 1773 || (i.types[j].bitfield.word 1774 && !t->operand_types[j].bitfield.word) 1775 || (i.types[j].bitfield.dword 1776 && !t->operand_types[j].bitfield.dword) 1777 || (i.types[j].bitfield.qword 1778 && !t->operand_types[j].bitfield.qword)); 1779} 1780 1781/* Return 1 if there is no conflict in any size on operand J for 1782 instruction template T. */ 1783 1784static INLINE int 1785match_mem_size (const insn_template *t, unsigned int j) 1786{ 1787 return (match_reg_size (t, j) 1788 && !((i.types[j].bitfield.unspecified 1789 && !i.broadcast 1790 && !t->operand_types[j].bitfield.unspecified) 1791 || (i.types[j].bitfield.fword 1792 && !t->operand_types[j].bitfield.fword) 1793 || (i.types[j].bitfield.tbyte 1794 && !t->operand_types[j].bitfield.tbyte) 1795 || (i.types[j].bitfield.xmmword 1796 && !t->operand_types[j].bitfield.xmmword) 1797 || (i.types[j].bitfield.ymmword 1798 && !t->operand_types[j].bitfield.ymmword) 1799 || (i.types[j].bitfield.zmmword 1800 && !t->operand_types[j].bitfield.zmmword))); 1801} 1802 1803/* Return 1 if there is no size conflict on any operands for 1804 instruction template T. */ 1805 1806static INLINE int 1807operand_size_match (const insn_template *t) 1808{ 1809 unsigned int j; 1810 int match = 1; 1811 1812 /* Don't check jump instructions. */ 1813 if (t->opcode_modifier.jump 1814 || t->opcode_modifier.jumpbyte 1815 || t->opcode_modifier.jumpdword 1816 || t->opcode_modifier.jumpintersegment) 1817 return match; 1818 1819 /* Check memory and accumulator operand size. */ 1820 for (j = 0; j < i.operands; j++) 1821 { 1822 if (t->operand_types[j].bitfield.anysize) 1823 continue; 1824 1825 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j)) 1826 { 1827 match = 0; 1828 break; 1829 } 1830 1831 if (i.types[j].bitfield.mem && !match_mem_size (t, j)) 1832 { 1833 match = 0; 1834 break; 1835 } 1836 } 1837 1838 if (match) 1839 return match; 1840 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd) 1841 { 1842mismatch: 1843 i.error = operand_size_mismatch; 1844 return 0; 1845 } 1846 1847 /* Check reverse. */ 1848 gas_assert (i.operands == 2); 1849 1850 match = 1; 1851 for (j = 0; j < 2; j++) 1852 { 1853 if (t->operand_types[j].bitfield.acc 1854 && !match_reg_size (t, j ? 0 : 1)) 1855 goto mismatch; 1856 1857 if (i.types[j].bitfield.mem 1858 && !match_mem_size (t, j ? 0 : 1)) 1859 goto mismatch; 1860 } 1861 1862 return match; 1863} 1864 1865static INLINE int 1866operand_type_match (i386_operand_type overlap, 1867 i386_operand_type given) 1868{ 1869 i386_operand_type temp = overlap; 1870 1871 temp.bitfield.jumpabsolute = 0; 1872 temp.bitfield.unspecified = 0; 1873 temp.bitfield.byte = 0; 1874 temp.bitfield.word = 0; 1875 temp.bitfield.dword = 0; 1876 temp.bitfield.fword = 0; 1877 temp.bitfield.qword = 0; 1878 temp.bitfield.tbyte = 0; 1879 temp.bitfield.xmmword = 0; 1880 temp.bitfield.ymmword = 0; 1881 temp.bitfield.zmmword = 0; 1882 if (operand_type_all_zero (&temp)) 1883 goto mismatch; 1884 1885 if (given.bitfield.baseindex == overlap.bitfield.baseindex 1886 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute) 1887 return 1; 1888 1889mismatch: 1890 i.error = operand_type_mismatch; 1891 return 0; 1892} 1893 1894/* If given types g0 and g1 are registers they must be of the same type 1895 unless the expected operand type register overlap is null. 1896 Note that Acc in a template matches every size of reg. */ 1897 1898static INLINE int 1899operand_type_register_match (i386_operand_type m0, 1900 i386_operand_type g0, 1901 i386_operand_type t0, 1902 i386_operand_type m1, 1903 i386_operand_type g1, 1904 i386_operand_type t1) 1905{ 1906 if (!operand_type_check (g0, reg)) 1907 return 1; 1908 1909 if (!operand_type_check (g1, reg)) 1910 return 1; 1911 1912 if (g0.bitfield.reg8 == g1.bitfield.reg8 1913 && g0.bitfield.reg16 == g1.bitfield.reg16 1914 && g0.bitfield.reg32 == g1.bitfield.reg32 1915 && g0.bitfield.reg64 == g1.bitfield.reg64) 1916 return 1; 1917 1918 if (m0.bitfield.acc) 1919 { 1920 t0.bitfield.reg8 = 1; 1921 t0.bitfield.reg16 = 1; 1922 t0.bitfield.reg32 = 1; 1923 t0.bitfield.reg64 = 1; 1924 } 1925 1926 if (m1.bitfield.acc) 1927 { 1928 t1.bitfield.reg8 = 1; 1929 t1.bitfield.reg16 = 1; 1930 t1.bitfield.reg32 = 1; 1931 t1.bitfield.reg64 = 1; 1932 } 1933 1934 if (!(t0.bitfield.reg8 & t1.bitfield.reg8) 1935 && !(t0.bitfield.reg16 & t1.bitfield.reg16) 1936 && !(t0.bitfield.reg32 & t1.bitfield.reg32) 1937 && !(t0.bitfield.reg64 & t1.bitfield.reg64)) 1938 return 1; 1939 1940 i.error = register_type_mismatch; 1941 1942 return 0; 1943} 1944 1945static INLINE unsigned int 1946register_number (const reg_entry *r) 1947{ 1948 unsigned int nr = r->reg_num; 1949 1950 if (r->reg_flags & RegRex) 1951 nr += 8; 1952 1953 if (r->reg_flags & RegVRex) 1954 nr += 16; 1955 1956 return nr; 1957} 1958 1959static INLINE unsigned int 1960mode_from_disp_size (i386_operand_type t) 1961{ 1962 if (t.bitfield.disp8 || t.bitfield.vec_disp8) 1963 return 1; 1964 else if (t.bitfield.disp16 1965 || t.bitfield.disp32 1966 || t.bitfield.disp32s) 1967 return 2; 1968 else 1969 return 0; 1970} 1971 1972static INLINE int 1973fits_in_signed_byte (addressT num) 1974{ 1975 return num + 0x80 <= 0xff; 1976} 1977 1978static INLINE int 1979fits_in_unsigned_byte (addressT num) 1980{ 1981 return num <= 0xff; 1982} 1983 1984static INLINE int 1985fits_in_unsigned_word (addressT num) 1986{ 1987 return num <= 0xffff; 1988} 1989 1990static INLINE int 1991fits_in_signed_word (addressT num) 1992{ 1993 return num + 0x8000 <= 0xffff; 1994} 1995 1996static INLINE int 1997fits_in_signed_long (addressT num ATTRIBUTE_UNUSED) 1998{ 1999#ifndef BFD64 2000 return 1; 2001#else 2002 return num + 0x80000000 <= 0xffffffff; 2003#endif 2004} /* fits_in_signed_long() */ 2005 2006static INLINE int 2007fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED) 2008{ 2009#ifndef BFD64 2010 return 1; 2011#else 2012 return num <= 0xffffffff; 2013#endif 2014} /* fits_in_unsigned_long() */ 2015 2016static INLINE int 2017fits_in_vec_disp8 (offsetT num) 2018{ 2019 int shift = i.memshift; 2020 unsigned int mask; 2021 2022 if (shift == -1) 2023 abort (); 2024 2025 mask = (1 << shift) - 1; 2026 2027 /* Return 0 if NUM isn't properly aligned. */ 2028 if ((num & mask)) 2029 return 0; 2030 2031 /* Check if NUM will fit in 8bit after shift. */ 2032 return fits_in_signed_byte (num >> shift); 2033} 2034 2035static INLINE int 2036fits_in_imm4 (offsetT num) 2037{ 2038 return (num & 0xf) == num; 2039} 2040 2041static i386_operand_type 2042smallest_imm_type (offsetT num) 2043{ 2044 i386_operand_type t; 2045 2046 operand_type_set (&t, 0); 2047 t.bitfield.imm64 = 1; 2048 2049 if (cpu_arch_tune != PROCESSOR_I486 && num == 1) 2050 { 2051 /* This code is disabled on the 486 because all the Imm1 forms 2052 in the opcode table are slower on the i486. They're the 2053 versions with the implicitly specified single-position 2054 displacement, which has another syntax if you really want to 2055 use that form. */ 2056 t.bitfield.imm1 = 1; 2057 t.bitfield.imm8 = 1; 2058 t.bitfield.imm8s = 1; 2059 t.bitfield.imm16 = 1; 2060 t.bitfield.imm32 = 1; 2061 t.bitfield.imm32s = 1; 2062 } 2063 else if (fits_in_signed_byte (num)) 2064 { 2065 t.bitfield.imm8 = 1; 2066 t.bitfield.imm8s = 1; 2067 t.bitfield.imm16 = 1; 2068 t.bitfield.imm32 = 1; 2069 t.bitfield.imm32s = 1; 2070 } 2071 else if (fits_in_unsigned_byte (num)) 2072 { 2073 t.bitfield.imm8 = 1; 2074 t.bitfield.imm16 = 1; 2075 t.bitfield.imm32 = 1; 2076 t.bitfield.imm32s = 1; 2077 } 2078 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) 2079 { 2080 t.bitfield.imm16 = 1; 2081 t.bitfield.imm32 = 1; 2082 t.bitfield.imm32s = 1; 2083 } 2084 else if (fits_in_signed_long (num)) 2085 { 2086 t.bitfield.imm32 = 1; 2087 t.bitfield.imm32s = 1; 2088 } 2089 else if (fits_in_unsigned_long (num)) 2090 t.bitfield.imm32 = 1; 2091 2092 return t; 2093} 2094 2095static offsetT 2096offset_in_range (offsetT val, int size) 2097{ 2098 addressT mask; 2099 2100 switch (size) 2101 { 2102 case 1: mask = ((addressT) 1 << 8) - 1; break; 2103 case 2: mask = ((addressT) 1 << 16) - 1; break; 2104 case 4: mask = ((addressT) 2 << 31) - 1; break; 2105#ifdef BFD64 2106 case 8: mask = ((addressT) 2 << 63) - 1; break; 2107#endif 2108 default: abort (); 2109 } 2110 2111#ifdef BFD64 2112 /* If BFD64, sign extend val for 32bit address mode. */ 2113 if (flag_code != CODE_64BIT 2114 || i.prefix[ADDR_PREFIX]) 2115 if ((val & ~(((addressT) 2 << 31) - 1)) == 0) 2116 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); 2117#endif 2118 2119 if ((val & ~mask) != 0 && (val & ~mask) != ~mask) 2120 { 2121 char buf1[40], buf2[40]; 2122 2123 sprint_value (buf1, val); 2124 sprint_value (buf2, val & mask); 2125 as_warn (_("%s shortened to %s"), buf1, buf2); 2126 } 2127 return val & mask; 2128} 2129 2130enum PREFIX_GROUP 2131{ 2132 PREFIX_EXIST = 0, 2133 PREFIX_LOCK, 2134 PREFIX_REP, 2135 PREFIX_OTHER 2136}; 2137 2138/* Returns 2139 a. PREFIX_EXIST if attempting to add a prefix where one from the 2140 same class already exists. 2141 b. PREFIX_LOCK if lock prefix is added. 2142 c. PREFIX_REP if rep/repne prefix is added. 2143 d. PREFIX_OTHER if other prefix is added. 2144 */ 2145 2146static enum PREFIX_GROUP 2147add_prefix (unsigned int prefix) 2148{ 2149 enum PREFIX_GROUP ret = PREFIX_OTHER; 2150 unsigned int q; 2151 2152 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 2153 && flag_code == CODE_64BIT) 2154 { 2155 if ((i.prefix[REX_PREFIX] & prefix & REX_W) 2156 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B)) 2157 && (prefix & (REX_R | REX_X | REX_B)))) 2158 ret = PREFIX_EXIST; 2159 q = REX_PREFIX; 2160 } 2161 else 2162 { 2163 switch (prefix) 2164 { 2165 default: 2166 abort (); 2167 2168 case CS_PREFIX_OPCODE: 2169 case DS_PREFIX_OPCODE: 2170 case ES_PREFIX_OPCODE: 2171 case FS_PREFIX_OPCODE: 2172 case GS_PREFIX_OPCODE: 2173 case SS_PREFIX_OPCODE: 2174 q = SEG_PREFIX; 2175 break; 2176 2177 case REPNE_PREFIX_OPCODE: 2178 case REPE_PREFIX_OPCODE: 2179 q = REP_PREFIX; 2180 ret = PREFIX_REP; 2181 break; 2182 2183 case LOCK_PREFIX_OPCODE: 2184 q = LOCK_PREFIX; 2185 ret = PREFIX_LOCK; 2186 break; 2187 2188 case FWAIT_OPCODE: 2189 q = WAIT_PREFIX; 2190 break; 2191 2192 case ADDR_PREFIX_OPCODE: 2193 q = ADDR_PREFIX; 2194 break; 2195 2196 case DATA_PREFIX_OPCODE: 2197 q = DATA_PREFIX; 2198 break; 2199 } 2200 if (i.prefix[q] != 0) 2201 ret = PREFIX_EXIST; 2202 } 2203 2204 if (ret) 2205 { 2206 if (!i.prefix[q]) 2207 ++i.prefixes; 2208 i.prefix[q] |= prefix; 2209 } 2210 else 2211 as_bad (_("same type of prefix used twice")); 2212 2213 return ret; 2214} 2215 2216static void 2217update_code_flag (int value, int check) 2218{ 2219 PRINTF_LIKE ((*as_error)); 2220 2221 flag_code = (enum flag_code) value; 2222 if (flag_code == CODE_64BIT) 2223 { 2224 cpu_arch_flags.bitfield.cpu64 = 1; 2225 cpu_arch_flags.bitfield.cpuno64 = 0; 2226 } 2227 else 2228 { 2229 cpu_arch_flags.bitfield.cpu64 = 0; 2230 cpu_arch_flags.bitfield.cpuno64 = 1; 2231 } 2232 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm ) 2233 { 2234 if (check) 2235 as_error = as_fatal; 2236 else 2237 as_error = as_bad; 2238 (*as_error) (_("64bit mode not supported on `%s'."), 2239 cpu_arch_name ? cpu_arch_name : default_arch); 2240 } 2241 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386) 2242 { 2243 if (check) 2244 as_error = as_fatal; 2245 else 2246 as_error = as_bad; 2247 (*as_error) (_("32bit mode not supported on `%s'."), 2248 cpu_arch_name ? cpu_arch_name : default_arch); 2249 } 2250 stackop_size = '\0'; 2251} 2252 2253static void 2254set_code_flag (int value) 2255{ 2256 update_code_flag (value, 0); 2257} 2258 2259static void 2260set_16bit_gcc_code_flag (int new_code_flag) 2261{ 2262 flag_code = (enum flag_code) new_code_flag; 2263 if (flag_code != CODE_16BIT) 2264 abort (); 2265 cpu_arch_flags.bitfield.cpu64 = 0; 2266 cpu_arch_flags.bitfield.cpuno64 = 1; 2267 stackop_size = LONG_MNEM_SUFFIX; 2268} 2269 2270static void 2271set_intel_syntax (int syntax_flag) 2272{ 2273 /* Find out if register prefixing is specified. */ 2274 int ask_naked_reg = 0; 2275 2276 SKIP_WHITESPACE (); 2277 if (!is_end_of_line[(unsigned char) *input_line_pointer]) 2278 { 2279 char *string; 2280 int e = get_symbol_name (&string); 2281 2282 if (strcmp (string, "prefix") == 0) 2283 ask_naked_reg = 1; 2284 else if (strcmp (string, "noprefix") == 0) 2285 ask_naked_reg = -1; 2286 else 2287 as_bad (_("bad argument to syntax directive.")); 2288 (void) restore_line_pointer (e); 2289 } 2290 demand_empty_rest_of_line (); 2291 2292 intel_syntax = syntax_flag; 2293 2294 if (ask_naked_reg == 0) 2295 allow_naked_reg = (intel_syntax 2296 && (bfd_get_symbol_leading_char (stdoutput) != '\0')); 2297 else 2298 allow_naked_reg = (ask_naked_reg < 0); 2299 2300 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0); 2301 2302 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0; 2303 identifier_chars['$'] = intel_syntax ? '$' : 0; 2304 register_prefix = allow_naked_reg ? "" : "%"; 2305} 2306 2307static void 2308set_intel_mnemonic (int mnemonic_flag) 2309{ 2310 intel_mnemonic = mnemonic_flag; 2311} 2312 2313static void 2314set_allow_index_reg (int flag) 2315{ 2316 allow_index_reg = flag; 2317} 2318 2319static void 2320set_check (int what) 2321{ 2322 enum check_kind *kind; 2323 const char *str; 2324 2325 if (what) 2326 { 2327 kind = &operand_check; 2328 str = "operand"; 2329 } 2330 else 2331 { 2332 kind = &sse_check; 2333 str = "sse"; 2334 } 2335 2336 SKIP_WHITESPACE (); 2337 2338 if (!is_end_of_line[(unsigned char) *input_line_pointer]) 2339 { 2340 char *string; 2341 int e = get_symbol_name (&string); 2342 2343 if (strcmp (string, "none") == 0) 2344 *kind = check_none; 2345 else if (strcmp (string, "warning") == 0) 2346 *kind = check_warning; 2347 else if (strcmp (string, "error") == 0) 2348 *kind = check_error; 2349 else 2350 as_bad (_("bad argument to %s_check directive."), str); 2351 (void) restore_line_pointer (e); 2352 } 2353 else 2354 as_bad (_("missing argument for %s_check directive"), str); 2355 2356 demand_empty_rest_of_line (); 2357} 2358 2359static void 2360check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED, 2361 i386_cpu_flags new_flag ATTRIBUTE_UNUSED) 2362{ 2363#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 2364 static const char *arch; 2365 2366 /* Intel LIOM is only supported on ELF. */ 2367 if (!IS_ELF) 2368 return; 2369 2370 if (!arch) 2371 { 2372 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise 2373 use default_arch. */ 2374 arch = cpu_arch_name; 2375 if (!arch) 2376 arch = default_arch; 2377 } 2378 2379 /* If we are targeting Intel MCU, we must enable it. */ 2380 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU 2381 || new_flag.bitfield.cpuiamcu) 2382 return; 2383 2384 /* If we are targeting Intel L1OM, we must enable it. */ 2385 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM 2386 || new_flag.bitfield.cpul1om) 2387 return; 2388 2389 /* If we are targeting Intel K1OM, we must enable it. */ 2390 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM 2391 || new_flag.bitfield.cpuk1om) 2392 return; 2393 2394 as_bad (_("`%s' is not supported on `%s'"), name, arch); 2395#endif 2396} 2397 2398static void 2399set_cpu_arch (int dummy ATTRIBUTE_UNUSED) 2400{ 2401 SKIP_WHITESPACE (); 2402 2403 if (!is_end_of_line[(unsigned char) *input_line_pointer]) 2404 { 2405 char *string; 2406 int e = get_symbol_name (&string); 2407 unsigned int j; 2408 i386_cpu_flags flags; 2409 2410 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) 2411 { 2412 if (strcmp (string, cpu_arch[j].name) == 0) 2413 { 2414 check_cpu_arch_compatible (string, cpu_arch[j].flags); 2415 2416 if (*string != '.') 2417 { 2418 cpu_arch_name = cpu_arch[j].name; 2419 cpu_sub_arch_name = NULL; 2420 cpu_arch_flags = cpu_arch[j].flags; 2421 if (flag_code == CODE_64BIT) 2422 { 2423 cpu_arch_flags.bitfield.cpu64 = 1; 2424 cpu_arch_flags.bitfield.cpuno64 = 0; 2425 } 2426 else 2427 { 2428 cpu_arch_flags.bitfield.cpu64 = 0; 2429 cpu_arch_flags.bitfield.cpuno64 = 1; 2430 } 2431 cpu_arch_isa = cpu_arch[j].type; 2432 cpu_arch_isa_flags = cpu_arch[j].flags; 2433 if (!cpu_arch_tune_set) 2434 { 2435 cpu_arch_tune = cpu_arch_isa; 2436 cpu_arch_tune_flags = cpu_arch_isa_flags; 2437 } 2438 break; 2439 } 2440 2441 flags = cpu_flags_or (cpu_arch_flags, 2442 cpu_arch[j].flags); 2443 2444 if (!cpu_flags_equal (&flags, &cpu_arch_flags)) 2445 { 2446 if (cpu_sub_arch_name) 2447 { 2448 char *name = cpu_sub_arch_name; 2449 cpu_sub_arch_name = concat (name, 2450 cpu_arch[j].name, 2451 (const char *) NULL); 2452 free (name); 2453 } 2454 else 2455 cpu_sub_arch_name = xstrdup (cpu_arch[j].name); 2456 cpu_arch_flags = flags; 2457 cpu_arch_isa_flags = flags; 2458 } 2459 (void) restore_line_pointer (e); 2460 demand_empty_rest_of_line (); 2461 return; 2462 } 2463 } 2464 2465 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch)) 2466 { 2467 /* Disable an ISA entension. */ 2468 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) 2469 if (strcmp (string + 1, cpu_noarch [j].name) == 0) 2470 { 2471 flags = cpu_flags_and_not (cpu_arch_flags, 2472 cpu_noarch[j].flags); 2473 if (!cpu_flags_equal (&flags, &cpu_arch_flags)) 2474 { 2475 if (cpu_sub_arch_name) 2476 { 2477 char *name = cpu_sub_arch_name; 2478 cpu_sub_arch_name = concat (name, string, 2479 (const char *) NULL); 2480 free (name); 2481 } 2482 else 2483 cpu_sub_arch_name = xstrdup (string); 2484 cpu_arch_flags = flags; 2485 cpu_arch_isa_flags = flags; 2486 } 2487 (void) restore_line_pointer (e); 2488 demand_empty_rest_of_line (); 2489 return; 2490 } 2491 2492 j = ARRAY_SIZE (cpu_arch); 2493 } 2494 2495 if (j >= ARRAY_SIZE (cpu_arch)) 2496 as_bad (_("no such architecture: `%s'"), string); 2497 2498 *input_line_pointer = e; 2499 } 2500 else 2501 as_bad (_("missing cpu architecture")); 2502 2503 no_cond_jump_promotion = 0; 2504 if (*input_line_pointer == ',' 2505 && !is_end_of_line[(unsigned char) input_line_pointer[1]]) 2506 { 2507 char *string; 2508 char e; 2509 2510 ++input_line_pointer; 2511 e = get_symbol_name (&string); 2512 2513 if (strcmp (string, "nojumps") == 0) 2514 no_cond_jump_promotion = 1; 2515 else if (strcmp (string, "jumps") == 0) 2516 ; 2517 else 2518 as_bad (_("no such architecture modifier: `%s'"), string); 2519 2520 (void) restore_line_pointer (e); 2521 } 2522 2523 demand_empty_rest_of_line (); 2524} 2525 2526enum bfd_architecture 2527i386_arch (void) 2528{ 2529 if (cpu_arch_isa == PROCESSOR_L1OM) 2530 { 2531 if (OUTPUT_FLAVOR != bfd_target_elf_flavour 2532 || flag_code != CODE_64BIT) 2533 as_fatal (_("Intel L1OM is 64bit ELF only")); 2534 return bfd_arch_l1om; 2535 } 2536 else if (cpu_arch_isa == PROCESSOR_K1OM) 2537 { 2538 if (OUTPUT_FLAVOR != bfd_target_elf_flavour 2539 || flag_code != CODE_64BIT) 2540 as_fatal (_("Intel K1OM is 64bit ELF only")); 2541 return bfd_arch_k1om; 2542 } 2543 else if (cpu_arch_isa == PROCESSOR_IAMCU) 2544 { 2545 if (OUTPUT_FLAVOR != bfd_target_elf_flavour 2546 || flag_code == CODE_64BIT) 2547 as_fatal (_("Intel MCU is 32bit ELF only")); 2548 return bfd_arch_iamcu; 2549 } 2550 else 2551 return bfd_arch_i386; 2552} 2553 2554unsigned long 2555i386_mach (void) 2556{ 2557 if (!strncmp (default_arch, "x86_64", 6)) 2558 { 2559 if (cpu_arch_isa == PROCESSOR_L1OM) 2560 { 2561 if (OUTPUT_FLAVOR != bfd_target_elf_flavour 2562 || default_arch[6] != '\0') 2563 as_fatal (_("Intel L1OM is 64bit ELF only")); 2564 return bfd_mach_l1om; 2565 } 2566 else if (cpu_arch_isa == PROCESSOR_K1OM) 2567 { 2568 if (OUTPUT_FLAVOR != bfd_target_elf_flavour 2569 || default_arch[6] != '\0') 2570 as_fatal (_("Intel K1OM is 64bit ELF only")); 2571 return bfd_mach_k1om; 2572 } 2573 else if (default_arch[6] == '\0') 2574 return bfd_mach_x86_64; 2575 else 2576 return bfd_mach_x64_32; 2577 } 2578 else if (!strcmp (default_arch, "i386") 2579 || !strcmp (default_arch, "iamcu")) 2580 { 2581 if (cpu_arch_isa == PROCESSOR_IAMCU) 2582 { 2583 if (OUTPUT_FLAVOR != bfd_target_elf_flavour) 2584 as_fatal (_("Intel MCU is 32bit ELF only")); 2585 return bfd_mach_i386_iamcu; 2586 } 2587 else 2588 return bfd_mach_i386_i386; 2589 } 2590 else 2591 as_fatal (_("unknown architecture")); 2592} 2593 2594void 2595md_begin (void) 2596{ 2597 const char *hash_err; 2598 2599 /* Initialize op_hash hash table. */ 2600 op_hash = hash_new (); 2601 2602 { 2603 const insn_template *optab; 2604 templates *core_optab; 2605 2606 /* Setup for loop. */ 2607 optab = i386_optab; 2608 core_optab = XNEW (templates); 2609 core_optab->start = optab; 2610 2611 while (1) 2612 { 2613 ++optab; 2614 if (optab->name == NULL 2615 || strcmp (optab->name, (optab - 1)->name) != 0) 2616 { 2617 /* different name --> ship out current template list; 2618 add to hash table; & begin anew. */ 2619 core_optab->end = optab; 2620 hash_err = hash_insert (op_hash, 2621 (optab - 1)->name, 2622 (void *) core_optab); 2623 if (hash_err) 2624 { 2625 as_fatal (_("can't hash %s: %s"), 2626 (optab - 1)->name, 2627 hash_err); 2628 } 2629 if (optab->name == NULL) 2630 break; 2631 core_optab = XNEW (templates); 2632 core_optab->start = optab; 2633 } 2634 } 2635 } 2636 2637 /* Initialize reg_hash hash table. */ 2638 reg_hash = hash_new (); 2639 { 2640 const reg_entry *regtab; 2641 unsigned int regtab_size = i386_regtab_size; 2642 2643 for (regtab = i386_regtab; regtab_size--; regtab++) 2644 { 2645 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab); 2646 if (hash_err) 2647 as_fatal (_("can't hash %s: %s"), 2648 regtab->reg_name, 2649 hash_err); 2650 } 2651 } 2652 2653 /* Fill in lexical tables: mnemonic_chars, operand_chars. */ 2654 { 2655 int c; 2656 char *p; 2657 2658 for (c = 0; c < 256; c++) 2659 { 2660 if (ISDIGIT (c)) 2661 { 2662 digit_chars[c] = c; 2663 mnemonic_chars[c] = c; 2664 register_chars[c] = c; 2665 operand_chars[c] = c; 2666 } 2667 else if (ISLOWER (c)) 2668 { 2669 mnemonic_chars[c] = c; 2670 register_chars[c] = c; 2671 operand_chars[c] = c; 2672 } 2673 else if (ISUPPER (c)) 2674 { 2675 mnemonic_chars[c] = TOLOWER (c); 2676 register_chars[c] = mnemonic_chars[c]; 2677 operand_chars[c] = c; 2678 } 2679 else if (c == '{' || c == '}') 2680 operand_chars[c] = c; 2681 2682 if (ISALPHA (c) || ISDIGIT (c)) 2683 identifier_chars[c] = c; 2684 else if (c >= 128) 2685 { 2686 identifier_chars[c] = c; 2687 operand_chars[c] = c; 2688 } 2689 } 2690 2691#ifdef LEX_AT 2692 identifier_chars['@'] = '@'; 2693#endif 2694#ifdef LEX_QM 2695 identifier_chars['?'] = '?'; 2696 operand_chars['?'] = '?'; 2697#endif 2698 digit_chars['-'] = '-'; 2699 mnemonic_chars['_'] = '_'; 2700 mnemonic_chars['-'] = '-'; 2701 mnemonic_chars['.'] = '.'; 2702 identifier_chars['_'] = '_'; 2703 identifier_chars['.'] = '.'; 2704 2705 for (p = operand_special_chars; *p != '\0'; p++) 2706 operand_chars[(unsigned char) *p] = *p; 2707 } 2708 2709 if (flag_code == CODE_64BIT) 2710 { 2711#if defined (OBJ_COFF) && defined (TE_PE) 2712 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour 2713 ? 32 : 16); 2714#else 2715 x86_dwarf2_return_column = 16; 2716#endif 2717 x86_cie_data_alignment = -8; 2718 } 2719 else 2720 { 2721 x86_dwarf2_return_column = 8; 2722 x86_cie_data_alignment = -4; 2723 } 2724} 2725 2726void 2727i386_print_statistics (FILE *file) 2728{ 2729 hash_print_statistics (file, "i386 opcode", op_hash); 2730 hash_print_statistics (file, "i386 register", reg_hash); 2731} 2732 2733#ifdef DEBUG386 2734 2735/* Debugging routines for md_assemble. */ 2736static void pte (insn_template *); 2737static void pt (i386_operand_type); 2738static void pe (expressionS *); 2739static void ps (symbolS *); 2740 2741static void 2742pi (char *line, i386_insn *x) 2743{ 2744 unsigned int j; 2745 2746 fprintf (stdout, "%s: template ", line); 2747 pte (&x->tm); 2748 fprintf (stdout, " address: base %s index %s scale %x\n", 2749 x->base_reg ? x->base_reg->reg_name : "none", 2750 x->index_reg ? x->index_reg->reg_name : "none", 2751 x->log2_scale_factor); 2752 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", 2753 x->rm.mode, x->rm.reg, x->rm.regmem); 2754 fprintf (stdout, " sib: base %x index %x scale %x\n", 2755 x->sib.base, x->sib.index, x->sib.scale); 2756 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", 2757 (x->rex & REX_W) != 0, 2758 (x->rex & REX_R) != 0, 2759 (x->rex & REX_X) != 0, 2760 (x->rex & REX_B) != 0); 2761 for (j = 0; j < x->operands; j++) 2762 { 2763 fprintf (stdout, " #%d: ", j + 1); 2764 pt (x->types[j]); 2765 fprintf (stdout, "\n"); 2766 if (x->types[j].bitfield.reg8 2767 || x->types[j].bitfield.reg16 2768 || x->types[j].bitfield.reg32 2769 || x->types[j].bitfield.reg64 2770 || x->types[j].bitfield.regmmx 2771 || x->types[j].bitfield.regxmm 2772 || x->types[j].bitfield.regymm 2773 || x->types[j].bitfield.regzmm 2774 || x->types[j].bitfield.sreg2 2775 || x->types[j].bitfield.sreg3 2776 || x->types[j].bitfield.control 2777 || x->types[j].bitfield.debug 2778 || x->types[j].bitfield.test) 2779 fprintf (stdout, "%s\n", x->op[j].regs->reg_name); 2780 if (operand_type_check (x->types[j], imm)) 2781 pe (x->op[j].imms); 2782 if (operand_type_check (x->types[j], disp)) 2783 pe (x->op[j].disps); 2784 } 2785} 2786 2787static void 2788pte (insn_template *t) 2789{ 2790 unsigned int j; 2791 fprintf (stdout, " %d operands ", t->operands); 2792 fprintf (stdout, "opcode %x ", t->base_opcode); 2793 if (t->extension_opcode != None) 2794 fprintf (stdout, "ext %x ", t->extension_opcode); 2795 if (t->opcode_modifier.d) 2796 fprintf (stdout, "D"); 2797 if (t->opcode_modifier.w) 2798 fprintf (stdout, "W"); 2799 fprintf (stdout, "\n"); 2800 for (j = 0; j < t->operands; j++) 2801 { 2802 fprintf (stdout, " #%d type ", j + 1); 2803 pt (t->operand_types[j]); 2804 fprintf (stdout, "\n"); 2805 } 2806} 2807 2808static void 2809pe (expressionS *e) 2810{ 2811 fprintf (stdout, " operation %d\n", e->X_op); 2812 fprintf (stdout, " add_number %ld (%lx)\n", 2813 (long) e->X_add_number, (long) e->X_add_number); 2814 if (e->X_add_symbol) 2815 { 2816 fprintf (stdout, " add_symbol "); 2817 ps (e->X_add_symbol); 2818 fprintf (stdout, "\n"); 2819 } 2820 if (e->X_op_symbol) 2821 { 2822 fprintf (stdout, " op_symbol "); 2823 ps (e->X_op_symbol); 2824 fprintf (stdout, "\n"); 2825 } 2826} 2827 2828static void 2829ps (symbolS *s) 2830{ 2831 fprintf (stdout, "%s type %s%s", 2832 S_GET_NAME (s), 2833 S_IS_EXTERNAL (s) ? "EXTERNAL " : "", 2834 segment_name (S_GET_SEGMENT (s))); 2835} 2836 2837static struct type_name 2838 { 2839 i386_operand_type mask; 2840 const char *name; 2841 } 2842const type_names[] = 2843{ 2844 { OPERAND_TYPE_REG8, "r8" }, 2845 { OPERAND_TYPE_REG16, "r16" }, 2846 { OPERAND_TYPE_REG32, "r32" }, 2847 { OPERAND_TYPE_REG64, "r64" }, 2848 { OPERAND_TYPE_IMM8, "i8" }, 2849 { OPERAND_TYPE_IMM8, "i8s" }, 2850 { OPERAND_TYPE_IMM16, "i16" }, 2851 { OPERAND_TYPE_IMM32, "i32" }, 2852 { OPERAND_TYPE_IMM32S, "i32s" }, 2853 { OPERAND_TYPE_IMM64, "i64" }, 2854 { OPERAND_TYPE_IMM1, "i1" }, 2855 { OPERAND_TYPE_BASEINDEX, "BaseIndex" }, 2856 { OPERAND_TYPE_DISP8, "d8" }, 2857 { OPERAND_TYPE_DISP16, "d16" }, 2858 { OPERAND_TYPE_DISP32, "d32" }, 2859 { OPERAND_TYPE_DISP32S, "d32s" }, 2860 { OPERAND_TYPE_DISP64, "d64" }, 2861 { OPERAND_TYPE_VEC_DISP8, "Vector d8" }, 2862 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" }, 2863 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" }, 2864 { OPERAND_TYPE_CONTROL, "control reg" }, 2865 { OPERAND_TYPE_TEST, "test reg" }, 2866 { OPERAND_TYPE_DEBUG, "debug reg" }, 2867 { OPERAND_TYPE_FLOATREG, "FReg" }, 2868 { OPERAND_TYPE_FLOATACC, "FAcc" }, 2869 { OPERAND_TYPE_SREG2, "SReg2" }, 2870 { OPERAND_TYPE_SREG3, "SReg3" }, 2871 { OPERAND_TYPE_ACC, "Acc" }, 2872 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" }, 2873 { OPERAND_TYPE_REGMMX, "rMMX" }, 2874 { OPERAND_TYPE_REGXMM, "rXMM" }, 2875 { OPERAND_TYPE_REGYMM, "rYMM" }, 2876 { OPERAND_TYPE_REGZMM, "rZMM" }, 2877 { OPERAND_TYPE_REGMASK, "Mask reg" }, 2878 { OPERAND_TYPE_ESSEG, "es" }, 2879}; 2880 2881static void 2882pt (i386_operand_type t) 2883{ 2884 unsigned int j; 2885 i386_operand_type a; 2886 2887 for (j = 0; j < ARRAY_SIZE (type_names); j++) 2888 { 2889 a = operand_type_and (t, type_names[j].mask); 2890 if (!operand_type_all_zero (&a)) 2891 fprintf (stdout, "%s, ", type_names[j].name); 2892 } 2893 fflush (stdout); 2894} 2895 2896#endif /* DEBUG386 */ 2897 2898static bfd_reloc_code_real_type 2899reloc (unsigned int size, 2900 int pcrel, 2901 int sign, 2902 bfd_reloc_code_real_type other) 2903{ 2904 if (other != NO_RELOC) 2905 { 2906 reloc_howto_type *rel; 2907 2908 if (size == 8) 2909 switch (other) 2910 { 2911 case BFD_RELOC_X86_64_GOT32: 2912 return BFD_RELOC_X86_64_GOT64; 2913 break; 2914 case BFD_RELOC_X86_64_GOTPLT64: 2915 return BFD_RELOC_X86_64_GOTPLT64; 2916 break; 2917 case BFD_RELOC_X86_64_PLTOFF64: 2918 return BFD_RELOC_X86_64_PLTOFF64; 2919 break; 2920 case BFD_RELOC_X86_64_GOTPC32: 2921 other = BFD_RELOC_X86_64_GOTPC64; 2922 break; 2923 case BFD_RELOC_X86_64_GOTPCREL: 2924 other = BFD_RELOC_X86_64_GOTPCREL64; 2925 break; 2926 case BFD_RELOC_X86_64_TPOFF32: 2927 other = BFD_RELOC_X86_64_TPOFF64; 2928 break; 2929 case BFD_RELOC_X86_64_DTPOFF32: 2930 other = BFD_RELOC_X86_64_DTPOFF64; 2931 break; 2932 default: 2933 break; 2934 } 2935 2936#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 2937 if (other == BFD_RELOC_SIZE32) 2938 { 2939 if (size == 8) 2940 other = BFD_RELOC_SIZE64; 2941 if (pcrel) 2942 { 2943 as_bad (_("there are no pc-relative size relocations")); 2944 return NO_RELOC; 2945 } 2946 } 2947#endif 2948 2949 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */ 2950 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc)) 2951 sign = -1; 2952 2953 rel = bfd_reloc_type_lookup (stdoutput, other); 2954 if (!rel) 2955 as_bad (_("unknown relocation (%u)"), other); 2956 else if (size != bfd_get_reloc_size (rel)) 2957 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"), 2958 bfd_get_reloc_size (rel), 2959 size); 2960 else if (pcrel && !rel->pc_relative) 2961 as_bad (_("non-pc-relative relocation for pc-relative field")); 2962 else if ((rel->complain_on_overflow == complain_overflow_signed 2963 && !sign) 2964 || (rel->complain_on_overflow == complain_overflow_unsigned 2965 && sign > 0)) 2966 as_bad (_("relocated field and relocation type differ in signedness")); 2967 else 2968 return other; 2969 return NO_RELOC; 2970 } 2971 2972 if (pcrel) 2973 { 2974 if (!sign) 2975 as_bad (_("there are no unsigned pc-relative relocations")); 2976 switch (size) 2977 { 2978 case 1: return BFD_RELOC_8_PCREL; 2979 case 2: return BFD_RELOC_16_PCREL; 2980 case 4: return BFD_RELOC_32_PCREL; 2981 case 8: return BFD_RELOC_64_PCREL; 2982 } 2983 as_bad (_("cannot do %u byte pc-relative relocation"), size); 2984 } 2985 else 2986 { 2987 if (sign > 0) 2988 switch (size) 2989 { 2990 case 4: return BFD_RELOC_X86_64_32S; 2991 } 2992 else 2993 switch (size) 2994 { 2995 case 1: return BFD_RELOC_8; 2996 case 2: return BFD_RELOC_16; 2997 case 4: return BFD_RELOC_32; 2998 case 8: return BFD_RELOC_64; 2999 } 3000 as_bad (_("cannot do %s %u byte relocation"), 3001 sign > 0 ? "signed" : "unsigned", size); 3002 } 3003 3004 return NO_RELOC; 3005} 3006 3007/* Here we decide which fixups can be adjusted to make them relative to 3008 the beginning of the section instead of the symbol. Basically we need 3009 to make sure that the dynamic relocations are done correctly, so in 3010 some cases we force the original symbol to be used. */ 3011 3012int 3013tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED) 3014{ 3015#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 3016 if (!IS_ELF) 3017 return 1; 3018 3019 /* Don't adjust pc-relative references to merge sections in 64-bit 3020 mode. */ 3021 if (use_rela_relocations 3022 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 3023 && fixP->fx_pcrel) 3024 return 0; 3025 3026 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations 3027 and changed later by validate_fix. */ 3028 if (GOT_symbol && fixP->fx_subsy == GOT_symbol 3029 && fixP->fx_r_type == BFD_RELOC_32_PCREL) 3030 return 0; 3031 3032 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol 3033 for size relocations. */ 3034 if (fixP->fx_r_type == BFD_RELOC_SIZE32 3035 || fixP->fx_r_type == BFD_RELOC_SIZE64 3036 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF 3037 || fixP->fx_r_type == BFD_RELOC_386_PLT32 3038 || fixP->fx_r_type == BFD_RELOC_386_GOT32 3039 || fixP->fx_r_type == BFD_RELOC_386_GOT32X 3040 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD 3041 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM 3042 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 3043 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 3044 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE 3045 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE 3046 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 3047 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE 3048 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC 3049 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL 3050 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32 3051 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 3052 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL 3053 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX 3054 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX 3055 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD 3056 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD 3057 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 3058 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 3059 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF 3060 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 3061 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 3062 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64 3063 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC 3064 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL 3065 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 3066 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 3067 return 0; 3068#endif 3069 return 1; 3070} 3071 3072static int 3073intel_float_operand (const char *mnemonic) 3074{ 3075 /* Note that the value returned is meaningful only for opcodes with (memory) 3076 operands, hence the code here is free to improperly handle opcodes that 3077 have no operands (for better performance and smaller code). */ 3078 3079 if (mnemonic[0] != 'f') 3080 return 0; /* non-math */ 3081 3082 switch (mnemonic[1]) 3083 { 3084 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and 3085 the fs segment override prefix not currently handled because no 3086 call path can make opcodes without operands get here */ 3087 case 'i': 3088 return 2 /* integer op */; 3089 case 'l': 3090 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) 3091 return 3; /* fldcw/fldenv */ 3092 break; 3093 case 'n': 3094 if (mnemonic[2] != 'o' /* fnop */) 3095 return 3; /* non-waiting control op */ 3096 break; 3097 case 'r': 3098 if (mnemonic[2] == 's') 3099 return 3; /* frstor/frstpm */ 3100 break; 3101 case 's': 3102 if (mnemonic[2] == 'a') 3103 return 3; /* fsave */ 3104 if (mnemonic[2] == 't') 3105 { 3106 switch (mnemonic[3]) 3107 { 3108 case 'c': /* fstcw */ 3109 case 'd': /* fstdw */ 3110 case 'e': /* fstenv */ 3111 case 's': /* fsts[gw] */ 3112 return 3; 3113 } 3114 } 3115 break; 3116 case 'x': 3117 if (mnemonic[2] == 'r' || mnemonic[2] == 's') 3118 return 0; /* fxsave/fxrstor are not really math ops */ 3119 break; 3120 } 3121 3122 return 1; 3123} 3124 3125/* Build the VEX prefix. */ 3126 3127static void 3128build_vex_prefix (const insn_template *t) 3129{ 3130 unsigned int register_specifier; 3131 unsigned int implied_prefix; 3132 unsigned int vector_length; 3133 3134 /* Check register specifier. */ 3135 if (i.vex.register_specifier) 3136 { 3137 register_specifier = 3138 ~register_number (i.vex.register_specifier) & 0xf; 3139 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0); 3140 } 3141 else 3142 register_specifier = 0xf; 3143 3144 /* Use 2-byte VEX prefix by swappping destination and source 3145 operand. */ 3146 if (!i.swap_operand 3147 && i.operands == i.reg_operands 3148 && i.tm.opcode_modifier.vexopcode == VEX0F 3149 && i.tm.opcode_modifier.s 3150 && i.rex == REX_B) 3151 { 3152 unsigned int xchg = i.operands - 1; 3153 union i386_op temp_op; 3154 i386_operand_type temp_type; 3155 3156 temp_type = i.types[xchg]; 3157 i.types[xchg] = i.types[0]; 3158 i.types[0] = temp_type; 3159 temp_op = i.op[xchg]; 3160 i.op[xchg] = i.op[0]; 3161 i.op[0] = temp_op; 3162 3163 gas_assert (i.rm.mode == 3); 3164 3165 i.rex = REX_R; 3166 xchg = i.rm.regmem; 3167 i.rm.regmem = i.rm.reg; 3168 i.rm.reg = xchg; 3169 3170 /* Use the next insn. */ 3171 i.tm = t[1]; 3172 } 3173 3174 if (i.tm.opcode_modifier.vex == VEXScalar) 3175 vector_length = avxscalar; 3176 else 3177 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0; 3178 3179 switch ((i.tm.base_opcode >> 8) & 0xff) 3180 { 3181 case 0: 3182 implied_prefix = 0; 3183 break; 3184 case DATA_PREFIX_OPCODE: 3185 implied_prefix = 1; 3186 break; 3187 case REPE_PREFIX_OPCODE: 3188 implied_prefix = 2; 3189 break; 3190 case REPNE_PREFIX_OPCODE: 3191 implied_prefix = 3; 3192 break; 3193 default: 3194 abort (); 3195 } 3196 3197 /* Use 2-byte VEX prefix if possible. */ 3198 if (i.tm.opcode_modifier.vexopcode == VEX0F 3199 && i.tm.opcode_modifier.vexw != VEXW1 3200 && (i.rex & (REX_W | REX_X | REX_B)) == 0) 3201 { 3202 /* 2-byte VEX prefix. */ 3203 unsigned int r; 3204 3205 i.vex.length = 2; 3206 i.vex.bytes[0] = 0xc5; 3207 3208 /* Check the REX.R bit. */ 3209 r = (i.rex & REX_R) ? 0 : 1; 3210 i.vex.bytes[1] = (r << 7 3211 | register_specifier << 3 3212 | vector_length << 2 3213 | implied_prefix); 3214 } 3215 else 3216 { 3217 /* 3-byte VEX prefix. */ 3218 unsigned int m, w; 3219 3220 i.vex.length = 3; 3221 3222 switch (i.tm.opcode_modifier.vexopcode) 3223 { 3224 case VEX0F: 3225 m = 0x1; 3226 i.vex.bytes[0] = 0xc4; 3227 break; 3228 case VEX0F38: 3229 m = 0x2; 3230 i.vex.bytes[0] = 0xc4; 3231 break; 3232 case VEX0F3A: 3233 m = 0x3; 3234 i.vex.bytes[0] = 0xc4; 3235 break; 3236 case XOP08: 3237 m = 0x8; 3238 i.vex.bytes[0] = 0x8f; 3239 break; 3240 case XOP09: 3241 m = 0x9; 3242 i.vex.bytes[0] = 0x8f; 3243 break; 3244 case XOP0A: 3245 m = 0xa; 3246 i.vex.bytes[0] = 0x8f; 3247 break; 3248 default: 3249 abort (); 3250 } 3251 3252 /* The high 3 bits of the second VEX byte are 1's compliment 3253 of RXB bits from REX. */ 3254 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; 3255 3256 /* Check the REX.W bit. */ 3257 w = (i.rex & REX_W) ? 1 : 0; 3258 if (i.tm.opcode_modifier.vexw == VEXW1) 3259 w = 1; 3260 3261 i.vex.bytes[2] = (w << 7 3262 | register_specifier << 3 3263 | vector_length << 2 3264 | implied_prefix); 3265 } 3266} 3267 3268/* Build the EVEX prefix. */ 3269 3270static void 3271build_evex_prefix (void) 3272{ 3273 unsigned int register_specifier; 3274 unsigned int implied_prefix; 3275 unsigned int m, w; 3276 rex_byte vrex_used = 0; 3277 3278 /* Check register specifier. */ 3279 if (i.vex.register_specifier) 3280 { 3281 gas_assert ((i.vrex & REX_X) == 0); 3282 3283 register_specifier = i.vex.register_specifier->reg_num; 3284 if ((i.vex.register_specifier->reg_flags & RegRex)) 3285 register_specifier += 8; 3286 /* The upper 16 registers are encoded in the fourth byte of the 3287 EVEX prefix. */ 3288 if (!(i.vex.register_specifier->reg_flags & RegVRex)) 3289 i.vex.bytes[3] = 0x8; 3290 register_specifier = ~register_specifier & 0xf; 3291 } 3292 else 3293 { 3294 register_specifier = 0xf; 3295 3296 /* Encode upper 16 vector index register in the fourth byte of 3297 the EVEX prefix. */ 3298 if (!(i.vrex & REX_X)) 3299 i.vex.bytes[3] = 0x8; 3300 else 3301 vrex_used |= REX_X; 3302 } 3303 3304 switch ((i.tm.base_opcode >> 8) & 0xff) 3305 { 3306 case 0: 3307 implied_prefix = 0; 3308 break; 3309 case DATA_PREFIX_OPCODE: 3310 implied_prefix = 1; 3311 break; 3312 case REPE_PREFIX_OPCODE: 3313 implied_prefix = 2; 3314 break; 3315 case REPNE_PREFIX_OPCODE: 3316 implied_prefix = 3; 3317 break; 3318 default: 3319 abort (); 3320 } 3321 3322 /* 4 byte EVEX prefix. */ 3323 i.vex.length = 4; 3324 i.vex.bytes[0] = 0x62; 3325 3326 /* mmmm bits. */ 3327 switch (i.tm.opcode_modifier.vexopcode) 3328 { 3329 case VEX0F: 3330 m = 1; 3331 break; 3332 case VEX0F38: 3333 m = 2; 3334 break; 3335 case VEX0F3A: 3336 m = 3; 3337 break; 3338 default: 3339 abort (); 3340 break; 3341 } 3342 3343 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB 3344 bits from REX. */ 3345 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; 3346 3347 /* The fifth bit of the second EVEX byte is 1's compliment of the 3348 REX_R bit in VREX. */ 3349 if (!(i.vrex & REX_R)) 3350 i.vex.bytes[1] |= 0x10; 3351 else 3352 vrex_used |= REX_R; 3353 3354 if ((i.reg_operands + i.imm_operands) == i.operands) 3355 { 3356 /* When all operands are registers, the REX_X bit in REX is not 3357 used. We reuse it to encode the upper 16 registers, which is 3358 indicated by the REX_B bit in VREX. The REX_X bit is encoded 3359 as 1's compliment. */ 3360 if ((i.vrex & REX_B)) 3361 { 3362 vrex_used |= REX_B; 3363 i.vex.bytes[1] &= ~0x40; 3364 } 3365 } 3366 3367 /* EVEX instructions shouldn't need the REX prefix. */ 3368 i.vrex &= ~vrex_used; 3369 gas_assert (i.vrex == 0); 3370 3371 /* Check the REX.W bit. */ 3372 w = (i.rex & REX_W) ? 1 : 0; 3373 if (i.tm.opcode_modifier.vexw) 3374 { 3375 if (i.tm.opcode_modifier.vexw == VEXW1) 3376 w = 1; 3377 } 3378 /* If w is not set it means we are dealing with WIG instruction. */ 3379 else if (!w) 3380 { 3381 if (evexwig == evexw1) 3382 w = 1; 3383 } 3384 3385 /* Encode the U bit. */ 3386 implied_prefix |= 0x4; 3387 3388 /* The third byte of the EVEX prefix. */ 3389 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix); 3390 3391 /* The fourth byte of the EVEX prefix. */ 3392 /* The zeroing-masking bit. */ 3393 if (i.mask && i.mask->zeroing) 3394 i.vex.bytes[3] |= 0x80; 3395 3396 /* Don't always set the broadcast bit if there is no RC. */ 3397 if (!i.rounding) 3398 { 3399 /* Encode the vector length. */ 3400 unsigned int vec_length; 3401 3402 switch (i.tm.opcode_modifier.evex) 3403 { 3404 case EVEXLIG: /* LL' is ignored */ 3405 vec_length = evexlig << 5; 3406 break; 3407 case EVEX128: 3408 vec_length = 0 << 5; 3409 break; 3410 case EVEX256: 3411 vec_length = 1 << 5; 3412 break; 3413 case EVEX512: 3414 vec_length = 2 << 5; 3415 break; 3416 default: 3417 abort (); 3418 break; 3419 } 3420 i.vex.bytes[3] |= vec_length; 3421 /* Encode the broadcast bit. */ 3422 if (i.broadcast) 3423 i.vex.bytes[3] |= 0x10; 3424 } 3425 else 3426 { 3427 if (i.rounding->type != saeonly) 3428 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5); 3429 else 3430 i.vex.bytes[3] |= 0x10 | (evexrcig << 5); 3431 } 3432 3433 if (i.mask && i.mask->mask) 3434 i.vex.bytes[3] |= i.mask->mask->reg_num; 3435} 3436 3437static void 3438process_immext (void) 3439{ 3440 expressionS *exp; 3441 3442 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme) 3443 && i.operands > 0) 3444 { 3445 /* MONITOR/MWAIT as well as SVME instructions have fixed operands 3446 with an opcode suffix which is coded in the same place as an 3447 8-bit immediate field would be. 3448 Here we check those operands and remove them afterwards. */ 3449 unsigned int x; 3450 3451 for (x = 0; x < i.operands; x++) 3452 if (register_number (i.op[x].regs) != x) 3453 as_bad (_("can't use register '%s%s' as operand %d in '%s'."), 3454 register_prefix, i.op[x].regs->reg_name, x + 1, 3455 i.tm.name); 3456 3457 i.operands = 0; 3458 } 3459 3460 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0) 3461 { 3462 /* MONITORX/MWAITX instructions have fixed operands with an opcode 3463 suffix which is coded in the same place as an 8-bit immediate 3464 field would be. 3465 Here we check those operands and remove them afterwards. */ 3466 unsigned int x; 3467 3468 if (i.operands != 3) 3469 abort(); 3470 3471 for (x = 0; x < 2; x++) 3472 if (register_number (i.op[x].regs) != x) 3473 goto bad_register_operand; 3474 3475 /* Check for third operand for mwaitx/monitorx insn. */ 3476 if (register_number (i.op[x].regs) 3477 != (x + (i.tm.extension_opcode == 0xfb))) 3478 { 3479bad_register_operand: 3480 as_bad (_("can't use register '%s%s' as operand %d in '%s'."), 3481 register_prefix, i.op[x].regs->reg_name, x+1, 3482 i.tm.name); 3483 } 3484 3485 i.operands = 0; 3486 } 3487 3488 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix 3489 which is coded in the same place as an 8-bit immediate field 3490 would be. Here we fake an 8-bit immediate operand from the 3491 opcode suffix stored in tm.extension_opcode. 3492 3493 AVX instructions also use this encoding, for some of 3494 3 argument instructions. */ 3495 3496 gas_assert (i.imm_operands <= 1 3497 && (i.operands <= 2 3498 || ((i.tm.opcode_modifier.vex 3499 || i.tm.opcode_modifier.evex) 3500 && i.operands <= 4))); 3501 3502 exp = &im_expressions[i.imm_operands++]; 3503 i.op[i.operands].imms = exp; 3504 i.types[i.operands] = imm8; 3505 i.operands++; 3506 exp->X_op = O_constant; 3507 exp->X_add_number = i.tm.extension_opcode; 3508 i.tm.extension_opcode = None; 3509} 3510 3511 3512static int 3513check_hle (void) 3514{ 3515 switch (i.tm.opcode_modifier.hleprefixok) 3516 { 3517 default: 3518 abort (); 3519 case HLEPrefixNone: 3520 as_bad (_("invalid instruction `%s' after `%s'"), 3521 i.tm.name, i.hle_prefix); 3522 return 0; 3523 case HLEPrefixLock: 3524 if (i.prefix[LOCK_PREFIX]) 3525 return 1; 3526 as_bad (_("missing `lock' with `%s'"), i.hle_prefix); 3527 return 0; 3528 case HLEPrefixAny: 3529 return 1; 3530 case HLEPrefixRelease: 3531 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE) 3532 { 3533 as_bad (_("instruction `%s' after `xacquire' not allowed"), 3534 i.tm.name); 3535 return 0; 3536 } 3537 if (i.mem_operands == 0 3538 || !operand_type_check (i.types[i.operands - 1], anymem)) 3539 { 3540 as_bad (_("memory destination needed for instruction `%s'" 3541 " after `xrelease'"), i.tm.name); 3542 return 0; 3543 } 3544 return 1; 3545 } 3546} 3547 3548/* This is the guts of the machine-dependent assembler. LINE points to a 3549 machine dependent instruction. This function is supposed to emit 3550 the frags/bytes it assembles to. */ 3551 3552void 3553md_assemble (char *line) 3554{ 3555 unsigned int j; 3556 char mnemonic[MAX_MNEM_SIZE], mnem_suffix; 3557 const insn_template *t; 3558 3559 /* Initialize globals. */ 3560 memset (&i, '\0', sizeof (i)); 3561 for (j = 0; j < MAX_OPERANDS; j++) 3562 i.reloc[j] = NO_RELOC; 3563 memset (disp_expressions, '\0', sizeof (disp_expressions)); 3564 memset (im_expressions, '\0', sizeof (im_expressions)); 3565 save_stack_p = save_stack; 3566 3567 /* First parse an instruction mnemonic & call i386_operand for the operands. 3568 We assume that the scrubber has arranged it so that line[0] is the valid 3569 start of a (possibly prefixed) mnemonic. */ 3570 3571 line = parse_insn (line, mnemonic); 3572 if (line == NULL) 3573 return; 3574 mnem_suffix = i.suffix; 3575 3576 line = parse_operands (line, mnemonic); 3577 this_operand = -1; 3578 xfree (i.memop1_string); 3579 i.memop1_string = NULL; 3580 if (line == NULL) 3581 return; 3582 3583 /* Now we've parsed the mnemonic into a set of templates, and have the 3584 operands at hand. */ 3585 3586 /* All intel opcodes have reversed operands except for "bound" and 3587 "enter". We also don't reverse intersegment "jmp" and "call" 3588 instructions with 2 immediate operands so that the immediate segment 3589 precedes the offset, as it does when in AT&T mode. */ 3590 if (intel_syntax 3591 && i.operands > 1 3592 && (strcmp (mnemonic, "bound") != 0) 3593 && (strcmp (mnemonic, "invlpga") != 0) 3594 && !(operand_type_check (i.types[0], imm) 3595 && operand_type_check (i.types[1], imm))) 3596 swap_operands (); 3597 3598 /* The order of the immediates should be reversed 3599 for 2 immediates extrq and insertq instructions */ 3600 if (i.imm_operands == 2 3601 && (strcmp (mnemonic, "extrq") == 0 3602 || strcmp (mnemonic, "insertq") == 0)) 3603 swap_2_operands (0, 1); 3604 3605 if (i.imm_operands) 3606 optimize_imm (); 3607 3608 /* Don't optimize displacement for movabs since it only takes 64bit 3609 displacement. */ 3610 if (i.disp_operands 3611 && i.disp_encoding != disp_encoding_32bit 3612 && (flag_code != CODE_64BIT 3613 || strcmp (mnemonic, "movabs") != 0)) 3614 optimize_disp (); 3615 3616 /* Next, we find a template that matches the given insn, 3617 making sure the overlap of the given operands types is consistent 3618 with the template operand types. */ 3619 3620 if (!(t = match_template (mnem_suffix))) 3621 return; 3622 3623 if (sse_check != check_none 3624 && !i.tm.opcode_modifier.noavx 3625 && (i.tm.cpu_flags.bitfield.cpusse 3626 || i.tm.cpu_flags.bitfield.cpusse2 3627 || i.tm.cpu_flags.bitfield.cpusse3 3628 || i.tm.cpu_flags.bitfield.cpussse3 3629 || i.tm.cpu_flags.bitfield.cpusse4_1 3630 || i.tm.cpu_flags.bitfield.cpusse4_2)) 3631 { 3632 (sse_check == check_warning 3633 ? as_warn 3634 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name); 3635 } 3636 3637 /* Zap movzx and movsx suffix. The suffix has been set from 3638 "word ptr" or "byte ptr" on the source operand in Intel syntax 3639 or extracted from mnemonic in AT&T syntax. But we'll use 3640 the destination register to choose the suffix for encoding. */ 3641 if ((i.tm.base_opcode & ~9) == 0x0fb6) 3642 { 3643 /* In Intel syntax, there must be a suffix. In AT&T syntax, if 3644 there is no suffix, the default will be byte extension. */ 3645 if (i.reg_operands != 2 3646 && !i.suffix 3647 && intel_syntax) 3648 as_bad (_("ambiguous operand size for `%s'"), i.tm.name); 3649 3650 i.suffix = 0; 3651 } 3652 3653 if (i.tm.opcode_modifier.fwait) 3654 if (!add_prefix (FWAIT_OPCODE)) 3655 return; 3656 3657 /* Check if REP prefix is OK. */ 3658 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok) 3659 { 3660 as_bad (_("invalid instruction `%s' after `%s'"), 3661 i.tm.name, i.rep_prefix); 3662 return; 3663 } 3664 3665 /* Check for lock without a lockable instruction. Destination operand 3666 must be memory unless it is xchg (0x86). */ 3667 if (i.prefix[LOCK_PREFIX] 3668 && (!i.tm.opcode_modifier.islockable 3669 || i.mem_operands == 0 3670 || (i.tm.base_opcode != 0x86 3671 && !operand_type_check (i.types[i.operands - 1], anymem)))) 3672 { 3673 as_bad (_("expecting lockable instruction after `lock'")); 3674 return; 3675 } 3676 3677 /* Check if HLE prefix is OK. */ 3678 if (i.hle_prefix && !check_hle ()) 3679 return; 3680 3681 /* Check BND prefix. */ 3682 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok) 3683 as_bad (_("expecting valid branch instruction after `bnd'")); 3684 3685 if (i.tm.cpu_flags.bitfield.cpumpx) 3686 { 3687 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX]) 3688 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions.")); 3689 else if (flag_code != CODE_16BIT 3690 ? i.prefix[ADDR_PREFIX] 3691 : i.mem_operands && !i.prefix[ADDR_PREFIX]) 3692 as_bad (_("16-bit address isn't allowed in MPX instructions")); 3693 } 3694 3695 /* Insert BND prefix. */ 3696 if (add_bnd_prefix 3697 && i.tm.opcode_modifier.bndprefixok 3698 && !i.prefix[BND_PREFIX]) 3699 add_prefix (BND_PREFIX_OPCODE); 3700 3701 /* Check string instruction segment overrides. */ 3702 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0) 3703 { 3704 if (!check_string ()) 3705 return; 3706 i.disp_operands = 0; 3707 } 3708 3709 if (!process_suffix ()) 3710 return; 3711 3712 /* Update operand types. */ 3713 for (j = 0; j < i.operands; j++) 3714 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]); 3715 3716 /* Make still unresolved immediate matches conform to size of immediate 3717 given in i.suffix. */ 3718 if (!finalize_imm ()) 3719 return; 3720 3721 if (i.types[0].bitfield.imm1) 3722 i.imm_operands = 0; /* kludge for shift insns. */ 3723 3724 /* We only need to check those implicit registers for instructions 3725 with 3 operands or less. */ 3726 if (i.operands <= 3) 3727 for (j = 0; j < i.operands; j++) 3728 if (i.types[j].bitfield.inoutportreg 3729 || i.types[j].bitfield.shiftcount 3730 || i.types[j].bitfield.acc 3731 || i.types[j].bitfield.floatacc) 3732 i.reg_operands--; 3733 3734 /* ImmExt should be processed after SSE2AVX. */ 3735 if (!i.tm.opcode_modifier.sse2avx 3736 && i.tm.opcode_modifier.immext) 3737 process_immext (); 3738 3739 /* For insns with operands there are more diddles to do to the opcode. */ 3740 if (i.operands) 3741 { 3742 if (!process_operands ()) 3743 return; 3744 } 3745 else if (!quiet_warnings && i.tm.opcode_modifier.ugh) 3746 { 3747 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ 3748 as_warn (_("translating to `%sp'"), i.tm.name); 3749 } 3750 3751 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex) 3752 { 3753 if (flag_code == CODE_16BIT) 3754 { 3755 as_bad (_("instruction `%s' isn't supported in 16-bit mode."), 3756 i.tm.name); 3757 return; 3758 } 3759 3760 if (i.tm.opcode_modifier.vex) 3761 build_vex_prefix (t); 3762 else 3763 build_evex_prefix (); 3764 } 3765 3766 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4 3767 instructions may define INT_OPCODE as well, so avoid this corner 3768 case for those instructions that use MODRM. */ 3769 if (i.tm.base_opcode == INT_OPCODE 3770 && !i.tm.opcode_modifier.modrm 3771 && i.op[0].imms->X_add_number == 3) 3772 { 3773 i.tm.base_opcode = INT3_OPCODE; 3774 i.imm_operands = 0; 3775 } 3776 3777 if ((i.tm.opcode_modifier.jump 3778 || i.tm.opcode_modifier.jumpbyte 3779 || i.tm.opcode_modifier.jumpdword) 3780 && i.op[0].disps->X_op == O_constant) 3781 { 3782 /* Convert "jmp constant" (and "call constant") to a jump (call) to 3783 the absolute address given by the constant. Since ix86 jumps and 3784 calls are pc relative, we need to generate a reloc. */ 3785 i.op[0].disps->X_add_symbol = &abs_symbol; 3786 i.op[0].disps->X_op = O_symbol; 3787 } 3788 3789 if (i.tm.opcode_modifier.rex64) 3790 i.rex |= REX_W; 3791 3792 /* For 8 bit registers we need an empty rex prefix. Also if the 3793 instruction already has a prefix, we need to convert old 3794 registers to new ones. */ 3795 3796 if ((i.types[0].bitfield.reg8 3797 && (i.op[0].regs->reg_flags & RegRex64) != 0) 3798 || (i.types[1].bitfield.reg8 3799 && (i.op[1].regs->reg_flags & RegRex64) != 0) 3800 || ((i.types[0].bitfield.reg8 3801 || i.types[1].bitfield.reg8) 3802 && i.rex != 0)) 3803 { 3804 int x; 3805 3806 i.rex |= REX_OPCODE; 3807 for (x = 0; x < 2; x++) 3808 { 3809 /* Look for 8 bit operand that uses old registers. */ 3810 if (i.types[x].bitfield.reg8 3811 && (i.op[x].regs->reg_flags & RegRex64) == 0) 3812 { 3813 /* In case it is "hi" register, give up. */ 3814 if (i.op[x].regs->reg_num > 3) 3815 as_bad (_("can't encode register '%s%s' in an " 3816 "instruction requiring REX prefix."), 3817 register_prefix, i.op[x].regs->reg_name); 3818 3819 /* Otherwise it is equivalent to the extended register. 3820 Since the encoding doesn't change this is merely 3821 cosmetic cleanup for debug output. */ 3822 3823 i.op[x].regs = i.op[x].regs + 8; 3824 } 3825 } 3826 } 3827 3828 if (i.rex != 0) 3829 add_prefix (REX_OPCODE | i.rex); 3830 3831 /* We are ready to output the insn. */ 3832 output_insn (); 3833} 3834 3835static char * 3836parse_insn (char *line, char *mnemonic) 3837{ 3838 char *l = line; 3839 char *token_start = l; 3840 char *mnem_p; 3841 int supported; 3842 const insn_template *t; 3843 char *dot_p = NULL; 3844 3845 while (1) 3846 { 3847 mnem_p = mnemonic; 3848 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) 3849 { 3850 if (*mnem_p == '.') 3851 dot_p = mnem_p; 3852 mnem_p++; 3853 if (mnem_p >= mnemonic + MAX_MNEM_SIZE) 3854 { 3855 as_bad (_("no such instruction: `%s'"), token_start); 3856 return NULL; 3857 } 3858 l++; 3859 } 3860 if (!is_space_char (*l) 3861 && *l != END_OF_INSN 3862 && (intel_syntax 3863 || (*l != PREFIX_SEPARATOR 3864 && *l != ','))) 3865 { 3866 as_bad (_("invalid character %s in mnemonic"), 3867 output_invalid (*l)); 3868 return NULL; 3869 } 3870 if (token_start == l) 3871 { 3872 if (!intel_syntax && *l == PREFIX_SEPARATOR) 3873 as_bad (_("expecting prefix; got nothing")); 3874 else 3875 as_bad (_("expecting mnemonic; got nothing")); 3876 return NULL; 3877 } 3878 3879 /* Look up instruction (or prefix) via hash table. */ 3880 current_templates = (const templates *) hash_find (op_hash, mnemonic); 3881 3882 if (*l != END_OF_INSN 3883 && (!is_space_char (*l) || l[1] != END_OF_INSN) 3884 && current_templates 3885 && current_templates->start->opcode_modifier.isprefix) 3886 { 3887 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags)) 3888 { 3889 as_bad ((flag_code != CODE_64BIT 3890 ? _("`%s' is only supported in 64-bit mode") 3891 : _("`%s' is not supported in 64-bit mode")), 3892 current_templates->start->name); 3893 return NULL; 3894 } 3895 /* If we are in 16-bit mode, do not allow addr16 or data16. 3896 Similarly, in 32-bit mode, do not allow addr32 or data32. */ 3897 if ((current_templates->start->opcode_modifier.size16 3898 || current_templates->start->opcode_modifier.size32) 3899 && flag_code != CODE_64BIT 3900 && (current_templates->start->opcode_modifier.size32 3901 ^ (flag_code == CODE_16BIT))) 3902 { 3903 as_bad (_("redundant %s prefix"), 3904 current_templates->start->name); 3905 return NULL; 3906 } 3907 /* Add prefix, checking for repeated prefixes. */ 3908 switch (add_prefix (current_templates->start->base_opcode)) 3909 { 3910 case PREFIX_EXIST: 3911 return NULL; 3912 case PREFIX_REP: 3913 if (current_templates->start->cpu_flags.bitfield.cpuhle) 3914 i.hle_prefix = current_templates->start->name; 3915 else if (current_templates->start->cpu_flags.bitfield.cpumpx) 3916 i.bnd_prefix = current_templates->start->name; 3917 else 3918 i.rep_prefix = current_templates->start->name; 3919 break; 3920 default: 3921 break; 3922 } 3923 /* Skip past PREFIX_SEPARATOR and reset token_start. */ 3924 token_start = ++l; 3925 } 3926 else 3927 break; 3928 } 3929 3930 if (!current_templates) 3931 { 3932 /* Check if we should swap operand or force 32bit displacement in 3933 encoding. */ 3934 if (mnem_p - 2 == dot_p && dot_p[1] == 's') 3935 i.swap_operand = 1; 3936 else if (mnem_p - 3 == dot_p 3937 && dot_p[1] == 'd' 3938 && dot_p[2] == '8') 3939 i.disp_encoding = disp_encoding_8bit; 3940 else if (mnem_p - 4 == dot_p 3941 && dot_p[1] == 'd' 3942 && dot_p[2] == '3' 3943 && dot_p[3] == '2') 3944 i.disp_encoding = disp_encoding_32bit; 3945 else 3946 goto check_suffix; 3947 mnem_p = dot_p; 3948 *dot_p = '\0'; 3949 current_templates = (const templates *) hash_find (op_hash, mnemonic); 3950 } 3951 3952 if (!current_templates) 3953 { 3954check_suffix: 3955 /* See if we can get a match by trimming off a suffix. */ 3956 switch (mnem_p[-1]) 3957 { 3958 case WORD_MNEM_SUFFIX: 3959 if (intel_syntax && (intel_float_operand (mnemonic) & 2)) 3960 i.suffix = SHORT_MNEM_SUFFIX; 3961 else 3962 /* Fall through. */ 3963 case BYTE_MNEM_SUFFIX: 3964 case QWORD_MNEM_SUFFIX: 3965 i.suffix = mnem_p[-1]; 3966 mnem_p[-1] = '\0'; 3967 current_templates = (const templates *) hash_find (op_hash, 3968 mnemonic); 3969 break; 3970 case SHORT_MNEM_SUFFIX: 3971 case LONG_MNEM_SUFFIX: 3972 if (!intel_syntax) 3973 { 3974 i.suffix = mnem_p[-1]; 3975 mnem_p[-1] = '\0'; 3976 current_templates = (const templates *) hash_find (op_hash, 3977 mnemonic); 3978 } 3979 break; 3980 3981 /* Intel Syntax. */ 3982 case 'd': 3983 if (intel_syntax) 3984 { 3985 if (intel_float_operand (mnemonic) == 1) 3986 i.suffix = SHORT_MNEM_SUFFIX; 3987 else 3988 i.suffix = LONG_MNEM_SUFFIX; 3989 mnem_p[-1] = '\0'; 3990 current_templates = (const templates *) hash_find (op_hash, 3991 mnemonic); 3992 } 3993 break; 3994 } 3995 if (!current_templates) 3996 { 3997 as_bad (_("no such instruction: `%s'"), token_start); 3998 return NULL; 3999 } 4000 } 4001 4002 if (current_templates->start->opcode_modifier.jump 4003 || current_templates->start->opcode_modifier.jumpbyte) 4004 { 4005 /* Check for a branch hint. We allow ",pt" and ",pn" for 4006 predict taken and predict not taken respectively. 4007 I'm not sure that branch hints actually do anything on loop 4008 and jcxz insns (JumpByte) for current Pentium4 chips. They 4009 may work in the future and it doesn't hurt to accept them 4010 now. */ 4011 if (l[0] == ',' && l[1] == 'p') 4012 { 4013 if (l[2] == 't') 4014 { 4015 if (!add_prefix (DS_PREFIX_OPCODE)) 4016 return NULL; 4017 l += 3; 4018 } 4019 else if (l[2] == 'n') 4020 { 4021 if (!add_prefix (CS_PREFIX_OPCODE)) 4022 return NULL; 4023 l += 3; 4024 } 4025 } 4026 } 4027 /* Any other comma loses. */ 4028 if (*l == ',') 4029 { 4030 as_bad (_("invalid character %s in mnemonic"), 4031 output_invalid (*l)); 4032 return NULL; 4033 } 4034 4035 /* Check if instruction is supported on specified architecture. */ 4036 supported = 0; 4037 for (t = current_templates->start; t < current_templates->end; ++t) 4038 { 4039 supported |= cpu_flags_match (t); 4040 if (supported == CPU_FLAGS_PERFECT_MATCH) 4041 goto skip; 4042 } 4043 4044 if (!(supported & CPU_FLAGS_64BIT_MATCH)) 4045 { 4046 as_bad (flag_code == CODE_64BIT 4047 ? _("`%s' is not supported in 64-bit mode") 4048 : _("`%s' is only supported in 64-bit mode"), 4049 current_templates->start->name); 4050 return NULL; 4051 } 4052 if (supported != CPU_FLAGS_PERFECT_MATCH) 4053 { 4054 as_bad (_("`%s' is not supported on `%s%s'"), 4055 current_templates->start->name, 4056 cpu_arch_name ? cpu_arch_name : default_arch, 4057 cpu_sub_arch_name ? cpu_sub_arch_name : ""); 4058 return NULL; 4059 } 4060 4061skip: 4062 if (!cpu_arch_flags.bitfield.cpui386 4063 && (flag_code != CODE_16BIT)) 4064 { 4065 as_warn (_("use .code16 to ensure correct addressing mode")); 4066 } 4067 4068 return l; 4069} 4070 4071static char * 4072parse_operands (char *l, const char *mnemonic) 4073{ 4074 char *token_start; 4075 4076 /* 1 if operand is pending after ','. */ 4077 unsigned int expecting_operand = 0; 4078 4079 /* Non-zero if operand parens not balanced. */ 4080 unsigned int paren_not_balanced; 4081 4082 while (*l != END_OF_INSN) 4083 { 4084 /* Skip optional white space before operand. */ 4085 if (is_space_char (*l)) 4086 ++l; 4087 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"') 4088 { 4089 as_bad (_("invalid character %s before operand %d"), 4090 output_invalid (*l), 4091 i.operands + 1); 4092 return NULL; 4093 } 4094 token_start = l; /* After white space. */ 4095 paren_not_balanced = 0; 4096 while (paren_not_balanced || *l != ',') 4097 { 4098 if (*l == END_OF_INSN) 4099 { 4100 if (paren_not_balanced) 4101 { 4102 if (!intel_syntax) 4103 as_bad (_("unbalanced parenthesis in operand %d."), 4104 i.operands + 1); 4105 else 4106 as_bad (_("unbalanced brackets in operand %d."), 4107 i.operands + 1); 4108 return NULL; 4109 } 4110 else 4111 break; /* we are done */ 4112 } 4113 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"') 4114 { 4115 as_bad (_("invalid character %s in operand %d"), 4116 output_invalid (*l), 4117 i.operands + 1); 4118 return NULL; 4119 } 4120 if (!intel_syntax) 4121 { 4122 if (*l == '(') 4123 ++paren_not_balanced; 4124 if (*l == ')') 4125 --paren_not_balanced; 4126 } 4127 else 4128 { 4129 if (*l == '[') 4130 ++paren_not_balanced; 4131 if (*l == ']') 4132 --paren_not_balanced; 4133 } 4134 l++; 4135 } 4136 if (l != token_start) 4137 { /* Yes, we've read in another operand. */ 4138 unsigned int operand_ok; 4139 this_operand = i.operands++; 4140 i.types[this_operand].bitfield.unspecified = 1; 4141 if (i.operands > MAX_OPERANDS) 4142 { 4143 as_bad (_("spurious operands; (%d operands/instruction max)"), 4144 MAX_OPERANDS); 4145 return NULL; 4146 } 4147 /* Now parse operand adding info to 'i' as we go along. */ 4148 END_STRING_AND_SAVE (l); 4149 4150 if (intel_syntax) 4151 operand_ok = 4152 i386_intel_operand (token_start, 4153 intel_float_operand (mnemonic)); 4154 else 4155 operand_ok = i386_att_operand (token_start); 4156 4157 RESTORE_END_STRING (l); 4158 if (!operand_ok) 4159 return NULL; 4160 } 4161 else 4162 { 4163 if (expecting_operand) 4164 { 4165 expecting_operand_after_comma: 4166 as_bad (_("expecting operand after ','; got nothing")); 4167 return NULL; 4168 } 4169 if (*l == ',') 4170 { 4171 as_bad (_("expecting operand before ','; got nothing")); 4172 return NULL; 4173 } 4174 } 4175 4176 /* Now *l must be either ',' or END_OF_INSN. */ 4177 if (*l == ',') 4178 { 4179 if (*++l == END_OF_INSN) 4180 { 4181 /* Just skip it, if it's \n complain. */ 4182 goto expecting_operand_after_comma; 4183 } 4184 expecting_operand = 1; 4185 } 4186 } 4187 return l; 4188} 4189 4190static void 4191swap_2_operands (int xchg1, int xchg2) 4192{ 4193 union i386_op temp_op; 4194 i386_operand_type temp_type; 4195 enum bfd_reloc_code_real temp_reloc; 4196 4197 temp_type = i.types[xchg2]; 4198 i.types[xchg2] = i.types[xchg1]; 4199 i.types[xchg1] = temp_type; 4200 temp_op = i.op[xchg2]; 4201 i.op[xchg2] = i.op[xchg1]; 4202 i.op[xchg1] = temp_op; 4203 temp_reloc = i.reloc[xchg2]; 4204 i.reloc[xchg2] = i.reloc[xchg1]; 4205 i.reloc[xchg1] = temp_reloc; 4206 4207 if (i.mask) 4208 { 4209 if (i.mask->operand == xchg1) 4210 i.mask->operand = xchg2; 4211 else if (i.mask->operand == xchg2) 4212 i.mask->operand = xchg1; 4213 } 4214 if (i.broadcast) 4215 { 4216 if (i.broadcast->operand == xchg1) 4217 i.broadcast->operand = xchg2; 4218 else if (i.broadcast->operand == xchg2) 4219 i.broadcast->operand = xchg1; 4220 } 4221 if (i.rounding) 4222 { 4223 if (i.rounding->operand == xchg1) 4224 i.rounding->operand = xchg2; 4225 else if (i.rounding->operand == xchg2) 4226 i.rounding->operand = xchg1; 4227 } 4228} 4229 4230static void 4231swap_operands (void) 4232{ 4233 switch (i.operands) 4234 { 4235 case 5: 4236 case 4: 4237 swap_2_operands (1, i.operands - 2); 4238 /* Fall through. */ 4239 case 3: 4240 case 2: 4241 swap_2_operands (0, i.operands - 1); 4242 break; 4243 default: 4244 abort (); 4245 } 4246 4247 if (i.mem_operands == 2) 4248 { 4249 const seg_entry *temp_seg; 4250 temp_seg = i.seg[0]; 4251 i.seg[0] = i.seg[1]; 4252 i.seg[1] = temp_seg; 4253 } 4254} 4255 4256/* Try to ensure constant immediates are represented in the smallest 4257 opcode possible. */ 4258static void 4259optimize_imm (void) 4260{ 4261 char guess_suffix = 0; 4262 int op; 4263 4264 if (i.suffix) 4265 guess_suffix = i.suffix; 4266 else if (i.reg_operands) 4267 { 4268 /* Figure out a suffix from the last register operand specified. 4269 We can't do this properly yet, ie. excluding InOutPortReg, 4270 but the following works for instructions with immediates. 4271 In any case, we can't set i.suffix yet. */ 4272 for (op = i.operands; --op >= 0;) 4273 if (i.types[op].bitfield.reg8) 4274 { 4275 guess_suffix = BYTE_MNEM_SUFFIX; 4276 break; 4277 } 4278 else if (i.types[op].bitfield.reg16) 4279 { 4280 guess_suffix = WORD_MNEM_SUFFIX; 4281 break; 4282 } 4283 else if (i.types[op].bitfield.reg32) 4284 { 4285 guess_suffix = LONG_MNEM_SUFFIX; 4286 break; 4287 } 4288 else if (i.types[op].bitfield.reg64) 4289 { 4290 guess_suffix = QWORD_MNEM_SUFFIX; 4291 break; 4292 } 4293 } 4294 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) 4295 guess_suffix = WORD_MNEM_SUFFIX; 4296 4297 for (op = i.operands; --op >= 0;) 4298 if (operand_type_check (i.types[op], imm)) 4299 { 4300 switch (i.op[op].imms->X_op) 4301 { 4302 case O_constant: 4303 /* If a suffix is given, this operand may be shortened. */ 4304 switch (guess_suffix) 4305 { 4306 case LONG_MNEM_SUFFIX: 4307 i.types[op].bitfield.imm32 = 1; 4308 i.types[op].bitfield.imm64 = 1; 4309 break; 4310 case WORD_MNEM_SUFFIX: 4311 i.types[op].bitfield.imm16 = 1; 4312 i.types[op].bitfield.imm32 = 1; 4313 i.types[op].bitfield.imm32s = 1; 4314 i.types[op].bitfield.imm64 = 1; 4315 break; 4316 case BYTE_MNEM_SUFFIX: 4317 i.types[op].bitfield.imm8 = 1; 4318 i.types[op].bitfield.imm8s = 1; 4319 i.types[op].bitfield.imm16 = 1; 4320 i.types[op].bitfield.imm32 = 1; 4321 i.types[op].bitfield.imm32s = 1; 4322 i.types[op].bitfield.imm64 = 1; 4323 break; 4324 } 4325 4326 /* If this operand is at most 16 bits, convert it 4327 to a signed 16 bit number before trying to see 4328 whether it will fit in an even smaller size. 4329 This allows a 16-bit operand such as $0xffe0 to 4330 be recognised as within Imm8S range. */ 4331 if ((i.types[op].bitfield.imm16) 4332 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) 4333 { 4334 i.op[op].imms->X_add_number = 4335 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); 4336 } 4337#ifdef BFD64 4338 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */ 4339 if ((i.types[op].bitfield.imm32) 4340 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) 4341 == 0)) 4342 { 4343 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number 4344 ^ ((offsetT) 1 << 31)) 4345 - ((offsetT) 1 << 31)); 4346 } 4347#endif 4348 i.types[op] 4349 = operand_type_or (i.types[op], 4350 smallest_imm_type (i.op[op].imms->X_add_number)); 4351 4352 /* We must avoid matching of Imm32 templates when 64bit 4353 only immediate is available. */ 4354 if (guess_suffix == QWORD_MNEM_SUFFIX) 4355 i.types[op].bitfield.imm32 = 0; 4356 break; 4357 4358 case O_absent: 4359 case O_register: 4360 abort (); 4361 4362 /* Symbols and expressions. */ 4363 default: 4364 /* Convert symbolic operand to proper sizes for matching, but don't 4365 prevent matching a set of insns that only supports sizes other 4366 than those matching the insn suffix. */ 4367 { 4368 i386_operand_type mask, allowed; 4369 const insn_template *t; 4370 4371 operand_type_set (&mask, 0); 4372 operand_type_set (&allowed, 0); 4373 4374 for (t = current_templates->start; 4375 t < current_templates->end; 4376 ++t) 4377 allowed = operand_type_or (allowed, 4378 t->operand_types[op]); 4379 switch (guess_suffix) 4380 { 4381 case QWORD_MNEM_SUFFIX: 4382 mask.bitfield.imm64 = 1; 4383 mask.bitfield.imm32s = 1; 4384 break; 4385 case LONG_MNEM_SUFFIX: 4386 mask.bitfield.imm32 = 1; 4387 break; 4388 case WORD_MNEM_SUFFIX: 4389 mask.bitfield.imm16 = 1; 4390 break; 4391 case BYTE_MNEM_SUFFIX: 4392 mask.bitfield.imm8 = 1; 4393 break; 4394 default: 4395 break; 4396 } 4397 allowed = operand_type_and (mask, allowed); 4398 if (!operand_type_all_zero (&allowed)) 4399 i.types[op] = operand_type_and (i.types[op], mask); 4400 } 4401 break; 4402 } 4403 } 4404} 4405 4406/* Try to use the smallest displacement type too. */ 4407static void 4408optimize_disp (void) 4409{ 4410 int op; 4411 4412 for (op = i.operands; --op >= 0;) 4413 if (operand_type_check (i.types[op], disp)) 4414 { 4415 if (i.op[op].disps->X_op == O_constant) 4416 { 4417 offsetT op_disp = i.op[op].disps->X_add_number; 4418 4419 if (i.types[op].bitfield.disp16 4420 && (op_disp & ~(offsetT) 0xffff) == 0) 4421 { 4422 /* If this operand is at most 16 bits, convert 4423 to a signed 16 bit number and don't use 64bit 4424 displacement. */ 4425 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000); 4426 i.types[op].bitfield.disp64 = 0; 4427 } 4428#ifdef BFD64 4429 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */ 4430 if (i.types[op].bitfield.disp32 4431 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0) 4432 { 4433 /* If this operand is at most 32 bits, convert 4434 to a signed 32 bit number and don't use 64bit 4435 displacement. */ 4436 op_disp &= (((offsetT) 2 << 31) - 1); 4437 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); 4438 i.types[op].bitfield.disp64 = 0; 4439 } 4440#endif 4441 if (!op_disp && i.types[op].bitfield.baseindex) 4442 { 4443 i.types[op].bitfield.disp8 = 0; 4444 i.types[op].bitfield.disp16 = 0; 4445 i.types[op].bitfield.disp32 = 0; 4446 i.types[op].bitfield.disp32s = 0; 4447 i.types[op].bitfield.disp64 = 0; 4448 i.op[op].disps = 0; 4449 i.disp_operands--; 4450 } 4451 else if (flag_code == CODE_64BIT) 4452 { 4453 if (fits_in_signed_long (op_disp)) 4454 { 4455 i.types[op].bitfield.disp64 = 0; 4456 i.types[op].bitfield.disp32s = 1; 4457 } 4458 if (i.prefix[ADDR_PREFIX] 4459 && fits_in_unsigned_long (op_disp)) 4460 i.types[op].bitfield.disp32 = 1; 4461 } 4462 if ((i.types[op].bitfield.disp32 4463 || i.types[op].bitfield.disp32s 4464 || i.types[op].bitfield.disp16) 4465 && fits_in_signed_byte (op_disp)) 4466 i.types[op].bitfield.disp8 = 1; 4467 } 4468 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL 4469 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL) 4470 { 4471 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, 4472 i.op[op].disps, 0, i.reloc[op]); 4473 i.types[op].bitfield.disp8 = 0; 4474 i.types[op].bitfield.disp16 = 0; 4475 i.types[op].bitfield.disp32 = 0; 4476 i.types[op].bitfield.disp32s = 0; 4477 i.types[op].bitfield.disp64 = 0; 4478 } 4479 else 4480 /* We only support 64bit displacement on constants. */ 4481 i.types[op].bitfield.disp64 = 0; 4482 } 4483} 4484 4485/* Check if operands are valid for the instruction. */ 4486 4487static int 4488check_VecOperands (const insn_template *t) 4489{ 4490 unsigned int op; 4491 4492 /* Without VSIB byte, we can't have a vector register for index. */ 4493 if (!t->opcode_modifier.vecsib 4494 && i.index_reg 4495 && (i.index_reg->reg_type.bitfield.regxmm 4496 || i.index_reg->reg_type.bitfield.regymm 4497 || i.index_reg->reg_type.bitfield.regzmm)) 4498 { 4499 i.error = unsupported_vector_index_register; 4500 return 1; 4501 } 4502 4503 /* Check if default mask is allowed. */ 4504 if (t->opcode_modifier.nodefmask 4505 && (!i.mask || i.mask->mask->reg_num == 0)) 4506 { 4507 i.error = no_default_mask; 4508 return 1; 4509 } 4510 4511 /* For VSIB byte, we need a vector register for index, and all vector 4512 registers must be distinct. */ 4513 if (t->opcode_modifier.vecsib) 4514 { 4515 if (!i.index_reg 4516 || !((t->opcode_modifier.vecsib == VecSIB128 4517 && i.index_reg->reg_type.bitfield.regxmm) 4518 || (t->opcode_modifier.vecsib == VecSIB256 4519 && i.index_reg->reg_type.bitfield.regymm) 4520 || (t->opcode_modifier.vecsib == VecSIB512 4521 && i.index_reg->reg_type.bitfield.regzmm))) 4522 { 4523 i.error = invalid_vsib_address; 4524 return 1; 4525 } 4526 4527 gas_assert (i.reg_operands == 2 || i.mask); 4528 if (i.reg_operands == 2 && !i.mask) 4529 { 4530 gas_assert (i.types[0].bitfield.regxmm 4531 || i.types[0].bitfield.regymm); 4532 gas_assert (i.types[2].bitfield.regxmm 4533 || i.types[2].bitfield.regymm); 4534 if (operand_check == check_none) 4535 return 0; 4536 if (register_number (i.op[0].regs) 4537 != register_number (i.index_reg) 4538 && register_number (i.op[2].regs) 4539 != register_number (i.index_reg) 4540 && register_number (i.op[0].regs) 4541 != register_number (i.op[2].regs)) 4542 return 0; 4543 if (operand_check == check_error) 4544 { 4545 i.error = invalid_vector_register_set; 4546 return 1; 4547 } 4548 as_warn (_("mask, index, and destination registers should be distinct")); 4549 } 4550 else if (i.reg_operands == 1 && i.mask) 4551 { 4552 if ((i.types[1].bitfield.regymm 4553 || i.types[1].bitfield.regzmm) 4554 && (register_number (i.op[1].regs) 4555 == register_number (i.index_reg))) 4556 { 4557 if (operand_check == check_error) 4558 { 4559 i.error = invalid_vector_register_set; 4560 return 1; 4561 } 4562 if (operand_check != check_none) 4563 as_warn (_("index and destination registers should be distinct")); 4564 } 4565 } 4566 } 4567 4568 /* Check if broadcast is supported by the instruction and is applied 4569 to the memory operand. */ 4570 if (i.broadcast) 4571 { 4572 int broadcasted_opnd_size; 4573 4574 /* Check if specified broadcast is supported in this instruction, 4575 and it's applied to memory operand of DWORD or QWORD type, 4576 depending on VecESize. */ 4577 if (i.broadcast->type != t->opcode_modifier.broadcast 4578 || !i.types[i.broadcast->operand].bitfield.mem 4579 || (t->opcode_modifier.vecesize == 0 4580 && !i.types[i.broadcast->operand].bitfield.dword 4581 && !i.types[i.broadcast->operand].bitfield.unspecified) 4582 || (t->opcode_modifier.vecesize == 1 4583 && !i.types[i.broadcast->operand].bitfield.qword 4584 && !i.types[i.broadcast->operand].bitfield.unspecified)) 4585 goto bad_broadcast; 4586 4587 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32; 4588 if (i.broadcast->type == BROADCAST_1TO16) 4589 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */ 4590 else if (i.broadcast->type == BROADCAST_1TO8) 4591 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */ 4592 else if (i.broadcast->type == BROADCAST_1TO4) 4593 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */ 4594 else if (i.broadcast->type == BROADCAST_1TO2) 4595 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */ 4596 else 4597 goto bad_broadcast; 4598 4599 if ((broadcasted_opnd_size == 256 4600 && !t->operand_types[i.broadcast->operand].bitfield.ymmword) 4601 || (broadcasted_opnd_size == 512 4602 && !t->operand_types[i.broadcast->operand].bitfield.zmmword)) 4603 { 4604 bad_broadcast: 4605 i.error = unsupported_broadcast; 4606 return 1; 4607 } 4608 } 4609 /* If broadcast is supported in this instruction, we need to check if 4610 operand of one-element size isn't specified without broadcast. */ 4611 else if (t->opcode_modifier.broadcast && i.mem_operands) 4612 { 4613 /* Find memory operand. */ 4614 for (op = 0; op < i.operands; op++) 4615 if (operand_type_check (i.types[op], anymem)) 4616 break; 4617 gas_assert (op < i.operands); 4618 /* Check size of the memory operand. */ 4619 if ((t->opcode_modifier.vecesize == 0 4620 && i.types[op].bitfield.dword) 4621 || (t->opcode_modifier.vecesize == 1 4622 && i.types[op].bitfield.qword)) 4623 { 4624 i.error = broadcast_needed; 4625 return 1; 4626 } 4627 } 4628 4629 /* Check if requested masking is supported. */ 4630 if (i.mask 4631 && (!t->opcode_modifier.masking 4632 || (i.mask->zeroing 4633 && t->opcode_modifier.masking == MERGING_MASKING))) 4634 { 4635 i.error = unsupported_masking; 4636 return 1; 4637 } 4638 4639 /* Check if masking is applied to dest operand. */ 4640 if (i.mask && (i.mask->operand != (int) (i.operands - 1))) 4641 { 4642 i.error = mask_not_on_destination; 4643 return 1; 4644 } 4645 4646 /* Check RC/SAE. */ 4647 if (i.rounding) 4648 { 4649 if ((i.rounding->type != saeonly 4650 && !t->opcode_modifier.staticrounding) 4651 || (i.rounding->type == saeonly 4652 && (t->opcode_modifier.staticrounding 4653 || !t->opcode_modifier.sae))) 4654 { 4655 i.error = unsupported_rc_sae; 4656 return 1; 4657 } 4658 /* If the instruction has several immediate operands and one of 4659 them is rounding, the rounding operand should be the last 4660 immediate operand. */ 4661 if (i.imm_operands > 1 4662 && i.rounding->operand != (int) (i.imm_operands - 1)) 4663 { 4664 i.error = rc_sae_operand_not_last_imm; 4665 return 1; 4666 } 4667 } 4668 4669 /* Check vector Disp8 operand. */ 4670 if (t->opcode_modifier.disp8memshift) 4671 { 4672 if (i.broadcast) 4673 i.memshift = t->opcode_modifier.vecesize ? 3 : 2; 4674 else 4675 i.memshift = t->opcode_modifier.disp8memshift; 4676 4677 for (op = 0; op < i.operands; op++) 4678 if (operand_type_check (i.types[op], disp) 4679 && i.op[op].disps->X_op == O_constant) 4680 { 4681 offsetT value = i.op[op].disps->X_add_number; 4682 int vec_disp8_ok 4683 = (i.disp_encoding != disp_encoding_32bit 4684 && fits_in_vec_disp8 (value)); 4685 if (t->operand_types [op].bitfield.vec_disp8) 4686 { 4687 if (vec_disp8_ok) 4688 i.types[op].bitfield.vec_disp8 = 1; 4689 else 4690 { 4691 /* Vector insn can only have Vec_Disp8/Disp32 in 4692 32/64bit modes, and Vec_Disp8/Disp16 in 16bit 4693 mode. */ 4694 i.types[op].bitfield.disp8 = 0; 4695 if (flag_code != CODE_16BIT) 4696 i.types[op].bitfield.disp16 = 0; 4697 } 4698 } 4699 else if (flag_code != CODE_16BIT) 4700 { 4701 /* One form of this instruction supports vector Disp8. 4702 Try vector Disp8 if we need to use Disp32. */ 4703 if (vec_disp8_ok && !fits_in_signed_byte (value)) 4704 { 4705 i.error = try_vector_disp8; 4706 return 1; 4707 } 4708 } 4709 } 4710 } 4711 else 4712 i.memshift = -1; 4713 4714 return 0; 4715} 4716 4717/* Check if operands are valid for the instruction. Update VEX 4718 operand types. */ 4719 4720static int 4721VEX_check_operands (const insn_template *t) 4722{ 4723 /* VREX is only valid with EVEX prefix. */ 4724 if (i.need_vrex && !t->opcode_modifier.evex) 4725 { 4726 i.error = invalid_register_operand; 4727 return 1; 4728 } 4729 4730 if (!t->opcode_modifier.vex) 4731 return 0; 4732 4733 /* Only check VEX_Imm4, which must be the first operand. */ 4734 if (t->operand_types[0].bitfield.vec_imm4) 4735 { 4736 if (i.op[0].imms->X_op != O_constant 4737 || !fits_in_imm4 (i.op[0].imms->X_add_number)) 4738 { 4739 i.error = bad_imm4; 4740 return 1; 4741 } 4742 4743 /* Turn off Imm8 so that update_imm won't complain. */ 4744 i.types[0] = vec_imm4; 4745 } 4746 4747 return 0; 4748} 4749 4750static const insn_template * 4751match_template (char mnem_suffix) 4752{ 4753 /* Points to template once we've found it. */ 4754 const insn_template *t; 4755 i386_operand_type overlap0, overlap1, overlap2, overlap3; 4756 i386_operand_type overlap4; 4757 unsigned int found_reverse_match; 4758 i386_opcode_modifier suffix_check, mnemsuf_check; 4759 i386_operand_type operand_types [MAX_OPERANDS]; 4760 int addr_prefix_disp; 4761 unsigned int j; 4762 unsigned int found_cpu_match; 4763 unsigned int check_register; 4764 enum i386_error specific_error = 0; 4765 4766#if MAX_OPERANDS != 5 4767# error "MAX_OPERANDS must be 5." 4768#endif 4769 4770 found_reverse_match = 0; 4771 addr_prefix_disp = -1; 4772 4773 memset (&suffix_check, 0, sizeof (suffix_check)); 4774 if (i.suffix == BYTE_MNEM_SUFFIX) 4775 suffix_check.no_bsuf = 1; 4776 else if (i.suffix == WORD_MNEM_SUFFIX) 4777 suffix_check.no_wsuf = 1; 4778 else if (i.suffix == SHORT_MNEM_SUFFIX) 4779 suffix_check.no_ssuf = 1; 4780 else if (i.suffix == LONG_MNEM_SUFFIX) 4781 suffix_check.no_lsuf = 1; 4782 else if (i.suffix == QWORD_MNEM_SUFFIX) 4783 suffix_check.no_qsuf = 1; 4784 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX) 4785 suffix_check.no_ldsuf = 1; 4786 4787 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check)); 4788 if (intel_syntax) 4789 { 4790 switch (mnem_suffix) 4791 { 4792 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break; 4793 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break; 4794 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break; 4795 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break; 4796 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break; 4797 } 4798 } 4799 4800 /* Must have right number of operands. */ 4801 i.error = number_of_operands_mismatch; 4802 4803 for (t = current_templates->start; t < current_templates->end; t++) 4804 { 4805 addr_prefix_disp = -1; 4806 4807 if (i.operands != t->operands) 4808 continue; 4809 4810 /* Check processor support. */ 4811 i.error = unsupported; 4812 found_cpu_match = (cpu_flags_match (t) 4813 == CPU_FLAGS_PERFECT_MATCH); 4814 if (!found_cpu_match) 4815 continue; 4816 4817 /* Check old gcc support. */ 4818 i.error = old_gcc_only; 4819 if (!old_gcc && t->opcode_modifier.oldgcc) 4820 continue; 4821 4822 /* Check AT&T mnemonic. */ 4823 i.error = unsupported_with_intel_mnemonic; 4824 if (intel_mnemonic && t->opcode_modifier.attmnemonic) 4825 continue; 4826 4827 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */ 4828 i.error = unsupported_syntax; 4829 if ((intel_syntax && t->opcode_modifier.attsyntax) 4830 || (!intel_syntax && t->opcode_modifier.intelsyntax) 4831 || (intel64 && t->opcode_modifier.amd64) 4832 || (!intel64 && t->opcode_modifier.intel64)) 4833 continue; 4834 4835 /* Check the suffix, except for some instructions in intel mode. */ 4836 i.error = invalid_instruction_suffix; 4837 if ((!intel_syntax || !t->opcode_modifier.ignoresize) 4838 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf) 4839 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf) 4840 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf) 4841 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf) 4842 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf) 4843 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf))) 4844 continue; 4845 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */ 4846 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf) 4847 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf) 4848 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf) 4849 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf) 4850 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf) 4851 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf)) 4852 continue; 4853 4854 if (!operand_size_match (t)) 4855 continue; 4856 4857 for (j = 0; j < MAX_OPERANDS; j++) 4858 operand_types[j] = t->operand_types[j]; 4859 4860 /* In general, don't allow 64-bit operands in 32-bit mode. */ 4861 if (i.suffix == QWORD_MNEM_SUFFIX 4862 && flag_code != CODE_64BIT 4863 && (intel_syntax 4864 ? (!t->opcode_modifier.ignoresize 4865 && !intel_float_operand (t->name)) 4866 : intel_float_operand (t->name) != 2) 4867 && ((!operand_types[0].bitfield.regmmx 4868 && !operand_types[0].bitfield.regxmm 4869 && !operand_types[0].bitfield.regymm 4870 && !operand_types[0].bitfield.regzmm) 4871 || (!operand_types[t->operands > 1].bitfield.regmmx 4872 && operand_types[t->operands > 1].bitfield.regxmm 4873 && operand_types[t->operands > 1].bitfield.regymm 4874 && operand_types[t->operands > 1].bitfield.regzmm)) 4875 && (t->base_opcode != 0x0fc7 4876 || t->extension_opcode != 1 /* cmpxchg8b */)) 4877 continue; 4878 4879 /* In general, don't allow 32-bit operands on pre-386. */ 4880 else if (i.suffix == LONG_MNEM_SUFFIX 4881 && !cpu_arch_flags.bitfield.cpui386 4882 && (intel_syntax 4883 ? (!t->opcode_modifier.ignoresize 4884 && !intel_float_operand (t->name)) 4885 : intel_float_operand (t->name) != 2) 4886 && ((!operand_types[0].bitfield.regmmx 4887 && !operand_types[0].bitfield.regxmm) 4888 || (!operand_types[t->operands > 1].bitfield.regmmx 4889 && operand_types[t->operands > 1].bitfield.regxmm))) 4890 continue; 4891 4892 /* Do not verify operands when there are none. */ 4893 else 4894 { 4895 if (!t->operands) 4896 /* We've found a match; break out of loop. */ 4897 break; 4898 } 4899 4900 /* Address size prefix will turn Disp64/Disp32/Disp16 operand 4901 into Disp32/Disp16/Disp32 operand. */ 4902 if (i.prefix[ADDR_PREFIX] != 0) 4903 { 4904 /* There should be only one Disp operand. */ 4905 switch (flag_code) 4906 { 4907 case CODE_16BIT: 4908 for (j = 0; j < MAX_OPERANDS; j++) 4909 { 4910 if (operand_types[j].bitfield.disp16) 4911 { 4912 addr_prefix_disp = j; 4913 operand_types[j].bitfield.disp32 = 1; 4914 operand_types[j].bitfield.disp16 = 0; 4915 break; 4916 } 4917 } 4918 break; 4919 case CODE_32BIT: 4920 for (j = 0; j < MAX_OPERANDS; j++) 4921 { 4922 if (operand_types[j].bitfield.disp32) 4923 { 4924 addr_prefix_disp = j; 4925 operand_types[j].bitfield.disp32 = 0; 4926 operand_types[j].bitfield.disp16 = 1; 4927 break; 4928 } 4929 } 4930 break; 4931 case CODE_64BIT: 4932 for (j = 0; j < MAX_OPERANDS; j++) 4933 { 4934 if (operand_types[j].bitfield.disp64) 4935 { 4936 addr_prefix_disp = j; 4937 operand_types[j].bitfield.disp64 = 0; 4938 operand_types[j].bitfield.disp32 = 1; 4939 break; 4940 } 4941 } 4942 break; 4943 } 4944 } 4945 4946 /* Force 0x8b encoding for "mov foo@GOT, %eax". */ 4947 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0) 4948 continue; 4949 4950 /* We check register size if needed. */ 4951 check_register = t->opcode_modifier.checkregsize; 4952 overlap0 = operand_type_and (i.types[0], operand_types[0]); 4953 switch (t->operands) 4954 { 4955 case 1: 4956 if (!operand_type_match (overlap0, i.types[0])) 4957 continue; 4958 break; 4959 case 2: 4960 /* xchg %eax, %eax is a special case. It is an aliase for nop 4961 only in 32bit mode and we can use opcode 0x90. In 64bit 4962 mode, we can't use 0x90 for xchg %eax, %eax since it should 4963 zero-extend %eax to %rax. */ 4964 if (flag_code == CODE_64BIT 4965 && t->base_opcode == 0x90 4966 && operand_type_equal (&i.types [0], &acc32) 4967 && operand_type_equal (&i.types [1], &acc32)) 4968 continue; 4969 if (i.swap_operand) 4970 { 4971 /* If we swap operand in encoding, we either match 4972 the next one or reverse direction of operands. */ 4973 if (t->opcode_modifier.s) 4974 continue; 4975 else if (t->opcode_modifier.d) 4976 goto check_reverse; 4977 } 4978 /* Fall through. */ 4979 4980 case 3: 4981 /* If we swap operand in encoding, we match the next one. */ 4982 if (i.swap_operand && t->opcode_modifier.s) 4983 continue; 4984 /* Fall through. */ 4985 case 4: 4986 case 5: 4987 overlap1 = operand_type_and (i.types[1], operand_types[1]); 4988 if (!operand_type_match (overlap0, i.types[0]) 4989 || !operand_type_match (overlap1, i.types[1]) 4990 || (check_register 4991 && !operand_type_register_match (overlap0, i.types[0], 4992 operand_types[0], 4993 overlap1, i.types[1], 4994 operand_types[1]))) 4995 { 4996 /* Check if other direction is valid ... */ 4997 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd) 4998 continue; 4999 5000check_reverse: 5001 /* Try reversing direction of operands. */ 5002 overlap0 = operand_type_and (i.types[0], operand_types[1]); 5003 overlap1 = operand_type_and (i.types[1], operand_types[0]); 5004 if (!operand_type_match (overlap0, i.types[0]) 5005 || !operand_type_match (overlap1, i.types[1]) 5006 || (check_register 5007 && !operand_type_register_match (overlap0, 5008 i.types[0], 5009 operand_types[1], 5010 overlap1, 5011 i.types[1], 5012 operand_types[0]))) 5013 { 5014 /* Does not match either direction. */ 5015 continue; 5016 } 5017 /* found_reverse_match holds which of D or FloatDR 5018 we've found. */ 5019 if (t->opcode_modifier.d) 5020 found_reverse_match = Opcode_D; 5021 else if (t->opcode_modifier.floatd) 5022 found_reverse_match = Opcode_FloatD; 5023 else 5024 found_reverse_match = 0; 5025 if (t->opcode_modifier.floatr) 5026 found_reverse_match |= Opcode_FloatR; 5027 } 5028 else 5029 { 5030 /* Found a forward 2 operand match here. */ 5031 switch (t->operands) 5032 { 5033 case 5: 5034 overlap4 = operand_type_and (i.types[4], 5035 operand_types[4]); 5036 /* Fall through. */ 5037 case 4: 5038 overlap3 = operand_type_and (i.types[3], 5039 operand_types[3]); 5040 /* Fall through. */ 5041 case 3: 5042 overlap2 = operand_type_and (i.types[2], 5043 operand_types[2]); 5044 break; 5045 } 5046 5047 switch (t->operands) 5048 { 5049 case 5: 5050 if (!operand_type_match (overlap4, i.types[4]) 5051 || !operand_type_register_match (overlap3, 5052 i.types[3], 5053 operand_types[3], 5054 overlap4, 5055 i.types[4], 5056 operand_types[4])) 5057 continue; 5058 /* Fall through. */ 5059 case 4: 5060 if (!operand_type_match (overlap3, i.types[3]) 5061 || (check_register 5062 && !operand_type_register_match (overlap2, 5063 i.types[2], 5064 operand_types[2], 5065 overlap3, 5066 i.types[3], 5067 operand_types[3]))) 5068 continue; 5069 /* Fall through. */ 5070 case 3: 5071 /* Here we make use of the fact that there are no 5072 reverse match 3 operand instructions, and all 3 5073 operand instructions only need to be checked for 5074 register consistency between operands 2 and 3. */ 5075 if (!operand_type_match (overlap2, i.types[2]) 5076 || (check_register 5077 && !operand_type_register_match (overlap1, 5078 i.types[1], 5079 operand_types[1], 5080 overlap2, 5081 i.types[2], 5082 operand_types[2]))) 5083 continue; 5084 break; 5085 } 5086 } 5087 /* Found either forward/reverse 2, 3 or 4 operand match here: 5088 slip through to break. */ 5089 } 5090 if (!found_cpu_match) 5091 { 5092 found_reverse_match = 0; 5093 continue; 5094 } 5095 5096 /* Check if vector and VEX operands are valid. */ 5097 if (check_VecOperands (t) || VEX_check_operands (t)) 5098 { 5099 specific_error = i.error; 5100 continue; 5101 } 5102 5103 /* We've found a match; break out of loop. */ 5104 break; 5105 } 5106 5107 if (t == current_templates->end) 5108 { 5109 /* We found no match. */ 5110 const char *err_msg; 5111 switch (specific_error ? specific_error : i.error) 5112 { 5113 default: 5114 abort (); 5115 case operand_size_mismatch: 5116 err_msg = _("operand size mismatch"); 5117 break; 5118 case operand_type_mismatch: 5119 err_msg = _("operand type mismatch"); 5120 break; 5121 case register_type_mismatch: 5122 err_msg = _("register type mismatch"); 5123 break; 5124 case number_of_operands_mismatch: 5125 err_msg = _("number of operands mismatch"); 5126 break; 5127 case invalid_instruction_suffix: 5128 err_msg = _("invalid instruction suffix"); 5129 break; 5130 case bad_imm4: 5131 err_msg = _("constant doesn't fit in 4 bits"); 5132 break; 5133 case old_gcc_only: 5134 err_msg = _("only supported with old gcc"); 5135 break; 5136 case unsupported_with_intel_mnemonic: 5137 err_msg = _("unsupported with Intel mnemonic"); 5138 break; 5139 case unsupported_syntax: 5140 err_msg = _("unsupported syntax"); 5141 break; 5142 case unsupported: 5143 as_bad (_("unsupported instruction `%s'"), 5144 current_templates->start->name); 5145 return NULL; 5146 case invalid_vsib_address: 5147 err_msg = _("invalid VSIB address"); 5148 break; 5149 case invalid_vector_register_set: 5150 err_msg = _("mask, index, and destination registers must be distinct"); 5151 break; 5152 case unsupported_vector_index_register: 5153 err_msg = _("unsupported vector index register"); 5154 break; 5155 case unsupported_broadcast: 5156 err_msg = _("unsupported broadcast"); 5157 break; 5158 case broadcast_not_on_src_operand: 5159 err_msg = _("broadcast not on source memory operand"); 5160 break; 5161 case broadcast_needed: 5162 err_msg = _("broadcast is needed for operand of such type"); 5163 break; 5164 case unsupported_masking: 5165 err_msg = _("unsupported masking"); 5166 break; 5167 case mask_not_on_destination: 5168 err_msg = _("mask not on destination operand"); 5169 break; 5170 case no_default_mask: 5171 err_msg = _("default mask isn't allowed"); 5172 break; 5173 case unsupported_rc_sae: 5174 err_msg = _("unsupported static rounding/sae"); 5175 break; 5176 case rc_sae_operand_not_last_imm: 5177 if (intel_syntax) 5178 err_msg = _("RC/SAE operand must precede immediate operands"); 5179 else 5180 err_msg = _("RC/SAE operand must follow immediate operands"); 5181 break; 5182 case invalid_register_operand: 5183 err_msg = _("invalid register operand"); 5184 break; 5185 } 5186 as_bad (_("%s for `%s'"), err_msg, 5187 current_templates->start->name); 5188 return NULL; 5189 } 5190 5191 if (!quiet_warnings) 5192 { 5193 if (!intel_syntax 5194 && (i.types[0].bitfield.jumpabsolute 5195 != operand_types[0].bitfield.jumpabsolute)) 5196 { 5197 as_warn (_("indirect %s without `*'"), t->name); 5198 } 5199 5200 if (t->opcode_modifier.isprefix 5201 && t->opcode_modifier.ignoresize) 5202 { 5203 /* Warn them that a data or address size prefix doesn't 5204 affect assembly of the next line of code. */ 5205 as_warn (_("stand-alone `%s' prefix"), t->name); 5206 } 5207 } 5208 5209 /* Copy the template we found. */ 5210 i.tm = *t; 5211 5212 if (addr_prefix_disp != -1) 5213 i.tm.operand_types[addr_prefix_disp] 5214 = operand_types[addr_prefix_disp]; 5215 5216 if (found_reverse_match) 5217 { 5218 /* If we found a reverse match we must alter the opcode 5219 direction bit. found_reverse_match holds bits to change 5220 (different for int & float insns). */ 5221 5222 i.tm.base_opcode ^= found_reverse_match; 5223 5224 i.tm.operand_types[0] = operand_types[1]; 5225 i.tm.operand_types[1] = operand_types[0]; 5226 } 5227 5228 return t; 5229} 5230 5231static int 5232check_string (void) 5233{ 5234 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1; 5235 if (i.tm.operand_types[mem_op].bitfield.esseg) 5236 { 5237 if (i.seg[0] != NULL && i.seg[0] != &es) 5238 { 5239 as_bad (_("`%s' operand %d must use `%ses' segment"), 5240 i.tm.name, 5241 mem_op + 1, 5242 register_prefix); 5243 return 0; 5244 } 5245 /* There's only ever one segment override allowed per instruction. 5246 This instruction possibly has a legal segment override on the 5247 second operand, so copy the segment to where non-string 5248 instructions store it, allowing common code. */ 5249 i.seg[0] = i.seg[1]; 5250 } 5251 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg) 5252 { 5253 if (i.seg[1] != NULL && i.seg[1] != &es) 5254 { 5255 as_bad (_("`%s' operand %d must use `%ses' segment"), 5256 i.tm.name, 5257 mem_op + 2, 5258 register_prefix); 5259 return 0; 5260 } 5261 } 5262 return 1; 5263} 5264 5265static int 5266process_suffix (void) 5267{ 5268 /* If matched instruction specifies an explicit instruction mnemonic 5269 suffix, use it. */ 5270 if (i.tm.opcode_modifier.size16) 5271 i.suffix = WORD_MNEM_SUFFIX; 5272 else if (i.tm.opcode_modifier.size32) 5273 i.suffix = LONG_MNEM_SUFFIX; 5274 else if (i.tm.opcode_modifier.size64) 5275 i.suffix = QWORD_MNEM_SUFFIX; 5276 else if (i.reg_operands) 5277 { 5278 /* If there's no instruction mnemonic suffix we try to invent one 5279 based on register operands. */ 5280 if (!i.suffix) 5281 { 5282 /* We take i.suffix from the last register operand specified, 5283 Destination register type is more significant than source 5284 register type. crc32 in SSE4.2 prefers source register 5285 type. */ 5286 if (i.tm.base_opcode == 0xf20f38f1) 5287 { 5288 if (i.types[0].bitfield.reg16) 5289 i.suffix = WORD_MNEM_SUFFIX; 5290 else if (i.types[0].bitfield.reg32) 5291 i.suffix = LONG_MNEM_SUFFIX; 5292 else if (i.types[0].bitfield.reg64) 5293 i.suffix = QWORD_MNEM_SUFFIX; 5294 } 5295 else if (i.tm.base_opcode == 0xf20f38f0) 5296 { 5297 if (i.types[0].bitfield.reg8) 5298 i.suffix = BYTE_MNEM_SUFFIX; 5299 } 5300 5301 if (!i.suffix) 5302 { 5303 int op; 5304 5305 if (i.tm.base_opcode == 0xf20f38f1 5306 || i.tm.base_opcode == 0xf20f38f0) 5307 { 5308 /* We have to know the operand size for crc32. */ 5309 as_bad (_("ambiguous memory operand size for `%s`"), 5310 i.tm.name); 5311 return 0; 5312 } 5313 5314 for (op = i.operands; --op >= 0;) 5315 if (!i.tm.operand_types[op].bitfield.inoutportreg) 5316 { 5317 if (i.types[op].bitfield.reg8) 5318 { 5319 i.suffix = BYTE_MNEM_SUFFIX; 5320 break; 5321 } 5322 else if (i.types[op].bitfield.reg16) 5323 { 5324 i.suffix = WORD_MNEM_SUFFIX; 5325 break; 5326 } 5327 else if (i.types[op].bitfield.reg32) 5328 { 5329 i.suffix = LONG_MNEM_SUFFIX; 5330 break; 5331 } 5332 else if (i.types[op].bitfield.reg64) 5333 { 5334 i.suffix = QWORD_MNEM_SUFFIX; 5335 break; 5336 } 5337 } 5338 } 5339 } 5340 else if (i.suffix == BYTE_MNEM_SUFFIX) 5341 { 5342 if (intel_syntax 5343 && i.tm.opcode_modifier.ignoresize 5344 && i.tm.opcode_modifier.no_bsuf) 5345 i.suffix = 0; 5346 else if (!check_byte_reg ()) 5347 return 0; 5348 } 5349 else if (i.suffix == LONG_MNEM_SUFFIX) 5350 { 5351 if (intel_syntax 5352 && i.tm.opcode_modifier.ignoresize 5353 && i.tm.opcode_modifier.no_lsuf) 5354 i.suffix = 0; 5355 else if (!check_long_reg ()) 5356 return 0; 5357 } 5358 else if (i.suffix == QWORD_MNEM_SUFFIX) 5359 { 5360 if (intel_syntax 5361 && i.tm.opcode_modifier.ignoresize 5362 && i.tm.opcode_modifier.no_qsuf) 5363 i.suffix = 0; 5364 else if (!check_qword_reg ()) 5365 return 0; 5366 } 5367 else if (i.suffix == WORD_MNEM_SUFFIX) 5368 { 5369 if (intel_syntax 5370 && i.tm.opcode_modifier.ignoresize 5371 && i.tm.opcode_modifier.no_wsuf) 5372 i.suffix = 0; 5373 else if (!check_word_reg ()) 5374 return 0; 5375 } 5376 else if (i.suffix == XMMWORD_MNEM_SUFFIX 5377 || i.suffix == YMMWORD_MNEM_SUFFIX 5378 || i.suffix == ZMMWORD_MNEM_SUFFIX) 5379 { 5380 /* Skip if the instruction has x/y/z suffix. match_template 5381 should check if it is a valid suffix. */ 5382 } 5383 else if (intel_syntax && i.tm.opcode_modifier.ignoresize) 5384 /* Do nothing if the instruction is going to ignore the prefix. */ 5385 ; 5386 else 5387 abort (); 5388 } 5389 else if (i.tm.opcode_modifier.defaultsize 5390 && !i.suffix 5391 /* exclude fldenv/frstor/fsave/fstenv */ 5392 && i.tm.opcode_modifier.no_ssuf) 5393 { 5394 i.suffix = stackop_size; 5395 } 5396 else if (intel_syntax 5397 && !i.suffix 5398 && (i.tm.operand_types[0].bitfield.jumpabsolute 5399 || i.tm.opcode_modifier.jumpbyte 5400 || i.tm.opcode_modifier.jumpintersegment 5401 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */ 5402 && i.tm.extension_opcode <= 3))) 5403 { 5404 switch (flag_code) 5405 { 5406 case CODE_64BIT: 5407 if (!i.tm.opcode_modifier.no_qsuf) 5408 { 5409 i.suffix = QWORD_MNEM_SUFFIX; 5410 break; 5411 } 5412 /* Fall through. */ 5413 case CODE_32BIT: 5414 if (!i.tm.opcode_modifier.no_lsuf) 5415 i.suffix = LONG_MNEM_SUFFIX; 5416 break; 5417 case CODE_16BIT: 5418 if (!i.tm.opcode_modifier.no_wsuf) 5419 i.suffix = WORD_MNEM_SUFFIX; 5420 break; 5421 } 5422 } 5423 5424 if (!i.suffix) 5425 { 5426 if (!intel_syntax) 5427 { 5428 if (i.tm.opcode_modifier.w) 5429 { 5430 as_bad (_("no instruction mnemonic suffix given and " 5431 "no register operands; can't size instruction")); 5432 return 0; 5433 } 5434 } 5435 else 5436 { 5437 unsigned int suffixes; 5438 5439 suffixes = !i.tm.opcode_modifier.no_bsuf; 5440 if (!i.tm.opcode_modifier.no_wsuf) 5441 suffixes |= 1 << 1; 5442 if (!i.tm.opcode_modifier.no_lsuf) 5443 suffixes |= 1 << 2; 5444 if (!i.tm.opcode_modifier.no_ldsuf) 5445 suffixes |= 1 << 3; 5446 if (!i.tm.opcode_modifier.no_ssuf) 5447 suffixes |= 1 << 4; 5448 if (!i.tm.opcode_modifier.no_qsuf) 5449 suffixes |= 1 << 5; 5450 5451 /* There are more than suffix matches. */ 5452 if (i.tm.opcode_modifier.w 5453 || ((suffixes & (suffixes - 1)) 5454 && !i.tm.opcode_modifier.defaultsize 5455 && !i.tm.opcode_modifier.ignoresize)) 5456 { 5457 as_bad (_("ambiguous operand size for `%s'"), i.tm.name); 5458 return 0; 5459 } 5460 } 5461 } 5462 5463 /* Change the opcode based on the operand size given by i.suffix; 5464 We don't need to change things for byte insns. */ 5465 5466 if (i.suffix 5467 && i.suffix != BYTE_MNEM_SUFFIX 5468 && i.suffix != XMMWORD_MNEM_SUFFIX 5469 && i.suffix != YMMWORD_MNEM_SUFFIX 5470 && i.suffix != ZMMWORD_MNEM_SUFFIX) 5471 { 5472 /* It's not a byte, select word/dword operation. */ 5473 if (i.tm.opcode_modifier.w) 5474 { 5475 if (i.tm.opcode_modifier.shortform) 5476 i.tm.base_opcode |= 8; 5477 else 5478 i.tm.base_opcode |= 1; 5479 } 5480 5481 /* Now select between word & dword operations via the operand 5482 size prefix, except for instructions that will ignore this 5483 prefix anyway. */ 5484 if (i.tm.opcode_modifier.addrprefixop0) 5485 { 5486 /* The address size override prefix changes the size of the 5487 first operand. */ 5488 if ((flag_code == CODE_32BIT 5489 && i.op->regs[0].reg_type.bitfield.reg16) 5490 || (flag_code != CODE_32BIT 5491 && i.op->regs[0].reg_type.bitfield.reg32)) 5492 if (!add_prefix (ADDR_PREFIX_OPCODE)) 5493 return 0; 5494 } 5495 else if (i.suffix != QWORD_MNEM_SUFFIX 5496 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX 5497 && !i.tm.opcode_modifier.ignoresize 5498 && !i.tm.opcode_modifier.floatmf 5499 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) 5500 || (flag_code == CODE_64BIT 5501 && i.tm.opcode_modifier.jumpbyte))) 5502 { 5503 unsigned int prefix = DATA_PREFIX_OPCODE; 5504 5505 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */ 5506 prefix = ADDR_PREFIX_OPCODE; 5507 5508 if (!add_prefix (prefix)) 5509 return 0; 5510 } 5511 5512 /* Set mode64 for an operand. */ 5513 if (i.suffix == QWORD_MNEM_SUFFIX 5514 && flag_code == CODE_64BIT 5515 && !i.tm.opcode_modifier.norex64) 5516 { 5517 /* Special case for xchg %rax,%rax. It is NOP and doesn't 5518 need rex64. cmpxchg8b is also a special case. */ 5519 if (! (i.operands == 2 5520 && i.tm.base_opcode == 0x90 5521 && i.tm.extension_opcode == None 5522 && operand_type_equal (&i.types [0], &acc64) 5523 && operand_type_equal (&i.types [1], &acc64)) 5524 && ! (i.operands == 1 5525 && i.tm.base_opcode == 0xfc7 5526 && i.tm.extension_opcode == 1 5527 && !operand_type_check (i.types [0], reg) 5528 && operand_type_check (i.types [0], anymem))) 5529 i.rex |= REX_W; 5530 } 5531 5532 /* Size floating point instruction. */ 5533 if (i.suffix == LONG_MNEM_SUFFIX) 5534 if (i.tm.opcode_modifier.floatmf) 5535 i.tm.base_opcode ^= 4; 5536 } 5537 5538 return 1; 5539} 5540 5541static int 5542check_byte_reg (void) 5543{ 5544 int op; 5545 5546 for (op = i.operands; --op >= 0;) 5547 { 5548 /* If this is an eight bit register, it's OK. If it's the 16 or 5549 32 bit version of an eight bit register, we will just use the 5550 low portion, and that's OK too. */ 5551 if (i.types[op].bitfield.reg8) 5552 continue; 5553 5554 /* I/O port address operands are OK too. */ 5555 if (i.tm.operand_types[op].bitfield.inoutportreg) 5556 continue; 5557 5558 /* crc32 doesn't generate this warning. */ 5559 if (i.tm.base_opcode == 0xf20f38f0) 5560 continue; 5561 5562 if ((i.types[op].bitfield.reg16 5563 || i.types[op].bitfield.reg32 5564 || i.types[op].bitfield.reg64) 5565 && i.op[op].regs->reg_num < 4 5566 /* Prohibit these changes in 64bit mode, since the lowering 5567 would be more complicated. */ 5568 && flag_code != CODE_64BIT) 5569 { 5570#if REGISTER_WARNINGS 5571 if (!quiet_warnings) 5572 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), 5573 register_prefix, 5574 (i.op[op].regs + (i.types[op].bitfield.reg16 5575 ? REGNAM_AL - REGNAM_AX 5576 : REGNAM_AL - REGNAM_EAX))->reg_name, 5577 register_prefix, 5578 i.op[op].regs->reg_name, 5579 i.suffix); 5580#endif 5581 continue; 5582 } 5583 /* Any other register is bad. */ 5584 if (i.types[op].bitfield.reg16 5585 || i.types[op].bitfield.reg32 5586 || i.types[op].bitfield.reg64 5587 || i.types[op].bitfield.regmmx 5588 || i.types[op].bitfield.regxmm 5589 || i.types[op].bitfield.regymm 5590 || i.types[op].bitfield.regzmm 5591 || i.types[op].bitfield.sreg2 5592 || i.types[op].bitfield.sreg3 5593 || i.types[op].bitfield.control 5594 || i.types[op].bitfield.debug 5595 || i.types[op].bitfield.test 5596 || i.types[op].bitfield.floatreg 5597 || i.types[op].bitfield.floatacc) 5598 { 5599 as_bad (_("`%s%s' not allowed with `%s%c'"), 5600 register_prefix, 5601 i.op[op].regs->reg_name, 5602 i.tm.name, 5603 i.suffix); 5604 return 0; 5605 } 5606 } 5607 return 1; 5608} 5609 5610static int 5611check_long_reg (void) 5612{ 5613 int op; 5614 5615 for (op = i.operands; --op >= 0;) 5616 /* Reject eight bit registers, except where the template requires 5617 them. (eg. movzb) */ 5618 if (i.types[op].bitfield.reg8 5619 && (i.tm.operand_types[op].bitfield.reg16 5620 || i.tm.operand_types[op].bitfield.reg32 5621 || i.tm.operand_types[op].bitfield.acc)) 5622 { 5623 as_bad (_("`%s%s' not allowed with `%s%c'"), 5624 register_prefix, 5625 i.op[op].regs->reg_name, 5626 i.tm.name, 5627 i.suffix); 5628 return 0; 5629 } 5630 /* Warn if the e prefix on a general reg is missing. */ 5631 else if ((!quiet_warnings || flag_code == CODE_64BIT) 5632 && i.types[op].bitfield.reg16 5633 && (i.tm.operand_types[op].bitfield.reg32 5634 || i.tm.operand_types[op].bitfield.acc)) 5635 { 5636 /* Prohibit these changes in the 64bit mode, since the 5637 lowering is more complicated. */ 5638 if (flag_code == CODE_64BIT) 5639 { 5640 as_bad (_("incorrect register `%s%s' used with `%c' suffix"), 5641 register_prefix, i.op[op].regs->reg_name, 5642 i.suffix); 5643 return 0; 5644 } 5645#if REGISTER_WARNINGS 5646 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), 5647 register_prefix, 5648 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name, 5649 register_prefix, i.op[op].regs->reg_name, i.suffix); 5650#endif 5651 } 5652 /* Warn if the r prefix on a general reg is present. */ 5653 else if (i.types[op].bitfield.reg64 5654 && (i.tm.operand_types[op].bitfield.reg32 5655 || i.tm.operand_types[op].bitfield.acc)) 5656 { 5657 if (intel_syntax 5658 && i.tm.opcode_modifier.toqword 5659 && !i.types[0].bitfield.regxmm) 5660 { 5661 /* Convert to QWORD. We want REX byte. */ 5662 i.suffix = QWORD_MNEM_SUFFIX; 5663 } 5664 else 5665 { 5666 as_bad (_("incorrect register `%s%s' used with `%c' suffix"), 5667 register_prefix, i.op[op].regs->reg_name, 5668 i.suffix); 5669 return 0; 5670 } 5671 } 5672 return 1; 5673} 5674 5675static int 5676check_qword_reg (void) 5677{ 5678 int op; 5679 5680 for (op = i.operands; --op >= 0; ) 5681 /* Reject eight bit registers, except where the template requires 5682 them. (eg. movzb) */ 5683 if (i.types[op].bitfield.reg8 5684 && (i.tm.operand_types[op].bitfield.reg16 5685 || i.tm.operand_types[op].bitfield.reg32 5686 || i.tm.operand_types[op].bitfield.acc)) 5687 { 5688 as_bad (_("`%s%s' not allowed with `%s%c'"), 5689 register_prefix, 5690 i.op[op].regs->reg_name, 5691 i.tm.name, 5692 i.suffix); 5693 return 0; 5694 } 5695 /* Warn if the r prefix on a general reg is missing. */ 5696 else if ((i.types[op].bitfield.reg16 5697 || i.types[op].bitfield.reg32) 5698 && (i.tm.operand_types[op].bitfield.reg64 5699 || i.tm.operand_types[op].bitfield.acc)) 5700 { 5701 /* Prohibit these changes in the 64bit mode, since the 5702 lowering is more complicated. */ 5703 if (intel_syntax 5704 && i.tm.opcode_modifier.todword 5705 && !i.types[0].bitfield.regxmm) 5706 { 5707 /* Convert to DWORD. We don't want REX byte. */ 5708 i.suffix = LONG_MNEM_SUFFIX; 5709 } 5710 else 5711 { 5712 as_bad (_("incorrect register `%s%s' used with `%c' suffix"), 5713 register_prefix, i.op[op].regs->reg_name, 5714 i.suffix); 5715 return 0; 5716 } 5717 } 5718 return 1; 5719} 5720 5721static int 5722check_word_reg (void) 5723{ 5724 int op; 5725 for (op = i.operands; --op >= 0;) 5726 /* Reject eight bit registers, except where the template requires 5727 them. (eg. movzb) */ 5728 if (i.types[op].bitfield.reg8 5729 && (i.tm.operand_types[op].bitfield.reg16 5730 || i.tm.operand_types[op].bitfield.reg32 5731 || i.tm.operand_types[op].bitfield.acc)) 5732 { 5733 as_bad (_("`%s%s' not allowed with `%s%c'"), 5734 register_prefix, 5735 i.op[op].regs->reg_name, 5736 i.tm.name, 5737 i.suffix); 5738 return 0; 5739 } 5740 /* Warn if the e or r prefix on a general reg is present. */ 5741 else if ((!quiet_warnings || flag_code == CODE_64BIT) 5742 && (i.types[op].bitfield.reg32 5743 || i.types[op].bitfield.reg64) 5744 && (i.tm.operand_types[op].bitfield.reg16 5745 || i.tm.operand_types[op].bitfield.acc)) 5746 { 5747 /* Prohibit these changes in the 64bit mode, since the 5748 lowering is more complicated. */ 5749 if (flag_code == CODE_64BIT) 5750 { 5751 as_bad (_("incorrect register `%s%s' used with `%c' suffix"), 5752 register_prefix, i.op[op].regs->reg_name, 5753 i.suffix); 5754 return 0; 5755 } 5756#if REGISTER_WARNINGS 5757 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), 5758 register_prefix, 5759 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name, 5760 register_prefix, i.op[op].regs->reg_name, i.suffix); 5761#endif 5762 } 5763 return 1; 5764} 5765 5766static int 5767update_imm (unsigned int j) 5768{ 5769 i386_operand_type overlap = i.types[j]; 5770 if ((overlap.bitfield.imm8 5771 || overlap.bitfield.imm8s 5772 || overlap.bitfield.imm16 5773 || overlap.bitfield.imm32 5774 || overlap.bitfield.imm32s 5775 || overlap.bitfield.imm64) 5776 && !operand_type_equal (&overlap, &imm8) 5777 && !operand_type_equal (&overlap, &imm8s) 5778 && !operand_type_equal (&overlap, &imm16) 5779 && !operand_type_equal (&overlap, &imm32) 5780 && !operand_type_equal (&overlap, &imm32s) 5781 && !operand_type_equal (&overlap, &imm64)) 5782 { 5783 if (i.suffix) 5784 { 5785 i386_operand_type temp; 5786 5787 operand_type_set (&temp, 0); 5788 if (i.suffix == BYTE_MNEM_SUFFIX) 5789 { 5790 temp.bitfield.imm8 = overlap.bitfield.imm8; 5791 temp.bitfield.imm8s = overlap.bitfield.imm8s; 5792 } 5793 else if (i.suffix == WORD_MNEM_SUFFIX) 5794 temp.bitfield.imm16 = overlap.bitfield.imm16; 5795 else if (i.suffix == QWORD_MNEM_SUFFIX) 5796 { 5797 temp.bitfield.imm64 = overlap.bitfield.imm64; 5798 temp.bitfield.imm32s = overlap.bitfield.imm32s; 5799 } 5800 else 5801 temp.bitfield.imm32 = overlap.bitfield.imm32; 5802 overlap = temp; 5803 } 5804 else if (operand_type_equal (&overlap, &imm16_32_32s) 5805 || operand_type_equal (&overlap, &imm16_32) 5806 || operand_type_equal (&overlap, &imm16_32s)) 5807 { 5808 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) 5809 overlap = imm16; 5810 else 5811 overlap = imm32s; 5812 } 5813 if (!operand_type_equal (&overlap, &imm8) 5814 && !operand_type_equal (&overlap, &imm8s) 5815 && !operand_type_equal (&overlap, &imm16) 5816 && !operand_type_equal (&overlap, &imm32) 5817 && !operand_type_equal (&overlap, &imm32s) 5818 && !operand_type_equal (&overlap, &imm64)) 5819 { 5820 as_bad (_("no instruction mnemonic suffix given; " 5821 "can't determine immediate size")); 5822 return 0; 5823 } 5824 } 5825 i.types[j] = overlap; 5826 5827 return 1; 5828} 5829 5830static int 5831finalize_imm (void) 5832{ 5833 unsigned int j, n; 5834 5835 /* Update the first 2 immediate operands. */ 5836 n = i.operands > 2 ? 2 : i.operands; 5837 if (n) 5838 { 5839 for (j = 0; j < n; j++) 5840 if (update_imm (j) == 0) 5841 return 0; 5842 5843 /* The 3rd operand can't be immediate operand. */ 5844 gas_assert (operand_type_check (i.types[2], imm) == 0); 5845 } 5846 5847 return 1; 5848} 5849 5850static int 5851bad_implicit_operand (int xmm) 5852{ 5853 const char *ireg = xmm ? "xmm0" : "ymm0"; 5854 5855 if (intel_syntax) 5856 as_bad (_("the last operand of `%s' must be `%s%s'"), 5857 i.tm.name, register_prefix, ireg); 5858 else 5859 as_bad (_("the first operand of `%s' must be `%s%s'"), 5860 i.tm.name, register_prefix, ireg); 5861 return 0; 5862} 5863 5864static int 5865process_operands (void) 5866{ 5867 /* Default segment register this instruction will use for memory 5868 accesses. 0 means unknown. This is only for optimizing out 5869 unnecessary segment overrides. */ 5870 const seg_entry *default_seg = 0; 5871 5872 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv) 5873 { 5874 unsigned int dupl = i.operands; 5875 unsigned int dest = dupl - 1; 5876 unsigned int j; 5877 5878 /* The destination must be an xmm register. */ 5879 gas_assert (i.reg_operands 5880 && MAX_OPERANDS > dupl 5881 && operand_type_equal (&i.types[dest], ®xmm)); 5882 5883 if (i.tm.opcode_modifier.firstxmm0) 5884 { 5885 /* The first operand is implicit and must be xmm0. */ 5886 gas_assert (operand_type_equal (&i.types[0], ®xmm)); 5887 if (register_number (i.op[0].regs) != 0) 5888 return bad_implicit_operand (1); 5889 5890 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES) 5891 { 5892 /* Keep xmm0 for instructions with VEX prefix and 3 5893 sources. */ 5894 goto duplicate; 5895 } 5896 else 5897 { 5898 /* We remove the first xmm0 and keep the number of 5899 operands unchanged, which in fact duplicates the 5900 destination. */ 5901 for (j = 1; j < i.operands; j++) 5902 { 5903 i.op[j - 1] = i.op[j]; 5904 i.types[j - 1] = i.types[j]; 5905 i.tm.operand_types[j - 1] = i.tm.operand_types[j]; 5906 } 5907 } 5908 } 5909 else if (i.tm.opcode_modifier.implicit1stxmm0) 5910 { 5911 gas_assert ((MAX_OPERANDS - 1) > dupl 5912 && (i.tm.opcode_modifier.vexsources 5913 == VEX3SOURCES)); 5914 5915 /* Add the implicit xmm0 for instructions with VEX prefix 5916 and 3 sources. */ 5917 for (j = i.operands; j > 0; j--) 5918 { 5919 i.op[j] = i.op[j - 1]; 5920 i.types[j] = i.types[j - 1]; 5921 i.tm.operand_types[j] = i.tm.operand_types[j - 1]; 5922 } 5923 i.op[0].regs 5924 = (const reg_entry *) hash_find (reg_hash, "xmm0"); 5925 i.types[0] = regxmm; 5926 i.tm.operand_types[0] = regxmm; 5927 5928 i.operands += 2; 5929 i.reg_operands += 2; 5930 i.tm.operands += 2; 5931 5932 dupl++; 5933 dest++; 5934 i.op[dupl] = i.op[dest]; 5935 i.types[dupl] = i.types[dest]; 5936 i.tm.operand_types[dupl] = i.tm.operand_types[dest]; 5937 } 5938 else 5939 { 5940duplicate: 5941 i.operands++; 5942 i.reg_operands++; 5943 i.tm.operands++; 5944 5945 i.op[dupl] = i.op[dest]; 5946 i.types[dupl] = i.types[dest]; 5947 i.tm.operand_types[dupl] = i.tm.operand_types[dest]; 5948 } 5949 5950 if (i.tm.opcode_modifier.immext) 5951 process_immext (); 5952 } 5953 else if (i.tm.opcode_modifier.firstxmm0) 5954 { 5955 unsigned int j; 5956 5957 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */ 5958 gas_assert (i.reg_operands 5959 && (operand_type_equal (&i.types[0], ®xmm) 5960 || operand_type_equal (&i.types[0], ®ymm) 5961 || operand_type_equal (&i.types[0], ®zmm))); 5962 if (register_number (i.op[0].regs) != 0) 5963 return bad_implicit_operand (i.types[0].bitfield.regxmm); 5964 5965 for (j = 1; j < i.operands; j++) 5966 { 5967 i.op[j - 1] = i.op[j]; 5968 i.types[j - 1] = i.types[j]; 5969 5970 /* We need to adjust fields in i.tm since they are used by 5971 build_modrm_byte. */ 5972 i.tm.operand_types [j - 1] = i.tm.operand_types [j]; 5973 } 5974 5975 i.operands--; 5976 i.reg_operands--; 5977 i.tm.operands--; 5978 } 5979 else if (i.tm.opcode_modifier.implicitquadgroup) 5980 { 5981 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */ 5982 gas_assert (i.operands >= 2 5983 && (operand_type_equal (&i.types[1], ®xmm) 5984 || operand_type_equal (&i.types[1], ®ymm) 5985 || operand_type_equal (&i.types[1], ®zmm))); 5986 unsigned int regnum = register_number (i.op[1].regs); 5987 unsigned int first_reg_in_group = regnum & ~3; 5988 unsigned int last_reg_in_group = first_reg_in_group + 3; 5989 if (regnum != first_reg_in_group) { 5990 as_warn (_("the second source register `%s%s' implicitly denotes" 5991 " `%s%.3s%d' to `%s%.3s%d' source group in `%s'"), 5992 register_prefix, i.op[1].regs->reg_name, 5993 register_prefix, i.op[1].regs->reg_name, first_reg_in_group, 5994 register_prefix, i.op[1].regs->reg_name, last_reg_in_group, 5995 i.tm.name); 5996 } 5997 } 5998 else if (i.tm.opcode_modifier.regkludge) 5999 { 6000 /* The imul $imm, %reg instruction is converted into 6001 imul $imm, %reg, %reg, and the clr %reg instruction 6002 is converted into xor %reg, %reg. */ 6003 6004 unsigned int first_reg_op; 6005 6006 if (operand_type_check (i.types[0], reg)) 6007 first_reg_op = 0; 6008 else 6009 first_reg_op = 1; 6010 /* Pretend we saw the extra register operand. */ 6011 gas_assert (i.reg_operands == 1 6012 && i.op[first_reg_op + 1].regs == 0); 6013 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; 6014 i.types[first_reg_op + 1] = i.types[first_reg_op]; 6015 i.operands++; 6016 i.reg_operands++; 6017 } 6018 6019 if (i.tm.opcode_modifier.shortform) 6020 { 6021 if (i.types[0].bitfield.sreg2 6022 || i.types[0].bitfield.sreg3) 6023 { 6024 if (i.tm.base_opcode == POP_SEG_SHORT 6025 && i.op[0].regs->reg_num == 1) 6026 { 6027 as_bad (_("you can't `pop %scs'"), register_prefix); 6028 return 0; 6029 } 6030 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); 6031 if ((i.op[0].regs->reg_flags & RegRex) != 0) 6032 i.rex |= REX_B; 6033 } 6034 else 6035 { 6036 /* The register or float register operand is in operand 6037 0 or 1. */ 6038 unsigned int op; 6039 6040 if (i.types[0].bitfield.floatreg 6041 || operand_type_check (i.types[0], reg)) 6042 op = 0; 6043 else 6044 op = 1; 6045 /* Register goes in low 3 bits of opcode. */ 6046 i.tm.base_opcode |= i.op[op].regs->reg_num; 6047 if ((i.op[op].regs->reg_flags & RegRex) != 0) 6048 i.rex |= REX_B; 6049 if (!quiet_warnings && i.tm.opcode_modifier.ugh) 6050 { 6051 /* Warn about some common errors, but press on regardless. 6052 The first case can be generated by gcc (<= 2.8.1). */ 6053 if (i.operands == 2) 6054 { 6055 /* Reversed arguments on faddp, fsubp, etc. */ 6056 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name, 6057 register_prefix, i.op[!intel_syntax].regs->reg_name, 6058 register_prefix, i.op[intel_syntax].regs->reg_name); 6059 } 6060 else 6061 { 6062 /* Extraneous `l' suffix on fp insn. */ 6063 as_warn (_("translating to `%s %s%s'"), i.tm.name, 6064 register_prefix, i.op[0].regs->reg_name); 6065 } 6066 } 6067 } 6068 } 6069 else if (i.tm.opcode_modifier.modrm) 6070 { 6071 /* The opcode is completed (modulo i.tm.extension_opcode which 6072 must be put into the modrm byte). Now, we make the modrm and 6073 index base bytes based on all the info we've collected. */ 6074 6075 default_seg = build_modrm_byte (); 6076 } 6077 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32) 6078 { 6079 default_seg = &ds; 6080 } 6081 else if (i.tm.opcode_modifier.isstring) 6082 { 6083 /* For the string instructions that allow a segment override 6084 on one of their operands, the default segment is ds. */ 6085 default_seg = &ds; 6086 } 6087 6088 if (i.tm.base_opcode == 0x8d /* lea */ 6089 && i.seg[0] 6090 && !quiet_warnings) 6091 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name); 6092 6093 /* If a segment was explicitly specified, and the specified segment 6094 is not the default, use an opcode prefix to select it. If we 6095 never figured out what the default segment is, then default_seg 6096 will be zero at this point, and the specified segment prefix will 6097 always be used. */ 6098 if ((i.seg[0]) && (i.seg[0] != default_seg)) 6099 { 6100 if (!add_prefix (i.seg[0]->seg_prefix)) 6101 return 0; 6102 } 6103 return 1; 6104} 6105 6106static const seg_entry * 6107build_modrm_byte (void) 6108{ 6109 const seg_entry *default_seg = 0; 6110 unsigned int source, dest; 6111 int vex_3_sources; 6112 6113 /* The first operand of instructions with VEX prefix and 3 sources 6114 must be VEX_Imm4. */ 6115 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES; 6116 if (vex_3_sources) 6117 { 6118 unsigned int nds, reg_slot; 6119 expressionS *exp; 6120 6121 if (i.tm.opcode_modifier.veximmext 6122 && i.tm.opcode_modifier.immext) 6123 { 6124 dest = i.operands - 2; 6125 gas_assert (dest == 3); 6126 } 6127 else 6128 dest = i.operands - 1; 6129 nds = dest - 1; 6130 6131 /* There are 2 kinds of instructions: 6132 1. 5 operands: 4 register operands or 3 register operands 6133 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and 6134 VexW0 or VexW1. The destination must be either XMM, YMM or 6135 ZMM register. 6136 2. 4 operands: 4 register operands or 3 register operands 6137 plus 1 memory operand, VexXDS, and VexImmExt */ 6138 gas_assert ((i.reg_operands == 4 6139 || (i.reg_operands == 3 && i.mem_operands == 1)) 6140 && i.tm.opcode_modifier.vexvvvv == VEXXDS 6141 && (i.tm.opcode_modifier.veximmext 6142 || (i.imm_operands == 1 6143 && i.types[0].bitfield.vec_imm4 6144 && (i.tm.opcode_modifier.vexw == VEXW0 6145 || i.tm.opcode_modifier.vexw == VEXW1) 6146 && (operand_type_equal (&i.tm.operand_types[dest], ®xmm) 6147 || operand_type_equal (&i.tm.operand_types[dest], ®ymm) 6148 || operand_type_equal (&i.tm.operand_types[dest], ®zmm))))); 6149 6150 if (i.imm_operands == 0) 6151 { 6152 /* When there is no immediate operand, generate an 8bit 6153 immediate operand to encode the first operand. */ 6154 exp = &im_expressions[i.imm_operands++]; 6155 i.op[i.operands].imms = exp; 6156 i.types[i.operands] = imm8; 6157 i.operands++; 6158 /* If VexW1 is set, the first operand is the source and 6159 the second operand is encoded in the immediate operand. */ 6160 if (i.tm.opcode_modifier.vexw == VEXW1) 6161 { 6162 source = 0; 6163 reg_slot = 1; 6164 } 6165 else 6166 { 6167 source = 1; 6168 reg_slot = 0; 6169 } 6170 6171 /* FMA swaps REG and NDS. */ 6172 if (i.tm.cpu_flags.bitfield.cpufma) 6173 { 6174 unsigned int tmp; 6175 tmp = reg_slot; 6176 reg_slot = nds; 6177 nds = tmp; 6178 } 6179 6180 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot], 6181 ®xmm) 6182 || operand_type_equal (&i.tm.operand_types[reg_slot], 6183 ®ymm) 6184 || operand_type_equal (&i.tm.operand_types[reg_slot], 6185 ®zmm)); 6186 exp->X_op = O_constant; 6187 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4; 6188 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); 6189 } 6190 else 6191 { 6192 unsigned int imm_slot; 6193 6194 if (i.tm.opcode_modifier.vexw == VEXW0) 6195 { 6196 /* If VexW0 is set, the third operand is the source and 6197 the second operand is encoded in the immediate 6198 operand. */ 6199 source = 2; 6200 reg_slot = 1; 6201 } 6202 else 6203 { 6204 /* VexW1 is set, the second operand is the source and 6205 the third operand is encoded in the immediate 6206 operand. */ 6207 source = 1; 6208 reg_slot = 2; 6209 } 6210 6211 if (i.tm.opcode_modifier.immext) 6212 { 6213 /* When ImmExt is set, the immdiate byte is the last 6214 operand. */ 6215 imm_slot = i.operands - 1; 6216 source--; 6217 reg_slot--; 6218 } 6219 else 6220 { 6221 imm_slot = 0; 6222 6223 /* Turn on Imm8 so that output_imm will generate it. */ 6224 i.types[imm_slot].bitfield.imm8 = 1; 6225 } 6226 6227 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot], 6228 ®xmm) 6229 || operand_type_equal (&i.tm.operand_types[reg_slot], 6230 ®ymm) 6231 || operand_type_equal (&i.tm.operand_types[reg_slot], 6232 ®zmm)); 6233 i.op[imm_slot].imms->X_add_number 6234 |= register_number (i.op[reg_slot].regs) << 4; 6235 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); 6236 } 6237 6238 gas_assert (operand_type_equal (&i.tm.operand_types[nds], ®xmm) 6239 || operand_type_equal (&i.tm.operand_types[nds], 6240 ®ymm) 6241 || operand_type_equal (&i.tm.operand_types[nds], 6242 ®zmm)); 6243 i.vex.register_specifier = i.op[nds].regs; 6244 } 6245 else 6246 source = dest = 0; 6247 6248 /* i.reg_operands MUST be the number of real register operands; 6249 implicit registers do not count. If there are 3 register 6250 operands, it must be a instruction with VexNDS. For a 6251 instruction with VexNDD, the destination register is encoded 6252 in VEX prefix. If there are 4 register operands, it must be 6253 a instruction with VEX prefix and 3 sources. */ 6254 if (i.mem_operands == 0 6255 && ((i.reg_operands == 2 6256 && i.tm.opcode_modifier.vexvvvv <= VEXXDS) 6257 || (i.reg_operands == 3 6258 && i.tm.opcode_modifier.vexvvvv == VEXXDS) 6259 || (i.reg_operands == 4 && vex_3_sources))) 6260 { 6261 switch (i.operands) 6262 { 6263 case 2: 6264 source = 0; 6265 break; 6266 case 3: 6267 /* When there are 3 operands, one of them may be immediate, 6268 which may be the first or the last operand. Otherwise, 6269 the first operand must be shift count register (cl) or it 6270 is an instruction with VexNDS. */ 6271 gas_assert (i.imm_operands == 1 6272 || (i.imm_operands == 0 6273 && (i.tm.opcode_modifier.vexvvvv == VEXXDS 6274 || i.types[0].bitfield.shiftcount))); 6275 if (operand_type_check (i.types[0], imm) 6276 || i.types[0].bitfield.shiftcount) 6277 source = 1; 6278 else 6279 source = 0; 6280 break; 6281 case 4: 6282 /* When there are 4 operands, the first two must be 8bit 6283 immediate operands. The source operand will be the 3rd 6284 one. 6285 6286 For instructions with VexNDS, if the first operand 6287 an imm8, the source operand is the 2nd one. If the last 6288 operand is imm8, the source operand is the first one. */ 6289 gas_assert ((i.imm_operands == 2 6290 && i.types[0].bitfield.imm8 6291 && i.types[1].bitfield.imm8) 6292 || (i.tm.opcode_modifier.vexvvvv == VEXXDS 6293 && i.imm_operands == 1 6294 && (i.types[0].bitfield.imm8 6295 || i.types[i.operands - 1].bitfield.imm8 6296 || i.rounding))); 6297 if (i.imm_operands == 2) 6298 source = 2; 6299 else 6300 { 6301 if (i.types[0].bitfield.imm8) 6302 source = 1; 6303 else 6304 source = 0; 6305 } 6306 break; 6307 case 5: 6308 if (i.tm.opcode_modifier.evex) 6309 { 6310 /* For EVEX instructions, when there are 5 operands, the 6311 first one must be immediate operand. If the second one 6312 is immediate operand, the source operand is the 3th 6313 one. If the last one is immediate operand, the source 6314 operand is the 2nd one. */ 6315 gas_assert (i.imm_operands == 2 6316 && i.tm.opcode_modifier.sae 6317 && operand_type_check (i.types[0], imm)); 6318 if (operand_type_check (i.types[1], imm)) 6319 source = 2; 6320 else if (operand_type_check (i.types[4], imm)) 6321 source = 1; 6322 else 6323 abort (); 6324 } 6325 break; 6326 default: 6327 abort (); 6328 } 6329 6330 if (!vex_3_sources) 6331 { 6332 dest = source + 1; 6333 6334 /* RC/SAE operand could be between DEST and SRC. That happens 6335 when one operand is GPR and the other one is XMM/YMM/ZMM 6336 register. */ 6337 if (i.rounding && i.rounding->operand == (int) dest) 6338 dest++; 6339 6340 if (i.tm.opcode_modifier.vexvvvv == VEXXDS) 6341 { 6342 /* For instructions with VexNDS, the register-only source 6343 operand must be 32/64bit integer, XMM, YMM or ZMM 6344 register. It is encoded in VEX prefix. We need to 6345 clear RegMem bit before calling operand_type_equal. */ 6346 6347 i386_operand_type op; 6348 unsigned int vvvv; 6349 6350 /* Check register-only source operand when two source 6351 operands are swapped. */ 6352 if (!i.tm.operand_types[source].bitfield.baseindex 6353 && i.tm.operand_types[dest].bitfield.baseindex) 6354 { 6355 vvvv = source; 6356 source = dest; 6357 } 6358 else 6359 vvvv = dest; 6360 6361 op = i.tm.operand_types[vvvv]; 6362 op.bitfield.regmem = 0; 6363 if ((dest + 1) >= i.operands 6364 || (!op.bitfield.reg32 6365 && op.bitfield.reg64 6366 && !operand_type_equal (&op, ®xmm) 6367 && !operand_type_equal (&op, ®ymm) 6368 && !operand_type_equal (&op, ®zmm) 6369 && !operand_type_equal (&op, ®mask))) 6370 abort (); 6371 i.vex.register_specifier = i.op[vvvv].regs; 6372 dest++; 6373 } 6374 } 6375 6376 i.rm.mode = 3; 6377 /* One of the register operands will be encoded in the i.tm.reg 6378 field, the other in the combined i.tm.mode and i.tm.regmem 6379 fields. If no form of this instruction supports a memory 6380 destination operand, then we assume the source operand may 6381 sometimes be a memory operand and so we need to store the 6382 destination in the i.rm.reg field. */ 6383 if (!i.tm.operand_types[dest].bitfield.regmem 6384 && operand_type_check (i.tm.operand_types[dest], anymem) == 0) 6385 { 6386 i.rm.reg = i.op[dest].regs->reg_num; 6387 i.rm.regmem = i.op[source].regs->reg_num; 6388 if ((i.op[dest].regs->reg_flags & RegRex) != 0) 6389 i.rex |= REX_R; 6390 if ((i.op[dest].regs->reg_flags & RegVRex) != 0) 6391 i.vrex |= REX_R; 6392 if ((i.op[source].regs->reg_flags & RegRex) != 0) 6393 i.rex |= REX_B; 6394 if ((i.op[source].regs->reg_flags & RegVRex) != 0) 6395 i.vrex |= REX_B; 6396 } 6397 else 6398 { 6399 i.rm.reg = i.op[source].regs->reg_num; 6400 i.rm.regmem = i.op[dest].regs->reg_num; 6401 if ((i.op[dest].regs->reg_flags & RegRex) != 0) 6402 i.rex |= REX_B; 6403 if ((i.op[dest].regs->reg_flags & RegVRex) != 0) 6404 i.vrex |= REX_B; 6405 if ((i.op[source].regs->reg_flags & RegRex) != 0) 6406 i.rex |= REX_R; 6407 if ((i.op[source].regs->reg_flags & RegVRex) != 0) 6408 i.vrex |= REX_R; 6409 } 6410 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B))) 6411 { 6412 if (!i.types[0].bitfield.control 6413 && !i.types[1].bitfield.control) 6414 abort (); 6415 i.rex &= ~(REX_R | REX_B); 6416 add_prefix (LOCK_PREFIX_OPCODE); 6417 } 6418 } 6419 else 6420 { /* If it's not 2 reg operands... */ 6421 unsigned int mem; 6422 6423 if (i.mem_operands) 6424 { 6425 unsigned int fake_zero_displacement = 0; 6426 unsigned int op; 6427 6428 for (op = 0; op < i.operands; op++) 6429 if (operand_type_check (i.types[op], anymem)) 6430 break; 6431 gas_assert (op < i.operands); 6432 6433 if (i.tm.opcode_modifier.vecsib) 6434 { 6435 if (i.index_reg->reg_num == RegEiz 6436 || i.index_reg->reg_num == RegRiz) 6437 abort (); 6438 6439 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; 6440 if (!i.base_reg) 6441 { 6442 i.sib.base = NO_BASE_REGISTER; 6443 i.sib.scale = i.log2_scale_factor; 6444 /* No Vec_Disp8 if there is no base. */ 6445 i.types[op].bitfield.vec_disp8 = 0; 6446 i.types[op].bitfield.disp8 = 0; 6447 i.types[op].bitfield.disp16 = 0; 6448 i.types[op].bitfield.disp64 = 0; 6449 if (flag_code != CODE_64BIT) 6450 { 6451 /* Must be 32 bit */ 6452 i.types[op].bitfield.disp32 = 1; 6453 i.types[op].bitfield.disp32s = 0; 6454 } 6455 else 6456 { 6457 i.types[op].bitfield.disp32 = 0; 6458 i.types[op].bitfield.disp32s = 1; 6459 } 6460 } 6461 i.sib.index = i.index_reg->reg_num; 6462 if ((i.index_reg->reg_flags & RegRex) != 0) 6463 i.rex |= REX_X; 6464 if ((i.index_reg->reg_flags & RegVRex) != 0) 6465 i.vrex |= REX_X; 6466 } 6467 6468 default_seg = &ds; 6469 6470 if (i.base_reg == 0) 6471 { 6472 i.rm.mode = 0; 6473 if (!i.disp_operands) 6474 { 6475 fake_zero_displacement = 1; 6476 /* Instructions with VSIB byte need 32bit displacement 6477 if there is no base register. */ 6478 if (i.tm.opcode_modifier.vecsib) 6479 i.types[op].bitfield.disp32 = 1; 6480 } 6481 if (i.index_reg == 0) 6482 { 6483 gas_assert (!i.tm.opcode_modifier.vecsib); 6484 /* Operand is just <disp> */ 6485 if (flag_code == CODE_64BIT) 6486 { 6487 /* 64bit mode overwrites the 32bit absolute 6488 addressing by RIP relative addressing and 6489 absolute addressing is encoded by one of the 6490 redundant SIB forms. */ 6491 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; 6492 i.sib.base = NO_BASE_REGISTER; 6493 i.sib.index = NO_INDEX_REGISTER; 6494 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) 6495 ? disp32s : disp32); 6496 } 6497 else if ((flag_code == CODE_16BIT) 6498 ^ (i.prefix[ADDR_PREFIX] != 0)) 6499 { 6500 i.rm.regmem = NO_BASE_REGISTER_16; 6501 i.types[op] = disp16; 6502 } 6503 else 6504 { 6505 i.rm.regmem = NO_BASE_REGISTER; 6506 i.types[op] = disp32; 6507 } 6508 } 6509 else if (!i.tm.opcode_modifier.vecsib) 6510 { 6511 /* !i.base_reg && i.index_reg */ 6512 if (i.index_reg->reg_num == RegEiz 6513 || i.index_reg->reg_num == RegRiz) 6514 i.sib.index = NO_INDEX_REGISTER; 6515 else 6516 i.sib.index = i.index_reg->reg_num; 6517 i.sib.base = NO_BASE_REGISTER; 6518 i.sib.scale = i.log2_scale_factor; 6519 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; 6520 /* No Vec_Disp8 if there is no base. */ 6521 i.types[op].bitfield.vec_disp8 = 0; 6522 i.types[op].bitfield.disp8 = 0; 6523 i.types[op].bitfield.disp16 = 0; 6524 i.types[op].bitfield.disp64 = 0; 6525 if (flag_code != CODE_64BIT) 6526 { 6527 /* Must be 32 bit */ 6528 i.types[op].bitfield.disp32 = 1; 6529 i.types[op].bitfield.disp32s = 0; 6530 } 6531 else 6532 { 6533 i.types[op].bitfield.disp32 = 0; 6534 i.types[op].bitfield.disp32s = 1; 6535 } 6536 if ((i.index_reg->reg_flags & RegRex) != 0) 6537 i.rex |= REX_X; 6538 } 6539 } 6540 /* RIP addressing for 64bit mode. */ 6541 else if (i.base_reg->reg_num == RegRip || 6542 i.base_reg->reg_num == RegEip) 6543 { 6544 gas_assert (!i.tm.opcode_modifier.vecsib); 6545 i.rm.regmem = NO_BASE_REGISTER; 6546 i.types[op].bitfield.disp8 = 0; 6547 i.types[op].bitfield.disp16 = 0; 6548 i.types[op].bitfield.disp32 = 0; 6549 i.types[op].bitfield.disp32s = 1; 6550 i.types[op].bitfield.disp64 = 0; 6551 i.types[op].bitfield.vec_disp8 = 0; 6552 i.flags[op] |= Operand_PCrel; 6553 if (! i.disp_operands) 6554 fake_zero_displacement = 1; 6555 } 6556 else if (i.base_reg->reg_type.bitfield.reg16) 6557 { 6558 gas_assert (!i.tm.opcode_modifier.vecsib); 6559 switch (i.base_reg->reg_num) 6560 { 6561 case 3: /* (%bx) */ 6562 if (i.index_reg == 0) 6563 i.rm.regmem = 7; 6564 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ 6565 i.rm.regmem = i.index_reg->reg_num - 6; 6566 break; 6567 case 5: /* (%bp) */ 6568 default_seg = &ss; 6569 if (i.index_reg == 0) 6570 { 6571 i.rm.regmem = 6; 6572 if (operand_type_check (i.types[op], disp) == 0) 6573 { 6574 /* fake (%bp) into 0(%bp) */ 6575 if (i.tm.operand_types[op].bitfield.vec_disp8) 6576 i.types[op].bitfield.vec_disp8 = 1; 6577 else 6578 i.types[op].bitfield.disp8 = 1; 6579 fake_zero_displacement = 1; 6580 } 6581 } 6582 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ 6583 i.rm.regmem = i.index_reg->reg_num - 6 + 2; 6584 break; 6585 default: /* (%si) -> 4 or (%di) -> 5 */ 6586 i.rm.regmem = i.base_reg->reg_num - 6 + 4; 6587 } 6588 i.rm.mode = mode_from_disp_size (i.types[op]); 6589 } 6590 else /* i.base_reg and 32/64 bit mode */ 6591 { 6592 if (flag_code == CODE_64BIT 6593 && operand_type_check (i.types[op], disp)) 6594 { 6595 i386_operand_type temp; 6596 operand_type_set (&temp, 0); 6597 temp.bitfield.disp8 = i.types[op].bitfield.disp8; 6598 temp.bitfield.vec_disp8 6599 = i.types[op].bitfield.vec_disp8; 6600 i.types[op] = temp; 6601 if (i.prefix[ADDR_PREFIX] == 0) 6602 i.types[op].bitfield.disp32s = 1; 6603 else 6604 i.types[op].bitfield.disp32 = 1; 6605 } 6606 6607 if (!i.tm.opcode_modifier.vecsib) 6608 i.rm.regmem = i.base_reg->reg_num; 6609 if ((i.base_reg->reg_flags & RegRex) != 0) 6610 i.rex |= REX_B; 6611 i.sib.base = i.base_reg->reg_num; 6612 /* x86-64 ignores REX prefix bit here to avoid decoder 6613 complications. */ 6614 if (!(i.base_reg->reg_flags & RegRex) 6615 && (i.base_reg->reg_num == EBP_REG_NUM 6616 || i.base_reg->reg_num == ESP_REG_NUM)) 6617 default_seg = &ss; 6618 if (i.base_reg->reg_num == 5 && i.disp_operands == 0) 6619 { 6620 fake_zero_displacement = 1; 6621 if (i.tm.operand_types [op].bitfield.vec_disp8) 6622 i.types[op].bitfield.vec_disp8 = 1; 6623 else 6624 i.types[op].bitfield.disp8 = 1; 6625 } 6626 i.sib.scale = i.log2_scale_factor; 6627 if (i.index_reg == 0) 6628 { 6629 gas_assert (!i.tm.opcode_modifier.vecsib); 6630 /* <disp>(%esp) becomes two byte modrm with no index 6631 register. We've already stored the code for esp 6632 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. 6633 Any base register besides %esp will not use the 6634 extra modrm byte. */ 6635 i.sib.index = NO_INDEX_REGISTER; 6636 } 6637 else if (!i.tm.opcode_modifier.vecsib) 6638 { 6639 if (i.index_reg->reg_num == RegEiz 6640 || i.index_reg->reg_num == RegRiz) 6641 i.sib.index = NO_INDEX_REGISTER; 6642 else 6643 i.sib.index = i.index_reg->reg_num; 6644 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; 6645 if ((i.index_reg->reg_flags & RegRex) != 0) 6646 i.rex |= REX_X; 6647 } 6648 6649 if (i.disp_operands 6650 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL 6651 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)) 6652 i.rm.mode = 0; 6653 else 6654 { 6655 if (!fake_zero_displacement 6656 && !i.disp_operands 6657 && i.disp_encoding) 6658 { 6659 fake_zero_displacement = 1; 6660 if (i.disp_encoding == disp_encoding_8bit) 6661 i.types[op].bitfield.disp8 = 1; 6662 else 6663 i.types[op].bitfield.disp32 = 1; 6664 } 6665 i.rm.mode = mode_from_disp_size (i.types[op]); 6666 } 6667 } 6668 6669 if (fake_zero_displacement) 6670 { 6671 /* Fakes a zero displacement assuming that i.types[op] 6672 holds the correct displacement size. */ 6673 expressionS *exp; 6674 6675 gas_assert (i.op[op].disps == 0); 6676 exp = &disp_expressions[i.disp_operands++]; 6677 i.op[op].disps = exp; 6678 exp->X_op = O_constant; 6679 exp->X_add_number = 0; 6680 exp->X_add_symbol = (symbolS *) 0; 6681 exp->X_op_symbol = (symbolS *) 0; 6682 } 6683 6684 mem = op; 6685 } 6686 else 6687 mem = ~0; 6688 6689 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES) 6690 { 6691 if (operand_type_check (i.types[0], imm)) 6692 i.vex.register_specifier = NULL; 6693 else 6694 { 6695 /* VEX.vvvv encodes one of the sources when the first 6696 operand is not an immediate. */ 6697 if (i.tm.opcode_modifier.vexw == VEXW0) 6698 i.vex.register_specifier = i.op[0].regs; 6699 else 6700 i.vex.register_specifier = i.op[1].regs; 6701 } 6702 6703 /* Destination is a XMM register encoded in the ModRM.reg 6704 and VEX.R bit. */ 6705 i.rm.reg = i.op[2].regs->reg_num; 6706 if ((i.op[2].regs->reg_flags & RegRex) != 0) 6707 i.rex |= REX_R; 6708 6709 /* ModRM.rm and VEX.B encodes the other source. */ 6710 if (!i.mem_operands) 6711 { 6712 i.rm.mode = 3; 6713 6714 if (i.tm.opcode_modifier.vexw == VEXW0) 6715 i.rm.regmem = i.op[1].regs->reg_num; 6716 else 6717 i.rm.regmem = i.op[0].regs->reg_num; 6718 6719 if ((i.op[1].regs->reg_flags & RegRex) != 0) 6720 i.rex |= REX_B; 6721 } 6722 } 6723 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP) 6724 { 6725 i.vex.register_specifier = i.op[2].regs; 6726 if (!i.mem_operands) 6727 { 6728 i.rm.mode = 3; 6729 i.rm.regmem = i.op[1].regs->reg_num; 6730 if ((i.op[1].regs->reg_flags & RegRex) != 0) 6731 i.rex |= REX_B; 6732 } 6733 } 6734 /* Fill in i.rm.reg or i.rm.regmem field with register operand 6735 (if any) based on i.tm.extension_opcode. Again, we must be 6736 careful to make sure that segment/control/debug/test/MMX 6737 registers are coded into the i.rm.reg field. */ 6738 else if (i.reg_operands) 6739 { 6740 unsigned int op; 6741 unsigned int vex_reg = ~0; 6742 6743 for (op = 0; op < i.operands; op++) 6744 if (i.types[op].bitfield.reg8 6745 || i.types[op].bitfield.reg16 6746 || i.types[op].bitfield.reg32 6747 || i.types[op].bitfield.reg64 6748 || i.types[op].bitfield.regmmx 6749 || i.types[op].bitfield.regxmm 6750 || i.types[op].bitfield.regymm 6751 || i.types[op].bitfield.regbnd 6752 || i.types[op].bitfield.regzmm 6753 || i.types[op].bitfield.regmask 6754 || i.types[op].bitfield.sreg2 6755 || i.types[op].bitfield.sreg3 6756 || i.types[op].bitfield.control 6757 || i.types[op].bitfield.debug 6758 || i.types[op].bitfield.test) 6759 break; 6760 6761 if (vex_3_sources) 6762 op = dest; 6763 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS) 6764 { 6765 /* For instructions with VexNDS, the register-only 6766 source operand is encoded in VEX prefix. */ 6767 gas_assert (mem != (unsigned int) ~0); 6768 6769 if (op > mem) 6770 { 6771 vex_reg = op++; 6772 gas_assert (op < i.operands); 6773 } 6774 else 6775 { 6776 /* Check register-only source operand when two source 6777 operands are swapped. */ 6778 if (!i.tm.operand_types[op].bitfield.baseindex 6779 && i.tm.operand_types[op + 1].bitfield.baseindex) 6780 { 6781 vex_reg = op; 6782 op += 2; 6783 gas_assert (mem == (vex_reg + 1) 6784 && op < i.operands); 6785 } 6786 else 6787 { 6788 vex_reg = op + 1; 6789 gas_assert (vex_reg < i.operands); 6790 } 6791 } 6792 } 6793 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD) 6794 { 6795 /* For instructions with VexNDD, the register destination 6796 is encoded in VEX prefix. */ 6797 if (i.mem_operands == 0) 6798 { 6799 /* There is no memory operand. */ 6800 gas_assert ((op + 2) == i.operands); 6801 vex_reg = op + 1; 6802 } 6803 else 6804 { 6805 /* There are only 2 operands. */ 6806 gas_assert (op < 2 && i.operands == 2); 6807 vex_reg = 1; 6808 } 6809 } 6810 else 6811 gas_assert (op < i.operands); 6812 6813 if (vex_reg != (unsigned int) ~0) 6814 { 6815 i386_operand_type *type = &i.tm.operand_types[vex_reg]; 6816 6817 if (type->bitfield.reg32 != 1 6818 && type->bitfield.reg64 != 1 6819 && !operand_type_equal (type, ®xmm) 6820 && !operand_type_equal (type, ®ymm) 6821 && !operand_type_equal (type, ®zmm) 6822 && !operand_type_equal (type, ®mask)) 6823 abort (); 6824 6825 i.vex.register_specifier = i.op[vex_reg].regs; 6826 } 6827 6828 /* Don't set OP operand twice. */ 6829 if (vex_reg != op) 6830 { 6831 /* If there is an extension opcode to put here, the 6832 register number must be put into the regmem field. */ 6833 if (i.tm.extension_opcode != None) 6834 { 6835 i.rm.regmem = i.op[op].regs->reg_num; 6836 if ((i.op[op].regs->reg_flags & RegRex) != 0) 6837 i.rex |= REX_B; 6838 if ((i.op[op].regs->reg_flags & RegVRex) != 0) 6839 i.vrex |= REX_B; 6840 } 6841 else 6842 { 6843 i.rm.reg = i.op[op].regs->reg_num; 6844 if ((i.op[op].regs->reg_flags & RegRex) != 0) 6845 i.rex |= REX_R; 6846 if ((i.op[op].regs->reg_flags & RegVRex) != 0) 6847 i.vrex |= REX_R; 6848 } 6849 } 6850 6851 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we 6852 must set it to 3 to indicate this is a register operand 6853 in the regmem field. */ 6854 if (!i.mem_operands) 6855 i.rm.mode = 3; 6856 } 6857 6858 /* Fill in i.rm.reg field with extension opcode (if any). */ 6859 if (i.tm.extension_opcode != None) 6860 i.rm.reg = i.tm.extension_opcode; 6861 } 6862 return default_seg; 6863} 6864 6865static void 6866output_branch (void) 6867{ 6868 char *p; 6869 int size; 6870 int code16; 6871 int prefix; 6872 relax_substateT subtype; 6873 symbolS *sym; 6874 offsetT off; 6875 6876 code16 = flag_code == CODE_16BIT ? CODE16 : 0; 6877 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL; 6878 6879 prefix = 0; 6880 if (i.prefix[DATA_PREFIX] != 0) 6881 { 6882 prefix = 1; 6883 i.prefixes -= 1; 6884 code16 ^= CODE16; 6885 } 6886 /* Pentium4 branch hints. */ 6887 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ 6888 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) 6889 { 6890 prefix++; 6891 i.prefixes--; 6892 } 6893 if (i.prefix[REX_PREFIX] != 0) 6894 { 6895 prefix++; 6896 i.prefixes--; 6897 } 6898 6899 /* BND prefixed jump. */ 6900 if (i.prefix[BND_PREFIX] != 0) 6901 { 6902 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]); 6903 i.prefixes -= 1; 6904 } 6905 6906 if (i.prefixes != 0 && !intel_syntax) 6907 as_warn (_("skipping prefixes on this instruction")); 6908 6909 /* It's always a symbol; End frag & setup for relax. 6910 Make sure there is enough room in this frag for the largest 6911 instruction we may generate in md_convert_frag. This is 2 6912 bytes for the opcode and room for the prefix and largest 6913 displacement. */ 6914 frag_grow (prefix + 2 + 4); 6915 /* Prefix and 1 opcode byte go in fr_fix. */ 6916 p = frag_more (prefix + 1); 6917 if (i.prefix[DATA_PREFIX] != 0) 6918 *p++ = DATA_PREFIX_OPCODE; 6919 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE 6920 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) 6921 *p++ = i.prefix[SEG_PREFIX]; 6922 if (i.prefix[REX_PREFIX] != 0) 6923 *p++ = i.prefix[REX_PREFIX]; 6924 *p = i.tm.base_opcode; 6925 6926 if ((unsigned char) *p == JUMP_PC_RELATIVE) 6927 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size); 6928 else if (cpu_arch_flags.bitfield.cpui386) 6929 subtype = ENCODE_RELAX_STATE (COND_JUMP, size); 6930 else 6931 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size); 6932 subtype |= code16; 6933 6934 sym = i.op[0].disps->X_add_symbol; 6935 off = i.op[0].disps->X_add_number; 6936 6937 if (i.op[0].disps->X_op != O_constant 6938 && i.op[0].disps->X_op != O_symbol) 6939 { 6940 /* Handle complex expressions. */ 6941 sym = make_expr_symbol (i.op[0].disps); 6942 off = 0; 6943 } 6944 6945 /* 1 possible extra opcode + 4 byte displacement go in var part. 6946 Pass reloc in fr_var. */ 6947 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); 6948} 6949 6950static void 6951output_jump (void) 6952{ 6953 char *p; 6954 int size; 6955 fixS *fixP; 6956 6957 if (i.tm.opcode_modifier.jumpbyte) 6958 { 6959 /* This is a loop or jecxz type instruction. */ 6960 size = 1; 6961 if (i.prefix[ADDR_PREFIX] != 0) 6962 { 6963 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); 6964 i.prefixes -= 1; 6965 } 6966 /* Pentium4 branch hints. */ 6967 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ 6968 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) 6969 { 6970 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]); 6971 i.prefixes--; 6972 } 6973 } 6974 else 6975 { 6976 int code16; 6977 6978 code16 = 0; 6979 if (flag_code == CODE_16BIT) 6980 code16 = CODE16; 6981 6982 if (i.prefix[DATA_PREFIX] != 0) 6983 { 6984 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); 6985 i.prefixes -= 1; 6986 code16 ^= CODE16; 6987 } 6988 6989 size = 4; 6990 if (code16) 6991 size = 2; 6992 } 6993 6994 if (i.prefix[REX_PREFIX] != 0) 6995 { 6996 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]); 6997 i.prefixes -= 1; 6998 } 6999 7000 /* BND prefixed jump. */ 7001 if (i.prefix[BND_PREFIX] != 0) 7002 { 7003 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]); 7004 i.prefixes -= 1; 7005 } 7006 7007 if (i.prefixes != 0 && !intel_syntax) 7008 as_warn (_("skipping prefixes on this instruction")); 7009 7010 p = frag_more (i.tm.opcode_length + size); 7011 switch (i.tm.opcode_length) 7012 { 7013 case 2: 7014 *p++ = i.tm.base_opcode >> 8; 7015 /* Fall through. */ 7016 case 1: 7017 *p++ = i.tm.base_opcode; 7018 break; 7019 default: 7020 abort (); 7021 } 7022 7023 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, 7024 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0])); 7025 7026 /* All jumps handled here are signed, but don't use a signed limit 7027 check for 32 and 16 bit jumps as we want to allow wrap around at 7028 4G and 64k respectively. */ 7029 if (size == 1) 7030 fixP->fx_signed = 1; 7031} 7032 7033static void 7034output_interseg_jump (void) 7035{ 7036 char *p; 7037 int size; 7038 int prefix; 7039 int code16; 7040 7041 code16 = 0; 7042 if (flag_code == CODE_16BIT) 7043 code16 = CODE16; 7044 7045 prefix = 0; 7046 if (i.prefix[DATA_PREFIX] != 0) 7047 { 7048 prefix = 1; 7049 i.prefixes -= 1; 7050 code16 ^= CODE16; 7051 } 7052 if (i.prefix[REX_PREFIX] != 0) 7053 { 7054 prefix++; 7055 i.prefixes -= 1; 7056 } 7057 7058 size = 4; 7059 if (code16) 7060 size = 2; 7061 7062 if (i.prefixes != 0 && !intel_syntax) 7063 as_warn (_("skipping prefixes on this instruction")); 7064 7065 /* 1 opcode; 2 segment; offset */ 7066 p = frag_more (prefix + 1 + 2 + size); 7067 7068 if (i.prefix[DATA_PREFIX] != 0) 7069 *p++ = DATA_PREFIX_OPCODE; 7070 7071 if (i.prefix[REX_PREFIX] != 0) 7072 *p++ = i.prefix[REX_PREFIX]; 7073 7074 *p++ = i.tm.base_opcode; 7075 if (i.op[1].imms->X_op == O_constant) 7076 { 7077 offsetT n = i.op[1].imms->X_add_number; 7078 7079 if (size == 2 7080 && !fits_in_unsigned_word (n) 7081 && !fits_in_signed_word (n)) 7082 { 7083 as_bad (_("16-bit jump out of range")); 7084 return; 7085 } 7086 md_number_to_chars (p, n, size); 7087 } 7088 else 7089 fix_new_exp (frag_now, p - frag_now->fr_literal, size, 7090 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); 7091 if (i.op[0].imms->X_op != O_constant) 7092 as_bad (_("can't handle non absolute segment in `%s'"), 7093 i.tm.name); 7094 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); 7095} 7096 7097static void 7098output_insn (void) 7099{ 7100 fragS *insn_start_frag; 7101 offsetT insn_start_off; 7102 7103 /* Tie dwarf2 debug info to the address at the start of the insn. 7104 We can't do this after the insn has been output as the current 7105 frag may have been closed off. eg. by frag_var. */ 7106 dwarf2_emit_insn (0); 7107 7108 insn_start_frag = frag_now; 7109 insn_start_off = frag_now_fix (); 7110 7111 /* Output jumps. */ 7112 if (i.tm.opcode_modifier.jump) 7113 output_branch (); 7114 else if (i.tm.opcode_modifier.jumpbyte 7115 || i.tm.opcode_modifier.jumpdword) 7116 output_jump (); 7117 else if (i.tm.opcode_modifier.jumpintersegment) 7118 output_interseg_jump (); 7119 else 7120 { 7121 /* Output normal instructions here. */ 7122 char *p; 7123 unsigned char *q; 7124 unsigned int j; 7125 unsigned int prefix; 7126 7127 if (avoid_fence 7128 && i.tm.base_opcode == 0xfae 7129 && i.operands == 1 7130 && i.imm_operands == 1 7131 && (i.op[0].imms->X_add_number == 0xe8 7132 || i.op[0].imms->X_add_number == 0xf0 7133 || i.op[0].imms->X_add_number == 0xf8)) 7134 { 7135 /* Encode lfence, mfence, and sfence as 7136 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */ 7137 offsetT val = 0x240483f0ULL; 7138 p = frag_more (5); 7139 md_number_to_chars (p, val, 5); 7140 return; 7141 } 7142 7143 /* Some processors fail on LOCK prefix. This options makes 7144 assembler ignore LOCK prefix and serves as a workaround. */ 7145 if (omit_lock_prefix) 7146 { 7147 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE) 7148 return; 7149 i.prefix[LOCK_PREFIX] = 0; 7150 } 7151 7152 /* Since the VEX/EVEX prefix contains the implicit prefix, we 7153 don't need the explicit prefix. */ 7154 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex) 7155 { 7156 switch (i.tm.opcode_length) 7157 { 7158 case 3: 7159 if (i.tm.base_opcode & 0xff000000) 7160 { 7161 prefix = (i.tm.base_opcode >> 24) & 0xff; 7162 goto check_prefix; 7163 } 7164 break; 7165 case 2: 7166 if ((i.tm.base_opcode & 0xff0000) != 0) 7167 { 7168 prefix = (i.tm.base_opcode >> 16) & 0xff; 7169 if (i.tm.cpu_flags.bitfield.cpupadlock) 7170 { 7171check_prefix: 7172 if (prefix != REPE_PREFIX_OPCODE 7173 || (i.prefix[REP_PREFIX] 7174 != REPE_PREFIX_OPCODE)) 7175 add_prefix (prefix); 7176 } 7177 else 7178 add_prefix (prefix); 7179 } 7180 break; 7181 case 1: 7182 break; 7183 default: 7184 abort (); 7185 } 7186 7187#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) 7188 /* For x32, add a dummy REX_OPCODE prefix for mov/add with 7189 R_X86_64_GOTTPOFF relocation so that linker can safely 7190 perform IE->LE optimization. */ 7191 if (x86_elf_abi == X86_64_X32_ABI 7192 && i.operands == 2 7193 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF 7194 && i.prefix[REX_PREFIX] == 0) 7195 add_prefix (REX_OPCODE); 7196#endif 7197 7198 /* The prefix bytes. */ 7199 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++) 7200 if (*q) 7201 FRAG_APPEND_1_CHAR (*q); 7202 } 7203 else 7204 { 7205 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++) 7206 if (*q) 7207 switch (j) 7208 { 7209 case REX_PREFIX: 7210 /* REX byte is encoded in VEX prefix. */ 7211 break; 7212 case SEG_PREFIX: 7213 case ADDR_PREFIX: 7214 FRAG_APPEND_1_CHAR (*q); 7215 break; 7216 default: 7217 /* There should be no other prefixes for instructions 7218 with VEX prefix. */ 7219 abort (); 7220 } 7221 7222 /* For EVEX instructions i.vrex should become 0 after 7223 build_evex_prefix. For VEX instructions upper 16 registers 7224 aren't available, so VREX should be 0. */ 7225 if (i.vrex) 7226 abort (); 7227 /* Now the VEX prefix. */ 7228 p = frag_more (i.vex.length); 7229 for (j = 0; j < i.vex.length; j++) 7230 p[j] = i.vex.bytes[j]; 7231 } 7232 7233 /* Now the opcode; be careful about word order here! */ 7234 if (i.tm.opcode_length == 1) 7235 { 7236 FRAG_APPEND_1_CHAR (i.tm.base_opcode); 7237 } 7238 else 7239 { 7240 switch (i.tm.opcode_length) 7241 { 7242 case 4: 7243 p = frag_more (4); 7244 *p++ = (i.tm.base_opcode >> 24) & 0xff; 7245 *p++ = (i.tm.base_opcode >> 16) & 0xff; 7246 break; 7247 case 3: 7248 p = frag_more (3); 7249 *p++ = (i.tm.base_opcode >> 16) & 0xff; 7250 break; 7251 case 2: 7252 p = frag_more (2); 7253 break; 7254 default: 7255 abort (); 7256 break; 7257 } 7258 7259 /* Put out high byte first: can't use md_number_to_chars! */ 7260 *p++ = (i.tm.base_opcode >> 8) & 0xff; 7261 *p = i.tm.base_opcode & 0xff; 7262 } 7263 7264 /* Now the modrm byte and sib byte (if present). */ 7265 if (i.tm.opcode_modifier.modrm) 7266 { 7267 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0 7268 | i.rm.reg << 3 7269 | i.rm.mode << 6)); 7270 /* If i.rm.regmem == ESP (4) 7271 && i.rm.mode != (Register mode) 7272 && not 16 bit 7273 ==> need second modrm byte. */ 7274 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING 7275 && i.rm.mode != 3 7276 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16)) 7277 FRAG_APPEND_1_CHAR ((i.sib.base << 0 7278 | i.sib.index << 3 7279 | i.sib.scale << 6)); 7280 } 7281 7282 if (i.disp_operands) 7283 output_disp (insn_start_frag, insn_start_off); 7284 7285 if (i.imm_operands) 7286 output_imm (insn_start_frag, insn_start_off); 7287 } 7288 7289#ifdef DEBUG386 7290 if (flag_debug) 7291 { 7292 pi ("" /*line*/, &i); 7293 } 7294#endif /* DEBUG386 */ 7295} 7296 7297/* Return the size of the displacement operand N. */ 7298 7299static int 7300disp_size (unsigned int n) 7301{ 7302 int size = 4; 7303 7304 /* Vec_Disp8 has to be 8bit. */ 7305 if (i.types[n].bitfield.vec_disp8) 7306 size = 1; 7307 else if (i.types[n].bitfield.disp64) 7308 size = 8; 7309 else if (i.types[n].bitfield.disp8) 7310 size = 1; 7311 else if (i.types[n].bitfield.disp16) 7312 size = 2; 7313 return size; 7314} 7315 7316/* Return the size of the immediate operand N. */ 7317 7318static int 7319imm_size (unsigned int n) 7320{ 7321 int size = 4; 7322 if (i.types[n].bitfield.imm64) 7323 size = 8; 7324 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s) 7325 size = 1; 7326 else if (i.types[n].bitfield.imm16) 7327 size = 2; 7328 return size; 7329} 7330 7331static void 7332output_disp (fragS *insn_start_frag, offsetT insn_start_off) 7333{ 7334 char *p; 7335 unsigned int n; 7336 7337 for (n = 0; n < i.operands; n++) 7338 { 7339 if (i.types[n].bitfield.vec_disp8 7340 || operand_type_check (i.types[n], disp)) 7341 { 7342 if (i.op[n].disps->X_op == O_constant) 7343 { 7344 int size = disp_size (n); 7345 offsetT val = i.op[n].disps->X_add_number; 7346 7347 if (i.types[n].bitfield.vec_disp8) 7348 val >>= i.memshift; 7349 val = offset_in_range (val, size); 7350 p = frag_more (size); 7351 md_number_to_chars (p, val, size); 7352 } 7353 else 7354 { 7355 enum bfd_reloc_code_real reloc_type; 7356 int size = disp_size (n); 7357 int sign = i.types[n].bitfield.disp32s; 7358 int pcrel = (i.flags[n] & Operand_PCrel) != 0; 7359 fixS *fixP; 7360 7361 /* We can't have 8 bit displacement here. */ 7362 gas_assert (!i.types[n].bitfield.disp8); 7363 7364 /* The PC relative address is computed relative 7365 to the instruction boundary, so in case immediate 7366 fields follows, we need to adjust the value. */ 7367 if (pcrel && i.imm_operands) 7368 { 7369 unsigned int n1; 7370 int sz = 0; 7371 7372 for (n1 = 0; n1 < i.operands; n1++) 7373 if (operand_type_check (i.types[n1], imm)) 7374 { 7375 /* Only one immediate is allowed for PC 7376 relative address. */ 7377 gas_assert (sz == 0); 7378 sz = imm_size (n1); 7379 i.op[n].disps->X_add_number -= sz; 7380 } 7381 /* We should find the immediate. */ 7382 gas_assert (sz != 0); 7383 } 7384 7385 p = frag_more (size); 7386 reloc_type = reloc (size, pcrel, sign, i.reloc[n]); 7387 if (GOT_symbol 7388 && GOT_symbol == i.op[n].disps->X_add_symbol 7389 && (((reloc_type == BFD_RELOC_32 7390 || reloc_type == BFD_RELOC_X86_64_32S 7391 || (reloc_type == BFD_RELOC_64 7392 && object_64bit)) 7393 && (i.op[n].disps->X_op == O_symbol 7394 || (i.op[n].disps->X_op == O_add 7395 && ((symbol_get_value_expression 7396 (i.op[n].disps->X_op_symbol)->X_op) 7397 == O_subtract)))) 7398 || reloc_type == BFD_RELOC_32_PCREL)) 7399 { 7400 offsetT add; 7401 7402 if (insn_start_frag == frag_now) 7403 add = (p - frag_now->fr_literal) - insn_start_off; 7404 else 7405 { 7406 fragS *fr; 7407 7408 add = insn_start_frag->fr_fix - insn_start_off; 7409 for (fr = insn_start_frag->fr_next; 7410 fr && fr != frag_now; fr = fr->fr_next) 7411 add += fr->fr_fix; 7412 add += p - frag_now->fr_literal; 7413 } 7414 7415 if (!object_64bit) 7416 { 7417 reloc_type = BFD_RELOC_386_GOTPC; 7418 i.op[n].imms->X_add_number += add; 7419 } 7420 else if (reloc_type == BFD_RELOC_64) 7421 reloc_type = BFD_RELOC_X86_64_GOTPC64; 7422 else 7423 /* Don't do the adjustment for x86-64, as there 7424 the pcrel addressing is relative to the _next_ 7425 insn, and that is taken care of in other code. */ 7426 reloc_type = BFD_RELOC_X86_64_GOTPC32; 7427 } 7428 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, 7429 size, i.op[n].disps, pcrel, 7430 reloc_type); 7431 /* Check for "call/jmp *mem", "mov mem, %reg", 7432 "test %reg, mem" and "binop mem, %reg" where binop 7433 is one of adc, add, and, cmp, or, sbb, sub, xor 7434 instructions. Always generate R_386_GOT32X for 7435 "sym*GOT" operand in 32-bit mode. */ 7436 if ((generate_relax_relocations 7437 || (!object_64bit 7438 && i.rm.mode == 0 7439 && i.rm.regmem == 5)) 7440 && (i.rm.mode == 2 7441 || (i.rm.mode == 0 && i.rm.regmem == 5)) 7442 && ((i.operands == 1 7443 && i.tm.base_opcode == 0xff 7444 && (i.rm.reg == 2 || i.rm.reg == 4)) 7445 || (i.operands == 2 7446 && (i.tm.base_opcode == 0x8b 7447 || i.tm.base_opcode == 0x85 7448 || (i.tm.base_opcode & 0xc7) == 0x03)))) 7449 { 7450 if (object_64bit) 7451 { 7452 fixP->fx_tcbit = i.rex != 0; 7453 if (i.base_reg 7454 && (i.base_reg->reg_num == RegRip 7455 || i.base_reg->reg_num == RegEip)) 7456 fixP->fx_tcbit2 = 1; 7457 } 7458 else 7459 fixP->fx_tcbit2 = 1; 7460 } 7461 } 7462 } 7463 } 7464} 7465 7466static void 7467output_imm (fragS *insn_start_frag, offsetT insn_start_off) 7468{ 7469 char *p; 7470 unsigned int n; 7471 7472 for (n = 0; n < i.operands; n++) 7473 { 7474 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */ 7475 if (i.rounding && (int) n == i.rounding->operand) 7476 continue; 7477 7478 if (operand_type_check (i.types[n], imm)) 7479 { 7480 if (i.op[n].imms->X_op == O_constant) 7481 { 7482 int size = imm_size (n); 7483 offsetT val; 7484 7485 val = offset_in_range (i.op[n].imms->X_add_number, 7486 size); 7487 p = frag_more (size); 7488 md_number_to_chars (p, val, size); 7489 } 7490 else 7491 { 7492 /* Not absolute_section. 7493 Need a 32-bit fixup (don't support 8bit 7494 non-absolute imms). Try to support other 7495 sizes ... */ 7496 enum bfd_reloc_code_real reloc_type; 7497 int size = imm_size (n); 7498 int sign; 7499 7500 if (i.types[n].bitfield.imm32s 7501 && (i.suffix == QWORD_MNEM_SUFFIX 7502 || (!i.suffix && i.tm.opcode_modifier.no_lsuf))) 7503 sign = 1; 7504 else 7505 sign = 0; 7506 7507 p = frag_more (size); 7508 reloc_type = reloc (size, 0, sign, i.reloc[n]); 7509 7510 /* This is tough to explain. We end up with this one if we 7511 * have operands that look like 7512 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to 7513 * obtain the absolute address of the GOT, and it is strongly 7514 * preferable from a performance point of view to avoid using 7515 * a runtime relocation for this. The actual sequence of 7516 * instructions often look something like: 7517 * 7518 * call .L66 7519 * .L66: 7520 * popl %ebx 7521 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx 7522 * 7523 * The call and pop essentially return the absolute address 7524 * of the label .L66 and store it in %ebx. The linker itself 7525 * will ultimately change the first operand of the addl so 7526 * that %ebx points to the GOT, but to keep things simple, the 7527 * .o file must have this operand set so that it generates not 7528 * the absolute address of .L66, but the absolute address of 7529 * itself. This allows the linker itself simply treat a GOTPC 7530 * relocation as asking for a pcrel offset to the GOT to be 7531 * added in, and the addend of the relocation is stored in the 7532 * operand field for the instruction itself. 7533 * 7534 * Our job here is to fix the operand so that it would add 7535 * the correct offset so that %ebx would point to itself. The 7536 * thing that is tricky is that .-.L66 will point to the 7537 * beginning of the instruction, so we need to further modify 7538 * the operand so that it will point to itself. There are 7539 * other cases where you have something like: 7540 * 7541 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] 7542 * 7543 * and here no correction would be required. Internally in 7544 * the assembler we treat operands of this form as not being 7545 * pcrel since the '.' is explicitly mentioned, and I wonder 7546 * whether it would simplify matters to do it this way. Who 7547 * knows. In earlier versions of the PIC patches, the 7548 * pcrel_adjust field was used to store the correction, but 7549 * since the expression is not pcrel, I felt it would be 7550 * confusing to do it this way. */ 7551 7552 if ((reloc_type == BFD_RELOC_32 7553 || reloc_type == BFD_RELOC_X86_64_32S 7554 || reloc_type == BFD_RELOC_64) 7555 && GOT_symbol 7556 && GOT_symbol == i.op[n].imms->X_add_symbol 7557 && (i.op[n].imms->X_op == O_symbol 7558 || (i.op[n].imms->X_op == O_add 7559 && ((symbol_get_value_expression 7560 (i.op[n].imms->X_op_symbol)->X_op) 7561 == O_subtract)))) 7562 { 7563 offsetT add; 7564 7565 if (insn_start_frag == frag_now) 7566 add = (p - frag_now->fr_literal) - insn_start_off; 7567 else 7568 { 7569 fragS *fr; 7570 7571 add = insn_start_frag->fr_fix - insn_start_off; 7572 for (fr = insn_start_frag->fr_next; 7573 fr && fr != frag_now; fr = fr->fr_next) 7574 add += fr->fr_fix; 7575 add += p - frag_now->fr_literal; 7576 } 7577 7578 if (!object_64bit) 7579 reloc_type = BFD_RELOC_386_GOTPC; 7580 else if (size == 4) 7581 reloc_type = BFD_RELOC_X86_64_GOTPC32; 7582 else if (size == 8) 7583 reloc_type = BFD_RELOC_X86_64_GOTPC64; 7584 i.op[n].imms->X_add_number += add; 7585 } 7586 fix_new_exp (frag_now, p - frag_now->fr_literal, size, 7587 i.op[n].imms, 0, reloc_type); 7588 } 7589 } 7590 } 7591} 7592 7593/* x86_cons_fix_new is called via the expression parsing code when a 7594 reloc is needed. We use this hook to get the correct .got reloc. */ 7595static int cons_sign = -1; 7596 7597void 7598x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len, 7599 expressionS *exp, bfd_reloc_code_real_type r) 7600{ 7601 r = reloc (len, 0, cons_sign, r); 7602 7603#ifdef TE_PE 7604 if (exp->X_op == O_secrel) 7605 { 7606 exp->X_op = O_symbol; 7607 r = BFD_RELOC_32_SECREL; 7608 } 7609#endif 7610 7611 fix_new_exp (frag, off, len, exp, 0, r); 7612} 7613 7614/* Export the ABI address size for use by TC_ADDRESS_BYTES for the 7615 purpose of the `.dc.a' internal pseudo-op. */ 7616 7617int 7618x86_address_bytes (void) 7619{ 7620 if ((stdoutput->arch_info->mach & bfd_mach_x64_32)) 7621 return 4; 7622 return stdoutput->arch_info->bits_per_address / 8; 7623} 7624 7625#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \ 7626 || defined (LEX_AT) 7627# define lex_got(reloc, adjust, types) NULL 7628#else 7629/* Parse operands of the form 7630 <symbol>@GOTOFF+<nnn> 7631 and similar .plt or .got references. 7632 7633 If we find one, set up the correct relocation in RELOC and copy the 7634 input string, minus the `@GOTOFF' into a malloc'd buffer for 7635 parsing by the calling routine. Return this buffer, and if ADJUST 7636 is non-null set it to the length of the string we removed from the 7637 input line. Otherwise return NULL. */ 7638static char * 7639lex_got (enum bfd_reloc_code_real *rel, 7640 int *adjust, 7641 i386_operand_type *types) 7642{ 7643 /* Some of the relocations depend on the size of what field is to 7644 be relocated. But in our callers i386_immediate and i386_displacement 7645 we don't yet know the operand size (this will be set by insn 7646 matching). Hence we record the word32 relocation here, 7647 and adjust the reloc according to the real size in reloc(). */ 7648 static const struct { 7649 const char *str; 7650 int len; 7651 const enum bfd_reloc_code_real rel[2]; 7652 const i386_operand_type types64; 7653 } gotrel[] = { 7654#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 7655 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32, 7656 BFD_RELOC_SIZE32 }, 7657 OPERAND_TYPE_IMM32_64 }, 7658#endif 7659 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real, 7660 BFD_RELOC_X86_64_PLTOFF64 }, 7661 OPERAND_TYPE_IMM64 }, 7662 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32, 7663 BFD_RELOC_X86_64_PLT32 }, 7664 OPERAND_TYPE_IMM32_32S_DISP32 }, 7665 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real, 7666 BFD_RELOC_X86_64_GOTPLT64 }, 7667 OPERAND_TYPE_IMM64_DISP64 }, 7668 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF, 7669 BFD_RELOC_X86_64_GOTOFF64 }, 7670 OPERAND_TYPE_IMM64_DISP64 }, 7671 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real, 7672 BFD_RELOC_X86_64_GOTPCREL }, 7673 OPERAND_TYPE_IMM32_32S_DISP32 }, 7674 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD, 7675 BFD_RELOC_X86_64_TLSGD }, 7676 OPERAND_TYPE_IMM32_32S_DISP32 }, 7677 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM, 7678 _dummy_first_bfd_reloc_code_real }, 7679 OPERAND_TYPE_NONE }, 7680 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real, 7681 BFD_RELOC_X86_64_TLSLD }, 7682 OPERAND_TYPE_IMM32_32S_DISP32 }, 7683 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32, 7684 BFD_RELOC_X86_64_GOTTPOFF }, 7685 OPERAND_TYPE_IMM32_32S_DISP32 }, 7686 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32, 7687 BFD_RELOC_X86_64_TPOFF32 }, 7688 OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, 7689 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE, 7690 _dummy_first_bfd_reloc_code_real }, 7691 OPERAND_TYPE_NONE }, 7692 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32, 7693 BFD_RELOC_X86_64_DTPOFF32 }, 7694 OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, 7695 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE, 7696 _dummy_first_bfd_reloc_code_real }, 7697 OPERAND_TYPE_NONE }, 7698 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE, 7699 _dummy_first_bfd_reloc_code_real }, 7700 OPERAND_TYPE_NONE }, 7701 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32, 7702 BFD_RELOC_X86_64_GOT32 }, 7703 OPERAND_TYPE_IMM32_32S_64_DISP32 }, 7704 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC, 7705 BFD_RELOC_X86_64_GOTPC32_TLSDESC }, 7706 OPERAND_TYPE_IMM32_32S_DISP32 }, 7707 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL, 7708 BFD_RELOC_X86_64_TLSDESC_CALL }, 7709 OPERAND_TYPE_IMM32_32S_DISP32 }, 7710 }; 7711 char *cp; 7712 unsigned int j; 7713 7714#if defined (OBJ_MAYBE_ELF) 7715 if (!IS_ELF) 7716 return NULL; 7717#endif 7718 7719 for (cp = input_line_pointer; *cp != '@'; cp++) 7720 if (is_end_of_line[(unsigned char) *cp] || *cp == ',') 7721 return NULL; 7722 7723 for (j = 0; j < ARRAY_SIZE (gotrel); j++) 7724 { 7725 int len = gotrel[j].len; 7726 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) 7727 { 7728 if (gotrel[j].rel[object_64bit] != 0) 7729 { 7730 int first, second; 7731 char *tmpbuf, *past_reloc; 7732 7733 *rel = gotrel[j].rel[object_64bit]; 7734 7735 if (types) 7736 { 7737 if (flag_code != CODE_64BIT) 7738 { 7739 types->bitfield.imm32 = 1; 7740 types->bitfield.disp32 = 1; 7741 } 7742 else 7743 *types = gotrel[j].types64; 7744 } 7745 7746 if (j != 0 && GOT_symbol == NULL) 7747 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); 7748 7749 /* The length of the first part of our input line. */ 7750 first = cp - input_line_pointer; 7751 7752 /* The second part goes from after the reloc token until 7753 (and including) an end_of_line char or comma. */ 7754 past_reloc = cp + 1 + len; 7755 cp = past_reloc; 7756 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') 7757 ++cp; 7758 second = cp + 1 - past_reloc; 7759 7760 /* Allocate and copy string. The trailing NUL shouldn't 7761 be necessary, but be safe. */ 7762 tmpbuf = XNEWVEC (char, first + second + 2); 7763 memcpy (tmpbuf, input_line_pointer, first); 7764 if (second != 0 && *past_reloc != ' ') 7765 /* Replace the relocation token with ' ', so that 7766 errors like foo@GOTOFF1 will be detected. */ 7767 tmpbuf[first++] = ' '; 7768 else 7769 /* Increment length by 1 if the relocation token is 7770 removed. */ 7771 len++; 7772 if (adjust) 7773 *adjust = len; 7774 memcpy (tmpbuf + first, past_reloc, second); 7775 tmpbuf[first + second] = '\0'; 7776 return tmpbuf; 7777 } 7778 7779 as_bad (_("@%s reloc is not supported with %d-bit output format"), 7780 gotrel[j].str, 1 << (5 + object_64bit)); 7781 return NULL; 7782 } 7783 } 7784 7785 /* Might be a symbol version string. Don't as_bad here. */ 7786 return NULL; 7787} 7788#endif 7789 7790#ifdef TE_PE 7791#ifdef lex_got 7792#undef lex_got 7793#endif 7794/* Parse operands of the form 7795 <symbol>@SECREL32+<nnn> 7796 7797 If we find one, set up the correct relocation in RELOC and copy the 7798 input string, minus the `@SECREL32' into a malloc'd buffer for 7799 parsing by the calling routine. Return this buffer, and if ADJUST 7800 is non-null set it to the length of the string we removed from the 7801 input line. Otherwise return NULL. 7802 7803 This function is copied from the ELF version above adjusted for PE targets. */ 7804 7805static char * 7806lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED, 7807 int *adjust ATTRIBUTE_UNUSED, 7808 i386_operand_type *types) 7809{ 7810 static const struct 7811 { 7812 const char *str; 7813 int len; 7814 const enum bfd_reloc_code_real rel[2]; 7815 const i386_operand_type types64; 7816 } 7817 gotrel[] = 7818 { 7819 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL, 7820 BFD_RELOC_32_SECREL }, 7821 OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, 7822 }; 7823 7824 char *cp; 7825 unsigned j; 7826 7827 for (cp = input_line_pointer; *cp != '@'; cp++) 7828 if (is_end_of_line[(unsigned char) *cp] || *cp == ',') 7829 return NULL; 7830 7831 for (j = 0; j < ARRAY_SIZE (gotrel); j++) 7832 { 7833 int len = gotrel[j].len; 7834 7835 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) 7836 { 7837 if (gotrel[j].rel[object_64bit] != 0) 7838 { 7839 int first, second; 7840 char *tmpbuf, *past_reloc; 7841 7842 *rel = gotrel[j].rel[object_64bit]; 7843 if (adjust) 7844 *adjust = len; 7845 7846 if (types) 7847 { 7848 if (flag_code != CODE_64BIT) 7849 { 7850 types->bitfield.imm32 = 1; 7851 types->bitfield.disp32 = 1; 7852 } 7853 else 7854 *types = gotrel[j].types64; 7855 } 7856 7857 /* The length of the first part of our input line. */ 7858 first = cp - input_line_pointer; 7859 7860 /* The second part goes from after the reloc token until 7861 (and including) an end_of_line char or comma. */ 7862 past_reloc = cp + 1 + len; 7863 cp = past_reloc; 7864 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') 7865 ++cp; 7866 second = cp + 1 - past_reloc; 7867 7868 /* Allocate and copy string. The trailing NUL shouldn't 7869 be necessary, but be safe. */ 7870 tmpbuf = XNEWVEC (char, first + second + 2); 7871 memcpy (tmpbuf, input_line_pointer, first); 7872 if (second != 0 && *past_reloc != ' ') 7873 /* Replace the relocation token with ' ', so that 7874 errors like foo@SECLREL321 will be detected. */ 7875 tmpbuf[first++] = ' '; 7876 memcpy (tmpbuf + first, past_reloc, second); 7877 tmpbuf[first + second] = '\0'; 7878 return tmpbuf; 7879 } 7880 7881 as_bad (_("@%s reloc is not supported with %d-bit output format"), 7882 gotrel[j].str, 1 << (5 + object_64bit)); 7883 return NULL; 7884 } 7885 } 7886 7887 /* Might be a symbol version string. Don't as_bad here. */ 7888 return NULL; 7889} 7890 7891#endif /* TE_PE */ 7892 7893bfd_reloc_code_real_type 7894x86_cons (expressionS *exp, int size) 7895{ 7896 bfd_reloc_code_real_type got_reloc = NO_RELOC; 7897 7898 intel_syntax = -intel_syntax; 7899 7900 exp->X_md = 0; 7901 if (size == 4 || (object_64bit && size == 8)) 7902 { 7903 /* Handle @GOTOFF and the like in an expression. */ 7904 char *save; 7905 char *gotfree_input_line; 7906 int adjust = 0; 7907 7908 save = input_line_pointer; 7909 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL); 7910 if (gotfree_input_line) 7911 input_line_pointer = gotfree_input_line; 7912 7913 expression (exp); 7914 7915 if (gotfree_input_line) 7916 { 7917 /* expression () has merrily parsed up to the end of line, 7918 or a comma - in the wrong buffer. Transfer how far 7919 input_line_pointer has moved to the right buffer. */ 7920 input_line_pointer = (save 7921 + (input_line_pointer - gotfree_input_line) 7922 + adjust); 7923 free (gotfree_input_line); 7924 if (exp->X_op == O_constant 7925 || exp->X_op == O_absent 7926 || exp->X_op == O_illegal 7927 || exp->X_op == O_register 7928 || exp->X_op == O_big) 7929 { 7930 char c = *input_line_pointer; 7931 *input_line_pointer = 0; 7932 as_bad (_("missing or invalid expression `%s'"), save); 7933 *input_line_pointer = c; 7934 } 7935 } 7936 } 7937 else 7938 expression (exp); 7939 7940 intel_syntax = -intel_syntax; 7941 7942 if (intel_syntax) 7943 i386_intel_simplify (exp); 7944 7945 return got_reloc; 7946} 7947 7948static void 7949signed_cons (int size) 7950{ 7951 if (flag_code == CODE_64BIT) 7952 cons_sign = 1; 7953 cons (size); 7954 cons_sign = -1; 7955} 7956 7957#ifdef TE_PE 7958static void 7959pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) 7960{ 7961 expressionS exp; 7962 7963 do 7964 { 7965 expression (&exp); 7966 if (exp.X_op == O_symbol) 7967 exp.X_op = O_secrel; 7968 7969 emit_expr (&exp, 4); 7970 } 7971 while (*input_line_pointer++ == ','); 7972 7973 input_line_pointer--; 7974 demand_empty_rest_of_line (); 7975} 7976#endif 7977 7978/* Handle Vector operations. */ 7979 7980static char * 7981check_VecOperations (char *op_string, char *op_end) 7982{ 7983 const reg_entry *mask; 7984 const char *saved; 7985 char *end_op; 7986 7987 while (*op_string 7988 && (op_end == NULL || op_string < op_end)) 7989 { 7990 saved = op_string; 7991 if (*op_string == '{') 7992 { 7993 op_string++; 7994 7995 /* Check broadcasts. */ 7996 if (strncmp (op_string, "1to", 3) == 0) 7997 { 7998 int bcst_type; 7999 8000 if (i.broadcast) 8001 goto duplicated_vec_op; 8002 8003 op_string += 3; 8004 if (*op_string == '8') 8005 bcst_type = BROADCAST_1TO8; 8006 else if (*op_string == '4') 8007 bcst_type = BROADCAST_1TO4; 8008 else if (*op_string == '2') 8009 bcst_type = BROADCAST_1TO2; 8010 else if (*op_string == '1' 8011 && *(op_string+1) == '6') 8012 { 8013 bcst_type = BROADCAST_1TO16; 8014 op_string++; 8015 } 8016 else 8017 { 8018 as_bad (_("Unsupported broadcast: `%s'"), saved); 8019 return NULL; 8020 } 8021 op_string++; 8022 8023 broadcast_op.type = bcst_type; 8024 broadcast_op.operand = this_operand; 8025 i.broadcast = &broadcast_op; 8026 } 8027 /* Check masking operation. */ 8028 else if ((mask = parse_register (op_string, &end_op)) != NULL) 8029 { 8030 /* k0 can't be used for write mask. */ 8031 if (mask->reg_num == 0) 8032 { 8033 as_bad (_("`%s' can't be used for write mask"), 8034 op_string); 8035 return NULL; 8036 } 8037 8038 if (!i.mask) 8039 { 8040 mask_op.mask = mask; 8041 mask_op.zeroing = 0; 8042 mask_op.operand = this_operand; 8043 i.mask = &mask_op; 8044 } 8045 else 8046 { 8047 if (i.mask->mask) 8048 goto duplicated_vec_op; 8049 8050 i.mask->mask = mask; 8051 8052 /* Only "{z}" is allowed here. No need to check 8053 zeroing mask explicitly. */ 8054 if (i.mask->operand != this_operand) 8055 { 8056 as_bad (_("invalid write mask `%s'"), saved); 8057 return NULL; 8058 } 8059 } 8060 8061 op_string = end_op; 8062 } 8063 /* Check zeroing-flag for masking operation. */ 8064 else if (*op_string == 'z') 8065 { 8066 if (!i.mask) 8067 { 8068 mask_op.mask = NULL; 8069 mask_op.zeroing = 1; 8070 mask_op.operand = this_operand; 8071 i.mask = &mask_op; 8072 } 8073 else 8074 { 8075 if (i.mask->zeroing) 8076 { 8077 duplicated_vec_op: 8078 as_bad (_("duplicated `%s'"), saved); 8079 return NULL; 8080 } 8081 8082 i.mask->zeroing = 1; 8083 8084 /* Only "{%k}" is allowed here. No need to check mask 8085 register explicitly. */ 8086 if (i.mask->operand != this_operand) 8087 { 8088 as_bad (_("invalid zeroing-masking `%s'"), 8089 saved); 8090 return NULL; 8091 } 8092 } 8093 8094 op_string++; 8095 } 8096 else 8097 goto unknown_vec_op; 8098 8099 if (*op_string != '}') 8100 { 8101 as_bad (_("missing `}' in `%s'"), saved); 8102 return NULL; 8103 } 8104 op_string++; 8105 continue; 8106 } 8107 unknown_vec_op: 8108 /* We don't know this one. */ 8109 as_bad (_("unknown vector operation: `%s'"), saved); 8110 return NULL; 8111 } 8112 8113 return op_string; 8114} 8115 8116static int 8117i386_immediate (char *imm_start) 8118{ 8119 char *save_input_line_pointer; 8120 char *gotfree_input_line; 8121 segT exp_seg = 0; 8122 expressionS *exp; 8123 i386_operand_type types; 8124 8125 operand_type_set (&types, ~0); 8126 8127 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) 8128 { 8129 as_bad (_("at most %d immediate operands are allowed"), 8130 MAX_IMMEDIATE_OPERANDS); 8131 return 0; 8132 } 8133 8134 exp = &im_expressions[i.imm_operands++]; 8135 i.op[this_operand].imms = exp; 8136 8137 if (is_space_char (*imm_start)) 8138 ++imm_start; 8139 8140 save_input_line_pointer = input_line_pointer; 8141 input_line_pointer = imm_start; 8142 8143 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); 8144 if (gotfree_input_line) 8145 input_line_pointer = gotfree_input_line; 8146 8147 exp_seg = expression (exp); 8148 8149 SKIP_WHITESPACE (); 8150 8151 /* Handle vector operations. */ 8152 if (*input_line_pointer == '{') 8153 { 8154 input_line_pointer = check_VecOperations (input_line_pointer, 8155 NULL); 8156 if (input_line_pointer == NULL) 8157 return 0; 8158 } 8159 8160 if (*input_line_pointer) 8161 as_bad (_("junk `%s' after expression"), input_line_pointer); 8162 8163 input_line_pointer = save_input_line_pointer; 8164 if (gotfree_input_line) 8165 { 8166 free (gotfree_input_line); 8167 8168 if (exp->X_op == O_constant || exp->X_op == O_register) 8169 exp->X_op = O_illegal; 8170 } 8171 8172 return i386_finalize_immediate (exp_seg, exp, types, imm_start); 8173} 8174 8175static int 8176i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, 8177 i386_operand_type types, const char *imm_start) 8178{ 8179 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big) 8180 { 8181 if (imm_start) 8182 as_bad (_("missing or invalid immediate expression `%s'"), 8183 imm_start); 8184 return 0; 8185 } 8186 else if (exp->X_op == O_constant) 8187 { 8188 /* Size it properly later. */ 8189 i.types[this_operand].bitfield.imm64 = 1; 8190 /* If not 64bit, sign extend val. */ 8191 if (flag_code != CODE_64BIT 8192 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) 8193 exp->X_add_number 8194 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); 8195 } 8196#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) 8197 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour 8198 && exp_seg != absolute_section 8199 && exp_seg != text_section 8200 && exp_seg != data_section 8201 && exp_seg != bss_section 8202 && exp_seg != undefined_section 8203 && !bfd_is_com_section (exp_seg)) 8204 { 8205 as_bad (_("unimplemented segment %s in operand"), exp_seg->name); 8206 return 0; 8207 } 8208#endif 8209 else if (!intel_syntax && exp_seg == reg_section) 8210 { 8211 if (imm_start) 8212 as_bad (_("illegal immediate register operand %s"), imm_start); 8213 return 0; 8214 } 8215 else 8216 { 8217 /* This is an address. The size of the address will be 8218 determined later, depending on destination register, 8219 suffix, or the default for the section. */ 8220 i.types[this_operand].bitfield.imm8 = 1; 8221 i.types[this_operand].bitfield.imm16 = 1; 8222 i.types[this_operand].bitfield.imm32 = 1; 8223 i.types[this_operand].bitfield.imm32s = 1; 8224 i.types[this_operand].bitfield.imm64 = 1; 8225 i.types[this_operand] = operand_type_and (i.types[this_operand], 8226 types); 8227 } 8228 8229 return 1; 8230} 8231 8232static char * 8233i386_scale (char *scale) 8234{ 8235 offsetT val; 8236 char *save = input_line_pointer; 8237 8238 input_line_pointer = scale; 8239 val = get_absolute_expression (); 8240 8241 switch (val) 8242 { 8243 case 1: 8244 i.log2_scale_factor = 0; 8245 break; 8246 case 2: 8247 i.log2_scale_factor = 1; 8248 break; 8249 case 4: 8250 i.log2_scale_factor = 2; 8251 break; 8252 case 8: 8253 i.log2_scale_factor = 3; 8254 break; 8255 default: 8256 { 8257 char sep = *input_line_pointer; 8258 8259 *input_line_pointer = '\0'; 8260 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), 8261 scale); 8262 *input_line_pointer = sep; 8263 input_line_pointer = save; 8264 return NULL; 8265 } 8266 } 8267 if (i.log2_scale_factor != 0 && i.index_reg == 0) 8268 { 8269 as_warn (_("scale factor of %d without an index register"), 8270 1 << i.log2_scale_factor); 8271 i.log2_scale_factor = 0; 8272 } 8273 scale = input_line_pointer; 8274 input_line_pointer = save; 8275 return scale; 8276} 8277 8278static int 8279i386_displacement (char *disp_start, char *disp_end) 8280{ 8281 expressionS *exp; 8282 segT exp_seg = 0; 8283 char *save_input_line_pointer; 8284 char *gotfree_input_line; 8285 int override; 8286 i386_operand_type bigdisp, types = anydisp; 8287 int ret; 8288 8289 if (i.disp_operands == MAX_MEMORY_OPERANDS) 8290 { 8291 as_bad (_("at most %d displacement operands are allowed"), 8292 MAX_MEMORY_OPERANDS); 8293 return 0; 8294 } 8295 8296 operand_type_set (&bigdisp, 0); 8297 if ((i.types[this_operand].bitfield.jumpabsolute) 8298 || (!current_templates->start->opcode_modifier.jump 8299 && !current_templates->start->opcode_modifier.jumpdword)) 8300 { 8301 bigdisp.bitfield.disp32 = 1; 8302 override = (i.prefix[ADDR_PREFIX] != 0); 8303 if (flag_code == CODE_64BIT) 8304 { 8305 if (!override) 8306 { 8307 bigdisp.bitfield.disp32s = 1; 8308 bigdisp.bitfield.disp64 = 1; 8309 } 8310 } 8311 else if ((flag_code == CODE_16BIT) ^ override) 8312 { 8313 bigdisp.bitfield.disp32 = 0; 8314 bigdisp.bitfield.disp16 = 1; 8315 } 8316 } 8317 else 8318 { 8319 /* For PC-relative branches, the width of the displacement 8320 is dependent upon data size, not address size. */ 8321 override = (i.prefix[DATA_PREFIX] != 0); 8322 if (flag_code == CODE_64BIT) 8323 { 8324 if (override || i.suffix == WORD_MNEM_SUFFIX) 8325 bigdisp.bitfield.disp16 = 1; 8326 else 8327 { 8328 bigdisp.bitfield.disp32 = 1; 8329 bigdisp.bitfield.disp32s = 1; 8330 } 8331 } 8332 else 8333 { 8334 if (!override) 8335 override = (i.suffix == (flag_code != CODE_16BIT 8336 ? WORD_MNEM_SUFFIX 8337 : LONG_MNEM_SUFFIX)); 8338 bigdisp.bitfield.disp32 = 1; 8339 if ((flag_code == CODE_16BIT) ^ override) 8340 { 8341 bigdisp.bitfield.disp32 = 0; 8342 bigdisp.bitfield.disp16 = 1; 8343 } 8344 } 8345 } 8346 i.types[this_operand] = operand_type_or (i.types[this_operand], 8347 bigdisp); 8348 8349 exp = &disp_expressions[i.disp_operands]; 8350 i.op[this_operand].disps = exp; 8351 i.disp_operands++; 8352 save_input_line_pointer = input_line_pointer; 8353 input_line_pointer = disp_start; 8354 END_STRING_AND_SAVE (disp_end); 8355 8356#ifndef GCC_ASM_O_HACK 8357#define GCC_ASM_O_HACK 0 8358#endif 8359#if GCC_ASM_O_HACK 8360 END_STRING_AND_SAVE (disp_end + 1); 8361 if (i.types[this_operand].bitfield.baseIndex 8362 && displacement_string_end[-1] == '+') 8363 { 8364 /* This hack is to avoid a warning when using the "o" 8365 constraint within gcc asm statements. 8366 For instance: 8367 8368 #define _set_tssldt_desc(n,addr,limit,type) \ 8369 __asm__ __volatile__ ( \ 8370 "movw %w2,%0\n\t" \ 8371 "movw %w1,2+%0\n\t" \ 8372 "rorl $16,%1\n\t" \ 8373 "movb %b1,4+%0\n\t" \ 8374 "movb %4,5+%0\n\t" \ 8375 "movb $0,6+%0\n\t" \ 8376 "movb %h1,7+%0\n\t" \ 8377 "rorl $16,%1" \ 8378 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) 8379 8380 This works great except that the output assembler ends 8381 up looking a bit weird if it turns out that there is 8382 no offset. You end up producing code that looks like: 8383 8384 #APP 8385 movw $235,(%eax) 8386 movw %dx,2+(%eax) 8387 rorl $16,%edx 8388 movb %dl,4+(%eax) 8389 movb $137,5+(%eax) 8390 movb $0,6+(%eax) 8391 movb %dh,7+(%eax) 8392 rorl $16,%edx 8393 #NO_APP 8394 8395 So here we provide the missing zero. */ 8396 8397 *displacement_string_end = '0'; 8398 } 8399#endif 8400 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); 8401 if (gotfree_input_line) 8402 input_line_pointer = gotfree_input_line; 8403 8404 exp_seg = expression (exp); 8405 8406 SKIP_WHITESPACE (); 8407 if (*input_line_pointer) 8408 as_bad (_("junk `%s' after expression"), input_line_pointer); 8409#if GCC_ASM_O_HACK 8410 RESTORE_END_STRING (disp_end + 1); 8411#endif 8412 input_line_pointer = save_input_line_pointer; 8413 if (gotfree_input_line) 8414 { 8415 free (gotfree_input_line); 8416 8417 if (exp->X_op == O_constant || exp->X_op == O_register) 8418 exp->X_op = O_illegal; 8419 } 8420 8421 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start); 8422 8423 RESTORE_END_STRING (disp_end); 8424 8425 return ret; 8426} 8427 8428static int 8429i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, 8430 i386_operand_type types, const char *disp_start) 8431{ 8432 i386_operand_type bigdisp; 8433 int ret = 1; 8434 8435 /* We do this to make sure that the section symbol is in 8436 the symbol table. We will ultimately change the relocation 8437 to be relative to the beginning of the section. */ 8438 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF 8439 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL 8440 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) 8441 { 8442 if (exp->X_op != O_symbol) 8443 goto inv_disp; 8444 8445 if (S_IS_LOCAL (exp->X_add_symbol) 8446 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section 8447 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section) 8448 section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); 8449 exp->X_op = O_subtract; 8450 exp->X_op_symbol = GOT_symbol; 8451 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) 8452 i.reloc[this_operand] = BFD_RELOC_32_PCREL; 8453 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) 8454 i.reloc[this_operand] = BFD_RELOC_64; 8455 else 8456 i.reloc[this_operand] = BFD_RELOC_32; 8457 } 8458 8459 else if (exp->X_op == O_absent 8460 || exp->X_op == O_illegal 8461 || exp->X_op == O_big) 8462 { 8463 inv_disp: 8464 as_bad (_("missing or invalid displacement expression `%s'"), 8465 disp_start); 8466 ret = 0; 8467 } 8468 8469 else if (flag_code == CODE_64BIT 8470 && !i.prefix[ADDR_PREFIX] 8471 && exp->X_op == O_constant) 8472 { 8473 /* Since displacement is signed extended to 64bit, don't allow 8474 disp32 and turn off disp32s if they are out of range. */ 8475 i.types[this_operand].bitfield.disp32 = 0; 8476 if (!fits_in_signed_long (exp->X_add_number)) 8477 { 8478 i.types[this_operand].bitfield.disp32s = 0; 8479 if (i.types[this_operand].bitfield.baseindex) 8480 { 8481 as_bad (_("0x%lx out range of signed 32bit displacement"), 8482 (long) exp->X_add_number); 8483 ret = 0; 8484 } 8485 } 8486 } 8487 8488#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) 8489 else if (exp->X_op != O_constant 8490 && OUTPUT_FLAVOR == bfd_target_aout_flavour 8491 && exp_seg != absolute_section 8492 && exp_seg != text_section 8493 && exp_seg != data_section 8494 && exp_seg != bss_section 8495 && exp_seg != undefined_section 8496 && !bfd_is_com_section (exp_seg)) 8497 { 8498 as_bad (_("unimplemented segment %s in operand"), exp_seg->name); 8499 ret = 0; 8500 } 8501#endif 8502 8503 /* Check if this is a displacement only operand. */ 8504 bigdisp = i.types[this_operand]; 8505 bigdisp.bitfield.disp8 = 0; 8506 bigdisp.bitfield.disp16 = 0; 8507 bigdisp.bitfield.disp32 = 0; 8508 bigdisp.bitfield.disp32s = 0; 8509 bigdisp.bitfield.disp64 = 0; 8510 if (operand_type_all_zero (&bigdisp)) 8511 i.types[this_operand] = operand_type_and (i.types[this_operand], 8512 types); 8513 8514 return ret; 8515} 8516 8517/* Make sure the memory operand we've been dealt is valid. 8518 Return 1 on success, 0 on a failure. */ 8519 8520static int 8521i386_index_check (const char *operand_string) 8522{ 8523 const char *kind = "base/index"; 8524 enum flag_code addr_mode; 8525 8526 if (i.prefix[ADDR_PREFIX]) 8527 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT; 8528 else 8529 { 8530 addr_mode = flag_code; 8531 8532#if INFER_ADDR_PREFIX 8533 if (i.mem_operands == 0) 8534 { 8535 /* Infer address prefix from the first memory operand. */ 8536 const reg_entry *addr_reg = i.base_reg; 8537 8538 if (addr_reg == NULL) 8539 addr_reg = i.index_reg; 8540 8541 if (addr_reg) 8542 { 8543 if (addr_reg->reg_num == RegEip 8544 || addr_reg->reg_num == RegEiz 8545 || addr_reg->reg_type.bitfield.reg32) 8546 addr_mode = CODE_32BIT; 8547 else if (flag_code != CODE_64BIT 8548 && addr_reg->reg_type.bitfield.reg16) 8549 addr_mode = CODE_16BIT; 8550 8551 if (addr_mode != flag_code) 8552 { 8553 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; 8554 i.prefixes += 1; 8555 /* Change the size of any displacement too. At most one 8556 of Disp16 or Disp32 is set. 8557 FIXME. There doesn't seem to be any real need for 8558 separate Disp16 and Disp32 flags. The same goes for 8559 Imm16 and Imm32. Removing them would probably clean 8560 up the code quite a lot. */ 8561 if (flag_code != CODE_64BIT 8562 && (i.types[this_operand].bitfield.disp16 8563 || i.types[this_operand].bitfield.disp32)) 8564 i.types[this_operand] 8565 = operand_type_xor (i.types[this_operand], disp16_32); 8566 } 8567 } 8568 } 8569#endif 8570 } 8571 8572 if (current_templates->start->opcode_modifier.isstring 8573 && !current_templates->start->opcode_modifier.immext 8574 && (current_templates->end[-1].opcode_modifier.isstring 8575 || i.mem_operands)) 8576 { 8577 /* Memory operands of string insns are special in that they only allow 8578 a single register (rDI, rSI, or rBX) as their memory address. */ 8579 const reg_entry *expected_reg; 8580 static const char *di_si[][2] = 8581 { 8582 { "esi", "edi" }, 8583 { "si", "di" }, 8584 { "rsi", "rdi" } 8585 }; 8586 static const char *bx[] = { "ebx", "bx", "rbx" }; 8587 8588 kind = "string address"; 8589 8590 if (current_templates->start->opcode_modifier.repprefixok) 8591 { 8592 i386_operand_type type = current_templates->end[-1].operand_types[0]; 8593 8594 if (!type.bitfield.baseindex 8595 || ((!i.mem_operands != !intel_syntax) 8596 && current_templates->end[-1].operand_types[1] 8597 .bitfield.baseindex)) 8598 type = current_templates->end[-1].operand_types[1]; 8599 expected_reg = hash_find (reg_hash, 8600 di_si[addr_mode][type.bitfield.esseg]); 8601 8602 } 8603 else 8604 expected_reg = hash_find (reg_hash, bx[addr_mode]); 8605 8606 if (i.base_reg != expected_reg 8607 || i.index_reg 8608 || operand_type_check (i.types[this_operand], disp)) 8609 { 8610 /* The second memory operand must have the same size as 8611 the first one. */ 8612 if (i.mem_operands 8613 && i.base_reg 8614 && !((addr_mode == CODE_64BIT 8615 && i.base_reg->reg_type.bitfield.reg64) 8616 || (addr_mode == CODE_32BIT 8617 ? i.base_reg->reg_type.bitfield.reg32 8618 : i.base_reg->reg_type.bitfield.reg16))) 8619 goto bad_address; 8620 8621 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"), 8622 operand_string, 8623 intel_syntax ? '[' : '(', 8624 register_prefix, 8625 expected_reg->reg_name, 8626 intel_syntax ? ']' : ')'); 8627 return 1; 8628 } 8629 else 8630 return 1; 8631 8632bad_address: 8633 as_bad (_("`%s' is not a valid %s expression"), 8634 operand_string, kind); 8635 return 0; 8636 } 8637 else 8638 { 8639 if (addr_mode != CODE_16BIT) 8640 { 8641 /* 32-bit/64-bit checks. */ 8642 if ((i.base_reg 8643 && (addr_mode == CODE_64BIT 8644 ? !i.base_reg->reg_type.bitfield.reg64 8645 : !i.base_reg->reg_type.bitfield.reg32) 8646 && (i.index_reg 8647 || (i.base_reg->reg_num 8648 != (addr_mode == CODE_64BIT ? RegRip : RegEip)))) 8649 || (i.index_reg 8650 && !i.index_reg->reg_type.bitfield.regxmm 8651 && !i.index_reg->reg_type.bitfield.regymm 8652 && !i.index_reg->reg_type.bitfield.regzmm 8653 && ((addr_mode == CODE_64BIT 8654 ? !(i.index_reg->reg_type.bitfield.reg64 8655 || i.index_reg->reg_num == RegRiz) 8656 : !(i.index_reg->reg_type.bitfield.reg32 8657 || i.index_reg->reg_num == RegEiz)) 8658 || !i.index_reg->reg_type.bitfield.baseindex))) 8659 goto bad_address; 8660 8661 /* bndmk, bndldx, and bndstx have special restrictions. */ 8662 if (current_templates->start->base_opcode == 0xf30f1b 8663 || (current_templates->start->base_opcode & ~1) == 0x0f1a) 8664 { 8665 /* They cannot use RIP-relative addressing. */ 8666 if (i.base_reg && i.base_reg->reg_num == RegRip) 8667 { 8668 as_bad (_("`%s' cannot be used here"), operand_string); 8669 return 0; 8670 } 8671 8672 /* bndldx and bndstx ignore their scale factor. */ 8673 if (current_templates->start->base_opcode != 0xf30f1b 8674 && i.log2_scale_factor) 8675 as_warn (_("register scaling is being ignored here")); 8676 } 8677 } 8678 else 8679 { 8680 /* 16-bit checks. */ 8681 if ((i.base_reg 8682 && (!i.base_reg->reg_type.bitfield.reg16 8683 || !i.base_reg->reg_type.bitfield.baseindex)) 8684 || (i.index_reg 8685 && (!i.index_reg->reg_type.bitfield.reg16 8686 || !i.index_reg->reg_type.bitfield.baseindex 8687 || !(i.base_reg 8688 && i.base_reg->reg_num < 6 8689 && i.index_reg->reg_num >= 6 8690 && i.log2_scale_factor == 0)))) 8691 goto bad_address; 8692 } 8693 } 8694 return 1; 8695} 8696 8697/* Handle vector immediates. */ 8698 8699static int 8700RC_SAE_immediate (const char *imm_start) 8701{ 8702 unsigned int match_found, j; 8703 const char *pstr = imm_start; 8704 expressionS *exp; 8705 8706 if (*pstr != '{') 8707 return 0; 8708 8709 pstr++; 8710 match_found = 0; 8711 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++) 8712 { 8713 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len)) 8714 { 8715 if (!i.rounding) 8716 { 8717 rc_op.type = RC_NamesTable[j].type; 8718 rc_op.operand = this_operand; 8719 i.rounding = &rc_op; 8720 } 8721 else 8722 { 8723 as_bad (_("duplicated `%s'"), imm_start); 8724 return 0; 8725 } 8726 pstr += RC_NamesTable[j].len; 8727 match_found = 1; 8728 break; 8729 } 8730 } 8731 if (!match_found) 8732 return 0; 8733 8734 if (*pstr++ != '}') 8735 { 8736 as_bad (_("Missing '}': '%s'"), imm_start); 8737 return 0; 8738 } 8739 /* RC/SAE immediate string should contain nothing more. */; 8740 if (*pstr != 0) 8741 { 8742 as_bad (_("Junk after '}': '%s'"), imm_start); 8743 return 0; 8744 } 8745 8746 exp = &im_expressions[i.imm_operands++]; 8747 i.op[this_operand].imms = exp; 8748 8749 exp->X_op = O_constant; 8750 exp->X_add_number = 0; 8751 exp->X_add_symbol = (symbolS *) 0; 8752 exp->X_op_symbol = (symbolS *) 0; 8753 8754 i.types[this_operand].bitfield.imm8 = 1; 8755 return 1; 8756} 8757 8758/* Only string instructions can have a second memory operand, so 8759 reduce current_templates to just those if it contains any. */ 8760static int 8761maybe_adjust_templates (void) 8762{ 8763 const insn_template *t; 8764 8765 gas_assert (i.mem_operands == 1); 8766 8767 for (t = current_templates->start; t < current_templates->end; ++t) 8768 if (t->opcode_modifier.isstring) 8769 break; 8770 8771 if (t < current_templates->end) 8772 { 8773 static templates aux_templates; 8774 bfd_boolean recheck; 8775 8776 aux_templates.start = t; 8777 for (; t < current_templates->end; ++t) 8778 if (!t->opcode_modifier.isstring) 8779 break; 8780 aux_templates.end = t; 8781 8782 /* Determine whether to re-check the first memory operand. */ 8783 recheck = (aux_templates.start != current_templates->start 8784 || t != current_templates->end); 8785 8786 current_templates = &aux_templates; 8787 8788 if (recheck) 8789 { 8790 i.mem_operands = 0; 8791 if (i.memop1_string != NULL 8792 && i386_index_check (i.memop1_string) == 0) 8793 return 0; 8794 i.mem_operands = 1; 8795 } 8796 } 8797 8798 return 1; 8799} 8800 8801/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero 8802 on error. */ 8803 8804static int 8805i386_att_operand (char *operand_string) 8806{ 8807 const reg_entry *r; 8808 char *end_op; 8809 char *op_string = operand_string; 8810 8811 if (is_space_char (*op_string)) 8812 ++op_string; 8813 8814 /* We check for an absolute prefix (differentiating, 8815 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ 8816 if (*op_string == ABSOLUTE_PREFIX) 8817 { 8818 ++op_string; 8819 if (is_space_char (*op_string)) 8820 ++op_string; 8821 i.types[this_operand].bitfield.jumpabsolute = 1; 8822 } 8823 8824 /* Check if operand is a register. */ 8825 if ((r = parse_register (op_string, &end_op)) != NULL) 8826 { 8827 i386_operand_type temp; 8828 8829 /* Check for a segment override by searching for ':' after a 8830 segment register. */ 8831 op_string = end_op; 8832 if (is_space_char (*op_string)) 8833 ++op_string; 8834 if (*op_string == ':' 8835 && (r->reg_type.bitfield.sreg2 8836 || r->reg_type.bitfield.sreg3)) 8837 { 8838 switch (r->reg_num) 8839 { 8840 case 0: 8841 i.seg[i.mem_operands] = &es; 8842 break; 8843 case 1: 8844 i.seg[i.mem_operands] = &cs; 8845 break; 8846 case 2: 8847 i.seg[i.mem_operands] = &ss; 8848 break; 8849 case 3: 8850 i.seg[i.mem_operands] = &ds; 8851 break; 8852 case 4: 8853 i.seg[i.mem_operands] = &fs; 8854 break; 8855 case 5: 8856 i.seg[i.mem_operands] = &gs; 8857 break; 8858 } 8859 8860 /* Skip the ':' and whitespace. */ 8861 ++op_string; 8862 if (is_space_char (*op_string)) 8863 ++op_string; 8864 8865 if (!is_digit_char (*op_string) 8866 && !is_identifier_char (*op_string) 8867 && *op_string != '(' 8868 && *op_string != ABSOLUTE_PREFIX) 8869 { 8870 as_bad (_("bad memory operand `%s'"), op_string); 8871 return 0; 8872 } 8873 /* Handle case of %es:*foo. */ 8874 if (*op_string == ABSOLUTE_PREFIX) 8875 { 8876 ++op_string; 8877 if (is_space_char (*op_string)) 8878 ++op_string; 8879 i.types[this_operand].bitfield.jumpabsolute = 1; 8880 } 8881 goto do_memory_reference; 8882 } 8883 8884 /* Handle vector operations. */ 8885 if (*op_string == '{') 8886 { 8887 op_string = check_VecOperations (op_string, NULL); 8888 if (op_string == NULL) 8889 return 0; 8890 } 8891 8892 if (*op_string) 8893 { 8894 as_bad (_("junk `%s' after register"), op_string); 8895 return 0; 8896 } 8897 temp = r->reg_type; 8898 temp.bitfield.baseindex = 0; 8899 i.types[this_operand] = operand_type_or (i.types[this_operand], 8900 temp); 8901 i.types[this_operand].bitfield.unspecified = 0; 8902 i.op[this_operand].regs = r; 8903 i.reg_operands++; 8904 } 8905 else if (*op_string == REGISTER_PREFIX) 8906 { 8907 as_bad (_("bad register name `%s'"), op_string); 8908 return 0; 8909 } 8910 else if (*op_string == IMMEDIATE_PREFIX) 8911 { 8912 ++op_string; 8913 if (i.types[this_operand].bitfield.jumpabsolute) 8914 { 8915 as_bad (_("immediate operand illegal with absolute jump")); 8916 return 0; 8917 } 8918 if (!i386_immediate (op_string)) 8919 return 0; 8920 } 8921 else if (RC_SAE_immediate (operand_string)) 8922 { 8923 /* If it is a RC or SAE immediate, do nothing. */ 8924 ; 8925 } 8926 else if (is_digit_char (*op_string) 8927 || is_identifier_char (*op_string) 8928 || *op_string == '"' 8929 || *op_string == '(') 8930 { 8931 /* This is a memory reference of some sort. */ 8932 char *base_string; 8933 8934 /* Start and end of displacement string expression (if found). */ 8935 char *displacement_string_start; 8936 char *displacement_string_end; 8937 char *vop_start; 8938 8939 do_memory_reference: 8940 if (i.mem_operands == 1 && !maybe_adjust_templates ()) 8941 return 0; 8942 if ((i.mem_operands == 1 8943 && !current_templates->start->opcode_modifier.isstring) 8944 || i.mem_operands == 2) 8945 { 8946 as_bad (_("too many memory references for `%s'"), 8947 current_templates->start->name); 8948 return 0; 8949 } 8950 8951 /* Check for base index form. We detect the base index form by 8952 looking for an ')' at the end of the operand, searching 8953 for the '(' matching it, and finding a REGISTER_PREFIX or ',' 8954 after the '('. */ 8955 base_string = op_string + strlen (op_string); 8956 8957 /* Handle vector operations. */ 8958 vop_start = strchr (op_string, '{'); 8959 if (vop_start && vop_start < base_string) 8960 { 8961 if (check_VecOperations (vop_start, base_string) == NULL) 8962 return 0; 8963 base_string = vop_start; 8964 } 8965 8966 --base_string; 8967 if (is_space_char (*base_string)) 8968 --base_string; 8969 8970 /* If we only have a displacement, set-up for it to be parsed later. */ 8971 displacement_string_start = op_string; 8972 displacement_string_end = base_string + 1; 8973 8974 if (*base_string == ')') 8975 { 8976 char *temp_string; 8977 unsigned int parens_balanced = 1; 8978 /* We've already checked that the number of left & right ()'s are 8979 equal, so this loop will not be infinite. */ 8980 do 8981 { 8982 base_string--; 8983 if (*base_string == ')') 8984 parens_balanced++; 8985 if (*base_string == '(') 8986 parens_balanced--; 8987 } 8988 while (parens_balanced); 8989 8990 temp_string = base_string; 8991 8992 /* Skip past '(' and whitespace. */ 8993 ++base_string; 8994 if (is_space_char (*base_string)) 8995 ++base_string; 8996 8997 if (*base_string == ',' 8998 || ((i.base_reg = parse_register (base_string, &end_op)) 8999 != NULL)) 9000 { 9001 displacement_string_end = temp_string; 9002 9003 i.types[this_operand].bitfield.baseindex = 1; 9004 9005 if (i.base_reg) 9006 { 9007 base_string = end_op; 9008 if (is_space_char (*base_string)) 9009 ++base_string; 9010 } 9011 9012 /* There may be an index reg or scale factor here. */ 9013 if (*base_string == ',') 9014 { 9015 ++base_string; 9016 if (is_space_char (*base_string)) 9017 ++base_string; 9018 9019 if ((i.index_reg = parse_register (base_string, &end_op)) 9020 != NULL) 9021 { 9022 base_string = end_op; 9023 if (is_space_char (*base_string)) 9024 ++base_string; 9025 if (*base_string == ',') 9026 { 9027 ++base_string; 9028 if (is_space_char (*base_string)) 9029 ++base_string; 9030 } 9031 else if (*base_string != ')') 9032 { 9033 as_bad (_("expecting `,' or `)' " 9034 "after index register in `%s'"), 9035 operand_string); 9036 return 0; 9037 } 9038 } 9039 else if (*base_string == REGISTER_PREFIX) 9040 { 9041 end_op = strchr (base_string, ','); 9042 if (end_op) 9043 *end_op = '\0'; 9044 as_bad (_("bad register name `%s'"), base_string); 9045 return 0; 9046 } 9047 9048 /* Check for scale factor. */ 9049 if (*base_string != ')') 9050 { 9051 char *end_scale = i386_scale (base_string); 9052 9053 if (!end_scale) 9054 return 0; 9055 9056 base_string = end_scale; 9057 if (is_space_char (*base_string)) 9058 ++base_string; 9059 if (*base_string != ')') 9060 { 9061 as_bad (_("expecting `)' " 9062 "after scale factor in `%s'"), 9063 operand_string); 9064 return 0; 9065 } 9066 } 9067 else if (!i.index_reg) 9068 { 9069 as_bad (_("expecting index register or scale factor " 9070 "after `,'; got '%c'"), 9071 *base_string); 9072 return 0; 9073 } 9074 } 9075 else if (*base_string != ')') 9076 { 9077 as_bad (_("expecting `,' or `)' " 9078 "after base register in `%s'"), 9079 operand_string); 9080 return 0; 9081 } 9082 } 9083 else if (*base_string == REGISTER_PREFIX) 9084 { 9085 end_op = strchr (base_string, ','); 9086 if (end_op) 9087 *end_op = '\0'; 9088 as_bad (_("bad register name `%s'"), base_string); 9089 return 0; 9090 } 9091 } 9092 9093 /* If there's an expression beginning the operand, parse it, 9094 assuming displacement_string_start and 9095 displacement_string_end are meaningful. */ 9096 if (displacement_string_start != displacement_string_end) 9097 { 9098 if (!i386_displacement (displacement_string_start, 9099 displacement_string_end)) 9100 return 0; 9101 } 9102 9103 /* Special case for (%dx) while doing input/output op. */ 9104 if (i.base_reg 9105 && operand_type_equal (&i.base_reg->reg_type, 9106 ®16_inoutportreg) 9107 && i.index_reg == 0 9108 && i.log2_scale_factor == 0 9109 && i.seg[i.mem_operands] == 0 9110 && !operand_type_check (i.types[this_operand], disp)) 9111 { 9112 i.types[this_operand] = inoutportreg; 9113 return 1; 9114 } 9115 9116 if (i386_index_check (operand_string) == 0) 9117 return 0; 9118 i.types[this_operand].bitfield.mem = 1; 9119 if (i.mem_operands == 0) 9120 i.memop1_string = xstrdup (operand_string); 9121 i.mem_operands++; 9122 } 9123 else 9124 { 9125 /* It's not a memory operand; argh! */ 9126 as_bad (_("invalid char %s beginning operand %d `%s'"), 9127 output_invalid (*op_string), 9128 this_operand + 1, 9129 op_string); 9130 return 0; 9131 } 9132 return 1; /* Normal return. */ 9133} 9134 9135/* Calculate the maximum variable size (i.e., excluding fr_fix) 9136 that an rs_machine_dependent frag may reach. */ 9137 9138unsigned int 9139i386_frag_max_var (fragS *frag) 9140{ 9141 /* The only relaxable frags are for jumps. 9142 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */ 9143 gas_assert (frag->fr_type == rs_machine_dependent); 9144 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5; 9145} 9146 9147#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 9148static int 9149elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var) 9150{ 9151 /* STT_GNU_IFUNC symbol must go through PLT. */ 9152 if ((symbol_get_bfdsym (fr_symbol)->flags 9153 & BSF_GNU_INDIRECT_FUNCTION) != 0) 9154 return 0; 9155 9156 if (!S_IS_EXTERNAL (fr_symbol)) 9157 /* Symbol may be weak or local. */ 9158 return !S_IS_WEAK (fr_symbol); 9159 9160 /* Global symbols with non-default visibility can't be preempted. */ 9161 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT) 9162 return 1; 9163 9164 if (fr_var != NO_RELOC) 9165 switch ((enum bfd_reloc_code_real) fr_var) 9166 { 9167 case BFD_RELOC_386_PLT32: 9168 case BFD_RELOC_X86_64_PLT32: 9169 /* Symbol with PLT relocatin may be preempted. */ 9170 return 0; 9171 default: 9172 abort (); 9173 } 9174 9175 /* Global symbols with default visibility in a shared library may be 9176 preempted by another definition. */ 9177 return !shared; 9178} 9179#endif 9180 9181/* md_estimate_size_before_relax() 9182 9183 Called just before relax() for rs_machine_dependent frags. The x86 9184 assembler uses these frags to handle variable size jump 9185 instructions. 9186 9187 Any symbol that is now undefined will not become defined. 9188 Return the correct fr_subtype in the frag. 9189 Return the initial "guess for variable size of frag" to caller. 9190 The guess is actually the growth beyond the fixed part. Whatever 9191 we do to grow the fixed or variable part contributes to our 9192 returned value. */ 9193 9194int 9195md_estimate_size_before_relax (fragS *fragP, segT segment) 9196{ 9197 /* We've already got fragP->fr_subtype right; all we have to do is 9198 check for un-relaxable symbols. On an ELF system, we can't relax 9199 an externally visible symbol, because it may be overridden by a 9200 shared library. */ 9201 if (S_GET_SEGMENT (fragP->fr_symbol) != segment 9202#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 9203 || (IS_ELF 9204 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol, 9205 fragP->fr_var)) 9206#endif 9207#if defined (OBJ_COFF) && defined (TE_PE) 9208 || (OUTPUT_FLAVOR == bfd_target_coff_flavour 9209 && S_IS_WEAK (fragP->fr_symbol)) 9210#endif 9211 ) 9212 { 9213 /* Symbol is undefined in this segment, or we need to keep a 9214 reloc so that weak symbols can be overridden. */ 9215 int size = (fragP->fr_subtype & CODE16) ? 2 : 4; 9216 enum bfd_reloc_code_real reloc_type; 9217 unsigned char *opcode; 9218 int old_fr_fix; 9219 9220 if (fragP->fr_var != NO_RELOC) 9221 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var; 9222 else if (size == 2) 9223 reloc_type = BFD_RELOC_16_PCREL; 9224 else 9225 reloc_type = BFD_RELOC_32_PCREL; 9226 9227 old_fr_fix = fragP->fr_fix; 9228 opcode = (unsigned char *) fragP->fr_opcode; 9229 9230 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) 9231 { 9232 case UNCOND_JUMP: 9233 /* Make jmp (0xeb) a (d)word displacement jump. */ 9234 opcode[0] = 0xe9; 9235 fragP->fr_fix += size; 9236 fix_new (fragP, old_fr_fix, size, 9237 fragP->fr_symbol, 9238 fragP->fr_offset, 1, 9239 reloc_type); 9240 break; 9241 9242 case COND_JUMP86: 9243 if (size == 2 9244 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) 9245 { 9246 /* Negate the condition, and branch past an 9247 unconditional jump. */ 9248 opcode[0] ^= 1; 9249 opcode[1] = 3; 9250 /* Insert an unconditional jump. */ 9251 opcode[2] = 0xe9; 9252 /* We added two extra opcode bytes, and have a two byte 9253 offset. */ 9254 fragP->fr_fix += 2 + 2; 9255 fix_new (fragP, old_fr_fix + 2, 2, 9256 fragP->fr_symbol, 9257 fragP->fr_offset, 1, 9258 reloc_type); 9259 break; 9260 } 9261 /* Fall through. */ 9262 9263 case COND_JUMP: 9264 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) 9265 { 9266 fixS *fixP; 9267 9268 fragP->fr_fix += 1; 9269 fixP = fix_new (fragP, old_fr_fix, 1, 9270 fragP->fr_symbol, 9271 fragP->fr_offset, 1, 9272 BFD_RELOC_8_PCREL); 9273 fixP->fx_signed = 1; 9274 break; 9275 } 9276 9277 /* This changes the byte-displacement jump 0x7N 9278 to the (d)word-displacement jump 0x0f,0x8N. */ 9279 opcode[1] = opcode[0] + 0x10; 9280 opcode[0] = TWO_BYTE_OPCODE_ESCAPE; 9281 /* We've added an opcode byte. */ 9282 fragP->fr_fix += 1 + size; 9283 fix_new (fragP, old_fr_fix + 1, size, 9284 fragP->fr_symbol, 9285 fragP->fr_offset, 1, 9286 reloc_type); 9287 break; 9288 9289 default: 9290 BAD_CASE (fragP->fr_subtype); 9291 break; 9292 } 9293 frag_wane (fragP); 9294 return fragP->fr_fix - old_fr_fix; 9295 } 9296 9297 /* Guess size depending on current relax state. Initially the relax 9298 state will correspond to a short jump and we return 1, because 9299 the variable part of the frag (the branch offset) is one byte 9300 long. However, we can relax a section more than once and in that 9301 case we must either set fr_subtype back to the unrelaxed state, 9302 or return the value for the appropriate branch. */ 9303 return md_relax_table[fragP->fr_subtype].rlx_length; 9304} 9305 9306/* Called after relax() is finished. 9307 9308 In: Address of frag. 9309 fr_type == rs_machine_dependent. 9310 fr_subtype is what the address relaxed to. 9311 9312 Out: Any fixSs and constants are set up. 9313 Caller will turn frag into a ".space 0". */ 9314 9315void 9316md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED, 9317 fragS *fragP) 9318{ 9319 unsigned char *opcode; 9320 unsigned char *where_to_put_displacement = NULL; 9321 offsetT target_address; 9322 offsetT opcode_address; 9323 unsigned int extension = 0; 9324 offsetT displacement_from_opcode_start; 9325 9326 opcode = (unsigned char *) fragP->fr_opcode; 9327 9328 /* Address we want to reach in file space. */ 9329 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; 9330 9331 /* Address opcode resides at in file space. */ 9332 opcode_address = fragP->fr_address + fragP->fr_fix; 9333 9334 /* Displacement from opcode start to fill into instruction. */ 9335 displacement_from_opcode_start = target_address - opcode_address; 9336 9337 if ((fragP->fr_subtype & BIG) == 0) 9338 { 9339 /* Don't have to change opcode. */ 9340 extension = 1; /* 1 opcode + 1 displacement */ 9341 where_to_put_displacement = &opcode[1]; 9342 } 9343 else 9344 { 9345 if (no_cond_jump_promotion 9346 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) 9347 as_warn_where (fragP->fr_file, fragP->fr_line, 9348 _("long jump required")); 9349 9350 switch (fragP->fr_subtype) 9351 { 9352 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): 9353 extension = 4; /* 1 opcode + 4 displacement */ 9354 opcode[0] = 0xe9; 9355 where_to_put_displacement = &opcode[1]; 9356 break; 9357 9358 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): 9359 extension = 2; /* 1 opcode + 2 displacement */ 9360 opcode[0] = 0xe9; 9361 where_to_put_displacement = &opcode[1]; 9362 break; 9363 9364 case ENCODE_RELAX_STATE (COND_JUMP, BIG): 9365 case ENCODE_RELAX_STATE (COND_JUMP86, BIG): 9366 extension = 5; /* 2 opcode + 4 displacement */ 9367 opcode[1] = opcode[0] + 0x10; 9368 opcode[0] = TWO_BYTE_OPCODE_ESCAPE; 9369 where_to_put_displacement = &opcode[2]; 9370 break; 9371 9372 case ENCODE_RELAX_STATE (COND_JUMP, BIG16): 9373 extension = 3; /* 2 opcode + 2 displacement */ 9374 opcode[1] = opcode[0] + 0x10; 9375 opcode[0] = TWO_BYTE_OPCODE_ESCAPE; 9376 where_to_put_displacement = &opcode[2]; 9377 break; 9378 9379 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): 9380 extension = 4; 9381 opcode[0] ^= 1; 9382 opcode[1] = 3; 9383 opcode[2] = 0xe9; 9384 where_to_put_displacement = &opcode[3]; 9385 break; 9386 9387 default: 9388 BAD_CASE (fragP->fr_subtype); 9389 break; 9390 } 9391 } 9392 9393 /* If size if less then four we are sure that the operand fits, 9394 but if it's 4, then it could be that the displacement is larger 9395 then -/+ 2GB. */ 9396 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4 9397 && object_64bit 9398 && ((addressT) (displacement_from_opcode_start - extension 9399 + ((addressT) 1 << 31)) 9400 > (((addressT) 2 << 31) - 1))) 9401 { 9402 as_bad_where (fragP->fr_file, fragP->fr_line, 9403 _("jump target out of range")); 9404 /* Make us emit 0. */ 9405 displacement_from_opcode_start = extension; 9406 } 9407 /* Now put displacement after opcode. */ 9408 md_number_to_chars ((char *) where_to_put_displacement, 9409 (valueT) (displacement_from_opcode_start - extension), 9410 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); 9411 fragP->fr_fix += extension; 9412} 9413 9414/* Apply a fixup (fixP) to segment data, once it has been determined 9415 by our caller that we have all the info we need to fix it up. 9416 9417 Parameter valP is the pointer to the value of the bits. 9418 9419 On the 386, immediates, displacements, and data pointers are all in 9420 the same (little-endian) format, so we don't need to care about which 9421 we are handling. */ 9422 9423void 9424md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) 9425{ 9426 char *p = fixP->fx_where + fixP->fx_frag->fr_literal; 9427 valueT value = *valP; 9428 9429#if !defined (TE_Mach) 9430 if (fixP->fx_pcrel) 9431 { 9432 switch (fixP->fx_r_type) 9433 { 9434 default: 9435 break; 9436 9437 case BFD_RELOC_64: 9438 fixP->fx_r_type = BFD_RELOC_64_PCREL; 9439 break; 9440 case BFD_RELOC_32: 9441 case BFD_RELOC_X86_64_32S: 9442 fixP->fx_r_type = BFD_RELOC_32_PCREL; 9443 break; 9444 case BFD_RELOC_16: 9445 fixP->fx_r_type = BFD_RELOC_16_PCREL; 9446 break; 9447 case BFD_RELOC_8: 9448 fixP->fx_r_type = BFD_RELOC_8_PCREL; 9449 break; 9450 } 9451 } 9452 9453 if (fixP->fx_addsy != NULL 9454 && (fixP->fx_r_type == BFD_RELOC_32_PCREL 9455 || fixP->fx_r_type == BFD_RELOC_64_PCREL 9456 || fixP->fx_r_type == BFD_RELOC_16_PCREL 9457 || fixP->fx_r_type == BFD_RELOC_8_PCREL) 9458 && !use_rela_relocations) 9459 { 9460 /* This is a hack. There should be a better way to handle this. 9461 This covers for the fact that bfd_install_relocation will 9462 subtract the current location (for partial_inplace, PC relative 9463 relocations); see more below. */ 9464#ifndef OBJ_AOUT 9465 if (IS_ELF 9466#ifdef TE_PE 9467 || OUTPUT_FLAVOR == bfd_target_coff_flavour 9468#endif 9469 ) 9470 value += fixP->fx_where + fixP->fx_frag->fr_address; 9471#endif 9472#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 9473 if (IS_ELF) 9474 { 9475 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); 9476 9477 if ((sym_seg == seg 9478 || (symbol_section_p (fixP->fx_addsy) 9479 && sym_seg != absolute_section)) 9480 && !generic_force_reloc (fixP)) 9481 { 9482 /* Yes, we add the values in twice. This is because 9483 bfd_install_relocation subtracts them out again. I think 9484 bfd_install_relocation is broken, but I don't dare change 9485 it. FIXME. */ 9486 value += fixP->fx_where + fixP->fx_frag->fr_address; 9487 } 9488 } 9489#endif 9490#if defined (OBJ_COFF) && defined (TE_PE) 9491 /* For some reason, the PE format does not store a 9492 section address offset for a PC relative symbol. */ 9493 if (S_GET_SEGMENT (fixP->fx_addsy) != seg 9494 || S_IS_WEAK (fixP->fx_addsy)) 9495 value += md_pcrel_from (fixP); 9496#endif 9497 } 9498#if defined (OBJ_COFF) && defined (TE_PE) 9499 if (fixP->fx_addsy != NULL 9500 && S_IS_WEAK (fixP->fx_addsy) 9501 /* PR 16858: Do not modify weak function references. */ 9502 && ! fixP->fx_pcrel) 9503 { 9504#if !defined (TE_PEP) 9505 /* For x86 PE weak function symbols are neither PC-relative 9506 nor do they set S_IS_FUNCTION. So the only reliable way 9507 to detect them is to check the flags of their containing 9508 section. */ 9509 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL 9510 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE) 9511 ; 9512 else 9513#endif 9514 value -= S_GET_VALUE (fixP->fx_addsy); 9515 } 9516#endif 9517 9518 /* Fix a few things - the dynamic linker expects certain values here, 9519 and we must not disappoint it. */ 9520#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 9521 if (IS_ELF && fixP->fx_addsy) 9522 switch (fixP->fx_r_type) 9523 { 9524 case BFD_RELOC_386_PLT32: 9525 case BFD_RELOC_X86_64_PLT32: 9526 /* Make the jump instruction point to the address of the operand. At 9527 runtime we merely add the offset to the actual PLT entry. */ 9528 value = -4; 9529 break; 9530 9531 case BFD_RELOC_386_TLS_GD: 9532 case BFD_RELOC_386_TLS_LDM: 9533 case BFD_RELOC_386_TLS_IE_32: 9534 case BFD_RELOC_386_TLS_IE: 9535 case BFD_RELOC_386_TLS_GOTIE: 9536 case BFD_RELOC_386_TLS_GOTDESC: 9537 case BFD_RELOC_X86_64_TLSGD: 9538 case BFD_RELOC_X86_64_TLSLD: 9539 case BFD_RELOC_X86_64_GOTTPOFF: 9540 case BFD_RELOC_X86_64_GOTPC32_TLSDESC: 9541 value = 0; /* Fully resolved at runtime. No addend. */ 9542 /* Fallthrough */ 9543 case BFD_RELOC_386_TLS_LE: 9544 case BFD_RELOC_386_TLS_LDO_32: 9545 case BFD_RELOC_386_TLS_LE_32: 9546 case BFD_RELOC_X86_64_DTPOFF32: 9547 case BFD_RELOC_X86_64_DTPOFF64: 9548 case BFD_RELOC_X86_64_TPOFF32: 9549 case BFD_RELOC_X86_64_TPOFF64: 9550 S_SET_THREAD_LOCAL (fixP->fx_addsy); 9551 break; 9552 9553 case BFD_RELOC_386_TLS_DESC_CALL: 9554 case BFD_RELOC_X86_64_TLSDESC_CALL: 9555 value = 0; /* Fully resolved at runtime. No addend. */ 9556 S_SET_THREAD_LOCAL (fixP->fx_addsy); 9557 fixP->fx_done = 0; 9558 return; 9559 9560 case BFD_RELOC_VTABLE_INHERIT: 9561 case BFD_RELOC_VTABLE_ENTRY: 9562 fixP->fx_done = 0; 9563 return; 9564 9565 default: 9566 break; 9567 } 9568#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ 9569 *valP = value; 9570#endif /* !defined (TE_Mach) */ 9571 9572 /* Are we finished with this relocation now? */ 9573 if (fixP->fx_addsy == NULL) 9574 fixP->fx_done = 1; 9575#if defined (OBJ_COFF) && defined (TE_PE) 9576 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy)) 9577 { 9578 fixP->fx_done = 0; 9579 /* Remember value for tc_gen_reloc. */ 9580 fixP->fx_addnumber = value; 9581 /* Clear out the frag for now. */ 9582 value = 0; 9583 } 9584#endif 9585 else if (use_rela_relocations) 9586 { 9587 fixP->fx_no_overflow = 1; 9588 /* Remember value for tc_gen_reloc. */ 9589 fixP->fx_addnumber = value; 9590 value = 0; 9591 } 9592 9593 md_number_to_chars (p, value, fixP->fx_size); 9594} 9595 9596const char * 9597md_atof (int type, char *litP, int *sizeP) 9598{ 9599 /* This outputs the LITTLENUMs in REVERSE order; 9600 in accord with the bigendian 386. */ 9601 return ieee_md_atof (type, litP, sizeP, FALSE); 9602} 9603 9604static char output_invalid_buf[sizeof (unsigned char) * 2 + 6]; 9605 9606static char * 9607output_invalid (int c) 9608{ 9609 if (ISPRINT (c)) 9610 snprintf (output_invalid_buf, sizeof (output_invalid_buf), 9611 "'%c'", c); 9612 else 9613 snprintf (output_invalid_buf, sizeof (output_invalid_buf), 9614 "(0x%x)", (unsigned char) c); 9615 return output_invalid_buf; 9616} 9617 9618/* REG_STRING starts *before* REGISTER_PREFIX. */ 9619 9620static const reg_entry * 9621parse_real_register (char *reg_string, char **end_op) 9622{ 9623 char *s = reg_string; 9624 char *p; 9625 char reg_name_given[MAX_REG_NAME_SIZE + 1]; 9626 const reg_entry *r; 9627 9628 /* Skip possible REGISTER_PREFIX and possible whitespace. */ 9629 if (*s == REGISTER_PREFIX) 9630 ++s; 9631 9632 if (is_space_char (*s)) 9633 ++s; 9634 9635 p = reg_name_given; 9636 while ((*p++ = register_chars[(unsigned char) *s]) != '\0') 9637 { 9638 if (p >= reg_name_given + MAX_REG_NAME_SIZE) 9639 return (const reg_entry *) NULL; 9640 s++; 9641 } 9642 9643 /* For naked regs, make sure that we are not dealing with an identifier. 9644 This prevents confusing an identifier like `eax_var' with register 9645 `eax'. */ 9646 if (allow_naked_reg && identifier_chars[(unsigned char) *s]) 9647 return (const reg_entry *) NULL; 9648 9649 *end_op = s; 9650 9651 r = (const reg_entry *) hash_find (reg_hash, reg_name_given); 9652 9653 /* Handle floating point regs, allowing spaces in the (i) part. */ 9654 if (r == i386_regtab /* %st is first entry of table */) 9655 { 9656 if (is_space_char (*s)) 9657 ++s; 9658 if (*s == '(') 9659 { 9660 ++s; 9661 if (is_space_char (*s)) 9662 ++s; 9663 if (*s >= '0' && *s <= '7') 9664 { 9665 int fpr = *s - '0'; 9666 ++s; 9667 if (is_space_char (*s)) 9668 ++s; 9669 if (*s == ')') 9670 { 9671 *end_op = s + 1; 9672 r = (const reg_entry *) hash_find (reg_hash, "st(0)"); 9673 know (r); 9674 return r + fpr; 9675 } 9676 } 9677 /* We have "%st(" then garbage. */ 9678 return (const reg_entry *) NULL; 9679 } 9680 } 9681 9682 if (r == NULL || allow_pseudo_reg) 9683 return r; 9684 9685 if (operand_type_all_zero (&r->reg_type)) 9686 return (const reg_entry *) NULL; 9687 9688 if ((r->reg_type.bitfield.reg32 9689 || r->reg_type.bitfield.sreg3 9690 || r->reg_type.bitfield.control 9691 || r->reg_type.bitfield.debug 9692 || r->reg_type.bitfield.test) 9693 && !cpu_arch_flags.bitfield.cpui386) 9694 return (const reg_entry *) NULL; 9695 9696 if (r->reg_type.bitfield.floatreg 9697 && !cpu_arch_flags.bitfield.cpu8087 9698 && !cpu_arch_flags.bitfield.cpu287 9699 && !cpu_arch_flags.bitfield.cpu387) 9700 return (const reg_entry *) NULL; 9701 9702 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx) 9703 return (const reg_entry *) NULL; 9704 9705 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpuregxmm) 9706 return (const reg_entry *) NULL; 9707 9708 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuregymm) 9709 return (const reg_entry *) NULL; 9710 9711 if (r->reg_type.bitfield.regzmm && !cpu_arch_flags.bitfield.cpuregzmm) 9712 return (const reg_entry *) NULL; 9713 9714 if (r->reg_type.bitfield.regmask 9715 && !cpu_arch_flags.bitfield.cpuregmask) 9716 return (const reg_entry *) NULL; 9717 9718 /* Don't allow fake index register unless allow_index_reg isn't 0. */ 9719 if (!allow_index_reg 9720 && (r->reg_num == RegEiz || r->reg_num == RegRiz)) 9721 return (const reg_entry *) NULL; 9722 9723 /* Upper 16 vector register is only available with VREX in 64bit 9724 mode. */ 9725 if ((r->reg_flags & RegVRex)) 9726 { 9727 if (!cpu_arch_flags.bitfield.cpuvrex 9728 || flag_code != CODE_64BIT) 9729 return (const reg_entry *) NULL; 9730 9731 i.need_vrex = 1; 9732 } 9733 9734 if (((r->reg_flags & (RegRex64 | RegRex)) 9735 || r->reg_type.bitfield.reg64) 9736 && (!cpu_arch_flags.bitfield.cpulm 9737 || !operand_type_equal (&r->reg_type, &control)) 9738 && flag_code != CODE_64BIT) 9739 return (const reg_entry *) NULL; 9740 9741 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax) 9742 return (const reg_entry *) NULL; 9743 9744 return r; 9745} 9746 9747/* REG_STRING starts *before* REGISTER_PREFIX. */ 9748 9749static const reg_entry * 9750parse_register (char *reg_string, char **end_op) 9751{ 9752 const reg_entry *r; 9753 9754 if (*reg_string == REGISTER_PREFIX || allow_naked_reg) 9755 r = parse_real_register (reg_string, end_op); 9756 else 9757 r = NULL; 9758 if (!r) 9759 { 9760 char *save = input_line_pointer; 9761 char c; 9762 symbolS *symbolP; 9763 9764 input_line_pointer = reg_string; 9765 c = get_symbol_name (®_string); 9766 symbolP = symbol_find (reg_string); 9767 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) 9768 { 9769 const expressionS *e = symbol_get_value_expression (symbolP); 9770 9771 know (e->X_op == O_register); 9772 know (e->X_add_number >= 0 9773 && (valueT) e->X_add_number < i386_regtab_size); 9774 r = i386_regtab + e->X_add_number; 9775 if ((r->reg_flags & RegVRex)) 9776 i.need_vrex = 1; 9777 *end_op = input_line_pointer; 9778 } 9779 *input_line_pointer = c; 9780 input_line_pointer = save; 9781 } 9782 return r; 9783} 9784 9785int 9786i386_parse_name (char *name, expressionS *e, char *nextcharP) 9787{ 9788 const reg_entry *r; 9789 char *end = input_line_pointer; 9790 9791 *end = *nextcharP; 9792 r = parse_register (name, &input_line_pointer); 9793 if (r && end <= input_line_pointer) 9794 { 9795 *nextcharP = *input_line_pointer; 9796 *input_line_pointer = 0; 9797 e->X_op = O_register; 9798 e->X_add_number = r - i386_regtab; 9799 return 1; 9800 } 9801 input_line_pointer = end; 9802 *end = 0; 9803 return intel_syntax ? i386_intel_parse_name (name, e) : 0; 9804} 9805 9806void 9807md_operand (expressionS *e) 9808{ 9809 char *end; 9810 const reg_entry *r; 9811 9812 switch (*input_line_pointer) 9813 { 9814 case REGISTER_PREFIX: 9815 r = parse_real_register (input_line_pointer, &end); 9816 if (r) 9817 { 9818 e->X_op = O_register; 9819 e->X_add_number = r - i386_regtab; 9820 input_line_pointer = end; 9821 } 9822 break; 9823 9824 case '[': 9825 gas_assert (intel_syntax); 9826 end = input_line_pointer++; 9827 expression (e); 9828 if (*input_line_pointer == ']') 9829 { 9830 ++input_line_pointer; 9831 e->X_op_symbol = make_expr_symbol (e); 9832 e->X_add_symbol = NULL; 9833 e->X_add_number = 0; 9834 e->X_op = O_index; 9835 } 9836 else 9837 { 9838 e->X_op = O_absent; 9839 input_line_pointer = end; 9840 } 9841 break; 9842 } 9843} 9844 9845 9846#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 9847const char *md_shortopts = "kVQ:sqn"; 9848#else 9849const char *md_shortopts = "qn"; 9850#endif 9851 9852#define OPTION_32 (OPTION_MD_BASE + 0) 9853#define OPTION_64 (OPTION_MD_BASE + 1) 9854#define OPTION_DIVIDE (OPTION_MD_BASE + 2) 9855#define OPTION_MARCH (OPTION_MD_BASE + 3) 9856#define OPTION_MTUNE (OPTION_MD_BASE + 4) 9857#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5) 9858#define OPTION_MSYNTAX (OPTION_MD_BASE + 6) 9859#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7) 9860#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8) 9861#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9) 9862#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10) 9863#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11) 9864#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12) 9865#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13) 9866#define OPTION_X32 (OPTION_MD_BASE + 14) 9867#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15) 9868#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16) 9869#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17) 9870#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18) 9871#define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19) 9872#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20) 9873#define OPTION_MSHARED (OPTION_MD_BASE + 21) 9874#define OPTION_MAMD64 (OPTION_MD_BASE + 22) 9875#define OPTION_MINTEL64 (OPTION_MD_BASE + 23) 9876#define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24) 9877#define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25) 9878 9879struct option md_longopts[] = 9880{ 9881 {"32", no_argument, NULL, OPTION_32}, 9882#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ 9883 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) 9884 {"64", no_argument, NULL, OPTION_64}, 9885#endif 9886#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 9887 {"x32", no_argument, NULL, OPTION_X32}, 9888 {"mshared", no_argument, NULL, OPTION_MSHARED}, 9889#endif 9890 {"divide", no_argument, NULL, OPTION_DIVIDE}, 9891 {"march", required_argument, NULL, OPTION_MARCH}, 9892 {"mtune", required_argument, NULL, OPTION_MTUNE}, 9893 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC}, 9894 {"msyntax", required_argument, NULL, OPTION_MSYNTAX}, 9895 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG}, 9896 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG}, 9897 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC}, 9898 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX}, 9899 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK}, 9900 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK}, 9901 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR}, 9902 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX}, 9903 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG}, 9904 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG}, 9905# if defined (TE_PE) || defined (TE_PEP) 9906 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ}, 9907#endif 9908 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX}, 9909 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD}, 9910 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS}, 9911 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG}, 9912 {"mamd64", no_argument, NULL, OPTION_MAMD64}, 9913 {"mintel64", no_argument, NULL, OPTION_MINTEL64}, 9914 {NULL, no_argument, NULL, 0} 9915}; 9916size_t md_longopts_size = sizeof (md_longopts); 9917 9918int 9919md_parse_option (int c, const char *arg) 9920{ 9921 unsigned int j; 9922 char *arch, *next, *saved; 9923 9924 switch (c) 9925 { 9926 case 'n': 9927 optimize_align_code = 0; 9928 break; 9929 9930 case 'q': 9931 quiet_warnings = 1; 9932 break; 9933 9934#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 9935 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section 9936 should be emitted or not. FIXME: Not implemented. */ 9937 case 'Q': 9938 break; 9939 9940 /* -V: SVR4 argument to print version ID. */ 9941 case 'V': 9942 print_version_id (); 9943 break; 9944 9945 /* -k: Ignore for FreeBSD compatibility. */ 9946 case 'k': 9947 break; 9948 9949 case 's': 9950 /* -s: On i386 Solaris, this tells the native assembler to use 9951 .stab instead of .stab.excl. We always use .stab anyhow. */ 9952 break; 9953 9954 case OPTION_MSHARED: 9955 shared = 1; 9956 break; 9957#endif 9958#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ 9959 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) 9960 case OPTION_64: 9961 { 9962 const char **list, **l; 9963 9964 list = bfd_target_list (); 9965 for (l = list; *l != NULL; l++) 9966 if (CONST_STRNEQ (*l, "elf64-x86-64") 9967 || strcmp (*l, "coff-x86-64") == 0 9968 || strcmp (*l, "pe-x86-64") == 0 9969 || strcmp (*l, "pei-x86-64") == 0 9970 || strcmp (*l, "mach-o-x86-64") == 0) 9971 { 9972 default_arch = "x86_64"; 9973 break; 9974 } 9975 if (*l == NULL) 9976 as_fatal (_("no compiled in support for x86_64")); 9977 free (list); 9978 } 9979 break; 9980#endif 9981 9982#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 9983 case OPTION_X32: 9984 if (IS_ELF) 9985 { 9986 const char **list, **l; 9987 9988 list = bfd_target_list (); 9989 for (l = list; *l != NULL; l++) 9990 if (CONST_STRNEQ (*l, "elf32-x86-64")) 9991 { 9992 default_arch = "x86_64:32"; 9993 break; 9994 } 9995 if (*l == NULL) 9996 as_fatal (_("no compiled in support for 32bit x86_64")); 9997 free (list); 9998 } 9999 else 10000 as_fatal (_("32bit x86_64 is only supported for ELF")); 10001 break; 10002#endif 10003 10004 case OPTION_32: 10005 default_arch = "i386"; 10006 break; 10007 10008 case OPTION_DIVIDE: 10009#ifdef SVR4_COMMENT_CHARS 10010 { 10011 char *n, *t; 10012 const char *s; 10013 10014 n = XNEWVEC (char, strlen (i386_comment_chars) + 1); 10015 t = n; 10016 for (s = i386_comment_chars; *s != '\0'; s++) 10017 if (*s != '/') 10018 *t++ = *s; 10019 *t = '\0'; 10020 i386_comment_chars = n; 10021 } 10022#endif 10023 break; 10024 10025 case OPTION_MARCH: 10026 saved = xstrdup (arg); 10027 arch = saved; 10028 /* Allow -march=+nosse. */ 10029 if (*arch == '+') 10030 arch++; 10031 do 10032 { 10033 if (*arch == '.') 10034 as_fatal (_("invalid -march= option: `%s'"), arg); 10035 next = strchr (arch, '+'); 10036 if (next) 10037 *next++ = '\0'; 10038 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) 10039 { 10040 if (strcmp (arch, cpu_arch [j].name) == 0) 10041 { 10042 /* Processor. */ 10043 if (! cpu_arch[j].flags.bitfield.cpui386) 10044 continue; 10045 10046 cpu_arch_name = cpu_arch[j].name; 10047 cpu_sub_arch_name = NULL; 10048 cpu_arch_flags = cpu_arch[j].flags; 10049 cpu_arch_isa = cpu_arch[j].type; 10050 cpu_arch_isa_flags = cpu_arch[j].flags; 10051 if (!cpu_arch_tune_set) 10052 { 10053 cpu_arch_tune = cpu_arch_isa; 10054 cpu_arch_tune_flags = cpu_arch_isa_flags; 10055 } 10056 break; 10057 } 10058 else if (*cpu_arch [j].name == '.' 10059 && strcmp (arch, cpu_arch [j].name + 1) == 0) 10060 { 10061 /* ISA entension. */ 10062 i386_cpu_flags flags; 10063 10064 flags = cpu_flags_or (cpu_arch_flags, 10065 cpu_arch[j].flags); 10066 10067 if (!cpu_flags_equal (&flags, &cpu_arch_flags)) 10068 { 10069 if (cpu_sub_arch_name) 10070 { 10071 char *name = cpu_sub_arch_name; 10072 cpu_sub_arch_name = concat (name, 10073 cpu_arch[j].name, 10074 (const char *) NULL); 10075 free (name); 10076 } 10077 else 10078 cpu_sub_arch_name = xstrdup (cpu_arch[j].name); 10079 cpu_arch_flags = flags; 10080 cpu_arch_isa_flags = flags; 10081 } 10082 break; 10083 } 10084 } 10085 10086 if (j >= ARRAY_SIZE (cpu_arch)) 10087 { 10088 /* Disable an ISA entension. */ 10089 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) 10090 if (strcmp (arch, cpu_noarch [j].name) == 0) 10091 { 10092 i386_cpu_flags flags; 10093 10094 flags = cpu_flags_and_not (cpu_arch_flags, 10095 cpu_noarch[j].flags); 10096 if (!cpu_flags_equal (&flags, &cpu_arch_flags)) 10097 { 10098 if (cpu_sub_arch_name) 10099 { 10100 char *name = cpu_sub_arch_name; 10101 cpu_sub_arch_name = concat (arch, 10102 (const char *) NULL); 10103 free (name); 10104 } 10105 else 10106 cpu_sub_arch_name = xstrdup (arch); 10107 cpu_arch_flags = flags; 10108 cpu_arch_isa_flags = flags; 10109 } 10110 break; 10111 } 10112 10113 if (j >= ARRAY_SIZE (cpu_noarch)) 10114 j = ARRAY_SIZE (cpu_arch); 10115 } 10116 10117 if (j >= ARRAY_SIZE (cpu_arch)) 10118 as_fatal (_("invalid -march= option: `%s'"), arg); 10119 10120 arch = next; 10121 } 10122 while (next != NULL); 10123 free (saved); 10124 break; 10125 10126 case OPTION_MTUNE: 10127 if (*arg == '.') 10128 as_fatal (_("invalid -mtune= option: `%s'"), arg); 10129 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) 10130 { 10131 if (strcmp (arg, cpu_arch [j].name) == 0) 10132 { 10133 cpu_arch_tune_set = 1; 10134 cpu_arch_tune = cpu_arch [j].type; 10135 cpu_arch_tune_flags = cpu_arch[j].flags; 10136 break; 10137 } 10138 } 10139 if (j >= ARRAY_SIZE (cpu_arch)) 10140 as_fatal (_("invalid -mtune= option: `%s'"), arg); 10141 break; 10142 10143 case OPTION_MMNEMONIC: 10144 if (strcasecmp (arg, "att") == 0) 10145 intel_mnemonic = 0; 10146 else if (strcasecmp (arg, "intel") == 0) 10147 intel_mnemonic = 1; 10148 else 10149 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg); 10150 break; 10151 10152 case OPTION_MSYNTAX: 10153 if (strcasecmp (arg, "att") == 0) 10154 intel_syntax = 0; 10155 else if (strcasecmp (arg, "intel") == 0) 10156 intel_syntax = 1; 10157 else 10158 as_fatal (_("invalid -msyntax= option: `%s'"), arg); 10159 break; 10160 10161 case OPTION_MINDEX_REG: 10162 allow_index_reg = 1; 10163 break; 10164 10165 case OPTION_MNAKED_REG: 10166 allow_naked_reg = 1; 10167 break; 10168 10169 case OPTION_MOLD_GCC: 10170 old_gcc = 1; 10171 break; 10172 10173 case OPTION_MSSE2AVX: 10174 sse2avx = 1; 10175 break; 10176 10177 case OPTION_MSSE_CHECK: 10178 if (strcasecmp (arg, "error") == 0) 10179 sse_check = check_error; 10180 else if (strcasecmp (arg, "warning") == 0) 10181 sse_check = check_warning; 10182 else if (strcasecmp (arg, "none") == 0) 10183 sse_check = check_none; 10184 else 10185 as_fatal (_("invalid -msse-check= option: `%s'"), arg); 10186 break; 10187 10188 case OPTION_MOPERAND_CHECK: 10189 if (strcasecmp (arg, "error") == 0) 10190 operand_check = check_error; 10191 else if (strcasecmp (arg, "warning") == 0) 10192 operand_check = check_warning; 10193 else if (strcasecmp (arg, "none") == 0) 10194 operand_check = check_none; 10195 else 10196 as_fatal (_("invalid -moperand-check= option: `%s'"), arg); 10197 break; 10198 10199 case OPTION_MAVXSCALAR: 10200 if (strcasecmp (arg, "128") == 0) 10201 avxscalar = vex128; 10202 else if (strcasecmp (arg, "256") == 0) 10203 avxscalar = vex256; 10204 else 10205 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg); 10206 break; 10207 10208 case OPTION_MADD_BND_PREFIX: 10209 add_bnd_prefix = 1; 10210 break; 10211 10212 case OPTION_MEVEXLIG: 10213 if (strcmp (arg, "128") == 0) 10214 evexlig = evexl128; 10215 else if (strcmp (arg, "256") == 0) 10216 evexlig = evexl256; 10217 else if (strcmp (arg, "512") == 0) 10218 evexlig = evexl512; 10219 else 10220 as_fatal (_("invalid -mevexlig= option: `%s'"), arg); 10221 break; 10222 10223 case OPTION_MEVEXRCIG: 10224 if (strcmp (arg, "rne") == 0) 10225 evexrcig = rne; 10226 else if (strcmp (arg, "rd") == 0) 10227 evexrcig = rd; 10228 else if (strcmp (arg, "ru") == 0) 10229 evexrcig = ru; 10230 else if (strcmp (arg, "rz") == 0) 10231 evexrcig = rz; 10232 else 10233 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg); 10234 break; 10235 10236 case OPTION_MEVEXWIG: 10237 if (strcmp (arg, "0") == 0) 10238 evexwig = evexw0; 10239 else if (strcmp (arg, "1") == 0) 10240 evexwig = evexw1; 10241 else 10242 as_fatal (_("invalid -mevexwig= option: `%s'"), arg); 10243 break; 10244 10245# if defined (TE_PE) || defined (TE_PEP) 10246 case OPTION_MBIG_OBJ: 10247 use_big_obj = 1; 10248 break; 10249#endif 10250 10251 case OPTION_MOMIT_LOCK_PREFIX: 10252 if (strcasecmp (arg, "yes") == 0) 10253 omit_lock_prefix = 1; 10254 else if (strcasecmp (arg, "no") == 0) 10255 omit_lock_prefix = 0; 10256 else 10257 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg); 10258 break; 10259 10260 case OPTION_MFENCE_AS_LOCK_ADD: 10261 if (strcasecmp (arg, "yes") == 0) 10262 avoid_fence = 1; 10263 else if (strcasecmp (arg, "no") == 0) 10264 avoid_fence = 0; 10265 else 10266 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg); 10267 break; 10268 10269 case OPTION_MRELAX_RELOCATIONS: 10270 if (strcasecmp (arg, "yes") == 0) 10271 generate_relax_relocations = 1; 10272 else if (strcasecmp (arg, "no") == 0) 10273 generate_relax_relocations = 0; 10274 else 10275 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg); 10276 break; 10277 10278 case OPTION_MAMD64: 10279 intel64 = 0; 10280 break; 10281 10282 case OPTION_MINTEL64: 10283 intel64 = 1; 10284 break; 10285 10286 default: 10287 return 0; 10288 } 10289 return 1; 10290} 10291 10292#define MESSAGE_TEMPLATE \ 10293" " 10294 10295static char * 10296output_message (FILE *stream, char *p, char *message, char *start, 10297 int *left_p, const char *name, int len) 10298{ 10299 int size = sizeof (MESSAGE_TEMPLATE); 10300 int left = *left_p; 10301 10302 /* Reserve 2 spaces for ", " or ",\0" */ 10303 left -= len + 2; 10304 10305 /* Check if there is any room. */ 10306 if (left >= 0) 10307 { 10308 if (p != start) 10309 { 10310 *p++ = ','; 10311 *p++ = ' '; 10312 } 10313 p = mempcpy (p, name, len); 10314 } 10315 else 10316 { 10317 /* Output the current message now and start a new one. */ 10318 *p++ = ','; 10319 *p = '\0'; 10320 fprintf (stream, "%s\n", message); 10321 p = start; 10322 left = size - (start - message) - len - 2; 10323 10324 gas_assert (left >= 0); 10325 10326 p = mempcpy (p, name, len); 10327 } 10328 10329 *left_p = left; 10330 return p; 10331} 10332 10333static void 10334show_arch (FILE *stream, int ext, int check) 10335{ 10336 static char message[] = MESSAGE_TEMPLATE; 10337 char *start = message + 27; 10338 char *p; 10339 int size = sizeof (MESSAGE_TEMPLATE); 10340 int left; 10341 const char *name; 10342 int len; 10343 unsigned int j; 10344 10345 p = start; 10346 left = size - (start - message); 10347 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) 10348 { 10349 /* Should it be skipped? */ 10350 if (cpu_arch [j].skip) 10351 continue; 10352 10353 name = cpu_arch [j].name; 10354 len = cpu_arch [j].len; 10355 if (*name == '.') 10356 { 10357 /* It is an extension. Skip if we aren't asked to show it. */ 10358 if (ext) 10359 { 10360 name++; 10361 len--; 10362 } 10363 else 10364 continue; 10365 } 10366 else if (ext) 10367 { 10368 /* It is an processor. Skip if we show only extension. */ 10369 continue; 10370 } 10371 else if (check && ! cpu_arch[j].flags.bitfield.cpui386) 10372 { 10373 /* It is an impossible processor - skip. */ 10374 continue; 10375 } 10376 10377 p = output_message (stream, p, message, start, &left, name, len); 10378 } 10379 10380 /* Display disabled extensions. */ 10381 if (ext) 10382 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) 10383 { 10384 name = cpu_noarch [j].name; 10385 len = cpu_noarch [j].len; 10386 p = output_message (stream, p, message, start, &left, name, 10387 len); 10388 } 10389 10390 *p = '\0'; 10391 fprintf (stream, "%s\n", message); 10392} 10393 10394void 10395md_show_usage (FILE *stream) 10396{ 10397#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 10398 fprintf (stream, _("\ 10399 -Q ignored\n\ 10400 -V print assembler version number\n\ 10401 -k ignored\n")); 10402#endif 10403 fprintf (stream, _("\ 10404 -n Do not optimize code alignment\n\ 10405 -q quieten some warnings\n")); 10406#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 10407 fprintf (stream, _("\ 10408 -s ignored\n")); 10409#endif 10410#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ 10411 || defined (TE_PE) || defined (TE_PEP)) 10412 fprintf (stream, _("\ 10413 --32/--64/--x32 generate 32bit/64bit/x32 code\n")); 10414#endif 10415#ifdef SVR4_COMMENT_CHARS 10416 fprintf (stream, _("\ 10417 --divide do not treat `/' as a comment character\n")); 10418#else 10419 fprintf (stream, _("\ 10420 --divide ignored\n")); 10421#endif 10422 fprintf (stream, _("\ 10423 -march=CPU[,+EXTENSION...]\n\ 10424 generate code for CPU and EXTENSION, CPU is one of:\n")); 10425 show_arch (stream, 0, 1); 10426 fprintf (stream, _("\ 10427 EXTENSION is combination of:\n")); 10428 show_arch (stream, 1, 0); 10429 fprintf (stream, _("\ 10430 -mtune=CPU optimize for CPU, CPU is one of:\n")); 10431 show_arch (stream, 0, 0); 10432 fprintf (stream, _("\ 10433 -msse2avx encode SSE instructions with VEX prefix\n")); 10434 fprintf (stream, _("\ 10435 -msse-check=[none|error|warning]\n\ 10436 check SSE instructions\n")); 10437 fprintf (stream, _("\ 10438 -moperand-check=[none|error|warning]\n\ 10439 check operand combinations for validity\n")); 10440 fprintf (stream, _("\ 10441 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\ 10442 length\n")); 10443 fprintf (stream, _("\ 10444 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\ 10445 length\n")); 10446 fprintf (stream, _("\ 10447 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\ 10448 for EVEX.W bit ignored instructions\n")); 10449 fprintf (stream, _("\ 10450 -mevexrcig=[rne|rd|ru|rz]\n\ 10451 encode EVEX instructions with specific EVEX.RC value\n\ 10452 for SAE-only ignored instructions\n")); 10453 fprintf (stream, _("\ 10454 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n")); 10455 fprintf (stream, _("\ 10456 -msyntax=[att|intel] use AT&T/Intel syntax\n")); 10457 fprintf (stream, _("\ 10458 -mindex-reg support pseudo index registers\n")); 10459 fprintf (stream, _("\ 10460 -mnaked-reg don't require `%%' prefix for registers\n")); 10461 fprintf (stream, _("\ 10462 -mold-gcc support old (<= 2.8.1) versions of gcc\n")); 10463 fprintf (stream, _("\ 10464 -madd-bnd-prefix add BND prefix for all valid branches\n")); 10465 fprintf (stream, _("\ 10466 -mshared disable branch optimization for shared code\n")); 10467# if defined (TE_PE) || defined (TE_PEP) 10468 fprintf (stream, _("\ 10469 -mbig-obj generate big object files\n")); 10470#endif 10471 fprintf (stream, _("\ 10472 -momit-lock-prefix=[no|yes]\n\ 10473 strip all lock prefixes\n")); 10474 fprintf (stream, _("\ 10475 -mfence-as-lock-add=[no|yes]\n\ 10476 encode lfence, mfence and sfence as\n\ 10477 lock addl $0x0, (%%{re}sp)\n")); 10478 fprintf (stream, _("\ 10479 -mrelax-relocations=[no|yes]\n\ 10480 generate relax relocations\n")); 10481 fprintf (stream, _("\ 10482 -mamd64 accept only AMD64 ISA\n")); 10483 fprintf (stream, _("\ 10484 -mintel64 accept only Intel64 ISA\n")); 10485} 10486 10487#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ 10488 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ 10489 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) 10490 10491/* Pick the target format to use. */ 10492 10493const char * 10494i386_target_format (void) 10495{ 10496 if (!strncmp (default_arch, "x86_64", 6)) 10497 { 10498 update_code_flag (CODE_64BIT, 1); 10499 if (default_arch[6] == '\0') 10500 x86_elf_abi = X86_64_ABI; 10501 else 10502 x86_elf_abi = X86_64_X32_ABI; 10503 } 10504 else if (!strcmp (default_arch, "i386")) 10505 update_code_flag (CODE_32BIT, 1); 10506 else if (!strcmp (default_arch, "iamcu")) 10507 { 10508 update_code_flag (CODE_32BIT, 1); 10509 if (cpu_arch_isa == PROCESSOR_UNKNOWN) 10510 { 10511 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS; 10512 cpu_arch_name = "iamcu"; 10513 cpu_sub_arch_name = NULL; 10514 cpu_arch_flags = iamcu_flags; 10515 cpu_arch_isa = PROCESSOR_IAMCU; 10516 cpu_arch_isa_flags = iamcu_flags; 10517 if (!cpu_arch_tune_set) 10518 { 10519 cpu_arch_tune = cpu_arch_isa; 10520 cpu_arch_tune_flags = cpu_arch_isa_flags; 10521 } 10522 } 10523 else if (cpu_arch_isa != PROCESSOR_IAMCU) 10524 as_fatal (_("Intel MCU doesn't support `%s' architecture"), 10525 cpu_arch_name); 10526 } 10527 else 10528 as_fatal (_("unknown architecture")); 10529 10530 if (cpu_flags_all_zero (&cpu_arch_isa_flags)) 10531 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags; 10532 if (cpu_flags_all_zero (&cpu_arch_tune_flags)) 10533 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags; 10534 10535 switch (OUTPUT_FLAVOR) 10536 { 10537#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT) 10538 case bfd_target_aout_flavour: 10539 return AOUT_TARGET_FORMAT; 10540#endif 10541#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF) 10542# if defined (TE_PE) || defined (TE_PEP) 10543 case bfd_target_coff_flavour: 10544 if (flag_code == CODE_64BIT) 10545 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64"; 10546 else 10547 return "pe-i386"; 10548# elif defined (TE_GO32) 10549 case bfd_target_coff_flavour: 10550 return "coff-go32"; 10551# else 10552 case bfd_target_coff_flavour: 10553 return "coff-i386"; 10554# endif 10555#endif 10556#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) 10557 case bfd_target_elf_flavour: 10558 { 10559 const char *format; 10560 10561 switch (x86_elf_abi) 10562 { 10563 default: 10564 format = ELF_TARGET_FORMAT; 10565 break; 10566 case X86_64_ABI: 10567 use_rela_relocations = 1; 10568 object_64bit = 1; 10569 format = ELF_TARGET_FORMAT64; 10570 break; 10571 case X86_64_X32_ABI: 10572 use_rela_relocations = 1; 10573 object_64bit = 1; 10574 disallow_64bit_reloc = 1; 10575 format = ELF_TARGET_FORMAT32; 10576 break; 10577 } 10578 if (cpu_arch_isa == PROCESSOR_L1OM) 10579 { 10580 if (x86_elf_abi != X86_64_ABI) 10581 as_fatal (_("Intel L1OM is 64bit only")); 10582 return ELF_TARGET_L1OM_FORMAT; 10583 } 10584 else if (cpu_arch_isa == PROCESSOR_K1OM) 10585 { 10586 if (x86_elf_abi != X86_64_ABI) 10587 as_fatal (_("Intel K1OM is 64bit only")); 10588 return ELF_TARGET_K1OM_FORMAT; 10589 } 10590 else if (cpu_arch_isa == PROCESSOR_IAMCU) 10591 { 10592 if (x86_elf_abi != I386_ABI) 10593 as_fatal (_("Intel MCU is 32bit only")); 10594 return ELF_TARGET_IAMCU_FORMAT; 10595 } 10596 else 10597 return format; 10598 } 10599#endif 10600#if defined (OBJ_MACH_O) 10601 case bfd_target_mach_o_flavour: 10602 if (flag_code == CODE_64BIT) 10603 { 10604 use_rela_relocations = 1; 10605 object_64bit = 1; 10606 return "mach-o-x86-64"; 10607 } 10608 else 10609 return "mach-o-i386"; 10610#endif 10611 default: 10612 abort (); 10613 return NULL; 10614 } 10615} 10616 10617#endif /* OBJ_MAYBE_ more than one */ 10618 10619symbolS * 10620md_undefined_symbol (char *name) 10621{ 10622 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] 10623 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] 10624 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] 10625 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) 10626 { 10627 if (!GOT_symbol) 10628 { 10629 if (symbol_find (name)) 10630 as_bad (_("GOT already in symbol table")); 10631 GOT_symbol = symbol_new (name, undefined_section, 10632 (valueT) 0, &zero_address_frag); 10633 }; 10634 return GOT_symbol; 10635 } 10636 return 0; 10637} 10638 10639/* Round up a section size to the appropriate boundary. */ 10640 10641valueT 10642md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) 10643{ 10644#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) 10645 if (OUTPUT_FLAVOR == bfd_target_aout_flavour) 10646 { 10647 /* For a.out, force the section size to be aligned. If we don't do 10648 this, BFD will align it for us, but it will not write out the 10649 final bytes of the section. This may be a bug in BFD, but it is 10650 easier to fix it here since that is how the other a.out targets 10651 work. */ 10652 int align; 10653 10654 align = bfd_get_section_alignment (stdoutput, segment); 10655 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align))); 10656 } 10657#endif 10658 10659 return size; 10660} 10661 10662/* On the i386, PC-relative offsets are relative to the start of the 10663 next instruction. That is, the address of the offset, plus its 10664 size, since the offset is always the last part of the insn. */ 10665 10666long 10667md_pcrel_from (fixS *fixP) 10668{ 10669 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; 10670} 10671 10672#ifndef I386COFF 10673 10674static void 10675s_bss (int ignore ATTRIBUTE_UNUSED) 10676{ 10677 int temp; 10678 10679#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 10680 if (IS_ELF) 10681 obj_elf_section_change_hook (); 10682#endif 10683 temp = get_absolute_expression (); 10684 subseg_set (bss_section, (subsegT) temp); 10685 demand_empty_rest_of_line (); 10686} 10687 10688#endif 10689 10690void 10691i386_validate_fix (fixS *fixp) 10692{ 10693 if (fixp->fx_subsy) 10694 { 10695 if (fixp->fx_subsy == GOT_symbol) 10696 { 10697 if (fixp->fx_r_type == BFD_RELOC_32_PCREL) 10698 { 10699 if (!object_64bit) 10700 abort (); 10701#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 10702 if (fixp->fx_tcbit2) 10703 fixp->fx_r_type = (fixp->fx_tcbit 10704 ? BFD_RELOC_X86_64_REX_GOTPCRELX 10705 : BFD_RELOC_X86_64_GOTPCRELX); 10706 else 10707#endif 10708 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; 10709 } 10710 else 10711 { 10712 if (!object_64bit) 10713 fixp->fx_r_type = BFD_RELOC_386_GOTOFF; 10714 else 10715 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; 10716 } 10717 fixp->fx_subsy = 0; 10718 } 10719 } 10720#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 10721 else if (!object_64bit) 10722 { 10723 if (fixp->fx_r_type == BFD_RELOC_386_GOT32 10724 && fixp->fx_tcbit2) 10725 fixp->fx_r_type = BFD_RELOC_386_GOT32X; 10726 } 10727#endif 10728} 10729 10730arelent * 10731tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) 10732{ 10733 arelent *rel; 10734 bfd_reloc_code_real_type code; 10735 10736 switch (fixp->fx_r_type) 10737 { 10738#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 10739 case BFD_RELOC_SIZE32: 10740 case BFD_RELOC_SIZE64: 10741 if (S_IS_DEFINED (fixp->fx_addsy) 10742 && !S_IS_EXTERNAL (fixp->fx_addsy)) 10743 { 10744 /* Resolve size relocation against local symbol to size of 10745 the symbol plus addend. */ 10746 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset; 10747 if (fixp->fx_r_type == BFD_RELOC_SIZE32 10748 && !fits_in_unsigned_long (value)) 10749 as_bad_where (fixp->fx_file, fixp->fx_line, 10750 _("symbol size computation overflow")); 10751 fixp->fx_addsy = NULL; 10752 fixp->fx_subsy = NULL; 10753 md_apply_fix (fixp, (valueT *) &value, NULL); 10754 return NULL; 10755 } 10756#endif 10757 /* Fall through. */ 10758 10759 case BFD_RELOC_X86_64_PLT32: 10760 case BFD_RELOC_X86_64_GOT32: 10761 case BFD_RELOC_X86_64_GOTPCREL: 10762 case BFD_RELOC_X86_64_GOTPCRELX: 10763 case BFD_RELOC_X86_64_REX_GOTPCRELX: 10764 case BFD_RELOC_386_PLT32: 10765 case BFD_RELOC_386_GOT32: 10766 case BFD_RELOC_386_GOT32X: 10767 case BFD_RELOC_386_GOTOFF: 10768 case BFD_RELOC_386_GOTPC: 10769 case BFD_RELOC_386_TLS_GD: 10770 case BFD_RELOC_386_TLS_LDM: 10771 case BFD_RELOC_386_TLS_LDO_32: 10772 case BFD_RELOC_386_TLS_IE_32: 10773 case BFD_RELOC_386_TLS_IE: 10774 case BFD_RELOC_386_TLS_GOTIE: 10775 case BFD_RELOC_386_TLS_LE_32: 10776 case BFD_RELOC_386_TLS_LE: 10777 case BFD_RELOC_386_TLS_GOTDESC: 10778 case BFD_RELOC_386_TLS_DESC_CALL: 10779 case BFD_RELOC_X86_64_TLSGD: 10780 case BFD_RELOC_X86_64_TLSLD: 10781 case BFD_RELOC_X86_64_DTPOFF32: 10782 case BFD_RELOC_X86_64_DTPOFF64: 10783 case BFD_RELOC_X86_64_GOTTPOFF: 10784 case BFD_RELOC_X86_64_TPOFF32: 10785 case BFD_RELOC_X86_64_TPOFF64: 10786 case BFD_RELOC_X86_64_GOTOFF64: 10787 case BFD_RELOC_X86_64_GOTPC32: 10788 case BFD_RELOC_X86_64_GOT64: 10789 case BFD_RELOC_X86_64_GOTPCREL64: 10790 case BFD_RELOC_X86_64_GOTPC64: 10791 case BFD_RELOC_X86_64_GOTPLT64: 10792 case BFD_RELOC_X86_64_PLTOFF64: 10793 case BFD_RELOC_X86_64_GOTPC32_TLSDESC: 10794 case BFD_RELOC_X86_64_TLSDESC_CALL: 10795 case BFD_RELOC_RVA: 10796 case BFD_RELOC_VTABLE_ENTRY: 10797 case BFD_RELOC_VTABLE_INHERIT: 10798#ifdef TE_PE 10799 case BFD_RELOC_32_SECREL: 10800#endif 10801 code = fixp->fx_r_type; 10802 break; 10803 case BFD_RELOC_X86_64_32S: 10804 if (!fixp->fx_pcrel) 10805 { 10806 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */ 10807 code = fixp->fx_r_type; 10808 break; 10809 } 10810 /* Fall through. */ 10811 default: 10812 if (fixp->fx_pcrel) 10813 { 10814 switch (fixp->fx_size) 10815 { 10816 default: 10817 as_bad_where (fixp->fx_file, fixp->fx_line, 10818 _("can not do %d byte pc-relative relocation"), 10819 fixp->fx_size); 10820 code = BFD_RELOC_32_PCREL; 10821 break; 10822 case 1: code = BFD_RELOC_8_PCREL; break; 10823 case 2: code = BFD_RELOC_16_PCREL; break; 10824 case 4: code = BFD_RELOC_32_PCREL; break; 10825#ifdef BFD64 10826 case 8: code = BFD_RELOC_64_PCREL; break; 10827#endif 10828 } 10829 } 10830 else 10831 { 10832 switch (fixp->fx_size) 10833 { 10834 default: 10835 as_bad_where (fixp->fx_file, fixp->fx_line, 10836 _("can not do %d byte relocation"), 10837 fixp->fx_size); 10838 code = BFD_RELOC_32; 10839 break; 10840 case 1: code = BFD_RELOC_8; break; 10841 case 2: code = BFD_RELOC_16; break; 10842 case 4: code = BFD_RELOC_32; break; 10843#ifdef BFD64 10844 case 8: code = BFD_RELOC_64; break; 10845#endif 10846 } 10847 } 10848 break; 10849 } 10850 10851 if ((code == BFD_RELOC_32 10852 || code == BFD_RELOC_32_PCREL 10853 || code == BFD_RELOC_X86_64_32S) 10854 && GOT_symbol 10855 && fixp->fx_addsy == GOT_symbol) 10856 { 10857 if (!object_64bit) 10858 code = BFD_RELOC_386_GOTPC; 10859 else 10860 code = BFD_RELOC_X86_64_GOTPC32; 10861 } 10862 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL) 10863 && GOT_symbol 10864 && fixp->fx_addsy == GOT_symbol) 10865 { 10866 code = BFD_RELOC_X86_64_GOTPC64; 10867 } 10868 10869 rel = XNEW (arelent); 10870 rel->sym_ptr_ptr = XNEW (asymbol *); 10871 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 10872 10873 rel->address = fixp->fx_frag->fr_address + fixp->fx_where; 10874 10875 if (!use_rela_relocations) 10876 { 10877 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the 10878 vtable entry to be used in the relocation's section offset. */ 10879 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 10880 rel->address = fixp->fx_offset; 10881#if defined (OBJ_COFF) && defined (TE_PE) 10882 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy)) 10883 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2); 10884 else 10885#endif 10886 rel->addend = 0; 10887 } 10888 /* Use the rela in 64bit mode. */ 10889 else 10890 { 10891 if (disallow_64bit_reloc) 10892 switch (code) 10893 { 10894 case BFD_RELOC_X86_64_DTPOFF64: 10895 case BFD_RELOC_X86_64_TPOFF64: 10896 case BFD_RELOC_64_PCREL: 10897 case BFD_RELOC_X86_64_GOTOFF64: 10898 case BFD_RELOC_X86_64_GOT64: 10899 case BFD_RELOC_X86_64_GOTPCREL64: 10900 case BFD_RELOC_X86_64_GOTPC64: 10901 case BFD_RELOC_X86_64_GOTPLT64: 10902 case BFD_RELOC_X86_64_PLTOFF64: 10903 as_bad_where (fixp->fx_file, fixp->fx_line, 10904 _("cannot represent relocation type %s in x32 mode"), 10905 bfd_get_reloc_code_name (code)); 10906 break; 10907 default: 10908 break; 10909 } 10910 10911 if (!fixp->fx_pcrel) 10912 rel->addend = fixp->fx_offset; 10913 else 10914 switch (code) 10915 { 10916 case BFD_RELOC_X86_64_PLT32: 10917 case BFD_RELOC_X86_64_GOT32: 10918 case BFD_RELOC_X86_64_GOTPCREL: 10919 case BFD_RELOC_X86_64_GOTPCRELX: 10920 case BFD_RELOC_X86_64_REX_GOTPCRELX: 10921 case BFD_RELOC_X86_64_TLSGD: 10922 case BFD_RELOC_X86_64_TLSLD: 10923 case BFD_RELOC_X86_64_GOTTPOFF: 10924 case BFD_RELOC_X86_64_GOTPC32_TLSDESC: 10925 case BFD_RELOC_X86_64_TLSDESC_CALL: 10926 rel->addend = fixp->fx_offset - fixp->fx_size; 10927 break; 10928 default: 10929 rel->addend = (section->vma 10930 - fixp->fx_size 10931 + fixp->fx_addnumber 10932 + md_pcrel_from (fixp)); 10933 break; 10934 } 10935 } 10936 10937 rel->howto = bfd_reloc_type_lookup (stdoutput, code); 10938 if (rel->howto == NULL) 10939 { 10940 as_bad_where (fixp->fx_file, fixp->fx_line, 10941 _("cannot represent relocation type %s"), 10942 bfd_get_reloc_code_name (code)); 10943 /* Set howto to a garbage value so that we can keep going. */ 10944 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); 10945 gas_assert (rel->howto != NULL); 10946 } 10947 10948 return rel; 10949} 10950 10951#include "tc-i386-intel.c" 10952 10953void 10954tc_x86_parse_to_dw2regnum (expressionS *exp) 10955{ 10956 int saved_naked_reg; 10957 char saved_register_dot; 10958 10959 saved_naked_reg = allow_naked_reg; 10960 allow_naked_reg = 1; 10961 saved_register_dot = register_chars['.']; 10962 register_chars['.'] = '.'; 10963 allow_pseudo_reg = 1; 10964 expression_and_evaluate (exp); 10965 allow_pseudo_reg = 0; 10966 register_chars['.'] = saved_register_dot; 10967 allow_naked_reg = saved_naked_reg; 10968 10969 if (exp->X_op == O_register && exp->X_add_number >= 0) 10970 { 10971 if ((addressT) exp->X_add_number < i386_regtab_size) 10972 { 10973 exp->X_op = O_constant; 10974 exp->X_add_number = i386_regtab[exp->X_add_number] 10975 .dw2_regnum[flag_code >> 1]; 10976 } 10977 else 10978 exp->X_op = O_illegal; 10979 } 10980} 10981 10982void 10983tc_x86_frame_initial_instructions (void) 10984{ 10985 static unsigned int sp_regno[2]; 10986 10987 if (!sp_regno[flag_code >> 1]) 10988 { 10989 char *saved_input = input_line_pointer; 10990 char sp[][4] = {"esp", "rsp"}; 10991 expressionS exp; 10992 10993 input_line_pointer = sp[flag_code >> 1]; 10994 tc_x86_parse_to_dw2regnum (&exp); 10995 gas_assert (exp.X_op == O_constant); 10996 sp_regno[flag_code >> 1] = exp.X_add_number; 10997 input_line_pointer = saved_input; 10998 } 10999 11000 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment); 11001 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); 11002} 11003 11004int 11005x86_dwarf2_addr_size (void) 11006{ 11007#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) 11008 if (x86_elf_abi == X86_64_X32_ABI) 11009 return 4; 11010#endif 11011 return bfd_arch_bits_per_address (stdoutput) / 8; 11012} 11013 11014int 11015i386_elf_section_type (const char *str, size_t len) 11016{ 11017 if (flag_code == CODE_64BIT 11018 && len == sizeof ("unwind") - 1 11019 && strncmp (str, "unwind", 6) == 0) 11020 return SHT_X86_64_UNWIND; 11021 11022 return -1; 11023} 11024 11025#ifdef TE_SOLARIS 11026void 11027i386_solaris_fix_up_eh_frame (segT sec) 11028{ 11029 if (flag_code == CODE_64BIT) 11030 elf_section_type (sec) = SHT_X86_64_UNWIND; 11031} 11032#endif 11033 11034#ifdef TE_PE 11035void 11036tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) 11037{ 11038 expressionS exp; 11039 11040 exp.X_op = O_secrel; 11041 exp.X_add_symbol = symbol; 11042 exp.X_add_number = 0; 11043 emit_expr (&exp, size); 11044} 11045#endif 11046 11047#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 11048/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ 11049 11050bfd_vma 11051x86_64_section_letter (int letter, const char **ptr_msg) 11052{ 11053 if (flag_code == CODE_64BIT) 11054 { 11055 if (letter == 'l') 11056 return SHF_X86_64_LARGE; 11057 11058 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string"); 11059 } 11060 else 11061 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string"); 11062 return -1; 11063} 11064 11065bfd_vma 11066x86_64_section_word (char *str, size_t len) 11067{ 11068 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large")) 11069 return SHF_X86_64_LARGE; 11070 11071 return -1; 11072} 11073 11074static void 11075handle_large_common (int small ATTRIBUTE_UNUSED) 11076{ 11077 if (flag_code != CODE_64BIT) 11078 { 11079 s_comm_internal (0, elf_common_parse); 11080 as_warn (_(".largecomm supported only in 64bit mode, producing .comm")); 11081 } 11082 else 11083 { 11084 static segT lbss_section; 11085 asection *saved_com_section_ptr = elf_com_section_ptr; 11086 asection *saved_bss_section = bss_section; 11087 11088 if (lbss_section == NULL) 11089 { 11090 flagword applicable; 11091 segT seg = now_seg; 11092 subsegT subseg = now_subseg; 11093 11094 /* The .lbss section is for local .largecomm symbols. */ 11095 lbss_section = subseg_new (".lbss", 0); 11096 applicable = bfd_applicable_section_flags (stdoutput); 11097 bfd_set_section_flags (stdoutput, lbss_section, 11098 applicable & SEC_ALLOC); 11099 seg_info (lbss_section)->bss = 1; 11100 11101 subseg_set (seg, subseg); 11102 } 11103 11104 elf_com_section_ptr = &_bfd_elf_large_com_section; 11105 bss_section = lbss_section; 11106 11107 s_comm_internal (0, elf_common_parse); 11108 11109 elf_com_section_ptr = saved_com_section_ptr; 11110 bss_section = saved_bss_section; 11111 } 11112} 11113#endif /* OBJ_ELF || OBJ_MAYBE_ELF */ 11114