1/* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 */ 28 29#ifndef _QLNX_IOCTL_H_ 30#define _QLNX_IOCTL_H_ 31 32#include <sys/ioccom.h> 33 34#define QLNX_MAX_HW_FUNCS 2 35 36/* 37 * Read grcdump and grcdump size 38 */ 39 40struct qlnx_grcdump { 41 uint16_t pci_func; 42 uint32_t grcdump_size[QLNX_MAX_HW_FUNCS]; 43 void *grcdump[QLNX_MAX_HW_FUNCS]; 44 uint32_t grcdump_dwords[QLNX_MAX_HW_FUNCS]; 45}; 46typedef struct qlnx_grcdump qlnx_grcdump_t; 47 48/* 49 * Read idle_chk and idle_chk size 50 */ 51struct qlnx_idle_chk { 52 uint16_t pci_func; 53 uint32_t idle_chk_size[QLNX_MAX_HW_FUNCS]; 54 void *idle_chk[QLNX_MAX_HW_FUNCS]; 55 uint32_t idle_chk_dwords[QLNX_MAX_HW_FUNCS]; 56}; 57typedef struct qlnx_idle_chk qlnx_idle_chk_t; 58 59/* 60 * Retrive traces 61 */ 62struct qlnx_trace { 63 uint16_t pci_func; 64 65 uint16_t cmd; 66#define QLNX_MCP_TRACE 0x01 67#define QLNX_REG_FIFO 0x02 68#define QLNX_IGU_FIFO 0x03 69#define QLNX_PROTECTION_OVERRIDE 0x04 70#define QLNX_FW_ASSERTS 0x05 71 72 uint32_t size[QLNX_MAX_HW_FUNCS]; 73 void *buffer[QLNX_MAX_HW_FUNCS]; 74 uint32_t dwords[QLNX_MAX_HW_FUNCS]; 75}; 76typedef struct qlnx_trace qlnx_trace_t; 77 78/* 79 * Read driver info 80 */ 81#define QLNX_DRV_INFO_NAME_LENGTH 32 82#define QLNX_DRV_INFO_VERSION_LENGTH 32 83#define QLNX_DRV_INFO_MFW_VERSION_LENGTH 32 84#define QLNX_DRV_INFO_STORMFW_VERSION_LENGTH 32 85#define QLNX_DRV_INFO_BUS_INFO_LENGTH 32 86 87struct qlnx_drvinfo { 88 char drv_name[QLNX_DRV_INFO_NAME_LENGTH]; 89 char drv_version[QLNX_DRV_INFO_VERSION_LENGTH]; 90 char mfw_version[QLNX_DRV_INFO_MFW_VERSION_LENGTH]; 91 char stormfw_version[QLNX_DRV_INFO_STORMFW_VERSION_LENGTH]; 92 uint32_t eeprom_dump_len; /* in bytes */ 93 uint32_t reg_dump_len; /* in bytes */ 94 char bus_info[QLNX_DRV_INFO_BUS_INFO_LENGTH]; 95}; 96typedef struct qlnx_drvinfo qlnx_drvinfo_t; 97 98/* 99 * Read Device Setting 100 */ 101struct qlnx_dev_setting { 102 uint32_t supported; /* Features this interface supports */ 103 uint32_t advertising; /* Features this interface advertises */ 104 uint32_t speed; /* The forced speed, 10Mb, 100Mb, gigabit */ 105 uint32_t duplex; /* Duplex, half or full */ 106 uint32_t port; /* Which connector port */ 107 uint32_t phy_address; /* port number*/ 108 uint32_t autoneg; /* Enable or disable autonegotiation */ 109}; 110typedef struct qlnx_dev_setting qlnx_dev_setting_t; 111 112/* 113 * Get Registers 114 */ 115struct qlnx_get_regs { 116 void *reg_buf; 117 uint32_t reg_buf_len; 118}; 119typedef struct qlnx_get_regs qlnx_get_regs_t; 120 121/* 122 * Get/Set NVRAM 123 */ 124struct qlnx_nvram { 125 uint32_t cmd; 126#define QLNX_NVRAM_CMD_WRITE_NVRAM 0x01 127#define QLNX_NVRAM_CMD_READ_NVRAM 0x02 128#define QLNX_NVRAM_CMD_SET_SECURE_MODE 0x03 129#define QLNX_NVRAM_CMD_DEL_FILE 0x04 130#define QLNX_NVRAM_CMD_PUT_FILE_BEGIN 0x05 131#define QLNX_NVRAM_CMD_GET_NVRAM_RESP 0x06 132#define QLNX_NVRAM_CMD_PUT_FILE_DATA 0x07 133 134 void *data; 135 uint32_t offset; 136 uint32_t data_len; 137 uint32_t magic; 138}; 139typedef struct qlnx_nvram qlnx_nvram_t; 140 141/* 142 * Get/Set Device registers 143 */ 144struct qlnx_reg_rd_wr { 145 uint32_t cmd; 146#define QLNX_REG_READ_CMD 0x01 147#define QLNX_REG_WRITE_CMD 0x02 148 149 uint32_t addr; 150 uint32_t val; 151 152 uint32_t access_type; 153#define QLNX_REG_ACCESS_DIRECT 0x01 154#define QLNX_REG_ACCESS_INDIRECT 0x02 155 156 uint32_t hwfn_index; 157}; 158typedef struct qlnx_reg_rd_wr qlnx_reg_rd_wr_t; 159 160/* 161 * Read/Write PCI Configuration 162 */ 163struct qlnx_pcicfg_rd_wr { 164 uint32_t cmd; 165#define QLNX_PCICFG_READ 0x01 166#define QLNX_PCICFG_WRITE 0x02 167 uint32_t reg; 168 uint32_t val; 169 uint32_t width; 170}; 171typedef struct qlnx_pcicfg_rd_wr qlnx_pcicfg_rd_wr_t; 172 173/* 174 * Read MAC address 175 */ 176struct qlnx_perm_mac_addr { 177 char addr[32]; 178}; 179typedef struct qlnx_perm_mac_addr qlnx_perm_mac_addr_t; 180 181/* 182 * Read STORM statistics registers 183 */ 184struct qlnx_storm_stats { 185 /* xstorm */ 186 uint32_t xstorm_active_cycles; 187 uint32_t xstorm_stall_cycles; 188 uint32_t xstorm_sleeping_cycles; 189 uint32_t xstorm_inactive_cycles; 190 191 /* ystorm */ 192 uint32_t ystorm_active_cycles; 193 uint32_t ystorm_stall_cycles; 194 uint32_t ystorm_sleeping_cycles; 195 uint32_t ystorm_inactive_cycles; 196 197 /* pstorm */ 198 uint32_t pstorm_active_cycles; 199 uint32_t pstorm_stall_cycles; 200 uint32_t pstorm_sleeping_cycles; 201 uint32_t pstorm_inactive_cycles; 202 203 /* tstorm */ 204 uint32_t tstorm_active_cycles; 205 uint32_t tstorm_stall_cycles; 206 uint32_t tstorm_sleeping_cycles; 207 uint32_t tstorm_inactive_cycles; 208 209 /* mstorm */ 210 uint32_t mstorm_active_cycles; 211 uint32_t mstorm_stall_cycles; 212 uint32_t mstorm_sleeping_cycles; 213 uint32_t mstorm_inactive_cycles; 214 215 /* ustorm */ 216 uint32_t ustorm_active_cycles; 217 uint32_t ustorm_stall_cycles; 218 uint32_t ustorm_sleeping_cycles; 219 uint32_t ustorm_inactive_cycles; 220}; 221 222typedef struct qlnx_storm_stats qlnx_storm_stats_t; 223 224#define QLNX_STORM_STATS_SAMPLES_PER_HWFN (10000) 225 226#define QLNX_STORM_STATS_BYTES_PER_HWFN (sizeof(qlnx_storm_stats_t) * \ 227 QLNX_STORM_STATS_SAMPLES_PER_HWFN) 228 229struct qlnx_storm_stats_dump { 230 int num_hwfns; 231 int num_samples; 232 void *buffer[QLNX_MAX_HW_FUNCS]; 233}; 234 235typedef struct qlnx_storm_stats_dump qlnx_storm_stats_dump_t; 236 237#define QLNX_LLDP_TYPE_END_OF_LLDPDU 0 238#define QLNX_LLDP_TYPE_CHASSIS_ID 1 239#define QLNX_LLDP_TYPE_PORT_ID 2 240#define QLNX_LLDP_TYPE_TTL 3 241#define QLNX_LLDP_TYPE_PORT_DESC 4 242#define QLNX_LLDP_TYPE_SYS_NAME 5 243#define QLNX_LLDP_TYPE_SYS_DESC 6 244#define QLNX_LLDP_TYPE_SYS_CAPS 7 245#define QLNX_LLDP_TYPE_MGMT_ADDR 8 246#define QLNX_LLDP_TYPE_ORG_SPECIFIC 127 247 248#define QLNX_LLDP_CHASSIS_ID_SUBTYPE_OCTETS 1 //Subtype is 1 byte 249#define QLNX_LLDP_CHASSIS_ID_SUBTYPE_MAC 0x04 //Mac Address 250#define QLNX_LLDP_CHASSIS_ID_MAC_ADDR_LEN 6 // Mac address is 6 bytes 251#define QLNX_LLDP_CHASSIS_ID_SUBTYPE_IF_NAME 0x06 //Interface Name 252 253#define QLNX_LLDP_PORT_ID_SUBTYPE_OCTETS 1 //Subtype is 1 byte 254#define QLNX_LLDP_PORT_ID_SUBTYPE_MAC 0x03 //Mac Address 255#define QLNX_LLDP_PORT_ID_MAC_ADDR_LEN 6 // Mac address is 6 bytes 256#define QLNX_LLDP_PORT_ID_SUBTYPE_IF_NAME 0x05 //Interface Name 257 258#define QLNX_LLDP_SYS_TLV_SIZE 256 259struct qlnx_lldp_sys_tlvs { 260 int discard_mandatory_tlv; 261 uint8_t buf[QLNX_LLDP_SYS_TLV_SIZE]; 262 uint16_t buf_size; 263}; 264typedef struct qlnx_lldp_sys_tlvs qlnx_lldp_sys_tlvs_t; 265 266/* 267 * Read grcdump size 268 */ 269#define QLNX_GRC_DUMP_SIZE _IOWR('q', 1, qlnx_grcdump_t) 270 271/* 272 * Read grcdump 273 */ 274#define QLNX_GRC_DUMP _IOWR('q', 2, qlnx_grcdump_t) 275 276/* 277 * Read idle_chk size 278 */ 279#define QLNX_IDLE_CHK_SIZE _IOWR('q', 3, qlnx_idle_chk_t) 280 281/* 282 * Read idle_chk 283 */ 284#define QLNX_IDLE_CHK _IOWR('q', 4, qlnx_idle_chk_t) 285 286/* 287 * Read driver info 288 */ 289#define QLNX_DRV_INFO _IOWR('q', 5, qlnx_drvinfo_t) 290 291/* 292 * Read Device Setting 293 */ 294#define QLNX_DEV_SETTING _IOR('q', 6, qlnx_dev_setting_t) 295 296/* 297 * Get Registers 298 */ 299#define QLNX_GET_REGS _IOR('q', 7, qlnx_get_regs_t) 300 301/* 302 * Get/Set NVRAM 303 */ 304#define QLNX_NVRAM _IOWR('q', 8, qlnx_nvram_t) 305 306/* 307 * Get/Set Device registers 308 */ 309#define QLNX_RD_WR_REG _IOWR('q', 9, qlnx_reg_rd_wr_t) 310 311/* 312 * Read/Write PCI Configuration 313 */ 314#define QLNX_RD_WR_PCICFG _IOWR('q', 10, qlnx_pcicfg_rd_wr_t) 315 316/* 317 * Read MAC address 318 */ 319#define QLNX_MAC_ADDR _IOWR('q', 11, qlnx_perm_mac_addr_t) 320 321/* 322 * Read STORM statistics 323 */ 324#define QLNX_STORM_STATS _IOWR('q', 12, qlnx_storm_stats_dump_t) 325 326/* 327 * Read trace size 328 */ 329#define QLNX_TRACE_SIZE _IOWR('q', 13, qlnx_trace_t) 330 331/* 332 * Read trace 333 */ 334#define QLNX_TRACE _IOWR('q', 14, qlnx_trace_t) 335 336/* 337 * Set LLDP TLVS 338 */ 339#define QLNX_SET_LLDP_TLVS _IOWR('q', 15, qlnx_lldp_sys_tlvs_t) 340 341#endif /* #ifndef _QLNX_IOCTL_H_ */ 342