1/* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 */ 28 29/**************************************************************************** 30 * Name: nvm_map.h 31 * 32 * Description: Everest NVRAM map 33 * 34 ****************************************************************************/ 35 36#ifndef NVM_MAP_H 37#define NVM_MAP_H 38 39#define CRC_MAGIC_VALUE 0xDEBB20E3 40#define CRC32_POLYNOMIAL 0xEDB88320 41#define _KB(x) (x*1024) 42#define _MB(x) (_KB(x)*1024) 43#define NVM_CRC_SIZE (sizeof(u32)) 44enum nvm_sw_arbitrator { 45 NVM_SW_ARB_HOST, 46 NVM_SW_ARB_MCP, 47 NVM_SW_ARB_UART, 48 NVM_SW_ARB_RESERVED 49}; 50 51/**************************************************************************** 52 * Boot Strap Region * 53 ****************************************************************************/ 54struct legacy_bootstrap_region { 55 u32 magic_value; /* a pattern not likely to occur randomly */ 56#define NVM_MAGIC_VALUE 0x669955aa 57 u32 sram_start_addr; /* where to locate LIM code (byte addr) */ 58 u32 code_len; /* boot code length (in dwords) */ 59 u32 code_start_addr; /* location of code on media (media byte addr) */ 60 u32 crc; /* 32-bit CRC */ 61}; 62 63/**************************************************************************** 64 * Directories Region * 65 ****************************************************************************/ 66struct nvm_code_entry { 67 u32 image_type; /* Image type */ 68 u32 nvm_start_addr; /* NVM address of the image */ 69 u32 len; /* Include CRC */ 70 u32 sram_start_addr; /* Where to load the image on the scratchpad */ 71 u32 sram_run_addr; /* Relevant in case of MIM only */ 72}; 73 74enum nvm_image_type { 75 NVM_TYPE_TIM1 = 0x01, 76 NVM_TYPE_TIM2 = 0x02, 77 NVM_TYPE_MIM1 = 0x03, 78 NVM_TYPE_MIM2 = 0x04, 79 NVM_TYPE_MBA = 0x05, 80 NVM_TYPE_MODULES_PN = 0x06, 81 NVM_TYPE_VPD = 0x07, 82 NVM_TYPE_MFW_TRACE1 = 0x08, 83 NVM_TYPE_MFW_TRACE2 = 0x09, 84 NVM_TYPE_NVM_CFG1 = 0x0a, 85 NVM_TYPE_L2B = 0x0b, 86 NVM_TYPE_DIR1 = 0x0c, 87 NVM_TYPE_EAGLE_FW1 = 0x0d, 88 NVM_TYPE_FALCON_FW1 = 0x0e, 89 NVM_TYPE_PCIE_FW1 = 0x0f, 90 NVM_TYPE_HW_SET = 0x10, 91 NVM_TYPE_LIM = 0x11, 92 NVM_TYPE_AVS_FW1 = 0x12, 93 NVM_TYPE_DIR2 = 0x13, 94 NVM_TYPE_CCM = 0x14, 95 NVM_TYPE_EAGLE_FW2 = 0x15, 96 NVM_TYPE_FALCON_FW2 = 0x16, 97 NVM_TYPE_PCIE_FW2 = 0x17, 98 NVM_TYPE_AVS_FW2 = 0x18, 99 NVM_TYPE_INIT_HW = 0x19, 100 NVM_TYPE_DEFAULT_CFG= 0x1a, 101 NVM_TYPE_MDUMP = 0x1b, 102 NVM_TYPE_NVM_META = 0x1c, 103 NVM_TYPE_ISCSI_CFG = 0x1d, 104 NVM_TYPE_FCOE_CFG = 0x1f, 105 NVM_TYPE_ETH_PHY_FW1 = 0x20, 106 NVM_TYPE_ETH_PHY_FW2 = 0x21, 107 NVM_TYPE_BDN = 0x22, 108 NVM_TYPE_8485X_PHY_FW = 0x23, 109 NVM_TYPE_PUB_KEY = 0x24, 110 NVM_TYPE_RECOVERY = 0x25, 111 NVM_TYPE_PLDM = 0x26, 112 NVM_TYPE_UPK1 = 0x27, 113 NVM_TYPE_UPK2 = 0x28, 114 NVM_TYPE_MASTER_KC = 0x29, 115 NVM_TYPE_BACKUP_KC = 0x2a, 116 NVM_TYPE_ROM_TEST = 0xf0, 117 NVM_TYPE_MAX, 118}; 119 120#ifdef DEFINE_IMAGE_TABLE 121struct image_map { 122 char name[32]; 123 char option[32]; 124 u32 image_type; 125}; 126 127struct image_map g_image_table[] = { 128 {"TIM1", "-tim1", NVM_TYPE_TIM1}, 129 {"TIM2", "-tim2", NVM_TYPE_TIM2}, 130 {"MIM1", "-mim1", NVM_TYPE_MIM1}, 131 {"MIM2", "-mim2", NVM_TYPE_MIM2}, 132 {"MBA", "-mba", NVM_TYPE_MBA}, 133 {"OPT_MODULES", "-optm", NVM_TYPE_MODULES_PN}, 134 {"VPD", "-vpd", NVM_TYPE_VPD}, 135 {"MFW_TRACE1", "-mfwt1", NVM_TYPE_MFW_TRACE1}, 136 {"MFW_TRACE2", "-mfwt2", NVM_TYPE_MFW_TRACE2}, 137 {"NVM_CFG1", "-cfg", NVM_TYPE_NVM_CFG1}, 138 {"L2B", "-l2b", NVM_TYPE_L2B}, 139 {"DIR1", "-dir1", NVM_TYPE_DIR1}, 140 {"EAGLE_FW1", "-eagle1", NVM_TYPE_EAGLE_FW1}, 141 {"FALCON_FW1", "-falcon1", NVM_TYPE_FALCON_FW1}, 142 {"PCIE_FW1", "-pcie1", NVM_TYPE_PCIE_FW1}, 143 {"HW_SET", "-hw_set", NVM_TYPE_HW_SET}, 144 {"LIM", "-lim", NVM_TYPE_LIM}, 145 {"AVS_FW1", "-avs1", NVM_TYPE_AVS_FW1}, 146 {"DIR2", "-dir2", NVM_TYPE_DIR2}, 147 {"CCM", "-ccm", NVM_TYPE_CCM}, 148 {"EAGLE_FW2", "-eagle2", NVM_TYPE_EAGLE_FW2}, 149 {"FALCON_FW2", "-falcon2", NVM_TYPE_FALCON_FW2}, 150 {"PCIE_FW2", "-pcie2", NVM_TYPE_PCIE_FW2}, 151 {"AVS_FW2", "-avs2", NVM_TYPE_AVS_FW2}, 152 {"INIT_HW", "-init_hw", NVM_TYPE_INIT_HW}, 153 {"DEFAULT_CFG", "-def_cfg", NVM_TYPE_DEFAULT_CFG}, 154 {"CRASH_DUMP", "-mdump", NVM_TYPE_MDUMP}, 155 {"META", "-meta", NVM_TYPE_NVM_META}, 156 {"ISCSI_CFG", "-iscsi_cfg", NVM_TYPE_ISCSI_CFG}, 157 {"FCOE_CFG", "-fcoe_cfg",NVM_TYPE_FCOE_CFG}, 158 {"ETH_PHY_FW1", "-ethphy1", NVM_TYPE_ETH_PHY_FW1}, 159 {"ETH_PHY_FW2", "-ethphy2", NVM_TYPE_ETH_PHY_FW2}, 160 {"BDN", "-bdn", NVM_TYPE_BDN}, 161 {"PK", "-pk", NVM_TYPE_PUB_KEY}, 162 {"RECOVERY", "-recovery",NVM_TYPE_RECOVERY}, 163 {"PLDM", "-pldm", NVM_TYPE_PLDM}, 164 {"UPK1", "-upk1", NVM_TYPE_UPK1}, 165 {"UPK2", "-upk2", NVM_TYPE_UPK2}, 166 {"ROMTEST", "-romtest" ,NVM_TYPE_ROM_TEST}, 167 {"MASTER_KC", "-kc" ,NVM_TYPE_MASTER_KC}, 168 {"BACKUP_KC", "" ,NVM_TYPE_BACKUP_KC} 169}; 170 171#define IMAGE_TABLE_SIZE (sizeof(g_image_table) / sizeof(struct image_map)) 172 173#endif /* #ifdef DEFINE_IMAGE_TABLE */ 174#define MAX_NVM_DIR_ENTRIES 150 175/* Note: The has given 150 possible entries since anyway each file captures at least one page. */ 176 177struct nvm_dir_meta { 178 u32 dir_id; 179 u32 nvm_dir_addr; 180 u32 num_images; 181 u32 next_mfw_to_run; 182}; 183 184struct nvm_dir { 185 s32 seq; /* This dword is used to indicate whether this dir is valid, and whether it is more updated than the other dir */ 186#define NVM_DIR_NEXT_MFW_MASK 0x00000001 187#define NVM_DIR_SEQ_MASK 0xfffffffe 188#define NVM_DIR_NEXT_MFW(seq) ((seq) & NVM_DIR_NEXT_MFW_MASK) 189#define NVM_DIR_UPDATE_SEQ(_seq, swap_mfw) \ 190 do { \ 191 _seq = (((_seq + 2) & NVM_DIR_SEQ_MASK) | (NVM_DIR_NEXT_MFW(_seq ^ swap_mfw))); \ 192 } while (0) 193#define IS_DIR_SEQ_VALID(seq) ((seq & NVM_DIR_SEQ_MASK) != NVM_DIR_SEQ_MASK) 194 195 u32 num_images; 196 u32 rsrv; 197 struct nvm_code_entry code[1]; /* Up to MAX_NVM_DIR_ENTRIES */ 198}; 199#define NVM_DIR_SIZE(_num_images) (sizeof(struct nvm_dir) + (_num_images - 1) * sizeof(struct nvm_code_entry) + NVM_CRC_SIZE) 200 201struct nvm_vpd_image { 202 u32 format_revision; 203#define VPD_IMAGE_VERSION 1 204 205 /* This array length depends on the number of VPD fields */ 206 u8 vpd_data[1]; 207}; 208 209/**************************************************************************** 210 * NVRAM FULL MAP * 211 ****************************************************************************/ 212#define DIR_ID_1 (0) 213#define DIR_ID_2 (1) 214#define MAX_DIR_IDS (2) 215 216#define MFW_BUNDLE_1 (0) 217#define MFW_BUNDLE_2 (1) 218#define MAX_MFW_BUNDLES (2) 219 220#define FLASH_PAGE_SIZE 0x1000 221#define NVM_DIR_MAX_SIZE (FLASH_PAGE_SIZE) /* 4Kb */ 222#define LEGACY_ASIC_MIM_MAX_SIZE (_KB(1200)) /* 1.2Mb - E4*/ 223#define NG_ASIC_MIM_MAX_SIZE (_MB(2)) /* 2Mb - E5 */ 224 225#define FPGA_MIM_MAX_SIZE (0x3E000) /* 250Kb */ 226 227/* Each image must start on its own page. Bootstrap and LIM are bound together, so they can share the same page. 228 * The LIM itself should be very small, so limit it to 8Kb, but in order to open a new page, we decrement the bootstrap size out of it. 229 */ 230#define LIM_MAX_SIZE ((2*FLASH_PAGE_SIZE) - sizeof(struct legacy_bootstrap_region) - NVM_RSV_SIZE) 231#define LIM_OFFSET (NVM_OFFSET(lim_image)) 232#define NVM_RSV_SIZE (44) 233#define GET_MIM_MAX_SIZE(is_asic, is_e4) ((!is_asic) ? FPGA_MIM_MAX_SIZE : ((is_e4) ? LEGACY_ASIC_MIM_MAX_SIZE : NG_ASIC_MIM_MAX_SIZE)) 234#define GET_MIM_OFFSET(idx, is_asic, is_e4) (NVM_OFFSET(dir[MAX_MFW_BUNDLES]) + ((idx == NVM_TYPE_MIM2) ?GET_MIM_MAX_SIZE(is_asic, is_e4) : 0)) 235#define GET_NVM_FIXED_AREA_SIZE(is_asic, is_e4) (sizeof(struct nvm_image) + GET_MIM_MAX_SIZE(is_asic, is_e4)*2) 236 237#define EMUL_NVM_FIXED_AREA_SIZE() (sizeof(struct nvm_image) + GET_MIM_MAX_SIZE(0, 0)) 238 239#define E5_MASTER_KEY_CHAIN_ADDR 0x1000 240#define E5_BACKUP_KEY_CHAIN_ADDR ((0x20000 << (REG_READ(0, MCP_REG_NVM_CFG4) & 0x7)) - 0x1000) 241 242union nvm_dir_union { 243 struct nvm_dir dir; 244 u8 page[FLASH_PAGE_SIZE]; 245}; 246 247/* E4 Address E5 Address 248 * +-------------------+ 0x000000 * +-------------------+ 0x000000 249 * | Bootstrap: | * | | 250 * | magic_number | * | | 251 * | sram_start_addr | * | | 252 * | code_len | * | | 253 * | code_start_addr | * | | 254 * | crc | * | | 255 * +-------------------+ 0x000014 * | | 256 * | rsrv | * | rsrv | 257 * +-------------------+ 0x000040 * +-------------------+ 0x001000 258 * | LIM | * | Master Key Chain | 259 * +-------------------+ 0x002000 * +-------------------+ 0x002000 260 * | Dir1 | * | Dir1 | 261 * +-------------------+ 0x003000 * +-------------------+ 0x003000 262 * | Dir2 | * | Dir2 | 263 * +-------------------+ 0x004000 * +-------------------+ 0x004000 264 * | MIM1 | * | MIM1 | 265 * +-------------------+ 0x130000 * +-------------------+ 0x130000 266 * | MIM2 | * | MIM2 | 267 * +-------------------+ 0x25C000 * +-------------------+ 0x25C000 268 * | Rest Images: | * | Rest Images: | 269 * | TIM1/2 | * | TIM1/2 | 270 * | MFW_TRACE1/2 | * | MFW_TRACE1/2 | 271 * | Eagle/Falcon FW | * | Eagle/Falcon FW | 272 * | PCIE/AVS FW | * | PCIE/AVS FW | 273 * | MBA/CCM/L2B | * | MBA/CCM/L2B | 274 * | VPD | * | VPD | 275 * | optic_modules | * +-------------------+ Flash end - 0x1000 276 * | ... | * | Backup Key Chain | 277 * +-------------------+ 0x400000 * +-------------------+ Flash end 278*/ 279struct nvm_image { 280/*********** !!! FIXED SECTIONS !!! DO NOT MODIFY !!! **********************/ 281 /* NVM Offset (size) */ 282 struct legacy_bootstrap_region bootstrap; /* 0x000000 (0x000014) */ 283 u8 rsrv[NVM_RSV_SIZE]; /* 0x000014 (0x00002c) */ 284 u8 lim_image[LIM_MAX_SIZE]; /* 0x000040 (0x001fc0) */ 285 union nvm_dir_union dir[MAX_MFW_BUNDLES]; /* 0x002000 (0x001000)x2 */ 286 /* MIM1_IMAGE 0x004000 (0x12c000) */ 287 /* MIM2_IMAGE 0x130000 (0x12c000) */ 288/*********** !!! FIXED SECTIONS !!! DO NOT MODIFY !!! **********************/ 289}; /* 0x134 */ 290 291#define NVM_OFFSET(f) ((u32_t)((int_ptr_t)(&(((struct nvm_image*)0)->f)))) 292 293struct hw_set_info { 294 u32 reg_type; 295#define GRC_REG_TYPE 1 296#define PHY_REG_TYPE 2 297#define PCI_REG_TYPE 4 298 299 u32 bank_num; 300 u32 pf_num; 301 u32 operation; 302#define READ_OP 1 303#define WRITE_OP 2 304#define RMW_SET_OP 3 305#define RMW_CLR_OP 4 306 307 u32 reg_addr; 308 u32 reg_data; 309 310 u32 reset_type; 311#define POR_RESET_TYPE (1 << 0) 312#define HARD_RESET_TYPE (1 << 1) 313#define CORE_RESET_TYPE (1 << 2) 314#define MCP_RESET_TYPE (1 << 3) 315#define PERSET_ASSERT (1 << 4) 316#define PERSET_DEASSERT (1 << 5) 317 318}; 319 320struct hw_set_image { 321 u32 format_version; 322#define HW_SET_IMAGE_VERSION 1 323 u32 no_hw_sets; 324 /* This array length depends on the no_hw_sets */ 325 struct hw_set_info hw_sets[1]; 326}; 327 328#endif //NVM_MAP_H 329