1/****************************************************************************** 2 SPDX-License-Identifier: BSD-3-Clause 3 4 Copyright (c) 2001-2020, Intel Corporation 5 All rights reserved. 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of the Intel Corporation nor the names of its 18 contributors may be used to endorse or promote products derived from 19 this software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33******************************************************************************/ 34 35#ifndef _E1000_HW_H_ 36#define _E1000_HW_H_ 37 38#include "e1000_osdep.h" 39#include "e1000_regs.h" 40#include "e1000_defines.h" 41 42struct e1000_hw; 43 44#define E1000_DEV_ID_82542 0x1000 45#define E1000_DEV_ID_82543GC_FIBER 0x1001 46#define E1000_DEV_ID_82543GC_COPPER 0x1004 47#define E1000_DEV_ID_82544EI_COPPER 0x1008 48#define E1000_DEV_ID_82544EI_FIBER 0x1009 49#define E1000_DEV_ID_82544GC_COPPER 0x100C 50#define E1000_DEV_ID_82544GC_LOM 0x100D 51#define E1000_DEV_ID_82540EM 0x100E 52#define E1000_DEV_ID_82540EM_LOM 0x1015 53#define E1000_DEV_ID_82540EP_LOM 0x1016 54#define E1000_DEV_ID_82540EP 0x1017 55#define E1000_DEV_ID_82540EP_LP 0x101E 56#define E1000_DEV_ID_82545EM_COPPER 0x100F 57#define E1000_DEV_ID_82545EM_FIBER 0x1011 58#define E1000_DEV_ID_82545GM_COPPER 0x1026 59#define E1000_DEV_ID_82545GM_FIBER 0x1027 60#define E1000_DEV_ID_82545GM_SERDES 0x1028 61#define E1000_DEV_ID_82546EB_COPPER 0x1010 62#define E1000_DEV_ID_82546EB_FIBER 0x1012 63#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D 64#define E1000_DEV_ID_82546GB_COPPER 0x1079 65#define E1000_DEV_ID_82546GB_FIBER 0x107A 66#define E1000_DEV_ID_82546GB_SERDES 0x107B 67#define E1000_DEV_ID_82546GB_PCIE 0x108A 68#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 69#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 70#define E1000_DEV_ID_82541EI 0x1013 71#define E1000_DEV_ID_82541EI_MOBILE 0x1018 72#define E1000_DEV_ID_82541ER_LOM 0x1014 73#define E1000_DEV_ID_82541ER 0x1078 74#define E1000_DEV_ID_82541GI 0x1076 75#define E1000_DEV_ID_82541GI_LF 0x107C 76#define E1000_DEV_ID_82541GI_MOBILE 0x1077 77#define E1000_DEV_ID_82547EI 0x1019 78#define E1000_DEV_ID_82547EI_MOBILE 0x101A 79#define E1000_DEV_ID_82547GI 0x1075 80#define E1000_DEV_ID_82571EB_COPPER 0x105E 81#define E1000_DEV_ID_82571EB_FIBER 0x105F 82#define E1000_DEV_ID_82571EB_SERDES 0x1060 83#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 84#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA 85#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 86#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 87#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 88#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC 89#define E1000_DEV_ID_82572EI_COPPER 0x107D 90#define E1000_DEV_ID_82572EI_FIBER 0x107E 91#define E1000_DEV_ID_82572EI_SERDES 0x107F 92#define E1000_DEV_ID_82572EI 0x10B9 93#define E1000_DEV_ID_82573E 0x108B 94#define E1000_DEV_ID_82573E_IAMT 0x108C 95#define E1000_DEV_ID_82573L 0x109A 96#define E1000_DEV_ID_82574L 0x10D3 97#define E1000_DEV_ID_82574LA 0x10F6 98#define E1000_DEV_ID_82583V 0x150C 99#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 100#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 101#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA 102#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB 103#define E1000_DEV_ID_ICH8_82567V_3 0x1501 104#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 105#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 106#define E1000_DEV_ID_ICH8_IGP_C 0x104B 107#define E1000_DEV_ID_ICH8_IFE 0x104C 108#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 109#define E1000_DEV_ID_ICH8_IFE_G 0x10C5 110#define E1000_DEV_ID_ICH8_IGP_M 0x104D 111#define E1000_DEV_ID_ICH9_IGP_M 0x10BF 112#define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 113#define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB 114#define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD 115#define E1000_DEV_ID_ICH9_BM 0x10E5 116#define E1000_DEV_ID_ICH9_IGP_C 0x294C 117#define E1000_DEV_ID_ICH9_IFE 0x10C0 118#define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 119#define E1000_DEV_ID_ICH9_IFE_G 0x10C2 120#define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC 121#define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD 122#define E1000_DEV_ID_ICH10_R_BM_V 0x10CE 123#define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE 124#define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF 125#define E1000_DEV_ID_ICH10_D_BM_V 0x1525 126#define E1000_DEV_ID_PCH_M_HV_LM 0x10EA 127#define E1000_DEV_ID_PCH_M_HV_LC 0x10EB 128#define E1000_DEV_ID_PCH_D_HV_DM 0x10EF 129#define E1000_DEV_ID_PCH_D_HV_DC 0x10F0 130#define E1000_DEV_ID_PCH2_LV_LM 0x1502 131#define E1000_DEV_ID_PCH2_LV_V 0x1503 132#define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A 133#define E1000_DEV_ID_PCH_LPT_I217_V 0x153B 134#define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A 135#define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559 136#define E1000_DEV_ID_PCH_I218_LM2 0x15A0 137#define E1000_DEV_ID_PCH_I218_V2 0x15A1 138#define E1000_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */ 139#define E1000_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */ 140#define E1000_DEV_ID_PCH_SPT_I219_LM 0x156F /* Sunrise Point PCH */ 141#define E1000_DEV_ID_PCH_SPT_I219_V 0x1570 /* Sunrise Point PCH */ 142#define E1000_DEV_ID_PCH_SPT_I219_LM2 0x15B7 /* Sunrise Point-H PCH */ 143#define E1000_DEV_ID_PCH_SPT_I219_V2 0x15B8 /* Sunrise Point-H PCH */ 144#define E1000_DEV_ID_PCH_LBG_I219_LM3 0x15B9 /* LEWISBURG PCH */ 145#define E1000_DEV_ID_PCH_SPT_I219_LM4 0x15D7 146#define E1000_DEV_ID_PCH_SPT_I219_V4 0x15D8 147#define E1000_DEV_ID_PCH_SPT_I219_LM5 0x15E3 148#define E1000_DEV_ID_PCH_SPT_I219_V5 0x15D6 149#define E1000_DEV_ID_PCH_CNP_I219_LM6 0x15BD 150#define E1000_DEV_ID_PCH_CNP_I219_V6 0x15BE 151#define E1000_DEV_ID_PCH_CNP_I219_LM7 0x15BB 152#define E1000_DEV_ID_PCH_CNP_I219_V7 0x15BC 153#define E1000_DEV_ID_PCH_ICP_I219_LM8 0x15DF 154#define E1000_DEV_ID_PCH_ICP_I219_V8 0x15E0 155#define E1000_DEV_ID_PCH_ICP_I219_LM9 0x15E1 156#define E1000_DEV_ID_PCH_ICP_I219_V9 0x15E2 157#define E1000_DEV_ID_PCH_CMP_I219_LM10 0x0D4E 158#define E1000_DEV_ID_PCH_CMP_I219_V10 0x0D4F 159#define E1000_DEV_ID_PCH_CMP_I219_LM11 0x0D4C 160#define E1000_DEV_ID_PCH_CMP_I219_V11 0x0D4D 161#define E1000_DEV_ID_PCH_CMP_I219_LM12 0x0D53 162#define E1000_DEV_ID_PCH_CMP_I219_V12 0x0D55 163#define E1000_DEV_ID_PCH_TGP_I219_LM13 0x15FB 164#define E1000_DEV_ID_PCH_TGP_I219_V13 0x15FC 165#define E1000_DEV_ID_PCH_TGP_I219_LM14 0x15F9 166#define E1000_DEV_ID_PCH_TGP_I219_V14 0x15FA 167#define E1000_DEV_ID_PCH_TGP_I219_LM15 0x15F4 168#define E1000_DEV_ID_PCH_TGP_I219_V15 0x15F5 169#define E1000_DEV_ID_PCH_ADL_I219_LM16 0x1A1E 170#define E1000_DEV_ID_PCH_ADL_I219_V16 0x1A1F 171#define E1000_DEV_ID_PCH_ADL_I219_LM17 0x1A1C 172#define E1000_DEV_ID_PCH_ADL_I219_V17 0x1A1D 173#define E1000_DEV_ID_PCH_MTP_I219_LM18 0x550A 174#define E1000_DEV_ID_PCH_MTP_I219_V18 0x550B 175#define E1000_DEV_ID_PCH_MTP_I219_LM19 0x550C 176#define E1000_DEV_ID_PCH_MTP_I219_V19 0x550D 177#define E1000_DEV_ID_PCH_LNL_I219_LM20 0x550E 178#define E1000_DEV_ID_PCH_LNL_I219_V20 0x550F 179#define E1000_DEV_ID_PCH_LNL_I219_LM21 0x5510 180#define E1000_DEV_ID_PCH_LNL_I219_V21 0x5511 181#define E1000_DEV_ID_PCH_RPL_I219_LM22 0x0DC7 182#define E1000_DEV_ID_PCH_RPL_I219_V22 0x0DC8 183#define E1000_DEV_ID_PCH_RPL_I219_LM23 0x0DC5 184#define E1000_DEV_ID_PCH_RPL_I219_V23 0x0DC6 185#define E1000_DEV_ID_PCH_ARL_I219_LM24 0x57A0 186#define E1000_DEV_ID_PCH_ARL_I219_V24 0x57A1 187#define E1000_DEV_ID_PCH_PTP_I219_LM25 0x57B3 188#define E1000_DEV_ID_PCH_PTP_I219_V25 0x57B4 189#define E1000_DEV_ID_PCH_PTP_I219_LM26 0x57B5 190#define E1000_DEV_ID_PCH_PTP_I219_V26 0x57B6 191#define E1000_DEV_ID_PCH_PTP_I219_LM27 0x57B7 192#define E1000_DEV_ID_PCH_PTP_I219_V27 0x57B8 193#define E1000_DEV_ID_82576 0x10C9 194#define E1000_DEV_ID_82576_FIBER 0x10E6 195#define E1000_DEV_ID_82576_SERDES 0x10E7 196#define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8 197#define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526 198#define E1000_DEV_ID_82576_NS 0x150A 199#define E1000_DEV_ID_82576_NS_SERDES 0x1518 200#define E1000_DEV_ID_82576_SERDES_QUAD 0x150D 201#define E1000_DEV_ID_82576_VF 0x10CA 202#define E1000_DEV_ID_82576_VF_HV 0x152D 203#define E1000_DEV_ID_I350_VF 0x1520 204#define E1000_DEV_ID_I350_VF_HV 0x152F 205#define E1000_DEV_ID_82575EB_COPPER 0x10A7 206#define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 207#define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 208#define E1000_DEV_ID_82580_COPPER 0x150E 209#define E1000_DEV_ID_82580_FIBER 0x150F 210#define E1000_DEV_ID_82580_SERDES 0x1510 211#define E1000_DEV_ID_82580_SGMII 0x1511 212#define E1000_DEV_ID_82580_COPPER_DUAL 0x1516 213#define E1000_DEV_ID_82580_QUAD_FIBER 0x1527 214#define E1000_DEV_ID_I350_COPPER 0x1521 215#define E1000_DEV_ID_I350_FIBER 0x1522 216#define E1000_DEV_ID_I350_SERDES 0x1523 217#define E1000_DEV_ID_I350_SGMII 0x1524 218#define E1000_DEV_ID_I350_DA4 0x1546 219#define E1000_DEV_ID_I210_COPPER 0x1533 220#define E1000_DEV_ID_I210_COPPER_OEM1 0x1534 221#define E1000_DEV_ID_I210_COPPER_IT 0x1535 222#define E1000_DEV_ID_I210_FIBER 0x1536 223#define E1000_DEV_ID_I210_SERDES 0x1537 224#define E1000_DEV_ID_I210_SGMII 0x1538 225#define E1000_DEV_ID_I210_COPPER_FLASHLESS 0x157B 226#define E1000_DEV_ID_I210_SERDES_FLASHLESS 0x157C 227#define E1000_DEV_ID_I210_SGMII_FLASHLESS 0x15F6 228#define E1000_DEV_ID_I211_COPPER 0x1539 229#define E1000_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40 230#define E1000_DEV_ID_I354_SGMII 0x1F41 231#define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS 0x1F45 232#define E1000_DEV_ID_DH89XXCC_SGMII 0x0438 233#define E1000_DEV_ID_DH89XXCC_SERDES 0x043A 234#define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C 235#define E1000_DEV_ID_DH89XXCC_SFP 0x0440 236 237#define E1000_REVISION_0 0 238#define E1000_REVISION_1 1 239#define E1000_REVISION_2 2 240#define E1000_REVISION_3 3 241#define E1000_REVISION_4 4 242 243#define E1000_FUNC_0 0 244#define E1000_FUNC_1 1 245#define E1000_FUNC_2 2 246#define E1000_FUNC_3 3 247 248#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 249#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 250#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6 251#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9 252 253enum e1000_mac_type { 254 e1000_undefined = 0, 255 e1000_82542, 256 e1000_82543, 257 e1000_82544, 258 e1000_82540, 259 e1000_82545, 260 e1000_82545_rev_3, 261 e1000_82546, 262 e1000_82546_rev_3, 263 e1000_82541, 264 e1000_82541_rev_2, 265 e1000_82547, 266 e1000_82547_rev_2, 267 e1000_82571, 268 e1000_82572, 269 e1000_82573, 270 e1000_82574, 271 e1000_82583, 272 e1000_80003es2lan, 273 e1000_ich8lan, 274 e1000_ich9lan, 275 e1000_ich10lan, 276 e1000_pchlan, 277 e1000_pch2lan, 278 e1000_pch_lpt, 279 e1000_pch_spt, 280 e1000_pch_cnp, 281 e1000_pch_tgp, 282 e1000_pch_adp, 283 e1000_pch_mtp, 284 e1000_pch_ptp, 285 e1000_82575, 286 e1000_82576, 287 e1000_82580, 288 e1000_i350, 289 e1000_i354, 290 e1000_i210, 291 e1000_i211, 292 e1000_vfadapt, 293 e1000_vfadapt_i350, 294 e1000_num_macs /* List is 1-based, so subtract 1 for true count. */ 295}; 296 297enum e1000_media_type { 298 e1000_media_type_unknown = 0, 299 e1000_media_type_copper = 1, 300 e1000_media_type_fiber = 2, 301 e1000_media_type_internal_serdes = 3, 302 e1000_num_media_types 303}; 304 305enum e1000_nvm_type { 306 e1000_nvm_unknown = 0, 307 e1000_nvm_none, 308 e1000_nvm_eeprom_spi, 309 e1000_nvm_eeprom_microwire, 310 e1000_nvm_flash_hw, 311 e1000_nvm_invm, 312 e1000_nvm_flash_sw 313}; 314 315enum e1000_nvm_override { 316 e1000_nvm_override_none = 0, 317 e1000_nvm_override_spi_small, 318 e1000_nvm_override_spi_large, 319 e1000_nvm_override_microwire_small, 320 e1000_nvm_override_microwire_large 321}; 322 323enum e1000_phy_type { 324 e1000_phy_unknown = 0, 325 e1000_phy_none, 326 e1000_phy_m88, 327 e1000_phy_igp, 328 e1000_phy_igp_2, 329 e1000_phy_gg82563, 330 e1000_phy_igp_3, 331 e1000_phy_ife, 332 e1000_phy_bm, 333 e1000_phy_82578, 334 e1000_phy_82577, 335 e1000_phy_82579, 336 e1000_phy_i217, 337 e1000_phy_82580, 338 e1000_phy_vf, 339 e1000_phy_i210, 340}; 341 342enum e1000_bus_type { 343 e1000_bus_type_unknown = 0, 344 e1000_bus_type_pci, 345 e1000_bus_type_pcix, 346 e1000_bus_type_pci_express, 347 e1000_bus_type_reserved 348}; 349 350enum e1000_bus_speed { 351 e1000_bus_speed_unknown = 0, 352 e1000_bus_speed_33, 353 e1000_bus_speed_66, 354 e1000_bus_speed_100, 355 e1000_bus_speed_120, 356 e1000_bus_speed_133, 357 e1000_bus_speed_2500, 358 e1000_bus_speed_5000, 359 e1000_bus_speed_reserved 360}; 361 362enum e1000_bus_width { 363 e1000_bus_width_unknown = 0, 364 e1000_bus_width_pcie_x1, 365 e1000_bus_width_pcie_x2, 366 e1000_bus_width_pcie_x4 = 4, 367 e1000_bus_width_pcie_x8 = 8, 368 e1000_bus_width_32, 369 e1000_bus_width_64, 370 e1000_bus_width_reserved 371}; 372 373enum e1000_1000t_rx_status { 374 e1000_1000t_rx_status_not_ok = 0, 375 e1000_1000t_rx_status_ok, 376 e1000_1000t_rx_status_undefined = 0xFF 377}; 378 379enum e1000_rev_polarity { 380 e1000_rev_polarity_normal = 0, 381 e1000_rev_polarity_reversed, 382 e1000_rev_polarity_undefined = 0xFF 383}; 384 385enum e1000_fc_mode { 386 e1000_fc_none = 0, 387 e1000_fc_rx_pause, 388 e1000_fc_tx_pause, 389 e1000_fc_full, 390 e1000_fc_default = 0xFF 391}; 392 393enum e1000_ffe_config { 394 e1000_ffe_config_enabled = 0, 395 e1000_ffe_config_active, 396 e1000_ffe_config_blocked 397}; 398 399enum e1000_dsp_config { 400 e1000_dsp_config_disabled = 0, 401 e1000_dsp_config_enabled, 402 e1000_dsp_config_activated, 403 e1000_dsp_config_undefined = 0xFF 404}; 405 406enum e1000_ms_type { 407 e1000_ms_hw_default = 0, 408 e1000_ms_force_master, 409 e1000_ms_force_slave, 410 e1000_ms_auto 411}; 412 413enum e1000_smart_speed { 414 e1000_smart_speed_default = 0, 415 e1000_smart_speed_on, 416 e1000_smart_speed_off 417}; 418 419enum e1000_serdes_link_state { 420 e1000_serdes_link_down = 0, 421 e1000_serdes_link_autoneg_progress, 422 e1000_serdes_link_autoneg_complete, 423 e1000_serdes_link_forced_up 424}; 425 426#define __le16 u16 427#define __le32 u32 428#define __le64 u64 429/* Receive Descriptor */ 430struct e1000_rx_desc { 431 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 432 __le16 length; /* Length of data DMAed into data buffer */ 433 __le16 csum; /* Packet checksum */ 434 u8 status; /* Descriptor status */ 435 u8 errors; /* Descriptor Errors */ 436 __le16 special; 437}; 438 439/* Receive Descriptor - Extended */ 440union e1000_rx_desc_extended { 441 struct { 442 __le64 buffer_addr; 443 __le64 reserved; 444 } read; 445 struct { 446 struct { 447 __le32 mrq; /* Multiple Rx Queues */ 448 union { 449 __le32 rss; /* RSS Hash */ 450 struct { 451 __le16 ip_id; /* IP id */ 452 __le16 csum; /* Packet Checksum */ 453 } csum_ip; 454 } hi_dword; 455 } lower; 456 struct { 457 __le32 status_error; /* ext status/error */ 458 __le16 length; 459 __le16 vlan; /* VLAN tag */ 460 } upper; 461 } wb; /* writeback */ 462}; 463 464#define MAX_PS_BUFFERS 4 465 466/* Number of packet split data buffers (not including the header buffer) */ 467#define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1) 468 469/* Receive Descriptor - Packet Split */ 470union e1000_rx_desc_packet_split { 471 struct { 472 /* one buffer for protocol header(s), three data buffers */ 473 __le64 buffer_addr[MAX_PS_BUFFERS]; 474 } read; 475 struct { 476 struct { 477 __le32 mrq; /* Multiple Rx Queues */ 478 union { 479 __le32 rss; /* RSS Hash */ 480 struct { 481 __le16 ip_id; /* IP id */ 482 __le16 csum; /* Packet Checksum */ 483 } csum_ip; 484 } hi_dword; 485 } lower; 486 struct { 487 __le32 status_error; /* ext status/error */ 488 __le16 length0; /* length of buffer 0 */ 489 __le16 vlan; /* VLAN tag */ 490 } middle; 491 struct { 492 __le16 header_status; 493 /* length of buffers 1-3 */ 494 __le16 length[PS_PAGE_BUFFERS]; 495 } upper; 496 __le64 reserved; 497 } wb; /* writeback */ 498}; 499 500/* Transmit Descriptor */ 501struct e1000_tx_desc { 502 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 503 union { 504 __le32 data; 505 struct { 506 __le16 length; /* Data buffer length */ 507 u8 cso; /* Checksum offset */ 508 u8 cmd; /* Descriptor control */ 509 } flags; 510 } lower; 511 union { 512 __le32 data; 513 struct { 514 u8 status; /* Descriptor status */ 515 u8 css; /* Checksum start */ 516 __le16 special; 517 } fields; 518 } upper; 519}; 520 521/* Offload Context Descriptor */ 522struct e1000_context_desc { 523 union { 524 __le32 ip_config; 525 struct { 526 u8 ipcss; /* IP checksum start */ 527 u8 ipcso; /* IP checksum offset */ 528 __le16 ipcse; /* IP checksum end */ 529 } ip_fields; 530 } lower_setup; 531 union { 532 __le32 tcp_config; 533 struct { 534 u8 tucss; /* TCP checksum start */ 535 u8 tucso; /* TCP checksum offset */ 536 __le16 tucse; /* TCP checksum end */ 537 } tcp_fields; 538 } upper_setup; 539 __le32 cmd_and_length; 540 union { 541 __le32 data; 542 struct { 543 u8 status; /* Descriptor status */ 544 u8 hdr_len; /* Header length */ 545 __le16 mss; /* Maximum segment size */ 546 } fields; 547 } tcp_seg_setup; 548}; 549 550/* Offload data descriptor */ 551struct e1000_data_desc { 552 __le64 buffer_addr; /* Address of the descriptor's buffer address */ 553 union { 554 __le32 data; 555 struct { 556 __le16 length; /* Data buffer length */ 557 u8 typ_len_ext; 558 u8 cmd; 559 } flags; 560 } lower; 561 union { 562 __le32 data; 563 struct { 564 u8 status; /* Descriptor status */ 565 u8 popts; /* Packet Options */ 566 __le16 special; 567 } fields; 568 } upper; 569}; 570 571/* Statistics counters collected by the MAC */ 572struct e1000_hw_stats { 573 u64 crcerrs; 574 u64 algnerrc; 575 u64 symerrs; 576 u64 rxerrc; 577 u64 mpc; 578 u64 scc; 579 u64 ecol; 580 u64 mcc; 581 u64 latecol; 582 u64 colc; 583 u64 dc; 584 u64 tncrs; 585 u64 sec; 586 u64 cexterr; 587 u64 rlec; 588 u64 xonrxc; 589 u64 xontxc; 590 u64 xoffrxc; 591 u64 xofftxc; 592 u64 fcruc; 593 u64 prc64; 594 u64 prc127; 595 u64 prc255; 596 u64 prc511; 597 u64 prc1023; 598 u64 prc1522; 599 u64 gprc; 600 u64 bprc; 601 u64 mprc; 602 u64 gptc; 603 u64 gorc; 604 u64 gotc; 605 u64 rnbc; 606 u64 ruc; 607 u64 rfc; 608 u64 roc; 609 u64 rjc; 610 u64 mgprc; 611 u64 mgpdc; 612 u64 mgptc; 613 u64 tor; 614 u64 tot; 615 u64 tpr; 616 u64 tpt; 617 u64 ptc64; 618 u64 ptc127; 619 u64 ptc255; 620 u64 ptc511; 621 u64 ptc1023; 622 u64 ptc1522; 623 u64 mptc; 624 u64 bptc; 625 u64 tsctc; 626 u64 tsctfc; 627 u64 iac; 628 u64 icrxptc; 629 u64 icrxatc; 630 u64 ictxptc; 631 u64 ictxatc; 632 u64 ictxqec; 633 u64 ictxqmtc; 634 u64 icrxdmtc; 635 u64 icrxoc; 636 u64 cbtmpc; 637 u64 htdpmc; 638 u64 cbrdpc; 639 u64 cbrmpc; 640 u64 rpthc; 641 u64 hgptc; 642 u64 htcbdpc; 643 u64 hgorc; 644 u64 hgotc; 645 u64 lenerrs; 646 u64 scvpc; 647 u64 hrmpc; 648 u64 doosync; 649 u64 o2bgptc; 650 u64 o2bspc; 651 u64 b2ospc; 652 u64 b2ogprc; 653}; 654 655struct e1000_vf_stats { 656 u64 base_gprc; 657 u64 base_gptc; 658 u64 base_gorc; 659 u64 base_gotc; 660 u64 base_mprc; 661 u64 base_gotlbc; 662 u64 base_gptlbc; 663 u64 base_gorlbc; 664 u64 base_gprlbc; 665 666 u32 last_gprc; 667 u32 last_gptc; 668 u32 last_gorc; 669 u32 last_gotc; 670 u32 last_mprc; 671 u32 last_gotlbc; 672 u32 last_gptlbc; 673 u32 last_gorlbc; 674 u32 last_gprlbc; 675 676 u64 gprc; 677 u64 gptc; 678 u64 gorc; 679 u64 gotc; 680 u64 mprc; 681 u64 gotlbc; 682 u64 gptlbc; 683 u64 gorlbc; 684 u64 gprlbc; 685}; 686 687struct e1000_phy_stats { 688 u32 idle_errors; 689 u32 receive_errors; 690}; 691 692struct e1000_host_mng_dhcp_cookie { 693 u32 signature; 694 u8 status; 695 u8 reserved0; 696 u16 vlan_id; 697 u32 reserved1; 698 u16 reserved2; 699 u8 reserved3; 700 u8 checksum; 701}; 702 703/* Host Interface "Rev 1" */ 704struct e1000_host_command_header { 705 u8 command_id; 706 u8 command_length; 707 u8 command_options; 708 u8 checksum; 709}; 710 711#define E1000_HI_MAX_DATA_LENGTH 252 712struct e1000_host_command_info { 713 struct e1000_host_command_header command_header; 714 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; 715}; 716 717/* Host Interface "Rev 2" */ 718struct e1000_host_mng_command_header { 719 u8 command_id; 720 u8 checksum; 721 u16 reserved1; 722 u16 reserved2; 723 u16 command_length; 724}; 725 726#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 727struct e1000_host_mng_command_info { 728 struct e1000_host_mng_command_header command_header; 729 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; 730}; 731 732#include "e1000_mac.h" 733#include "e1000_phy.h" 734#include "e1000_nvm.h" 735#include "e1000_manage.h" 736#include "e1000_mbx.h" 737 738/* Function pointers for the MAC. */ 739struct e1000_mac_operations { 740 s32 (*init_params)(struct e1000_hw *); 741 s32 (*id_led_init)(struct e1000_hw *); 742 s32 (*blink_led)(struct e1000_hw *); 743 bool (*check_mng_mode)(struct e1000_hw *); 744 s32 (*check_for_link)(struct e1000_hw *); 745 s32 (*cleanup_led)(struct e1000_hw *); 746 void (*clear_hw_cntrs)(struct e1000_hw *); 747 void (*clear_vfta)(struct e1000_hw *); 748 s32 (*get_bus_info)(struct e1000_hw *); 749 void (*set_lan_id)(struct e1000_hw *); 750 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 751 s32 (*led_on)(struct e1000_hw *); 752 s32 (*led_off)(struct e1000_hw *); 753 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); 754 s32 (*reset_hw)(struct e1000_hw *); 755 s32 (*init_hw)(struct e1000_hw *); 756 void (*shutdown_serdes)(struct e1000_hw *); 757 void (*power_up_serdes)(struct e1000_hw *); 758 s32 (*setup_link)(struct e1000_hw *); 759 s32 (*setup_physical_interface)(struct e1000_hw *); 760 s32 (*setup_led)(struct e1000_hw *); 761 void (*write_vfta)(struct e1000_hw *, u32, u32); 762 void (*config_collision_dist)(struct e1000_hw *); 763 int (*rar_set)(struct e1000_hw *, u8*, u32); 764 s32 (*read_mac_addr)(struct e1000_hw *); 765 s32 (*validate_mdi_setting)(struct e1000_hw *); 766 s32 (*set_obff_timer)(struct e1000_hw *, u32); 767 s32 (*acquire_swfw_sync)(struct e1000_hw *, u16); 768 void (*release_swfw_sync)(struct e1000_hw *, u16); 769}; 770 771/* When to use various PHY register access functions: 772 * 773 * Func Caller 774 * Function Does Does When to use 775 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 776 * X_reg L,P,A n/a for simple PHY reg accesses 777 * X_reg_locked P,A L for multiple accesses of different regs 778 * on different pages 779 * X_reg_page A L,P for multiple accesses of different regs 780 * on the same page 781 * 782 * Where X=[read|write], L=locking, P=sets page, A=register access 783 * 784 */ 785struct e1000_phy_operations { 786 s32 (*init_params)(struct e1000_hw *); 787 s32 (*acquire)(struct e1000_hw *); 788 s32 (*cfg_on_link_up)(struct e1000_hw *); 789 s32 (*check_polarity)(struct e1000_hw *); 790 s32 (*check_reset_block)(struct e1000_hw *); 791 s32 (*commit)(struct e1000_hw *); 792 s32 (*force_speed_duplex)(struct e1000_hw *); 793 s32 (*get_cfg_done)(struct e1000_hw *hw); 794 s32 (*get_cable_length)(struct e1000_hw *); 795 s32 (*get_info)(struct e1000_hw *); 796 s32 (*set_page)(struct e1000_hw *, u16); 797 s32 (*read_reg)(struct e1000_hw *, u32, u16 *); 798 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *); 799 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *); 800 void (*release)(struct e1000_hw *); 801 s32 (*reset)(struct e1000_hw *); 802 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); 803 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); 804 s32 (*write_reg)(struct e1000_hw *, u32, u16); 805 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16); 806 s32 (*write_reg_page)(struct e1000_hw *, u32, u16); 807 void (*power_up)(struct e1000_hw *); 808 void (*power_down)(struct e1000_hw *); 809 s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *); 810 s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8); 811}; 812 813/* Function pointers for the NVM. */ 814struct e1000_nvm_operations { 815 s32 (*init_params)(struct e1000_hw *); 816 s32 (*acquire)(struct e1000_hw *); 817 s32 (*read)(struct e1000_hw *, u16, u16, u16 *); 818 void (*release)(struct e1000_hw *); 819 void (*reload)(struct e1000_hw *); 820 s32 (*update)(struct e1000_hw *); 821 s32 (*valid_led_default)(struct e1000_hw *, u16 *); 822 s32 (*validate)(struct e1000_hw *); 823 s32 (*write)(struct e1000_hw *, u16, u16, u16 *); 824}; 825 826struct e1000_mac_info { 827 struct e1000_mac_operations ops; 828 u8 addr[ETHER_ADDR_LEN]; 829 u8 perm_addr[ETHER_ADDR_LEN]; 830 831 enum e1000_mac_type type; 832 833 u32 collision_delta; 834 u32 ledctl_default; 835 u32 ledctl_mode1; 836 u32 ledctl_mode2; 837 u32 mc_filter_type; 838 u32 tx_packet_delta; 839 u32 txcw; 840 841 u16 current_ifs_val; 842 u16 ifs_max_val; 843 u16 ifs_min_val; 844 u16 ifs_ratio; 845 u16 ifs_step_size; 846 u16 mta_reg_count; 847 u16 uta_reg_count; 848 849 /* Maximum size of the MTA register table in all supported adapters */ 850#define MAX_MTA_REG 128 851 u32 mta_shadow[MAX_MTA_REG]; 852 u16 rar_entry_count; 853 854 u8 forced_speed_duplex; 855 856 bool adaptive_ifs; 857 bool has_fwsm; 858 bool arc_subsystem_valid; 859 bool asf_firmware_present; 860 bool autoneg; 861 bool autoneg_failed; 862 bool get_link_status; 863 bool in_ifs_mode; 864 bool report_tx_early; 865 enum e1000_serdes_link_state serdes_link_state; 866 bool serdes_has_link; 867 bool tx_pkt_filtering; 868 u32 max_frame_size; 869}; 870 871struct e1000_phy_info { 872 struct e1000_phy_operations ops; 873 enum e1000_phy_type type; 874 875 enum e1000_1000t_rx_status local_rx; 876 enum e1000_1000t_rx_status remote_rx; 877 enum e1000_ms_type ms_type; 878 enum e1000_ms_type original_ms_type; 879 enum e1000_rev_polarity cable_polarity; 880 enum e1000_smart_speed smart_speed; 881 882 u32 addr; 883 u32 id; 884 u32 reset_delay_us; /* in usec */ 885 u32 revision; 886 887 enum e1000_media_type media_type; 888 889 u16 autoneg_advertised; 890 u16 autoneg_mask; 891 u16 cable_length; 892 u16 max_cable_length; 893 u16 min_cable_length; 894 895 u8 mdix; 896 897 bool disable_polarity_correction; 898 bool is_mdix; 899 bool polarity_correction; 900 bool speed_downgraded; 901 bool autoneg_wait_to_complete; 902}; 903 904struct e1000_nvm_info { 905 struct e1000_nvm_operations ops; 906 enum e1000_nvm_type type; 907 enum e1000_nvm_override override; 908 909 u32 flash_bank_size; 910 u32 flash_base_addr; 911 912 u16 word_size; 913 u16 delay_usec; 914 u16 address_bits; 915 u16 opcode_bits; 916 u16 page_size; 917}; 918 919struct e1000_bus_info { 920 enum e1000_bus_type type; 921 enum e1000_bus_speed speed; 922 enum e1000_bus_width width; 923 924 u16 func; 925 u16 pci_cmd_word; 926}; 927 928struct e1000_fc_info { 929 u32 high_water; /* Flow control high-water mark */ 930 u32 low_water; /* Flow control low-water mark */ 931 u16 pause_time; /* Flow control pause timer */ 932 u16 refresh_time; /* Flow control refresh timer */ 933 bool send_xon; /* Flow control send XON */ 934 bool strict_ieee; /* Strict IEEE mode */ 935 enum e1000_fc_mode current_mode; /* FC mode in effect */ 936 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */ 937}; 938 939struct e1000_mbx_operations { 940 s32 (*init_params)(struct e1000_hw *hw); 941 s32 (*read)(struct e1000_hw *, u32 *, u16, u16); 942 s32 (*write)(struct e1000_hw *, u32 *, u16, u16); 943 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16); 944 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16); 945 s32 (*check_for_msg)(struct e1000_hw *, u16); 946 s32 (*check_for_ack)(struct e1000_hw *, u16); 947 s32 (*check_for_rst)(struct e1000_hw *, u16); 948}; 949 950struct e1000_mbx_stats { 951 u32 msgs_tx; 952 u32 msgs_rx; 953 954 u32 acks; 955 u32 reqs; 956 u32 rsts; 957}; 958 959struct e1000_mbx_info { 960 struct e1000_mbx_operations ops; 961 struct e1000_mbx_stats stats; 962 u32 timeout; 963 u32 usec_delay; 964 u16 size; 965}; 966 967struct e1000_dev_spec_82541 { 968 enum e1000_dsp_config dsp_config; 969 enum e1000_ffe_config ffe_config; 970 u16 spd_default; 971 bool phy_init_script; 972}; 973 974struct e1000_dev_spec_82542 { 975 bool dma_fairness; 976}; 977 978struct e1000_dev_spec_82543 { 979 u32 tbi_compatibility; 980 bool dma_fairness; 981 bool init_phy_disabled; 982}; 983 984struct e1000_dev_spec_82571 { 985 bool laa_is_present; 986 u32 smb_counter; 987}; 988 989struct e1000_dev_spec_80003es2lan { 990 bool mdic_wa_enable; 991}; 992 993struct e1000_shadow_ram { 994 u16 value; 995 bool modified; 996}; 997 998#define E1000_SHADOW_RAM_WORDS 2048 999 1000/* I218 PHY Ultra Low Power (ULP) states */ 1001enum e1000_ulp_state { 1002 e1000_ulp_state_unknown, 1003 e1000_ulp_state_off, 1004 e1000_ulp_state_on, 1005}; 1006 1007struct e1000_dev_spec_ich8lan { 1008 bool kmrn_lock_loss_workaround_enabled; 1009 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS]; 1010 bool nvm_k1_enabled; 1011 bool disable_k1_off; 1012 bool eee_disable; 1013 u16 eee_lp_ability; 1014 enum e1000_ulp_state ulp_state; 1015 bool ulp_capability_disabled; 1016 bool during_suspend_flow; 1017 bool smbus_disable; 1018}; 1019 1020struct e1000_dev_spec_82575 { 1021 bool sgmii_active; 1022 bool global_device_reset; 1023 bool eee_disable; 1024 bool module_plugged; 1025 bool clear_semaphore_once; 1026 u32 mtu; 1027 struct sfp_e1000_flags eth_flags; 1028 u8 media_port; 1029 bool media_changed; 1030}; 1031 1032struct e1000_dev_spec_vf { 1033 u32 vf_number; 1034 u32 v2p_mailbox; 1035}; 1036 1037struct e1000_hw { 1038 void *back; 1039 1040 u8 *hw_addr; 1041 u8 *flash_address; 1042 unsigned long io_base; 1043 1044 struct e1000_mac_info mac; 1045 struct e1000_fc_info fc; 1046 struct e1000_phy_info phy; 1047 struct e1000_nvm_info nvm; 1048 struct e1000_bus_info bus; 1049 struct e1000_mbx_info mbx; 1050 struct e1000_host_mng_dhcp_cookie mng_cookie; 1051 1052 union { 1053 struct e1000_dev_spec_82541 _82541; 1054 struct e1000_dev_spec_82542 _82542; 1055 struct e1000_dev_spec_82543 _82543; 1056 struct e1000_dev_spec_82571 _82571; 1057 struct e1000_dev_spec_80003es2lan _80003es2lan; 1058 struct e1000_dev_spec_ich8lan ich8lan; 1059 struct e1000_dev_spec_82575 _82575; 1060 struct e1000_dev_spec_vf vf; 1061 } dev_spec; 1062 1063 u16 device_id; 1064 u16 subsystem_vendor_id; 1065 u16 subsystem_device_id; 1066 u16 vendor_id; 1067 1068 u8 revision_id; 1069}; 1070 1071#include "e1000_82541.h" 1072#include "e1000_82543.h" 1073#include "e1000_82571.h" 1074#include "e1000_80003es2lan.h" 1075#include "e1000_ich8lan.h" 1076#include "e1000_82575.h" 1077#include "e1000_i210.h" 1078#include "e1000_base.h" 1079 1080/* These functions must be implemented by drivers */ 1081void e1000_pci_clear_mwi(struct e1000_hw *hw); 1082void e1000_pci_set_mwi(struct e1000_hw *hw); 1083s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 1084s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 1085void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 1086void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 1087 1088#endif 1089