1/** 2 * \file drm.h 3 * Header for the Direct Rendering Manager 4 * 5 * \author Rickard E. (Rik) Faith <faith@valinux.com> 6 * 7 * \par Acknowledgments: 8 * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg. 9 */ 10 11/*- 12 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 13 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 14 * All rights reserved. 15 * 16 * Permission is hereby granted, free of charge, to any person obtaining a 17 * copy of this software and associated documentation files (the "Software"), 18 * to deal in the Software without restriction, including without limitation 19 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 20 * and/or sell copies of the Software, and to permit persons to whom the 21 * Software is furnished to do so, subject to the following conditions: 22 * 23 * The above copyright notice and this permission notice (including the next 24 * paragraph) shall be included in all copies or substantial portions of the 25 * Software. 26 * 27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 28 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 29 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 30 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 31 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 32 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 33 * OTHER DEALINGS IN THE SOFTWARE. 34 */ 35 36#include <sys/cdefs.h> 37#ifndef _DRM_H_ 38#define _DRM_H_ 39 40#if defined(__linux__) 41 42#include <linux/types.h> 43#include <asm/ioctl.h> 44typedef unsigned int drm_handle_t; 45 46#else /* One of the BSDs */ 47 48#include <sys/ioccom.h> 49#include <sys/types.h> 50typedef int8_t __s8; 51typedef uint8_t __u8; 52typedef int16_t __s16; 53typedef uint16_t __u16; 54typedef int32_t __s32; 55typedef uint32_t __u32; 56typedef int64_t __s64; 57typedef uint64_t __u64; 58typedef unsigned long drm_handle_t; 59 60#include <dev/drm2/drm_os_freebsd.h> 61#endif 62 63#define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */ 64#define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */ 65#define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */ 66#define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */ 67 68#define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */ 69#define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */ 70#define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD) 71#define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT) 72#define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT)) 73 74typedef unsigned int drm_context_t; 75typedef unsigned int drm_drawable_t; 76typedef unsigned int drm_magic_t; 77 78/** 79 * Cliprect. 80 * 81 * \warning: If you change this structure, make sure you change 82 * XF86DRIClipRectRec in the server as well 83 * 84 * \note KW: Actually it's illegal to change either for 85 * backwards-compatibility reasons. 86 */ 87struct drm_clip_rect { 88 unsigned short x1; 89 unsigned short y1; 90 unsigned short x2; 91 unsigned short y2; 92}; 93 94/** 95 * Drawable information. 96 */ 97struct drm_drawable_info { 98 unsigned int num_rects; 99 struct drm_clip_rect *rects; 100}; 101 102/** 103 * Texture region, 104 */ 105struct drm_tex_region { 106 unsigned char next; 107 unsigned char prev; 108 unsigned char in_use; 109 unsigned char padding; 110 unsigned int age; 111}; 112 113/** 114 * Hardware lock. 115 * 116 * The lock structure is a simple cache-line aligned integer. To avoid 117 * processor bus contention on a multiprocessor system, there should not be any 118 * other data stored in the same cache line. 119 */ 120struct drm_hw_lock { 121 __volatile__ unsigned int lock; /**< lock variable */ 122 char padding[60]; /**< Pad to cache line */ 123}; 124 125/** 126 * DRM_IOCTL_VERSION ioctl argument type. 127 * 128 * \sa drmGetVersion(). 129 */ 130struct drm_version { 131 int version_major; /**< Major version */ 132 int version_minor; /**< Minor version */ 133 int version_patchlevel; /**< Patch level */ 134 size_t name_len; /**< Length of name buffer */ 135 char __user *name; /**< Name of driver */ 136 size_t date_len; /**< Length of date buffer */ 137 char __user *date; /**< User-space buffer to hold date */ 138 size_t desc_len; /**< Length of desc buffer */ 139 char __user *desc; /**< User-space buffer to hold desc */ 140}; 141 142/** 143 * DRM_IOCTL_GET_UNIQUE ioctl argument type. 144 * 145 * \sa drmGetBusid() and drmSetBusId(). 146 */ 147struct drm_unique { 148 size_t unique_len; /**< Length of unique */ 149 char __user *unique; /**< Unique name for driver instantiation */ 150}; 151 152struct drm_list { 153 int count; /**< Length of user-space structures */ 154 struct drm_version __user *version; 155}; 156 157struct drm_block { 158 int unused; 159}; 160 161/** 162 * DRM_IOCTL_CONTROL ioctl argument type. 163 * 164 * \sa drmCtlInstHandler() and drmCtlUninstHandler(). 165 */ 166struct drm_control { 167 enum { 168 DRM_ADD_COMMAND, 169 DRM_RM_COMMAND, 170 DRM_INST_HANDLER, 171 DRM_UNINST_HANDLER 172 } func; 173 int irq; 174}; 175 176/** 177 * Type of memory to map. 178 */ 179enum drm_map_type { 180 _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */ 181 _DRM_REGISTERS = 1, /**< no caching, no core dump */ 182 _DRM_SHM = 2, /**< shared, cached */ 183 _DRM_AGP = 3, /**< AGP/GART */ 184 _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */ 185 _DRM_CONSISTENT = 5, /**< Consistent memory for PCI DMA */ 186 _DRM_GEM = 6, /**< GEM object */ 187}; 188 189/** 190 * Memory mapping flags. 191 */ 192enum drm_map_flags { 193 _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */ 194 _DRM_READ_ONLY = 0x02, 195 _DRM_LOCKED = 0x04, /**< shared, cached, locked */ 196 _DRM_KERNEL = 0x08, /**< kernel requires access */ 197 _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */ 198 _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */ 199 _DRM_REMOVABLE = 0x40, /**< Removable mapping */ 200 _DRM_DRIVER = 0x80 /**< Managed by driver */ 201}; 202 203struct drm_ctx_priv_map { 204 unsigned int ctx_id; /**< Context requesting private mapping */ 205 void *handle; /**< Handle of map */ 206}; 207 208/** 209 * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls 210 * argument type. 211 * 212 * \sa drmAddMap(). 213 */ 214struct drm_map { 215 unsigned long offset; /**< Requested physical address (0 for SAREA)*/ 216 unsigned long size; /**< Requested physical size (bytes) */ 217 enum drm_map_type type; /**< Type of memory to map */ 218 enum drm_map_flags flags; /**< Flags */ 219 void *handle; /**< User-space: "Handle" to pass to mmap() */ 220 /**< Kernel-space: kernel-virtual address */ 221 int mtrr; /**< MTRR slot used */ 222 /* Private data */ 223}; 224 225/** 226 * DRM_IOCTL_GET_CLIENT ioctl argument type. 227 */ 228struct drm_client { 229 int idx; /**< Which client desired? */ 230 int auth; /**< Is client authenticated? */ 231 unsigned long pid; /**< Process ID */ 232 unsigned long uid; /**< User ID */ 233 unsigned long magic; /**< Magic */ 234 unsigned long iocs; /**< Ioctl count */ 235}; 236 237enum drm_stat_type { 238 _DRM_STAT_LOCK, 239 _DRM_STAT_OPENS, 240 _DRM_STAT_CLOSES, 241 _DRM_STAT_IOCTLS, 242 _DRM_STAT_LOCKS, 243 _DRM_STAT_UNLOCKS, 244 _DRM_STAT_VALUE, /**< Generic value */ 245 _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */ 246 _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */ 247 248 _DRM_STAT_IRQ, /**< IRQ */ 249 _DRM_STAT_PRIMARY, /**< Primary DMA bytes */ 250 _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */ 251 _DRM_STAT_DMA, /**< DMA */ 252 _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */ 253 _DRM_STAT_MISSED /**< Missed DMA opportunity */ 254 /* Add to the *END* of the list */ 255}; 256 257/** 258 * DRM_IOCTL_GET_STATS ioctl argument type. 259 */ 260struct drm_stats { 261 unsigned long count; 262 struct { 263 unsigned long value; 264 enum drm_stat_type type; 265 } data[15]; 266}; 267 268/** 269 * Hardware locking flags. 270 */ 271enum drm_lock_flags { 272 _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */ 273 _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */ 274 _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */ 275 _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */ 276 /* These *HALT* flags aren't supported yet 277 -- they will be used to support the 278 full-screen DGA-like mode. */ 279 _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */ 280 _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */ 281}; 282 283/** 284 * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type. 285 * 286 * \sa drmGetLock() and drmUnlock(). 287 */ 288struct drm_lock { 289 int context; 290 enum drm_lock_flags flags; 291}; 292 293/** 294 * DMA flags 295 * 296 * \warning 297 * These values \e must match xf86drm.h. 298 * 299 * \sa drm_dma. 300 */ 301enum drm_dma_flags { 302 /* Flags for DMA buffer dispatch */ 303 _DRM_DMA_BLOCK = 0x01, /**< 304 * Block until buffer dispatched. 305 * 306 * \note The buffer may not yet have 307 * been processed by the hardware -- 308 * getting a hardware lock with the 309 * hardware quiescent will ensure 310 * that the buffer has been 311 * processed. 312 */ 313 _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */ 314 _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */ 315 316 /* Flags for DMA buffer request */ 317 _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */ 318 _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */ 319 _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */ 320}; 321 322/** 323 * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type. 324 * 325 * \sa drmAddBufs(). 326 */ 327struct drm_buf_desc { 328 int count; /**< Number of buffers of this size */ 329 int size; /**< Size in bytes */ 330 int low_mark; /**< Low water mark */ 331 int high_mark; /**< High water mark */ 332 enum { 333 _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */ 334 _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */ 335 _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */ 336 _DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */ 337 _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */ 338 } flags; 339 unsigned long agp_start; /**< 340 * Start address of where the AGP buffers are 341 * in the AGP aperture 342 */ 343}; 344 345/** 346 * DRM_IOCTL_INFO_BUFS ioctl argument type. 347 */ 348struct drm_buf_info { 349 int count; /**< Entries in list */ 350 struct drm_buf_desc __user *list; 351}; 352 353/** 354 * DRM_IOCTL_FREE_BUFS ioctl argument type. 355 */ 356struct drm_buf_free { 357 int count; 358 int __user *list; 359}; 360 361/** 362 * Buffer information 363 * 364 * \sa drm_buf_map. 365 */ 366struct drm_buf_pub { 367 int idx; /**< Index into the master buffer list */ 368 int total; /**< Buffer size */ 369 int used; /**< Amount of buffer in use (for DMA) */ 370 void __user *address; /**< Address of buffer */ 371}; 372 373/** 374 * DRM_IOCTL_MAP_BUFS ioctl argument type. 375 */ 376struct drm_buf_map { 377 int count; /**< Length of the buffer list */ 378 void __user *virtual; /**< Mmap'd area in user-virtual */ 379 struct drm_buf_pub __user *list; /**< Buffer information */ 380}; 381 382/** 383 * DRM_IOCTL_DMA ioctl argument type. 384 * 385 * Indices here refer to the offset into the buffer list in drm_buf_get. 386 * 387 * \sa drmDMA(). 388 */ 389struct drm_dma { 390 int context; /**< Context handle */ 391 int send_count; /**< Number of buffers to send */ 392 int __user *send_indices; /**< List of handles to buffers */ 393 int __user *send_sizes; /**< Lengths of data to send */ 394 enum drm_dma_flags flags; /**< Flags */ 395 int request_count; /**< Number of buffers requested */ 396 int request_size; /**< Desired size for buffers */ 397 int __user *request_indices; /**< Buffer information */ 398 int __user *request_sizes; 399 int granted_count; /**< Number of buffers granted */ 400}; 401 402enum drm_ctx_flags { 403 _DRM_CONTEXT_PRESERVED = 0x01, 404 _DRM_CONTEXT_2DONLY = 0x02 405}; 406 407/** 408 * DRM_IOCTL_ADD_CTX ioctl argument type. 409 * 410 * \sa drmCreateContext() and drmDestroyContext(). 411 */ 412struct drm_ctx { 413 drm_context_t handle; 414 enum drm_ctx_flags flags; 415}; 416 417/** 418 * DRM_IOCTL_RES_CTX ioctl argument type. 419 */ 420struct drm_ctx_res { 421 int count; 422 struct drm_ctx __user *contexts; 423}; 424 425/** 426 * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type. 427 */ 428struct drm_draw { 429 drm_drawable_t handle; 430}; 431 432/** 433 * DRM_IOCTL_UPDATE_DRAW ioctl argument type. 434 */ 435typedef enum { 436 DRM_DRAWABLE_CLIPRECTS, 437} drm_drawable_info_type_t; 438 439struct drm_update_draw { 440 drm_drawable_t handle; 441 unsigned int type; 442 unsigned int num; 443 unsigned long long data; 444}; 445 446/** 447 * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type. 448 */ 449struct drm_auth { 450 drm_magic_t magic; 451}; 452 453/** 454 * DRM_IOCTL_IRQ_BUSID ioctl argument type. 455 * 456 * \sa drmGetInterruptFromBusID(). 457 */ 458struct drm_irq_busid { 459 int irq; /**< IRQ number */ 460 int busnum; /**< bus number */ 461 int devnum; /**< device number */ 462 int funcnum; /**< function number */ 463}; 464 465enum drm_vblank_seq_type { 466 _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */ 467 _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */ 468 /* bits 1-6 are reserved for high crtcs */ 469 _DRM_VBLANK_HIGH_CRTC_MASK = 0x0000003e, 470 _DRM_VBLANK_EVENT = 0x4000000, /**< Send event instead of blocking */ 471 _DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */ 472 _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */ 473 _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */ 474 _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking, unsupported */ 475}; 476#define _DRM_VBLANK_HIGH_CRTC_SHIFT 1 477 478#define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE) 479#define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT | _DRM_VBLANK_SIGNAL | \ 480 _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS) 481 482struct drm_wait_vblank_request { 483 enum drm_vblank_seq_type type; 484 unsigned int sequence; 485 unsigned long signal; 486}; 487 488struct drm_wait_vblank_reply { 489 enum drm_vblank_seq_type type; 490 unsigned int sequence; 491 long tval_sec; 492 long tval_usec; 493}; 494 495/** 496 * DRM_IOCTL_WAIT_VBLANK ioctl argument type. 497 * 498 * \sa drmWaitVBlank(). 499 */ 500union drm_wait_vblank { 501 struct drm_wait_vblank_request request; 502 struct drm_wait_vblank_reply reply; 503}; 504 505#define _DRM_PRE_MODESET 1 506#define _DRM_POST_MODESET 2 507 508/** 509 * DRM_IOCTL_MODESET_CTL ioctl argument type 510 * 511 * \sa drmModesetCtl(). 512 */ 513struct drm_modeset_ctl { 514 __u32 crtc; 515 __u32 cmd; 516}; 517 518/** 519 * DRM_IOCTL_AGP_ENABLE ioctl argument type. 520 * 521 * \sa drmAgpEnable(). 522 */ 523struct drm_agp_mode { 524 unsigned long mode; /**< AGP mode */ 525}; 526 527/** 528 * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type. 529 * 530 * \sa drmAgpAlloc() and drmAgpFree(). 531 */ 532struct drm_agp_buffer { 533 unsigned long size; /**< In bytes -- will round to page boundary */ 534 unsigned long handle; /**< Used for binding / unbinding */ 535 unsigned long type; /**< Type of memory to allocate */ 536 unsigned long physical; /**< Physical used by i810 */ 537}; 538 539/** 540 * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type. 541 * 542 * \sa drmAgpBind() and drmAgpUnbind(). 543 */ 544struct drm_agp_binding { 545 unsigned long handle; /**< From drm_agp_buffer */ 546 unsigned long offset; /**< In bytes -- will round to page boundary */ 547}; 548 549/** 550 * DRM_IOCTL_AGP_INFO ioctl argument type. 551 * 552 * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(), 553 * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(), 554 * drmAgpVendorId() and drmAgpDeviceId(). 555 */ 556struct drm_agp_info { 557 int agp_version_major; 558 int agp_version_minor; 559 unsigned long mode; 560 unsigned long aperture_base; /* physical address */ 561 unsigned long aperture_size; /* bytes */ 562 unsigned long memory_allowed; /* bytes */ 563 unsigned long memory_used; 564 565 /* PCI information */ 566 unsigned short id_vendor; 567 unsigned short id_device; 568}; 569 570/** 571 * DRM_IOCTL_SG_ALLOC ioctl argument type. 572 */ 573struct drm_scatter_gather { 574 unsigned long size; /**< In bytes -- will round to page boundary */ 575 unsigned long handle; /**< Used for mapping / unmapping */ 576}; 577 578/** 579 * DRM_IOCTL_SET_VERSION ioctl argument type. 580 */ 581struct drm_set_version { 582 int drm_di_major; 583 int drm_di_minor; 584 int drm_dd_major; 585 int drm_dd_minor; 586}; 587 588/** DRM_IOCTL_GEM_CLOSE ioctl argument type */ 589struct drm_gem_close { 590 /** Handle of the object to be closed. */ 591 __u32 handle; 592 __u32 pad; 593}; 594 595/** DRM_IOCTL_GEM_FLINK ioctl argument type */ 596struct drm_gem_flink { 597 /** Handle for the object being named */ 598 __u32 handle; 599 600 /** Returned global name */ 601 __u32 name; 602}; 603 604/** DRM_IOCTL_GEM_OPEN ioctl argument type */ 605struct drm_gem_open { 606 /** Name of object being opened */ 607 __u32 name; 608 609 /** Returned handle for the object */ 610 __u32 handle; 611 612 /** Returned size of the object */ 613 __u64 size; 614}; 615 616/** DRM_IOCTL_GET_CAP ioctl argument type */ 617struct drm_get_cap { 618 __u64 capability; 619 __u64 value; 620}; 621 622#define DRM_CLOEXEC O_CLOEXEC 623struct drm_prime_handle { 624 __u32 handle; 625 626 /** Flags.. only applicable for handle->fd */ 627 __u32 flags; 628 629 /** Returned dmabuf file descriptor */ 630 __s32 fd; 631}; 632 633#include <dev/drm2/drm_mode.h> 634 635#define DRM_IOCTL_BASE 'd' 636#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr) 637#define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type) 638#define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type) 639#define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type) 640 641#define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version) 642#define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, struct drm_unique) 643#define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, struct drm_auth) 644#define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, struct drm_irq_busid) 645#define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map) 646#define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client) 647#define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats) 648#define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version) 649#define DRM_IOCTL_MODESET_CTL DRM_IOW(0x08, struct drm_modeset_ctl) 650#define DRM_IOCTL_GEM_CLOSE DRM_IOW (0x09, struct drm_gem_close) 651#define DRM_IOCTL_GEM_FLINK DRM_IOWR(0x0a, struct drm_gem_flink) 652#define DRM_IOCTL_GEM_OPEN DRM_IOWR(0x0b, struct drm_gem_open) 653#define DRM_IOCTL_GET_CAP DRM_IOWR(0x0c, struct drm_get_cap) 654 655#define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique) 656#define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth) 657#define DRM_IOCTL_BLOCK DRM_IOWR(0x12, struct drm_block) 658#define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, struct drm_block) 659#define DRM_IOCTL_CONTROL DRM_IOW( 0x14, struct drm_control) 660#define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map) 661#define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, struct drm_buf_desc) 662#define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, struct drm_buf_desc) 663#define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info) 664#define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, struct drm_buf_map) 665#define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, struct drm_buf_free) 666 667#define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map) 668 669#define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map) 670#define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map) 671 672#define DRM_IOCTL_SET_MASTER DRM_IO(0x1e) 673#define DRM_IOCTL_DROP_MASTER DRM_IO(0x1f) 674 675#define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx) 676#define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx) 677#define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, struct drm_ctx) 678#define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, struct drm_ctx) 679#define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, struct drm_ctx) 680#define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, struct drm_ctx) 681#define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, struct drm_ctx_res) 682#define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, struct drm_draw) 683#define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, struct drm_draw) 684#define DRM_IOCTL_DMA DRM_IOWR(0x29, struct drm_dma) 685#define DRM_IOCTL_LOCK DRM_IOW( 0x2a, struct drm_lock) 686#define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock) 687#define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock) 688 689#define DRM_IOCTL_PRIME_HANDLE_TO_FD DRM_IOWR(0x2d, struct drm_prime_handle) 690#define DRM_IOCTL_PRIME_FD_TO_HANDLE DRM_IOWR(0x2e, struct drm_prime_handle) 691 692#define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30) 693#define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31) 694#define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, struct drm_agp_mode) 695#define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, struct drm_agp_info) 696#define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, struct drm_agp_buffer) 697#define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, struct drm_agp_buffer) 698#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding) 699#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding) 700 701#define DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather) 702#define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather) 703 704#define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank) 705 706#define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw) 707 708#define DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res) 709#define DRM_IOCTL_MODE_GETCRTC DRM_IOWR(0xA1, struct drm_mode_crtc) 710#define DRM_IOCTL_MODE_SETCRTC DRM_IOWR(0xA2, struct drm_mode_crtc) 711#define DRM_IOCTL_MODE_CURSOR DRM_IOWR(0xA3, struct drm_mode_cursor) 712#define DRM_IOCTL_MODE_GETGAMMA DRM_IOWR(0xA4, struct drm_mode_crtc_lut) 713#define DRM_IOCTL_MODE_SETGAMMA DRM_IOWR(0xA5, struct drm_mode_crtc_lut) 714#define DRM_IOCTL_MODE_GETENCODER DRM_IOWR(0xA6, struct drm_mode_get_encoder) 715#define DRM_IOCTL_MODE_GETCONNECTOR DRM_IOWR(0xA7, struct drm_mode_get_connector) 716#define DRM_IOCTL_MODE_ATTACHMODE DRM_IOWR(0xA8, struct drm_mode_mode_cmd) 717#define DRM_IOCTL_MODE_DETACHMODE DRM_IOWR(0xA9, struct drm_mode_mode_cmd) 718 719#define DRM_IOCTL_MODE_GETPROPERTY DRM_IOWR(0xAA, struct drm_mode_get_property) 720#define DRM_IOCTL_MODE_SETPROPERTY DRM_IOWR(0xAB, struct drm_mode_connector_set_property) 721#define DRM_IOCTL_MODE_GETPROPBLOB DRM_IOWR(0xAC, struct drm_mode_get_blob) 722#define DRM_IOCTL_MODE_GETFB DRM_IOWR(0xAD, struct drm_mode_fb_cmd) 723#define DRM_IOCTL_MODE_ADDFB DRM_IOWR(0xAE, struct drm_mode_fb_cmd) 724#define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xAF, unsigned int) 725#define DRM_IOCTL_MODE_PAGE_FLIP DRM_IOWR(0xB0, struct drm_mode_crtc_page_flip) 726#define DRM_IOCTL_MODE_DIRTYFB DRM_IOWR(0xB1, struct drm_mode_fb_dirty_cmd) 727 728#define DRM_IOCTL_MODE_CREATE_DUMB DRM_IOWR(0xB2, struct drm_mode_create_dumb) 729#define DRM_IOCTL_MODE_MAP_DUMB DRM_IOWR(0xB3, struct drm_mode_map_dumb) 730#define DRM_IOCTL_MODE_DESTROY_DUMB DRM_IOWR(0xB4, struct drm_mode_destroy_dumb) 731#define DRM_IOCTL_MODE_GETPLANERESOURCES DRM_IOWR(0xB5, struct drm_mode_get_plane_res) 732#define DRM_IOCTL_MODE_GETPLANE DRM_IOWR(0xB6, struct drm_mode_get_plane) 733#define DRM_IOCTL_MODE_SETPLANE DRM_IOWR(0xB7, struct drm_mode_set_plane) 734#define DRM_IOCTL_MODE_ADDFB2 DRM_IOWR(0xB8, struct drm_mode_fb_cmd2) 735#define DRM_IOCTL_MODE_OBJ_GETPROPERTIES DRM_IOWR(0xB9, struct drm_mode_obj_get_properties) 736#define DRM_IOCTL_MODE_OBJ_SETPROPERTY DRM_IOWR(0xBA, struct drm_mode_obj_set_property) 737 738/** 739 * Device specific ioctls should only be in their respective headers 740 * The device specific ioctl range is from 0x40 to 0x99. 741 * Generic IOCTLS restart at 0xA0. 742 * 743 * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and 744 * drmCommandReadWrite(). 745 */ 746#define DRM_COMMAND_BASE 0x40 747#define DRM_COMMAND_END 0xA0 748 749/** 750 * Header for events written back to userspace on the drm fd. The 751 * type defines the type of event, the length specifies the total 752 * length of the event (including the header), and user_data is 753 * typically a 64 bit value passed with the ioctl that triggered the 754 * event. A read on the drm fd will always only return complete 755 * events, that is, if for example the read buffer is 100 bytes, and 756 * there are two 64 byte events pending, only one will be returned. 757 * 758 * Event types 0 - 0x7fffffff are generic drm events, 0x80000000 and 759 * up are chipset specific. 760 */ 761struct drm_event { 762 __u32 type; 763 __u32 length; 764}; 765 766#define DRM_EVENT_VBLANK 0x01 767#define DRM_EVENT_FLIP_COMPLETE 0x02 768 769struct drm_event_vblank { 770 struct drm_event base; 771 __u64 user_data; 772 __u32 tv_sec; 773 __u32 tv_usec; 774 __u32 sequence; 775 __u32 reserved; 776}; 777 778#define DRM_CAP_DUMB_BUFFER 0x1 779#define DRM_CAP_VBLANK_HIGH_CRTC 0x2 780#define DRM_CAP_DUMB_PREFERRED_DEPTH 0x3 781#define DRM_CAP_DUMB_PREFER_SHADOW 0x4 782#define DRM_CAP_PRIME 0x5 783#define DRM_CAP_TIMESTAMP_MONOTONIC 0x6 784 785#define DRM_PRIME_CAP_IMPORT 0x1 786#define DRM_PRIME_CAP_EXPORT 0x2 787 788/* typedef area */ 789#ifndef __KERNEL__ 790typedef struct drm_clip_rect drm_clip_rect_t; 791typedef struct drm_drawable_info drm_drawable_info_t; 792typedef struct drm_tex_region drm_tex_region_t; 793typedef struct drm_hw_lock drm_hw_lock_t; 794typedef struct drm_version drm_version_t; 795typedef struct drm_unique drm_unique_t; 796typedef struct drm_list drm_list_t; 797typedef struct drm_block drm_block_t; 798typedef struct drm_control drm_control_t; 799typedef enum drm_map_type drm_map_type_t; 800typedef enum drm_map_flags drm_map_flags_t; 801typedef struct drm_ctx_priv_map drm_ctx_priv_map_t; 802typedef struct drm_map drm_map_t; 803typedef struct drm_client drm_client_t; 804typedef enum drm_stat_type drm_stat_type_t; 805typedef struct drm_stats drm_stats_t; 806typedef enum drm_lock_flags drm_lock_flags_t; 807typedef struct drm_lock drm_lock_t; 808typedef enum drm_dma_flags drm_dma_flags_t; 809typedef struct drm_buf_desc drm_buf_desc_t; 810typedef struct drm_buf_info drm_buf_info_t; 811typedef struct drm_buf_free drm_buf_free_t; 812typedef struct drm_buf_pub drm_buf_pub_t; 813typedef struct drm_buf_map drm_buf_map_t; 814typedef struct drm_dma drm_dma_t; 815typedef union drm_wait_vblank drm_wait_vblank_t; 816typedef struct drm_agp_mode drm_agp_mode_t; 817typedef enum drm_ctx_flags drm_ctx_flags_t; 818typedef struct drm_ctx drm_ctx_t; 819typedef struct drm_ctx_res drm_ctx_res_t; 820typedef struct drm_draw drm_draw_t; 821typedef struct drm_update_draw drm_update_draw_t; 822typedef struct drm_auth drm_auth_t; 823typedef struct drm_irq_busid drm_irq_busid_t; 824typedef enum drm_vblank_seq_type drm_vblank_seq_type_t; 825 826typedef struct drm_agp_buffer drm_agp_buffer_t; 827typedef struct drm_agp_binding drm_agp_binding_t; 828typedef struct drm_agp_info drm_agp_info_t; 829typedef struct drm_scatter_gather drm_scatter_gather_t; 830typedef struct drm_set_version drm_set_version_t; 831#endif 832 833#endif 834