1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> 5 * Copyright (c) 2014 Steven Lawrance <stl@koffein.net> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30#include <sys/cdefs.h> 31/* 32 * Analog PLL and power regulator driver for Freescale i.MX6 family of SoCs. 33 * Also, temperature montoring and cpu frequency control. It was Freescale who 34 * kitchen-sinked this device, not us. :) 35 * 36 * We don't really do anything with analog PLLs, but the registers for 37 * controlling them belong to the same block as the power regulator registers. 38 * Since the newbus hierarchy makes it hard for anyone other than us to get at 39 * them, we just export a couple public functions to allow the imx6 CCM clock 40 * driver to read and write those registers. 41 * 42 * We also don't do anything about power regulation yet, but when the need 43 * arises, this would be the place for that code to live. 44 * 45 * I have no idea where the "anatop" name comes from. It's in the standard DTS 46 * source describing i.MX6 SoCs, and in the linux and u-boot code which comes 47 * from Freescale, but it's not in the SoC manual. 48 * 49 * Note that temperature values throughout this code are handled in two types of 50 * units. Items with '_cnt' in the name use the hardware temperature count 51 * units (higher counts are lower temperatures). Items with '_val' in the name 52 * are deci-Celsius, which are converted to/from deci-Kelvins in the sysctl 53 * handlers (dK is the standard unit for temperature in sysctl). 54 */ 55 56#include <sys/param.h> 57#include <sys/systm.h> 58#include <sys/callout.h> 59#include <sys/kernel.h> 60#include <sys/limits.h> 61#include <sys/sysctl.h> 62#include <sys/module.h> 63#include <sys/bus.h> 64#include <sys/rman.h> 65 66#include <dev/ofw/ofw_bus.h> 67#include <dev/ofw/ofw_bus_subr.h> 68 69#include <machine/bus.h> 70 71#include <arm/arm/mpcore_timervar.h> 72#include <arm/freescale/fsl_ocotpreg.h> 73#include <arm/freescale/fsl_ocotpvar.h> 74#include <arm/freescale/imx/imx_ccmvar.h> 75#include <arm/freescale/imx/imx_machdep.h> 76#include <arm/freescale/imx/imx6_anatopreg.h> 77#include <arm/freescale/imx/imx6_anatopvar.h> 78 79static struct resource_spec imx6_anatop_spec[] = { 80 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 81 { -1, 0 } 82}; 83#define MEMRES 0 84#define IRQRES 1 85 86struct imx6_anatop_softc { 87 device_t dev; 88 struct resource *res[2]; 89 struct intr_config_hook 90 intr_setup_hook; 91 uint32_t cpu_curmhz; 92 uint32_t cpu_curmv; 93 uint32_t cpu_minmhz; 94 uint32_t cpu_minmv; 95 uint32_t cpu_maxmhz; 96 uint32_t cpu_maxmv; 97 uint32_t cpu_maxmhz_hw; 98 boolean_t cpu_overclock_enable; 99 boolean_t cpu_init_done; 100 uint32_t refosc_mhz; 101 void *temp_intrhand; 102 uint32_t temp_high_val; 103 uint32_t temp_high_cnt; 104 uint32_t temp_last_cnt; 105 uint32_t temp_room_cnt; 106 struct callout temp_throttle_callout; 107 sbintime_t temp_throttle_delay; 108 uint32_t temp_throttle_reset_cnt; 109 uint32_t temp_throttle_trigger_cnt; 110 uint32_t temp_throttle_val; 111}; 112 113static struct imx6_anatop_softc *imx6_anatop_sc; 114 115/* 116 * Table of "operating points". 117 * These are combinations of frequency and voltage blessed by Freescale. 118 * While the datasheet says the ARM voltage can be as low as 925mV at 119 * 396MHz, it also says that the ARM and SOC voltages can't differ by 120 * more than 200mV, and the minimum SOC voltage is 1150mV, so that 121 * dictates the 950mV entry in this table. 122 */ 123static struct oppt { 124 uint32_t mhz; 125 uint32_t mv; 126} imx6_oppt_table[] = { 127 { 396, 950}, 128 { 792, 1150}, 129 { 852, 1225}, 130 { 996, 1225}, 131 {1200, 1275}, 132}; 133 134/* 135 * Table of CPU max frequencies. This is used to translate the max frequency 136 * value (0-3) from the ocotp CFG3 register into a mhz value that can be looked 137 * up in the operating points table. 138 */ 139static uint32_t imx6_ocotp_mhz_tab[] = {792, 852, 996, 1200}; 140 141#define TZ_ZEROC 2731 /* deci-Kelvin <-> deci-Celsius offset. */ 142 143uint32_t 144imx6_anatop_read_4(bus_size_t offset) 145{ 146 147 KASSERT(imx6_anatop_sc != NULL, ("imx6_anatop_read_4 sc NULL")); 148 149 return (bus_read_4(imx6_anatop_sc->res[MEMRES], offset)); 150} 151 152void 153imx6_anatop_write_4(bus_size_t offset, uint32_t value) 154{ 155 156 KASSERT(imx6_anatop_sc != NULL, ("imx6_anatop_write_4 sc NULL")); 157 158 bus_write_4(imx6_anatop_sc->res[MEMRES], offset, value); 159} 160 161static void 162vdd_set(struct imx6_anatop_softc *sc, int mv) 163{ 164 int newtarg, newtargSoc, oldtarg; 165 uint32_t delay, pmureg; 166 static boolean_t init_done = false; 167 168 /* 169 * The datasheet says VDD_PU and VDD_SOC must be equal, and VDD_ARM 170 * can't be more than 50mV above or 200mV below them. We keep them the 171 * same except in the case of the lowest operating point, which is 172 * handled as a special case below. 173 */ 174 175 pmureg = imx6_anatop_read_4(IMX6_ANALOG_PMU_REG_CORE); 176 oldtarg = pmureg & IMX6_ANALOG_PMU_REG0_TARG_MASK; 177 178 /* Convert mV to target value. Clamp target to valid range. */ 179 if (mv < 725) 180 newtarg = 0x00; 181 else if (mv > 1450) 182 newtarg = 0x1F; 183 else 184 newtarg = (mv - 700) / 25; 185 186 /* 187 * The SOC voltage can't go below 1150mV, and thus because of the 200mV 188 * rule, the ARM voltage can't go below 950mV. The 950 is encoded in 189 * our oppt table, here we handle the SOC 1150 rule as a special case. 190 * (1150-700/25=18). 191 */ 192 newtargSoc = (newtarg < 18) ? 18 : newtarg; 193 194 /* 195 * The first time through the 3 voltages might not be equal so use a 196 * long conservative delay. After that we need to delay 3uS for every 197 * 25mV step upward; we actually delay 6uS because empirically, it works 198 * and the 3uS per step recommended by the docs doesn't (3uS fails when 199 * going from 400->1200, but works for smaller changes). 200 */ 201 if (init_done) { 202 if (newtarg == oldtarg) 203 return; 204 else if (newtarg > oldtarg) 205 delay = (newtarg - oldtarg) * 6; 206 else 207 delay = 0; 208 } else { 209 delay = (700 / 25) * 6; 210 init_done = true; 211 } 212 213 /* 214 * Make the change and wait for it to take effect. 215 */ 216 pmureg &= ~(IMX6_ANALOG_PMU_REG0_TARG_MASK | 217 IMX6_ANALOG_PMU_REG1_TARG_MASK | 218 IMX6_ANALOG_PMU_REG2_TARG_MASK); 219 220 pmureg |= newtarg << IMX6_ANALOG_PMU_REG0_TARG_SHIFT; 221 pmureg |= newtarg << IMX6_ANALOG_PMU_REG1_TARG_SHIFT; 222 pmureg |= newtargSoc << IMX6_ANALOG_PMU_REG2_TARG_SHIFT; 223 224 imx6_anatop_write_4(IMX6_ANALOG_PMU_REG_CORE, pmureg); 225 DELAY(delay); 226 sc->cpu_curmv = newtarg * 25 + 700; 227} 228 229static inline uint32_t 230cpufreq_mhz_from_div(struct imx6_anatop_softc *sc, uint32_t corediv, 231 uint32_t plldiv) 232{ 233 234 return ((sc->refosc_mhz * (plldiv / 2)) / (corediv + 1)); 235} 236 237static inline void 238cpufreq_mhz_to_div(struct imx6_anatop_softc *sc, uint32_t cpu_mhz, 239 uint32_t *corediv, uint32_t *plldiv) 240{ 241 242 *corediv = (cpu_mhz < 650) ? 1 : 0; 243 *plldiv = ((*corediv + 1) * cpu_mhz) / (sc->refosc_mhz / 2); 244} 245 246static inline uint32_t 247cpufreq_actual_mhz(struct imx6_anatop_softc *sc, uint32_t cpu_mhz) 248{ 249 uint32_t corediv, plldiv; 250 251 cpufreq_mhz_to_div(sc, cpu_mhz, &corediv, &plldiv); 252 return (cpufreq_mhz_from_div(sc, corediv, plldiv)); 253} 254 255static struct oppt * 256cpufreq_nearest_oppt(struct imx6_anatop_softc *sc, uint32_t cpu_newmhz) 257{ 258 int d, diff, i, nearest; 259 260 if (cpu_newmhz > sc->cpu_maxmhz_hw && !sc->cpu_overclock_enable) 261 cpu_newmhz = sc->cpu_maxmhz_hw; 262 263 diff = INT_MAX; 264 nearest = 0; 265 for (i = 0; i < nitems(imx6_oppt_table); ++i) { 266 d = abs((int)cpu_newmhz - (int)imx6_oppt_table[i].mhz); 267 if (diff > d) { 268 diff = d; 269 nearest = i; 270 } 271 } 272 return (&imx6_oppt_table[nearest]); 273} 274 275static void 276cpufreq_set_clock(struct imx6_anatop_softc * sc, struct oppt *op) 277{ 278 uint32_t corediv, plldiv, timeout, wrk32; 279 280 /* If increasing the frequency, we must first increase the voltage. */ 281 if (op->mhz > sc->cpu_curmhz) { 282 vdd_set(sc, op->mv); 283 } 284 285 /* 286 * I can't find a documented procedure for changing the ARM PLL divisor, 287 * but some trial and error came up with this: 288 * - Set the bypass clock source to REF_CLK_24M (source #0). 289 * - Set the PLL into bypass mode; cpu should now be running at 24mhz. 290 * - Change the divisor. 291 * - Wait for the LOCK bit to come on; it takes ~50 loop iterations. 292 * - Turn off bypass mode; cpu should now be running at the new speed. 293 */ 294 cpufreq_mhz_to_div(sc, op->mhz, &corediv, &plldiv); 295 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM_CLR, 296 IMX6_ANALOG_CCM_PLL_ARM_CLK_SRC_MASK); 297 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM_SET, 298 IMX6_ANALOG_CCM_PLL_ARM_BYPASS); 299 300 wrk32 = imx6_anatop_read_4(IMX6_ANALOG_CCM_PLL_ARM); 301 wrk32 &= ~IMX6_ANALOG_CCM_PLL_ARM_DIV_MASK; 302 wrk32 |= plldiv; 303 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM, wrk32); 304 305 timeout = 10000; 306 while ((imx6_anatop_read_4(IMX6_ANALOG_CCM_PLL_ARM) & 307 IMX6_ANALOG_CCM_PLL_ARM_LOCK) == 0) 308 if (--timeout == 0) 309 panic("imx6_set_cpu_clock(): PLL never locked"); 310 311 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM_CLR, 312 IMX6_ANALOG_CCM_PLL_ARM_BYPASS); 313 imx_ccm_set_cacrr(corediv); 314 315 /* If lowering the frequency, it is now safe to lower the voltage. */ 316 if (op->mhz < sc->cpu_curmhz) 317 vdd_set(sc, op->mv); 318 sc->cpu_curmhz = op->mhz; 319 320 /* Tell the mpcore timer that its frequency has changed. */ 321 arm_tmr_change_frequency( 322 cpufreq_actual_mhz(sc, sc->cpu_curmhz) * 1000000 / 2); 323} 324 325static int 326cpufreq_sysctl_minmhz(SYSCTL_HANDLER_ARGS) 327{ 328 struct imx6_anatop_softc *sc; 329 struct oppt * op; 330 uint32_t temp; 331 int err; 332 333 sc = arg1; 334 335 temp = sc->cpu_minmhz; 336 err = sysctl_handle_int(oidp, &temp, 0, req); 337 if (err != 0 || req->newptr == NULL) 338 return (err); 339 340 op = cpufreq_nearest_oppt(sc, temp); 341 if (op->mhz > sc->cpu_maxmhz) 342 return (ERANGE); 343 else if (op->mhz == sc->cpu_minmhz) 344 return (0); 345 346 /* 347 * Value changed, update softc. If the new min is higher than the 348 * current speed, raise the current speed to match. 349 */ 350 sc->cpu_minmhz = op->mhz; 351 if (sc->cpu_minmhz > sc->cpu_curmhz) { 352 cpufreq_set_clock(sc, op); 353 } 354 return (err); 355} 356 357static int 358cpufreq_sysctl_maxmhz(SYSCTL_HANDLER_ARGS) 359{ 360 struct imx6_anatop_softc *sc; 361 struct oppt * op; 362 uint32_t temp; 363 int err; 364 365 sc = arg1; 366 367 temp = sc->cpu_maxmhz; 368 err = sysctl_handle_int(oidp, &temp, 0, req); 369 if (err != 0 || req->newptr == NULL) 370 return (err); 371 372 op = cpufreq_nearest_oppt(sc, temp); 373 if (op->mhz < sc->cpu_minmhz) 374 return (ERANGE); 375 else if (op->mhz == sc->cpu_maxmhz) 376 return (0); 377 378 /* 379 * Value changed, update softc and hardware. The hardware update is 380 * unconditional. We always try to run at max speed, so any change of 381 * the max means we need to change the current speed too, regardless of 382 * whether it is higher or lower than the old max. 383 */ 384 sc->cpu_maxmhz = op->mhz; 385 cpufreq_set_clock(sc, op); 386 387 return (err); 388} 389 390static void 391cpufreq_initialize(struct imx6_anatop_softc *sc) 392{ 393 uint32_t cfg3speed; 394 struct oppt * op; 395 396 SYSCTL_ADD_INT(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx), 397 OID_AUTO, "cpu_mhz", CTLFLAG_RD, &sc->cpu_curmhz, 0, 398 "CPU frequency"); 399 400 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx), 401 OID_AUTO, "cpu_minmhz", 402 CTLTYPE_INT | CTLFLAG_RWTUN | CTLFLAG_NOFETCH | CTLFLAG_NEEDGIANT, 403 sc, 0, cpufreq_sysctl_minmhz, "IU", "Minimum CPU frequency"); 404 405 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx), 406 OID_AUTO, "cpu_maxmhz", 407 CTLTYPE_INT | CTLFLAG_RWTUN | CTLFLAG_NOFETCH | CTLFLAG_NEEDGIANT, 408 sc, 0, cpufreq_sysctl_maxmhz, "IU", "Maximum CPU frequency"); 409 410 SYSCTL_ADD_INT(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx), 411 OID_AUTO, "cpu_maxmhz_hw", CTLFLAG_RD, &sc->cpu_maxmhz_hw, 0, 412 "Maximum CPU frequency allowed by hardware"); 413 414 SYSCTL_ADD_INT(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx), 415 OID_AUTO, "cpu_overclock_enable", CTLFLAG_RWTUN, 416 &sc->cpu_overclock_enable, 0, 417 "Allow setting CPU frequency higher than cpu_maxmhz_hw"); 418 419 /* 420 * XXX 24mhz shouldn't be hard-coded, should get this from imx6_ccm 421 * (even though in the real world it will always be 24mhz). Oh wait a 422 * sec, I never wrote imx6_ccm. 423 */ 424 sc->refosc_mhz = 24; 425 426 /* 427 * Get the maximum speed this cpu can be set to. The values in the 428 * OCOTP CFG3 register are not documented in the reference manual. 429 * The following info was in an archived email found via web search: 430 * - 2b'11: 1200000000Hz; 431 * - 2b'10: 996000000Hz; 432 * - 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz. 433 * - 2b'00: 792000000Hz; 434 * The default hardware max speed can be overridden by a tunable. 435 */ 436 cfg3speed = (fsl_ocotp_read_4(FSL_OCOTP_CFG3) & 437 FSL_OCOTP_CFG3_SPEED_MASK) >> FSL_OCOTP_CFG3_SPEED_SHIFT; 438 sc->cpu_maxmhz_hw = imx6_ocotp_mhz_tab[cfg3speed]; 439 sc->cpu_maxmhz = sc->cpu_maxmhz_hw; 440 441 TUNABLE_INT_FETCH("hw.imx6.cpu_minmhz", &sc->cpu_minmhz); 442 op = cpufreq_nearest_oppt(sc, sc->cpu_minmhz); 443 sc->cpu_minmhz = op->mhz; 444 sc->cpu_minmv = op->mv; 445 446 TUNABLE_INT_FETCH("hw.imx6.cpu_maxmhz", &sc->cpu_maxmhz); 447 op = cpufreq_nearest_oppt(sc, sc->cpu_maxmhz); 448 sc->cpu_maxmhz = op->mhz; 449 sc->cpu_maxmv = op->mv; 450 451 /* 452 * Set the CPU to maximum speed. 453 * 454 * We won't have thermal throttling until interrupts are enabled, but we 455 * want to run at full speed through all the device init stuff. This 456 * basically assumes that a single core can't overheat before interrupts 457 * are enabled; empirical testing shows that to be a safe assumption. 458 */ 459 cpufreq_set_clock(sc, op); 460} 461 462static inline uint32_t 463temp_from_count(struct imx6_anatop_softc *sc, uint32_t count) 464{ 465 466 return (((sc->temp_high_val - (count - sc->temp_high_cnt) * 467 (sc->temp_high_val - 250) / 468 (sc->temp_room_cnt - sc->temp_high_cnt)))); 469} 470 471static inline uint32_t 472temp_to_count(struct imx6_anatop_softc *sc, uint32_t temp) 473{ 474 475 return ((sc->temp_room_cnt - sc->temp_high_cnt) * 476 (sc->temp_high_val - temp) / (sc->temp_high_val - 250) + 477 sc->temp_high_cnt); 478} 479 480static void 481temp_update_count(struct imx6_anatop_softc *sc) 482{ 483 uint32_t val; 484 485 val = imx6_anatop_read_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0); 486 if (!(val & IMX6_ANALOG_TEMPMON_TEMPSENSE0_VALID)) 487 return; 488 sc->temp_last_cnt = 489 (val & IMX6_ANALOG_TEMPMON_TEMPSENSE0_TEMP_CNT_MASK) >> 490 IMX6_ANALOG_TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT; 491} 492 493static int 494temp_sysctl_handler(SYSCTL_HANDLER_ARGS) 495{ 496 struct imx6_anatop_softc *sc = arg1; 497 uint32_t t; 498 499 temp_update_count(sc); 500 501 t = temp_from_count(sc, sc->temp_last_cnt) + TZ_ZEROC; 502 503 return (sysctl_handle_int(oidp, &t, 0, req)); 504} 505 506static int 507temp_throttle_sysctl_handler(SYSCTL_HANDLER_ARGS) 508{ 509 struct imx6_anatop_softc *sc = arg1; 510 int err; 511 uint32_t temp; 512 513 temp = sc->temp_throttle_val + TZ_ZEROC; 514 err = sysctl_handle_int(oidp, &temp, 0, req); 515 if (temp < TZ_ZEROC) 516 return (ERANGE); 517 temp -= TZ_ZEROC; 518 if (err != 0 || req->newptr == NULL || temp == sc->temp_throttle_val) 519 return (err); 520 521 /* Value changed, update counts in softc and hardware. */ 522 sc->temp_throttle_val = temp; 523 sc->temp_throttle_trigger_cnt = temp_to_count(sc, sc->temp_throttle_val); 524 sc->temp_throttle_reset_cnt = temp_to_count(sc, sc->temp_throttle_val - 100); 525 imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0_CLR, 526 IMX6_ANALOG_TEMPMON_TEMPSENSE0_ALARM_MASK); 527 imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0_SET, 528 (sc->temp_throttle_trigger_cnt << 529 IMX6_ANALOG_TEMPMON_TEMPSENSE0_ALARM_SHIFT)); 530 return (err); 531} 532 533static void 534tempmon_gofast(struct imx6_anatop_softc *sc) 535{ 536 537 if (sc->cpu_curmhz < sc->cpu_maxmhz) { 538 cpufreq_set_clock(sc, cpufreq_nearest_oppt(sc, sc->cpu_maxmhz)); 539 } 540} 541 542static void 543tempmon_goslow(struct imx6_anatop_softc *sc) 544{ 545 546 if (sc->cpu_curmhz > sc->cpu_minmhz) { 547 cpufreq_set_clock(sc, cpufreq_nearest_oppt(sc, sc->cpu_minmhz)); 548 } 549} 550 551static int 552tempmon_intr(void *arg) 553{ 554 struct imx6_anatop_softc *sc = arg; 555 556 /* 557 * XXX Note that this code doesn't currently run (for some mysterious 558 * reason we just never get an interrupt), so the real monitoring is 559 * done by tempmon_throttle_check(). 560 */ 561 tempmon_goslow(sc); 562 /* XXX Schedule callout to speed back up eventually. */ 563 return (FILTER_HANDLED); 564} 565 566static void 567tempmon_throttle_check(void *arg) 568{ 569 struct imx6_anatop_softc *sc = arg; 570 571 /* Lower counts are higher temperatures. */ 572 if (sc->temp_last_cnt < sc->temp_throttle_trigger_cnt) 573 tempmon_goslow(sc); 574 else if (sc->temp_last_cnt > (sc->temp_throttle_reset_cnt)) 575 tempmon_gofast(sc); 576 577 callout_reset_sbt(&sc->temp_throttle_callout, sc->temp_throttle_delay, 578 0, tempmon_throttle_check, sc, 0); 579 580} 581 582static void 583initialize_tempmon(struct imx6_anatop_softc *sc) 584{ 585 uint32_t cal; 586 587 /* 588 * Fetch calibration data: a sensor count at room temperature (25C), 589 * a sensor count at a high temperature, and that temperature 590 */ 591 cal = fsl_ocotp_read_4(FSL_OCOTP_ANA1); 592 sc->temp_room_cnt = (cal & 0xFFF00000) >> 20; 593 sc->temp_high_cnt = (cal & 0x000FFF00) >> 8; 594 sc->temp_high_val = (cal & 0x000000FF) * 10; 595 596 /* 597 * Throttle to a lower cpu freq at 10C below the "hot" temperature, and 598 * reset back to max cpu freq at 5C below the trigger. 599 */ 600 sc->temp_throttle_val = sc->temp_high_val - 100; 601 sc->temp_throttle_trigger_cnt = 602 temp_to_count(sc, sc->temp_throttle_val); 603 sc->temp_throttle_reset_cnt = 604 temp_to_count(sc, sc->temp_throttle_val - 50); 605 606 /* 607 * Set the sensor to sample automatically at 16Hz (32.768KHz/0x800), set 608 * the throttle count, and begin making measurements. 609 */ 610 imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE1, 0x0800); 611 imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0, 612 (sc->temp_throttle_trigger_cnt << 613 IMX6_ANALOG_TEMPMON_TEMPSENSE0_ALARM_SHIFT) | 614 IMX6_ANALOG_TEMPMON_TEMPSENSE0_MEASURE); 615 616 /* 617 * XXX Note that the alarm-interrupt feature isn't working yet, so 618 * we'll use a callout handler to check at 10Hz. Make sure we have an 619 * initial temperature reading before starting up the callouts so we 620 * don't get a bogus reading of zero. 621 */ 622 while (sc->temp_last_cnt == 0) 623 temp_update_count(sc); 624 sc->temp_throttle_delay = 100 * SBT_1MS; 625 callout_init(&sc->temp_throttle_callout, 0); 626 callout_reset_sbt(&sc->temp_throttle_callout, sc->temp_throttle_delay, 627 0, tempmon_throttle_check, sc, 0); 628 629 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx), 630 OID_AUTO, "temperature", 631 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 632 temp_sysctl_handler, "IK", "Current die temperature"); 633 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx), 634 OID_AUTO, "throttle_temperature", 635 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 636 0, temp_throttle_sysctl_handler, "IK", 637 "Throttle CPU when exceeding this temperature"); 638} 639 640static void 641intr_setup(void *arg) 642{ 643 int rid; 644 struct imx6_anatop_softc *sc; 645 646 sc = arg; 647 rid = 0; 648 sc->res[IRQRES] = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &rid, 649 RF_ACTIVE); 650 if (sc->res[IRQRES] != NULL) { 651 bus_setup_intr(sc->dev, sc->res[IRQRES], 652 INTR_TYPE_MISC | INTR_MPSAFE, tempmon_intr, NULL, sc, 653 &sc->temp_intrhand); 654 } else { 655 device_printf(sc->dev, "Cannot allocate IRQ resource\n"); 656 } 657 config_intrhook_disestablish(&sc->intr_setup_hook); 658} 659 660static void 661imx6_anatop_new_pass(device_t dev) 662{ 663 struct imx6_anatop_softc *sc; 664 const int cpu_init_pass = BUS_PASS_CPU + BUS_PASS_ORDER_MIDDLE; 665 666 /* 667 * We attach during BUS_PASS_BUS (because some day we will be a 668 * simplebus that has regulator devices as children), but some of our 669 * init work cannot be done until BUS_PASS_CPU (we rely on other devices 670 * that attach on the CPU pass). 671 */ 672 sc = device_get_softc(dev); 673 if (!sc->cpu_init_done && bus_current_pass >= cpu_init_pass) { 674 sc->cpu_init_done = true; 675 cpufreq_initialize(sc); 676 initialize_tempmon(sc); 677 if (bootverbose) { 678 device_printf(sc->dev, "CPU %uMHz @ %umV\n", 679 sc->cpu_curmhz, sc->cpu_curmv); 680 } 681 } 682 bus_generic_new_pass(dev); 683} 684 685static int 686imx6_anatop_detach(device_t dev) 687{ 688 689 /* This device can never detach. */ 690 return (EBUSY); 691} 692 693static int 694imx6_anatop_attach(device_t dev) 695{ 696 struct imx6_anatop_softc *sc; 697 int err; 698 699 sc = device_get_softc(dev); 700 sc->dev = dev; 701 702 /* Allocate bus_space resources. */ 703 if (bus_alloc_resources(dev, imx6_anatop_spec, sc->res)) { 704 device_printf(dev, "Cannot allocate resources\n"); 705 err = ENXIO; 706 goto out; 707 } 708 709 sc->intr_setup_hook.ich_func = intr_setup; 710 sc->intr_setup_hook.ich_arg = sc; 711 config_intrhook_establish(&sc->intr_setup_hook); 712 713 SYSCTL_ADD_UINT(device_get_sysctl_ctx(sc->dev), 714 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 715 OID_AUTO, "cpu_voltage", CTLFLAG_RD, 716 &sc->cpu_curmv, 0, "Current CPU voltage in millivolts"); 717 718 imx6_anatop_sc = sc; 719 720 /* 721 * Other code seen on the net sets this SELFBIASOFF flag around the same 722 * time the temperature sensor is set up, although it's unclear how the 723 * two are related (if at all). 724 */ 725 imx6_anatop_write_4(IMX6_ANALOG_PMU_MISC0_SET, 726 IMX6_ANALOG_PMU_MISC0_SELFBIASOFF); 727 728 /* 729 * Some day, when we're ready to deal with the actual anatop regulators 730 * that are described in fdt data as children of this "bus", this would 731 * be the place to invoke a simplebus helper routine to instantiate the 732 * children from the fdt data. 733 */ 734 735 err = 0; 736 737out: 738 739 if (err != 0) { 740 bus_release_resources(dev, imx6_anatop_spec, sc->res); 741 } 742 743 return (err); 744} 745 746uint32_t 747pll4_configure_output(uint32_t mfi, uint32_t mfn, uint32_t mfd) 748{ 749 int reg; 750 751 /* 752 * Audio PLL (PLL4). 753 * PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM) 754 */ 755 756 reg = (IMX6_ANALOG_CCM_PLL_AUDIO_ENABLE); 757 reg &= ~(IMX6_ANALOG_CCM_PLL_AUDIO_DIV_SELECT_MASK << \ 758 IMX6_ANALOG_CCM_PLL_AUDIO_DIV_SELECT_SHIFT); 759 reg |= (mfi << IMX6_ANALOG_CCM_PLL_AUDIO_DIV_SELECT_SHIFT); 760 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_AUDIO, reg); 761 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_AUDIO_NUM, mfn); 762 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_AUDIO_DENOM, mfd); 763 764 return (0); 765} 766 767static int 768imx6_anatop_probe(device_t dev) 769{ 770 771 if (!ofw_bus_status_okay(dev)) 772 return (ENXIO); 773 774 if (ofw_bus_is_compatible(dev, "fsl,imx6q-anatop") == 0) 775 return (ENXIO); 776 777 device_set_desc(dev, "Freescale i.MX6 Analog PLLs and Power"); 778 779 return (BUS_PROBE_DEFAULT); 780} 781 782uint32_t 783imx6_get_cpu_clock(void) 784{ 785 uint32_t corediv, plldiv; 786 787 corediv = imx_ccm_get_cacrr(); 788 plldiv = imx6_anatop_read_4(IMX6_ANALOG_CCM_PLL_ARM) & 789 IMX6_ANALOG_CCM_PLL_ARM_DIV_MASK; 790 return (cpufreq_mhz_from_div(imx6_anatop_sc, corediv, plldiv)); 791} 792 793static device_method_t imx6_anatop_methods[] = { 794 /* Device interface */ 795 DEVMETHOD(device_probe, imx6_anatop_probe), 796 DEVMETHOD(device_attach, imx6_anatop_attach), 797 DEVMETHOD(device_detach, imx6_anatop_detach), 798 799 /* Bus interface */ 800 DEVMETHOD(bus_new_pass, imx6_anatop_new_pass), 801 802 DEVMETHOD_END 803}; 804 805static driver_t imx6_anatop_driver = { 806 "imx6_anatop", 807 imx6_anatop_methods, 808 sizeof(struct imx6_anatop_softc) 809}; 810 811EARLY_DRIVER_MODULE(imx6_anatop, simplebus, imx6_anatop_driver, 0, 0, 812 BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); 813EARLY_DRIVER_MODULE(imx6_anatop, ofwbus, imx6_anatop_driver, 0, 0, 814 BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); 815