1/*- 2 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca> 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 18 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 19 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 20 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 21 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26#include <sys/param.h> 27#include <sys/systm.h> 28#include <sys/kernel.h> 29#include <sys/types.h> 30 31#include <arm/allwinner/allwinner_pinctrl.h> 32 33#include "opt_soc.h" 34 35#ifdef SOC_ALLWINNER_A64 36 37static const struct allwinner_pins a64_pins[] = { 38 { "PB0", 1, 0, { "gpio_in", "gpio_out", "uart2", NULL, "jtag", NULL, "pb_eint0" }, 6, 0, 0}, 39 { "PB1", 1, 1, { "gpio_in", "gpio_out", "uart2", NULL, "jtag", "sim", "pb_eint1" }, 6, 1, 0}, 40 { "PB2", 1, 2, { "gpio_in", "gpio_out", "uart2", NULL, "jtag", "sim", "pb_eint2" }, 6, 2, 0}, 41 { "PB3", 1, 3, { "gpio_in", "gpio_out", "uart2", "i2s0", "jtag", "sim", "pb_eint3" }, 6, 3, 0}, 42 { "PB4", 1, 4, { "gpio_in", "gpio_out", "aif2", "pcm0", NULL, "sim", "pb_eint4" }, 6, 4, 0}, 43 { "PB5", 1, 5, { "gpio_in", "gpio_out", "aif2", "pcm0", NULL, "sim", "pb_eint5" }, 6, 5, 0}, 44 { "PB6", 1, 6, { "gpio_in", "gpio_out", "aif2", "pcm0", NULL, "sim", "pb_eint6" }, 6, 6, 0}, 45 { "PB7", 1, 7, { "gpio_in", "gpio_out", "aif2", "pcm0", NULL, "sim", "pb_eint7" }, 6, 7, 0}, 46 { "PB8", 1, 8, { "gpio_in", "gpio_out", NULL, NULL, "uart0", NULL, "pb_eint8" }, 6, 8, 0}, 47 { "PB9", 1, 9, { "gpio_in", "gpio_out", NULL, NULL, "uart0", NULL, "pb_eint9" }, 6, 9, 0}, 48 49 { "PC0", 2, 0, { "gpio_in", "gpio_out", "nand", NULL, "spi0" } }, 50 { "PC1", 2, 1, { "gpio_in", "gpio_out", "nand", "mmc2", "spi0" } }, 51 { "PC2", 2, 2, { "gpio_in", "gpio_out", "nand", NULL, "spi0" } }, 52 { "PC3", 2, 3, { "gpio_in", "gpio_out", "nand", NULL, "spi0" } }, 53 { "PC4", 2, 4, { "gpio_in", "gpio_out", "nand" } }, 54 { "PC5", 2, 5, { "gpio_in", "gpio_out", "nand", "mmc2" } }, 55 { "PC6", 2, 6, { "gpio_in", "gpio_out", "nand", "mmc2" } }, 56 { "PC7", 2, 7, { "gpio_in", "gpio_out", "nand" } }, 57 { "PC8", 2, 8, { "gpio_in", "gpio_out", "nand", "mmc2" } }, 58 { "PC9", 2, 9, { "gpio_in", "gpio_out", "nand", "mmc2" } }, 59 { "PC10", 2, 10, { "gpio_in", "gpio_out", "nand", "mmc2" } }, 60 { "PC11", 2, 11, { "gpio_in", "gpio_out", "nand", "mmc2" } }, 61 { "PC12", 2, 12, { "gpio_in", "gpio_out", "nand", "mmc2" } }, 62 { "PC13", 2, 13, { "gpio_in", "gpio_out", "nand", "mmc2" } }, 63 { "PC14", 2, 14, { "gpio_in", "gpio_out", "nand", "mmc2" } }, 64 { "PC15", 2, 15, { "gpio_in", "gpio_out", "nand", "mmc2" } }, 65 { "PC16", 2, 16, { "gpio_in", "gpio_out", "nand", "mmc2" } }, 66 67 { "PD0", 3, 0, { "gpio_in", "gpio_out", "lcd", "uart3", "spi1", "ccir" } }, 68 { "PD1", 3, 1, { "gpio_in", "gpio_out", "lcd", "uart3", "spi1", "ccir" } }, 69 { "PD2", 3, 2, { "gpio_in", "gpio_out", "lcd", "uart4", "spi1", "ccir" } }, 70 { "PD3", 3, 3, { "gpio_in", "gpio_out", "lcd", "uart4", "spi1", "ccir" } }, 71 { "PD4", 3, 4, { "gpio_in", "gpio_out", "lcd", "uart4", "spi1", "ccir" } }, 72 { "PD5", 3, 5, { "gpio_in", "gpio_out", "lcd", "uart4", "spi1", "ccir" } }, 73 { "PD6", 3, 6, { "gpio_in", "gpio_out", "lcd", NULL, NULL, "ccir" } }, 74 { "PD7", 3, 7, { "gpio_in", "gpio_out", "lcd", NULL, NULL, "ccir" } }, 75 { "PD8", 3, 8, { "gpio_in", "gpio_out", "lcd", NULL, "emac", "ccir" } }, 76 { "PD9", 3, 9, { "gpio_in", "gpio_out", "lcd", NULL, "emac", "ccir" } }, 77 { "PD10", 3, 10, { "gpio_in", "gpio_out", "lcd", NULL, "emac" } }, 78 { "PD11", 3, 11, { "gpio_in", "gpio_out", "lcd", NULL, "emac" } }, 79 { "PD12", 3, 12, { "gpio_in", "gpio_out", "lcd", "lvds", "emac" } }, 80 { "PD13", 3, 13, { "gpio_in", "gpio_out", "lcd", "lvds", "emac" } }, 81 { "PD14", 3, 14, { "gpio_in", "gpio_out", "lcd", "lvds", "emac" } }, 82 { "PD15", 3, 15, { "gpio_in", "gpio_out", "lcd", "lvds", "emac", "ccir" } }, 83 { "PD16", 3, 16, { "gpio_in", "gpio_out", "lcd", "lvds", "emac", "ccir" } }, 84 { "PD17", 3, 17, { "gpio_in", "gpio_out", "lcd", "lvds", "emac" } }, 85 { "PD18", 3, 18, { "gpio_in", "gpio_out", "lcd", "lvds", "emac" } }, 86 { "PD19", 3, 19, { "gpio_in", "gpio_out", "lcd", "lvds", "emac" } }, 87 { "PD20", 3, 20, { "gpio_in", "gpio_out", "lcd", "lvds", "emac" } }, 88 { "PD21", 3, 21, { "gpio_in", "gpio_out", "lcd", "lvds", "emac" } }, 89 { "PD22", 3, 22, { "gpio_in", "gpio_out", "pwm0", NULL, "emac" } }, 90 { "PD23", 3, 23, { "gpio_in", "gpio_out", NULL, NULL, "emac" } }, 91 { "PD24", 3, 24, { "gpio_in", "gpio_out" } }, 92 93 { "PE0", 4, 0, { "gpio_in", "gpio_out", "csi", NULL, "ts" } }, 94 { "PE1", 4, 1, { "gpio_in", "gpio_out", "csi", NULL, "ts" } }, 95 { "PE2", 4, 2, { "gpio_in", "gpio_out", "csi", NULL, "ts" } }, 96 { "PE3", 4, 3, { "gpio_in", "gpio_out", "csi", NULL, "ts" } }, 97 { "PE4", 4, 4, { "gpio_in", "gpio_out", "csi", NULL, "ts" } }, 98 { "PE5", 4, 5, { "gpio_in", "gpio_out", "csi", NULL, "ts" } }, 99 { "PE6", 4, 6, { "gpio_in", "gpio_out", "csi", NULL, "ts" } }, 100 { "PE7", 4, 7, { "gpio_in", "gpio_out", "csi", NULL, "ts" } }, 101 { "PE8", 4, 8, { "gpio_in", "gpio_out", "csi", NULL, "ts" } }, 102 { "PE9", 4, 9, { "gpio_in", "gpio_out", "csi", NULL, "ts" } }, 103 { "PE10", 4, 10, { "gpio_in", "gpio_out", "csi", NULL, "ts" } }, 104 { "PE11", 4, 11, { "gpio_in", "gpio_out", "csi", NULL, "ts" } }, 105 { "PE12", 4, 12, { "gpio_in", "gpio_out", "csi" } }, 106 { "PE13", 4, 13, { "gpio_in", "gpio_out", "csi" } }, 107 { "PE14", 4, 14, { "gpio_in", "gpio_out", "pll_lock", "twi2" } }, 108 { "PE15", 4, 15, { "gpio_in", "gpio_out", NULL, "twi2" } }, 109 { "PE16", 4, 16, { "gpio_in", "gpio_out" } }, 110 { "PE17", 4, 17, { "gpio_in", "gpio_out" } }, 111 112 { "PF0", 5, 0, { "gpio_in", "gpio_out", "mmc0", "jtag" } }, 113 { "PF1", 5, 1, { "gpio_in", "gpio_out", "mmc0", "jtag" } }, 114 { "PF2", 5, 2, { "gpio_in", "gpio_out", "mmc0", "uart0" } }, 115 { "PF3", 5, 3, { "gpio_in", "gpio_out", "mmc0", "jtag" } }, 116 { "PF4", 5, 4, { "gpio_in", "gpio_out", "mmc0", "uart0" } }, 117 { "PF5", 5, 5, { "gpio_in", "gpio_out", "mmc0", "jtag" } }, 118 { "PF6", 5, 6, { "gpio_in", "gpio_out" } }, 119 120 { "PG0", 6, 0, { "gpio_in", "gpio_out", "mmc1", NULL, NULL, NULL, "pg_eint0" }, 6, 0, 1}, 121 { "PG1", 6, 1, { "gpio_in", "gpio_out", "mmc1", NULL, NULL, NULL, "pg_eint1" }, 6, 1, 1}, 122 { "PG2", 6, 2, { "gpio_in", "gpio_out", "mmc1", NULL, NULL, NULL, "pg_eint2" }, 6, 2, 1}, 123 { "PG3", 6, 3, { "gpio_in", "gpio_out", "mmc1", NULL, NULL, NULL, "pg_eint3" }, 6, 3, 1}, 124 { "PG4", 6, 4, { "gpio_in", "gpio_out", "mmc1", NULL, NULL, NULL, "pg_eint4" }, 6, 4, 1}, 125 { "PG5", 6, 5, { "gpio_in", "gpio_out", "mmc1", NULL, NULL, NULL, "pg_eint5" }, 6, 5, 1}, 126 { "PG6", 6, 6, { "gpio_in", "gpio_out", "uart1", NULL, NULL, NULL, "pg_eint6" }, 6, 6, 1}, 127 { "PG7", 6, 7, { "gpio_in", "gpio_out", "uart1", NULL, NULL, NULL, "pg_eint7" }, 6, 7, 1}, 128 { "PG8", 6, 8, { "gpio_in", "gpio_out", "uart1", NULL, NULL, NULL, "pg_eint8" }, 6, 8, 1}, 129 { "PG9", 6, 9, { "gpio_in", "gpio_out", "uart1", NULL, NULL, NULL, "pg_eint9" }, 6, 9, 1}, 130 { "PG10", 6, 10, { "gpio_in", "gpio_out", "aif3", "pcm1", NULL, NULL, "pg_eint10" }, 6, 10, 1}, 131 { "PG11", 6, 11, { "gpio_in", "gpio_out", "aif3", "pcm1", NULL, NULL, "pg_eint11" }, 6, 11, 1}, 132 { "PG12", 6, 12, { "gpio_in", "gpio_out", "aif3", "pcm1", NULL, NULL, "pg_eint12" }, 6, 12, 1}, 133 { "PG13", 6, 13, { "gpio_in", "gpio_out", "aif3", "pcm1", NULL, NULL, "pg_eint13" }, 6, 13, 1}, 134 135 { "PH0", 7, 0, { "gpio_in", "gpio_out", "i2c0", NULL, NULL, NULL, "ph_eint0" }, 6, 0, 2}, 136 { "PH1", 7, 1, { "gpio_in", "gpio_out", "i2c0", NULL, NULL, NULL, "ph_eint1" }, 6, 1, 2}, 137 { "PH2", 7, 2, { "gpio_in", "gpio_out", "i2c1", NULL, NULL, NULL, "ph_eint2" }, 6, 2, 2}, 138 { "PH3", 7, 3, { "gpio_in", "gpio_out", "i2c1", NULL, NULL, NULL, "ph_eint3" }, 6, 3, 2}, 139 { "PH4", 7, 4, { "gpio_in", "gpio_out", "uart3", NULL, NULL, NULL, "ph_eint4" }, 6, 4, 2}, 140 { "PH5", 7, 5, { "gpio_in", "gpio_out", "uart3", NULL, NULL, NULL, "ph_eint5" }, 6, 5, 2}, 141 { "PH6", 7, 6, { "gpio_in", "gpio_out", "uart3", NULL, NULL, NULL, "ph_eint6" }, 6, 6, 2}, 142 { "PH7", 7, 7, { "gpio_in", "gpio_out", "uart3", NULL, NULL, NULL, "ph_eint7" }, 6, 7, 2}, 143 { "PH8", 7, 8, { "gpio_in", "gpio_out", "owa", NULL, NULL, NULL, "ph_eint8" }, 6, 8, 2}, 144 { "PH9", 7, 9, { "gpio_in", "gpio_out", NULL, NULL, NULL, NULL, "ph_eint9" }, 6, 9, 2}, 145 { "PH10", 7, 10, { "gpio_in", "gpio_out", "mic", NULL, NULL, NULL, "ph_eint10" }, 6, 10, 2}, 146 { "PH11", 7, 11, { "gpio_in", "gpio_out", "mic", NULL, NULL, NULL, "ph_eint11" }, 6, 11, 2}, 147}; 148 149const struct allwinner_padconf a64_padconf = { 150 .npins = nitems(a64_pins), 151 .pins = a64_pins, 152}; 153 154#endif /* !SOC_ALLWINNER_A64 */ 155