1//===- MipsISelLowering.cpp - Mips DAG Lowering Implementation ------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the interfaces that Mips uses to lower LLVM code into a 10// selection DAG. 11// 12//===----------------------------------------------------------------------===// 13 14#include "MipsISelLowering.h" 15#include "MCTargetDesc/MipsBaseInfo.h" 16#include "MCTargetDesc/MipsInstPrinter.h" 17#include "MCTargetDesc/MipsMCTargetDesc.h" 18#include "MipsCCState.h" 19#include "MipsInstrInfo.h" 20#include "MipsMachineFunction.h" 21#include "MipsRegisterInfo.h" 22#include "MipsSubtarget.h" 23#include "MipsTargetMachine.h" 24#include "MipsTargetObjectFile.h" 25#include "llvm/ADT/APFloat.h" 26#include "llvm/ADT/ArrayRef.h" 27#include "llvm/ADT/SmallVector.h" 28#include "llvm/ADT/Statistic.h" 29#include "llvm/ADT/StringRef.h" 30#include "llvm/ADT/StringSwitch.h" 31#include "llvm/CodeGen/CallingConvLower.h" 32#include "llvm/CodeGen/FunctionLoweringInfo.h" 33#include "llvm/CodeGen/ISDOpcodes.h" 34#include "llvm/CodeGen/MachineBasicBlock.h" 35#include "llvm/CodeGen/MachineFrameInfo.h" 36#include "llvm/CodeGen/MachineFunction.h" 37#include "llvm/CodeGen/MachineInstr.h" 38#include "llvm/CodeGen/MachineInstrBuilder.h" 39#include "llvm/CodeGen/MachineJumpTableInfo.h" 40#include "llvm/CodeGen/MachineMemOperand.h" 41#include "llvm/CodeGen/MachineOperand.h" 42#include "llvm/CodeGen/MachineRegisterInfo.h" 43#include "llvm/CodeGen/MachineValueType.h" 44#include "llvm/CodeGen/RuntimeLibcalls.h" 45#include "llvm/CodeGen/SelectionDAG.h" 46#include "llvm/CodeGen/SelectionDAGNodes.h" 47#include "llvm/CodeGen/TargetFrameLowering.h" 48#include "llvm/CodeGen/TargetInstrInfo.h" 49#include "llvm/CodeGen/TargetRegisterInfo.h" 50#include "llvm/CodeGen/ValueTypes.h" 51#include "llvm/IR/CallingConv.h" 52#include "llvm/IR/Constants.h" 53#include "llvm/IR/DataLayout.h" 54#include "llvm/IR/DebugLoc.h" 55#include "llvm/IR/DerivedTypes.h" 56#include "llvm/IR/Function.h" 57#include "llvm/IR/GlobalValue.h" 58#include "llvm/IR/Type.h" 59#include "llvm/IR/Value.h" 60#include "llvm/MC/MCContext.h" 61#include "llvm/MC/MCRegisterInfo.h" 62#include "llvm/Support/Casting.h" 63#include "llvm/Support/CodeGen.h" 64#include "llvm/Support/CommandLine.h" 65#include "llvm/Support/Compiler.h" 66#include "llvm/Support/ErrorHandling.h" 67#include "llvm/Support/MathExtras.h" 68#include "llvm/Target/TargetMachine.h" 69#include "llvm/Target/TargetOptions.h" 70#include <algorithm> 71#include <cassert> 72#include <cctype> 73#include <cstdint> 74#include <deque> 75#include <iterator> 76#include <utility> 77#include <vector> 78 79using namespace llvm; 80 81#define DEBUG_TYPE "mips-lower" 82 83STATISTIC(NumTailCalls, "Number of tail calls"); 84 85static cl::opt<bool> 86NoZeroDivCheck("mno-check-zero-division", cl::Hidden, 87 cl::desc("MIPS: Don't trap on integer division by zero."), 88 cl::init(false)); 89 90extern cl::opt<bool> EmitJalrReloc; 91 92static const MCPhysReg Mips64DPRegs[8] = { 93 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, 94 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64 95}; 96 97// The MIPS MSA ABI passes vector arguments in the integer register set. 98// The number of integer registers used is dependant on the ABI used. 99MVT MipsTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context, 100 CallingConv::ID CC, 101 EVT VT) const { 102 if (!VT.isVector()) 103 return getRegisterType(Context, VT); 104 105 if (VT.isPow2VectorType() && VT.getVectorElementType().isRound()) 106 return Subtarget.isABI_O32() || VT.getSizeInBits() == 32 ? MVT::i32 107 : MVT::i64; 108 return getRegisterType(Context, VT.getVectorElementType()); 109} 110 111unsigned MipsTargetLowering::getNumRegistersForCallingConv(LLVMContext &Context, 112 CallingConv::ID CC, 113 EVT VT) const { 114 if (VT.isVector()) { 115 if (VT.isPow2VectorType() && VT.getVectorElementType().isRound()) 116 return divideCeil(VT.getSizeInBits(), Subtarget.isABI_O32() ? 32 : 64); 117 return VT.getVectorNumElements() * 118 getNumRegisters(Context, VT.getVectorElementType()); 119 } 120 return MipsTargetLowering::getNumRegisters(Context, VT); 121} 122 123unsigned MipsTargetLowering::getVectorTypeBreakdownForCallingConv( 124 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, 125 unsigned &NumIntermediates, MVT &RegisterVT) const { 126 if (VT.isPow2VectorType()) { 127 IntermediateVT = getRegisterTypeForCallingConv(Context, CC, VT); 128 RegisterVT = IntermediateVT.getSimpleVT(); 129 NumIntermediates = getNumRegistersForCallingConv(Context, CC, VT); 130 return NumIntermediates; 131 } 132 IntermediateVT = VT.getVectorElementType(); 133 NumIntermediates = VT.getVectorNumElements(); 134 RegisterVT = getRegisterType(Context, IntermediateVT); 135 return NumIntermediates * getNumRegisters(Context, IntermediateVT); 136} 137 138SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const { 139 MachineFunction &MF = DAG.getMachineFunction(); 140 MipsFunctionInfo *FI = MF.getInfo<MipsFunctionInfo>(); 141 return DAG.getRegister(FI->getGlobalBaseReg(MF), Ty); 142} 143 144SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty, 145 SelectionDAG &DAG, 146 unsigned Flag) const { 147 return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag); 148} 149 150SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty, 151 SelectionDAG &DAG, 152 unsigned Flag) const { 153 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag); 154} 155 156SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty, 157 SelectionDAG &DAG, 158 unsigned Flag) const { 159 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag); 160} 161 162SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty, 163 SelectionDAG &DAG, 164 unsigned Flag) const { 165 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag); 166} 167 168SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty, 169 SelectionDAG &DAG, 170 unsigned Flag) const { 171 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlign(), 172 N->getOffset(), Flag); 173} 174 175const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { 176 switch ((MipsISD::NodeType)Opcode) { 177 case MipsISD::FIRST_NUMBER: break; 178 case MipsISD::JmpLink: return "MipsISD::JmpLink"; 179 case MipsISD::TailCall: return "MipsISD::TailCall"; 180 case MipsISD::Highest: return "MipsISD::Highest"; 181 case MipsISD::Higher: return "MipsISD::Higher"; 182 case MipsISD::Hi: return "MipsISD::Hi"; 183 case MipsISD::Lo: return "MipsISD::Lo"; 184 case MipsISD::GotHi: return "MipsISD::GotHi"; 185 case MipsISD::TlsHi: return "MipsISD::TlsHi"; 186 case MipsISD::GPRel: return "MipsISD::GPRel"; 187 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer"; 188 case MipsISD::Ret: return "MipsISD::Ret"; 189 case MipsISD::ERet: return "MipsISD::ERet"; 190 case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN"; 191 case MipsISD::FAbs: return "MipsISD::FAbs"; 192 case MipsISD::FMS: return "MipsISD::FMS"; 193 case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; 194 case MipsISD::FPCmp: return "MipsISD::FPCmp"; 195 case MipsISD::FSELECT: return "MipsISD::FSELECT"; 196 case MipsISD::MTC1_D64: return "MipsISD::MTC1_D64"; 197 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; 198 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; 199 case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP"; 200 case MipsISD::MFHI: return "MipsISD::MFHI"; 201 case MipsISD::MFLO: return "MipsISD::MFLO"; 202 case MipsISD::MTLOHI: return "MipsISD::MTLOHI"; 203 case MipsISD::Mult: return "MipsISD::Mult"; 204 case MipsISD::Multu: return "MipsISD::Multu"; 205 case MipsISD::MAdd: return "MipsISD::MAdd"; 206 case MipsISD::MAddu: return "MipsISD::MAddu"; 207 case MipsISD::MSub: return "MipsISD::MSub"; 208 case MipsISD::MSubu: return "MipsISD::MSubu"; 209 case MipsISD::DivRem: return "MipsISD::DivRem"; 210 case MipsISD::DivRemU: return "MipsISD::DivRemU"; 211 case MipsISD::DivRem16: return "MipsISD::DivRem16"; 212 case MipsISD::DivRemU16: return "MipsISD::DivRemU16"; 213 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; 214 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; 215 case MipsISD::Wrapper: return "MipsISD::Wrapper"; 216 case MipsISD::DynAlloc: return "MipsISD::DynAlloc"; 217 case MipsISD::Sync: return "MipsISD::Sync"; 218 case MipsISD::Ext: return "MipsISD::Ext"; 219 case MipsISD::Ins: return "MipsISD::Ins"; 220 case MipsISD::CIns: return "MipsISD::CIns"; 221 case MipsISD::LWL: return "MipsISD::LWL"; 222 case MipsISD::LWR: return "MipsISD::LWR"; 223 case MipsISD::SWL: return "MipsISD::SWL"; 224 case MipsISD::SWR: return "MipsISD::SWR"; 225 case MipsISD::LDL: return "MipsISD::LDL"; 226 case MipsISD::LDR: return "MipsISD::LDR"; 227 case MipsISD::SDL: return "MipsISD::SDL"; 228 case MipsISD::SDR: return "MipsISD::SDR"; 229 case MipsISD::EXTP: return "MipsISD::EXTP"; 230 case MipsISD::EXTPDP: return "MipsISD::EXTPDP"; 231 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H"; 232 case MipsISD::EXTR_W: return "MipsISD::EXTR_W"; 233 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W"; 234 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W"; 235 case MipsISD::SHILO: return "MipsISD::SHILO"; 236 case MipsISD::MTHLIP: return "MipsISD::MTHLIP"; 237 case MipsISD::MULSAQ_S_W_PH: return "MipsISD::MULSAQ_S_W_PH"; 238 case MipsISD::MAQ_S_W_PHL: return "MipsISD::MAQ_S_W_PHL"; 239 case MipsISD::MAQ_S_W_PHR: return "MipsISD::MAQ_S_W_PHR"; 240 case MipsISD::MAQ_SA_W_PHL: return "MipsISD::MAQ_SA_W_PHL"; 241 case MipsISD::MAQ_SA_W_PHR: return "MipsISD::MAQ_SA_W_PHR"; 242 case MipsISD::DPAU_H_QBL: return "MipsISD::DPAU_H_QBL"; 243 case MipsISD::DPAU_H_QBR: return "MipsISD::DPAU_H_QBR"; 244 case MipsISD::DPSU_H_QBL: return "MipsISD::DPSU_H_QBL"; 245 case MipsISD::DPSU_H_QBR: return "MipsISD::DPSU_H_QBR"; 246 case MipsISD::DPAQ_S_W_PH: return "MipsISD::DPAQ_S_W_PH"; 247 case MipsISD::DPSQ_S_W_PH: return "MipsISD::DPSQ_S_W_PH"; 248 case MipsISD::DPAQ_SA_L_W: return "MipsISD::DPAQ_SA_L_W"; 249 case MipsISD::DPSQ_SA_L_W: return "MipsISD::DPSQ_SA_L_W"; 250 case MipsISD::DPA_W_PH: return "MipsISD::DPA_W_PH"; 251 case MipsISD::DPS_W_PH: return "MipsISD::DPS_W_PH"; 252 case MipsISD::DPAQX_S_W_PH: return "MipsISD::DPAQX_S_W_PH"; 253 case MipsISD::DPAQX_SA_W_PH: return "MipsISD::DPAQX_SA_W_PH"; 254 case MipsISD::DPAX_W_PH: return "MipsISD::DPAX_W_PH"; 255 case MipsISD::DPSX_W_PH: return "MipsISD::DPSX_W_PH"; 256 case MipsISD::DPSQX_S_W_PH: return "MipsISD::DPSQX_S_W_PH"; 257 case MipsISD::DPSQX_SA_W_PH: return "MipsISD::DPSQX_SA_W_PH"; 258 case MipsISD::MULSA_W_PH: return "MipsISD::MULSA_W_PH"; 259 case MipsISD::MULT: return "MipsISD::MULT"; 260 case MipsISD::MULTU: return "MipsISD::MULTU"; 261 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP"; 262 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP"; 263 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP"; 264 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP"; 265 case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP"; 266 case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP"; 267 case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP"; 268 case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP"; 269 case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP"; 270 case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO"; 271 case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO"; 272 case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO"; 273 case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO"; 274 case MipsISD::VCEQ: return "MipsISD::VCEQ"; 275 case MipsISD::VCLE_S: return "MipsISD::VCLE_S"; 276 case MipsISD::VCLE_U: return "MipsISD::VCLE_U"; 277 case MipsISD::VCLT_S: return "MipsISD::VCLT_S"; 278 case MipsISD::VCLT_U: return "MipsISD::VCLT_U"; 279 case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT"; 280 case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT"; 281 case MipsISD::VNOR: return "MipsISD::VNOR"; 282 case MipsISD::VSHF: return "MipsISD::VSHF"; 283 case MipsISD::SHF: return "MipsISD::SHF"; 284 case MipsISD::ILVEV: return "MipsISD::ILVEV"; 285 case MipsISD::ILVOD: return "MipsISD::ILVOD"; 286 case MipsISD::ILVL: return "MipsISD::ILVL"; 287 case MipsISD::ILVR: return "MipsISD::ILVR"; 288 case MipsISD::PCKEV: return "MipsISD::PCKEV"; 289 case MipsISD::PCKOD: return "MipsISD::PCKOD"; 290 case MipsISD::INSVE: return "MipsISD::INSVE"; 291 } 292 return nullptr; 293} 294 295MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM, 296 const MipsSubtarget &STI) 297 : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) { 298 // Mips does not have i1 type, so use i32 for 299 // setcc operations results (slt, sgt, ...). 300 setBooleanContents(ZeroOrOneBooleanContent); 301 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 302 // The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA 303 // does. Integer booleans still use 0 and 1. 304 if (Subtarget.hasMips32r6()) 305 setBooleanContents(ZeroOrOneBooleanContent, 306 ZeroOrNegativeOneBooleanContent); 307 308 // Load extented operations for i1 types must be promoted 309 for (MVT VT : MVT::integer_valuetypes()) { 310 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); 311 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); 312 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); 313 } 314 315 // MIPS doesn't have extending float->double load/store. Set LoadExtAction 316 // for f32, f16 317 for (MVT VT : MVT::fp_valuetypes()) { 318 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); 319 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand); 320 } 321 322 // Set LoadExtAction for f16 vectors to Expand 323 for (MVT VT : MVT::fp_fixedlen_vector_valuetypes()) { 324 MVT F16VT = MVT::getVectorVT(MVT::f16, VT.getVectorNumElements()); 325 if (F16VT.isValid()) 326 setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand); 327 } 328 329 setTruncStoreAction(MVT::f32, MVT::f16, Expand); 330 setTruncStoreAction(MVT::f64, MVT::f16, Expand); 331 332 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 333 334 // Used by legalize types to correctly generate the setcc result. 335 // Without this, every float setcc comes with a AND/OR with the result, 336 // we don't want this, since the fpcmp result goes to a flag register, 337 // which is used implicitly by brcond and select operations. 338 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 339 340 // Mips Custom Operations 341 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 342 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 343 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 344 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 345 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 346 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 347 setOperationAction(ISD::SELECT, MVT::f32, Custom); 348 setOperationAction(ISD::SELECT, MVT::f64, Custom); 349 setOperationAction(ISD::SELECT, MVT::i32, Custom); 350 setOperationAction(ISD::SETCC, MVT::f32, Custom); 351 setOperationAction(ISD::SETCC, MVT::f64, Custom); 352 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 353 setOperationAction(ISD::FABS, MVT::f32, Custom); 354 setOperationAction(ISD::FABS, MVT::f64, Custom); 355 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 356 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 357 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 358 359 if (Subtarget.isGP64bit()) { 360 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 361 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 362 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 363 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 364 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 365 setOperationAction(ISD::SELECT, MVT::i64, Custom); 366 setOperationAction(ISD::LOAD, MVT::i64, Custom); 367 setOperationAction(ISD::STORE, MVT::i64, Custom); 368 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 369 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); 370 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); 371 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); 372 } 373 374 if (!Subtarget.isGP64bit()) { 375 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 376 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 377 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 378 } 379 380 setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom); 381 if (Subtarget.isGP64bit()) 382 setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom); 383 384 setOperationAction(ISD::SDIV, MVT::i32, Expand); 385 setOperationAction(ISD::SREM, MVT::i32, Expand); 386 setOperationAction(ISD::UDIV, MVT::i32, Expand); 387 setOperationAction(ISD::UREM, MVT::i32, Expand); 388 setOperationAction(ISD::SDIV, MVT::i64, Expand); 389 setOperationAction(ISD::SREM, MVT::i64, Expand); 390 setOperationAction(ISD::UDIV, MVT::i64, Expand); 391 setOperationAction(ISD::UREM, MVT::i64, Expand); 392 393 // Operations not directly supported by Mips. 394 setOperationAction(ISD::BR_CC, MVT::f32, Expand); 395 setOperationAction(ISD::BR_CC, MVT::f64, Expand); 396 setOperationAction(ISD::BR_CC, MVT::i32, Expand); 397 setOperationAction(ISD::BR_CC, MVT::i64, Expand); 398 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); 399 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); 400 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); 401 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); 402 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 403 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 404 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 405 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 406 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 407 if (Subtarget.hasCnMips()) { 408 setOperationAction(ISD::CTPOP, MVT::i32, Legal); 409 setOperationAction(ISD::CTPOP, MVT::i64, Legal); 410 } else { 411 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 412 setOperationAction(ISD::CTPOP, MVT::i64, Expand); 413 } 414 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 415 setOperationAction(ISD::CTTZ, MVT::i64, Expand); 416 setOperationAction(ISD::ROTL, MVT::i32, Expand); 417 setOperationAction(ISD::ROTL, MVT::i64, Expand); 418 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 419 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 420 421 if (!Subtarget.hasMips32r2()) 422 setOperationAction(ISD::ROTR, MVT::i32, Expand); 423 424 if (!Subtarget.hasMips64r2()) 425 setOperationAction(ISD::ROTR, MVT::i64, Expand); 426 427 setOperationAction(ISD::FSIN, MVT::f32, Expand); 428 setOperationAction(ISD::FSIN, MVT::f64, Expand); 429 setOperationAction(ISD::FCOS, MVT::f32, Expand); 430 setOperationAction(ISD::FCOS, MVT::f64, Expand); 431 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); 432 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); 433 setOperationAction(ISD::FPOW, MVT::f32, Expand); 434 setOperationAction(ISD::FPOW, MVT::f64, Expand); 435 setOperationAction(ISD::FLOG, MVT::f32, Expand); 436 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 437 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 438 setOperationAction(ISD::FEXP, MVT::f32, Expand); 439 setOperationAction(ISD::FMA, MVT::f32, Expand); 440 setOperationAction(ISD::FMA, MVT::f64, Expand); 441 setOperationAction(ISD::FREM, MVT::f32, Expand); 442 setOperationAction(ISD::FREM, MVT::f64, Expand); 443 444 // Lower f16 conversion operations into library calls 445 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand); 446 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); 447 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); 448 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); 449 450 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom); 451 452 setOperationAction(ISD::VASTART, MVT::Other, Custom); 453 setOperationAction(ISD::VAARG, MVT::Other, Custom); 454 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 455 setOperationAction(ISD::VAEND, MVT::Other, Expand); 456 457 // Use the default for now 458 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 459 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 460 461 if (!Subtarget.isGP64bit()) { 462 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); 463 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); 464 } 465 466 if (!Subtarget.hasMips32r2()) { 467 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 468 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 469 } 470 471 // MIPS16 lacks MIPS32's clz and clo instructions. 472 if (!Subtarget.hasMips32() || Subtarget.inMips16Mode()) 473 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 474 if (!Subtarget.hasMips64()) 475 setOperationAction(ISD::CTLZ, MVT::i64, Expand); 476 477 if (!Subtarget.hasMips32r2()) 478 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 479 if (!Subtarget.hasMips64r2()) 480 setOperationAction(ISD::BSWAP, MVT::i64, Expand); 481 482 if (Subtarget.isGP64bit()) { 483 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, MVT::i32, Custom); 484 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom); 485 setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom); 486 setTruncStoreAction(MVT::i64, MVT::i32, Custom); 487 } 488 489 setOperationAction(ISD::TRAP, MVT::Other, Legal); 490 491 setTargetDAGCombine({ISD::SDIVREM, ISD::UDIVREM, ISD::SELECT, ISD::AND, 492 ISD::OR, ISD::ADD, ISD::SUB, ISD::AssertZext, ISD::SHL}); 493 494 if (ABI.IsO32()) { 495 // These libcalls are not available in 32-bit. 496 setLibcallName(RTLIB::SHL_I128, nullptr); 497 setLibcallName(RTLIB::SRL_I128, nullptr); 498 setLibcallName(RTLIB::SRA_I128, nullptr); 499 setLibcallName(RTLIB::MUL_I128, nullptr); 500 setLibcallName(RTLIB::MULO_I64, nullptr); 501 setLibcallName(RTLIB::MULO_I128, nullptr); 502 } 503 504 if (Subtarget.isGP64bit()) 505 setMaxAtomicSizeInBitsSupported(64); 506 else 507 setMaxAtomicSizeInBitsSupported(32); 508 509 setMinFunctionAlignment(Subtarget.isGP64bit() ? Align(8) : Align(4)); 510 511 // The arguments on the stack are defined in terms of 4-byte slots on O32 512 // and 8-byte slots on N32/N64. 513 setMinStackArgumentAlignment((ABI.IsN32() || ABI.IsN64()) ? Align(8) 514 : Align(4)); 515 516 setStackPointerRegisterToSaveRestore(ABI.IsN64() ? Mips::SP_64 : Mips::SP); 517 518 MaxStoresPerMemcpy = 16; 519 520 isMicroMips = Subtarget.inMicroMipsMode(); 521} 522 523const MipsTargetLowering * 524MipsTargetLowering::create(const MipsTargetMachine &TM, 525 const MipsSubtarget &STI) { 526 if (STI.inMips16Mode()) 527 return createMips16TargetLowering(TM, STI); 528 529 return createMipsSETargetLowering(TM, STI); 530} 531 532// Create a fast isel object. 533FastISel * 534MipsTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo, 535 const TargetLibraryInfo *libInfo) const { 536 const MipsTargetMachine &TM = 537 static_cast<const MipsTargetMachine &>(funcInfo.MF->getTarget()); 538 539 // We support only the standard encoding [MIPS32,MIPS32R5] ISAs. 540 bool UseFastISel = TM.Options.EnableFastISel && Subtarget.hasMips32() && 541 !Subtarget.hasMips32r6() && !Subtarget.inMips16Mode() && 542 !Subtarget.inMicroMipsMode(); 543 544 // Disable if either of the following is true: 545 // We do not generate PIC, the ABI is not O32, XGOT is being used. 546 if (!TM.isPositionIndependent() || !TM.getABI().IsO32() || 547 Subtarget.useXGOT()) 548 UseFastISel = false; 549 550 return UseFastISel ? Mips::createFastISel(funcInfo, libInfo) : nullptr; 551} 552 553EVT MipsTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &, 554 EVT VT) const { 555 if (!VT.isVector()) 556 return MVT::i32; 557 return VT.changeVectorElementTypeToInteger(); 558} 559 560static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG, 561 TargetLowering::DAGCombinerInfo &DCI, 562 const MipsSubtarget &Subtarget) { 563 if (DCI.isBeforeLegalizeOps()) 564 return SDValue(); 565 566 EVT Ty = N->getValueType(0); 567 unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64; 568 unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64; 569 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 : 570 MipsISD::DivRemU16; 571 SDLoc DL(N); 572 573 SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue, 574 N->getOperand(0), N->getOperand(1)); 575 SDValue InChain = DAG.getEntryNode(); 576 SDValue InGlue = DivRem; 577 578 // insert MFLO 579 if (N->hasAnyUseOfValue(0)) { 580 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty, 581 InGlue); 582 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo); 583 InChain = CopyFromLo.getValue(1); 584 InGlue = CopyFromLo.getValue(2); 585 } 586 587 // insert MFHI 588 if (N->hasAnyUseOfValue(1)) { 589 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL, 590 HI, Ty, InGlue); 591 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi); 592 } 593 594 return SDValue(); 595} 596 597static Mips::CondCode condCodeToFCC(ISD::CondCode CC) { 598 switch (CC) { 599 default: llvm_unreachable("Unknown fp condition code!"); 600 case ISD::SETEQ: 601 case ISD::SETOEQ: return Mips::FCOND_OEQ; 602 case ISD::SETUNE: return Mips::FCOND_UNE; 603 case ISD::SETLT: 604 case ISD::SETOLT: return Mips::FCOND_OLT; 605 case ISD::SETGT: 606 case ISD::SETOGT: return Mips::FCOND_OGT; 607 case ISD::SETLE: 608 case ISD::SETOLE: return Mips::FCOND_OLE; 609 case ISD::SETGE: 610 case ISD::SETOGE: return Mips::FCOND_OGE; 611 case ISD::SETULT: return Mips::FCOND_ULT; 612 case ISD::SETULE: return Mips::FCOND_ULE; 613 case ISD::SETUGT: return Mips::FCOND_UGT; 614 case ISD::SETUGE: return Mips::FCOND_UGE; 615 case ISD::SETUO: return Mips::FCOND_UN; 616 case ISD::SETO: return Mips::FCOND_OR; 617 case ISD::SETNE: 618 case ISD::SETONE: return Mips::FCOND_ONE; 619 case ISD::SETUEQ: return Mips::FCOND_UEQ; 620 } 621} 622 623/// This function returns true if the floating point conditional branches and 624/// conditional moves which use condition code CC should be inverted. 625static bool invertFPCondCodeUser(Mips::CondCode CC) { 626 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 627 return false; 628 629 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && 630 "Illegal Condition Code"); 631 632 return true; 633} 634 635// Creates and returns an FPCmp node from a setcc node. 636// Returns Op if setcc is not a floating point comparison. 637static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) { 638 // must be a SETCC node 639 if (Op.getOpcode() != ISD::SETCC) 640 return Op; 641 642 SDValue LHS = Op.getOperand(0); 643 644 if (!LHS.getValueType().isFloatingPoint()) 645 return Op; 646 647 SDValue RHS = Op.getOperand(1); 648 SDLoc DL(Op); 649 650 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of 651 // node if necessary. 652 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 653 654 return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS, 655 DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32)); 656} 657 658// Creates and returns a CMovFPT/F node. 659static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, 660 SDValue False, const SDLoc &DL) { 661 ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2)); 662 bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue()); 663 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 664 665 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, 666 True.getValueType(), True, FCC0, False, Cond); 667} 668 669static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, 670 TargetLowering::DAGCombinerInfo &DCI, 671 const MipsSubtarget &Subtarget) { 672 if (DCI.isBeforeLegalizeOps()) 673 return SDValue(); 674 675 SDValue SetCC = N->getOperand(0); 676 677 if ((SetCC.getOpcode() != ISD::SETCC) || 678 !SetCC.getOperand(0).getValueType().isInteger()) 679 return SDValue(); 680 681 SDValue False = N->getOperand(2); 682 EVT FalseTy = False.getValueType(); 683 684 if (!FalseTy.isInteger()) 685 return SDValue(); 686 687 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False); 688 689 // If the RHS (False) is 0, we swap the order of the operands 690 // of ISD::SELECT (obviously also inverting the condition) so that we can 691 // take advantage of conditional moves using the $0 register. 692 // Example: 693 // return (a != 0) ? x : 0; 694 // load $reg, x 695 // movz $reg, $0, a 696 if (!FalseC) 697 return SDValue(); 698 699 const SDLoc DL(N); 700 701 if (!FalseC->getZExtValue()) { 702 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 703 SDValue True = N->getOperand(1); 704 705 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 706 SetCC.getOperand(1), 707 ISD::getSetCCInverse(CC, SetCC.getValueType())); 708 709 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); 710 } 711 712 // If both operands are integer constants there's a possibility that we 713 // can do some interesting optimizations. 714 SDValue True = N->getOperand(1); 715 ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(True); 716 717 if (!TrueC || !True.getValueType().isInteger()) 718 return SDValue(); 719 720 // We'll also ignore MVT::i64 operands as this optimizations proves 721 // to be ineffective because of the required sign extensions as the result 722 // of a SETCC operator is always MVT::i32 for non-vector types. 723 if (True.getValueType() == MVT::i64) 724 return SDValue(); 725 726 int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue(); 727 728 // 1) (a < x) ? y : y-1 729 // slti $reg1, a, x 730 // addiu $reg2, $reg1, y-1 731 if (Diff == 1) 732 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False); 733 734 // 2) (a < x) ? y-1 : y 735 // slti $reg1, a, x 736 // xor $reg1, $reg1, 1 737 // addiu $reg2, $reg1, y-1 738 if (Diff == -1) { 739 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 740 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 741 SetCC.getOperand(1), 742 ISD::getSetCCInverse(CC, SetCC.getValueType())); 743 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True); 744 } 745 746 // Could not optimize. 747 return SDValue(); 748} 749 750static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG, 751 TargetLowering::DAGCombinerInfo &DCI, 752 const MipsSubtarget &Subtarget) { 753 if (DCI.isBeforeLegalizeOps()) 754 return SDValue(); 755 756 SDValue ValueIfTrue = N->getOperand(0), ValueIfFalse = N->getOperand(2); 757 758 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(ValueIfFalse); 759 if (!FalseC || FalseC->getZExtValue()) 760 return SDValue(); 761 762 // Since RHS (False) is 0, we swap the order of the True/False operands 763 // (obviously also inverting the condition) so that we can 764 // take advantage of conditional moves using the $0 register. 765 // Example: 766 // return (a != 0) ? x : 0; 767 // load $reg, x 768 // movz $reg, $0, a 769 unsigned Opc = (N->getOpcode() == MipsISD::CMovFP_T) ? MipsISD::CMovFP_F : 770 MipsISD::CMovFP_T; 771 772 SDValue FCC = N->getOperand(1), Glue = N->getOperand(3); 773 return DAG.getNode(Opc, SDLoc(N), ValueIfFalse.getValueType(), 774 ValueIfFalse, FCC, ValueIfTrue, Glue); 775} 776 777static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, 778 TargetLowering::DAGCombinerInfo &DCI, 779 const MipsSubtarget &Subtarget) { 780 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) 781 return SDValue(); 782 783 SDValue FirstOperand = N->getOperand(0); 784 unsigned FirstOperandOpc = FirstOperand.getOpcode(); 785 SDValue Mask = N->getOperand(1); 786 EVT ValTy = N->getValueType(0); 787 SDLoc DL(N); 788 789 uint64_t Pos = 0; 790 unsigned SMPos, SMSize; 791 ConstantSDNode *CN; 792 SDValue NewOperand; 793 unsigned Opc; 794 795 // Op's second operand must be a shifted mask. 796 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) || 797 !isShiftedMask_64(CN->getZExtValue(), SMPos, SMSize)) 798 return SDValue(); 799 800 if (FirstOperandOpc == ISD::SRA || FirstOperandOpc == ISD::SRL) { 801 // Pattern match EXT. 802 // $dst = and ((sra or srl) $src , pos), (2**size - 1) 803 // => ext $dst, $src, pos, size 804 805 // The second operand of the shift must be an immediate. 806 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1)))) 807 return SDValue(); 808 809 Pos = CN->getZExtValue(); 810 811 // Return if the shifted mask does not start at bit 0 or the sum of its size 812 // and Pos exceeds the word's size. 813 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits()) 814 return SDValue(); 815 816 Opc = MipsISD::Ext; 817 NewOperand = FirstOperand.getOperand(0); 818 } else if (FirstOperandOpc == ISD::SHL && Subtarget.hasCnMips()) { 819 // Pattern match CINS. 820 // $dst = and (shl $src , pos), mask 821 // => cins $dst, $src, pos, size 822 // mask is a shifted mask with consecutive 1's, pos = shift amount, 823 // size = population count. 824 825 // The second operand of the shift must be an immediate. 826 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1)))) 827 return SDValue(); 828 829 Pos = CN->getZExtValue(); 830 831 if (SMPos != Pos || Pos >= ValTy.getSizeInBits() || SMSize >= 32 || 832 Pos + SMSize > ValTy.getSizeInBits()) 833 return SDValue(); 834 835 NewOperand = FirstOperand.getOperand(0); 836 // SMSize is 'location' (position) in this case, not size. 837 SMSize--; 838 Opc = MipsISD::CIns; 839 } else { 840 // Pattern match EXT. 841 // $dst = and $src, (2**size - 1) , if size > 16 842 // => ext $dst, $src, pos, size , pos = 0 843 844 // If the mask is <= 0xffff, andi can be used instead. 845 if (CN->getZExtValue() <= 0xffff) 846 return SDValue(); 847 848 // Return if the mask doesn't start at position 0. 849 if (SMPos) 850 return SDValue(); 851 852 Opc = MipsISD::Ext; 853 NewOperand = FirstOperand; 854 } 855 return DAG.getNode(Opc, DL, ValTy, NewOperand, 856 DAG.getConstant(Pos, DL, MVT::i32), 857 DAG.getConstant(SMSize, DL, MVT::i32)); 858} 859 860static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, 861 TargetLowering::DAGCombinerInfo &DCI, 862 const MipsSubtarget &Subtarget) { 863 // Pattern match INS. 864 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1), 865 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1 866 // => ins $dst, $src, size, pos, $src1 867 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) 868 return SDValue(); 869 870 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); 871 unsigned SMPos0, SMSize0, SMPos1, SMSize1; 872 ConstantSDNode *CN, *CN1; 873 874 // See if Op's first operand matches (and $src1 , mask0). 875 if (And0.getOpcode() != ISD::AND) 876 return SDValue(); 877 878 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) || 879 !isShiftedMask_64(~CN->getSExtValue(), SMPos0, SMSize0)) 880 return SDValue(); 881 882 // See if Op's second operand matches (and (shl $src, pos), mask1). 883 if (And1.getOpcode() == ISD::AND && 884 And1.getOperand(0).getOpcode() == ISD::SHL) { 885 886 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) || 887 !isShiftedMask_64(CN->getZExtValue(), SMPos1, SMSize1)) 888 return SDValue(); 889 890 // The shift masks must have the same position and size. 891 if (SMPos0 != SMPos1 || SMSize0 != SMSize1) 892 return SDValue(); 893 894 SDValue Shl = And1.getOperand(0); 895 896 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1)))) 897 return SDValue(); 898 899 unsigned Shamt = CN->getZExtValue(); 900 901 // Return if the shift amount and the first bit position of mask are not the 902 // same. 903 EVT ValTy = N->getValueType(0); 904 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits())) 905 return SDValue(); 906 907 SDLoc DL(N); 908 return DAG.getNode(MipsISD::Ins, DL, ValTy, Shl.getOperand(0), 909 DAG.getConstant(SMPos0, DL, MVT::i32), 910 DAG.getConstant(SMSize0, DL, MVT::i32), 911 And0.getOperand(0)); 912 } else { 913 // Pattern match DINS. 914 // $dst = or (and $src, mask0), mask1 915 // where mask0 = ((1 << SMSize0) -1) << SMPos0 916 // => dins $dst, $src, pos, size 917 if (~CN->getSExtValue() == ((((int64_t)1 << SMSize0) - 1) << SMPos0) && 918 ((SMSize0 + SMPos0 <= 64 && Subtarget.hasMips64r2()) || 919 (SMSize0 + SMPos0 <= 32))) { 920 // Check if AND instruction has constant as argument 921 bool isConstCase = And1.getOpcode() != ISD::AND; 922 if (And1.getOpcode() == ISD::AND) { 923 if (!(CN1 = dyn_cast<ConstantSDNode>(And1->getOperand(1)))) 924 return SDValue(); 925 } else { 926 if (!(CN1 = dyn_cast<ConstantSDNode>(N->getOperand(1)))) 927 return SDValue(); 928 } 929 // Don't generate INS if constant OR operand doesn't fit into bits 930 // cleared by constant AND operand. 931 if (CN->getSExtValue() & CN1->getSExtValue()) 932 return SDValue(); 933 934 SDLoc DL(N); 935 EVT ValTy = N->getOperand(0)->getValueType(0); 936 SDValue Const1; 937 SDValue SrlX; 938 if (!isConstCase) { 939 Const1 = DAG.getConstant(SMPos0, DL, MVT::i32); 940 SrlX = DAG.getNode(ISD::SRL, DL, And1->getValueType(0), And1, Const1); 941 } 942 return DAG.getNode( 943 MipsISD::Ins, DL, N->getValueType(0), 944 isConstCase 945 ? DAG.getConstant(CN1->getSExtValue() >> SMPos0, DL, ValTy) 946 : SrlX, 947 DAG.getConstant(SMPos0, DL, MVT::i32), 948 DAG.getConstant(ValTy.getSizeInBits() / 8 < 8 ? SMSize0 & 31 949 : SMSize0, 950 DL, MVT::i32), 951 And0->getOperand(0)); 952 953 } 954 return SDValue(); 955 } 956} 957 958static SDValue performMADD_MSUBCombine(SDNode *ROOTNode, SelectionDAG &CurDAG, 959 const MipsSubtarget &Subtarget) { 960 // ROOTNode must have a multiplication as an operand for the match to be 961 // successful. 962 if (ROOTNode->getOperand(0).getOpcode() != ISD::MUL && 963 ROOTNode->getOperand(1).getOpcode() != ISD::MUL) 964 return SDValue(); 965 966 // In the case where we have a multiplication as the left operand of 967 // of a subtraction, we can't combine into a MipsISD::MSub node as the 968 // the instruction definition of msub(u) places the multiplication on 969 // on the right. 970 if (ROOTNode->getOpcode() == ISD::SUB && 971 ROOTNode->getOperand(0).getOpcode() == ISD::MUL) 972 return SDValue(); 973 974 // We don't handle vector types here. 975 if (ROOTNode->getValueType(0).isVector()) 976 return SDValue(); 977 978 // For MIPS64, madd / msub instructions are inefficent to use with 64 bit 979 // arithmetic. E.g. 980 // (add (mul a b) c) => 981 // let res = (madd (mthi (drotr c 32))x(mtlo c) a b) in 982 // MIPS64: (or (dsll (mfhi res) 32) (dsrl (dsll (mflo res) 32) 32) 983 // or 984 // MIPS64R2: (dins (mflo res) (mfhi res) 32 32) 985 // 986 // The overhead of setting up the Hi/Lo registers and reassembling the 987 // result makes this a dubious optimzation for MIPS64. The core of the 988 // problem is that Hi/Lo contain the upper and lower 32 bits of the 989 // operand and result. 990 // 991 // It requires a chain of 4 add/mul for MIPS64R2 to get better code 992 // density than doing it naively, 5 for MIPS64. Additionally, using 993 // madd/msub on MIPS64 requires the operands actually be 32 bit sign 994 // extended operands, not true 64 bit values. 995 // 996 // FIXME: For the moment, disable this completely for MIPS64. 997 if (Subtarget.hasMips64()) 998 return SDValue(); 999 1000 SDValue Mult = ROOTNode->getOperand(0).getOpcode() == ISD::MUL 1001 ? ROOTNode->getOperand(0) 1002 : ROOTNode->getOperand(1); 1003 1004 SDValue AddOperand = ROOTNode->getOperand(0).getOpcode() == ISD::MUL 1005 ? ROOTNode->getOperand(1) 1006 : ROOTNode->getOperand(0); 1007 1008 // Transform this to a MADD only if the user of this node is the add. 1009 // If there are other users of the mul, this function returns here. 1010 if (!Mult.hasOneUse()) 1011 return SDValue(); 1012 1013 // maddu and madd are unusual instructions in that on MIPS64 bits 63..31 1014 // must be in canonical form, i.e. sign extended. For MIPS32, the operands 1015 // of the multiply must have 32 or more sign bits, otherwise we cannot 1016 // perform this optimization. We have to check this here as we're performing 1017 // this optimization pre-legalization. 1018 SDValue MultLHS = Mult->getOperand(0); 1019 SDValue MultRHS = Mult->getOperand(1); 1020 1021 bool IsSigned = MultLHS->getOpcode() == ISD::SIGN_EXTEND && 1022 MultRHS->getOpcode() == ISD::SIGN_EXTEND; 1023 bool IsUnsigned = MultLHS->getOpcode() == ISD::ZERO_EXTEND && 1024 MultRHS->getOpcode() == ISD::ZERO_EXTEND; 1025 1026 if (!IsSigned && !IsUnsigned) 1027 return SDValue(); 1028 1029 // Initialize accumulator. 1030 SDLoc DL(ROOTNode); 1031 SDValue BottomHalf, TopHalf; 1032 std::tie(BottomHalf, TopHalf) = 1033 CurDAG.SplitScalar(AddOperand, DL, MVT::i32, MVT::i32); 1034 SDValue ACCIn = 1035 CurDAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, BottomHalf, TopHalf); 1036 1037 // Create MipsMAdd(u) / MipsMSub(u) node. 1038 bool IsAdd = ROOTNode->getOpcode() == ISD::ADD; 1039 unsigned Opcode = IsAdd ? (IsUnsigned ? MipsISD::MAddu : MipsISD::MAdd) 1040 : (IsUnsigned ? MipsISD::MSubu : MipsISD::MSub); 1041 SDValue MAddOps[3] = { 1042 CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(0)), 1043 CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(1)), ACCIn}; 1044 EVT VTs[2] = {MVT::i32, MVT::i32}; 1045 SDValue MAdd = CurDAG.getNode(Opcode, DL, VTs, MAddOps); 1046 1047 SDValue ResLo = CurDAG.getNode(MipsISD::MFLO, DL, MVT::i32, MAdd); 1048 SDValue ResHi = CurDAG.getNode(MipsISD::MFHI, DL, MVT::i32, MAdd); 1049 SDValue Combined = 1050 CurDAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResLo, ResHi); 1051 return Combined; 1052} 1053 1054static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG, 1055 TargetLowering::DAGCombinerInfo &DCI, 1056 const MipsSubtarget &Subtarget) { 1057 // (sub v0 (mul v1, v2)) => (msub v1, v2, v0) 1058 if (DCI.isBeforeLegalizeOps()) { 1059 if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() && 1060 !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64) 1061 return performMADD_MSUBCombine(N, DAG, Subtarget); 1062 1063 return SDValue(); 1064 } 1065 1066 return SDValue(); 1067} 1068 1069static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG, 1070 TargetLowering::DAGCombinerInfo &DCI, 1071 const MipsSubtarget &Subtarget) { 1072 // (add v0 (mul v1, v2)) => (madd v1, v2, v0) 1073 if (DCI.isBeforeLegalizeOps()) { 1074 if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() && 1075 !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64) 1076 return performMADD_MSUBCombine(N, DAG, Subtarget); 1077 1078 return SDValue(); 1079 } 1080 1081 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt)) 1082 SDValue Add = N->getOperand(1); 1083 1084 if (Add.getOpcode() != ISD::ADD) 1085 return SDValue(); 1086 1087 SDValue Lo = Add.getOperand(1); 1088 1089 if ((Lo.getOpcode() != MipsISD::Lo) || 1090 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable)) 1091 return SDValue(); 1092 1093 EVT ValTy = N->getValueType(0); 1094 SDLoc DL(N); 1095 1096 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0), 1097 Add.getOperand(0)); 1098 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo); 1099} 1100 1101static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG, 1102 TargetLowering::DAGCombinerInfo &DCI, 1103 const MipsSubtarget &Subtarget) { 1104 // Pattern match CINS. 1105 // $dst = shl (and $src , imm), pos 1106 // => cins $dst, $src, pos, size 1107 1108 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasCnMips()) 1109 return SDValue(); 1110 1111 SDValue FirstOperand = N->getOperand(0); 1112 unsigned FirstOperandOpc = FirstOperand.getOpcode(); 1113 SDValue SecondOperand = N->getOperand(1); 1114 EVT ValTy = N->getValueType(0); 1115 SDLoc DL(N); 1116 1117 uint64_t Pos = 0; 1118 unsigned SMPos, SMSize; 1119 ConstantSDNode *CN; 1120 SDValue NewOperand; 1121 1122 // The second operand of the shift must be an immediate. 1123 if (!(CN = dyn_cast<ConstantSDNode>(SecondOperand))) 1124 return SDValue(); 1125 1126 Pos = CN->getZExtValue(); 1127 1128 if (Pos >= ValTy.getSizeInBits()) 1129 return SDValue(); 1130 1131 if (FirstOperandOpc != ISD::AND) 1132 return SDValue(); 1133 1134 // AND's second operand must be a shifted mask. 1135 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))) || 1136 !isShiftedMask_64(CN->getZExtValue(), SMPos, SMSize)) 1137 return SDValue(); 1138 1139 // Return if the shifted mask does not start at bit 0 or the sum of its size 1140 // and Pos exceeds the word's size. 1141 if (SMPos != 0 || SMSize > 32 || Pos + SMSize > ValTy.getSizeInBits()) 1142 return SDValue(); 1143 1144 NewOperand = FirstOperand.getOperand(0); 1145 // SMSize is 'location' (position) in this case, not size. 1146 SMSize--; 1147 1148 return DAG.getNode(MipsISD::CIns, DL, ValTy, NewOperand, 1149 DAG.getConstant(Pos, DL, MVT::i32), 1150 DAG.getConstant(SMSize, DL, MVT::i32)); 1151} 1152 1153SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) 1154 const { 1155 SelectionDAG &DAG = DCI.DAG; 1156 unsigned Opc = N->getOpcode(); 1157 1158 switch (Opc) { 1159 default: break; 1160 case ISD::SDIVREM: 1161 case ISD::UDIVREM: 1162 return performDivRemCombine(N, DAG, DCI, Subtarget); 1163 case ISD::SELECT: 1164 return performSELECTCombine(N, DAG, DCI, Subtarget); 1165 case MipsISD::CMovFP_F: 1166 case MipsISD::CMovFP_T: 1167 return performCMovFPCombine(N, DAG, DCI, Subtarget); 1168 case ISD::AND: 1169 return performANDCombine(N, DAG, DCI, Subtarget); 1170 case ISD::OR: 1171 return performORCombine(N, DAG, DCI, Subtarget); 1172 case ISD::ADD: 1173 return performADDCombine(N, DAG, DCI, Subtarget); 1174 case ISD::SHL: 1175 return performSHLCombine(N, DAG, DCI, Subtarget); 1176 case ISD::SUB: 1177 return performSUBCombine(N, DAG, DCI, Subtarget); 1178 } 1179 1180 return SDValue(); 1181} 1182 1183bool MipsTargetLowering::isCheapToSpeculateCttz(Type *Ty) const { 1184 return Subtarget.hasMips32(); 1185} 1186 1187bool MipsTargetLowering::isCheapToSpeculateCtlz(Type *Ty) const { 1188 return Subtarget.hasMips32(); 1189} 1190 1191bool MipsTargetLowering::hasBitTest(SDValue X, SDValue Y) const { 1192 // We can use ANDI+SLTIU as a bit test. Y contains the bit position. 1193 // For MIPSR2 or later, we may be able to use the `ext` instruction or its' 1194 // double-word variants. 1195 if (auto *C = dyn_cast<ConstantSDNode>(Y)) 1196 return C->getAPIntValue().ule(15); 1197 1198 return false; 1199} 1200 1201bool MipsTargetLowering::shouldFoldConstantShiftPairToMask( 1202 const SDNode *N, CombineLevel Level) const { 1203 assert(((N->getOpcode() == ISD::SHL && 1204 N->getOperand(0).getOpcode() == ISD::SRL) || 1205 (N->getOpcode() == ISD::SRL && 1206 N->getOperand(0).getOpcode() == ISD::SHL)) && 1207 "Expected shift-shift mask"); 1208 1209 if (N->getOperand(0).getValueType().isVector()) 1210 return false; 1211 return true; 1212} 1213 1214void 1215MipsTargetLowering::ReplaceNodeResults(SDNode *N, 1216 SmallVectorImpl<SDValue> &Results, 1217 SelectionDAG &DAG) const { 1218 return LowerOperationWrapper(N, Results, DAG); 1219} 1220 1221SDValue MipsTargetLowering:: 1222LowerOperation(SDValue Op, SelectionDAG &DAG) const 1223{ 1224 switch (Op.getOpcode()) 1225 { 1226 case ISD::BRCOND: return lowerBRCOND(Op, DAG); 1227 case ISD::ConstantPool: return lowerConstantPool(Op, DAG); 1228 case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG); 1229 case ISD::BlockAddress: return lowerBlockAddress(Op, DAG); 1230 case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG); 1231 case ISD::JumpTable: return lowerJumpTable(Op, DAG); 1232 case ISD::SELECT: return lowerSELECT(Op, DAG); 1233 case ISD::SETCC: return lowerSETCC(Op, DAG); 1234 case ISD::VASTART: return lowerVASTART(Op, DAG); 1235 case ISD::VAARG: return lowerVAARG(Op, DAG); 1236 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG); 1237 case ISD::FABS: return lowerFABS(Op, DAG); 1238 case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG); 1239 case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG); 1240 case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG); 1241 case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG); 1242 case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG); 1243 case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true); 1244 case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false); 1245 case ISD::LOAD: return lowerLOAD(Op, DAG); 1246 case ISD::STORE: return lowerSTORE(Op, DAG); 1247 case ISD::EH_DWARF_CFA: return lowerEH_DWARF_CFA(Op, DAG); 1248 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG); 1249 } 1250 return SDValue(); 1251} 1252 1253//===----------------------------------------------------------------------===// 1254// Lower helper functions 1255//===----------------------------------------------------------------------===// 1256 1257// addLiveIn - This helper function adds the specified physical register to the 1258// MachineFunction as a live in value. It also creates a corresponding 1259// virtual register for it. 1260static unsigned 1261addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC) 1262{ 1263 Register VReg = MF.getRegInfo().createVirtualRegister(RC); 1264 MF.getRegInfo().addLiveIn(PReg, VReg); 1265 return VReg; 1266} 1267 1268static MachineBasicBlock *insertDivByZeroTrap(MachineInstr &MI, 1269 MachineBasicBlock &MBB, 1270 const TargetInstrInfo &TII, 1271 bool Is64Bit, bool IsMicroMips) { 1272 if (NoZeroDivCheck) 1273 return &MBB; 1274 1275 // Insert instruction "teq $divisor_reg, $zero, 7". 1276 MachineBasicBlock::iterator I(MI); 1277 MachineInstrBuilder MIB; 1278 MachineOperand &Divisor = MI.getOperand(2); 1279 MIB = BuildMI(MBB, std::next(I), MI.getDebugLoc(), 1280 TII.get(IsMicroMips ? Mips::TEQ_MM : Mips::TEQ)) 1281 .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill())) 1282 .addReg(Mips::ZERO) 1283 .addImm(7); 1284 1285 // Use the 32-bit sub-register if this is a 64-bit division. 1286 if (Is64Bit) 1287 MIB->getOperand(0).setSubReg(Mips::sub_32); 1288 1289 // Clear Divisor's kill flag. 1290 Divisor.setIsKill(false); 1291 1292 // We would normally delete the original instruction here but in this case 1293 // we only needed to inject an additional instruction rather than replace it. 1294 1295 return &MBB; 1296} 1297 1298MachineBasicBlock * 1299MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, 1300 MachineBasicBlock *BB) const { 1301 switch (MI.getOpcode()) { 1302 default: 1303 llvm_unreachable("Unexpected instr type to insert"); 1304 case Mips::ATOMIC_LOAD_ADD_I8: 1305 return emitAtomicBinaryPartword(MI, BB, 1); 1306 case Mips::ATOMIC_LOAD_ADD_I16: 1307 return emitAtomicBinaryPartword(MI, BB, 2); 1308 case Mips::ATOMIC_LOAD_ADD_I32: 1309 return emitAtomicBinary(MI, BB); 1310 case Mips::ATOMIC_LOAD_ADD_I64: 1311 return emitAtomicBinary(MI, BB); 1312 1313 case Mips::ATOMIC_LOAD_AND_I8: 1314 return emitAtomicBinaryPartword(MI, BB, 1); 1315 case Mips::ATOMIC_LOAD_AND_I16: 1316 return emitAtomicBinaryPartword(MI, BB, 2); 1317 case Mips::ATOMIC_LOAD_AND_I32: 1318 return emitAtomicBinary(MI, BB); 1319 case Mips::ATOMIC_LOAD_AND_I64: 1320 return emitAtomicBinary(MI, BB); 1321 1322 case Mips::ATOMIC_LOAD_OR_I8: 1323 return emitAtomicBinaryPartword(MI, BB, 1); 1324 case Mips::ATOMIC_LOAD_OR_I16: 1325 return emitAtomicBinaryPartword(MI, BB, 2); 1326 case Mips::ATOMIC_LOAD_OR_I32: 1327 return emitAtomicBinary(MI, BB); 1328 case Mips::ATOMIC_LOAD_OR_I64: 1329 return emitAtomicBinary(MI, BB); 1330 1331 case Mips::ATOMIC_LOAD_XOR_I8: 1332 return emitAtomicBinaryPartword(MI, BB, 1); 1333 case Mips::ATOMIC_LOAD_XOR_I16: 1334 return emitAtomicBinaryPartword(MI, BB, 2); 1335 case Mips::ATOMIC_LOAD_XOR_I32: 1336 return emitAtomicBinary(MI, BB); 1337 case Mips::ATOMIC_LOAD_XOR_I64: 1338 return emitAtomicBinary(MI, BB); 1339 1340 case Mips::ATOMIC_LOAD_NAND_I8: 1341 return emitAtomicBinaryPartword(MI, BB, 1); 1342 case Mips::ATOMIC_LOAD_NAND_I16: 1343 return emitAtomicBinaryPartword(MI, BB, 2); 1344 case Mips::ATOMIC_LOAD_NAND_I32: 1345 return emitAtomicBinary(MI, BB); 1346 case Mips::ATOMIC_LOAD_NAND_I64: 1347 return emitAtomicBinary(MI, BB); 1348 1349 case Mips::ATOMIC_LOAD_SUB_I8: 1350 return emitAtomicBinaryPartword(MI, BB, 1); 1351 case Mips::ATOMIC_LOAD_SUB_I16: 1352 return emitAtomicBinaryPartword(MI, BB, 2); 1353 case Mips::ATOMIC_LOAD_SUB_I32: 1354 return emitAtomicBinary(MI, BB); 1355 case Mips::ATOMIC_LOAD_SUB_I64: 1356 return emitAtomicBinary(MI, BB); 1357 1358 case Mips::ATOMIC_SWAP_I8: 1359 return emitAtomicBinaryPartword(MI, BB, 1); 1360 case Mips::ATOMIC_SWAP_I16: 1361 return emitAtomicBinaryPartword(MI, BB, 2); 1362 case Mips::ATOMIC_SWAP_I32: 1363 return emitAtomicBinary(MI, BB); 1364 case Mips::ATOMIC_SWAP_I64: 1365 return emitAtomicBinary(MI, BB); 1366 1367 case Mips::ATOMIC_CMP_SWAP_I8: 1368 return emitAtomicCmpSwapPartword(MI, BB, 1); 1369 case Mips::ATOMIC_CMP_SWAP_I16: 1370 return emitAtomicCmpSwapPartword(MI, BB, 2); 1371 case Mips::ATOMIC_CMP_SWAP_I32: 1372 return emitAtomicCmpSwap(MI, BB); 1373 case Mips::ATOMIC_CMP_SWAP_I64: 1374 return emitAtomicCmpSwap(MI, BB); 1375 1376 case Mips::ATOMIC_LOAD_MIN_I8: 1377 return emitAtomicBinaryPartword(MI, BB, 1); 1378 case Mips::ATOMIC_LOAD_MIN_I16: 1379 return emitAtomicBinaryPartword(MI, BB, 2); 1380 case Mips::ATOMIC_LOAD_MIN_I32: 1381 return emitAtomicBinary(MI, BB); 1382 case Mips::ATOMIC_LOAD_MIN_I64: 1383 return emitAtomicBinary(MI, BB); 1384 1385 case Mips::ATOMIC_LOAD_MAX_I8: 1386 return emitAtomicBinaryPartword(MI, BB, 1); 1387 case Mips::ATOMIC_LOAD_MAX_I16: 1388 return emitAtomicBinaryPartword(MI, BB, 2); 1389 case Mips::ATOMIC_LOAD_MAX_I32: 1390 return emitAtomicBinary(MI, BB); 1391 case Mips::ATOMIC_LOAD_MAX_I64: 1392 return emitAtomicBinary(MI, BB); 1393 1394 case Mips::ATOMIC_LOAD_UMIN_I8: 1395 return emitAtomicBinaryPartword(MI, BB, 1); 1396 case Mips::ATOMIC_LOAD_UMIN_I16: 1397 return emitAtomicBinaryPartword(MI, BB, 2); 1398 case Mips::ATOMIC_LOAD_UMIN_I32: 1399 return emitAtomicBinary(MI, BB); 1400 case Mips::ATOMIC_LOAD_UMIN_I64: 1401 return emitAtomicBinary(MI, BB); 1402 1403 case Mips::ATOMIC_LOAD_UMAX_I8: 1404 return emitAtomicBinaryPartword(MI, BB, 1); 1405 case Mips::ATOMIC_LOAD_UMAX_I16: 1406 return emitAtomicBinaryPartword(MI, BB, 2); 1407 case Mips::ATOMIC_LOAD_UMAX_I32: 1408 return emitAtomicBinary(MI, BB); 1409 case Mips::ATOMIC_LOAD_UMAX_I64: 1410 return emitAtomicBinary(MI, BB); 1411 1412 case Mips::PseudoSDIV: 1413 case Mips::PseudoUDIV: 1414 case Mips::DIV: 1415 case Mips::DIVU: 1416 case Mips::MOD: 1417 case Mips::MODU: 1418 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, 1419 false); 1420 case Mips::SDIV_MM_Pseudo: 1421 case Mips::UDIV_MM_Pseudo: 1422 case Mips::SDIV_MM: 1423 case Mips::UDIV_MM: 1424 case Mips::DIV_MMR6: 1425 case Mips::DIVU_MMR6: 1426 case Mips::MOD_MMR6: 1427 case Mips::MODU_MMR6: 1428 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, true); 1429 case Mips::PseudoDSDIV: 1430 case Mips::PseudoDUDIV: 1431 case Mips::DDIV: 1432 case Mips::DDIVU: 1433 case Mips::DMOD: 1434 case Mips::DMODU: 1435 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, false); 1436 1437 case Mips::PseudoSELECT_I: 1438 case Mips::PseudoSELECT_I64: 1439 case Mips::PseudoSELECT_S: 1440 case Mips::PseudoSELECT_D32: 1441 case Mips::PseudoSELECT_D64: 1442 return emitPseudoSELECT(MI, BB, false, Mips::BNE); 1443 case Mips::PseudoSELECTFP_F_I: 1444 case Mips::PseudoSELECTFP_F_I64: 1445 case Mips::PseudoSELECTFP_F_S: 1446 case Mips::PseudoSELECTFP_F_D32: 1447 case Mips::PseudoSELECTFP_F_D64: 1448 return emitPseudoSELECT(MI, BB, true, Mips::BC1F); 1449 case Mips::PseudoSELECTFP_T_I: 1450 case Mips::PseudoSELECTFP_T_I64: 1451 case Mips::PseudoSELECTFP_T_S: 1452 case Mips::PseudoSELECTFP_T_D32: 1453 case Mips::PseudoSELECTFP_T_D64: 1454 return emitPseudoSELECT(MI, BB, true, Mips::BC1T); 1455 case Mips::PseudoD_SELECT_I: 1456 case Mips::PseudoD_SELECT_I64: 1457 return emitPseudoD_SELECT(MI, BB); 1458 case Mips::LDR_W: 1459 return emitLDR_W(MI, BB); 1460 case Mips::LDR_D: 1461 return emitLDR_D(MI, BB); 1462 case Mips::STR_W: 1463 return emitSTR_W(MI, BB); 1464 case Mips::STR_D: 1465 return emitSTR_D(MI, BB); 1466 } 1467} 1468 1469// This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and 1470// Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) 1471MachineBasicBlock * 1472MipsTargetLowering::emitAtomicBinary(MachineInstr &MI, 1473 MachineBasicBlock *BB) const { 1474 1475 MachineFunction *MF = BB->getParent(); 1476 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1477 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1478 DebugLoc DL = MI.getDebugLoc(); 1479 1480 unsigned AtomicOp; 1481 bool NeedsAdditionalReg = false; 1482 switch (MI.getOpcode()) { 1483 case Mips::ATOMIC_LOAD_ADD_I32: 1484 AtomicOp = Mips::ATOMIC_LOAD_ADD_I32_POSTRA; 1485 break; 1486 case Mips::ATOMIC_LOAD_SUB_I32: 1487 AtomicOp = Mips::ATOMIC_LOAD_SUB_I32_POSTRA; 1488 break; 1489 case Mips::ATOMIC_LOAD_AND_I32: 1490 AtomicOp = Mips::ATOMIC_LOAD_AND_I32_POSTRA; 1491 break; 1492 case Mips::ATOMIC_LOAD_OR_I32: 1493 AtomicOp = Mips::ATOMIC_LOAD_OR_I32_POSTRA; 1494 break; 1495 case Mips::ATOMIC_LOAD_XOR_I32: 1496 AtomicOp = Mips::ATOMIC_LOAD_XOR_I32_POSTRA; 1497 break; 1498 case Mips::ATOMIC_LOAD_NAND_I32: 1499 AtomicOp = Mips::ATOMIC_LOAD_NAND_I32_POSTRA; 1500 break; 1501 case Mips::ATOMIC_SWAP_I32: 1502 AtomicOp = Mips::ATOMIC_SWAP_I32_POSTRA; 1503 break; 1504 case Mips::ATOMIC_LOAD_ADD_I64: 1505 AtomicOp = Mips::ATOMIC_LOAD_ADD_I64_POSTRA; 1506 break; 1507 case Mips::ATOMIC_LOAD_SUB_I64: 1508 AtomicOp = Mips::ATOMIC_LOAD_SUB_I64_POSTRA; 1509 break; 1510 case Mips::ATOMIC_LOAD_AND_I64: 1511 AtomicOp = Mips::ATOMIC_LOAD_AND_I64_POSTRA; 1512 break; 1513 case Mips::ATOMIC_LOAD_OR_I64: 1514 AtomicOp = Mips::ATOMIC_LOAD_OR_I64_POSTRA; 1515 break; 1516 case Mips::ATOMIC_LOAD_XOR_I64: 1517 AtomicOp = Mips::ATOMIC_LOAD_XOR_I64_POSTRA; 1518 break; 1519 case Mips::ATOMIC_LOAD_NAND_I64: 1520 AtomicOp = Mips::ATOMIC_LOAD_NAND_I64_POSTRA; 1521 break; 1522 case Mips::ATOMIC_SWAP_I64: 1523 AtomicOp = Mips::ATOMIC_SWAP_I64_POSTRA; 1524 break; 1525 case Mips::ATOMIC_LOAD_MIN_I32: 1526 AtomicOp = Mips::ATOMIC_LOAD_MIN_I32_POSTRA; 1527 NeedsAdditionalReg = true; 1528 break; 1529 case Mips::ATOMIC_LOAD_MAX_I32: 1530 AtomicOp = Mips::ATOMIC_LOAD_MAX_I32_POSTRA; 1531 NeedsAdditionalReg = true; 1532 break; 1533 case Mips::ATOMIC_LOAD_UMIN_I32: 1534 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I32_POSTRA; 1535 NeedsAdditionalReg = true; 1536 break; 1537 case Mips::ATOMIC_LOAD_UMAX_I32: 1538 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I32_POSTRA; 1539 NeedsAdditionalReg = true; 1540 break; 1541 case Mips::ATOMIC_LOAD_MIN_I64: 1542 AtomicOp = Mips::ATOMIC_LOAD_MIN_I64_POSTRA; 1543 NeedsAdditionalReg = true; 1544 break; 1545 case Mips::ATOMIC_LOAD_MAX_I64: 1546 AtomicOp = Mips::ATOMIC_LOAD_MAX_I64_POSTRA; 1547 NeedsAdditionalReg = true; 1548 break; 1549 case Mips::ATOMIC_LOAD_UMIN_I64: 1550 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I64_POSTRA; 1551 NeedsAdditionalReg = true; 1552 break; 1553 case Mips::ATOMIC_LOAD_UMAX_I64: 1554 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I64_POSTRA; 1555 NeedsAdditionalReg = true; 1556 break; 1557 default: 1558 llvm_unreachable("Unknown pseudo atomic for replacement!"); 1559 } 1560 1561 Register OldVal = MI.getOperand(0).getReg(); 1562 Register Ptr = MI.getOperand(1).getReg(); 1563 Register Incr = MI.getOperand(2).getReg(); 1564 Register Scratch = RegInfo.createVirtualRegister(RegInfo.getRegClass(OldVal)); 1565 1566 MachineBasicBlock::iterator II(MI); 1567 1568 // The scratch registers here with the EarlyClobber | Define | Implicit 1569 // flags is used to persuade the register allocator and the machine 1570 // verifier to accept the usage of this register. This has to be a real 1571 // register which has an UNDEF value but is dead after the instruction which 1572 // is unique among the registers chosen for the instruction. 1573 1574 // The EarlyClobber flag has the semantic properties that the operand it is 1575 // attached to is clobbered before the rest of the inputs are read. Hence it 1576 // must be unique among the operands to the instruction. 1577 // The Define flag is needed to coerce the machine verifier that an Undef 1578 // value isn't a problem. 1579 // The Dead flag is needed as the value in scratch isn't used by any other 1580 // instruction. Kill isn't used as Dead is more precise. 1581 // The implicit flag is here due to the interaction between the other flags 1582 // and the machine verifier. 1583 1584 // For correctness purpose, a new pseudo is introduced here. We need this 1585 // new pseudo, so that FastRegisterAllocator does not see an ll/sc sequence 1586 // that is spread over >1 basic blocks. A register allocator which 1587 // introduces (or any codegen infact) a store, can violate the expectations 1588 // of the hardware. 1589 // 1590 // An atomic read-modify-write sequence starts with a linked load 1591 // instruction and ends with a store conditional instruction. The atomic 1592 // read-modify-write sequence fails if any of the following conditions 1593 // occur between the execution of ll and sc: 1594 // * A coherent store is completed by another process or coherent I/O 1595 // module into the block of synchronizable physical memory containing 1596 // the word. The size and alignment of the block is 1597 // implementation-dependent. 1598 // * A coherent store is executed between an LL and SC sequence on the 1599 // same processor to the block of synchornizable physical memory 1600 // containing the word. 1601 // 1602 1603 Register PtrCopy = RegInfo.createVirtualRegister(RegInfo.getRegClass(Ptr)); 1604 Register IncrCopy = RegInfo.createVirtualRegister(RegInfo.getRegClass(Incr)); 1605 1606 BuildMI(*BB, II, DL, TII->get(Mips::COPY), IncrCopy).addReg(Incr); 1607 BuildMI(*BB, II, DL, TII->get(Mips::COPY), PtrCopy).addReg(Ptr); 1608 1609 MachineInstrBuilder MIB = 1610 BuildMI(*BB, II, DL, TII->get(AtomicOp)) 1611 .addReg(OldVal, RegState::Define | RegState::EarlyClobber) 1612 .addReg(PtrCopy) 1613 .addReg(IncrCopy) 1614 .addReg(Scratch, RegState::Define | RegState::EarlyClobber | 1615 RegState::Implicit | RegState::Dead); 1616 if (NeedsAdditionalReg) { 1617 Register Scratch2 = 1618 RegInfo.createVirtualRegister(RegInfo.getRegClass(OldVal)); 1619 MIB.addReg(Scratch2, RegState::Define | RegState::EarlyClobber | 1620 RegState::Implicit | RegState::Dead); 1621 } 1622 1623 MI.eraseFromParent(); 1624 1625 return BB; 1626} 1627 1628MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg( 1629 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg, 1630 unsigned SrcReg) const { 1631 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1632 const DebugLoc &DL = MI.getDebugLoc(); 1633 1634 if (Subtarget.hasMips32r2() && Size == 1) { 1635 BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg); 1636 return BB; 1637 } 1638 1639 if (Subtarget.hasMips32r2() && Size == 2) { 1640 BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg); 1641 return BB; 1642 } 1643 1644 MachineFunction *MF = BB->getParent(); 1645 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1646 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1647 Register ScrReg = RegInfo.createVirtualRegister(RC); 1648 1649 assert(Size < 32); 1650 int64_t ShiftImm = 32 - (Size * 8); 1651 1652 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm); 1653 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm); 1654 1655 return BB; 1656} 1657 1658MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword( 1659 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const { 1660 assert((Size == 1 || Size == 2) && 1661 "Unsupported size for EmitAtomicBinaryPartial."); 1662 1663 MachineFunction *MF = BB->getParent(); 1664 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1665 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1666 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1667 const TargetRegisterClass *RCp = 1668 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); 1669 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1670 DebugLoc DL = MI.getDebugLoc(); 1671 1672 Register Dest = MI.getOperand(0).getReg(); 1673 Register Ptr = MI.getOperand(1).getReg(); 1674 Register Incr = MI.getOperand(2).getReg(); 1675 1676 Register AlignedAddr = RegInfo.createVirtualRegister(RCp); 1677 Register ShiftAmt = RegInfo.createVirtualRegister(RC); 1678 Register Mask = RegInfo.createVirtualRegister(RC); 1679 Register Mask2 = RegInfo.createVirtualRegister(RC); 1680 Register Incr2 = RegInfo.createVirtualRegister(RC); 1681 Register MaskLSB2 = RegInfo.createVirtualRegister(RCp); 1682 Register PtrLSB2 = RegInfo.createVirtualRegister(RC); 1683 Register MaskUpper = RegInfo.createVirtualRegister(RC); 1684 Register Scratch = RegInfo.createVirtualRegister(RC); 1685 Register Scratch2 = RegInfo.createVirtualRegister(RC); 1686 Register Scratch3 = RegInfo.createVirtualRegister(RC); 1687 1688 unsigned AtomicOp = 0; 1689 bool NeedsAdditionalReg = false; 1690 switch (MI.getOpcode()) { 1691 case Mips::ATOMIC_LOAD_NAND_I8: 1692 AtomicOp = Mips::ATOMIC_LOAD_NAND_I8_POSTRA; 1693 break; 1694 case Mips::ATOMIC_LOAD_NAND_I16: 1695 AtomicOp = Mips::ATOMIC_LOAD_NAND_I16_POSTRA; 1696 break; 1697 case Mips::ATOMIC_SWAP_I8: 1698 AtomicOp = Mips::ATOMIC_SWAP_I8_POSTRA; 1699 break; 1700 case Mips::ATOMIC_SWAP_I16: 1701 AtomicOp = Mips::ATOMIC_SWAP_I16_POSTRA; 1702 break; 1703 case Mips::ATOMIC_LOAD_ADD_I8: 1704 AtomicOp = Mips::ATOMIC_LOAD_ADD_I8_POSTRA; 1705 break; 1706 case Mips::ATOMIC_LOAD_ADD_I16: 1707 AtomicOp = Mips::ATOMIC_LOAD_ADD_I16_POSTRA; 1708 break; 1709 case Mips::ATOMIC_LOAD_SUB_I8: 1710 AtomicOp = Mips::ATOMIC_LOAD_SUB_I8_POSTRA; 1711 break; 1712 case Mips::ATOMIC_LOAD_SUB_I16: 1713 AtomicOp = Mips::ATOMIC_LOAD_SUB_I16_POSTRA; 1714 break; 1715 case Mips::ATOMIC_LOAD_AND_I8: 1716 AtomicOp = Mips::ATOMIC_LOAD_AND_I8_POSTRA; 1717 break; 1718 case Mips::ATOMIC_LOAD_AND_I16: 1719 AtomicOp = Mips::ATOMIC_LOAD_AND_I16_POSTRA; 1720 break; 1721 case Mips::ATOMIC_LOAD_OR_I8: 1722 AtomicOp = Mips::ATOMIC_LOAD_OR_I8_POSTRA; 1723 break; 1724 case Mips::ATOMIC_LOAD_OR_I16: 1725 AtomicOp = Mips::ATOMIC_LOAD_OR_I16_POSTRA; 1726 break; 1727 case Mips::ATOMIC_LOAD_XOR_I8: 1728 AtomicOp = Mips::ATOMIC_LOAD_XOR_I8_POSTRA; 1729 break; 1730 case Mips::ATOMIC_LOAD_XOR_I16: 1731 AtomicOp = Mips::ATOMIC_LOAD_XOR_I16_POSTRA; 1732 break; 1733 case Mips::ATOMIC_LOAD_MIN_I8: 1734 AtomicOp = Mips::ATOMIC_LOAD_MIN_I8_POSTRA; 1735 NeedsAdditionalReg = true; 1736 break; 1737 case Mips::ATOMIC_LOAD_MIN_I16: 1738 AtomicOp = Mips::ATOMIC_LOAD_MIN_I16_POSTRA; 1739 NeedsAdditionalReg = true; 1740 break; 1741 case Mips::ATOMIC_LOAD_MAX_I8: 1742 AtomicOp = Mips::ATOMIC_LOAD_MAX_I8_POSTRA; 1743 NeedsAdditionalReg = true; 1744 break; 1745 case Mips::ATOMIC_LOAD_MAX_I16: 1746 AtomicOp = Mips::ATOMIC_LOAD_MAX_I16_POSTRA; 1747 NeedsAdditionalReg = true; 1748 break; 1749 case Mips::ATOMIC_LOAD_UMIN_I8: 1750 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I8_POSTRA; 1751 NeedsAdditionalReg = true; 1752 break; 1753 case Mips::ATOMIC_LOAD_UMIN_I16: 1754 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I16_POSTRA; 1755 NeedsAdditionalReg = true; 1756 break; 1757 case Mips::ATOMIC_LOAD_UMAX_I8: 1758 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I8_POSTRA; 1759 NeedsAdditionalReg = true; 1760 break; 1761 case Mips::ATOMIC_LOAD_UMAX_I16: 1762 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I16_POSTRA; 1763 NeedsAdditionalReg = true; 1764 break; 1765 default: 1766 llvm_unreachable("Unknown subword atomic pseudo for expansion!"); 1767 } 1768 1769 // insert new blocks after the current block 1770 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1771 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1772 MachineFunction::iterator It = ++BB->getIterator(); 1773 MF->insert(It, exitMBB); 1774 1775 // Transfer the remainder of BB and its successor edges to exitMBB. 1776 exitMBB->splice(exitMBB->begin(), BB, 1777 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1778 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1779 1780 BB->addSuccessor(exitMBB, BranchProbability::getOne()); 1781 1782 // thisMBB: 1783 // addiu masklsb2,$0,-4 # 0xfffffffc 1784 // and alignedaddr,ptr,masklsb2 1785 // andi ptrlsb2,ptr,3 1786 // sll shiftamt,ptrlsb2,3 1787 // ori maskupper,$0,255 # 0xff 1788 // sll mask,maskupper,shiftamt 1789 // nor mask2,$0,mask 1790 // sll incr2,incr,shiftamt 1791 1792 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1793 BuildMI(BB, DL, TII->get(ABI.GetPtrAddiuOp()), MaskLSB2) 1794 .addReg(ABI.GetNullPtr()).addImm(-4); 1795 BuildMI(BB, DL, TII->get(ABI.GetPtrAndOp()), AlignedAddr) 1796 .addReg(Ptr).addReg(MaskLSB2); 1797 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2) 1798 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3); 1799 if (Subtarget.isLittle()) { 1800 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1801 } else { 1802 Register Off = RegInfo.createVirtualRegister(RC); 1803 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1804 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1805 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1806 } 1807 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1808 .addReg(Mips::ZERO).addImm(MaskImm); 1809 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1810 .addReg(MaskUpper).addReg(ShiftAmt); 1811 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1812 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt); 1813 1814 1815 // The purposes of the flags on the scratch registers is explained in 1816 // emitAtomicBinary. In summary, we need a scratch register which is going to 1817 // be undef, that is unique among registers chosen for the instruction. 1818 1819 MachineInstrBuilder MIB = 1820 BuildMI(BB, DL, TII->get(AtomicOp)) 1821 .addReg(Dest, RegState::Define | RegState::EarlyClobber) 1822 .addReg(AlignedAddr) 1823 .addReg(Incr2) 1824 .addReg(Mask) 1825 .addReg(Mask2) 1826 .addReg(ShiftAmt) 1827 .addReg(Scratch, RegState::EarlyClobber | RegState::Define | 1828 RegState::Dead | RegState::Implicit) 1829 .addReg(Scratch2, RegState::EarlyClobber | RegState::Define | 1830 RegState::Dead | RegState::Implicit) 1831 .addReg(Scratch3, RegState::EarlyClobber | RegState::Define | 1832 RegState::Dead | RegState::Implicit); 1833 if (NeedsAdditionalReg) { 1834 Register Scratch4 = RegInfo.createVirtualRegister(RC); 1835 MIB.addReg(Scratch4, RegState::EarlyClobber | RegState::Define | 1836 RegState::Dead | RegState::Implicit); 1837 } 1838 1839 MI.eraseFromParent(); // The instruction is gone now. 1840 1841 return exitMBB; 1842} 1843 1844// Lower atomic compare and swap to a pseudo instruction, taking care to 1845// define a scratch register for the pseudo instruction's expansion. The 1846// instruction is expanded after the register allocator as to prevent 1847// the insertion of stores between the linked load and the store conditional. 1848 1849MachineBasicBlock * 1850MipsTargetLowering::emitAtomicCmpSwap(MachineInstr &MI, 1851 MachineBasicBlock *BB) const { 1852 1853 assert((MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 || 1854 MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I64) && 1855 "Unsupported atomic pseudo for EmitAtomicCmpSwap."); 1856 1857 const unsigned Size = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 ? 4 : 8; 1858 1859 MachineFunction *MF = BB->getParent(); 1860 MachineRegisterInfo &MRI = MF->getRegInfo(); 1861 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1862 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1863 DebugLoc DL = MI.getDebugLoc(); 1864 1865 unsigned AtomicOp = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 1866 ? Mips::ATOMIC_CMP_SWAP_I32_POSTRA 1867 : Mips::ATOMIC_CMP_SWAP_I64_POSTRA; 1868 Register Dest = MI.getOperand(0).getReg(); 1869 Register Ptr = MI.getOperand(1).getReg(); 1870 Register OldVal = MI.getOperand(2).getReg(); 1871 Register NewVal = MI.getOperand(3).getReg(); 1872 1873 Register Scratch = MRI.createVirtualRegister(RC); 1874 MachineBasicBlock::iterator II(MI); 1875 1876 // We need to create copies of the various registers and kill them at the 1877 // atomic pseudo. If the copies are not made, when the atomic is expanded 1878 // after fast register allocation, the spills will end up outside of the 1879 // blocks that their values are defined in, causing livein errors. 1880 1881 Register PtrCopy = MRI.createVirtualRegister(MRI.getRegClass(Ptr)); 1882 Register OldValCopy = MRI.createVirtualRegister(MRI.getRegClass(OldVal)); 1883 Register NewValCopy = MRI.createVirtualRegister(MRI.getRegClass(NewVal)); 1884 1885 BuildMI(*BB, II, DL, TII->get(Mips::COPY), PtrCopy).addReg(Ptr); 1886 BuildMI(*BB, II, DL, TII->get(Mips::COPY), OldValCopy).addReg(OldVal); 1887 BuildMI(*BB, II, DL, TII->get(Mips::COPY), NewValCopy).addReg(NewVal); 1888 1889 // The purposes of the flags on the scratch registers is explained in 1890 // emitAtomicBinary. In summary, we need a scratch register which is going to 1891 // be undef, that is unique among registers chosen for the instruction. 1892 1893 BuildMI(*BB, II, DL, TII->get(AtomicOp)) 1894 .addReg(Dest, RegState::Define | RegState::EarlyClobber) 1895 .addReg(PtrCopy, RegState::Kill) 1896 .addReg(OldValCopy, RegState::Kill) 1897 .addReg(NewValCopy, RegState::Kill) 1898 .addReg(Scratch, RegState::EarlyClobber | RegState::Define | 1899 RegState::Dead | RegState::Implicit); 1900 1901 MI.eraseFromParent(); // The instruction is gone now. 1902 1903 return BB; 1904} 1905 1906MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwapPartword( 1907 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const { 1908 assert((Size == 1 || Size == 2) && 1909 "Unsupported size for EmitAtomicCmpSwapPartial."); 1910 1911 MachineFunction *MF = BB->getParent(); 1912 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1913 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1914 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1915 const TargetRegisterClass *RCp = 1916 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); 1917 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1918 DebugLoc DL = MI.getDebugLoc(); 1919 1920 Register Dest = MI.getOperand(0).getReg(); 1921 Register Ptr = MI.getOperand(1).getReg(); 1922 Register CmpVal = MI.getOperand(2).getReg(); 1923 Register NewVal = MI.getOperand(3).getReg(); 1924 1925 Register AlignedAddr = RegInfo.createVirtualRegister(RCp); 1926 Register ShiftAmt = RegInfo.createVirtualRegister(RC); 1927 Register Mask = RegInfo.createVirtualRegister(RC); 1928 Register Mask2 = RegInfo.createVirtualRegister(RC); 1929 Register ShiftedCmpVal = RegInfo.createVirtualRegister(RC); 1930 Register ShiftedNewVal = RegInfo.createVirtualRegister(RC); 1931 Register MaskLSB2 = RegInfo.createVirtualRegister(RCp); 1932 Register PtrLSB2 = RegInfo.createVirtualRegister(RC); 1933 Register MaskUpper = RegInfo.createVirtualRegister(RC); 1934 Register MaskedCmpVal = RegInfo.createVirtualRegister(RC); 1935 Register MaskedNewVal = RegInfo.createVirtualRegister(RC); 1936 unsigned AtomicOp = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I8 1937 ? Mips::ATOMIC_CMP_SWAP_I8_POSTRA 1938 : Mips::ATOMIC_CMP_SWAP_I16_POSTRA; 1939 1940 // The scratch registers here with the EarlyClobber | Define | Dead | Implicit 1941 // flags are used to coerce the register allocator and the machine verifier to 1942 // accept the usage of these registers. 1943 // The EarlyClobber flag has the semantic properties that the operand it is 1944 // attached to is clobbered before the rest of the inputs are read. Hence it 1945 // must be unique among the operands to the instruction. 1946 // The Define flag is needed to coerce the machine verifier that an Undef 1947 // value isn't a problem. 1948 // The Dead flag is needed as the value in scratch isn't used by any other 1949 // instruction. Kill isn't used as Dead is more precise. 1950 Register Scratch = RegInfo.createVirtualRegister(RC); 1951 Register Scratch2 = RegInfo.createVirtualRegister(RC); 1952 1953 // insert new blocks after the current block 1954 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1955 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1956 MachineFunction::iterator It = ++BB->getIterator(); 1957 MF->insert(It, exitMBB); 1958 1959 // Transfer the remainder of BB and its successor edges to exitMBB. 1960 exitMBB->splice(exitMBB->begin(), BB, 1961 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1962 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1963 1964 BB->addSuccessor(exitMBB, BranchProbability::getOne()); 1965 1966 // thisMBB: 1967 // addiu masklsb2,$0,-4 # 0xfffffffc 1968 // and alignedaddr,ptr,masklsb2 1969 // andi ptrlsb2,ptr,3 1970 // xori ptrlsb2,ptrlsb2,3 # Only for BE 1971 // sll shiftamt,ptrlsb2,3 1972 // ori maskupper,$0,255 # 0xff 1973 // sll mask,maskupper,shiftamt 1974 // nor mask2,$0,mask 1975 // andi maskedcmpval,cmpval,255 1976 // sll shiftedcmpval,maskedcmpval,shiftamt 1977 // andi maskednewval,newval,255 1978 // sll shiftednewval,maskednewval,shiftamt 1979 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1980 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2) 1981 .addReg(ABI.GetNullPtr()).addImm(-4); 1982 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr) 1983 .addReg(Ptr).addReg(MaskLSB2); 1984 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2) 1985 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3); 1986 if (Subtarget.isLittle()) { 1987 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1988 } else { 1989 Register Off = RegInfo.createVirtualRegister(RC); 1990 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1991 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1992 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1993 } 1994 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1995 .addReg(Mips::ZERO).addImm(MaskImm); 1996 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1997 .addReg(MaskUpper).addReg(ShiftAmt); 1998 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1999 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal) 2000 .addReg(CmpVal).addImm(MaskImm); 2001 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal) 2002 .addReg(MaskedCmpVal).addReg(ShiftAmt); 2003 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal) 2004 .addReg(NewVal).addImm(MaskImm); 2005 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal) 2006 .addReg(MaskedNewVal).addReg(ShiftAmt); 2007 2008 // The purposes of the flags on the scratch registers are explained in 2009 // emitAtomicBinary. In summary, we need a scratch register which is going to 2010 // be undef, that is unique among the register chosen for the instruction. 2011 2012 BuildMI(BB, DL, TII->get(AtomicOp)) 2013 .addReg(Dest, RegState::Define | RegState::EarlyClobber) 2014 .addReg(AlignedAddr) 2015 .addReg(Mask) 2016 .addReg(ShiftedCmpVal) 2017 .addReg(Mask2) 2018 .addReg(ShiftedNewVal) 2019 .addReg(ShiftAmt) 2020 .addReg(Scratch, RegState::EarlyClobber | RegState::Define | 2021 RegState::Dead | RegState::Implicit) 2022 .addReg(Scratch2, RegState::EarlyClobber | RegState::Define | 2023 RegState::Dead | RegState::Implicit); 2024 2025 MI.eraseFromParent(); // The instruction is gone now. 2026 2027 return exitMBB; 2028} 2029 2030SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 2031 // The first operand is the chain, the second is the condition, the third is 2032 // the block to branch to if the condition is true. 2033 SDValue Chain = Op.getOperand(0); 2034 SDValue Dest = Op.getOperand(2); 2035 SDLoc DL(Op); 2036 2037 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 2038 SDValue CondRes = createFPCmp(DAG, Op.getOperand(1)); 2039 2040 // Return if flag is not set by a floating point comparison. 2041 if (CondRes.getOpcode() != MipsISD::FPCmp) 2042 return Op; 2043 2044 SDValue CCNode = CondRes.getOperand(2); 2045 Mips::CondCode CC = (Mips::CondCode)CCNode->getAsZExtVal(); 2046 unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T; 2047 SDValue BrCode = DAG.getConstant(Opc, DL, MVT::i32); 2048 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 2049 return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode, 2050 FCC0, Dest, CondRes); 2051} 2052 2053SDValue MipsTargetLowering:: 2054lowerSELECT(SDValue Op, SelectionDAG &DAG) const 2055{ 2056 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 2057 SDValue Cond = createFPCmp(DAG, Op.getOperand(0)); 2058 2059 // Return if flag is not set by a floating point comparison. 2060 if (Cond.getOpcode() != MipsISD::FPCmp) 2061 return Op; 2062 2063 return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), 2064 SDLoc(Op)); 2065} 2066 2067SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const { 2068 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 2069 SDValue Cond = createFPCmp(DAG, Op); 2070 2071 assert(Cond.getOpcode() == MipsISD::FPCmp && 2072 "Floating point operand expected."); 2073 2074 SDLoc DL(Op); 2075 SDValue True = DAG.getConstant(1, DL, MVT::i32); 2076 SDValue False = DAG.getConstant(0, DL, MVT::i32); 2077 2078 return createCMovFP(DAG, Cond, True, False, DL); 2079} 2080 2081SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op, 2082 SelectionDAG &DAG) const { 2083 EVT Ty = Op.getValueType(); 2084 GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op); 2085 const GlobalValue *GV = N->getGlobal(); 2086 2087 if (!isPositionIndependent()) { 2088 const MipsTargetObjectFile *TLOF = 2089 static_cast<const MipsTargetObjectFile *>( 2090 getTargetMachine().getObjFileLowering()); 2091 const GlobalObject *GO = GV->getAliaseeObject(); 2092 if (GO && TLOF->IsGlobalInSmallSection(GO, getTargetMachine())) 2093 // %gp_rel relocation 2094 return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64()); 2095 2096 // %hi/%lo relocation 2097 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 2098 // %highest/%higher/%hi/%lo relocation 2099 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 2100 } 2101 2102 // Every other architecture would use shouldAssumeDSOLocal in here, but 2103 // mips is special. 2104 // * In PIC code mips requires got loads even for local statics! 2105 // * To save on got entries, for local statics the got entry contains the 2106 // page and an additional add instruction takes care of the low bits. 2107 // * It is legal to access a hidden symbol with a non hidden undefined, 2108 // so one cannot guarantee that all access to a hidden symbol will know 2109 // it is hidden. 2110 // * Mips linkers don't support creating a page and a full got entry for 2111 // the same symbol. 2112 // * Given all that, we have to use a full got entry for hidden symbols :-( 2113 if (GV->hasLocalLinkage()) 2114 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 2115 2116 if (Subtarget.useXGOT()) 2117 return getAddrGlobalLargeGOT( 2118 N, SDLoc(N), Ty, DAG, MipsII::MO_GOT_HI16, MipsII::MO_GOT_LO16, 2119 DAG.getEntryNode(), 2120 MachinePointerInfo::getGOT(DAG.getMachineFunction())); 2121 2122 return getAddrGlobal( 2123 N, SDLoc(N), Ty, DAG, 2124 (ABI.IsN32() || ABI.IsN64()) ? MipsII::MO_GOT_DISP : MipsII::MO_GOT, 2125 DAG.getEntryNode(), MachinePointerInfo::getGOT(DAG.getMachineFunction())); 2126} 2127 2128SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op, 2129 SelectionDAG &DAG) const { 2130 BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op); 2131 EVT Ty = Op.getValueType(); 2132 2133 if (!isPositionIndependent()) 2134 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 2135 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 2136 2137 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 2138} 2139 2140SDValue MipsTargetLowering:: 2141lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const 2142{ 2143 // If the relocation model is PIC, use the General Dynamic TLS Model or 2144 // Local Dynamic TLS model, otherwise use the Initial Exec or 2145 // Local Exec TLS Model. 2146 2147 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 2148 if (DAG.getTarget().useEmulatedTLS()) 2149 return LowerToTLSEmulatedModel(GA, DAG); 2150 2151 SDLoc DL(GA); 2152 const GlobalValue *GV = GA->getGlobal(); 2153 EVT PtrVT = getPointerTy(DAG.getDataLayout()); 2154 2155 TLSModel::Model model = getTargetMachine().getTLSModel(GV); 2156 2157 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) { 2158 // General Dynamic and Local Dynamic TLS Model. 2159 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM 2160 : MipsII::MO_TLSGD; 2161 2162 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag); 2163 SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, 2164 getGlobalReg(DAG, PtrVT), TGA); 2165 unsigned PtrSize = PtrVT.getSizeInBits(); 2166 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize); 2167 2168 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT); 2169 2170 ArgListTy Args; 2171 ArgListEntry Entry; 2172 Entry.Node = Argument; 2173 Entry.Ty = PtrTy; 2174 Args.push_back(Entry); 2175 2176 TargetLowering::CallLoweringInfo CLI(DAG); 2177 CLI.setDebugLoc(DL) 2178 .setChain(DAG.getEntryNode()) 2179 .setLibCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args)); 2180 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 2181 2182 SDValue Ret = CallResult.first; 2183 2184 if (model != TLSModel::LocalDynamic) 2185 return Ret; 2186 2187 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2188 MipsII::MO_DTPREL_HI); 2189 SDValue Hi = DAG.getNode(MipsISD::TlsHi, DL, PtrVT, TGAHi); 2190 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2191 MipsII::MO_DTPREL_LO); 2192 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 2193 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret); 2194 return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo); 2195 } 2196 2197 SDValue Offset; 2198 if (model == TLSModel::InitialExec) { 2199 // Initial Exec TLS Model 2200 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2201 MipsII::MO_GOTTPREL); 2202 TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT), 2203 TGA); 2204 Offset = 2205 DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), TGA, MachinePointerInfo()); 2206 } else { 2207 // Local Exec TLS Model 2208 assert(model == TLSModel::LocalExec); 2209 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2210 MipsII::MO_TPREL_HI); 2211 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2212 MipsII::MO_TPREL_LO); 2213 SDValue Hi = DAG.getNode(MipsISD::TlsHi, DL, PtrVT, TGAHi); 2214 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 2215 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); 2216 } 2217 2218 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT); 2219 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset); 2220} 2221 2222SDValue MipsTargetLowering:: 2223lowerJumpTable(SDValue Op, SelectionDAG &DAG) const 2224{ 2225 JumpTableSDNode *N = cast<JumpTableSDNode>(Op); 2226 EVT Ty = Op.getValueType(); 2227 2228 if (!isPositionIndependent()) 2229 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 2230 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 2231 2232 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 2233} 2234 2235SDValue MipsTargetLowering:: 2236lowerConstantPool(SDValue Op, SelectionDAG &DAG) const 2237{ 2238 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 2239 EVT Ty = Op.getValueType(); 2240 2241 if (!isPositionIndependent()) { 2242 const MipsTargetObjectFile *TLOF = 2243 static_cast<const MipsTargetObjectFile *>( 2244 getTargetMachine().getObjFileLowering()); 2245 2246 if (TLOF->IsConstantInSmallSection(DAG.getDataLayout(), N->getConstVal(), 2247 getTargetMachine())) 2248 // %gp_rel relocation 2249 return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64()); 2250 2251 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 2252 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 2253 } 2254 2255 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 2256} 2257 2258SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const { 2259 MachineFunction &MF = DAG.getMachineFunction(); 2260 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 2261 2262 SDLoc DL(Op); 2263 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 2264 getPointerTy(MF.getDataLayout())); 2265 2266 // vastart just stores the address of the VarArgsFrameIndex slot into the 2267 // memory location argument. 2268 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 2269 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1), 2270 MachinePointerInfo(SV)); 2271} 2272 2273SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const { 2274 SDNode *Node = Op.getNode(); 2275 EVT VT = Node->getValueType(0); 2276 SDValue Chain = Node->getOperand(0); 2277 SDValue VAListPtr = Node->getOperand(1); 2278 const Align Align = 2279 llvm::MaybeAlign(Node->getConstantOperandVal(3)).valueOrOne(); 2280 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 2281 SDLoc DL(Node); 2282 unsigned ArgSlotSizeInBytes = (ABI.IsN32() || ABI.IsN64()) ? 8 : 4; 2283 2284 SDValue VAListLoad = DAG.getLoad(getPointerTy(DAG.getDataLayout()), DL, Chain, 2285 VAListPtr, MachinePointerInfo(SV)); 2286 SDValue VAList = VAListLoad; 2287 2288 // Re-align the pointer if necessary. 2289 // It should only ever be necessary for 64-bit types on O32 since the minimum 2290 // argument alignment is the same as the maximum type alignment for N32/N64. 2291 // 2292 // FIXME: We currently align too often. The code generator doesn't notice 2293 // when the pointer is still aligned from the last va_arg (or pair of 2294 // va_args for the i64 on O32 case). 2295 if (Align > getMinStackArgumentAlignment()) { 2296 VAList = DAG.getNode( 2297 ISD::ADD, DL, VAList.getValueType(), VAList, 2298 DAG.getConstant(Align.value() - 1, DL, VAList.getValueType())); 2299 2300 VAList = DAG.getNode( 2301 ISD::AND, DL, VAList.getValueType(), VAList, 2302 DAG.getConstant(-(int64_t)Align.value(), DL, VAList.getValueType())); 2303 } 2304 2305 // Increment the pointer, VAList, to the next vaarg. 2306 auto &TD = DAG.getDataLayout(); 2307 unsigned ArgSizeInBytes = 2308 TD.getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())); 2309 SDValue Tmp3 = 2310 DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList, 2311 DAG.getConstant(alignTo(ArgSizeInBytes, ArgSlotSizeInBytes), 2312 DL, VAList.getValueType())); 2313 // Store the incremented VAList to the legalized pointer 2314 Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr, 2315 MachinePointerInfo(SV)); 2316 2317 // In big-endian mode we must adjust the pointer when the load size is smaller 2318 // than the argument slot size. We must also reduce the known alignment to 2319 // match. For example in the N64 ABI, we must add 4 bytes to the offset to get 2320 // the correct half of the slot, and reduce the alignment from 8 (slot 2321 // alignment) down to 4 (type alignment). 2322 if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) { 2323 unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes; 2324 VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList, 2325 DAG.getIntPtrConstant(Adjustment, DL)); 2326 } 2327 // Load the actual argument out of the pointer VAList 2328 return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo()); 2329} 2330 2331static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, 2332 bool HasExtractInsert) { 2333 EVT TyX = Op.getOperand(0).getValueType(); 2334 EVT TyY = Op.getOperand(1).getValueType(); 2335 SDLoc DL(Op); 2336 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32); 2337 SDValue Const31 = DAG.getConstant(31, DL, MVT::i32); 2338 SDValue Res; 2339 2340 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 2341 // to i32. 2342 SDValue X = (TyX == MVT::f32) ? 2343 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : 2344 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 2345 Const1); 2346 SDValue Y = (TyY == MVT::f32) ? 2347 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) : 2348 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1), 2349 Const1); 2350 2351 if (HasExtractInsert) { 2352 // ext E, Y, 31, 1 ; extract bit31 of Y 2353 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X 2354 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1); 2355 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X); 2356 } else { 2357 // sll SllX, X, 1 2358 // srl SrlX, SllX, 1 2359 // srl SrlY, Y, 31 2360 // sll SllY, SrlX, 31 2361 // or Or, SrlX, SllY 2362 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 2363 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 2364 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31); 2365 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31); 2366 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY); 2367 } 2368 2369 if (TyX == MVT::f32) 2370 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res); 2371 2372 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2373 Op.getOperand(0), 2374 DAG.getConstant(0, DL, MVT::i32)); 2375 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 2376} 2377 2378static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, 2379 bool HasExtractInsert) { 2380 unsigned WidthX = Op.getOperand(0).getValueSizeInBits(); 2381 unsigned WidthY = Op.getOperand(1).getValueSizeInBits(); 2382 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY); 2383 SDLoc DL(Op); 2384 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32); 2385 2386 // Bitcast to integer nodes. 2387 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0)); 2388 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1)); 2389 2390 if (HasExtractInsert) { 2391 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y 2392 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X 2393 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y, 2394 DAG.getConstant(WidthY - 1, DL, MVT::i32), Const1); 2395 2396 if (WidthX > WidthY) 2397 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E); 2398 else if (WidthY > WidthX) 2399 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E); 2400 2401 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E, 2402 DAG.getConstant(WidthX - 1, DL, MVT::i32), Const1, 2403 X); 2404 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I); 2405 } 2406 2407 // (d)sll SllX, X, 1 2408 // (d)srl SrlX, SllX, 1 2409 // (d)srl SrlY, Y, width(Y)-1 2410 // (d)sll SllY, SrlX, width(Y)-1 2411 // or Or, SrlX, SllY 2412 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1); 2413 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); 2414 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, 2415 DAG.getConstant(WidthY - 1, DL, MVT::i32)); 2416 2417 if (WidthX > WidthY) 2418 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY); 2419 else if (WidthY > WidthX) 2420 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY); 2421 2422 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY, 2423 DAG.getConstant(WidthX - 1, DL, MVT::i32)); 2424 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY); 2425 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or); 2426} 2427 2428SDValue 2429MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 2430 if (Subtarget.isGP64bit()) 2431 return lowerFCOPYSIGN64(Op, DAG, Subtarget.hasExtractInsert()); 2432 2433 return lowerFCOPYSIGN32(Op, DAG, Subtarget.hasExtractInsert()); 2434} 2435 2436SDValue MipsTargetLowering::lowerFABS32(SDValue Op, SelectionDAG &DAG, 2437 bool HasExtractInsert) const { 2438 SDLoc DL(Op); 2439 SDValue Res, Const1 = DAG.getConstant(1, DL, MVT::i32); 2440 2441 if (DAG.getTarget().Options.NoNaNsFPMath || Subtarget.inAbs2008Mode()) 2442 return DAG.getNode(MipsISD::FAbs, DL, Op.getValueType(), Op.getOperand(0)); 2443 2444 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 2445 // to i32. 2446 SDValue X = (Op.getValueType() == MVT::f32) 2447 ? DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) 2448 : DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2449 Op.getOperand(0), Const1); 2450 2451 // Clear MSB. 2452 if (HasExtractInsert) 2453 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, 2454 DAG.getRegister(Mips::ZERO, MVT::i32), 2455 DAG.getConstant(31, DL, MVT::i32), Const1, X); 2456 else { 2457 // TODO: Provide DAG patterns which transform (and x, cst) 2458 // back to a (shl (srl x (clz cst)) (clz cst)) sequence. 2459 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 2460 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 2461 } 2462 2463 if (Op.getValueType() == MVT::f32) 2464 return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res); 2465 2466 // FIXME: For mips32r2, the sequence of (BuildPairF64 (ins (ExtractElementF64 2467 // Op 1), $zero, 31 1) (ExtractElementF64 Op 0)) and the Op has one use, we 2468 // should be able to drop the usage of mfc1/mtc1 and rewrite the register in 2469 // place. 2470 SDValue LowX = 2471 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 2472 DAG.getConstant(0, DL, MVT::i32)); 2473 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 2474} 2475 2476SDValue MipsTargetLowering::lowerFABS64(SDValue Op, SelectionDAG &DAG, 2477 bool HasExtractInsert) const { 2478 SDLoc DL(Op); 2479 SDValue Res, Const1 = DAG.getConstant(1, DL, MVT::i32); 2480 2481 if (DAG.getTarget().Options.NoNaNsFPMath || Subtarget.inAbs2008Mode()) 2482 return DAG.getNode(MipsISD::FAbs, DL, Op.getValueType(), Op.getOperand(0)); 2483 2484 // Bitcast to integer node. 2485 SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0)); 2486 2487 // Clear MSB. 2488 if (HasExtractInsert) 2489 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64, 2490 DAG.getRegister(Mips::ZERO_64, MVT::i64), 2491 DAG.getConstant(63, DL, MVT::i32), Const1, X); 2492 else { 2493 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1); 2494 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1); 2495 } 2496 2497 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res); 2498} 2499 2500SDValue MipsTargetLowering::lowerFABS(SDValue Op, SelectionDAG &DAG) const { 2501 if ((ABI.IsN32() || ABI.IsN64()) && (Op.getValueType() == MVT::f64)) 2502 return lowerFABS64(Op, DAG, Subtarget.hasExtractInsert()); 2503 2504 return lowerFABS32(Op, DAG, Subtarget.hasExtractInsert()); 2505} 2506 2507SDValue MipsTargetLowering:: 2508lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 2509 // check the depth 2510 if (Op.getConstantOperandVal(0) != 0) { 2511 DAG.getContext()->emitError( 2512 "return address can be determined only for current frame"); 2513 return SDValue(); 2514 } 2515 2516 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 2517 MFI.setFrameAddressIsTaken(true); 2518 EVT VT = Op.getValueType(); 2519 SDLoc DL(Op); 2520 SDValue FrameAddr = DAG.getCopyFromReg( 2521 DAG.getEntryNode(), DL, ABI.IsN64() ? Mips::FP_64 : Mips::FP, VT); 2522 return FrameAddr; 2523} 2524 2525SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op, 2526 SelectionDAG &DAG) const { 2527 if (verifyReturnAddressArgumentIsConstant(Op, DAG)) 2528 return SDValue(); 2529 2530 // check the depth 2531 if (Op.getConstantOperandVal(0) != 0) { 2532 DAG.getContext()->emitError( 2533 "return address can be determined only for current frame"); 2534 return SDValue(); 2535 } 2536 2537 MachineFunction &MF = DAG.getMachineFunction(); 2538 MachineFrameInfo &MFI = MF.getFrameInfo(); 2539 MVT VT = Op.getSimpleValueType(); 2540 unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA; 2541 MFI.setReturnAddressIsTaken(true); 2542 2543 // Return RA, which contains the return address. Mark it an implicit live-in. 2544 Register Reg = MF.addLiveIn(RA, getRegClassFor(VT)); 2545 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT); 2546} 2547 2548// An EH_RETURN is the result of lowering llvm.eh.return which in turn is 2549// generated from __builtin_eh_return (offset, handler) 2550// The effect of this is to adjust the stack pointer by "offset" 2551// and then branch to "handler". 2552SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) 2553 const { 2554 MachineFunction &MF = DAG.getMachineFunction(); 2555 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2556 2557 MipsFI->setCallsEhReturn(); 2558 SDValue Chain = Op.getOperand(0); 2559 SDValue Offset = Op.getOperand(1); 2560 SDValue Handler = Op.getOperand(2); 2561 SDLoc DL(Op); 2562 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32; 2563 2564 // Store stack offset in V1, store jump target in V0. Glue CopyToReg and 2565 // EH_RETURN nodes, so that instructions are emitted back-to-back. 2566 unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1; 2567 unsigned AddrReg = ABI.IsN64() ? Mips::V0_64 : Mips::V0; 2568 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue()); 2569 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1)); 2570 return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain, 2571 DAG.getRegister(OffsetReg, Ty), 2572 DAG.getRegister(AddrReg, getPointerTy(MF.getDataLayout())), 2573 Chain.getValue(1)); 2574} 2575 2576SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op, 2577 SelectionDAG &DAG) const { 2578 // FIXME: Need pseudo-fence for 'singlethread' fences 2579 // FIXME: Set SType for weaker fences where supported/appropriate. 2580 unsigned SType = 0; 2581 SDLoc DL(Op); 2582 return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0), 2583 DAG.getConstant(SType, DL, MVT::i32)); 2584} 2585 2586SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op, 2587 SelectionDAG &DAG) const { 2588 SDLoc DL(Op); 2589 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; 2590 2591 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2592 SDValue Shamt = Op.getOperand(2); 2593 // if shamt < (VT.bits): 2594 // lo = (shl lo, shamt) 2595 // hi = (or (shl hi, shamt) (srl (srl lo, 1), (xor shamt, (VT.bits-1)))) 2596 // else: 2597 // lo = 0 2598 // hi = (shl lo, shamt[4:0]) 2599 SDValue Not = 2600 DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2601 DAG.getConstant(VT.getSizeInBits() - 1, DL, MVT::i32)); 2602 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, 2603 DAG.getConstant(1, DL, VT)); 2604 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not); 2605 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt); 2606 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); 2607 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt); 2608 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2609 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32)); 2610 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, 2611 DAG.getConstant(0, DL, VT), ShiftLeftLo); 2612 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or); 2613 2614 SDValue Ops[2] = {Lo, Hi}; 2615 return DAG.getMergeValues(Ops, DL); 2616} 2617 2618SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, 2619 bool IsSRA) const { 2620 SDLoc DL(Op); 2621 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2622 SDValue Shamt = Op.getOperand(2); 2623 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; 2624 2625 // if shamt < (VT.bits): 2626 // lo = (or (shl (shl hi, 1), (xor shamt, (VT.bits-1))) (srl lo, shamt)) 2627 // if isSRA: 2628 // hi = (sra hi, shamt) 2629 // else: 2630 // hi = (srl hi, shamt) 2631 // else: 2632 // if isSRA: 2633 // lo = (sra hi, shamt[4:0]) 2634 // hi = (sra hi, 31) 2635 // else: 2636 // lo = (srl hi, shamt[4:0]) 2637 // hi = 0 2638 SDValue Not = 2639 DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2640 DAG.getConstant(VT.getSizeInBits() - 1, DL, MVT::i32)); 2641 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, 2642 DAG.getConstant(1, DL, VT)); 2643 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not); 2644 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt); 2645 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); 2646 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, 2647 DL, VT, Hi, Shamt); 2648 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2649 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32)); 2650 SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi, 2651 DAG.getConstant(VT.getSizeInBits() - 1, DL, VT)); 2652 2653 if (!(Subtarget.hasMips4() || Subtarget.hasMips32())) { 2654 SDVTList VTList = DAG.getVTList(VT, VT); 2655 return DAG.getNode(Subtarget.isGP64bit() ? Mips::PseudoD_SELECT_I64 2656 : Mips::PseudoD_SELECT_I, 2657 DL, VTList, Cond, ShiftRightHi, 2658 IsSRA ? Ext : DAG.getConstant(0, DL, VT), Or, 2659 ShiftRightHi); 2660 } 2661 2662 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or); 2663 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, 2664 IsSRA ? Ext : DAG.getConstant(0, DL, VT), ShiftRightHi); 2665 2666 SDValue Ops[2] = {Lo, Hi}; 2667 return DAG.getMergeValues(Ops, DL); 2668} 2669 2670static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, 2671 SDValue Chain, SDValue Src, unsigned Offset) { 2672 SDValue Ptr = LD->getBasePtr(); 2673 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT(); 2674 EVT BasePtrVT = Ptr.getValueType(); 2675 SDLoc DL(LD); 2676 SDVTList VTList = DAG.getVTList(VT, MVT::Other); 2677 2678 if (Offset) 2679 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2680 DAG.getConstant(Offset, DL, BasePtrVT)); 2681 2682 SDValue Ops[] = { Chain, Ptr, Src }; 2683 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, 2684 LD->getMemOperand()); 2685} 2686 2687// Expand an unaligned 32 or 64-bit integer load node. 2688SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const { 2689 LoadSDNode *LD = cast<LoadSDNode>(Op); 2690 EVT MemVT = LD->getMemoryVT(); 2691 2692 if (Subtarget.systemSupportsUnalignedAccess()) 2693 return Op; 2694 2695 // Return if load is aligned or if MemVT is neither i32 nor i64. 2696 if ((LD->getAlign().value() >= (MemVT.getSizeInBits() / 8)) || 2697 ((MemVT != MVT::i32) && (MemVT != MVT::i64))) 2698 return SDValue(); 2699 2700 bool IsLittle = Subtarget.isLittle(); 2701 EVT VT = Op.getValueType(); 2702 ISD::LoadExtType ExtType = LD->getExtensionType(); 2703 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT); 2704 2705 assert((VT == MVT::i32) || (VT == MVT::i64)); 2706 2707 // Expand 2708 // (set dst, (i64 (load baseptr))) 2709 // to 2710 // (set tmp, (ldl (add baseptr, 7), undef)) 2711 // (set dst, (ldr baseptr, tmp)) 2712 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) { 2713 SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef, 2714 IsLittle ? 7 : 0); 2715 return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL, 2716 IsLittle ? 0 : 7); 2717 } 2718 2719 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef, 2720 IsLittle ? 3 : 0); 2721 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL, 2722 IsLittle ? 0 : 3); 2723 2724 // Expand 2725 // (set dst, (i32 (load baseptr))) or 2726 // (set dst, (i64 (sextload baseptr))) or 2727 // (set dst, (i64 (extload baseptr))) 2728 // to 2729 // (set tmp, (lwl (add baseptr, 3), undef)) 2730 // (set dst, (lwr baseptr, tmp)) 2731 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) || 2732 (ExtType == ISD::EXTLOAD)) 2733 return LWR; 2734 2735 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)); 2736 2737 // Expand 2738 // (set dst, (i64 (zextload baseptr))) 2739 // to 2740 // (set tmp0, (lwl (add baseptr, 3), undef)) 2741 // (set tmp1, (lwr baseptr, tmp0)) 2742 // (set tmp2, (shl tmp1, 32)) 2743 // (set dst, (srl tmp2, 32)) 2744 SDLoc DL(LD); 2745 SDValue Const32 = DAG.getConstant(32, DL, MVT::i32); 2746 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32); 2747 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32); 2748 SDValue Ops[] = { SRL, LWR.getValue(1) }; 2749 return DAG.getMergeValues(Ops, DL); 2750} 2751 2752static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD, 2753 SDValue Chain, unsigned Offset) { 2754 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue(); 2755 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType(); 2756 SDLoc DL(SD); 2757 SDVTList VTList = DAG.getVTList(MVT::Other); 2758 2759 if (Offset) 2760 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2761 DAG.getConstant(Offset, DL, BasePtrVT)); 2762 2763 SDValue Ops[] = { Chain, Value, Ptr }; 2764 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, 2765 SD->getMemOperand()); 2766} 2767 2768// Expand an unaligned 32 or 64-bit integer store node. 2769static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG, 2770 bool IsLittle) { 2771 SDValue Value = SD->getValue(), Chain = SD->getChain(); 2772 EVT VT = Value.getValueType(); 2773 2774 // Expand 2775 // (store val, baseptr) or 2776 // (truncstore val, baseptr) 2777 // to 2778 // (swl val, (add baseptr, 3)) 2779 // (swr val, baseptr) 2780 if ((VT == MVT::i32) || SD->isTruncatingStore()) { 2781 SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain, 2782 IsLittle ? 3 : 0); 2783 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3); 2784 } 2785 2786 assert(VT == MVT::i64); 2787 2788 // Expand 2789 // (store val, baseptr) 2790 // to 2791 // (sdl val, (add baseptr, 7)) 2792 // (sdr val, baseptr) 2793 SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0); 2794 return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7); 2795} 2796 2797// Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr). 2798static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG, 2799 bool SingleFloat) { 2800 SDValue Val = SD->getValue(); 2801 2802 if (Val.getOpcode() != ISD::FP_TO_SINT || 2803 (Val.getValueSizeInBits() > 32 && SingleFloat)) 2804 return SDValue(); 2805 2806 EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits()); 2807 SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy, 2808 Val.getOperand(0)); 2809 return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(), 2810 SD->getPointerInfo(), SD->getAlign(), 2811 SD->getMemOperand()->getFlags()); 2812} 2813 2814SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const { 2815 StoreSDNode *SD = cast<StoreSDNode>(Op); 2816 EVT MemVT = SD->getMemoryVT(); 2817 2818 // Lower unaligned integer stores. 2819 if (!Subtarget.systemSupportsUnalignedAccess() && 2820 (SD->getAlign().value() < (MemVT.getSizeInBits() / 8)) && 2821 ((MemVT == MVT::i32) || (MemVT == MVT::i64))) 2822 return lowerUnalignedIntStore(SD, DAG, Subtarget.isLittle()); 2823 2824 return lowerFP_TO_SINT_STORE(SD, DAG, Subtarget.isSingleFloat()); 2825} 2826 2827SDValue MipsTargetLowering::lowerEH_DWARF_CFA(SDValue Op, 2828 SelectionDAG &DAG) const { 2829 2830 // Return a fixed StackObject with offset 0 which points to the old stack 2831 // pointer. 2832 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 2833 EVT ValTy = Op->getValueType(0); 2834 int FI = MFI.CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false); 2835 return DAG.getFrameIndex(FI, ValTy); 2836} 2837 2838SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op, 2839 SelectionDAG &DAG) const { 2840 if (Op.getValueSizeInBits() > 32 && Subtarget.isSingleFloat()) 2841 return SDValue(); 2842 2843 EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits()); 2844 SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy, 2845 Op.getOperand(0)); 2846 return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc); 2847} 2848 2849//===----------------------------------------------------------------------===// 2850// Calling Convention Implementation 2851//===----------------------------------------------------------------------===// 2852 2853//===----------------------------------------------------------------------===// 2854// TODO: Implement a generic logic using tblgen that can support this. 2855// Mips O32 ABI rules: 2856// --- 2857// i32 - Passed in A0, A1, A2, A3 and stack 2858// f32 - Only passed in f32 registers if no int reg has been used yet to hold 2859// an argument. Otherwise, passed in A1, A2, A3 and stack. 2860// f64 - Only passed in two aliased f32 registers if no int reg has been used 2861// yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is 2862// not used, it must be shadowed. If only A3 is available, shadow it and 2863// go to stack. 2864// vXiX - Received as scalarized i32s, passed in A0 - A3 and the stack. 2865// vXf32 - Passed in either a pair of registers {A0, A1}, {A2, A3} or {A0 - A3} 2866// with the remainder spilled to the stack. 2867// vXf64 - Passed in either {A0, A1, A2, A3} or {A2, A3} and in both cases 2868// spilling the remainder to the stack. 2869// 2870// For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack. 2871//===----------------------------------------------------------------------===// 2872 2873static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, 2874 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, 2875 CCState &State, ArrayRef<MCPhysReg> F64Regs) { 2876 const MipsSubtarget &Subtarget = static_cast<const MipsSubtarget &>( 2877 State.getMachineFunction().getSubtarget()); 2878 2879 static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 }; 2880 2881 const MipsCCState * MipsState = static_cast<MipsCCState *>(&State); 2882 2883 static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 }; 2884 2885 static const MCPhysReg FloatVectorIntRegs[] = { Mips::A0, Mips::A2 }; 2886 2887 // Do not process byval args here. 2888 if (ArgFlags.isByVal()) 2889 return true; 2890 2891 // Promote i8 and i16 2892 if (ArgFlags.isInReg() && !Subtarget.isLittle()) { 2893 if (LocVT == MVT::i8 || LocVT == MVT::i16 || LocVT == MVT::i32) { 2894 LocVT = MVT::i32; 2895 if (ArgFlags.isSExt()) 2896 LocInfo = CCValAssign::SExtUpper; 2897 else if (ArgFlags.isZExt()) 2898 LocInfo = CCValAssign::ZExtUpper; 2899 else 2900 LocInfo = CCValAssign::AExtUpper; 2901 } 2902 } 2903 2904 // Promote i8 and i16 2905 if (LocVT == MVT::i8 || LocVT == MVT::i16) { 2906 LocVT = MVT::i32; 2907 if (ArgFlags.isSExt()) 2908 LocInfo = CCValAssign::SExt; 2909 else if (ArgFlags.isZExt()) 2910 LocInfo = CCValAssign::ZExt; 2911 else 2912 LocInfo = CCValAssign::AExt; 2913 } 2914 2915 unsigned Reg; 2916 2917 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following 2918 // is true: function is vararg, argument is 3rd or higher, there is previous 2919 // argument which is not f32 or f64. 2920 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 || 2921 State.getFirstUnallocated(F32Regs) != ValNo; 2922 Align OrigAlign = ArgFlags.getNonZeroOrigAlign(); 2923 bool isI64 = (ValVT == MVT::i32 && OrigAlign == Align(8)); 2924 bool isVectorFloat = MipsState->WasOriginalArgVectorFloat(ValNo); 2925 2926 // The MIPS vector ABI for floats passes them in a pair of registers 2927 if (ValVT == MVT::i32 && isVectorFloat) { 2928 // This is the start of an vector that was scalarized into an unknown number 2929 // of components. It doesn't matter how many there are. Allocate one of the 2930 // notional 8 byte aligned registers which map onto the argument stack, and 2931 // shadow the register lost to alignment requirements. 2932 if (ArgFlags.isSplit()) { 2933 Reg = State.AllocateReg(FloatVectorIntRegs); 2934 if (Reg == Mips::A2) 2935 State.AllocateReg(Mips::A1); 2936 else if (Reg == 0) 2937 State.AllocateReg(Mips::A3); 2938 } else { 2939 // If we're an intermediate component of the split, we can just attempt to 2940 // allocate a register directly. 2941 Reg = State.AllocateReg(IntRegs); 2942 } 2943 } else if (ValVT == MVT::i32 || 2944 (ValVT == MVT::f32 && AllocateFloatsInIntReg)) { 2945 Reg = State.AllocateReg(IntRegs); 2946 // If this is the first part of an i64 arg, 2947 // the allocated register must be either A0 or A2. 2948 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3)) 2949 Reg = State.AllocateReg(IntRegs); 2950 LocVT = MVT::i32; 2951 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) { 2952 // Allocate int register and shadow next int register. If first 2953 // available register is Mips::A1 or Mips::A3, shadow it too. 2954 Reg = State.AllocateReg(IntRegs); 2955 if (Reg == Mips::A1 || Reg == Mips::A3) 2956 Reg = State.AllocateReg(IntRegs); 2957 2958 if (Reg) { 2959 LocVT = MVT::i32; 2960 2961 State.addLoc( 2962 CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2963 MCRegister HiReg = State.AllocateReg(IntRegs); 2964 assert(HiReg); 2965 State.addLoc( 2966 CCValAssign::getCustomReg(ValNo, ValVT, HiReg, LocVT, LocInfo)); 2967 return false; 2968 } 2969 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) { 2970 // we are guaranteed to find an available float register 2971 if (ValVT == MVT::f32) { 2972 Reg = State.AllocateReg(F32Regs); 2973 // Shadow int register 2974 State.AllocateReg(IntRegs); 2975 } else { 2976 Reg = State.AllocateReg(F64Regs); 2977 // Shadow int registers 2978 unsigned Reg2 = State.AllocateReg(IntRegs); 2979 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) 2980 State.AllocateReg(IntRegs); 2981 State.AllocateReg(IntRegs); 2982 } 2983 } else 2984 llvm_unreachable("Cannot handle this ValVT."); 2985 2986 if (!Reg) { 2987 unsigned Offset = State.AllocateStack(ValVT.getStoreSize(), OrigAlign); 2988 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 2989 } else 2990 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2991 2992 return false; 2993} 2994 2995static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, 2996 MVT LocVT, CCValAssign::LocInfo LocInfo, 2997 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2998 static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 }; 2999 3000 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 3001} 3002 3003static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, 3004 MVT LocVT, CCValAssign::LocInfo LocInfo, 3005 ISD::ArgFlagsTy ArgFlags, CCState &State) { 3006 static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 }; 3007 3008 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 3009} 3010 3011static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, 3012 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, 3013 CCState &State) LLVM_ATTRIBUTE_UNUSED; 3014 3015#include "MipsGenCallingConv.inc" 3016 3017 CCAssignFn *MipsTargetLowering::CCAssignFnForCall() const{ 3018 return CC_Mips_FixedArg; 3019 } 3020 3021 CCAssignFn *MipsTargetLowering::CCAssignFnForReturn() const{ 3022 return RetCC_Mips; 3023 } 3024//===----------------------------------------------------------------------===// 3025// Call Calling Convention Implementation 3026//===----------------------------------------------------------------------===// 3027 3028SDValue MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset, 3029 SDValue Chain, SDValue Arg, 3030 const SDLoc &DL, bool IsTailCall, 3031 SelectionDAG &DAG) const { 3032 if (!IsTailCall) { 3033 SDValue PtrOff = 3034 DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr, 3035 DAG.getIntPtrConstant(Offset, DL)); 3036 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo()); 3037 } 3038 3039 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 3040 int FI = MFI.CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false); 3041 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 3042 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(), MaybeAlign(), 3043 MachineMemOperand::MOVolatile); 3044} 3045 3046void MipsTargetLowering:: 3047getOpndList(SmallVectorImpl<SDValue> &Ops, 3048 std::deque<std::pair<unsigned, SDValue>> &RegsToPass, 3049 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 3050 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, 3051 SDValue Chain) const { 3052 // Insert node "GP copy globalreg" before call to function. 3053 // 3054 // R_MIPS_CALL* operators (emitted when non-internal functions are called 3055 // in PIC mode) allow symbols to be resolved via lazy binding. 3056 // The lazy binding stub requires GP to point to the GOT. 3057 // Note that we don't need GP to point to the GOT for indirect calls 3058 // (when R_MIPS_CALL* is not used for the call) because Mips linker generates 3059 // lazy binding stub for a function only when R_MIPS_CALL* are the only relocs 3060 // used for the function (that is, Mips linker doesn't generate lazy binding 3061 // stub for a function whose address is taken in the program). 3062 if (IsPICCall && !InternalLinkage && IsCallReloc) { 3063 unsigned GPReg = ABI.IsN64() ? Mips::GP_64 : Mips::GP; 3064 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32; 3065 RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty))); 3066 } 3067 3068 // Build a sequence of copy-to-reg nodes chained together with token 3069 // chain and flag operands which copy the outgoing args into registers. 3070 // The InGlue in necessary since all emitted instructions must be 3071 // stuck together. 3072 SDValue InGlue; 3073 3074 for (auto &R : RegsToPass) { 3075 Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, R.first, R.second, InGlue); 3076 InGlue = Chain.getValue(1); 3077 } 3078 3079 // Add argument registers to the end of the list so that they are 3080 // known live into the call. 3081 for (auto &R : RegsToPass) 3082 Ops.push_back(CLI.DAG.getRegister(R.first, R.second.getValueType())); 3083 3084 // Add a register mask operand representing the call-preserved registers. 3085 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); 3086 const uint32_t *Mask = 3087 TRI->getCallPreservedMask(CLI.DAG.getMachineFunction(), CLI.CallConv); 3088 assert(Mask && "Missing call preserved mask for calling convention"); 3089 if (Subtarget.inMips16HardFloat()) { 3090 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) { 3091 StringRef Sym = G->getGlobal()->getName(); 3092 Function *F = G->getGlobal()->getParent()->getFunction(Sym); 3093 if (F && F->hasFnAttribute("__Mips16RetHelper")) { 3094 Mask = MipsRegisterInfo::getMips16RetHelperMask(); 3095 } 3096 } 3097 } 3098 Ops.push_back(CLI.DAG.getRegisterMask(Mask)); 3099 3100 if (InGlue.getNode()) 3101 Ops.push_back(InGlue); 3102} 3103 3104void MipsTargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI, 3105 SDNode *Node) const { 3106 switch (MI.getOpcode()) { 3107 default: 3108 return; 3109 case Mips::JALR: 3110 case Mips::JALRPseudo: 3111 case Mips::JALR64: 3112 case Mips::JALR64Pseudo: 3113 case Mips::JALR16_MM: 3114 case Mips::JALRC16_MMR6: 3115 case Mips::TAILCALLREG: 3116 case Mips::TAILCALLREG64: 3117 case Mips::TAILCALLR6REG: 3118 case Mips::TAILCALL64R6REG: 3119 case Mips::TAILCALLREG_MM: 3120 case Mips::TAILCALLREG_MMR6: { 3121 if (!EmitJalrReloc || 3122 Subtarget.inMips16Mode() || 3123 !isPositionIndependent() || 3124 Node->getNumOperands() < 1 || 3125 Node->getOperand(0).getNumOperands() < 2) { 3126 return; 3127 } 3128 // We are after the callee address, set by LowerCall(). 3129 // If added to MI, asm printer will emit .reloc R_MIPS_JALR for the 3130 // symbol. 3131 const SDValue TargetAddr = Node->getOperand(0).getOperand(1); 3132 StringRef Sym; 3133 if (const GlobalAddressSDNode *G = 3134 dyn_cast_or_null<const GlobalAddressSDNode>(TargetAddr)) { 3135 // We must not emit the R_MIPS_JALR relocation against data symbols 3136 // since this will cause run-time crashes if the linker replaces the 3137 // call instruction with a relative branch to the data symbol. 3138 if (!isa<Function>(G->getGlobal())) { 3139 LLVM_DEBUG(dbgs() << "Not adding R_MIPS_JALR against data symbol " 3140 << G->getGlobal()->getName() << "\n"); 3141 return; 3142 } 3143 Sym = G->getGlobal()->getName(); 3144 } 3145 else if (const ExternalSymbolSDNode *ES = 3146 dyn_cast_or_null<const ExternalSymbolSDNode>(TargetAddr)) { 3147 Sym = ES->getSymbol(); 3148 } 3149 3150 if (Sym.empty()) 3151 return; 3152 3153 MachineFunction *MF = MI.getParent()->getParent(); 3154 MCSymbol *S = MF->getContext().getOrCreateSymbol(Sym); 3155 LLVM_DEBUG(dbgs() << "Adding R_MIPS_JALR against " << Sym << "\n"); 3156 MI.addOperand(MachineOperand::CreateMCSymbol(S, MipsII::MO_JALR)); 3157 } 3158 } 3159} 3160 3161/// LowerCall - functions arguments are copied from virtual regs to 3162/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 3163SDValue 3164MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 3165 SmallVectorImpl<SDValue> &InVals) const { 3166 SelectionDAG &DAG = CLI.DAG; 3167 SDLoc DL = CLI.DL; 3168 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; 3169 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; 3170 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; 3171 SDValue Chain = CLI.Chain; 3172 SDValue Callee = CLI.Callee; 3173 bool &IsTailCall = CLI.IsTailCall; 3174 CallingConv::ID CallConv = CLI.CallConv; 3175 bool IsVarArg = CLI.IsVarArg; 3176 3177 MachineFunction &MF = DAG.getMachineFunction(); 3178 MachineFrameInfo &MFI = MF.getFrameInfo(); 3179 const TargetFrameLowering *TFL = Subtarget.getFrameLowering(); 3180 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 3181 bool IsPIC = isPositionIndependent(); 3182 3183 // Analyze operands of the call, assigning locations to each operand. 3184 SmallVector<CCValAssign, 16> ArgLocs; 3185 MipsCCState CCInfo( 3186 CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(), 3187 MipsCCState::getSpecialCallingConvForCallee(Callee.getNode(), Subtarget)); 3188 3189 const ExternalSymbolSDNode *ES = 3190 dyn_cast_or_null<const ExternalSymbolSDNode>(Callee.getNode()); 3191 3192 // There is one case where CALLSEQ_START..CALLSEQ_END can be nested, which 3193 // is during the lowering of a call with a byval argument which produces 3194 // a call to memcpy. For the O32 case, this causes the caller to allocate 3195 // stack space for the reserved argument area for the callee, then recursively 3196 // again for the memcpy call. In the NEWABI case, this doesn't occur as those 3197 // ABIs mandate that the callee allocates the reserved argument area. We do 3198 // still produce nested CALLSEQ_START..CALLSEQ_END with zero space though. 3199 // 3200 // If the callee has a byval argument and memcpy is used, we are mandated 3201 // to already have produced a reserved argument area for the callee for O32. 3202 // Therefore, the reserved argument area can be reused for both calls. 3203 // 3204 // Other cases of calling memcpy cannot have a chain with a CALLSEQ_START 3205 // present, as we have yet to hook that node onto the chain. 3206 // 3207 // Hence, the CALLSEQ_START and CALLSEQ_END nodes can be eliminated in this 3208 // case. GCC does a similar trick, in that wherever possible, it calculates 3209 // the maximum out going argument area (including the reserved area), and 3210 // preallocates the stack space on entrance to the caller. 3211 // 3212 // FIXME: We should do the same for efficiency and space. 3213 3214 // Note: The check on the calling convention below must match 3215 // MipsABIInfo::GetCalleeAllocdArgSizeInBytes(). 3216 bool MemcpyInByVal = ES && 3217 StringRef(ES->getSymbol()) == StringRef("memcpy") && 3218 CallConv != CallingConv::Fast && 3219 Chain.getOpcode() == ISD::CALLSEQ_START; 3220 3221 // Allocate the reserved argument area. It seems strange to do this from the 3222 // caller side but removing it breaks the frame size calculation. 3223 unsigned ReservedArgArea = 3224 MemcpyInByVal ? 0 : ABI.GetCalleeAllocdArgSizeInBytes(CallConv); 3225 CCInfo.AllocateStack(ReservedArgArea, Align(1)); 3226 3227 CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(), 3228 ES ? ES->getSymbol() : nullptr); 3229 3230 // Get a count of how many bytes are to be pushed on the stack. 3231 unsigned StackSize = CCInfo.getStackSize(); 3232 3233 // Call site info for function parameters tracking. 3234 MachineFunction::CallSiteInfo CSInfo; 3235 3236 // Check if it's really possible to do a tail call. Restrict it to functions 3237 // that are part of this compilation unit. 3238 bool InternalLinkage = false; 3239 if (IsTailCall) { 3240 IsTailCall = isEligibleForTailCallOptimization( 3241 CCInfo, StackSize, *MF.getInfo<MipsFunctionInfo>()); 3242 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 3243 InternalLinkage = G->getGlobal()->hasInternalLinkage(); 3244 IsTailCall &= (InternalLinkage || G->getGlobal()->hasLocalLinkage() || 3245 G->getGlobal()->hasPrivateLinkage() || 3246 G->getGlobal()->hasHiddenVisibility() || 3247 G->getGlobal()->hasProtectedVisibility()); 3248 } 3249 } 3250 if (!IsTailCall && CLI.CB && CLI.CB->isMustTailCall()) 3251 report_fatal_error("failed to perform tail call elimination on a call " 3252 "site marked musttail"); 3253 3254 if (IsTailCall) 3255 ++NumTailCalls; 3256 3257 // Chain is the output chain of the last Load/Store or CopyToReg node. 3258 // ByValChain is the output chain of the last Memcpy node created for copying 3259 // byval arguments to the stack. 3260 unsigned StackAlignment = TFL->getStackAlignment(); 3261 StackSize = alignTo(StackSize, StackAlignment); 3262 3263 if (!(IsTailCall || MemcpyInByVal)) 3264 Chain = DAG.getCALLSEQ_START(Chain, StackSize, 0, DL); 3265 3266 SDValue StackPtr = 3267 DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP, 3268 getPointerTy(DAG.getDataLayout())); 3269 3270 std::deque<std::pair<unsigned, SDValue>> RegsToPass; 3271 SmallVector<SDValue, 8> MemOpChains; 3272 3273 CCInfo.rewindByValRegsInfo(); 3274 3275 // Walk the register/memloc assignments, inserting copies/loads. 3276 for (unsigned i = 0, e = ArgLocs.size(), OutIdx = 0; i != e; ++i, ++OutIdx) { 3277 SDValue Arg = OutVals[OutIdx]; 3278 CCValAssign &VA = ArgLocs[i]; 3279 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); 3280 ISD::ArgFlagsTy Flags = Outs[OutIdx].Flags; 3281 bool UseUpperBits = false; 3282 3283 // ByVal Arg. 3284 if (Flags.isByVal()) { 3285 unsigned FirstByValReg, LastByValReg; 3286 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed(); 3287 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg); 3288 3289 assert(Flags.getByValSize() && 3290 "ByVal args of size 0 should have been ignored by front-end."); 3291 assert(ByValIdx < CCInfo.getInRegsParamsCount()); 3292 assert(!IsTailCall && 3293 "Do not tail-call optimize if there is a byval argument."); 3294 passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg, 3295 FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(), 3296 VA); 3297 CCInfo.nextInRegsParam(); 3298 continue; 3299 } 3300 3301 // Promote the value if needed. 3302 switch (VA.getLocInfo()) { 3303 default: 3304 llvm_unreachable("Unknown loc info!"); 3305 case CCValAssign::Full: 3306 if (VA.isRegLoc()) { 3307 if ((ValVT == MVT::f32 && LocVT == MVT::i32) || 3308 (ValVT == MVT::f64 && LocVT == MVT::i64) || 3309 (ValVT == MVT::i64 && LocVT == MVT::f64)) 3310 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); 3311 else if (ValVT == MVT::f64 && LocVT == MVT::i32) { 3312 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 3313 Arg, DAG.getConstant(0, DL, MVT::i32)); 3314 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 3315 Arg, DAG.getConstant(1, DL, MVT::i32)); 3316 if (!Subtarget.isLittle()) 3317 std::swap(Lo, Hi); 3318 3319 assert(VA.needsCustom()); 3320 3321 Register LocRegLo = VA.getLocReg(); 3322 Register LocRegHigh = ArgLocs[++i].getLocReg(); 3323 RegsToPass.push_back(std::make_pair(LocRegLo, Lo)); 3324 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi)); 3325 continue; 3326 } 3327 } 3328 break; 3329 case CCValAssign::BCvt: 3330 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); 3331 break; 3332 case CCValAssign::SExtUpper: 3333 UseUpperBits = true; 3334 [[fallthrough]]; 3335 case CCValAssign::SExt: 3336 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg); 3337 break; 3338 case CCValAssign::ZExtUpper: 3339 UseUpperBits = true; 3340 [[fallthrough]]; 3341 case CCValAssign::ZExt: 3342 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg); 3343 break; 3344 case CCValAssign::AExtUpper: 3345 UseUpperBits = true; 3346 [[fallthrough]]; 3347 case CCValAssign::AExt: 3348 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg); 3349 break; 3350 } 3351 3352 if (UseUpperBits) { 3353 unsigned ValSizeInBits = Outs[OutIdx].ArgVT.getSizeInBits(); 3354 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3355 Arg = DAG.getNode( 3356 ISD::SHL, DL, VA.getLocVT(), Arg, 3357 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3358 } 3359 3360 // Arguments that can be passed on register must be kept at 3361 // RegsToPass vector 3362 if (VA.isRegLoc()) { 3363 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 3364 3365 // If the parameter is passed through reg $D, which splits into 3366 // two physical registers, avoid creating call site info. 3367 if (Mips::AFGR64RegClass.contains(VA.getLocReg())) 3368 continue; 3369 3370 // Collect CSInfo about which register passes which parameter. 3371 const TargetOptions &Options = DAG.getTarget().Options; 3372 if (Options.SupportsDebugEntryValues) 3373 CSInfo.emplace_back(VA.getLocReg(), i); 3374 3375 continue; 3376 } 3377 3378 // Register can't get to this point... 3379 assert(VA.isMemLoc()); 3380 3381 // emit ISD::STORE whichs stores the 3382 // parameter value to a stack Location 3383 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(), 3384 Chain, Arg, DL, IsTailCall, DAG)); 3385 } 3386 3387 // Transform all store nodes into one single node because all store 3388 // nodes are independent of each other. 3389 if (!MemOpChains.empty()) 3390 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); 3391 3392 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 3393 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 3394 // node so that legalize doesn't hack it. 3395 3396 EVT Ty = Callee.getValueType(); 3397 bool GlobalOrExternal = false, IsCallReloc = false; 3398 3399 // The long-calls feature is ignored in case of PIC. 3400 // While we do not support -mshared / -mno-shared properly, 3401 // ignore long-calls in case of -mabicalls too. 3402 if (!Subtarget.isABICalls() && !IsPIC) { 3403 // If the function should be called using "long call", 3404 // get its address into a register to prevent using 3405 // of the `jal` instruction for the direct call. 3406 if (auto *N = dyn_cast<ExternalSymbolSDNode>(Callee)) { 3407 if (Subtarget.useLongCalls()) 3408 Callee = Subtarget.hasSym32() 3409 ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 3410 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 3411 } else if (auto *N = dyn_cast<GlobalAddressSDNode>(Callee)) { 3412 bool UseLongCalls = Subtarget.useLongCalls(); 3413 // If the function has long-call/far/near attribute 3414 // it overrides command line switch pased to the backend. 3415 if (auto *F = dyn_cast<Function>(N->getGlobal())) { 3416 if (F->hasFnAttribute("long-call")) 3417 UseLongCalls = true; 3418 else if (F->hasFnAttribute("short-call")) 3419 UseLongCalls = false; 3420 } 3421 if (UseLongCalls) 3422 Callee = Subtarget.hasSym32() 3423 ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 3424 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 3425 } 3426 } 3427 3428 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 3429 if (IsPIC) { 3430 const GlobalValue *Val = G->getGlobal(); 3431 InternalLinkage = Val->hasInternalLinkage(); 3432 3433 if (InternalLinkage) 3434 Callee = getAddrLocal(G, DL, Ty, DAG, ABI.IsN32() || ABI.IsN64()); 3435 else if (Subtarget.useXGOT()) { 3436 Callee = getAddrGlobalLargeGOT(G, DL, Ty, DAG, MipsII::MO_CALL_HI16, 3437 MipsII::MO_CALL_LO16, Chain, 3438 FuncInfo->callPtrInfo(MF, Val)); 3439 IsCallReloc = true; 3440 } else { 3441 Callee = getAddrGlobal(G, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain, 3442 FuncInfo->callPtrInfo(MF, Val)); 3443 IsCallReloc = true; 3444 } 3445 } else 3446 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, 3447 getPointerTy(DAG.getDataLayout()), 0, 3448 MipsII::MO_NO_FLAG); 3449 GlobalOrExternal = true; 3450 } 3451 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 3452 const char *Sym = S->getSymbol(); 3453 3454 if (!IsPIC) // static 3455 Callee = DAG.getTargetExternalSymbol( 3456 Sym, getPointerTy(DAG.getDataLayout()), MipsII::MO_NO_FLAG); 3457 else if (Subtarget.useXGOT()) { 3458 Callee = getAddrGlobalLargeGOT(S, DL, Ty, DAG, MipsII::MO_CALL_HI16, 3459 MipsII::MO_CALL_LO16, Chain, 3460 FuncInfo->callPtrInfo(MF, Sym)); 3461 IsCallReloc = true; 3462 } else { // PIC 3463 Callee = getAddrGlobal(S, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain, 3464 FuncInfo->callPtrInfo(MF, Sym)); 3465 IsCallReloc = true; 3466 } 3467 3468 GlobalOrExternal = true; 3469 } 3470 3471 SmallVector<SDValue, 8> Ops(1, Chain); 3472 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 3473 3474 getOpndList(Ops, RegsToPass, IsPIC, GlobalOrExternal, InternalLinkage, 3475 IsCallReloc, CLI, Callee, Chain); 3476 3477 if (IsTailCall) { 3478 MF.getFrameInfo().setHasTailCall(); 3479 SDValue Ret = DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops); 3480 DAG.addCallSiteInfo(Ret.getNode(), std::move(CSInfo)); 3481 return Ret; 3482 } 3483 3484 Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops); 3485 SDValue InGlue = Chain.getValue(1); 3486 3487 DAG.addCallSiteInfo(Chain.getNode(), std::move(CSInfo)); 3488 3489 // Create the CALLSEQ_END node in the case of where it is not a call to 3490 // memcpy. 3491 if (!(MemcpyInByVal)) { 3492 Chain = DAG.getCALLSEQ_END(Chain, StackSize, 0, InGlue, DL); 3493 InGlue = Chain.getValue(1); 3494 } 3495 3496 // Handle result values, copying them out of physregs into vregs that we 3497 // return. 3498 return LowerCallResult(Chain, InGlue, CallConv, IsVarArg, Ins, DL, DAG, 3499 InVals, CLI); 3500} 3501 3502/// LowerCallResult - Lower the result values of a call into the 3503/// appropriate copies out of appropriate physical registers. 3504SDValue MipsTargetLowering::LowerCallResult( 3505 SDValue Chain, SDValue InGlue, CallingConv::ID CallConv, bool IsVarArg, 3506 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, 3507 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, 3508 TargetLowering::CallLoweringInfo &CLI) const { 3509 // Assign locations to each value returned by this call. 3510 SmallVector<CCValAssign, 16> RVLocs; 3511 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, 3512 *DAG.getContext()); 3513 3514 const ExternalSymbolSDNode *ES = 3515 dyn_cast_or_null<const ExternalSymbolSDNode>(CLI.Callee.getNode()); 3516 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips, CLI.RetTy, 3517 ES ? ES->getSymbol() : nullptr); 3518 3519 // Copy all of the result registers out of their specified physreg. 3520 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3521 CCValAssign &VA = RVLocs[i]; 3522 assert(VA.isRegLoc() && "Can only return in registers!"); 3523 3524 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(), 3525 RVLocs[i].getLocVT(), InGlue); 3526 Chain = Val.getValue(1); 3527 InGlue = Val.getValue(2); 3528 3529 if (VA.isUpperBitsInLoc()) { 3530 unsigned ValSizeInBits = Ins[i].ArgVT.getSizeInBits(); 3531 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3532 unsigned Shift = 3533 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA; 3534 Val = DAG.getNode( 3535 Shift, DL, VA.getLocVT(), Val, 3536 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3537 } 3538 3539 switch (VA.getLocInfo()) { 3540 default: 3541 llvm_unreachable("Unknown loc info!"); 3542 case CCValAssign::Full: 3543 break; 3544 case CCValAssign::BCvt: 3545 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val); 3546 break; 3547 case CCValAssign::AExt: 3548 case CCValAssign::AExtUpper: 3549 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 3550 break; 3551 case CCValAssign::ZExt: 3552 case CCValAssign::ZExtUpper: 3553 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val, 3554 DAG.getValueType(VA.getValVT())); 3555 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 3556 break; 3557 case CCValAssign::SExt: 3558 case CCValAssign::SExtUpper: 3559 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val, 3560 DAG.getValueType(VA.getValVT())); 3561 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 3562 break; 3563 } 3564 3565 InVals.push_back(Val); 3566 } 3567 3568 return Chain; 3569} 3570 3571static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA, 3572 EVT ArgVT, const SDLoc &DL, 3573 SelectionDAG &DAG) { 3574 MVT LocVT = VA.getLocVT(); 3575 EVT ValVT = VA.getValVT(); 3576 3577 // Shift into the upper bits if necessary. 3578 switch (VA.getLocInfo()) { 3579 default: 3580 break; 3581 case CCValAssign::AExtUpper: 3582 case CCValAssign::SExtUpper: 3583 case CCValAssign::ZExtUpper: { 3584 unsigned ValSizeInBits = ArgVT.getSizeInBits(); 3585 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3586 unsigned Opcode = 3587 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA; 3588 Val = DAG.getNode( 3589 Opcode, DL, VA.getLocVT(), Val, 3590 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3591 break; 3592 } 3593 } 3594 3595 // If this is an value smaller than the argument slot size (32-bit for O32, 3596 // 64-bit for N32/N64), it has been promoted in some way to the argument slot 3597 // size. Extract the value and insert any appropriate assertions regarding 3598 // sign/zero extension. 3599 switch (VA.getLocInfo()) { 3600 default: 3601 llvm_unreachable("Unknown loc info!"); 3602 case CCValAssign::Full: 3603 break; 3604 case CCValAssign::AExtUpper: 3605 case CCValAssign::AExt: 3606 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 3607 break; 3608 case CCValAssign::SExtUpper: 3609 case CCValAssign::SExt: 3610 Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT)); 3611 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 3612 break; 3613 case CCValAssign::ZExtUpper: 3614 case CCValAssign::ZExt: 3615 Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT)); 3616 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 3617 break; 3618 case CCValAssign::BCvt: 3619 Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val); 3620 break; 3621 } 3622 3623 return Val; 3624} 3625 3626//===----------------------------------------------------------------------===// 3627// Formal Arguments Calling Convention Implementation 3628//===----------------------------------------------------------------------===// 3629/// LowerFormalArguments - transform physical registers into virtual registers 3630/// and generate load operations for arguments places on the stack. 3631SDValue MipsTargetLowering::LowerFormalArguments( 3632 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 3633 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, 3634 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { 3635 MachineFunction &MF = DAG.getMachineFunction(); 3636 MachineFrameInfo &MFI = MF.getFrameInfo(); 3637 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3638 3639 MipsFI->setVarArgsFrameIndex(0); 3640 3641 // Used with vargs to acumulate store chains. 3642 std::vector<SDValue> OutChains; 3643 3644 // Assign locations to all of the incoming arguments. 3645 SmallVector<CCValAssign, 16> ArgLocs; 3646 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, 3647 *DAG.getContext()); 3648 CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), Align(1)); 3649 const Function &Func = DAG.getMachineFunction().getFunction(); 3650 Function::const_arg_iterator FuncArg = Func.arg_begin(); 3651 3652 if (Func.hasFnAttribute("interrupt") && !Func.arg_empty()) 3653 report_fatal_error( 3654 "Functions with the interrupt attribute cannot have arguments!"); 3655 3656 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg); 3657 MipsFI->setFormalArgInfo(CCInfo.getStackSize(), 3658 CCInfo.getInRegsParamsCount() > 0); 3659 3660 unsigned CurArgIdx = 0; 3661 CCInfo.rewindByValRegsInfo(); 3662 3663 for (unsigned i = 0, e = ArgLocs.size(), InsIdx = 0; i != e; ++i, ++InsIdx) { 3664 CCValAssign &VA = ArgLocs[i]; 3665 if (Ins[InsIdx].isOrigArg()) { 3666 std::advance(FuncArg, Ins[InsIdx].getOrigArgIndex() - CurArgIdx); 3667 CurArgIdx = Ins[InsIdx].getOrigArgIndex(); 3668 } 3669 EVT ValVT = VA.getValVT(); 3670 ISD::ArgFlagsTy Flags = Ins[InsIdx].Flags; 3671 bool IsRegLoc = VA.isRegLoc(); 3672 3673 if (Flags.isByVal()) { 3674 assert(Ins[InsIdx].isOrigArg() && "Byval arguments cannot be implicit"); 3675 unsigned FirstByValReg, LastByValReg; 3676 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed(); 3677 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg); 3678 3679 assert(Flags.getByValSize() && 3680 "ByVal args of size 0 should have been ignored by front-end."); 3681 assert(ByValIdx < CCInfo.getInRegsParamsCount()); 3682 copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg, 3683 FirstByValReg, LastByValReg, VA, CCInfo); 3684 CCInfo.nextInRegsParam(); 3685 continue; 3686 } 3687 3688 // Arguments stored on registers 3689 if (IsRegLoc) { 3690 MVT RegVT = VA.getLocVT(); 3691 Register ArgReg = VA.getLocReg(); 3692 const TargetRegisterClass *RC = getRegClassFor(RegVT); 3693 3694 // Transform the arguments stored on 3695 // physical registers into virtual ones 3696 unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC); 3697 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); 3698 3699 ArgValue = 3700 UnpackFromArgumentSlot(ArgValue, VA, Ins[InsIdx].ArgVT, DL, DAG); 3701 3702 // Handle floating point arguments passed in integer registers and 3703 // long double arguments passed in floating point registers. 3704 if ((RegVT == MVT::i32 && ValVT == MVT::f32) || 3705 (RegVT == MVT::i64 && ValVT == MVT::f64) || 3706 (RegVT == MVT::f64 && ValVT == MVT::i64)) 3707 ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue); 3708 else if (ABI.IsO32() && RegVT == MVT::i32 && 3709 ValVT == MVT::f64) { 3710 assert(VA.needsCustom() && "Expected custom argument for f64 split"); 3711 CCValAssign &NextVA = ArgLocs[++i]; 3712 unsigned Reg2 = 3713 addLiveIn(DAG.getMachineFunction(), NextVA.getLocReg(), RC); 3714 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT); 3715 if (!Subtarget.isLittle()) 3716 std::swap(ArgValue, ArgValue2); 3717 ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, 3718 ArgValue, ArgValue2); 3719 } 3720 3721 InVals.push_back(ArgValue); 3722 } else { // VA.isRegLoc() 3723 MVT LocVT = VA.getLocVT(); 3724 3725 assert(!VA.needsCustom() && "unexpected custom memory argument"); 3726 3727 // Only arguments pased on the stack should make it here. 3728 assert(VA.isMemLoc()); 3729 3730 // The stack pointer offset is relative to the caller stack frame. 3731 int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8, 3732 VA.getLocMemOffset(), true); 3733 3734 // Create load nodes to retrieve arguments from the stack 3735 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 3736 SDValue ArgValue = DAG.getLoad( 3737 LocVT, DL, Chain, FIN, 3738 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)); 3739 OutChains.push_back(ArgValue.getValue(1)); 3740 3741 ArgValue = 3742 UnpackFromArgumentSlot(ArgValue, VA, Ins[InsIdx].ArgVT, DL, DAG); 3743 3744 InVals.push_back(ArgValue); 3745 } 3746 } 3747 3748 for (unsigned i = 0, e = ArgLocs.size(), InsIdx = 0; i != e; ++i, ++InsIdx) { 3749 3750 if (ArgLocs[i].needsCustom()) { 3751 ++i; 3752 continue; 3753 } 3754 3755 // The mips ABIs for returning structs by value requires that we copy 3756 // the sret argument into $v0 for the return. Save the argument into 3757 // a virtual register so that we can access it from the return points. 3758 if (Ins[InsIdx].Flags.isSRet()) { 3759 unsigned Reg = MipsFI->getSRetReturnReg(); 3760 if (!Reg) { 3761 Reg = MF.getRegInfo().createVirtualRegister( 3762 getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32)); 3763 MipsFI->setSRetReturnReg(Reg); 3764 } 3765 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]); 3766 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain); 3767 break; 3768 } 3769 } 3770 3771 if (IsVarArg) 3772 writeVarArgRegs(OutChains, Chain, DL, DAG, CCInfo); 3773 3774 // All stores are grouped in one node to allow the matching between 3775 // the size of Ins and InVals. This only happens when on varg functions 3776 if (!OutChains.empty()) { 3777 OutChains.push_back(Chain); 3778 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains); 3779 } 3780 3781 return Chain; 3782} 3783 3784//===----------------------------------------------------------------------===// 3785// Return Value Calling Convention Implementation 3786//===----------------------------------------------------------------------===// 3787 3788bool 3789MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv, 3790 MachineFunction &MF, bool IsVarArg, 3791 const SmallVectorImpl<ISD::OutputArg> &Outs, 3792 LLVMContext &Context) const { 3793 SmallVector<CCValAssign, 16> RVLocs; 3794 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); 3795 return CCInfo.CheckReturn(Outs, RetCC_Mips); 3796} 3797 3798bool MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, 3799 bool IsSigned) const { 3800 if ((ABI.IsN32() || ABI.IsN64()) && Type == MVT::i32) 3801 return true; 3802 3803 return IsSigned; 3804} 3805 3806SDValue 3807MipsTargetLowering::LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps, 3808 const SDLoc &DL, 3809 SelectionDAG &DAG) const { 3810 MachineFunction &MF = DAG.getMachineFunction(); 3811 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3812 3813 MipsFI->setISR(); 3814 3815 return DAG.getNode(MipsISD::ERet, DL, MVT::Other, RetOps); 3816} 3817 3818SDValue 3819MipsTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, 3820 bool IsVarArg, 3821 const SmallVectorImpl<ISD::OutputArg> &Outs, 3822 const SmallVectorImpl<SDValue> &OutVals, 3823 const SDLoc &DL, SelectionDAG &DAG) const { 3824 // CCValAssign - represent the assignment of 3825 // the return value to a location 3826 SmallVector<CCValAssign, 16> RVLocs; 3827 MachineFunction &MF = DAG.getMachineFunction(); 3828 3829 // CCState - Info about the registers and stack slot. 3830 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); 3831 3832 // Analyze return values. 3833 CCInfo.AnalyzeReturn(Outs, RetCC_Mips); 3834 3835 SDValue Glue; 3836 SmallVector<SDValue, 4> RetOps(1, Chain); 3837 3838 // Copy the result values into the output registers. 3839 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3840 SDValue Val = OutVals[i]; 3841 CCValAssign &VA = RVLocs[i]; 3842 assert(VA.isRegLoc() && "Can only return in registers!"); 3843 bool UseUpperBits = false; 3844 3845 switch (VA.getLocInfo()) { 3846 default: 3847 llvm_unreachable("Unknown loc info!"); 3848 case CCValAssign::Full: 3849 break; 3850 case CCValAssign::BCvt: 3851 Val = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Val); 3852 break; 3853 case CCValAssign::AExtUpper: 3854 UseUpperBits = true; 3855 [[fallthrough]]; 3856 case CCValAssign::AExt: 3857 Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val); 3858 break; 3859 case CCValAssign::ZExtUpper: 3860 UseUpperBits = true; 3861 [[fallthrough]]; 3862 case CCValAssign::ZExt: 3863 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val); 3864 break; 3865 case CCValAssign::SExtUpper: 3866 UseUpperBits = true; 3867 [[fallthrough]]; 3868 case CCValAssign::SExt: 3869 Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val); 3870 break; 3871 } 3872 3873 if (UseUpperBits) { 3874 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits(); 3875 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3876 Val = DAG.getNode( 3877 ISD::SHL, DL, VA.getLocVT(), Val, 3878 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3879 } 3880 3881 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Glue); 3882 3883 // Guarantee that all emitted copies are stuck together with flags. 3884 Glue = Chain.getValue(1); 3885 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 3886 } 3887 3888 // The mips ABIs for returning structs by value requires that we copy 3889 // the sret argument into $v0 for the return. We saved the argument into 3890 // a virtual register in the entry block, so now we copy the value out 3891 // and into $v0. 3892 if (MF.getFunction().hasStructRetAttr()) { 3893 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3894 unsigned Reg = MipsFI->getSRetReturnReg(); 3895 3896 if (!Reg) 3897 llvm_unreachable("sret virtual register not created in the entry block"); 3898 SDValue Val = 3899 DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout())); 3900 unsigned V0 = ABI.IsN64() ? Mips::V0_64 : Mips::V0; 3901 3902 Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Glue); 3903 Glue = Chain.getValue(1); 3904 RetOps.push_back(DAG.getRegister(V0, getPointerTy(DAG.getDataLayout()))); 3905 } 3906 3907 RetOps[0] = Chain; // Update chain. 3908 3909 // Add the glue if we have it. 3910 if (Glue.getNode()) 3911 RetOps.push_back(Glue); 3912 3913 // ISRs must use "eret". 3914 if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt")) 3915 return LowerInterruptReturn(RetOps, DL, DAG); 3916 3917 // Standard return on Mips is a "jr $ra" 3918 return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps); 3919} 3920 3921//===----------------------------------------------------------------------===// 3922// Mips Inline Assembly Support 3923//===----------------------------------------------------------------------===// 3924 3925/// getConstraintType - Given a constraint letter, return the type of 3926/// constraint it is for this target. 3927MipsTargetLowering::ConstraintType 3928MipsTargetLowering::getConstraintType(StringRef Constraint) const { 3929 // Mips specific constraints 3930 // GCC config/mips/constraints.md 3931 // 3932 // 'd' : An address register. Equivalent to r 3933 // unless generating MIPS16 code. 3934 // 'y' : Equivalent to r; retained for 3935 // backwards compatibility. 3936 // 'c' : A register suitable for use in an indirect 3937 // jump. This will always be $25 for -mabicalls. 3938 // 'l' : The lo register. 1 word storage. 3939 // 'x' : The hilo register pair. Double word storage. 3940 if (Constraint.size() == 1) { 3941 switch (Constraint[0]) { 3942 default : break; 3943 case 'd': 3944 case 'y': 3945 case 'f': 3946 case 'c': 3947 case 'l': 3948 case 'x': 3949 return C_RegisterClass; 3950 case 'R': 3951 return C_Memory; 3952 } 3953 } 3954 3955 if (Constraint == "ZC") 3956 return C_Memory; 3957 3958 return TargetLowering::getConstraintType(Constraint); 3959} 3960 3961/// Examine constraint type and operand type and determine a weight value. 3962/// This object must already have been set up with the operand type 3963/// and the current alternative constraint selected. 3964TargetLowering::ConstraintWeight 3965MipsTargetLowering::getSingleConstraintMatchWeight( 3966 AsmOperandInfo &info, const char *constraint) const { 3967 ConstraintWeight weight = CW_Invalid; 3968 Value *CallOperandVal = info.CallOperandVal; 3969 // If we don't have a value, we can't do a match, 3970 // but allow it at the lowest weight. 3971 if (!CallOperandVal) 3972 return CW_Default; 3973 Type *type = CallOperandVal->getType(); 3974 // Look at the constraint type. 3975 switch (*constraint) { 3976 default: 3977 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 3978 break; 3979 case 'd': 3980 case 'y': 3981 if (type->isIntegerTy()) 3982 weight = CW_Register; 3983 break; 3984 case 'f': // FPU or MSA register 3985 if (Subtarget.hasMSA() && type->isVectorTy() && 3986 type->getPrimitiveSizeInBits().getFixedValue() == 128) 3987 weight = CW_Register; 3988 else if (type->isFloatTy()) 3989 weight = CW_Register; 3990 break; 3991 case 'c': // $25 for indirect jumps 3992 case 'l': // lo register 3993 case 'x': // hilo register pair 3994 if (type->isIntegerTy()) 3995 weight = CW_SpecificReg; 3996 break; 3997 case 'I': // signed 16 bit immediate 3998 case 'J': // integer zero 3999 case 'K': // unsigned 16 bit immediate 4000 case 'L': // signed 32 bit immediate where lower 16 bits are 0 4001 case 'N': // immediate in the range of -65535 to -1 (inclusive) 4002 case 'O': // signed 15 bit immediate (+- 16383) 4003 case 'P': // immediate in the range of 65535 to 1 (inclusive) 4004 if (isa<ConstantInt>(CallOperandVal)) 4005 weight = CW_Constant; 4006 break; 4007 case 'R': 4008 weight = CW_Memory; 4009 break; 4010 } 4011 return weight; 4012} 4013 4014/// This is a helper function to parse a physical register string and split it 4015/// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag 4016/// that is returned indicates whether parsing was successful. The second flag 4017/// is true if the numeric part exists. 4018static std::pair<bool, bool> parsePhysicalReg(StringRef C, StringRef &Prefix, 4019 unsigned long long &Reg) { 4020 if (C.front() != '{' || C.back() != '}') 4021 return std::make_pair(false, false); 4022 4023 // Search for the first numeric character. 4024 StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1; 4025 I = std::find_if(B, E, isdigit); 4026 4027 Prefix = StringRef(B, I - B); 4028 4029 // The second flag is set to false if no numeric characters were found. 4030 if (I == E) 4031 return std::make_pair(true, false); 4032 4033 // Parse the numeric characters. 4034 return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg), 4035 true); 4036} 4037 4038EVT MipsTargetLowering::getTypeForExtReturn(LLVMContext &Context, EVT VT, 4039 ISD::NodeType) const { 4040 bool Cond = !Subtarget.isABI_O32() && VT.getSizeInBits() == 32; 4041 EVT MinVT = getRegisterType(Cond ? MVT::i64 : MVT::i32); 4042 return VT.bitsLT(MinVT) ? MinVT : VT; 4043} 4044 4045std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering:: 4046parseRegForInlineAsmConstraint(StringRef C, MVT VT) const { 4047 const TargetRegisterInfo *TRI = 4048 Subtarget.getRegisterInfo(); 4049 const TargetRegisterClass *RC; 4050 StringRef Prefix; 4051 unsigned long long Reg; 4052 4053 std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg); 4054 4055 if (!R.first) 4056 return std::make_pair(0U, nullptr); 4057 4058 if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo. 4059 // No numeric characters follow "hi" or "lo". 4060 if (R.second) 4061 return std::make_pair(0U, nullptr); 4062 4063 RC = TRI->getRegClass(Prefix == "hi" ? 4064 Mips::HI32RegClassID : Mips::LO32RegClassID); 4065 return std::make_pair(*(RC->begin()), RC); 4066 } else if (Prefix.starts_with("$msa")) { 4067 // Parse $msa(ir|csr|access|save|modify|request|map|unmap) 4068 4069 // No numeric characters follow the name. 4070 if (R.second) 4071 return std::make_pair(0U, nullptr); 4072 4073 Reg = StringSwitch<unsigned long long>(Prefix) 4074 .Case("$msair", Mips::MSAIR) 4075 .Case("$msacsr", Mips::MSACSR) 4076 .Case("$msaaccess", Mips::MSAAccess) 4077 .Case("$msasave", Mips::MSASave) 4078 .Case("$msamodify", Mips::MSAModify) 4079 .Case("$msarequest", Mips::MSARequest) 4080 .Case("$msamap", Mips::MSAMap) 4081 .Case("$msaunmap", Mips::MSAUnmap) 4082 .Default(0); 4083 4084 if (!Reg) 4085 return std::make_pair(0U, nullptr); 4086 4087 RC = TRI->getRegClass(Mips::MSACtrlRegClassID); 4088 return std::make_pair(Reg, RC); 4089 } 4090 4091 if (!R.second) 4092 return std::make_pair(0U, nullptr); 4093 4094 if (Prefix == "$f") { // Parse $f0-$f31. 4095 // If the size of FP registers is 64-bit or Reg is an even number, select 4096 // the 64-bit register class. Otherwise, select the 32-bit register class. 4097 if (VT == MVT::Other) 4098 VT = (Subtarget.isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32; 4099 4100 RC = getRegClassFor(VT); 4101 4102 if (RC == &Mips::AFGR64RegClass) { 4103 assert(Reg % 2 == 0); 4104 Reg >>= 1; 4105 } 4106 } else if (Prefix == "$fcc") // Parse $fcc0-$fcc7. 4107 RC = TRI->getRegClass(Mips::FCCRegClassID); 4108 else if (Prefix == "$w") { // Parse $w0-$w31. 4109 RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT); 4110 } else { // Parse $0-$31. 4111 assert(Prefix == "$"); 4112 RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT); 4113 } 4114 4115 assert(Reg < RC->getNumRegs()); 4116 return std::make_pair(*(RC->begin() + Reg), RC); 4117} 4118 4119/// Given a register class constraint, like 'r', if this corresponds directly 4120/// to an LLVM register class, return a register of 0 and the register class 4121/// pointer. 4122std::pair<unsigned, const TargetRegisterClass *> 4123MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 4124 StringRef Constraint, 4125 MVT VT) const { 4126 if (Constraint.size() == 1) { 4127 switch (Constraint[0]) { 4128 case 'd': // Address register. Same as 'r' unless generating MIPS16 code. 4129 case 'y': // Same as 'r'. Exists for compatibility. 4130 case 'r': 4131 if ((VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8 || 4132 VT == MVT::i1) || 4133 (VT == MVT::f32 && Subtarget.useSoftFloat())) { 4134 if (Subtarget.inMips16Mode()) 4135 return std::make_pair(0U, &Mips::CPU16RegsRegClass); 4136 return std::make_pair(0U, &Mips::GPR32RegClass); 4137 } 4138 if ((VT == MVT::i64 || (VT == MVT::f64 && Subtarget.useSoftFloat())) && 4139 !Subtarget.isGP64bit()) 4140 return std::make_pair(0U, &Mips::GPR32RegClass); 4141 if ((VT == MVT::i64 || (VT == MVT::f64 && Subtarget.useSoftFloat())) && 4142 Subtarget.isGP64bit()) 4143 return std::make_pair(0U, &Mips::GPR64RegClass); 4144 // This will generate an error message 4145 return std::make_pair(0U, nullptr); 4146 case 'f': // FPU or MSA register 4147 if (VT == MVT::v16i8) 4148 return std::make_pair(0U, &Mips::MSA128BRegClass); 4149 else if (VT == MVT::v8i16 || VT == MVT::v8f16) 4150 return std::make_pair(0U, &Mips::MSA128HRegClass); 4151 else if (VT == MVT::v4i32 || VT == MVT::v4f32) 4152 return std::make_pair(0U, &Mips::MSA128WRegClass); 4153 else if (VT == MVT::v2i64 || VT == MVT::v2f64) 4154 return std::make_pair(0U, &Mips::MSA128DRegClass); 4155 else if (VT == MVT::f32) 4156 return std::make_pair(0U, &Mips::FGR32RegClass); 4157 else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) { 4158 if (Subtarget.isFP64bit()) 4159 return std::make_pair(0U, &Mips::FGR64RegClass); 4160 return std::make_pair(0U, &Mips::AFGR64RegClass); 4161 } 4162 break; 4163 case 'c': // register suitable for indirect jump 4164 if (VT == MVT::i32) 4165 return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass); 4166 if (VT == MVT::i64) 4167 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass); 4168 // This will generate an error message 4169 return std::make_pair(0U, nullptr); 4170 case 'l': // use the `lo` register to store values 4171 // that are no bigger than a word 4172 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) 4173 return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass); 4174 return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass); 4175 case 'x': // use the concatenated `hi` and `lo` registers 4176 // to store doubleword values 4177 // Fixme: Not triggering the use of both hi and low 4178 // This will generate an error message 4179 return std::make_pair(0U, nullptr); 4180 } 4181 } 4182 4183 if (!Constraint.empty()) { 4184 std::pair<unsigned, const TargetRegisterClass *> R; 4185 R = parseRegForInlineAsmConstraint(Constraint, VT); 4186 4187 if (R.second) 4188 return R; 4189 } 4190 4191 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); 4192} 4193 4194/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 4195/// vector. If it is invalid, don't add anything to Ops. 4196void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 4197 StringRef Constraint, 4198 std::vector<SDValue> &Ops, 4199 SelectionDAG &DAG) const { 4200 SDLoc DL(Op); 4201 SDValue Result; 4202 4203 // Only support length 1 constraints for now. 4204 if (Constraint.size() > 1) 4205 return; 4206 4207 char ConstraintLetter = Constraint[0]; 4208 switch (ConstraintLetter) { 4209 default: break; // This will fall through to the generic implementation 4210 case 'I': // Signed 16 bit constant 4211 // If this fails, the parent routine will give an error 4212 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 4213 EVT Type = Op.getValueType(); 4214 int64_t Val = C->getSExtValue(); 4215 if (isInt<16>(Val)) { 4216 Result = DAG.getTargetConstant(Val, DL, Type); 4217 break; 4218 } 4219 } 4220 return; 4221 case 'J': // integer zero 4222 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 4223 EVT Type = Op.getValueType(); 4224 int64_t Val = C->getZExtValue(); 4225 if (Val == 0) { 4226 Result = DAG.getTargetConstant(0, DL, Type); 4227 break; 4228 } 4229 } 4230 return; 4231 case 'K': // unsigned 16 bit immediate 4232 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 4233 EVT Type = Op.getValueType(); 4234 uint64_t Val = (uint64_t)C->getZExtValue(); 4235 if (isUInt<16>(Val)) { 4236 Result = DAG.getTargetConstant(Val, DL, Type); 4237 break; 4238 } 4239 } 4240 return; 4241 case 'L': // signed 32 bit immediate where lower 16 bits are 0 4242 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 4243 EVT Type = Op.getValueType(); 4244 int64_t Val = C->getSExtValue(); 4245 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){ 4246 Result = DAG.getTargetConstant(Val, DL, Type); 4247 break; 4248 } 4249 } 4250 return; 4251 case 'N': // immediate in the range of -65535 to -1 (inclusive) 4252 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 4253 EVT Type = Op.getValueType(); 4254 int64_t Val = C->getSExtValue(); 4255 if ((Val >= -65535) && (Val <= -1)) { 4256 Result = DAG.getTargetConstant(Val, DL, Type); 4257 break; 4258 } 4259 } 4260 return; 4261 case 'O': // signed 15 bit immediate 4262 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 4263 EVT Type = Op.getValueType(); 4264 int64_t Val = C->getSExtValue(); 4265 if ((isInt<15>(Val))) { 4266 Result = DAG.getTargetConstant(Val, DL, Type); 4267 break; 4268 } 4269 } 4270 return; 4271 case 'P': // immediate in the range of 1 to 65535 (inclusive) 4272 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 4273 EVT Type = Op.getValueType(); 4274 int64_t Val = C->getSExtValue(); 4275 if ((Val <= 65535) && (Val >= 1)) { 4276 Result = DAG.getTargetConstant(Val, DL, Type); 4277 break; 4278 } 4279 } 4280 return; 4281 } 4282 4283 if (Result.getNode()) { 4284 Ops.push_back(Result); 4285 return; 4286 } 4287 4288 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 4289} 4290 4291bool MipsTargetLowering::isLegalAddressingMode(const DataLayout &DL, 4292 const AddrMode &AM, Type *Ty, 4293 unsigned AS, 4294 Instruction *I) const { 4295 // No global is ever allowed as a base. 4296 if (AM.BaseGV) 4297 return false; 4298 4299 switch (AM.Scale) { 4300 case 0: // "r+i" or just "i", depending on HasBaseReg. 4301 break; 4302 case 1: 4303 if (!AM.HasBaseReg) // allow "r+i". 4304 break; 4305 return false; // disallow "r+r" or "r+r+i". 4306 default: 4307 return false; 4308 } 4309 4310 return true; 4311} 4312 4313bool 4314MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 4315 // The Mips target isn't yet aware of offsets. 4316 return false; 4317} 4318 4319EVT MipsTargetLowering::getOptimalMemOpType( 4320 const MemOp &Op, const AttributeList &FuncAttributes) const { 4321 if (Subtarget.hasMips64()) 4322 return MVT::i64; 4323 4324 return MVT::i32; 4325} 4326 4327bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT, 4328 bool ForCodeSize) const { 4329 if (VT != MVT::f32 && VT != MVT::f64) 4330 return false; 4331 if (Imm.isNegZero()) 4332 return false; 4333 return Imm.isZero(); 4334} 4335 4336unsigned MipsTargetLowering::getJumpTableEncoding() const { 4337 4338 // FIXME: For space reasons this should be: EK_GPRel32BlockAddress. 4339 if (ABI.IsN64() && isPositionIndependent()) 4340 return MachineJumpTableInfo::EK_GPRel64BlockAddress; 4341 4342 return TargetLowering::getJumpTableEncoding(); 4343} 4344 4345bool MipsTargetLowering::useSoftFloat() const { 4346 return Subtarget.useSoftFloat(); 4347} 4348 4349void MipsTargetLowering::copyByValRegs( 4350 SDValue Chain, const SDLoc &DL, std::vector<SDValue> &OutChains, 4351 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags, 4352 SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg, 4353 unsigned FirstReg, unsigned LastReg, const CCValAssign &VA, 4354 MipsCCState &State) const { 4355 MachineFunction &MF = DAG.getMachineFunction(); 4356 MachineFrameInfo &MFI = MF.getFrameInfo(); 4357 unsigned GPRSizeInBytes = Subtarget.getGPRSizeInBytes(); 4358 unsigned NumRegs = LastReg - FirstReg; 4359 unsigned RegAreaSize = NumRegs * GPRSizeInBytes; 4360 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize); 4361 int FrameObjOffset; 4362 ArrayRef<MCPhysReg> ByValArgRegs = ABI.GetByValArgRegs(); 4363 4364 if (RegAreaSize) 4365 FrameObjOffset = 4366 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) - 4367 (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes); 4368 else 4369 FrameObjOffset = VA.getLocMemOffset(); 4370 4371 // Create frame object. 4372 EVT PtrTy = getPointerTy(DAG.getDataLayout()); 4373 // Make the fixed object stored to mutable so that the load instructions 4374 // referencing it have their memory dependencies added. 4375 // Set the frame object as isAliased which clears the underlying objects 4376 // vector in ScheduleDAGInstrs::buildSchedGraph() resulting in addition of all 4377 // stores as dependencies for loads referencing this fixed object. 4378 int FI = MFI.CreateFixedObject(FrameObjSize, FrameObjOffset, false, true); 4379 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 4380 InVals.push_back(FIN); 4381 4382 if (!NumRegs) 4383 return; 4384 4385 // Copy arg registers. 4386 MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8); 4387 const TargetRegisterClass *RC = getRegClassFor(RegTy); 4388 4389 for (unsigned I = 0; I < NumRegs; ++I) { 4390 unsigned ArgReg = ByValArgRegs[FirstReg + I]; 4391 unsigned VReg = addLiveIn(MF, ArgReg, RC); 4392 unsigned Offset = I * GPRSizeInBytes; 4393 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN, 4394 DAG.getConstant(Offset, DL, PtrTy)); 4395 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy), 4396 StorePtr, MachinePointerInfo(FuncArg, Offset)); 4397 OutChains.push_back(Store); 4398 } 4399} 4400 4401// Copy byVal arg to registers and stack. 4402void MipsTargetLowering::passByValArg( 4403 SDValue Chain, const SDLoc &DL, 4404 std::deque<std::pair<unsigned, SDValue>> &RegsToPass, 4405 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr, 4406 MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg, 4407 unsigned LastReg, const ISD::ArgFlagsTy &Flags, bool isLittle, 4408 const CCValAssign &VA) const { 4409 unsigned ByValSizeInBytes = Flags.getByValSize(); 4410 unsigned OffsetInBytes = 0; // From beginning of struct 4411 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 4412 Align Alignment = 4413 std::min(Flags.getNonZeroByValAlign(), Align(RegSizeInBytes)); 4414 EVT PtrTy = getPointerTy(DAG.getDataLayout()), 4415 RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); 4416 unsigned NumRegs = LastReg - FirstReg; 4417 4418 if (NumRegs) { 4419 ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs(); 4420 bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes); 4421 unsigned I = 0; 4422 4423 // Copy words to registers. 4424 for (; I < NumRegs - LeftoverBytes; ++I, OffsetInBytes += RegSizeInBytes) { 4425 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 4426 DAG.getConstant(OffsetInBytes, DL, PtrTy)); 4427 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr, 4428 MachinePointerInfo(), Alignment); 4429 MemOpChains.push_back(LoadVal.getValue(1)); 4430 unsigned ArgReg = ArgRegs[FirstReg + I]; 4431 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal)); 4432 } 4433 4434 // Return if the struct has been fully copied. 4435 if (ByValSizeInBytes == OffsetInBytes) 4436 return; 4437 4438 // Copy the remainder of the byval argument with sub-word loads and shifts. 4439 if (LeftoverBytes) { 4440 SDValue Val; 4441 4442 for (unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0; 4443 OffsetInBytes < ByValSizeInBytes; LoadSizeInBytes /= 2) { 4444 unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes; 4445 4446 if (RemainingSizeInBytes < LoadSizeInBytes) 4447 continue; 4448 4449 // Load subword. 4450 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 4451 DAG.getConstant(OffsetInBytes, DL, 4452 PtrTy)); 4453 SDValue LoadVal = DAG.getExtLoad( 4454 ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(), 4455 MVT::getIntegerVT(LoadSizeInBytes * 8), Alignment); 4456 MemOpChains.push_back(LoadVal.getValue(1)); 4457 4458 // Shift the loaded value. 4459 unsigned Shamt; 4460 4461 if (isLittle) 4462 Shamt = TotalBytesLoaded * 8; 4463 else 4464 Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8; 4465 4466 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal, 4467 DAG.getConstant(Shamt, DL, MVT::i32)); 4468 4469 if (Val.getNode()) 4470 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift); 4471 else 4472 Val = Shift; 4473 4474 OffsetInBytes += LoadSizeInBytes; 4475 TotalBytesLoaded += LoadSizeInBytes; 4476 Alignment = std::min(Alignment, Align(LoadSizeInBytes)); 4477 } 4478 4479 unsigned ArgReg = ArgRegs[FirstReg + I]; 4480 RegsToPass.push_back(std::make_pair(ArgReg, Val)); 4481 return; 4482 } 4483 } 4484 4485 // Copy remainder of byval arg to it with memcpy. 4486 unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes; 4487 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 4488 DAG.getConstant(OffsetInBytes, DL, PtrTy)); 4489 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr, 4490 DAG.getIntPtrConstant(VA.getLocMemOffset(), DL)); 4491 Chain = DAG.getMemcpy( 4492 Chain, DL, Dst, Src, DAG.getConstant(MemCpySize, DL, PtrTy), 4493 Align(Alignment), /*isVolatile=*/false, /*AlwaysInline=*/false, 4494 /*isTailCall=*/false, MachinePointerInfo(), MachinePointerInfo()); 4495 MemOpChains.push_back(Chain); 4496} 4497 4498void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains, 4499 SDValue Chain, const SDLoc &DL, 4500 SelectionDAG &DAG, 4501 CCState &State) const { 4502 ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs(); 4503 unsigned Idx = State.getFirstUnallocated(ArgRegs); 4504 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 4505 MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); 4506 const TargetRegisterClass *RC = getRegClassFor(RegTy); 4507 MachineFunction &MF = DAG.getMachineFunction(); 4508 MachineFrameInfo &MFI = MF.getFrameInfo(); 4509 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 4510 4511 // Offset of the first variable argument from stack pointer. 4512 int VaArgOffset; 4513 4514 if (ArgRegs.size() == Idx) 4515 VaArgOffset = alignTo(State.getStackSize(), RegSizeInBytes); 4516 else { 4517 VaArgOffset = 4518 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) - 4519 (int)(RegSizeInBytes * (ArgRegs.size() - Idx)); 4520 } 4521 4522 // Record the frame index of the first variable argument 4523 // which is a value necessary to VASTART. 4524 int FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true); 4525 MipsFI->setVarArgsFrameIndex(FI); 4526 4527 // Copy the integer registers that have not been used for argument passing 4528 // to the argument register save area. For O32, the save area is allocated 4529 // in the caller's stack frame, while for N32/64, it is allocated in the 4530 // callee's stack frame. 4531 for (unsigned I = Idx; I < ArgRegs.size(); 4532 ++I, VaArgOffset += RegSizeInBytes) { 4533 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC); 4534 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy); 4535 FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true); 4536 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 4537 SDValue Store = 4538 DAG.getStore(Chain, DL, ArgValue, PtrOff, MachinePointerInfo()); 4539 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue( 4540 (Value *)nullptr); 4541 OutChains.push_back(Store); 4542 } 4543} 4544 4545void MipsTargetLowering::HandleByVal(CCState *State, unsigned &Size, 4546 Align Alignment) const { 4547 const TargetFrameLowering *TFL = Subtarget.getFrameLowering(); 4548 4549 assert(Size && "Byval argument's size shouldn't be 0."); 4550 4551 Alignment = std::min(Alignment, TFL->getStackAlign()); 4552 4553 unsigned FirstReg = 0; 4554 unsigned NumRegs = 0; 4555 4556 if (State->getCallingConv() != CallingConv::Fast) { 4557 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 4558 ArrayRef<MCPhysReg> IntArgRegs = ABI.GetByValArgRegs(); 4559 // FIXME: The O32 case actually describes no shadow registers. 4560 const MCPhysReg *ShadowRegs = 4561 ABI.IsO32() ? IntArgRegs.data() : Mips64DPRegs; 4562 4563 // We used to check the size as well but we can't do that anymore since 4564 // CCState::HandleByVal() rounds up the size after calling this function. 4565 assert( 4566 Alignment >= Align(RegSizeInBytes) && 4567 "Byval argument's alignment should be a multiple of RegSizeInBytes."); 4568 4569 FirstReg = State->getFirstUnallocated(IntArgRegs); 4570 4571 // If Alignment > RegSizeInBytes, the first arg register must be even. 4572 // FIXME: This condition happens to do the right thing but it's not the 4573 // right way to test it. We want to check that the stack frame offset 4574 // of the register is aligned. 4575 if ((Alignment > RegSizeInBytes) && (FirstReg % 2)) { 4576 State->AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]); 4577 ++FirstReg; 4578 } 4579 4580 // Mark the registers allocated. 4581 Size = alignTo(Size, RegSizeInBytes); 4582 for (unsigned I = FirstReg; Size > 0 && (I < IntArgRegs.size()); 4583 Size -= RegSizeInBytes, ++I, ++NumRegs) 4584 State->AllocateReg(IntArgRegs[I], ShadowRegs[I]); 4585 } 4586 4587 State->addInRegsParamInfo(FirstReg, FirstReg + NumRegs); 4588} 4589 4590MachineBasicBlock *MipsTargetLowering::emitPseudoSELECT(MachineInstr &MI, 4591 MachineBasicBlock *BB, 4592 bool isFPCmp, 4593 unsigned Opc) const { 4594 assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) && 4595 "Subtarget already supports SELECT nodes with the use of" 4596 "conditional-move instructions."); 4597 4598 const TargetInstrInfo *TII = 4599 Subtarget.getInstrInfo(); 4600 DebugLoc DL = MI.getDebugLoc(); 4601 4602 // To "insert" a SELECT instruction, we actually have to insert the 4603 // diamond control-flow pattern. The incoming instruction knows the 4604 // destination vreg to set, the condition code register to branch on, the 4605 // true/false values to select between, and a branch opcode to use. 4606 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 4607 MachineFunction::iterator It = ++BB->getIterator(); 4608 4609 // thisMBB: 4610 // ... 4611 // TrueVal = ... 4612 // setcc r1, r2, r3 4613 // bNE r1, r0, copy1MBB 4614 // fallthrough --> copy0MBB 4615 MachineBasicBlock *thisMBB = BB; 4616 MachineFunction *F = BB->getParent(); 4617 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 4618 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 4619 F->insert(It, copy0MBB); 4620 F->insert(It, sinkMBB); 4621 4622 // Transfer the remainder of BB and its successor edges to sinkMBB. 4623 sinkMBB->splice(sinkMBB->begin(), BB, 4624 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 4625 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 4626 4627 // Next, add the true and fallthrough blocks as its successors. 4628 BB->addSuccessor(copy0MBB); 4629 BB->addSuccessor(sinkMBB); 4630 4631 if (isFPCmp) { 4632 // bc1[tf] cc, sinkMBB 4633 BuildMI(BB, DL, TII->get(Opc)) 4634 .addReg(MI.getOperand(1).getReg()) 4635 .addMBB(sinkMBB); 4636 } else { 4637 // bne rs, $0, sinkMBB 4638 BuildMI(BB, DL, TII->get(Opc)) 4639 .addReg(MI.getOperand(1).getReg()) 4640 .addReg(Mips::ZERO) 4641 .addMBB(sinkMBB); 4642 } 4643 4644 // copy0MBB: 4645 // %FalseValue = ... 4646 // # fallthrough to sinkMBB 4647 BB = copy0MBB; 4648 4649 // Update machine-CFG edges 4650 BB->addSuccessor(sinkMBB); 4651 4652 // sinkMBB: 4653 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 4654 // ... 4655 BB = sinkMBB; 4656 4657 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg()) 4658 .addReg(MI.getOperand(2).getReg()) 4659 .addMBB(thisMBB) 4660 .addReg(MI.getOperand(3).getReg()) 4661 .addMBB(copy0MBB); 4662 4663 MI.eraseFromParent(); // The pseudo instruction is gone now. 4664 4665 return BB; 4666} 4667 4668MachineBasicBlock * 4669MipsTargetLowering::emitPseudoD_SELECT(MachineInstr &MI, 4670 MachineBasicBlock *BB) const { 4671 assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) && 4672 "Subtarget already supports SELECT nodes with the use of" 4673 "conditional-move instructions."); 4674 4675 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 4676 DebugLoc DL = MI.getDebugLoc(); 4677 4678 // D_SELECT substitutes two SELECT nodes that goes one after another and 4679 // have the same condition operand. On machines which don't have 4680 // conditional-move instruction, it reduces unnecessary branch instructions 4681 // which are result of using two diamond patterns that are result of two 4682 // SELECT pseudo instructions. 4683 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 4684 MachineFunction::iterator It = ++BB->getIterator(); 4685 4686 // thisMBB: 4687 // ... 4688 // TrueVal = ... 4689 // setcc r1, r2, r3 4690 // bNE r1, r0, copy1MBB 4691 // fallthrough --> copy0MBB 4692 MachineBasicBlock *thisMBB = BB; 4693 MachineFunction *F = BB->getParent(); 4694 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 4695 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 4696 F->insert(It, copy0MBB); 4697 F->insert(It, sinkMBB); 4698 4699 // Transfer the remainder of BB and its successor edges to sinkMBB. 4700 sinkMBB->splice(sinkMBB->begin(), BB, 4701 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 4702 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 4703 4704 // Next, add the true and fallthrough blocks as its successors. 4705 BB->addSuccessor(copy0MBB); 4706 BB->addSuccessor(sinkMBB); 4707 4708 // bne rs, $0, sinkMBB 4709 BuildMI(BB, DL, TII->get(Mips::BNE)) 4710 .addReg(MI.getOperand(2).getReg()) 4711 .addReg(Mips::ZERO) 4712 .addMBB(sinkMBB); 4713 4714 // copy0MBB: 4715 // %FalseValue = ... 4716 // # fallthrough to sinkMBB 4717 BB = copy0MBB; 4718 4719 // Update machine-CFG edges 4720 BB->addSuccessor(sinkMBB); 4721 4722 // sinkMBB: 4723 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 4724 // ... 4725 BB = sinkMBB; 4726 4727 // Use two PHI nodes to select two reults 4728 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg()) 4729 .addReg(MI.getOperand(3).getReg()) 4730 .addMBB(thisMBB) 4731 .addReg(MI.getOperand(5).getReg()) 4732 .addMBB(copy0MBB); 4733 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(1).getReg()) 4734 .addReg(MI.getOperand(4).getReg()) 4735 .addMBB(thisMBB) 4736 .addReg(MI.getOperand(6).getReg()) 4737 .addMBB(copy0MBB); 4738 4739 MI.eraseFromParent(); // The pseudo instruction is gone now. 4740 4741 return BB; 4742} 4743 4744// FIXME? Maybe this could be a TableGen attribute on some registers and 4745// this table could be generated automatically from RegInfo. 4746Register 4747MipsTargetLowering::getRegisterByName(const char *RegName, LLT VT, 4748 const MachineFunction &MF) const { 4749 // The Linux kernel uses $28 and sp. 4750 if (Subtarget.isGP64bit()) { 4751 Register Reg = StringSwitch<Register>(RegName) 4752 .Case("$28", Mips::GP_64) 4753 .Case("sp", Mips::SP_64) 4754 .Default(Register()); 4755 if (Reg) 4756 return Reg; 4757 } else { 4758 Register Reg = StringSwitch<Register>(RegName) 4759 .Case("$28", Mips::GP) 4760 .Case("sp", Mips::SP) 4761 .Default(Register()); 4762 if (Reg) 4763 return Reg; 4764 } 4765 report_fatal_error("Invalid register name global variable"); 4766} 4767 4768MachineBasicBlock *MipsTargetLowering::emitLDR_W(MachineInstr &MI, 4769 MachineBasicBlock *BB) const { 4770 MachineFunction *MF = BB->getParent(); 4771 MachineRegisterInfo &MRI = MF->getRegInfo(); 4772 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 4773 const bool IsLittle = Subtarget.isLittle(); 4774 DebugLoc DL = MI.getDebugLoc(); 4775 4776 Register Dest = MI.getOperand(0).getReg(); 4777 Register Address = MI.getOperand(1).getReg(); 4778 unsigned Imm = MI.getOperand(2).getImm(); 4779 4780 MachineBasicBlock::iterator I(MI); 4781 4782 if (Subtarget.hasMips32r6() || Subtarget.hasMips64r6()) { 4783 // Mips release 6 can load from adress that is not naturally-aligned. 4784 Register Temp = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4785 BuildMI(*BB, I, DL, TII->get(Mips::LW)) 4786 .addDef(Temp) 4787 .addUse(Address) 4788 .addImm(Imm); 4789 BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Dest).addUse(Temp); 4790 } else { 4791 // Mips release 5 needs to use instructions that can load from an unaligned 4792 // memory address. 4793 Register LoadHalf = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4794 Register LoadFull = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4795 Register Undef = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4796 BuildMI(*BB, I, DL, TII->get(Mips::IMPLICIT_DEF)).addDef(Undef); 4797 BuildMI(*BB, I, DL, TII->get(Mips::LWR)) 4798 .addDef(LoadHalf) 4799 .addUse(Address) 4800 .addImm(Imm + (IsLittle ? 0 : 3)) 4801 .addUse(Undef); 4802 BuildMI(*BB, I, DL, TII->get(Mips::LWL)) 4803 .addDef(LoadFull) 4804 .addUse(Address) 4805 .addImm(Imm + (IsLittle ? 3 : 0)) 4806 .addUse(LoadHalf); 4807 BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Dest).addUse(LoadFull); 4808 } 4809 4810 MI.eraseFromParent(); 4811 return BB; 4812} 4813 4814MachineBasicBlock *MipsTargetLowering::emitLDR_D(MachineInstr &MI, 4815 MachineBasicBlock *BB) const { 4816 MachineFunction *MF = BB->getParent(); 4817 MachineRegisterInfo &MRI = MF->getRegInfo(); 4818 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 4819 const bool IsLittle = Subtarget.isLittle(); 4820 DebugLoc DL = MI.getDebugLoc(); 4821 4822 Register Dest = MI.getOperand(0).getReg(); 4823 Register Address = MI.getOperand(1).getReg(); 4824 unsigned Imm = MI.getOperand(2).getImm(); 4825 4826 MachineBasicBlock::iterator I(MI); 4827 4828 if (Subtarget.hasMips32r6() || Subtarget.hasMips64r6()) { 4829 // Mips release 6 can load from adress that is not naturally-aligned. 4830 if (Subtarget.isGP64bit()) { 4831 Register Temp = MRI.createVirtualRegister(&Mips::GPR64RegClass); 4832 BuildMI(*BB, I, DL, TII->get(Mips::LD)) 4833 .addDef(Temp) 4834 .addUse(Address) 4835 .addImm(Imm); 4836 BuildMI(*BB, I, DL, TII->get(Mips::FILL_D)).addDef(Dest).addUse(Temp); 4837 } else { 4838 Register Wtemp = MRI.createVirtualRegister(&Mips::MSA128WRegClass); 4839 Register Lo = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4840 Register Hi = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4841 BuildMI(*BB, I, DL, TII->get(Mips::LW)) 4842 .addDef(Lo) 4843 .addUse(Address) 4844 .addImm(Imm + (IsLittle ? 0 : 4)); 4845 BuildMI(*BB, I, DL, TII->get(Mips::LW)) 4846 .addDef(Hi) 4847 .addUse(Address) 4848 .addImm(Imm + (IsLittle ? 4 : 0)); 4849 BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Wtemp).addUse(Lo); 4850 BuildMI(*BB, I, DL, TII->get(Mips::INSERT_W), Dest) 4851 .addUse(Wtemp) 4852 .addUse(Hi) 4853 .addImm(1); 4854 } 4855 } else { 4856 // Mips release 5 needs to use instructions that can load from an unaligned 4857 // memory address. 4858 Register LoHalf = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4859 Register LoFull = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4860 Register LoUndef = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4861 Register HiHalf = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4862 Register HiFull = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4863 Register HiUndef = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4864 Register Wtemp = MRI.createVirtualRegister(&Mips::MSA128WRegClass); 4865 BuildMI(*BB, I, DL, TII->get(Mips::IMPLICIT_DEF)).addDef(LoUndef); 4866 BuildMI(*BB, I, DL, TII->get(Mips::LWR)) 4867 .addDef(LoHalf) 4868 .addUse(Address) 4869 .addImm(Imm + (IsLittle ? 0 : 7)) 4870 .addUse(LoUndef); 4871 BuildMI(*BB, I, DL, TII->get(Mips::LWL)) 4872 .addDef(LoFull) 4873 .addUse(Address) 4874 .addImm(Imm + (IsLittle ? 3 : 4)) 4875 .addUse(LoHalf); 4876 BuildMI(*BB, I, DL, TII->get(Mips::IMPLICIT_DEF)).addDef(HiUndef); 4877 BuildMI(*BB, I, DL, TII->get(Mips::LWR)) 4878 .addDef(HiHalf) 4879 .addUse(Address) 4880 .addImm(Imm + (IsLittle ? 4 : 3)) 4881 .addUse(HiUndef); 4882 BuildMI(*BB, I, DL, TII->get(Mips::LWL)) 4883 .addDef(HiFull) 4884 .addUse(Address) 4885 .addImm(Imm + (IsLittle ? 7 : 0)) 4886 .addUse(HiHalf); 4887 BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Wtemp).addUse(LoFull); 4888 BuildMI(*BB, I, DL, TII->get(Mips::INSERT_W), Dest) 4889 .addUse(Wtemp) 4890 .addUse(HiFull) 4891 .addImm(1); 4892 } 4893 4894 MI.eraseFromParent(); 4895 return BB; 4896} 4897 4898MachineBasicBlock *MipsTargetLowering::emitSTR_W(MachineInstr &MI, 4899 MachineBasicBlock *BB) const { 4900 MachineFunction *MF = BB->getParent(); 4901 MachineRegisterInfo &MRI = MF->getRegInfo(); 4902 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 4903 const bool IsLittle = Subtarget.isLittle(); 4904 DebugLoc DL = MI.getDebugLoc(); 4905 4906 Register StoreVal = MI.getOperand(0).getReg(); 4907 Register Address = MI.getOperand(1).getReg(); 4908 unsigned Imm = MI.getOperand(2).getImm(); 4909 4910 MachineBasicBlock::iterator I(MI); 4911 4912 if (Subtarget.hasMips32r6() || Subtarget.hasMips64r6()) { 4913 // Mips release 6 can store to adress that is not naturally-aligned. 4914 Register BitcastW = MRI.createVirtualRegister(&Mips::MSA128WRegClass); 4915 Register Tmp = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4916 BuildMI(*BB, I, DL, TII->get(Mips::COPY)).addDef(BitcastW).addUse(StoreVal); 4917 BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_W)) 4918 .addDef(Tmp) 4919 .addUse(BitcastW) 4920 .addImm(0); 4921 BuildMI(*BB, I, DL, TII->get(Mips::SW)) 4922 .addUse(Tmp) 4923 .addUse(Address) 4924 .addImm(Imm); 4925 } else { 4926 // Mips release 5 needs to use instructions that can store to an unaligned 4927 // memory address. 4928 Register Tmp = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4929 BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_W)) 4930 .addDef(Tmp) 4931 .addUse(StoreVal) 4932 .addImm(0); 4933 BuildMI(*BB, I, DL, TII->get(Mips::SWR)) 4934 .addUse(Tmp) 4935 .addUse(Address) 4936 .addImm(Imm + (IsLittle ? 0 : 3)); 4937 BuildMI(*BB, I, DL, TII->get(Mips::SWL)) 4938 .addUse(Tmp) 4939 .addUse(Address) 4940 .addImm(Imm + (IsLittle ? 3 : 0)); 4941 } 4942 4943 MI.eraseFromParent(); 4944 4945 return BB; 4946} 4947 4948MachineBasicBlock *MipsTargetLowering::emitSTR_D(MachineInstr &MI, 4949 MachineBasicBlock *BB) const { 4950 MachineFunction *MF = BB->getParent(); 4951 MachineRegisterInfo &MRI = MF->getRegInfo(); 4952 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 4953 const bool IsLittle = Subtarget.isLittle(); 4954 DebugLoc DL = MI.getDebugLoc(); 4955 4956 Register StoreVal = MI.getOperand(0).getReg(); 4957 Register Address = MI.getOperand(1).getReg(); 4958 unsigned Imm = MI.getOperand(2).getImm(); 4959 4960 MachineBasicBlock::iterator I(MI); 4961 4962 if (Subtarget.hasMips32r6() || Subtarget.hasMips64r6()) { 4963 // Mips release 6 can store to adress that is not naturally-aligned. 4964 if (Subtarget.isGP64bit()) { 4965 Register BitcastD = MRI.createVirtualRegister(&Mips::MSA128DRegClass); 4966 Register Lo = MRI.createVirtualRegister(&Mips::GPR64RegClass); 4967 BuildMI(*BB, I, DL, TII->get(Mips::COPY)) 4968 .addDef(BitcastD) 4969 .addUse(StoreVal); 4970 BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_D)) 4971 .addDef(Lo) 4972 .addUse(BitcastD) 4973 .addImm(0); 4974 BuildMI(*BB, I, DL, TII->get(Mips::SD)) 4975 .addUse(Lo) 4976 .addUse(Address) 4977 .addImm(Imm); 4978 } else { 4979 Register BitcastW = MRI.createVirtualRegister(&Mips::MSA128WRegClass); 4980 Register Lo = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4981 Register Hi = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4982 BuildMI(*BB, I, DL, TII->get(Mips::COPY)) 4983 .addDef(BitcastW) 4984 .addUse(StoreVal); 4985 BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_W)) 4986 .addDef(Lo) 4987 .addUse(BitcastW) 4988 .addImm(0); 4989 BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_W)) 4990 .addDef(Hi) 4991 .addUse(BitcastW) 4992 .addImm(1); 4993 BuildMI(*BB, I, DL, TII->get(Mips::SW)) 4994 .addUse(Lo) 4995 .addUse(Address) 4996 .addImm(Imm + (IsLittle ? 0 : 4)); 4997 BuildMI(*BB, I, DL, TII->get(Mips::SW)) 4998 .addUse(Hi) 4999 .addUse(Address) 5000 .addImm(Imm + (IsLittle ? 4 : 0)); 5001 } 5002 } else { 5003 // Mips release 5 needs to use instructions that can store to an unaligned 5004 // memory address. 5005 Register Bitcast = MRI.createVirtualRegister(&Mips::MSA128WRegClass); 5006 Register Lo = MRI.createVirtualRegister(&Mips::GPR32RegClass); 5007 Register Hi = MRI.createVirtualRegister(&Mips::GPR32RegClass); 5008 BuildMI(*BB, I, DL, TII->get(Mips::COPY)).addDef(Bitcast).addUse(StoreVal); 5009 BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_W)) 5010 .addDef(Lo) 5011 .addUse(Bitcast) 5012 .addImm(0); 5013 BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_W)) 5014 .addDef(Hi) 5015 .addUse(Bitcast) 5016 .addImm(1); 5017 BuildMI(*BB, I, DL, TII->get(Mips::SWR)) 5018 .addUse(Lo) 5019 .addUse(Address) 5020 .addImm(Imm + (IsLittle ? 0 : 3)); 5021 BuildMI(*BB, I, DL, TII->get(Mips::SWL)) 5022 .addUse(Lo) 5023 .addUse(Address) 5024 .addImm(Imm + (IsLittle ? 3 : 0)); 5025 BuildMI(*BB, I, DL, TII->get(Mips::SWR)) 5026 .addUse(Hi) 5027 .addUse(Address) 5028 .addImm(Imm + (IsLittle ? 4 : 7)); 5029 BuildMI(*BB, I, DL, TII->get(Mips::SWL)) 5030 .addUse(Hi) 5031 .addUse(Address) 5032 .addImm(Imm + (IsLittle ? 7 : 4)); 5033 } 5034 5035 MI.eraseFromParent(); 5036 return BB; 5037} 5038