1/****************************************************************************** 2 SPDX-License-Identifier: BSD-3-Clause 3 4 Copyright (c) 2001-2015, Intel Corporation 5 All rights reserved. 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of the Intel Corporation nor the names of its 18 contributors may be used to endorse or promote products derived from 19 this software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33******************************************************************************/ 34/*$FreeBSD$*/ 35 36#ifndef _E1000_HW_H_ 37#define _E1000_HW_H_ 38 39#include "e1000_osdep.h" 40#include "e1000_regs.h" 41#include "e1000_defines.h" 42 43struct e1000_hw; 44 45#define E1000_DEV_ID_82542 0x1000 46#define E1000_DEV_ID_82543GC_FIBER 0x1001 47#define E1000_DEV_ID_82543GC_COPPER 0x1004 48#define E1000_DEV_ID_82544EI_COPPER 0x1008 49#define E1000_DEV_ID_82544EI_FIBER 0x1009 50#define E1000_DEV_ID_82544GC_COPPER 0x100C 51#define E1000_DEV_ID_82544GC_LOM 0x100D 52#define E1000_DEV_ID_82540EM 0x100E 53#define E1000_DEV_ID_82540EM_LOM 0x1015 54#define E1000_DEV_ID_82540EP_LOM 0x1016 55#define E1000_DEV_ID_82540EP 0x1017 56#define E1000_DEV_ID_82540EP_LP 0x101E 57#define E1000_DEV_ID_82545EM_COPPER 0x100F 58#define E1000_DEV_ID_82545EM_FIBER 0x1011 59#define E1000_DEV_ID_82545GM_COPPER 0x1026 60#define E1000_DEV_ID_82545GM_FIBER 0x1027 61#define E1000_DEV_ID_82545GM_SERDES 0x1028 62#define E1000_DEV_ID_82546EB_COPPER 0x1010 63#define E1000_DEV_ID_82546EB_FIBER 0x1012 64#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D 65#define E1000_DEV_ID_82546GB_COPPER 0x1079 66#define E1000_DEV_ID_82546GB_FIBER 0x107A 67#define E1000_DEV_ID_82546GB_SERDES 0x107B 68#define E1000_DEV_ID_82546GB_PCIE 0x108A 69#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 70#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 71#define E1000_DEV_ID_82541EI 0x1013 72#define E1000_DEV_ID_82541EI_MOBILE 0x1018 73#define E1000_DEV_ID_82541ER_LOM 0x1014 74#define E1000_DEV_ID_82541ER 0x1078 75#define E1000_DEV_ID_82541GI 0x1076 76#define E1000_DEV_ID_82541GI_LF 0x107C 77#define E1000_DEV_ID_82541GI_MOBILE 0x1077 78#define E1000_DEV_ID_82547EI 0x1019 79#define E1000_DEV_ID_82547EI_MOBILE 0x101A 80#define E1000_DEV_ID_82547GI 0x1075 81#define E1000_DEV_ID_82571EB_COPPER 0x105E 82#define E1000_DEV_ID_82571EB_FIBER 0x105F 83#define E1000_DEV_ID_82571EB_SERDES 0x1060 84#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 85#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA 86#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 87#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 88#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 89#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC 90#define E1000_DEV_ID_82572EI_COPPER 0x107D 91#define E1000_DEV_ID_82572EI_FIBER 0x107E 92#define E1000_DEV_ID_82572EI_SERDES 0x107F 93#define E1000_DEV_ID_82572EI 0x10B9 94#define E1000_DEV_ID_82573E 0x108B 95#define E1000_DEV_ID_82573E_IAMT 0x108C 96#define E1000_DEV_ID_82573L 0x109A 97#define E1000_DEV_ID_82574L 0x10D3 98#define E1000_DEV_ID_82574LA 0x10F6 99#define E1000_DEV_ID_82583V 0x150C 100#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 101#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 102#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA 103#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB 104#define E1000_DEV_ID_ICH8_82567V_3 0x1501 105#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 106#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 107#define E1000_DEV_ID_ICH8_IGP_C 0x104B 108#define E1000_DEV_ID_ICH8_IFE 0x104C 109#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 110#define E1000_DEV_ID_ICH8_IFE_G 0x10C5 111#define E1000_DEV_ID_ICH8_IGP_M 0x104D 112#define E1000_DEV_ID_ICH9_IGP_M 0x10BF 113#define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 114#define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB 115#define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD 116#define E1000_DEV_ID_ICH9_BM 0x10E5 117#define E1000_DEV_ID_ICH9_IGP_C 0x294C 118#define E1000_DEV_ID_ICH9_IFE 0x10C0 119#define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 120#define E1000_DEV_ID_ICH9_IFE_G 0x10C2 121#define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC 122#define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD 123#define E1000_DEV_ID_ICH10_R_BM_V 0x10CE 124#define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE 125#define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF 126#define E1000_DEV_ID_ICH10_D_BM_V 0x1525 127#define E1000_DEV_ID_PCH_M_HV_LM 0x10EA 128#define E1000_DEV_ID_PCH_M_HV_LC 0x10EB 129#define E1000_DEV_ID_PCH_D_HV_DM 0x10EF 130#define E1000_DEV_ID_PCH_D_HV_DC 0x10F0 131#define E1000_DEV_ID_PCH2_LV_LM 0x1502 132#define E1000_DEV_ID_PCH2_LV_V 0x1503 133#define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A 134#define E1000_DEV_ID_PCH_LPT_I217_V 0x153B 135#define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A 136#define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559 137#define E1000_DEV_ID_PCH_I218_LM2 0x15A0 138#define E1000_DEV_ID_PCH_I218_V2 0x15A1 139#define E1000_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */ 140#define E1000_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */ 141#define E1000_DEV_ID_PCH_SPT_I219_LM 0x156F /* Sunrise Point PCH */ 142#define E1000_DEV_ID_PCH_SPT_I219_V 0x1570 /* Sunrise Point PCH */ 143#define E1000_DEV_ID_PCH_SPT_I219_LM2 0x15B7 /* Sunrise Point-H PCH */ 144#define E1000_DEV_ID_PCH_SPT_I219_V2 0x15B8 /* Sunrise Point-H PCH */ 145#define E1000_DEV_ID_PCH_LBG_I219_LM3 0x15B9 /* LEWISBURG PCH */ 146#define E1000_DEV_ID_PCH_SPT_I219_LM4 0x15D7 147#define E1000_DEV_ID_PCH_SPT_I219_V4 0x15D8 148#define E1000_DEV_ID_PCH_SPT_I219_LM5 0x15E3 149#define E1000_DEV_ID_PCH_SPT_I219_V5 0x15D6 150#define E1000_DEV_ID_PCH_CNP_I219_LM6 0x15BD 151#define E1000_DEV_ID_PCH_CNP_I219_V6 0x15BE 152#define E1000_DEV_ID_PCH_CNP_I219_LM7 0x15BB 153#define E1000_DEV_ID_PCH_CNP_I219_V7 0x15BC 154#define E1000_DEV_ID_PCH_ICP_I219_LM8 0x15DF 155#define E1000_DEV_ID_PCH_ICP_I219_V8 0x15E0 156#define E1000_DEV_ID_PCH_ICP_I219_LM9 0x15E1 157#define E1000_DEV_ID_PCH_ICP_I219_V9 0x15E2 158#define E1000_DEV_ID_PCH_CMP_I219_LM10 0x0D4E 159#define E1000_DEV_ID_PCH_CMP_I219_V10 0x0D4F 160#define E1000_DEV_ID_PCH_CMP_I219_LM11 0x0D4C 161#define E1000_DEV_ID_PCH_CMP_I219_V11 0x0D4D 162#define E1000_DEV_ID_PCH_CMP_I219_LM12 0x0D53 163#define E1000_DEV_ID_PCH_CMP_I219_V12 0x0D55 164#define E1000_DEV_ID_PCH_TGP_I219_LM13 0x15FB 165#define E1000_DEV_ID_PCH_TGP_I219_V13 0x15FC 166#define E1000_DEV_ID_PCH_TGP_I219_LM14 0x15F9 167#define E1000_DEV_ID_PCH_TGP_I219_V14 0x15FA 168#define E1000_DEV_ID_PCH_TGP_I219_LM15 0x15F4 169#define E1000_DEV_ID_PCH_TGP_I219_V15 0x15F5 170#define E1000_DEV_ID_PCH_ADL_I219_LM16 0x1A1E 171#define E1000_DEV_ID_PCH_ADL_I219_V16 0x1A1F 172#define E1000_DEV_ID_PCH_ADL_I219_LM17 0x1A1C 173#define E1000_DEV_ID_PCH_ADL_I219_V17 0x1A1D 174#define E1000_DEV_ID_PCH_MTP_I219_LM18 0x550A 175#define E1000_DEV_ID_PCH_MTP_I219_V18 0x550B 176#define E1000_DEV_ID_PCH_MTP_I219_LM19 0x550C 177#define E1000_DEV_ID_PCH_MTP_I219_V19 0x550D 178#define E1000_DEV_ID_82576 0x10C9 179#define E1000_DEV_ID_82576_FIBER 0x10E6 180#define E1000_DEV_ID_82576_SERDES 0x10E7 181#define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8 182#define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526 183#define E1000_DEV_ID_82576_NS 0x150A 184#define E1000_DEV_ID_82576_NS_SERDES 0x1518 185#define E1000_DEV_ID_82576_SERDES_QUAD 0x150D 186#define E1000_DEV_ID_82576_VF 0x10CA 187#define E1000_DEV_ID_82576_VF_HV 0x152D 188#define E1000_DEV_ID_I350_VF 0x1520 189#define E1000_DEV_ID_I350_VF_HV 0x152F 190#define E1000_DEV_ID_82575EB_COPPER 0x10A7 191#define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 192#define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 193#define E1000_DEV_ID_82580_COPPER 0x150E 194#define E1000_DEV_ID_82580_FIBER 0x150F 195#define E1000_DEV_ID_82580_SERDES 0x1510 196#define E1000_DEV_ID_82580_SGMII 0x1511 197#define E1000_DEV_ID_82580_COPPER_DUAL 0x1516 198#define E1000_DEV_ID_82580_QUAD_FIBER 0x1527 199#define E1000_DEV_ID_I350_COPPER 0x1521 200#define E1000_DEV_ID_I350_FIBER 0x1522 201#define E1000_DEV_ID_I350_SERDES 0x1523 202#define E1000_DEV_ID_I350_SGMII 0x1524 203#define E1000_DEV_ID_I350_DA4 0x1546 204#define E1000_DEV_ID_I210_COPPER 0x1533 205#define E1000_DEV_ID_I210_COPPER_OEM1 0x1534 206#define E1000_DEV_ID_I210_COPPER_IT 0x1535 207#define E1000_DEV_ID_I210_FIBER 0x1536 208#define E1000_DEV_ID_I210_SERDES 0x1537 209#define E1000_DEV_ID_I210_SGMII 0x1538 210#define E1000_DEV_ID_I210_COPPER_FLASHLESS 0x157B 211#define E1000_DEV_ID_I210_SERDES_FLASHLESS 0x157C 212#define E1000_DEV_ID_I211_COPPER 0x1539 213#define E1000_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40 214#define E1000_DEV_ID_I354_SGMII 0x1F41 215#define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS 0x1F45 216#define E1000_DEV_ID_DH89XXCC_SGMII 0x0438 217#define E1000_DEV_ID_DH89XXCC_SERDES 0x043A 218#define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C 219#define E1000_DEV_ID_DH89XXCC_SFP 0x0440 220 221#define E1000_REVISION_0 0 222#define E1000_REVISION_1 1 223#define E1000_REVISION_2 2 224#define E1000_REVISION_3 3 225#define E1000_REVISION_4 4 226 227#define E1000_FUNC_0 0 228#define E1000_FUNC_1 1 229#define E1000_FUNC_2 2 230#define E1000_FUNC_3 3 231 232#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 233#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 234#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6 235#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9 236 237enum e1000_mac_type { 238 e1000_undefined = 0, 239 e1000_82542, 240 e1000_82543, 241 e1000_82544, 242 e1000_82540, 243 e1000_82545, 244 e1000_82545_rev_3, 245 e1000_82546, 246 e1000_82546_rev_3, 247 e1000_82541, 248 e1000_82541_rev_2, 249 e1000_82547, 250 e1000_82547_rev_2, 251 e1000_82571, 252 e1000_82572, 253 e1000_82573, 254 e1000_82574, 255 e1000_82583, 256 e1000_80003es2lan, 257 e1000_ich8lan, 258 e1000_ich9lan, 259 e1000_ich10lan, 260 e1000_pchlan, 261 e1000_pch2lan, 262 e1000_pch_lpt, 263 e1000_pch_spt, 264 e1000_pch_cnp, 265 e1000_pch_tgp, 266 e1000_pch_adp, 267 e1000_pch_mtp, 268 e1000_82575, 269 e1000_82576, 270 e1000_82580, 271 e1000_i350, 272 e1000_i354, 273 e1000_i210, 274 e1000_i211, 275 e1000_vfadapt, 276 e1000_vfadapt_i350, 277 e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */ 278}; 279 280enum e1000_media_type { 281 e1000_media_type_unknown = 0, 282 e1000_media_type_copper = 1, 283 e1000_media_type_fiber = 2, 284 e1000_media_type_internal_serdes = 3, 285 e1000_num_media_types 286}; 287 288enum e1000_nvm_type { 289 e1000_nvm_unknown = 0, 290 e1000_nvm_none, 291 e1000_nvm_eeprom_spi, 292 e1000_nvm_eeprom_microwire, 293 e1000_nvm_flash_hw, 294 e1000_nvm_invm, 295 e1000_nvm_flash_sw 296}; 297 298enum e1000_nvm_override { 299 e1000_nvm_override_none = 0, 300 e1000_nvm_override_spi_small, 301 e1000_nvm_override_spi_large, 302 e1000_nvm_override_microwire_small, 303 e1000_nvm_override_microwire_large 304}; 305 306enum e1000_phy_type { 307 e1000_phy_unknown = 0, 308 e1000_phy_none, 309 e1000_phy_m88, 310 e1000_phy_igp, 311 e1000_phy_igp_2, 312 e1000_phy_gg82563, 313 e1000_phy_igp_3, 314 e1000_phy_ife, 315 e1000_phy_bm, 316 e1000_phy_82578, 317 e1000_phy_82577, 318 e1000_phy_82579, 319 e1000_phy_i217, 320 e1000_phy_82580, 321 e1000_phy_vf, 322 e1000_phy_i210, 323}; 324 325enum e1000_bus_type { 326 e1000_bus_type_unknown = 0, 327 e1000_bus_type_pci, 328 e1000_bus_type_pcix, 329 e1000_bus_type_pci_express, 330 e1000_bus_type_reserved 331}; 332 333enum e1000_bus_speed { 334 e1000_bus_speed_unknown = 0, 335 e1000_bus_speed_33, 336 e1000_bus_speed_66, 337 e1000_bus_speed_100, 338 e1000_bus_speed_120, 339 e1000_bus_speed_133, 340 e1000_bus_speed_2500, 341 e1000_bus_speed_5000, 342 e1000_bus_speed_reserved 343}; 344 345enum e1000_bus_width { 346 e1000_bus_width_unknown = 0, 347 e1000_bus_width_pcie_x1, 348 e1000_bus_width_pcie_x2, 349 e1000_bus_width_pcie_x4 = 4, 350 e1000_bus_width_pcie_x8 = 8, 351 e1000_bus_width_32, 352 e1000_bus_width_64, 353 e1000_bus_width_reserved 354}; 355 356enum e1000_1000t_rx_status { 357 e1000_1000t_rx_status_not_ok = 0, 358 e1000_1000t_rx_status_ok, 359 e1000_1000t_rx_status_undefined = 0xFF 360}; 361 362enum e1000_rev_polarity { 363 e1000_rev_polarity_normal = 0, 364 e1000_rev_polarity_reversed, 365 e1000_rev_polarity_undefined = 0xFF 366}; 367 368enum e1000_fc_mode { 369 e1000_fc_none = 0, 370 e1000_fc_rx_pause, 371 e1000_fc_tx_pause, 372 e1000_fc_full, 373 e1000_fc_default = 0xFF 374}; 375 376enum e1000_ffe_config { 377 e1000_ffe_config_enabled = 0, 378 e1000_ffe_config_active, 379 e1000_ffe_config_blocked 380}; 381 382enum e1000_dsp_config { 383 e1000_dsp_config_disabled = 0, 384 e1000_dsp_config_enabled, 385 e1000_dsp_config_activated, 386 e1000_dsp_config_undefined = 0xFF 387}; 388 389enum e1000_ms_type { 390 e1000_ms_hw_default = 0, 391 e1000_ms_force_master, 392 e1000_ms_force_slave, 393 e1000_ms_auto 394}; 395 396enum e1000_smart_speed { 397 e1000_smart_speed_default = 0, 398 e1000_smart_speed_on, 399 e1000_smart_speed_off 400}; 401 402enum e1000_serdes_link_state { 403 e1000_serdes_link_down = 0, 404 e1000_serdes_link_autoneg_progress, 405 e1000_serdes_link_autoneg_complete, 406 e1000_serdes_link_forced_up 407}; 408 409#define __le16 u16 410#define __le32 u32 411#define __le64 u64 412/* Receive Descriptor */ 413struct e1000_rx_desc { 414 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 415 __le16 length; /* Length of data DMAed into data buffer */ 416 __le16 csum; /* Packet checksum */ 417 u8 status; /* Descriptor status */ 418 u8 errors; /* Descriptor Errors */ 419 __le16 special; 420}; 421 422/* Receive Descriptor - Extended */ 423union e1000_rx_desc_extended { 424 struct { 425 __le64 buffer_addr; 426 __le64 reserved; 427 } read; 428 struct { 429 struct { 430 __le32 mrq; /* Multiple Rx Queues */ 431 union { 432 __le32 rss; /* RSS Hash */ 433 struct { 434 __le16 ip_id; /* IP id */ 435 __le16 csum; /* Packet Checksum */ 436 } csum_ip; 437 } hi_dword; 438 } lower; 439 struct { 440 __le32 status_error; /* ext status/error */ 441 __le16 length; 442 __le16 vlan; /* VLAN tag */ 443 } upper; 444 } wb; /* writeback */ 445}; 446 447#define MAX_PS_BUFFERS 4 448 449/* Number of packet split data buffers (not including the header buffer) */ 450#define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1) 451 452/* Receive Descriptor - Packet Split */ 453union e1000_rx_desc_packet_split { 454 struct { 455 /* one buffer for protocol header(s), three data buffers */ 456 __le64 buffer_addr[MAX_PS_BUFFERS]; 457 } read; 458 struct { 459 struct { 460 __le32 mrq; /* Multiple Rx Queues */ 461 union { 462 __le32 rss; /* RSS Hash */ 463 struct { 464 __le16 ip_id; /* IP id */ 465 __le16 csum; /* Packet Checksum */ 466 } csum_ip; 467 } hi_dword; 468 } lower; 469 struct { 470 __le32 status_error; /* ext status/error */ 471 __le16 length0; /* length of buffer 0 */ 472 __le16 vlan; /* VLAN tag */ 473 } middle; 474 struct { 475 __le16 header_status; 476 /* length of buffers 1-3 */ 477 __le16 length[PS_PAGE_BUFFERS]; 478 } upper; 479 __le64 reserved; 480 } wb; /* writeback */ 481}; 482 483/* Transmit Descriptor */ 484struct e1000_tx_desc { 485 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 486 union { 487 __le32 data; 488 struct { 489 __le16 length; /* Data buffer length */ 490 u8 cso; /* Checksum offset */ 491 u8 cmd; /* Descriptor control */ 492 } flags; 493 } lower; 494 union { 495 __le32 data; 496 struct { 497 u8 status; /* Descriptor status */ 498 u8 css; /* Checksum start */ 499 __le16 special; 500 } fields; 501 } upper; 502}; 503 504/* Offload Context Descriptor */ 505struct e1000_context_desc { 506 union { 507 __le32 ip_config; 508 struct { 509 u8 ipcss; /* IP checksum start */ 510 u8 ipcso; /* IP checksum offset */ 511 __le16 ipcse; /* IP checksum end */ 512 } ip_fields; 513 } lower_setup; 514 union { 515 __le32 tcp_config; 516 struct { 517 u8 tucss; /* TCP checksum start */ 518 u8 tucso; /* TCP checksum offset */ 519 __le16 tucse; /* TCP checksum end */ 520 } tcp_fields; 521 } upper_setup; 522 __le32 cmd_and_length; 523 union { 524 __le32 data; 525 struct { 526 u8 status; /* Descriptor status */ 527 u8 hdr_len; /* Header length */ 528 __le16 mss; /* Maximum segment size */ 529 } fields; 530 } tcp_seg_setup; 531}; 532 533/* Offload data descriptor */ 534struct e1000_data_desc { 535 __le64 buffer_addr; /* Address of the descriptor's buffer address */ 536 union { 537 __le32 data; 538 struct { 539 __le16 length; /* Data buffer length */ 540 u8 typ_len_ext; 541 u8 cmd; 542 } flags; 543 } lower; 544 union { 545 __le32 data; 546 struct { 547 u8 status; /* Descriptor status */ 548 u8 popts; /* Packet Options */ 549 __le16 special; 550 } fields; 551 } upper; 552}; 553 554/* Statistics counters collected by the MAC */ 555struct e1000_hw_stats { 556 u64 crcerrs; 557 u64 algnerrc; 558 u64 symerrs; 559 u64 rxerrc; 560 u64 mpc; 561 u64 scc; 562 u64 ecol; 563 u64 mcc; 564 u64 latecol; 565 u64 colc; 566 u64 dc; 567 u64 tncrs; 568 u64 sec; 569 u64 cexterr; 570 u64 rlec; 571 u64 xonrxc; 572 u64 xontxc; 573 u64 xoffrxc; 574 u64 xofftxc; 575 u64 fcruc; 576 u64 prc64; 577 u64 prc127; 578 u64 prc255; 579 u64 prc511; 580 u64 prc1023; 581 u64 prc1522; 582 u64 gprc; 583 u64 bprc; 584 u64 mprc; 585 u64 gptc; 586 u64 gorc; 587 u64 gotc; 588 u64 rnbc; 589 u64 ruc; 590 u64 rfc; 591 u64 roc; 592 u64 rjc; 593 u64 mgprc; 594 u64 mgpdc; 595 u64 mgptc; 596 u64 tor; 597 u64 tot; 598 u64 tpr; 599 u64 tpt; 600 u64 ptc64; 601 u64 ptc127; 602 u64 ptc255; 603 u64 ptc511; 604 u64 ptc1023; 605 u64 ptc1522; 606 u64 mptc; 607 u64 bptc; 608 u64 tsctc; 609 u64 tsctfc; 610 u64 iac; 611 u64 icrxptc; 612 u64 icrxatc; 613 u64 ictxptc; 614 u64 ictxatc; 615 u64 ictxqec; 616 u64 ictxqmtc; 617 u64 icrxdmtc; 618 u64 icrxoc; 619 u64 cbtmpc; 620 u64 htdpmc; 621 u64 cbrdpc; 622 u64 cbrmpc; 623 u64 rpthc; 624 u64 hgptc; 625 u64 htcbdpc; 626 u64 hgorc; 627 u64 hgotc; 628 u64 lenerrs; 629 u64 scvpc; 630 u64 hrmpc; 631 u64 doosync; 632 u64 o2bgptc; 633 u64 o2bspc; 634 u64 b2ospc; 635 u64 b2ogprc; 636}; 637 638struct e1000_vf_stats { 639 u64 base_gprc; 640 u64 base_gptc; 641 u64 base_gorc; 642 u64 base_gotc; 643 u64 base_mprc; 644 u64 base_gotlbc; 645 u64 base_gptlbc; 646 u64 base_gorlbc; 647 u64 base_gprlbc; 648 649 u32 last_gprc; 650 u32 last_gptc; 651 u32 last_gorc; 652 u32 last_gotc; 653 u32 last_mprc; 654 u32 last_gotlbc; 655 u32 last_gptlbc; 656 u32 last_gorlbc; 657 u32 last_gprlbc; 658 659 u64 gprc; 660 u64 gptc; 661 u64 gorc; 662 u64 gotc; 663 u64 mprc; 664 u64 gotlbc; 665 u64 gptlbc; 666 u64 gorlbc; 667 u64 gprlbc; 668}; 669 670struct e1000_phy_stats { 671 u32 idle_errors; 672 u32 receive_errors; 673}; 674 675struct e1000_host_mng_dhcp_cookie { 676 u32 signature; 677 u8 status; 678 u8 reserved0; 679 u16 vlan_id; 680 u32 reserved1; 681 u16 reserved2; 682 u8 reserved3; 683 u8 checksum; 684}; 685 686/* Host Interface "Rev 1" */ 687struct e1000_host_command_header { 688 u8 command_id; 689 u8 command_length; 690 u8 command_options; 691 u8 checksum; 692}; 693 694#define E1000_HI_MAX_DATA_LENGTH 252 695struct e1000_host_command_info { 696 struct e1000_host_command_header command_header; 697 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; 698}; 699 700/* Host Interface "Rev 2" */ 701struct e1000_host_mng_command_header { 702 u8 command_id; 703 u8 checksum; 704 u16 reserved1; 705 u16 reserved2; 706 u16 command_length; 707}; 708 709#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 710struct e1000_host_mng_command_info { 711 struct e1000_host_mng_command_header command_header; 712 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; 713}; 714 715#include "e1000_mac.h" 716#include "e1000_phy.h" 717#include "e1000_nvm.h" 718#include "e1000_manage.h" 719#include "e1000_mbx.h" 720 721/* Function pointers for the MAC. */ 722struct e1000_mac_operations { 723 s32 (*init_params)(struct e1000_hw *); 724 s32 (*id_led_init)(struct e1000_hw *); 725 s32 (*blink_led)(struct e1000_hw *); 726 bool (*check_mng_mode)(struct e1000_hw *); 727 s32 (*check_for_link)(struct e1000_hw *); 728 s32 (*cleanup_led)(struct e1000_hw *); 729 void (*clear_hw_cntrs)(struct e1000_hw *); 730 void (*clear_vfta)(struct e1000_hw *); 731 s32 (*get_bus_info)(struct e1000_hw *); 732 void (*set_lan_id)(struct e1000_hw *); 733 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 734 s32 (*led_on)(struct e1000_hw *); 735 s32 (*led_off)(struct e1000_hw *); 736 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); 737 s32 (*reset_hw)(struct e1000_hw *); 738 s32 (*init_hw)(struct e1000_hw *); 739 void (*shutdown_serdes)(struct e1000_hw *); 740 void (*power_up_serdes)(struct e1000_hw *); 741 s32 (*setup_link)(struct e1000_hw *); 742 s32 (*setup_physical_interface)(struct e1000_hw *); 743 s32 (*setup_led)(struct e1000_hw *); 744 void (*write_vfta)(struct e1000_hw *, u32, u32); 745 void (*config_collision_dist)(struct e1000_hw *); 746 int (*rar_set)(struct e1000_hw *, u8*, u32); 747 s32 (*read_mac_addr)(struct e1000_hw *); 748 s32 (*validate_mdi_setting)(struct e1000_hw *); 749 s32 (*set_obff_timer)(struct e1000_hw *, u32); 750 s32 (*acquire_swfw_sync)(struct e1000_hw *, u16); 751 void (*release_swfw_sync)(struct e1000_hw *, u16); 752}; 753 754/* When to use various PHY register access functions: 755 * 756 * Func Caller 757 * Function Does Does When to use 758 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 759 * X_reg L,P,A n/a for simple PHY reg accesses 760 * X_reg_locked P,A L for multiple accesses of different regs 761 * on different pages 762 * X_reg_page A L,P for multiple accesses of different regs 763 * on the same page 764 * 765 * Where X=[read|write], L=locking, P=sets page, A=register access 766 * 767 */ 768struct e1000_phy_operations { 769 s32 (*init_params)(struct e1000_hw *); 770 s32 (*acquire)(struct e1000_hw *); 771 s32 (*cfg_on_link_up)(struct e1000_hw *); 772 s32 (*check_polarity)(struct e1000_hw *); 773 s32 (*check_reset_block)(struct e1000_hw *); 774 s32 (*commit)(struct e1000_hw *); 775 s32 (*force_speed_duplex)(struct e1000_hw *); 776 s32 (*get_cfg_done)(struct e1000_hw *hw); 777 s32 (*get_cable_length)(struct e1000_hw *); 778 s32 (*get_info)(struct e1000_hw *); 779 s32 (*set_page)(struct e1000_hw *, u16); 780 s32 (*read_reg)(struct e1000_hw *, u32, u16 *); 781 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *); 782 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *); 783 void (*release)(struct e1000_hw *); 784 s32 (*reset)(struct e1000_hw *); 785 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); 786 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); 787 s32 (*write_reg)(struct e1000_hw *, u32, u16); 788 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16); 789 s32 (*write_reg_page)(struct e1000_hw *, u32, u16); 790 void (*power_up)(struct e1000_hw *); 791 void (*power_down)(struct e1000_hw *); 792 s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *); 793 s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8); 794}; 795 796/* Function pointers for the NVM. */ 797struct e1000_nvm_operations { 798 s32 (*init_params)(struct e1000_hw *); 799 s32 (*acquire)(struct e1000_hw *); 800 s32 (*read)(struct e1000_hw *, u16, u16, u16 *); 801 void (*release)(struct e1000_hw *); 802 void (*reload)(struct e1000_hw *); 803 s32 (*update)(struct e1000_hw *); 804 s32 (*valid_led_default)(struct e1000_hw *, u16 *); 805 s32 (*validate)(struct e1000_hw *); 806 s32 (*write)(struct e1000_hw *, u16, u16, u16 *); 807}; 808 809struct e1000_mac_info { 810 struct e1000_mac_operations ops; 811 u8 addr[ETHER_ADDR_LEN]; 812 u8 perm_addr[ETHER_ADDR_LEN]; 813 814 enum e1000_mac_type type; 815 816 u32 collision_delta; 817 u32 ledctl_default; 818 u32 ledctl_mode1; 819 u32 ledctl_mode2; 820 u32 mc_filter_type; 821 u32 tx_packet_delta; 822 u32 txcw; 823 824 u16 current_ifs_val; 825 u16 ifs_max_val; 826 u16 ifs_min_val; 827 u16 ifs_ratio; 828 u16 ifs_step_size; 829 u16 mta_reg_count; 830 u16 uta_reg_count; 831 832 /* Maximum size of the MTA register table in all supported adapters */ 833#define MAX_MTA_REG 128 834 u32 mta_shadow[MAX_MTA_REG]; 835 u16 rar_entry_count; 836 837 u8 forced_speed_duplex; 838 839 bool adaptive_ifs; 840 bool has_fwsm; 841 bool arc_subsystem_valid; 842 bool asf_firmware_present; 843 bool autoneg; 844 bool autoneg_failed; 845 bool get_link_status; 846 bool in_ifs_mode; 847 bool report_tx_early; 848 enum e1000_serdes_link_state serdes_link_state; 849 bool serdes_has_link; 850 bool tx_pkt_filtering; 851 u32 max_frame_size; 852}; 853 854struct e1000_phy_info { 855 struct e1000_phy_operations ops; 856 enum e1000_phy_type type; 857 858 enum e1000_1000t_rx_status local_rx; 859 enum e1000_1000t_rx_status remote_rx; 860 enum e1000_ms_type ms_type; 861 enum e1000_ms_type original_ms_type; 862 enum e1000_rev_polarity cable_polarity; 863 enum e1000_smart_speed smart_speed; 864 865 u32 addr; 866 u32 id; 867 u32 reset_delay_us; /* in usec */ 868 u32 revision; 869 870 enum e1000_media_type media_type; 871 872 u16 autoneg_advertised; 873 u16 autoneg_mask; 874 u16 cable_length; 875 u16 max_cable_length; 876 u16 min_cable_length; 877 878 u8 mdix; 879 880 bool disable_polarity_correction; 881 bool is_mdix; 882 bool polarity_correction; 883 bool speed_downgraded; 884 bool autoneg_wait_to_complete; 885}; 886 887struct e1000_nvm_info { 888 struct e1000_nvm_operations ops; 889 enum e1000_nvm_type type; 890 enum e1000_nvm_override override; 891 892 u32 flash_bank_size; 893 u32 flash_base_addr; 894 895 u16 word_size; 896 u16 delay_usec; 897 u16 address_bits; 898 u16 opcode_bits; 899 u16 page_size; 900}; 901 902struct e1000_bus_info { 903 enum e1000_bus_type type; 904 enum e1000_bus_speed speed; 905 enum e1000_bus_width width; 906 907 u16 func; 908 u16 pci_cmd_word; 909}; 910 911struct e1000_fc_info { 912 u32 high_water; /* Flow control high-water mark */ 913 u32 low_water; /* Flow control low-water mark */ 914 u16 pause_time; /* Flow control pause timer */ 915 u16 refresh_time; /* Flow control refresh timer */ 916 bool send_xon; /* Flow control send XON */ 917 bool strict_ieee; /* Strict IEEE mode */ 918 enum e1000_fc_mode current_mode; /* FC mode in effect */ 919 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */ 920}; 921 922struct e1000_mbx_operations { 923 s32 (*init_params)(struct e1000_hw *hw); 924 s32 (*read)(struct e1000_hw *, u32 *, u16, u16); 925 s32 (*write)(struct e1000_hw *, u32 *, u16, u16); 926 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16); 927 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16); 928 s32 (*check_for_msg)(struct e1000_hw *, u16); 929 s32 (*check_for_ack)(struct e1000_hw *, u16); 930 s32 (*check_for_rst)(struct e1000_hw *, u16); 931}; 932 933struct e1000_mbx_stats { 934 u32 msgs_tx; 935 u32 msgs_rx; 936 937 u32 acks; 938 u32 reqs; 939 u32 rsts; 940}; 941 942struct e1000_mbx_info { 943 struct e1000_mbx_operations ops; 944 struct e1000_mbx_stats stats; 945 u32 timeout; 946 u32 usec_delay; 947 u16 size; 948}; 949 950struct e1000_dev_spec_82541 { 951 enum e1000_dsp_config dsp_config; 952 enum e1000_ffe_config ffe_config; 953 u16 spd_default; 954 bool phy_init_script; 955}; 956 957struct e1000_dev_spec_82542 { 958 bool dma_fairness; 959}; 960 961struct e1000_dev_spec_82543 { 962 u32 tbi_compatibility; 963 bool dma_fairness; 964 bool init_phy_disabled; 965}; 966 967struct e1000_dev_spec_82571 { 968 bool laa_is_present; 969 u32 smb_counter; 970}; 971 972struct e1000_dev_spec_80003es2lan { 973 bool mdic_wa_enable; 974}; 975 976struct e1000_shadow_ram { 977 u16 value; 978 bool modified; 979}; 980 981#define E1000_SHADOW_RAM_WORDS 2048 982 983/* I218 PHY Ultra Low Power (ULP) states */ 984enum e1000_ulp_state { 985 e1000_ulp_state_unknown, 986 e1000_ulp_state_off, 987 e1000_ulp_state_on, 988}; 989 990struct e1000_dev_spec_ich8lan { 991 bool kmrn_lock_loss_workaround_enabled; 992 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS]; 993 bool nvm_k1_enabled; 994 bool disable_k1_off; 995 bool eee_disable; 996 u16 eee_lp_ability; 997 enum e1000_ulp_state ulp_state; 998 bool ulp_capability_disabled; 999 bool during_suspend_flow; 1000 bool during_dpg_exit; 1001}; 1002 1003struct e1000_dev_spec_82575 { 1004 bool sgmii_active; 1005 bool global_device_reset; 1006 bool eee_disable; 1007 bool module_plugged; 1008 bool clear_semaphore_once; 1009 u32 mtu; 1010 struct sfp_e1000_flags eth_flags; 1011 u8 media_port; 1012 bool media_changed; 1013}; 1014 1015struct e1000_dev_spec_vf { 1016 u32 vf_number; 1017 u32 v2p_mailbox; 1018}; 1019 1020struct e1000_hw { 1021 void *back; 1022 1023 u8 *hw_addr; 1024 u8 *flash_address; 1025 unsigned long io_base; 1026 1027 struct e1000_mac_info mac; 1028 struct e1000_fc_info fc; 1029 struct e1000_phy_info phy; 1030 struct e1000_nvm_info nvm; 1031 struct e1000_bus_info bus; 1032 struct e1000_mbx_info mbx; 1033 struct e1000_host_mng_dhcp_cookie mng_cookie; 1034 1035 union { 1036 struct e1000_dev_spec_82541 _82541; 1037 struct e1000_dev_spec_82542 _82542; 1038 struct e1000_dev_spec_82543 _82543; 1039 struct e1000_dev_spec_82571 _82571; 1040 struct e1000_dev_spec_80003es2lan _80003es2lan; 1041 struct e1000_dev_spec_ich8lan ich8lan; 1042 struct e1000_dev_spec_82575 _82575; 1043 struct e1000_dev_spec_vf vf; 1044 } dev_spec; 1045 1046 u16 device_id; 1047 u16 subsystem_vendor_id; 1048 u16 subsystem_device_id; 1049 u16 vendor_id; 1050 1051 u8 revision_id; 1052}; 1053 1054#include "e1000_82541.h" 1055#include "e1000_82543.h" 1056#include "e1000_82571.h" 1057#include "e1000_80003es2lan.h" 1058#include "e1000_ich8lan.h" 1059#include "e1000_82575.h" 1060#include "e1000_i210.h" 1061 1062/* These functions must be implemented by drivers */ 1063void e1000_pci_clear_mwi(struct e1000_hw *hw); 1064void e1000_pci_set_mwi(struct e1000_hw *hw); 1065s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 1066s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 1067void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 1068void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 1069 1070#endif 1071