1/*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29/*- 30 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 31 * Copyright (C) 1995, 1996 TooLs GmbH. 32 * All rights reserved. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 3. All advertising materials mentioning features or use of this software 43 * must display the following acknowledgement: 44 * This product includes software developed by TooLs GmbH. 45 * 4. The name of TooLs GmbH may not be used to endorse or promote products 46 * derived from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 49 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 50 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 51 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 52 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 53 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 54 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 55 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 56 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 57 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 58 * 59 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 60 */ 61/*- 62 * Copyright (C) 2001 Benno Rice. 63 * All rights reserved. 64 * 65 * Redistribution and use in source and binary forms, with or without 66 * modification, are permitted provided that the following conditions 67 * are met: 68 * 1. Redistributions of source code must retain the above copyright 69 * notice, this list of conditions and the following disclaimer. 70 * 2. Redistributions in binary form must reproduce the above copyright 71 * notice, this list of conditions and the following disclaimer in the 72 * documentation and/or other materials provided with the distribution. 73 * 74 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 75 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 76 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 77 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 78 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 79 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 80 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 81 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 82 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 83 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 84 */ 85 86#include <sys/cdefs.h> 87__FBSDID("$FreeBSD: stable/11/sys/powerpc/aim/mmu_oea.c 368823 2020-12-30 01:10:59Z bdragon $"); 88 89/* 90 * Manages physical address maps. 91 * 92 * Since the information managed by this module is also stored by the 93 * logical address mapping module, this module may throw away valid virtual 94 * to physical mappings at almost any time. However, invalidations of 95 * mappings must be done as requested. 96 * 97 * In order to cope with hardware architectures which make virtual to 98 * physical map invalidates expensive, this module may delay invalidate 99 * reduced protection operations until such time as they are actually 100 * necessary. This module is given full information as to which processors 101 * are currently using which maps, and to when physical maps must be made 102 * correct. 103 */ 104 105#include "opt_kstack_pages.h" 106 107#include <sys/param.h> 108#include <sys/kernel.h> 109#include <sys/conf.h> 110#include <sys/queue.h> 111#include <sys/cpuset.h> 112#include <sys/kerneldump.h> 113#include <sys/ktr.h> 114#include <sys/lock.h> 115#include <sys/msgbuf.h> 116#include <sys/mutex.h> 117#include <sys/proc.h> 118#include <sys/rwlock.h> 119#include <sys/sched.h> 120#include <sys/sysctl.h> 121#include <sys/systm.h> 122#include <sys/vmmeter.h> 123 124#include <dev/ofw/openfirm.h> 125 126#include <vm/vm.h> 127#include <vm/vm_param.h> 128#include <vm/vm_kern.h> 129#include <vm/vm_page.h> 130#include <vm/vm_map.h> 131#include <vm/vm_object.h> 132#include <vm/vm_extern.h> 133#include <vm/vm_pageout.h> 134#include <vm/uma.h> 135 136#include <machine/cpu.h> 137#include <machine/platform.h> 138#include <machine/bat.h> 139#include <machine/frame.h> 140#include <machine/md_var.h> 141#include <machine/psl.h> 142#include <machine/pte.h> 143#include <machine/smp.h> 144#include <machine/sr.h> 145#include <machine/mmuvar.h> 146#include <machine/trap.h> 147 148#include "mmu_if.h" 149 150#define MOEA_DEBUG 151 152#define TODO panic("%s: not implemented", __func__); 153 154#define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 155#define VSID_TO_SR(vsid) ((vsid) & 0xf) 156#define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 157 158struct ofw_map { 159 vm_offset_t om_va; 160 vm_size_t om_len; 161 vm_offset_t om_pa; 162 u_int om_mode; 163}; 164 165extern unsigned char _etext[]; 166extern unsigned char _end[]; 167 168/* 169 * Map of physical memory regions. 170 */ 171static struct mem_region *regions; 172static struct mem_region *pregions; 173static u_int phys_avail_count; 174static int regions_sz, pregions_sz; 175static struct ofw_map *translations; 176 177/* 178 * Lock for the pteg and pvo tables. 179 */ 180struct mtx moea_table_mutex; 181struct mtx moea_vsid_mutex; 182 183/* tlbie instruction synchronization */ 184static struct mtx tlbie_mtx; 185 186/* 187 * PTEG data. 188 */ 189static struct pteg *moea_pteg_table; 190u_int moea_pteg_count; 191u_int moea_pteg_mask; 192 193/* 194 * PVO data. 195 */ 196struct pvo_head *moea_pvo_table; /* pvo entries by pteg index */ 197struct pvo_head moea_pvo_kunmanaged = 198 LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */ 199 200static struct rwlock_padalign pvh_global_lock; 201 202uma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */ 203uma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */ 204 205#define BPVO_POOL_SIZE 32768 206static struct pvo_entry *moea_bpvo_pool; 207static int moea_bpvo_pool_index = 0; 208 209#define VSID_NBPW (sizeof(u_int32_t) * 8) 210static u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW]; 211 212static boolean_t moea_initialized = FALSE; 213 214/* 215 * Statistics. 216 */ 217u_int moea_pte_valid = 0; 218u_int moea_pte_overflow = 0; 219u_int moea_pte_replacements = 0; 220u_int moea_pvo_entries = 0; 221u_int moea_pvo_enter_calls = 0; 222u_int moea_pvo_remove_calls = 0; 223u_int moea_pte_spills = 0; 224SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid, 225 0, ""); 226SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD, 227 &moea_pte_overflow, 0, ""); 228SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD, 229 &moea_pte_replacements, 0, ""); 230SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries, 231 0, ""); 232SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD, 233 &moea_pvo_enter_calls, 0, ""); 234SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD, 235 &moea_pvo_remove_calls, 0, ""); 236SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD, 237 &moea_pte_spills, 0, ""); 238 239/* 240 * Allocate physical memory for use in moea_bootstrap. 241 */ 242static vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int); 243 244/* 245 * PTE calls. 246 */ 247static int moea_pte_insert(u_int, struct pte *); 248 249/* 250 * PVO calls. 251 */ 252static int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 253 vm_offset_t, vm_paddr_t, u_int, int); 254static void moea_pvo_remove(struct pvo_entry *, int); 255static struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *); 256static struct pte *moea_pvo_to_pte(const struct pvo_entry *, int); 257 258/* 259 * Utility routines. 260 */ 261static int moea_enter_locked(pmap_t, vm_offset_t, vm_page_t, 262 vm_prot_t, u_int, int8_t); 263static void moea_syncicache(vm_paddr_t, vm_size_t); 264static boolean_t moea_query_bit(vm_page_t, int); 265static u_int moea_clear_bit(vm_page_t, int); 266static void moea_kremove(mmu_t, vm_offset_t); 267int moea_pte_spill(vm_offset_t); 268 269/* 270 * Kernel MMU interface 271 */ 272void moea_clear_modify(mmu_t, vm_page_t); 273void moea_copy_page(mmu_t, vm_page_t, vm_page_t); 274void moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 275 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 276int moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, u_int, 277 int8_t); 278void moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 279 vm_prot_t); 280void moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 281vm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t); 282vm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 283void moea_init(mmu_t); 284boolean_t moea_is_modified(mmu_t, vm_page_t); 285boolean_t moea_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 286boolean_t moea_is_referenced(mmu_t, vm_page_t); 287int moea_ts_referenced(mmu_t, vm_page_t); 288vm_offset_t moea_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 289boolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t); 290void moea_page_init(mmu_t, vm_page_t); 291int moea_page_wired_mappings(mmu_t, vm_page_t); 292void moea_pinit(mmu_t, pmap_t); 293void moea_pinit0(mmu_t, pmap_t); 294void moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 295void moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 296void moea_qremove(mmu_t, vm_offset_t, int); 297void moea_release(mmu_t, pmap_t); 298void moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 299void moea_remove_all(mmu_t, vm_page_t); 300void moea_remove_write(mmu_t, vm_page_t); 301void moea_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 302void moea_zero_page(mmu_t, vm_page_t); 303void moea_zero_page_area(mmu_t, vm_page_t, int, int); 304void moea_zero_page_idle(mmu_t, vm_page_t); 305void moea_activate(mmu_t, struct thread *); 306void moea_deactivate(mmu_t, struct thread *); 307void moea_cpu_bootstrap(mmu_t, int); 308void moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 309void *moea_mapdev(mmu_t, vm_paddr_t, vm_size_t); 310void *moea_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t); 311void moea_unmapdev(mmu_t, vm_offset_t, vm_size_t); 312vm_paddr_t moea_kextract(mmu_t, vm_offset_t); 313void moea_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t); 314void moea_kenter(mmu_t, vm_offset_t, vm_paddr_t); 315void moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma); 316boolean_t moea_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 317static void moea_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 318void moea_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va); 319void moea_scan_init(mmu_t mmu); 320vm_offset_t moea_quick_enter_page(mmu_t mmu, vm_page_t m); 321void moea_quick_remove_page(mmu_t mmu, vm_offset_t addr); 322 323static mmu_method_t moea_methods[] = { 324 MMUMETHOD(mmu_clear_modify, moea_clear_modify), 325 MMUMETHOD(mmu_copy_page, moea_copy_page), 326 MMUMETHOD(mmu_copy_pages, moea_copy_pages), 327 MMUMETHOD(mmu_enter, moea_enter), 328 MMUMETHOD(mmu_enter_object, moea_enter_object), 329 MMUMETHOD(mmu_enter_quick, moea_enter_quick), 330 MMUMETHOD(mmu_extract, moea_extract), 331 MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold), 332 MMUMETHOD(mmu_init, moea_init), 333 MMUMETHOD(mmu_is_modified, moea_is_modified), 334 MMUMETHOD(mmu_is_prefaultable, moea_is_prefaultable), 335 MMUMETHOD(mmu_is_referenced, moea_is_referenced), 336 MMUMETHOD(mmu_ts_referenced, moea_ts_referenced), 337 MMUMETHOD(mmu_map, moea_map), 338 MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick), 339 MMUMETHOD(mmu_page_init, moea_page_init), 340 MMUMETHOD(mmu_page_wired_mappings,moea_page_wired_mappings), 341 MMUMETHOD(mmu_pinit, moea_pinit), 342 MMUMETHOD(mmu_pinit0, moea_pinit0), 343 MMUMETHOD(mmu_protect, moea_protect), 344 MMUMETHOD(mmu_qenter, moea_qenter), 345 MMUMETHOD(mmu_qremove, moea_qremove), 346 MMUMETHOD(mmu_release, moea_release), 347 MMUMETHOD(mmu_remove, moea_remove), 348 MMUMETHOD(mmu_remove_all, moea_remove_all), 349 MMUMETHOD(mmu_remove_write, moea_remove_write), 350 MMUMETHOD(mmu_sync_icache, moea_sync_icache), 351 MMUMETHOD(mmu_unwire, moea_unwire), 352 MMUMETHOD(mmu_zero_page, moea_zero_page), 353 MMUMETHOD(mmu_zero_page_area, moea_zero_page_area), 354 MMUMETHOD(mmu_zero_page_idle, moea_zero_page_idle), 355 MMUMETHOD(mmu_activate, moea_activate), 356 MMUMETHOD(mmu_deactivate, moea_deactivate), 357 MMUMETHOD(mmu_page_set_memattr, moea_page_set_memattr), 358 MMUMETHOD(mmu_quick_enter_page, moea_quick_enter_page), 359 MMUMETHOD(mmu_quick_remove_page, moea_quick_remove_page), 360 361 /* Internal interfaces */ 362 MMUMETHOD(mmu_bootstrap, moea_bootstrap), 363 MMUMETHOD(mmu_cpu_bootstrap, moea_cpu_bootstrap), 364 MMUMETHOD(mmu_mapdev_attr, moea_mapdev_attr), 365 MMUMETHOD(mmu_mapdev, moea_mapdev), 366 MMUMETHOD(mmu_unmapdev, moea_unmapdev), 367 MMUMETHOD(mmu_kextract, moea_kextract), 368 MMUMETHOD(mmu_kenter, moea_kenter), 369 MMUMETHOD(mmu_kenter_attr, moea_kenter_attr), 370 MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped), 371 MMUMETHOD(mmu_scan_init, moea_scan_init), 372 MMUMETHOD(mmu_dumpsys_map, moea_dumpsys_map), 373 374 { 0, 0 } 375}; 376 377MMU_DEF(oea_mmu, MMU_TYPE_OEA, moea_methods, 0); 378 379static __inline uint32_t 380moea_calc_wimg(vm_paddr_t pa, vm_memattr_t ma) 381{ 382 uint32_t pte_lo; 383 int i; 384 385 if (ma != VM_MEMATTR_DEFAULT) { 386 switch (ma) { 387 case VM_MEMATTR_UNCACHEABLE: 388 return (PTE_I | PTE_G); 389 case VM_MEMATTR_CACHEABLE: 390 return (PTE_M); 391 case VM_MEMATTR_WRITE_COMBINING: 392 case VM_MEMATTR_WRITE_BACK: 393 case VM_MEMATTR_PREFETCHABLE: 394 return (PTE_I); 395 case VM_MEMATTR_WRITE_THROUGH: 396 return (PTE_W | PTE_M); 397 } 398 } 399 400 /* 401 * Assume the page is cache inhibited and access is guarded unless 402 * it's in our available memory array. 403 */ 404 pte_lo = PTE_I | PTE_G; 405 for (i = 0; i < pregions_sz; i++) { 406 if ((pa >= pregions[i].mr_start) && 407 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 408 pte_lo = PTE_M; 409 break; 410 } 411 } 412 413 return pte_lo; 414} 415 416/* 417 * Translate OFW translations into VM attributes. 418 */ 419static __inline vm_memattr_t 420moea_bootstrap_convert_wimg(uint32_t mode) 421{ 422 423 switch (mode) { 424 case (PTE_I | PTE_G): 425 /* PCI device memory */ 426 return VM_MEMATTR_UNCACHEABLE; 427 case (PTE_M): 428 /* Explicitly coherent */ 429 return VM_MEMATTR_CACHEABLE; 430 case 0: /* Default claim */ 431 case 2: /* Alternate PP bits set by OF for the original payload */ 432 /* "Normal" memory. */ 433 return VM_MEMATTR_DEFAULT; 434 435 default: 436 /* Err on the side of caution for unknowns */ 437 /* XXX should we panic instead? */ 438 return VM_MEMATTR_UNCACHEABLE; 439 } 440} 441 442static void 443tlbie(vm_offset_t va) 444{ 445 446 mtx_lock_spin(&tlbie_mtx); 447 __asm __volatile("ptesync"); 448 __asm __volatile("tlbie %0" :: "r"(va)); 449 __asm __volatile("eieio; tlbsync; ptesync"); 450 mtx_unlock_spin(&tlbie_mtx); 451} 452 453static void 454tlbia(void) 455{ 456 vm_offset_t va; 457 458 for (va = 0; va < 0x00040000; va += 0x00001000) { 459 __asm __volatile("tlbie %0" :: "r"(va)); 460 powerpc_sync(); 461 } 462 __asm __volatile("tlbsync"); 463 powerpc_sync(); 464} 465 466static __inline int 467va_to_sr(u_int *sr, vm_offset_t va) 468{ 469 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]); 470} 471 472static __inline u_int 473va_to_pteg(u_int sr, vm_offset_t addr) 474{ 475 u_int hash; 476 477 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >> 478 ADDR_PIDX_SHFT); 479 return (hash & moea_pteg_mask); 480} 481 482static __inline struct pvo_head * 483vm_page_to_pvoh(vm_page_t m) 484{ 485 486 return (&m->md.mdpg_pvoh); 487} 488 489static __inline void 490moea_attr_clear(vm_page_t m, int ptebit) 491{ 492 493 rw_assert(&pvh_global_lock, RA_WLOCKED); 494 m->md.mdpg_attrs &= ~ptebit; 495} 496 497static __inline int 498moea_attr_fetch(vm_page_t m) 499{ 500 501 return (m->md.mdpg_attrs); 502} 503 504static __inline void 505moea_attr_save(vm_page_t m, int ptebit) 506{ 507 508 rw_assert(&pvh_global_lock, RA_WLOCKED); 509 m->md.mdpg_attrs |= ptebit; 510} 511 512static __inline int 513moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt) 514{ 515 if (pt->pte_hi == pvo_pt->pte_hi) 516 return (1); 517 518 return (0); 519} 520 521static __inline int 522moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which) 523{ 524 return (pt->pte_hi & ~PTE_VALID) == 525 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 526 ((va >> ADDR_API_SHFT) & PTE_API) | which); 527} 528 529static __inline void 530moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo) 531{ 532 533 mtx_assert(&moea_table_mutex, MA_OWNED); 534 535 /* 536 * Construct a PTE. Default to IMB initially. Valid bit only gets 537 * set when the real pte is set in memory. 538 * 539 * Note: Don't set the valid bit for correct operation of tlb update. 540 */ 541 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 542 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API); 543 pt->pte_lo = pte_lo; 544} 545 546static __inline void 547moea_pte_synch(struct pte *pt, struct pte *pvo_pt) 548{ 549 550 mtx_assert(&moea_table_mutex, MA_OWNED); 551 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG); 552} 553 554static __inline void 555moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit) 556{ 557 558 mtx_assert(&moea_table_mutex, MA_OWNED); 559 560 /* 561 * As shown in Section 7.6.3.2.3 562 */ 563 pt->pte_lo &= ~ptebit; 564 tlbie(va); 565} 566 567static __inline void 568moea_pte_set(struct pte *pt, struct pte *pvo_pt) 569{ 570 571 mtx_assert(&moea_table_mutex, MA_OWNED); 572 pvo_pt->pte_hi |= PTE_VALID; 573 574 /* 575 * Update the PTE as defined in section 7.6.3.1. 576 * Note that the REF/CHG bits are from pvo_pt and thus should have 577 * been saved so this routine can restore them (if desired). 578 */ 579 pt->pte_lo = pvo_pt->pte_lo; 580 powerpc_sync(); 581 pt->pte_hi = pvo_pt->pte_hi; 582 powerpc_sync(); 583 moea_pte_valid++; 584} 585 586static __inline void 587moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 588{ 589 590 mtx_assert(&moea_table_mutex, MA_OWNED); 591 pvo_pt->pte_hi &= ~PTE_VALID; 592 593 /* 594 * Force the reg & chg bits back into the PTEs. 595 */ 596 powerpc_sync(); 597 598 /* 599 * Invalidate the pte. 600 */ 601 pt->pte_hi &= ~PTE_VALID; 602 603 tlbie(va); 604 605 /* 606 * Save the reg & chg bits. 607 */ 608 moea_pte_synch(pt, pvo_pt); 609 moea_pte_valid--; 610} 611 612static __inline void 613moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 614{ 615 616 /* 617 * Invalidate the PTE 618 */ 619 moea_pte_unset(pt, pvo_pt, va); 620 moea_pte_set(pt, pvo_pt); 621} 622 623/* 624 * Quick sort callout for comparing memory regions. 625 */ 626static int om_cmp(const void *a, const void *b); 627 628static int 629om_cmp(const void *a, const void *b) 630{ 631 const struct ofw_map *mapa; 632 const struct ofw_map *mapb; 633 634 mapa = a; 635 mapb = b; 636 if (mapa->om_pa < mapb->om_pa) 637 return (-1); 638 else if (mapa->om_pa > mapb->om_pa) 639 return (1); 640 else 641 return (0); 642} 643 644void 645moea_cpu_bootstrap(mmu_t mmup, int ap) 646{ 647 u_int sdr; 648 int i; 649 650 if (ap) { 651 powerpc_sync(); 652 __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu)); 653 __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl)); 654 isync(); 655 __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu)); 656 __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl)); 657 isync(); 658 } 659 660 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 661 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 662 isync(); 663 664 __asm __volatile("mtibatu 1,%0" :: "r"(0)); 665 __asm __volatile("mtdbatu 2,%0" :: "r"(0)); 666 __asm __volatile("mtibatu 2,%0" :: "r"(0)); 667 __asm __volatile("mtdbatu 3,%0" :: "r"(0)); 668 __asm __volatile("mtibatu 3,%0" :: "r"(0)); 669 isync(); 670 671 for (i = 0; i < 16; i++) 672 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]); 673 powerpc_sync(); 674 675 sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10); 676 __asm __volatile("mtsdr1 %0" :: "r"(sdr)); 677 isync(); 678 679 tlbia(); 680} 681 682void 683moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 684{ 685 ihandle_t mmui; 686 phandle_t chosen, mmu; 687 int sz; 688 int i, j; 689 vm_size_t size, physsz, hwphyssz; 690 vm_offset_t pa, va, off; 691 void *dpcpu; 692 693 /* 694 * Map PCI memory space. 695 */ 696 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 697 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 698 699 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 700 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 701 702 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW); 703 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs); 704 705 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW); 706 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs); 707 708 powerpc_sync(); 709 710 /* map pci space */ 711 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 712 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 713 isync(); 714 715 /* set global direct map flag */ 716 hw_direct_map = 1; 717 718 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 719 CTR0(KTR_PMAP, "moea_bootstrap: physical memory"); 720 721 for (i = 0; i < pregions_sz; i++) { 722 vm_offset_t pa; 723 vm_offset_t end; 724 725 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)", 726 pregions[i].mr_start, 727 pregions[i].mr_start + pregions[i].mr_size, 728 pregions[i].mr_size); 729 /* 730 * Install entries into the BAT table to allow all 731 * of physmem to be convered by on-demand BAT entries. 732 * The loop will sometimes set the same battable element 733 * twice, but that's fine since they won't be used for 734 * a while yet. 735 */ 736 pa = pregions[i].mr_start & 0xf0000000; 737 end = pregions[i].mr_start + pregions[i].mr_size; 738 do { 739 u_int n = pa >> ADDR_SR_SHFT; 740 741 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW); 742 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs); 743 pa += SEGMENT_LENGTH; 744 } while (pa < end); 745 } 746 747 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 748 panic("moea_bootstrap: phys_avail too small"); 749 750 phys_avail_count = 0; 751 physsz = 0; 752 hwphyssz = 0; 753 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 754 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 755 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 756 regions[i].mr_start + regions[i].mr_size, 757 regions[i].mr_size); 758 if (hwphyssz != 0 && 759 (physsz + regions[i].mr_size) >= hwphyssz) { 760 if (physsz < hwphyssz) { 761 phys_avail[j] = regions[i].mr_start; 762 phys_avail[j + 1] = regions[i].mr_start + 763 hwphyssz - physsz; 764 physsz = hwphyssz; 765 phys_avail_count++; 766 } 767 break; 768 } 769 phys_avail[j] = regions[i].mr_start; 770 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 771 phys_avail_count++; 772 physsz += regions[i].mr_size; 773 } 774 775 /* Check for overlap with the kernel and exception vectors */ 776 for (j = 0; j < 2*phys_avail_count; j+=2) { 777 if (phys_avail[j] < EXC_LAST) 778 phys_avail[j] += EXC_LAST; 779 780 if (kernelstart >= phys_avail[j] && 781 kernelstart < phys_avail[j+1]) { 782 if (kernelend < phys_avail[j+1]) { 783 phys_avail[2*phys_avail_count] = 784 (kernelend & ~PAGE_MASK) + PAGE_SIZE; 785 phys_avail[2*phys_avail_count + 1] = 786 phys_avail[j+1]; 787 phys_avail_count++; 788 } 789 790 phys_avail[j+1] = kernelstart & ~PAGE_MASK; 791 } 792 793 if (kernelend >= phys_avail[j] && 794 kernelend < phys_avail[j+1]) { 795 if (kernelstart > phys_avail[j]) { 796 phys_avail[2*phys_avail_count] = phys_avail[j]; 797 phys_avail[2*phys_avail_count + 1] = 798 kernelstart & ~PAGE_MASK; 799 phys_avail_count++; 800 } 801 802 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE; 803 } 804 } 805 806 physmem = btoc(physsz); 807 808 /* 809 * Allocate PTEG table. 810 */ 811#ifdef PTEGCOUNT 812 moea_pteg_count = PTEGCOUNT; 813#else 814 moea_pteg_count = 0x1000; 815 816 while (moea_pteg_count < physmem) 817 moea_pteg_count <<= 1; 818 819 moea_pteg_count >>= 1; 820#endif /* PTEGCOUNT */ 821 822 size = moea_pteg_count * sizeof(struct pteg); 823 CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count, 824 size); 825 moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size); 826 CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table); 827 bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg)); 828 moea_pteg_mask = moea_pteg_count - 1; 829 830 /* 831 * Allocate pv/overflow lists. 832 */ 833 size = sizeof(struct pvo_head) * moea_pteg_count; 834 moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size, 835 PAGE_SIZE); 836 CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table); 837 for (i = 0; i < moea_pteg_count; i++) 838 LIST_INIT(&moea_pvo_table[i]); 839 840 /* 841 * Initialize the lock that synchronizes access to the pteg and pvo 842 * tables. 843 */ 844 mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF | 845 MTX_RECURSE); 846 mtx_init(&moea_vsid_mutex, "VSID table", NULL, MTX_DEF); 847 848 mtx_init(&tlbie_mtx, "tlbie", NULL, MTX_SPIN); 849 850 /* 851 * Initialise the unmanaged pvo pool. 852 */ 853 moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc( 854 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 855 moea_bpvo_pool_index = 0; 856 857 /* 858 * Make sure kernel vsid is allocated as well as VSID 0. 859 */ 860 moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 861 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 862 moea_vsid_bitmap[0] |= 1; 863 864 /* 865 * Initialize the kernel pmap (which is statically allocated). 866 */ 867 PMAP_LOCK_INIT(kernel_pmap); 868 for (i = 0; i < 16; i++) 869 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 870 CPU_FILL(&kernel_pmap->pm_active); 871 RB_INIT(&kernel_pmap->pmap_pvo); 872 873 /* 874 * Initialize the global pv list lock. 875 */ 876 rw_init(&pvh_global_lock, "pmap pv global"); 877 878 /* 879 * Set up the Open Firmware mappings 880 */ 881 chosen = OF_finddevice("/chosen"); 882 if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1 && 883 (mmu = OF_instance_to_package(mmui)) != -1 && 884 (sz = OF_getproplen(mmu, "translations")) != -1) { 885 translations = NULL; 886 for (i = 0; phys_avail[i] != 0; i += 2) { 887 if (phys_avail[i + 1] >= sz) { 888 translations = (struct ofw_map *)phys_avail[i]; 889 break; 890 } 891 } 892 if (translations == NULL) 893 panic("moea_bootstrap: no space to copy translations"); 894 bzero(translations, sz); 895 if (OF_getprop(mmu, "translations", translations, sz) == -1) 896 panic("moea_bootstrap: can't get ofw translations"); 897 CTR0(KTR_PMAP, "moea_bootstrap: translations"); 898 sz /= sizeof(*translations); 899 qsort(translations, sz, sizeof (*translations), om_cmp); 900 for (i = 0; i < sz; i++) { 901 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 902 translations[i].om_pa, translations[i].om_va, 903 translations[i].om_len); 904 905 /* 906 * If the mapping is 1:1, let the RAM and device 907 * on-demand BAT tables take care of the translation. 908 * 909 * However, always enter mappings for segment 16, 910 * which is mixed-protection and therefore not 911 * compatible with a BAT entry. 912 */ 913 if ((translations[i].om_va >> ADDR_SR_SHFT) != 0xf && 914 translations[i].om_va == translations[i].om_pa) 915 continue; 916 917 /* Enter the pages */ 918 for (off = 0; off < translations[i].om_len; 919 off += PAGE_SIZE) 920 moea_kenter_attr(mmup, 921 translations[i].om_va + off, 922 translations[i].om_pa + off, 923 moea_bootstrap_convert_wimg(translations[i].om_mode)); 924 } 925 } 926 927 /* 928 * Calculate the last available physical address. 929 */ 930 for (i = 0; phys_avail[i + 2] != 0; i += 2) 931 ; 932 Maxmem = powerpc_btop(phys_avail[i + 1]); 933 934 moea_cpu_bootstrap(mmup,0); 935 mtmsr(mfmsr() | PSL_DR | PSL_IR); 936 pmap_bootstrapped++; 937 938 /* 939 * Set the start and end of kva. 940 */ 941 virtual_avail = VM_MIN_KERNEL_ADDRESS; 942 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 943 944 /* 945 * Allocate a kernel stack with a guard page for thread0 and map it 946 * into the kernel page map. 947 */ 948 pa = moea_bootstrap_alloc(kstack_pages * PAGE_SIZE, PAGE_SIZE); 949 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 950 virtual_avail = va + kstack_pages * PAGE_SIZE; 951 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va); 952 thread0.td_kstack = va; 953 thread0.td_kstack_pages = kstack_pages; 954 for (i = 0; i < kstack_pages; i++) { 955 moea_kenter(mmup, va, pa); 956 pa += PAGE_SIZE; 957 va += PAGE_SIZE; 958 } 959 960 /* 961 * Allocate virtual address space for the message buffer. 962 */ 963 pa = msgbuf_phys = moea_bootstrap_alloc(msgbufsize, PAGE_SIZE); 964 msgbufp = (struct msgbuf *)virtual_avail; 965 va = virtual_avail; 966 virtual_avail += round_page(msgbufsize); 967 while (va < virtual_avail) { 968 moea_kenter(mmup, va, pa); 969 pa += PAGE_SIZE; 970 va += PAGE_SIZE; 971 } 972 973 /* 974 * Allocate virtual address space for the dynamic percpu area. 975 */ 976 pa = moea_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 977 dpcpu = (void *)virtual_avail; 978 va = virtual_avail; 979 virtual_avail += DPCPU_SIZE; 980 while (va < virtual_avail) { 981 moea_kenter(mmup, va, pa); 982 pa += PAGE_SIZE; 983 va += PAGE_SIZE; 984 } 985 dpcpu_init(dpcpu, 0); 986} 987 988/* 989 * Activate a user pmap. The pmap must be activated before it's address 990 * space can be accessed in any way. 991 */ 992void 993moea_activate(mmu_t mmu, struct thread *td) 994{ 995 pmap_t pm, pmr; 996 997 /* 998 * Load all the data we need up front to encourage the compiler to 999 * not issue any loads while we have interrupts disabled below. 1000 */ 1001 pm = &td->td_proc->p_vmspace->vm_pmap; 1002 pmr = pm->pmap_phys; 1003 1004 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 1005 PCPU_SET(curpmap, pmr); 1006 1007 mtsrin(USER_SR << ADDR_SR_SHFT, td->td_pcb->pcb_cpu.aim.usr_vsid); 1008} 1009 1010void 1011moea_deactivate(mmu_t mmu, struct thread *td) 1012{ 1013 pmap_t pm; 1014 1015 pm = &td->td_proc->p_vmspace->vm_pmap; 1016 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1017 PCPU_SET(curpmap, NULL); 1018} 1019 1020void 1021moea_unwire(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1022{ 1023 struct pvo_entry key, *pvo; 1024 1025 PMAP_LOCK(pm); 1026 key.pvo_vaddr = sva; 1027 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1028 pvo != NULL && PVO_VADDR(pvo) < eva; 1029 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 1030 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1031 panic("moea_unwire: pvo %p is missing PVO_WIRED", pvo); 1032 pvo->pvo_vaddr &= ~PVO_WIRED; 1033 pm->pm_stats.wired_count--; 1034 } 1035 PMAP_UNLOCK(pm); 1036} 1037 1038void 1039moea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1040{ 1041 vm_offset_t dst; 1042 vm_offset_t src; 1043 1044 dst = VM_PAGE_TO_PHYS(mdst); 1045 src = VM_PAGE_TO_PHYS(msrc); 1046 1047 bcopy((void *)src, (void *)dst, PAGE_SIZE); 1048} 1049 1050void 1051moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1052 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1053{ 1054 void *a_cp, *b_cp; 1055 vm_offset_t a_pg_offset, b_pg_offset; 1056 int cnt; 1057 1058 while (xfersize > 0) { 1059 a_pg_offset = a_offset & PAGE_MASK; 1060 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1061 a_cp = (char *)VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]) + 1062 a_pg_offset; 1063 b_pg_offset = b_offset & PAGE_MASK; 1064 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1065 b_cp = (char *)VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]) + 1066 b_pg_offset; 1067 bcopy(a_cp, b_cp, cnt); 1068 a_offset += cnt; 1069 b_offset += cnt; 1070 xfersize -= cnt; 1071 } 1072} 1073 1074/* 1075 * Zero a page of physical memory by temporarily mapping it into the tlb. 1076 */ 1077void 1078moea_zero_page(mmu_t mmu, vm_page_t m) 1079{ 1080 vm_offset_t off, pa = VM_PAGE_TO_PHYS(m); 1081 1082 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1083 __asm __volatile("dcbz 0,%0" :: "r"(pa + off)); 1084} 1085 1086void 1087moea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1088{ 1089 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1090 void *va = (void *)(pa + off); 1091 1092 bzero(va, size); 1093} 1094 1095void 1096moea_zero_page_idle(mmu_t mmu, vm_page_t m) 1097{ 1098 1099 moea_zero_page(mmu, m); 1100} 1101 1102vm_offset_t 1103moea_quick_enter_page(mmu_t mmu, vm_page_t m) 1104{ 1105 1106 return (VM_PAGE_TO_PHYS(m)); 1107} 1108 1109void 1110moea_quick_remove_page(mmu_t mmu, vm_offset_t addr) 1111{ 1112} 1113 1114/* 1115 * Map the given physical page at the specified virtual address in the 1116 * target pmap with the protection requested. If specified the page 1117 * will be wired down. 1118 */ 1119int 1120moea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1121 u_int flags, int8_t psind) 1122{ 1123 int error; 1124 1125 for (;;) { 1126 rw_wlock(&pvh_global_lock); 1127 PMAP_LOCK(pmap); 1128 error = moea_enter_locked(pmap, va, m, prot, flags, psind); 1129 rw_wunlock(&pvh_global_lock); 1130 PMAP_UNLOCK(pmap); 1131 if (error != ENOMEM) 1132 return (KERN_SUCCESS); 1133 if ((flags & PMAP_ENTER_NOSLEEP) != 0) 1134 return (KERN_RESOURCE_SHORTAGE); 1135 VM_OBJECT_ASSERT_UNLOCKED(m->object); 1136 VM_WAIT; 1137 } 1138} 1139 1140/* 1141 * Map the given physical page at the specified virtual address in the 1142 * target pmap with the protection requested. If specified the page 1143 * will be wired down. 1144 * 1145 * The global pvh and pmap must be locked. 1146 */ 1147static int 1148moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1149 u_int flags, int8_t psind __unused) 1150{ 1151 struct pvo_head *pvo_head; 1152 uma_zone_t zone; 1153 u_int pte_lo, pvo_flags; 1154 int error; 1155 1156 if (pmap_bootstrapped) 1157 rw_assert(&pvh_global_lock, RA_WLOCKED); 1158 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1159 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 1160 VM_OBJECT_ASSERT_LOCKED(m->object); 1161 1162 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea_initialized) { 1163 pvo_head = &moea_pvo_kunmanaged; 1164 zone = moea_upvo_zone; 1165 pvo_flags = 0; 1166 } else { 1167 pvo_head = vm_page_to_pvoh(m); 1168 zone = moea_mpvo_zone; 1169 pvo_flags = PVO_MANAGED; 1170 } 1171 1172 pte_lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1173 1174 if (prot & VM_PROT_WRITE) { 1175 pte_lo |= PTE_BW; 1176 if (pmap_bootstrapped && 1177 (m->oflags & VPO_UNMANAGED) == 0) 1178 vm_page_aflag_set(m, PGA_WRITEABLE); 1179 } else 1180 pte_lo |= PTE_BR; 1181 1182 if ((flags & PMAP_ENTER_WIRED) != 0) 1183 pvo_flags |= PVO_WIRED; 1184 1185 error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1186 pte_lo, pvo_flags); 1187 1188 /* 1189 * Flush the real page from the instruction cache. This has be done 1190 * for all user mappings to prevent information leakage via the 1191 * instruction cache. moea_pvo_enter() returns ENOENT for the first 1192 * mapping for a page. 1193 */ 1194 if (pmap != kernel_pmap && error == ENOENT && 1195 (pte_lo & (PTE_I | PTE_G)) == 0) 1196 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1197 1198 return (error); 1199} 1200 1201/* 1202 * Maps a sequence of resident pages belonging to the same object. 1203 * The sequence begins with the given page m_start. This page is 1204 * mapped at the given virtual address start. Each subsequent page is 1205 * mapped at a virtual address that is offset from start by the same 1206 * amount as the page is offset from m_start within the object. The 1207 * last page in the sequence is the page with the largest offset from 1208 * m_start that can be mapped at a virtual address less than the given 1209 * virtual address end. Not every virtual page between start and end 1210 * is mapped; only those for which a resident page exists with the 1211 * corresponding offset from m_start are mapped. 1212 */ 1213void 1214moea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1215 vm_page_t m_start, vm_prot_t prot) 1216{ 1217 vm_page_t m; 1218 vm_pindex_t diff, psize; 1219 1220 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1221 1222 psize = atop(end - start); 1223 m = m_start; 1224 rw_wlock(&pvh_global_lock); 1225 PMAP_LOCK(pm); 1226 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1227 moea_enter_locked(pm, start + ptoa(diff), m, prot & 1228 (VM_PROT_READ | VM_PROT_EXECUTE), 0, 0); 1229 m = TAILQ_NEXT(m, listq); 1230 } 1231 rw_wunlock(&pvh_global_lock); 1232 PMAP_UNLOCK(pm); 1233} 1234 1235void 1236moea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1237 vm_prot_t prot) 1238{ 1239 1240 rw_wlock(&pvh_global_lock); 1241 PMAP_LOCK(pm); 1242 moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1243 0, 0); 1244 rw_wunlock(&pvh_global_lock); 1245 PMAP_UNLOCK(pm); 1246} 1247 1248vm_paddr_t 1249moea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1250{ 1251 struct pvo_entry *pvo; 1252 vm_paddr_t pa; 1253 1254 PMAP_LOCK(pm); 1255 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1256 if (pvo == NULL) 1257 pa = 0; 1258 else 1259 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1260 PMAP_UNLOCK(pm); 1261 return (pa); 1262} 1263 1264/* 1265 * Atomically extract and hold the physical page with the given 1266 * pmap and virtual address pair if that mapping permits the given 1267 * protection. 1268 */ 1269vm_page_t 1270moea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1271{ 1272 struct pvo_entry *pvo; 1273 vm_page_t m; 1274 vm_paddr_t pa; 1275 1276 m = NULL; 1277 pa = 0; 1278 PMAP_LOCK(pmap); 1279retry: 1280 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1281 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID) && 1282 ((pvo->pvo_pte.pte.pte_lo & PTE_PP) == PTE_RW || 1283 (prot & VM_PROT_WRITE) == 0)) { 1284 if (vm_page_pa_tryrelock(pmap, pvo->pvo_pte.pte.pte_lo & PTE_RPGN, &pa)) 1285 goto retry; 1286 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 1287 vm_page_hold(m); 1288 } 1289 PA_UNLOCK_COND(pa); 1290 PMAP_UNLOCK(pmap); 1291 return (m); 1292} 1293 1294void 1295moea_init(mmu_t mmu) 1296{ 1297 1298 moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1299 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1300 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1301 moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1302 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1303 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1304 moea_initialized = TRUE; 1305} 1306 1307boolean_t 1308moea_is_referenced(mmu_t mmu, vm_page_t m) 1309{ 1310 boolean_t rv; 1311 1312 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1313 ("moea_is_referenced: page %p is not managed", m)); 1314 rw_wlock(&pvh_global_lock); 1315 rv = moea_query_bit(m, PTE_REF); 1316 rw_wunlock(&pvh_global_lock); 1317 return (rv); 1318} 1319 1320boolean_t 1321moea_is_modified(mmu_t mmu, vm_page_t m) 1322{ 1323 boolean_t rv; 1324 1325 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1326 ("moea_is_modified: page %p is not managed", m)); 1327 1328 /* 1329 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1330 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 1331 * is clear, no PTEs can have PTE_CHG set. 1332 */ 1333 VM_OBJECT_ASSERT_WLOCKED(m->object); 1334 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1335 return (FALSE); 1336 rw_wlock(&pvh_global_lock); 1337 rv = moea_query_bit(m, PTE_CHG); 1338 rw_wunlock(&pvh_global_lock); 1339 return (rv); 1340} 1341 1342boolean_t 1343moea_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1344{ 1345 struct pvo_entry *pvo; 1346 boolean_t rv; 1347 1348 PMAP_LOCK(pmap); 1349 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1350 rv = pvo == NULL || (pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0; 1351 PMAP_UNLOCK(pmap); 1352 return (rv); 1353} 1354 1355void 1356moea_clear_modify(mmu_t mmu, vm_page_t m) 1357{ 1358 1359 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1360 ("moea_clear_modify: page %p is not managed", m)); 1361 VM_OBJECT_ASSERT_WLOCKED(m->object); 1362 KASSERT(!vm_page_xbusied(m), 1363 ("moea_clear_modify: page %p is exclusive busy", m)); 1364 1365 /* 1366 * If the page is not PGA_WRITEABLE, then no PTEs can have PTE_CHG 1367 * set. If the object containing the page is locked and the page is 1368 * not exclusive busied, then PGA_WRITEABLE cannot be concurrently set. 1369 */ 1370 if ((m->aflags & PGA_WRITEABLE) == 0) 1371 return; 1372 rw_wlock(&pvh_global_lock); 1373 moea_clear_bit(m, PTE_CHG); 1374 rw_wunlock(&pvh_global_lock); 1375} 1376 1377/* 1378 * Clear the write and modified bits in each of the given page's mappings. 1379 */ 1380void 1381moea_remove_write(mmu_t mmu, vm_page_t m) 1382{ 1383 struct pvo_entry *pvo; 1384 struct pte *pt; 1385 pmap_t pmap; 1386 u_int lo; 1387 1388 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1389 ("moea_remove_write: page %p is not managed", m)); 1390 1391 /* 1392 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1393 * set by another thread while the object is locked. Thus, 1394 * if PGA_WRITEABLE is clear, no page table entries need updating. 1395 */ 1396 VM_OBJECT_ASSERT_WLOCKED(m->object); 1397 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1398 return; 1399 rw_wlock(&pvh_global_lock); 1400 lo = moea_attr_fetch(m); 1401 powerpc_sync(); 1402 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1403 pmap = pvo->pvo_pmap; 1404 PMAP_LOCK(pmap); 1405 if ((pvo->pvo_pte.pte.pte_lo & PTE_PP) != PTE_BR) { 1406 pt = moea_pvo_to_pte(pvo, -1); 1407 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1408 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1409 if (pt != NULL) { 1410 moea_pte_synch(pt, &pvo->pvo_pte.pte); 1411 lo |= pvo->pvo_pte.pte.pte_lo; 1412 pvo->pvo_pte.pte.pte_lo &= ~PTE_CHG; 1413 moea_pte_change(pt, &pvo->pvo_pte.pte, 1414 pvo->pvo_vaddr); 1415 mtx_unlock(&moea_table_mutex); 1416 } 1417 } 1418 PMAP_UNLOCK(pmap); 1419 } 1420 if ((lo & PTE_CHG) != 0) { 1421 moea_attr_clear(m, PTE_CHG); 1422 vm_page_dirty(m); 1423 } 1424 vm_page_aflag_clear(m, PGA_WRITEABLE); 1425 rw_wunlock(&pvh_global_lock); 1426} 1427 1428/* 1429 * moea_ts_referenced: 1430 * 1431 * Return a count of reference bits for a page, clearing those bits. 1432 * It is not necessary for every reference bit to be cleared, but it 1433 * is necessary that 0 only be returned when there are truly no 1434 * reference bits set. 1435 * 1436 * XXX: The exact number of bits to check and clear is a matter that 1437 * should be tested and standardized at some point in the future for 1438 * optimal aging of shared pages. 1439 */ 1440int 1441moea_ts_referenced(mmu_t mmu, vm_page_t m) 1442{ 1443 int count; 1444 1445 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1446 ("moea_ts_referenced: page %p is not managed", m)); 1447 rw_wlock(&pvh_global_lock); 1448 count = moea_clear_bit(m, PTE_REF); 1449 rw_wunlock(&pvh_global_lock); 1450 return (count); 1451} 1452 1453/* 1454 * Modify the WIMG settings of all mappings for a page. 1455 */ 1456void 1457moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1458{ 1459 struct pvo_entry *pvo; 1460 struct pvo_head *pvo_head; 1461 struct pte *pt; 1462 pmap_t pmap; 1463 u_int lo; 1464 1465 if ((m->oflags & VPO_UNMANAGED) != 0) { 1466 m->md.mdpg_cache_attrs = ma; 1467 return; 1468 } 1469 1470 rw_wlock(&pvh_global_lock); 1471 pvo_head = vm_page_to_pvoh(m); 1472 lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1473 1474 LIST_FOREACH(pvo, pvo_head, pvo_vlink) { 1475 pmap = pvo->pvo_pmap; 1476 PMAP_LOCK(pmap); 1477 pt = moea_pvo_to_pte(pvo, -1); 1478 pvo->pvo_pte.pte.pte_lo &= ~PTE_WIMG; 1479 pvo->pvo_pte.pte.pte_lo |= lo; 1480 if (pt != NULL) { 1481 moea_pte_change(pt, &pvo->pvo_pte.pte, 1482 pvo->pvo_vaddr); 1483 if (pvo->pvo_pmap == kernel_pmap) 1484 isync(); 1485 } 1486 mtx_unlock(&moea_table_mutex); 1487 PMAP_UNLOCK(pmap); 1488 } 1489 m->md.mdpg_cache_attrs = ma; 1490 rw_wunlock(&pvh_global_lock); 1491} 1492 1493/* 1494 * Map a wired page into kernel virtual address space. 1495 */ 1496void 1497moea_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1498{ 1499 1500 moea_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1501} 1502 1503void 1504moea_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 1505{ 1506 u_int pte_lo; 1507 int error; 1508 1509#if 0 1510 if (va < VM_MIN_KERNEL_ADDRESS) 1511 panic("moea_kenter: attempt to enter non-kernel address %#x", 1512 va); 1513#endif 1514 1515 pte_lo = moea_calc_wimg(pa, ma); 1516 1517 PMAP_LOCK(kernel_pmap); 1518 error = moea_pvo_enter(kernel_pmap, moea_upvo_zone, 1519 &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED); 1520 1521 if (error != 0 && error != ENOENT) 1522 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va, 1523 pa, error); 1524 1525 PMAP_UNLOCK(kernel_pmap); 1526} 1527 1528/* 1529 * Extract the physical page address associated with the given kernel virtual 1530 * address. 1531 */ 1532vm_paddr_t 1533moea_kextract(mmu_t mmu, vm_offset_t va) 1534{ 1535 struct pvo_entry *pvo; 1536 vm_paddr_t pa; 1537 1538 /* 1539 * Allow direct mappings on 32-bit OEA 1540 */ 1541 if (va < VM_MIN_KERNEL_ADDRESS) { 1542 return (va); 1543 } 1544 1545 PMAP_LOCK(kernel_pmap); 1546 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1547 KASSERT(pvo != NULL, ("moea_kextract: no addr found")); 1548 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1549 PMAP_UNLOCK(kernel_pmap); 1550 return (pa); 1551} 1552 1553/* 1554 * Remove a wired page from kernel virtual address space. 1555 */ 1556void 1557moea_kremove(mmu_t mmu, vm_offset_t va) 1558{ 1559 1560 moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1561} 1562 1563/* 1564 * Map a range of physical addresses into kernel virtual address space. 1565 * 1566 * The value passed in *virt is a suggested virtual address for the mapping. 1567 * Architectures which can support a direct-mapped physical to virtual region 1568 * can return the appropriate address within that region, leaving '*virt' 1569 * unchanged. We cannot and therefore do not; *virt is updated with the 1570 * first usable address after the mapped region. 1571 */ 1572vm_offset_t 1573moea_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 1574 vm_paddr_t pa_end, int prot) 1575{ 1576 vm_offset_t sva, va; 1577 1578 sva = *virt; 1579 va = sva; 1580 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1581 moea_kenter(mmu, va, pa_start); 1582 *virt = va; 1583 return (sva); 1584} 1585 1586/* 1587 * Returns true if the pmap's pv is one of the first 1588 * 16 pvs linked to from this page. This count may 1589 * be changed upwards or downwards in the future; it 1590 * is only necessary that true be returned for a small 1591 * subset of pmaps for proper page aging. 1592 */ 1593boolean_t 1594moea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1595{ 1596 int loops; 1597 struct pvo_entry *pvo; 1598 boolean_t rv; 1599 1600 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1601 ("moea_page_exists_quick: page %p is not managed", m)); 1602 loops = 0; 1603 rv = FALSE; 1604 rw_wlock(&pvh_global_lock); 1605 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1606 if (pvo->pvo_pmap == pmap) { 1607 rv = TRUE; 1608 break; 1609 } 1610 if (++loops >= 16) 1611 break; 1612 } 1613 rw_wunlock(&pvh_global_lock); 1614 return (rv); 1615} 1616 1617void 1618moea_page_init(mmu_t mmu __unused, vm_page_t m) 1619{ 1620 1621 m->md.mdpg_attrs = 0; 1622 m->md.mdpg_cache_attrs = VM_MEMATTR_DEFAULT; 1623 LIST_INIT(&m->md.mdpg_pvoh); 1624} 1625 1626/* 1627 * Return the number of managed mappings to the given physical page 1628 * that are wired. 1629 */ 1630int 1631moea_page_wired_mappings(mmu_t mmu, vm_page_t m) 1632{ 1633 struct pvo_entry *pvo; 1634 int count; 1635 1636 count = 0; 1637 if ((m->oflags & VPO_UNMANAGED) != 0) 1638 return (count); 1639 rw_wlock(&pvh_global_lock); 1640 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1641 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1642 count++; 1643 rw_wunlock(&pvh_global_lock); 1644 return (count); 1645} 1646 1647static u_int moea_vsidcontext; 1648 1649void 1650moea_pinit(mmu_t mmu, pmap_t pmap) 1651{ 1652 int i, mask; 1653 u_int entropy; 1654 1655 KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap")); 1656 RB_INIT(&pmap->pmap_pvo); 1657 1658 entropy = 0; 1659 __asm __volatile("mftb %0" : "=r"(entropy)); 1660 1661 if ((pmap->pmap_phys = (pmap_t)moea_kextract(mmu, (vm_offset_t)pmap)) 1662 == NULL) { 1663 pmap->pmap_phys = pmap; 1664 } 1665 1666 1667 mtx_lock(&moea_vsid_mutex); 1668 /* 1669 * Allocate some segment registers for this pmap. 1670 */ 1671 for (i = 0; i < NPMAPS; i += VSID_NBPW) { 1672 u_int hash, n; 1673 1674 /* 1675 * Create a new value by mutiplying by a prime and adding in 1676 * entropy from the timebase register. This is to make the 1677 * VSID more random so that the PT hash function collides 1678 * less often. (Note that the prime casues gcc to do shifts 1679 * instead of a multiply.) 1680 */ 1681 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy; 1682 hash = moea_vsidcontext & (NPMAPS - 1); 1683 if (hash == 0) /* 0 is special, avoid it */ 1684 continue; 1685 n = hash >> 5; 1686 mask = 1 << (hash & (VSID_NBPW - 1)); 1687 hash = (moea_vsidcontext & 0xfffff); 1688 if (moea_vsid_bitmap[n] & mask) { /* collision? */ 1689 /* anything free in this bucket? */ 1690 if (moea_vsid_bitmap[n] == 0xffffffff) { 1691 entropy = (moea_vsidcontext >> 20); 1692 continue; 1693 } 1694 i = ffs(~moea_vsid_bitmap[n]) - 1; 1695 mask = 1 << i; 1696 hash &= rounddown2(0xfffff, VSID_NBPW); 1697 hash |= i; 1698 } 1699 KASSERT(!(moea_vsid_bitmap[n] & mask), 1700 ("Allocating in-use VSID group %#x\n", hash)); 1701 moea_vsid_bitmap[n] |= mask; 1702 for (i = 0; i < 16; i++) 1703 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1704 mtx_unlock(&moea_vsid_mutex); 1705 return; 1706 } 1707 1708 mtx_unlock(&moea_vsid_mutex); 1709 panic("moea_pinit: out of segments"); 1710} 1711 1712/* 1713 * Initialize the pmap associated with process 0. 1714 */ 1715void 1716moea_pinit0(mmu_t mmu, pmap_t pm) 1717{ 1718 1719 PMAP_LOCK_INIT(pm); 1720 moea_pinit(mmu, pm); 1721 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1722} 1723 1724/* 1725 * Set the physical protection on the specified range of this map as requested. 1726 */ 1727void 1728moea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1729 vm_prot_t prot) 1730{ 1731 struct pvo_entry *pvo, *tpvo, key; 1732 struct pte *pt; 1733 1734 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1735 ("moea_protect: non current pmap")); 1736 1737 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1738 moea_remove(mmu, pm, sva, eva); 1739 return; 1740 } 1741 1742 rw_wlock(&pvh_global_lock); 1743 PMAP_LOCK(pm); 1744 key.pvo_vaddr = sva; 1745 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1746 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 1747 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 1748 1749 /* 1750 * Grab the PTE pointer before we diddle with the cached PTE 1751 * copy. 1752 */ 1753 pt = moea_pvo_to_pte(pvo, -1); 1754 /* 1755 * Change the protection of the page. 1756 */ 1757 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1758 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1759 1760 /* 1761 * If the PVO is in the page table, update that pte as well. 1762 */ 1763 if (pt != NULL) { 1764 moea_pte_change(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 1765 mtx_unlock(&moea_table_mutex); 1766 } 1767 } 1768 rw_wunlock(&pvh_global_lock); 1769 PMAP_UNLOCK(pm); 1770} 1771 1772/* 1773 * Map a list of wired pages into kernel virtual address space. This is 1774 * intended for temporary mappings which do not need page modification or 1775 * references recorded. Existing mappings in the region are overwritten. 1776 */ 1777void 1778moea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1779{ 1780 vm_offset_t va; 1781 1782 va = sva; 1783 while (count-- > 0) { 1784 moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1785 va += PAGE_SIZE; 1786 m++; 1787 } 1788} 1789 1790/* 1791 * Remove page mappings from kernel virtual address space. Intended for 1792 * temporary mappings entered by moea_qenter. 1793 */ 1794void 1795moea_qremove(mmu_t mmu, vm_offset_t sva, int count) 1796{ 1797 vm_offset_t va; 1798 1799 va = sva; 1800 while (count-- > 0) { 1801 moea_kremove(mmu, va); 1802 va += PAGE_SIZE; 1803 } 1804} 1805 1806void 1807moea_release(mmu_t mmu, pmap_t pmap) 1808{ 1809 int idx, mask; 1810 1811 /* 1812 * Free segment register's VSID 1813 */ 1814 if (pmap->pm_sr[0] == 0) 1815 panic("moea_release"); 1816 1817 mtx_lock(&moea_vsid_mutex); 1818 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1819 mask = 1 << (idx % VSID_NBPW); 1820 idx /= VSID_NBPW; 1821 moea_vsid_bitmap[idx] &= ~mask; 1822 mtx_unlock(&moea_vsid_mutex); 1823} 1824 1825/* 1826 * Remove the given range of addresses from the specified map. 1827 */ 1828void 1829moea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1830{ 1831 struct pvo_entry *pvo, *tpvo, key; 1832 1833 rw_wlock(&pvh_global_lock); 1834 PMAP_LOCK(pm); 1835 key.pvo_vaddr = sva; 1836 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1837 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 1838 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 1839 moea_pvo_remove(pvo, -1); 1840 } 1841 PMAP_UNLOCK(pm); 1842 rw_wunlock(&pvh_global_lock); 1843} 1844 1845/* 1846 * Remove physical page from all pmaps in which it resides. moea_pvo_remove() 1847 * will reflect changes in pte's back to the vm_page. 1848 */ 1849void 1850moea_remove_all(mmu_t mmu, vm_page_t m) 1851{ 1852 struct pvo_head *pvo_head; 1853 struct pvo_entry *pvo, *next_pvo; 1854 pmap_t pmap; 1855 1856 rw_wlock(&pvh_global_lock); 1857 pvo_head = vm_page_to_pvoh(m); 1858 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1859 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1860 1861 pmap = pvo->pvo_pmap; 1862 PMAP_LOCK(pmap); 1863 moea_pvo_remove(pvo, -1); 1864 PMAP_UNLOCK(pmap); 1865 } 1866 if ((m->aflags & PGA_WRITEABLE) && moea_query_bit(m, PTE_CHG)) { 1867 moea_attr_clear(m, PTE_CHG); 1868 vm_page_dirty(m); 1869 } 1870 vm_page_aflag_clear(m, PGA_WRITEABLE); 1871 rw_wunlock(&pvh_global_lock); 1872} 1873 1874/* 1875 * Allocate a physical page of memory directly from the phys_avail map. 1876 * Can only be called from moea_bootstrap before avail start and end are 1877 * calculated. 1878 */ 1879static vm_offset_t 1880moea_bootstrap_alloc(vm_size_t size, u_int align) 1881{ 1882 vm_offset_t s, e; 1883 int i, j; 1884 1885 size = round_page(size); 1886 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 1887 if (align != 0) 1888 s = roundup2(phys_avail[i], align); 1889 else 1890 s = phys_avail[i]; 1891 e = s + size; 1892 1893 if (s < phys_avail[i] || e > phys_avail[i + 1]) 1894 continue; 1895 1896 if (s == phys_avail[i]) { 1897 phys_avail[i] += size; 1898 } else if (e == phys_avail[i + 1]) { 1899 phys_avail[i + 1] -= size; 1900 } else { 1901 for (j = phys_avail_count * 2; j > i; j -= 2) { 1902 phys_avail[j] = phys_avail[j - 2]; 1903 phys_avail[j + 1] = phys_avail[j - 1]; 1904 } 1905 1906 phys_avail[i + 3] = phys_avail[i + 1]; 1907 phys_avail[i + 1] = s; 1908 phys_avail[i + 2] = e; 1909 phys_avail_count++; 1910 } 1911 1912 return (s); 1913 } 1914 panic("moea_bootstrap_alloc: could not allocate memory"); 1915} 1916 1917static void 1918moea_syncicache(vm_paddr_t pa, vm_size_t len) 1919{ 1920 __syncicache((void *)pa, len); 1921} 1922 1923static int 1924moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 1925 vm_offset_t va, vm_paddr_t pa, u_int pte_lo, int flags) 1926{ 1927 struct pvo_entry *pvo; 1928 u_int sr; 1929 int first; 1930 u_int ptegidx; 1931 int i; 1932 int bootstrap; 1933 1934 moea_pvo_enter_calls++; 1935 first = 0; 1936 bootstrap = 0; 1937 1938 /* 1939 * Compute the PTE Group index. 1940 */ 1941 va &= ~ADDR_POFF; 1942 sr = va_to_sr(pm->pm_sr, va); 1943 ptegidx = va_to_pteg(sr, va); 1944 1945 /* 1946 * Remove any existing mapping for this page. Reuse the pvo entry if 1947 * there is a mapping. 1948 */ 1949 mtx_lock(&moea_table_mutex); 1950 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 1951 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 1952 if ((pvo->pvo_pte.pte.pte_lo & PTE_RPGN) == pa && 1953 (pvo->pvo_pte.pte.pte_lo & PTE_PP) == 1954 (pte_lo & PTE_PP)) { 1955 /* 1956 * The PTE is not changing. Instead, this may 1957 * be a request to change the mapping's wired 1958 * attribute. 1959 */ 1960 mtx_unlock(&moea_table_mutex); 1961 if ((flags & PVO_WIRED) != 0 && 1962 (pvo->pvo_vaddr & PVO_WIRED) == 0) { 1963 pvo->pvo_vaddr |= PVO_WIRED; 1964 pm->pm_stats.wired_count++; 1965 } else if ((flags & PVO_WIRED) == 0 && 1966 (pvo->pvo_vaddr & PVO_WIRED) != 0) { 1967 pvo->pvo_vaddr &= ~PVO_WIRED; 1968 pm->pm_stats.wired_count--; 1969 } 1970 return (0); 1971 } 1972 moea_pvo_remove(pvo, -1); 1973 break; 1974 } 1975 } 1976 1977 /* 1978 * If we aren't overwriting a mapping, try to allocate. 1979 */ 1980 if (moea_initialized) { 1981 pvo = uma_zalloc(zone, M_NOWAIT); 1982 } else { 1983 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) { 1984 panic("moea_enter: bpvo pool exhausted, %d, %d, %d", 1985 moea_bpvo_pool_index, BPVO_POOL_SIZE, 1986 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 1987 } 1988 pvo = &moea_bpvo_pool[moea_bpvo_pool_index]; 1989 moea_bpvo_pool_index++; 1990 bootstrap = 1; 1991 } 1992 1993 if (pvo == NULL) { 1994 mtx_unlock(&moea_table_mutex); 1995 return (ENOMEM); 1996 } 1997 1998 moea_pvo_entries++; 1999 pvo->pvo_vaddr = va; 2000 pvo->pvo_pmap = pm; 2001 LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink); 2002 pvo->pvo_vaddr &= ~ADDR_POFF; 2003 if (flags & PVO_WIRED) 2004 pvo->pvo_vaddr |= PVO_WIRED; 2005 if (pvo_head != &moea_pvo_kunmanaged) 2006 pvo->pvo_vaddr |= PVO_MANAGED; 2007 if (bootstrap) 2008 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 2009 2010 moea_pte_create(&pvo->pvo_pte.pte, sr, va, pa | pte_lo); 2011 2012 /* 2013 * Add to pmap list 2014 */ 2015 RB_INSERT(pvo_tree, &pm->pmap_pvo, pvo); 2016 2017 /* 2018 * Remember if the list was empty and therefore will be the first 2019 * item. 2020 */ 2021 if (LIST_FIRST(pvo_head) == NULL) 2022 first = 1; 2023 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2024 2025 if (pvo->pvo_vaddr & PVO_WIRED) 2026 pm->pm_stats.wired_count++; 2027 pm->pm_stats.resident_count++; 2028 2029 i = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 2030 KASSERT(i < 8, ("Invalid PTE index")); 2031 if (i >= 0) { 2032 PVO_PTEGIDX_SET(pvo, i); 2033 } else { 2034 panic("moea_pvo_enter: overflow"); 2035 moea_pte_overflow++; 2036 } 2037 mtx_unlock(&moea_table_mutex); 2038 2039 return (first ? ENOENT : 0); 2040} 2041 2042static void 2043moea_pvo_remove(struct pvo_entry *pvo, int pteidx) 2044{ 2045 struct pte *pt; 2046 2047 /* 2048 * If there is an active pte entry, we need to deactivate it (and 2049 * save the ref & cfg bits). 2050 */ 2051 pt = moea_pvo_to_pte(pvo, pteidx); 2052 if (pt != NULL) { 2053 moea_pte_unset(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 2054 mtx_unlock(&moea_table_mutex); 2055 PVO_PTEGIDX_CLR(pvo); 2056 } else { 2057 moea_pte_overflow--; 2058 } 2059 2060 /* 2061 * Update our statistics. 2062 */ 2063 pvo->pvo_pmap->pm_stats.resident_count--; 2064 if (pvo->pvo_vaddr & PVO_WIRED) 2065 pvo->pvo_pmap->pm_stats.wired_count--; 2066 2067 /* 2068 * Save the REF/CHG bits into their cache if the page is managed. 2069 */ 2070 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED) { 2071 struct vm_page *pg; 2072 2073 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 2074 if (pg != NULL) { 2075 moea_attr_save(pg, pvo->pvo_pte.pte.pte_lo & 2076 (PTE_REF | PTE_CHG)); 2077 } 2078 } 2079 2080 /* 2081 * Remove this PVO from the PV and pmap lists. 2082 */ 2083 LIST_REMOVE(pvo, pvo_vlink); 2084 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2085 2086 /* 2087 * Remove this from the overflow list and return it to the pool 2088 * if we aren't going to reuse it. 2089 */ 2090 LIST_REMOVE(pvo, pvo_olink); 2091 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2092 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone : 2093 moea_upvo_zone, pvo); 2094 moea_pvo_entries--; 2095 moea_pvo_remove_calls++; 2096} 2097 2098static __inline int 2099moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 2100{ 2101 int pteidx; 2102 2103 /* 2104 * We can find the actual pte entry without searching by grabbing 2105 * the PTEG index from 3 unused bits in pte_lo[11:9] and by 2106 * noticing the HID bit. 2107 */ 2108 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo); 2109 if (pvo->pvo_pte.pte.pte_hi & PTE_HID) 2110 pteidx ^= moea_pteg_mask * 8; 2111 2112 return (pteidx); 2113} 2114 2115static struct pvo_entry * 2116moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 2117{ 2118 struct pvo_entry *pvo; 2119 int ptegidx; 2120 u_int sr; 2121 2122 va &= ~ADDR_POFF; 2123 sr = va_to_sr(pm->pm_sr, va); 2124 ptegidx = va_to_pteg(sr, va); 2125 2126 mtx_lock(&moea_table_mutex); 2127 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2128 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2129 if (pteidx_p) 2130 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx); 2131 break; 2132 } 2133 } 2134 mtx_unlock(&moea_table_mutex); 2135 2136 return (pvo); 2137} 2138 2139static struct pte * 2140moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 2141{ 2142 struct pte *pt; 2143 2144 /* 2145 * If we haven't been supplied the ptegidx, calculate it. 2146 */ 2147 if (pteidx == -1) { 2148 int ptegidx; 2149 u_int sr; 2150 2151 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr); 2152 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr); 2153 pteidx = moea_pvo_pte_index(pvo, ptegidx); 2154 } 2155 2156 pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7]; 2157 mtx_lock(&moea_table_mutex); 2158 2159 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) { 2160 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no " 2161 "valid pte index", pvo); 2162 } 2163 2164 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) { 2165 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo " 2166 "pvo but no valid pte", pvo); 2167 } 2168 2169 if ((pt->pte_hi ^ (pvo->pvo_pte.pte.pte_hi & ~PTE_VALID)) == PTE_VALID) { 2170 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0) { 2171 panic("moea_pvo_to_pte: pvo %p has valid pte in " 2172 "moea_pteg_table %p but invalid in pvo", pvo, pt); 2173 } 2174 2175 if (((pt->pte_lo ^ pvo->pvo_pte.pte.pte_lo) & ~(PTE_CHG|PTE_REF)) 2176 != 0) { 2177 panic("moea_pvo_to_pte: pvo %p pte does not match " 2178 "pte %p in moea_pteg_table", pvo, pt); 2179 } 2180 2181 mtx_assert(&moea_table_mutex, MA_OWNED); 2182 return (pt); 2183 } 2184 2185 if (pvo->pvo_pte.pte.pte_hi & PTE_VALID) { 2186 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in " 2187 "moea_pteg_table but valid in pvo: %8x, %8x", pvo, pt, pvo->pvo_pte.pte.pte_hi, pt->pte_hi); 2188 } 2189 2190 mtx_unlock(&moea_table_mutex); 2191 return (NULL); 2192} 2193 2194/* 2195 * XXX: THIS STUFF SHOULD BE IN pte.c? 2196 */ 2197int 2198moea_pte_spill(vm_offset_t addr) 2199{ 2200 struct pvo_entry *source_pvo, *victim_pvo; 2201 struct pvo_entry *pvo; 2202 int ptegidx, i, j; 2203 u_int sr; 2204 struct pteg *pteg; 2205 struct pte *pt; 2206 2207 moea_pte_spills++; 2208 2209 sr = mfsrin(addr); 2210 ptegidx = va_to_pteg(sr, addr); 2211 2212 /* 2213 * Have to substitute some entry. Use the primary hash for this. 2214 * Use low bits of timebase as random generator. 2215 */ 2216 pteg = &moea_pteg_table[ptegidx]; 2217 mtx_lock(&moea_table_mutex); 2218 __asm __volatile("mftb %0" : "=r"(i)); 2219 i &= 7; 2220 pt = &pteg->pt[i]; 2221 2222 source_pvo = NULL; 2223 victim_pvo = NULL; 2224 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2225 /* 2226 * We need to find a pvo entry for this address. 2227 */ 2228 if (source_pvo == NULL && 2229 moea_pte_match(&pvo->pvo_pte.pte, sr, addr, 2230 pvo->pvo_pte.pte.pte_hi & PTE_HID)) { 2231 /* 2232 * Now found an entry to be spilled into the pteg. 2233 * The PTE is now valid, so we know it's active. 2234 */ 2235 j = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 2236 2237 if (j >= 0) { 2238 PVO_PTEGIDX_SET(pvo, j); 2239 moea_pte_overflow--; 2240 mtx_unlock(&moea_table_mutex); 2241 return (1); 2242 } 2243 2244 source_pvo = pvo; 2245 2246 if (victim_pvo != NULL) 2247 break; 2248 } 2249 2250 /* 2251 * We also need the pvo entry of the victim we are replacing 2252 * so save the R & C bits of the PTE. 2253 */ 2254 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL && 2255 moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2256 victim_pvo = pvo; 2257 if (source_pvo != NULL) 2258 break; 2259 } 2260 } 2261 2262 if (source_pvo == NULL) { 2263 mtx_unlock(&moea_table_mutex); 2264 return (0); 2265 } 2266 2267 if (victim_pvo == NULL) { 2268 if ((pt->pte_hi & PTE_HID) == 0) 2269 panic("moea_pte_spill: victim p-pte (%p) has no pvo" 2270 "entry", pt); 2271 2272 /* 2273 * If this is a secondary PTE, we need to search it's primary 2274 * pvo bucket for the matching PVO. 2275 */ 2276 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask], 2277 pvo_olink) { 2278 /* 2279 * We also need the pvo entry of the victim we are 2280 * replacing so save the R & C bits of the PTE. 2281 */ 2282 if (moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2283 victim_pvo = pvo; 2284 break; 2285 } 2286 } 2287 2288 if (victim_pvo == NULL) 2289 panic("moea_pte_spill: victim s-pte (%p) has no pvo" 2290 "entry", pt); 2291 } 2292 2293 /* 2294 * We are invalidating the TLB entry for the EA we are replacing even 2295 * though it's valid. If we don't, we lose any ref/chg bit changes 2296 * contained in the TLB entry. 2297 */ 2298 source_pvo->pvo_pte.pte.pte_hi &= ~PTE_HID; 2299 2300 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2301 moea_pte_set(pt, &source_pvo->pvo_pte.pte); 2302 2303 PVO_PTEGIDX_CLR(victim_pvo); 2304 PVO_PTEGIDX_SET(source_pvo, i); 2305 moea_pte_replacements++; 2306 2307 mtx_unlock(&moea_table_mutex); 2308 return (1); 2309} 2310 2311static __inline struct pvo_entry * 2312moea_pte_spillable_ident(u_int ptegidx) 2313{ 2314 struct pte *pt; 2315 struct pvo_entry *pvo_walk, *pvo = NULL; 2316 2317 LIST_FOREACH(pvo_walk, &moea_pvo_table[ptegidx], pvo_olink) { 2318 if (pvo_walk->pvo_vaddr & PVO_WIRED) 2319 continue; 2320 2321 if (!(pvo_walk->pvo_pte.pte.pte_hi & PTE_VALID)) 2322 continue; 2323 2324 pt = moea_pvo_to_pte(pvo_walk, -1); 2325 2326 if (pt == NULL) 2327 continue; 2328 2329 pvo = pvo_walk; 2330 2331 mtx_unlock(&moea_table_mutex); 2332 if (!(pt->pte_lo & PTE_REF)) 2333 return (pvo_walk); 2334 } 2335 2336 return (pvo); 2337} 2338 2339static int 2340moea_pte_insert(u_int ptegidx, struct pte *pvo_pt) 2341{ 2342 struct pte *pt; 2343 struct pvo_entry *victim_pvo; 2344 int i; 2345 int victim_idx; 2346 u_int pteg_bkpidx = ptegidx; 2347 2348 mtx_assert(&moea_table_mutex, MA_OWNED); 2349 2350 /* 2351 * First try primary hash. 2352 */ 2353 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2354 if ((pt->pte_hi & PTE_VALID) == 0) { 2355 pvo_pt->pte_hi &= ~PTE_HID; 2356 moea_pte_set(pt, pvo_pt); 2357 return (i); 2358 } 2359 } 2360 2361 /* 2362 * Now try secondary hash. 2363 */ 2364 ptegidx ^= moea_pteg_mask; 2365 2366 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2367 if ((pt->pte_hi & PTE_VALID) == 0) { 2368 pvo_pt->pte_hi |= PTE_HID; 2369 moea_pte_set(pt, pvo_pt); 2370 return (i); 2371 } 2372 } 2373 2374 /* Try again, but this time try to force a PTE out. */ 2375 ptegidx = pteg_bkpidx; 2376 2377 victim_pvo = moea_pte_spillable_ident(ptegidx); 2378 if (victim_pvo == NULL) { 2379 ptegidx ^= moea_pteg_mask; 2380 victim_pvo = moea_pte_spillable_ident(ptegidx); 2381 } 2382 2383 if (victim_pvo == NULL) { 2384 panic("moea_pte_insert: overflow"); 2385 return (-1); 2386 } 2387 2388 victim_idx = moea_pvo_pte_index(victim_pvo, ptegidx); 2389 2390 if (pteg_bkpidx == ptegidx) 2391 pvo_pt->pte_hi &= ~PTE_HID; 2392 else 2393 pvo_pt->pte_hi |= PTE_HID; 2394 2395 /* 2396 * Synchronize the sacrifice PTE with its PVO, then mark both 2397 * invalid. The PVO will be reused when/if the VM system comes 2398 * here after a fault. 2399 */ 2400 pt = &moea_pteg_table[victim_idx >> 3].pt[victim_idx & 7]; 2401 2402 if (pt->pte_hi != victim_pvo->pvo_pte.pte.pte_hi) 2403 panic("Victim PVO doesn't match PTE! PVO: %8x, PTE: %8x", victim_pvo->pvo_pte.pte.pte_hi, pt->pte_hi); 2404 2405 /* 2406 * Set the new PTE. 2407 */ 2408 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2409 PVO_PTEGIDX_CLR(victim_pvo); 2410 moea_pte_overflow++; 2411 moea_pte_set(pt, pvo_pt); 2412 2413 return (victim_idx & 7); 2414} 2415 2416static boolean_t 2417moea_query_bit(vm_page_t m, int ptebit) 2418{ 2419 struct pvo_entry *pvo; 2420 struct pte *pt; 2421 2422 rw_assert(&pvh_global_lock, RA_WLOCKED); 2423 if (moea_attr_fetch(m) & ptebit) 2424 return (TRUE); 2425 2426 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2427 2428 /* 2429 * See if we saved the bit off. If so, cache it and return 2430 * success. 2431 */ 2432 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2433 moea_attr_save(m, ptebit); 2434 return (TRUE); 2435 } 2436 } 2437 2438 /* 2439 * No luck, now go through the hard part of looking at the PTEs 2440 * themselves. Sync so that any pending REF/CHG bits are flushed to 2441 * the PTEs. 2442 */ 2443 powerpc_sync(); 2444 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2445 2446 /* 2447 * See if this pvo has a valid PTE. if so, fetch the 2448 * REF/CHG bits from the valid PTE. If the appropriate 2449 * ptebit is set, cache it and return success. 2450 */ 2451 pt = moea_pvo_to_pte(pvo, -1); 2452 if (pt != NULL) { 2453 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2454 mtx_unlock(&moea_table_mutex); 2455 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2456 moea_attr_save(m, ptebit); 2457 return (TRUE); 2458 } 2459 } 2460 } 2461 2462 return (FALSE); 2463} 2464 2465static u_int 2466moea_clear_bit(vm_page_t m, int ptebit) 2467{ 2468 u_int count; 2469 struct pvo_entry *pvo; 2470 struct pte *pt; 2471 2472 rw_assert(&pvh_global_lock, RA_WLOCKED); 2473 2474 /* 2475 * Clear the cached value. 2476 */ 2477 moea_attr_clear(m, ptebit); 2478 2479 /* 2480 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2481 * we can reset the right ones). note that since the pvo entries and 2482 * list heads are accessed via BAT0 and are never placed in the page 2483 * table, we don't have to worry about further accesses setting the 2484 * REF/CHG bits. 2485 */ 2486 powerpc_sync(); 2487 2488 /* 2489 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2490 * valid pte clear the ptebit from the valid pte. 2491 */ 2492 count = 0; 2493 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2494 pt = moea_pvo_to_pte(pvo, -1); 2495 if (pt != NULL) { 2496 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2497 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2498 count++; 2499 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit); 2500 } 2501 mtx_unlock(&moea_table_mutex); 2502 } 2503 pvo->pvo_pte.pte.pte_lo &= ~ptebit; 2504 } 2505 2506 return (count); 2507} 2508 2509/* 2510 * Return true if the physical range is encompassed by the battable[idx] 2511 */ 2512static int 2513moea_bat_mapped(int idx, vm_paddr_t pa, vm_size_t size) 2514{ 2515 u_int prot; 2516 u_int32_t start; 2517 u_int32_t end; 2518 u_int32_t bat_ble; 2519 2520 /* 2521 * Return immediately if not a valid mapping 2522 */ 2523 if (!(battable[idx].batu & BAT_Vs)) 2524 return (EINVAL); 2525 2526 /* 2527 * The BAT entry must be cache-inhibited, guarded, and r/w 2528 * so it can function as an i/o page 2529 */ 2530 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW); 2531 if (prot != (BAT_I|BAT_G|BAT_PP_RW)) 2532 return (EPERM); 2533 2534 /* 2535 * The address should be within the BAT range. Assume that the 2536 * start address in the BAT has the correct alignment (thus 2537 * not requiring masking) 2538 */ 2539 start = battable[idx].batl & BAT_PBS; 2540 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03; 2541 end = start | (bat_ble << 15) | 0x7fff; 2542 2543 if ((pa < start) || ((pa + size) > end)) 2544 return (ERANGE); 2545 2546 return (0); 2547} 2548 2549boolean_t 2550moea_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2551{ 2552 int i; 2553 2554 /* 2555 * This currently does not work for entries that 2556 * overlap 256M BAT segments. 2557 */ 2558 2559 for(i = 0; i < 16; i++) 2560 if (moea_bat_mapped(i, pa, size) == 0) 2561 return (0); 2562 2563 return (EFAULT); 2564} 2565 2566/* 2567 * Map a set of physical memory pages into the kernel virtual 2568 * address space. Return a pointer to where it is mapped. This 2569 * routine is intended to be used for mapping device memory, 2570 * NOT real memory. 2571 */ 2572void * 2573moea_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2574{ 2575 2576 return (moea_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT)); 2577} 2578 2579void * 2580moea_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 2581{ 2582 vm_offset_t va, tmpva, ppa, offset; 2583 int i; 2584 2585 ppa = trunc_page(pa); 2586 offset = pa & PAGE_MASK; 2587 size = roundup(offset + size, PAGE_SIZE); 2588 2589 /* 2590 * If the physical address lies within a valid BAT table entry, 2591 * return the 1:1 mapping. This currently doesn't work 2592 * for regions that overlap 256M BAT segments. 2593 */ 2594 for (i = 0; i < 16; i++) { 2595 if (moea_bat_mapped(i, pa, size) == 0) 2596 return ((void *) pa); 2597 } 2598 2599 va = kva_alloc(size); 2600 if (!va) 2601 panic("moea_mapdev: Couldn't alloc kernel virtual memory"); 2602 2603 for (tmpva = va; size > 0;) { 2604 moea_kenter_attr(mmu, tmpva, ppa, ma); 2605 tlbie(tmpva); 2606 size -= PAGE_SIZE; 2607 tmpva += PAGE_SIZE; 2608 ppa += PAGE_SIZE; 2609 } 2610 2611 return ((void *)(va + offset)); 2612} 2613 2614void 2615moea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2616{ 2617 vm_offset_t base, offset; 2618 2619 /* 2620 * If this is outside kernel virtual space, then it's a 2621 * battable entry and doesn't require unmapping 2622 */ 2623 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= virtual_end)) { 2624 base = trunc_page(va); 2625 offset = va & PAGE_MASK; 2626 size = roundup(offset + size, PAGE_SIZE); 2627 kva_free(base, size); 2628 } 2629} 2630 2631static void 2632moea_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2633{ 2634 struct pvo_entry *pvo; 2635 vm_offset_t lim; 2636 vm_paddr_t pa; 2637 vm_size_t len; 2638 2639 PMAP_LOCK(pm); 2640 while (sz > 0) { 2641 lim = round_page(va); 2642 len = MIN(lim - va, sz); 2643 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 2644 if (pvo != NULL) { 2645 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | 2646 (va & ADDR_POFF); 2647 moea_syncicache(pa, len); 2648 } 2649 va += len; 2650 sz -= len; 2651 } 2652 PMAP_UNLOCK(pm); 2653} 2654 2655void 2656moea_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va) 2657{ 2658 2659 *va = (void *)pa; 2660} 2661 2662extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 2663 2664void 2665moea_scan_init(mmu_t mmu) 2666{ 2667 struct pvo_entry *pvo; 2668 vm_offset_t va; 2669 int i; 2670 2671 if (!do_minidump) { 2672 /* Initialize phys. segments for dumpsys(). */ 2673 memset(&dump_map, 0, sizeof(dump_map)); 2674 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 2675 for (i = 0; i < pregions_sz; i++) { 2676 dump_map[i].pa_start = pregions[i].mr_start; 2677 dump_map[i].pa_size = pregions[i].mr_size; 2678 } 2679 return; 2680 } 2681 2682 /* Virtual segments for minidumps: */ 2683 memset(&dump_map, 0, sizeof(dump_map)); 2684 2685 /* 1st: kernel .data and .bss. */ 2686 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 2687 dump_map[0].pa_size = 2688 round_page((uintptr_t)_end) - dump_map[0].pa_start; 2689 2690 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2691 dump_map[1].pa_start = (vm_paddr_t)msgbufp->msg_ptr; 2692 dump_map[1].pa_size = round_page(msgbufp->msg_size); 2693 2694 /* 3rd: kernel VM. */ 2695 va = dump_map[1].pa_start + dump_map[1].pa_size; 2696 /* Find start of next chunk (from va). */ 2697 while (va < virtual_end) { 2698 /* Don't dump the buffer cache. */ 2699 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 2700 va = kmi.buffer_eva; 2701 continue; 2702 } 2703 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 2704 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID)) 2705 break; 2706 va += PAGE_SIZE; 2707 } 2708 if (va < virtual_end) { 2709 dump_map[2].pa_start = va; 2710 va += PAGE_SIZE; 2711 /* Find last page in chunk. */ 2712 while (va < virtual_end) { 2713 /* Don't run into the buffer cache. */ 2714 if (va == kmi.buffer_sva) 2715 break; 2716 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, 2717 NULL); 2718 if (pvo == NULL || 2719 !(pvo->pvo_pte.pte.pte_hi & PTE_VALID)) 2720 break; 2721 va += PAGE_SIZE; 2722 } 2723 dump_map[2].pa_size = va - dump_map[2].pa_start; 2724 } 2725} 2726