1/*- 2 * Copyright (c) 2004 Texas A&M University 3 * All rights reserved. 4 * 5 * Developer: Wm. Daryl Hawkins 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * Intel ICH Watchdog Timer (WDT) driver 31 * 32 * Originally developed by Wm. Daryl Hawkins of Texas A&M 33 * Heavily modified by <des@FreeBSD.org> 34 * 35 * This is a tricky one. The ICH WDT can't be treated as a regular PCI 36 * device as it's actually an integrated function of the ICH LPC interface 37 * bridge. Detection is also awkward, because we can only infer the 38 * presence of the watchdog timer from the fact that the machine has an 39 * ICH chipset, or, on ACPI 2.x systems, by the presence of the 'WDDT' 40 * ACPI table (although this driver does not support the ACPI detection 41 * method). 42 * 43 * There is one slight problem on non-ACPI or ACPI 1.x systems: we have no 44 * way of knowing if the WDT is permanently disabled (either by the BIOS 45 * or in hardware). 46 * 47 * The WDT is programmed through I/O registers in the ACPI I/O space. 48 * Intel swears it's always at offset 0x60, so we use that. 49 * 50 * For details about the ICH WDT, see Intel Application Note AP-725 51 * (document no. 292273-001). The WDT is also described in the individual 52 * chipset datasheets, e.g. Intel82801EB ICH5 / 82801ER ICH5R Datasheet 53 * (document no. 252516-001) sections 9.10 and 9.11. 54 * 55 * ICH6/7/8 support by Takeharu KATO <takeharu1219@ybb.ne.jp> 56 * SoC PMC support by Denir Li <denir.li@cas-well.com> 57 */ 58 59#include <sys/cdefs.h> 60__FBSDID("$FreeBSD: stable/11/sys/dev/ichwd/ichwd.c 359361 2020-03-27 15:26:30Z jhibbits $"); 61 62#include <sys/param.h> 63#include <sys/kernel.h> 64#include <sys/module.h> 65#include <sys/systm.h> 66#include <sys/bus.h> 67#include <machine/bus.h> 68#include <sys/rman.h> 69#include <machine/resource.h> 70#include <sys/watchdog.h> 71 72#include <isa/isavar.h> 73#include <dev/pci/pcivar.h> 74 75#include <dev/ichwd/ichwd.h> 76 77#include <x86/pci_cfgreg.h> 78#include <dev/pci/pcivar.h> 79#include <dev/pci/pci_private.h> 80 81static struct ichwd_device ichwd_devices[] = { 82 { DEVICEID_82801AA, "Intel 82801AA watchdog timer", 1, 1 }, 83 { DEVICEID_82801AB, "Intel 82801AB watchdog timer", 1, 1 }, 84 { DEVICEID_82801BA, "Intel 82801BA watchdog timer", 2, 1 }, 85 { DEVICEID_82801BAM, "Intel 82801BAM watchdog timer", 2, 1 }, 86 { DEVICEID_82801CA, "Intel 82801CA watchdog timer", 3, 1 }, 87 { DEVICEID_82801CAM, "Intel 82801CAM watchdog timer", 3, 1 }, 88 { DEVICEID_82801DB, "Intel 82801DB watchdog timer", 4, 1 }, 89 { DEVICEID_82801DBM, "Intel 82801DBM watchdog timer", 4, 1 }, 90 { DEVICEID_82801E, "Intel 82801E watchdog timer", 5, 1 }, 91 { DEVICEID_82801EB, "Intel 82801EB watchdog timer", 5, 1 }, 92 { DEVICEID_82801EBR, "Intel 82801EB/ER watchdog timer", 5, 1 }, 93 { DEVICEID_6300ESB, "Intel 6300ESB watchdog timer", 5, 1 }, 94 { DEVICEID_82801FBR, "Intel 82801FB/FR watchdog timer", 6, 2 }, 95 { DEVICEID_ICH6M, "Intel ICH6M watchdog timer", 6, 2 }, 96 { DEVICEID_ICH6W, "Intel ICH6W watchdog timer", 6, 2 }, 97 { DEVICEID_ICH7, "Intel ICH7 watchdog timer", 7, 2 }, 98 { DEVICEID_ICH7DH, "Intel ICH7DH watchdog timer", 7, 2 }, 99 { DEVICEID_ICH7M, "Intel ICH7M watchdog timer", 7, 2 }, 100 { DEVICEID_ICH7MDH, "Intel ICH7MDH watchdog timer", 7, 2 }, 101 { DEVICEID_NM10, "Intel NM10 watchdog timer", 7, 2 }, 102 { DEVICEID_ICH8, "Intel ICH8 watchdog timer", 8, 2 }, 103 { DEVICEID_ICH8DH, "Intel ICH8DH watchdog timer", 8, 2 }, 104 { DEVICEID_ICH8DO, "Intel ICH8DO watchdog timer", 8, 2 }, 105 { DEVICEID_ICH8M, "Intel ICH8M watchdog timer", 8, 2 }, 106 { DEVICEID_ICH8ME, "Intel ICH8M-E watchdog timer", 8, 2 }, 107 { DEVICEID_63XXESB, "Intel 63XXESB watchdog timer", 8, 2 }, 108 { DEVICEID_ICH9, "Intel ICH9 watchdog timer", 9, 2 }, 109 { DEVICEID_ICH9DH, "Intel ICH9DH watchdog timer", 9, 2 }, 110 { DEVICEID_ICH9DO, "Intel ICH9DO watchdog timer", 9, 2 }, 111 { DEVICEID_ICH9M, "Intel ICH9M watchdog timer", 9, 2 }, 112 { DEVICEID_ICH9ME, "Intel ICH9M-E watchdog timer", 9, 2 }, 113 { DEVICEID_ICH9R, "Intel ICH9R watchdog timer", 9, 2 }, 114 { DEVICEID_ICH10, "Intel ICH10 watchdog timer", 10, 2 }, 115 { DEVICEID_ICH10D, "Intel ICH10D watchdog timer", 10, 2 }, 116 { DEVICEID_ICH10DO, "Intel ICH10DO watchdog timer", 10, 2 }, 117 { DEVICEID_ICH10R, "Intel ICH10R watchdog timer", 10, 2 }, 118 { DEVICEID_PCH, "Intel PCH watchdog timer", 10, 2 }, 119 { DEVICEID_PCHM, "Intel PCH watchdog timer", 10, 2 }, 120 { DEVICEID_P55, "Intel P55 watchdog timer", 10, 2 }, 121 { DEVICEID_PM55, "Intel PM55 watchdog timer", 10, 2 }, 122 { DEVICEID_H55, "Intel H55 watchdog timer", 10, 2 }, 123 { DEVICEID_QM57, "Intel QM57 watchdog timer", 10, 2 }, 124 { DEVICEID_H57, "Intel H57 watchdog timer", 10, 2 }, 125 { DEVICEID_HM55, "Intel HM55 watchdog timer", 10, 2 }, 126 { DEVICEID_Q57, "Intel Q57 watchdog timer", 10, 2 }, 127 { DEVICEID_HM57, "Intel HM57 watchdog timer", 10, 2 }, 128 { DEVICEID_PCHMSFF, "Intel PCHMSFF watchdog timer", 10, 2 }, 129 { DEVICEID_QS57, "Intel QS57 watchdog timer", 10, 2 }, 130 { DEVICEID_3400, "Intel 3400 watchdog timer", 10, 2 }, 131 { DEVICEID_3420, "Intel 3420 watchdog timer", 10, 2 }, 132 { DEVICEID_3450, "Intel 3450 watchdog timer", 10, 2 }, 133 { DEVICEID_CPT0, "Intel Cougar Point watchdog timer", 10, 2 }, 134 { DEVICEID_CPT1, "Intel Cougar Point watchdog timer", 10, 2 }, 135 { DEVICEID_CPT2, "Intel Cougar Point watchdog timer", 10, 2 }, 136 { DEVICEID_CPT3, "Intel Cougar Point watchdog timer", 10, 2 }, 137 { DEVICEID_CPT4, "Intel Cougar Point watchdog timer", 10, 2 }, 138 { DEVICEID_CPT5, "Intel Cougar Point watchdog timer", 10, 2 }, 139 { DEVICEID_CPT6, "Intel Cougar Point watchdog timer", 10, 2 }, 140 { DEVICEID_CPT7, "Intel Cougar Point watchdog timer", 10, 2 }, 141 { DEVICEID_CPT8, "Intel Cougar Point watchdog timer", 10, 2 }, 142 { DEVICEID_CPT9, "Intel Cougar Point watchdog timer", 10, 2 }, 143 { DEVICEID_CPT10, "Intel Cougar Point watchdog timer", 10, 2 }, 144 { DEVICEID_CPT11, "Intel Cougar Point watchdog timer", 10, 2 }, 145 { DEVICEID_CPT12, "Intel Cougar Point watchdog timer", 10, 2 }, 146 { DEVICEID_CPT13, "Intel Cougar Point watchdog timer", 10, 2 }, 147 { DEVICEID_CPT14, "Intel Cougar Point watchdog timer", 10, 2 }, 148 { DEVICEID_CPT15, "Intel Cougar Point watchdog timer", 10, 2 }, 149 { DEVICEID_CPT16, "Intel Cougar Point watchdog timer", 10, 2 }, 150 { DEVICEID_CPT17, "Intel Cougar Point watchdog timer", 10, 2 }, 151 { DEVICEID_CPT18, "Intel Cougar Point watchdog timer", 10, 2 }, 152 { DEVICEID_CPT19, "Intel Cougar Point watchdog timer", 10, 2 }, 153 { DEVICEID_CPT20, "Intel Cougar Point watchdog timer", 10, 2 }, 154 { DEVICEID_CPT21, "Intel Cougar Point watchdog timer", 10, 2 }, 155 { DEVICEID_CPT22, "Intel Cougar Point watchdog timer", 10, 2 }, 156 { DEVICEID_CPT23, "Intel Cougar Point watchdog timer", 10, 2 }, 157 { DEVICEID_CPT24, "Intel Cougar Point watchdog timer", 10, 2 }, 158 { DEVICEID_CPT25, "Intel Cougar Point watchdog timer", 10, 2 }, 159 { DEVICEID_CPT26, "Intel Cougar Point watchdog timer", 10, 2 }, 160 { DEVICEID_CPT27, "Intel Cougar Point watchdog timer", 10, 2 }, 161 { DEVICEID_CPT28, "Intel Cougar Point watchdog timer", 10, 2 }, 162 { DEVICEID_CPT29, "Intel Cougar Point watchdog timer", 10, 2 }, 163 { DEVICEID_CPT30, "Intel Cougar Point watchdog timer", 10, 2 }, 164 { DEVICEID_CPT31, "Intel Cougar Point watchdog timer", 10, 2 }, 165 { DEVICEID_PATSBURG_LPC1, "Intel Patsburg watchdog timer", 10, 2 }, 166 { DEVICEID_PATSBURG_LPC2, "Intel Patsburg watchdog timer", 10, 2 }, 167 { DEVICEID_PPT0, "Intel Panther Point watchdog timer", 10, 2 }, 168 { DEVICEID_PPT1, "Intel Panther Point watchdog timer", 10, 2 }, 169 { DEVICEID_PPT2, "Intel Panther Point watchdog timer", 10, 2 }, 170 { DEVICEID_PPT3, "Intel Panther Point watchdog timer", 10, 2 }, 171 { DEVICEID_PPT4, "Intel Panther Point watchdog timer", 10, 2 }, 172 { DEVICEID_PPT5, "Intel Panther Point watchdog timer", 10, 2 }, 173 { DEVICEID_PPT6, "Intel Panther Point watchdog timer", 10, 2 }, 174 { DEVICEID_PPT7, "Intel Panther Point watchdog timer", 10, 2 }, 175 { DEVICEID_PPT8, "Intel Panther Point watchdog timer", 10, 2 }, 176 { DEVICEID_PPT9, "Intel Panther Point watchdog timer", 10, 2 }, 177 { DEVICEID_PPT10, "Intel Panther Point watchdog timer", 10, 2 }, 178 { DEVICEID_PPT11, "Intel Panther Point watchdog timer", 10, 2 }, 179 { DEVICEID_PPT12, "Intel Panther Point watchdog timer", 10, 2 }, 180 { DEVICEID_PPT13, "Intel Panther Point watchdog timer", 10, 2 }, 181 { DEVICEID_PPT14, "Intel Panther Point watchdog timer", 10, 2 }, 182 { DEVICEID_PPT15, "Intel Panther Point watchdog timer", 10, 2 }, 183 { DEVICEID_PPT16, "Intel Panther Point watchdog timer", 10, 2 }, 184 { DEVICEID_PPT17, "Intel Panther Point watchdog timer", 10, 2 }, 185 { DEVICEID_PPT18, "Intel Panther Point watchdog timer", 10, 2 }, 186 { DEVICEID_PPT19, "Intel Panther Point watchdog timer", 10, 2 }, 187 { DEVICEID_PPT20, "Intel Panther Point watchdog timer", 10, 2 }, 188 { DEVICEID_PPT21, "Intel Panther Point watchdog timer", 10, 2 }, 189 { DEVICEID_PPT22, "Intel Panther Point watchdog timer", 10, 2 }, 190 { DEVICEID_PPT23, "Intel Panther Point watchdog timer", 10, 2 }, 191 { DEVICEID_PPT24, "Intel Panther Point watchdog timer", 10, 2 }, 192 { DEVICEID_PPT25, "Intel Panther Point watchdog timer", 10, 2 }, 193 { DEVICEID_PPT26, "Intel Panther Point watchdog timer", 10, 2 }, 194 { DEVICEID_PPT27, "Intel Panther Point watchdog timer", 10, 2 }, 195 { DEVICEID_PPT28, "Intel Panther Point watchdog timer", 10, 2 }, 196 { DEVICEID_PPT29, "Intel Panther Point watchdog timer", 10, 2 }, 197 { DEVICEID_PPT30, "Intel Panther Point watchdog timer", 10, 2 }, 198 { DEVICEID_PPT31, "Intel Panther Point watchdog timer", 10, 2 }, 199 { DEVICEID_LPT0, "Intel Lynx Point watchdog timer", 10, 2 }, 200 { DEVICEID_LPT1, "Intel Lynx Point watchdog timer", 10, 2 }, 201 { DEVICEID_LPT2, "Intel Lynx Point watchdog timer", 10, 2 }, 202 { DEVICEID_LPT3, "Intel Lynx Point watchdog timer", 10, 2 }, 203 { DEVICEID_LPT4, "Intel Lynx Point watchdog timer", 10, 2 }, 204 { DEVICEID_LPT5, "Intel Lynx Point watchdog timer", 10, 2 }, 205 { DEVICEID_LPT6, "Intel Lynx Point watchdog timer", 10, 2 }, 206 { DEVICEID_LPT7, "Intel Lynx Point watchdog timer", 10, 2 }, 207 { DEVICEID_LPT8, "Intel Lynx Point watchdog timer", 10, 2 }, 208 { DEVICEID_LPT9, "Intel Lynx Point watchdog timer", 10, 2 }, 209 { DEVICEID_LPT10, "Intel Lynx Point watchdog timer", 10, 2 }, 210 { DEVICEID_LPT11, "Intel Lynx Point watchdog timer", 10, 2 }, 211 { DEVICEID_LPT12, "Intel Lynx Point watchdog timer", 10, 2 }, 212 { DEVICEID_LPT13, "Intel Lynx Point watchdog timer", 10, 2 }, 213 { DEVICEID_LPT14, "Intel Lynx Point watchdog timer", 10, 2 }, 214 { DEVICEID_LPT15, "Intel Lynx Point watchdog timer", 10, 2 }, 215 { DEVICEID_LPT16, "Intel Lynx Point watchdog timer", 10, 2 }, 216 { DEVICEID_LPT17, "Intel Lynx Point watchdog timer", 10, 2 }, 217 { DEVICEID_LPT18, "Intel Lynx Point watchdog timer", 10, 2 }, 218 { DEVICEID_LPT19, "Intel Lynx Point watchdog timer", 10, 2 }, 219 { DEVICEID_LPT20, "Intel Lynx Point watchdog timer", 10, 2 }, 220 { DEVICEID_LPT21, "Intel Lynx Point watchdog timer", 10, 2 }, 221 { DEVICEID_LPT22, "Intel Lynx Point watchdog timer", 10, 2 }, 222 { DEVICEID_LPT23, "Intel Lynx Point watchdog timer", 10, 2 }, 223 { DEVICEID_LPT24, "Intel Lynx Point watchdog timer", 10, 2 }, 224 { DEVICEID_LPT25, "Intel Lynx Point watchdog timer", 10, 2 }, 225 { DEVICEID_LPT26, "Intel Lynx Point watchdog timer", 10, 2 }, 226 { DEVICEID_LPT27, "Intel Lynx Point watchdog timer", 10, 2 }, 227 { DEVICEID_LPT28, "Intel Lynx Point watchdog timer", 10, 2 }, 228 { DEVICEID_LPT29, "Intel Lynx Point watchdog timer", 10, 2 }, 229 { DEVICEID_LPT30, "Intel Lynx Point watchdog timer", 10, 2 }, 230 { DEVICEID_LPT31, "Intel Lynx Point watchdog timer", 10, 2 }, 231 { DEVICEID_WCPT1, "Intel Wildcat Point watchdog timer", 10, 2 }, 232 { DEVICEID_WCPT2, "Intel Wildcat Point watchdog timer", 10, 2 }, 233 { DEVICEID_WCPT3, "Intel Wildcat Point watchdog timer", 10, 2 }, 234 { DEVICEID_WCPT4, "Intel Wildcat Point watchdog timer", 10, 2 }, 235 { DEVICEID_WCPT6, "Intel Wildcat Point watchdog timer", 10, 2 }, 236 { DEVICEID_WBG0, "Intel Wellsburg watchdog timer", 10, 2 }, 237 { DEVICEID_WBG1, "Intel Wellsburg watchdog timer", 10, 2 }, 238 { DEVICEID_WBG2, "Intel Wellsburg watchdog timer", 10, 2 }, 239 { DEVICEID_WBG3, "Intel Wellsburg watchdog timer", 10, 2 }, 240 { DEVICEID_WBG4, "Intel Wellsburg watchdog timer", 10, 2 }, 241 { DEVICEID_WBG5, "Intel Wellsburg watchdog timer", 10, 2 }, 242 { DEVICEID_WBG6, "Intel Wellsburg watchdog timer", 10, 2 }, 243 { DEVICEID_WBG7, "Intel Wellsburg watchdog timer", 10, 2 }, 244 { DEVICEID_WBG8, "Intel Wellsburg watchdog timer", 10, 2 }, 245 { DEVICEID_WBG9, "Intel Wellsburg watchdog timer", 10, 2 }, 246 { DEVICEID_WBG10, "Intel Wellsburg watchdog timer", 10, 2 }, 247 { DEVICEID_WBG11, "Intel Wellsburg watchdog timer", 10, 2 }, 248 { DEVICEID_WBG12, "Intel Wellsburg watchdog timer", 10, 2 }, 249 { DEVICEID_WBG13, "Intel Wellsburg watchdog timer", 10, 2 }, 250 { DEVICEID_WBG14, "Intel Wellsburg watchdog timer", 10, 2 }, 251 { DEVICEID_WBG15, "Intel Wellsburg watchdog timer", 10, 2 }, 252 { DEVICEID_WBG16, "Intel Wellsburg watchdog timer", 10, 2 }, 253 { DEVICEID_WBG17, "Intel Wellsburg watchdog timer", 10, 2 }, 254 { DEVICEID_WBG18, "Intel Wellsburg watchdog timer", 10, 2 }, 255 { DEVICEID_WBG19, "Intel Wellsburg watchdog timer", 10, 2 }, 256 { DEVICEID_WBG20, "Intel Wellsburg watchdog timer", 10, 2 }, 257 { DEVICEID_WBG21, "Intel Wellsburg watchdog timer", 10, 2 }, 258 { DEVICEID_WBG22, "Intel Wellsburg watchdog timer", 10, 2 }, 259 { DEVICEID_WBG23, "Intel Wellsburg watchdog timer", 10, 2 }, 260 { DEVICEID_WBG24, "Intel Wellsburg watchdog timer", 10, 2 }, 261 { DEVICEID_WBG25, "Intel Wellsburg watchdog timer", 10, 2 }, 262 { DEVICEID_WBG26, "Intel Wellsburg watchdog timer", 10, 2 }, 263 { DEVICEID_WBG27, "Intel Wellsburg watchdog timer", 10, 2 }, 264 { DEVICEID_WBG28, "Intel Wellsburg watchdog timer", 10, 2 }, 265 { DEVICEID_WBG29, "Intel Wellsburg watchdog timer", 10, 2 }, 266 { DEVICEID_WBG30, "Intel Wellsburg watchdog timer", 10, 2 }, 267 { DEVICEID_WBG31, "Intel Wellsburg watchdog timer", 10, 2 }, 268 { DEVICEID_LPT_LP0, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 269 { DEVICEID_LPT_LP1, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 270 { DEVICEID_LPT_LP2, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 271 { DEVICEID_LPT_LP3, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 272 { DEVICEID_LPT_LP4, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 273 { DEVICEID_LPT_LP5, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 274 { DEVICEID_LPT_LP6, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 275 { DEVICEID_LPT_LP7, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 276 { DEVICEID_WCPT_LP1, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, 277 { DEVICEID_WCPT_LP2, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, 278 { DEVICEID_WCPT_LP3, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, 279 { DEVICEID_WCPT_LP5, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, 280 { DEVICEID_WCPT_LP6, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, 281 { DEVICEID_WCPT_LP7, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, 282 { DEVICEID_WCPT_LP9, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, 283 { DEVICEID_DH89XXCC_LPC, "Intel DH89xxCC watchdog timer", 10, 2 }, 284 { DEVICEID_COLETOCRK_LPC, "Intel Coleto Creek watchdog timer", 10, 2 }, 285 { DEVICEID_AVN0, "Intel Avoton/Rangeley SoC watchdog timer",10, 3 }, 286 { DEVICEID_AVN1, "Intel Avoton/Rangeley SoC watchdog timer",10, 3 }, 287 { DEVICEID_AVN2, "Intel Avoton/Rangeley SoC watchdog timer",10, 3 }, 288 { DEVICEID_AVN3, "Intel Avoton/Rangeley SoC watchdog timer",10, 3 }, 289 { DEVICEID_BAYTRAIL, "Intel Bay Trail SoC watchdog timer", 10, 3 }, 290 { DEVICEID_BRASWELL, "Intel Braswell SoC watchdog timer", 10, 3 }, 291 { 0, NULL, 0, 0 }, 292}; 293 294static struct ichwd_device ichwd_smb_devices[] = { 295 { DEVICEID_LEWISBURG_SMB, "Lewisburg watchdog timer", 10, 4 }, 296 { DEVICEID_SRPTLP_SMB, "Sunrise Point-LP watchdog timer", 10, 4 }, 297 { DEVICEID_C3000, "Intel Atom C3000 watchdog timer", 10, 4 }, 298 { 0, NULL, 0, 0 }, 299}; 300 301static devclass_t ichwd_devclass; 302 303#define ichwd_read_tco_1(sc, off) \ 304 bus_read_1((sc)->tco_res, (off)) 305#define ichwd_read_tco_2(sc, off) \ 306 bus_read_2((sc)->tco_res, (off)) 307#define ichwd_read_tco_4(sc, off) \ 308 bus_read_4((sc)->tco_res, (off)) 309#define ichwd_read_smi_4(sc, off) \ 310 bus_read_4((sc)->smi_res, (off)) 311#define ichwd_read_gcs_4(sc, off) \ 312 bus_read_4((sc)->gcs_res, (off)) 313/* NB: TCO version 3 devices use the gcs_res resource for the PMC register. */ 314#define ichwd_read_pmc_4(sc, off) \ 315 bus_read_4((sc)->gcs_res, (off)) 316#define ichwd_read_gc_4(sc, off) \ 317 bus_read_4((sc)->gc_res, (off)) 318 319#define ichwd_write_tco_1(sc, off, val) \ 320 bus_write_1((sc)->tco_res, (off), (val)) 321#define ichwd_write_tco_2(sc, off, val) \ 322 bus_write_2((sc)->tco_res, (off), (val)) 323#define ichwd_write_tco_4(sc, off, val) \ 324 bus_write_4((sc)->tco_res, (off), (val)) 325#define ichwd_write_smi_4(sc, off, val) \ 326 bus_write_4((sc)->smi_res, (off), (val)) 327#define ichwd_write_gcs_4(sc, off, val) \ 328 bus_write_4((sc)->gcs_res, (off), (val)) 329/* NB: TCO version 3 devices use the gcs_res resource for the PMC register. */ 330#define ichwd_write_pmc_4(sc, off, val) \ 331 bus_write_4((sc)->gcs_res, (off), (val)) 332#define ichwd_write_gc_4(sc, off, val) \ 333 bus_write_4((sc)->gc_res, (off), (val)) 334 335#define ichwd_verbose_printf(dev, ...) \ 336 do { \ 337 if (bootverbose) \ 338 device_printf(dev, __VA_ARGS__);\ 339 } while (0) 340 341/* 342 * Disable the watchdog timeout SMI handler. 343 * 344 * Apparently, some BIOSes install handlers that reset or disable the 345 * watchdog timer instead of resetting the system, so we disable the SMI 346 * (by clearing the SMI_TCO_EN bit of the SMI_EN register) to prevent this 347 * from happening. 348 */ 349static __inline void 350ichwd_smi_disable(struct ichwd_softc *sc) 351{ 352 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) & ~SMI_TCO_EN); 353} 354 355/* 356 * Enable the watchdog timeout SMI handler. See above for details. 357 */ 358static __inline void 359ichwd_smi_enable(struct ichwd_softc *sc) 360{ 361 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) | SMI_TCO_EN); 362} 363 364/* 365 * Check if the watchdog SMI triggering is enabled. 366 */ 367static __inline int 368ichwd_smi_is_enabled(struct ichwd_softc *sc) 369{ 370 return ((ichwd_read_smi_4(sc, SMI_EN) & SMI_TCO_EN) != 0); 371} 372 373/* 374 * Reset the watchdog status bits. 375 */ 376static __inline void 377ichwd_sts_reset(struct ichwd_softc *sc) 378{ 379 /* 380 * The watchdog status bits are set to 1 by the hardware to 381 * indicate various conditions. They can be cleared by software 382 * by writing a 1, not a 0. 383 */ 384 ichwd_write_tco_2(sc, TCO1_STS, TCO_TIMEOUT); 385 /* 386 * According to Intel's docs, clearing SECOND_TO_STS and BOOT_STS must 387 * be done in two separate operations. 388 */ 389 ichwd_write_tco_2(sc, TCO2_STS, TCO_SECOND_TO_STS); 390 if (sc->tco_version < 4) 391 ichwd_write_tco_2(sc, TCO2_STS, TCO_BOOT_STS); 392} 393 394/* 395 * Enable the watchdog timer by clearing the TCO_TMR_HALT bit in the 396 * TCO1_CNT register. This is complicated by the need to preserve bit 9 397 * of that same register, and the requirement that all other bits must be 398 * written back as zero. 399 */ 400static __inline void 401ichwd_tmr_enable(struct ichwd_softc *sc) 402{ 403 uint16_t cnt; 404 405 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE; 406 ichwd_write_tco_2(sc, TCO1_CNT, cnt & ~TCO_TMR_HALT); 407 sc->active = 1; 408 ichwd_verbose_printf(sc->device, "timer enabled\n"); 409} 410 411/* 412 * Disable the watchdog timer. See above for details. 413 */ 414static __inline void 415ichwd_tmr_disable(struct ichwd_softc *sc) 416{ 417 uint16_t cnt; 418 419 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE; 420 ichwd_write_tco_2(sc, TCO1_CNT, cnt | TCO_TMR_HALT); 421 sc->active = 0; 422 ichwd_verbose_printf(sc->device, "timer disabled\n"); 423} 424 425/* 426 * Reload the watchdog timer: writing anything to any of the lower five 427 * bits of the TCO_RLD register reloads the timer from the last value 428 * written to TCO_TMR. 429 */ 430static __inline void 431ichwd_tmr_reload(struct ichwd_softc *sc) 432{ 433 if (sc->tco_version == 1) 434 ichwd_write_tco_1(sc, TCO_RLD, 1); 435 else 436 ichwd_write_tco_2(sc, TCO_RLD, 1); 437} 438 439/* 440 * Set the initial timeout value. Note that this must always be followed 441 * by a reload. 442 */ 443static __inline void 444ichwd_tmr_set(struct ichwd_softc *sc, unsigned int timeout) 445{ 446 447 if (timeout < TCO_RLD_TMR_MIN) 448 timeout = TCO_RLD_TMR_MIN; 449 450 if (sc->tco_version == 1) { 451 uint8_t tmr_val8 = ichwd_read_tco_1(sc, TCO_TMR1); 452 453 tmr_val8 &= (~TCO_RLD1_TMR_MAX & 0xff); 454 if (timeout > TCO_RLD1_TMR_MAX) 455 timeout = TCO_RLD1_TMR_MAX; 456 tmr_val8 |= timeout; 457 ichwd_write_tco_1(sc, TCO_TMR1, tmr_val8); 458 } else { 459 uint16_t tmr_val16 = ichwd_read_tco_2(sc, TCO_TMR2); 460 461 tmr_val16 &= (~TCO_RLD2_TMR_MAX & 0xffff); 462 if (timeout > TCO_RLD2_TMR_MAX) 463 timeout = TCO_RLD2_TMR_MAX; 464 tmr_val16 |= timeout; 465 ichwd_write_tco_2(sc, TCO_TMR2, tmr_val16); 466 } 467 468 sc->timeout = timeout; 469 470 ichwd_verbose_printf(sc->device, "timeout set to %u ticks\n", timeout); 471} 472 473static __inline int 474ichwd_clear_noreboot(struct ichwd_softc *sc) 475{ 476 uint32_t status; 477 int rc = 0; 478 479 /* try to clear the NO_REBOOT bit */ 480 switch (sc->tco_version) { 481 case 1: 482 status = pci_read_config(sc->ich, ICH_GEN_STA, 1); 483 status &= ~ICH_GEN_STA_NO_REBOOT; 484 pci_write_config(sc->ich, ICH_GEN_STA, status, 1); 485 status = pci_read_config(sc->ich, ICH_GEN_STA, 1); 486 if (status & ICH_GEN_STA_NO_REBOOT) 487 rc = EIO; 488 break; 489 case 2: 490 status = ichwd_read_gcs_4(sc, 0); 491 status &= ~ICH_GCS_NO_REBOOT; 492 ichwd_write_gcs_4(sc, 0, status); 493 status = ichwd_read_gcs_4(sc, 0); 494 if (status & ICH_GCS_NO_REBOOT) 495 rc = EIO; 496 break; 497 case 3: 498 status = ichwd_read_pmc_4(sc, 0); 499 status &= ~ICH_PMC_NO_REBOOT; 500 ichwd_write_pmc_4(sc, 0, status); 501 status = ichwd_read_pmc_4(sc, 0); 502 if (status & ICH_PMC_NO_REBOOT) 503 rc = EIO; 504 break; 505 case 4: 506 status = ichwd_read_gc_4(sc, 0); 507 status &= ~SMB_GC_NO_REBOOT; 508 ichwd_write_gc_4(sc, 0, status); 509 status = ichwd_read_gc_4(sc, 0); 510 if (status & SMB_GC_NO_REBOOT) 511 rc = EIO; 512 break; 513 default: 514 ichwd_verbose_printf(sc->device, 515 "Unknown TCO Version: %d, can't set NO_REBOOT.\n", 516 sc->tco_version); 517 break; 518 } 519 520 if (rc) 521 device_printf(sc->device, 522 "ICH WDT present but disabled in BIOS or hardware\n"); 523 524 return (rc); 525} 526 527/* 528 * Watchdog event handler - called by the framework to enable or disable 529 * the watchdog or change the initial timeout value. 530 */ 531static void 532ichwd_event(void *arg, unsigned int cmd, int *error) 533{ 534 struct ichwd_softc *sc = arg; 535 unsigned int timeout; 536 537 /* convert from power-of-two-ns to WDT ticks */ 538 cmd &= WD_INTERVAL; 539 540 if (sc->tco_version == 3) { 541 timeout = ((uint64_t)1 << cmd) / ICHWD_TCO_V3_TICK; 542 } else { 543 timeout = ((uint64_t)1 << cmd) / ICHWD_TICK; 544 } 545 546 if (cmd) { 547 if (!sc->active) 548 ichwd_tmr_enable(sc); 549 if (timeout != sc->timeout) 550 ichwd_tmr_set(sc, timeout); 551 ichwd_tmr_reload(sc); 552 *error = 0; 553 } else { 554 if (sc->active) 555 ichwd_tmr_disable(sc); 556 } 557} 558 559static device_t 560ichwd_find_ich_lpc_bridge(device_t isa, struct ichwd_device **id_p) 561{ 562 struct ichwd_device *id; 563 device_t isab, pci; 564 uint16_t devid; 565 566 /* Check whether parent ISA bridge looks familiar. */ 567 isab = device_get_parent(isa); 568 pci = device_get_parent(isab); 569 if (pci == NULL || device_get_devclass(pci) != devclass_find("pci")) 570 return (NULL); 571 if (pci_get_vendor(isab) != VENDORID_INTEL) 572 return (NULL); 573 devid = pci_get_device(isab); 574 for (id = ichwd_devices; id->desc != NULL; ++id) { 575 if (devid == id->device) { 576 if (id_p != NULL) 577 *id_p = id; 578 return (isab); 579 } 580 } 581 582 return (NULL); 583} 584 585static device_t 586ichwd_find_smb_dev(device_t isa, struct ichwd_device **id_p) 587{ 588 struct ichwd_device *id; 589 device_t isab, smb; 590 uint16_t devid; 591 592 /* 593 * Check if SMBus controller provides TCO configuration. 594 * The controller's device and function are fixed and we expect 595 * it to be on the same bus as ISA bridge. 596 */ 597 isab = device_get_parent(isa); 598 smb = pci_find_dbsf(pci_get_domain(isab), pci_get_bus(isab), 31, 4); 599 if (smb == NULL) 600 return (NULL); 601 if (pci_get_vendor(smb) != VENDORID_INTEL) 602 return (NULL); 603 devid = pci_get_device(smb); 604 for (id = ichwd_smb_devices; id->desc != NULL; ++id) { 605 if (devid == id->device) { 606 if (id_p != NULL) 607 *id_p = id; 608 return (smb); 609 } 610 } 611 612 return (NULL); 613} 614 615/* 616 * Look for an ICH LPC interface bridge. If one is found, register an 617 * ichwd device. There can be only one. 618 */ 619static void 620ichwd_identify(driver_t *driver, device_t parent) 621{ 622 struct ichwd_device *id_p; 623 device_t ich, smb; 624 device_t dev; 625 uint64_t base_address64; 626 uint32_t base_address; 627 uint32_t ctl; 628 int rc; 629 630 ich = ichwd_find_ich_lpc_bridge(parent, &id_p); 631 if (ich == NULL) { 632 smb = ichwd_find_smb_dev(parent, &id_p); 633 if (smb == NULL) 634 return; 635 } 636 637 KASSERT(id_p->tco_version >= 1, 638 ("unexpected TCO version %d", id_p->tco_version)); 639 KASSERT(id_p->tco_version != 4 || smb != NULL, 640 ("could not find PCI SMBus device for TCOv4")); 641 KASSERT(id_p->tco_version >= 4 || ich != NULL, 642 ("could not find PCI LPC bridge device for TCOv1-3")); 643 644 /* good, add child to bus */ 645 if ((dev = device_find_child(parent, driver->name, 0)) == NULL) 646 dev = BUS_ADD_CHILD(parent, 0, driver->name, 0); 647 648 if (dev == NULL) 649 return; 650 651 switch (id_p->tco_version) { 652 case 1: 653 break; 654 case 2: 655 /* get RCBA (root complex base address) */ 656 base_address = pci_read_config(ich, ICH_RCBA, 4); 657 rc = bus_set_resource(ich, SYS_RES_MEMORY, 0, 658 (base_address & 0xffffc000) + ICH_GCS_OFFSET, 659 ICH_GCS_SIZE); 660 if (rc) 661 ichwd_verbose_printf(dev, 662 "Can not set TCO v%d memory resource for RCBA\n", 663 id_p->tco_version); 664 break; 665 case 3: 666 /* get PBASE (Power Management Controller base address) */ 667 base_address = pci_read_config(ich, ICH_PBASE, 4); 668 rc = bus_set_resource(ich, SYS_RES_MEMORY, 0, 669 (base_address & 0xfffffe00) + ICH_PMC_OFFSET, 670 ICH_PMC_SIZE); 671 if (rc) 672 ichwd_verbose_printf(dev, 673 "Can not set TCO v%d memory resource for PBASE\n", 674 id_p->tco_version); 675 break; 676 case 4: 677 /* Get TCO base address. */ 678 ctl = pci_read_config(smb, ICH_TCOCTL, 4); 679 if ((ctl & ICH_TCOCTL_TCO_BASE_EN) == 0) { 680 ichwd_verbose_printf(dev, 681 "TCO v%d decoding is not enabled\n", 682 id_p->tco_version); 683 break; 684 } 685 base_address = pci_read_config(smb, ICH_TCOBASE, 4); 686 rc = bus_set_resource(dev, SYS_RES_IOPORT, 0, 687 base_address & ICH_TCOBASE_ADDRMASK, ICH_TCOBASE_SIZE); 688 if (rc != 0) { 689 ichwd_verbose_printf(dev, 690 "Can not set TCO v%d I/O resource (err = %d)\n", 691 id_p->tco_version, rc); 692 } 693 694 /* 695 * Unhide Primary to Sideband Bridge (P2SB) PCI device, so that 696 * we can discover the base address of Private Configuration 697 * Space via the bridge's BAR. 698 * Then hide back the bridge. 699 */ 700 pci_cfgregwrite(0, 31, 1, 0xe1, 0, 1); 701 base_address64 = pci_cfgregread(0, 31, 1, SBREG_BAR + 4, 4); 702 base_address64 <<= 32; 703 base_address64 |= pci_cfgregread(0, 31, 1, SBREG_BAR, 4); 704 base_address64 &= ~0xfull; 705 pci_cfgregwrite(0, 31, 1, 0xe1, 1, 1); 706 707 /* 708 * No Reboot bit is in General Control register, offset 0xc, 709 * within the SMBus target port, ID 0xc6. 710 */ 711 base_address64 += PCR_REG_OFF(SMB_PORT_ID, SMB_GC_REG); 712 rc = bus_set_resource(dev, SYS_RES_MEMORY, 1, base_address64, 713 SMB_GC_SIZE); 714 if (rc != 0) { 715 ichwd_verbose_printf(dev, 716 "Can not set TCO v%d PCR I/O resource (err = %d)\n", 717 id_p->tco_version, rc); 718 } 719 720 break; 721 default: 722 ichwd_verbose_printf(dev, 723 "Can not set unknown TCO v%d memory resource for unknown base address\n", 724 id_p->tco_version); 725 break; 726 } 727} 728 729static int 730ichwd_probe(device_t dev) 731{ 732 struct ichwd_device *id_p; 733 734 /* Do not claim some ISA PnP device by accident. */ 735 if (isa_get_logicalid(dev) != 0) 736 return (ENXIO); 737 738 if (ichwd_find_ich_lpc_bridge(device_get_parent(dev), &id_p) == NULL && 739 ichwd_find_smb_dev(device_get_parent(dev), &id_p) == NULL) 740 return (ENXIO); 741 742 device_set_desc_copy(dev, id_p->desc); 743 return (0); 744} 745 746static int 747ichwd_smb_attach(device_t dev) 748{ 749 struct ichwd_softc *sc; 750 struct ichwd_device *id_p; 751 device_t isab, pmdev; 752 device_t smb; 753 uint32_t acpi_base; 754 755 sc = device_get_softc(dev); 756 smb = ichwd_find_smb_dev(device_get_parent(dev), &id_p); 757 if (smb == NULL) 758 return (ENXIO); 759 760 sc->ich_version = id_p->ich_version; 761 sc->tco_version = id_p->tco_version; 762 763 /* Allocate TCO control I/O register space. */ 764 sc->tco_rid = 0; 765 sc->tco_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->tco_rid, 766 RF_ACTIVE | RF_SHAREABLE); 767 if (sc->tco_res == NULL) { 768 device_printf(dev, "unable to reserve TCO registers\n"); 769 return (ENXIO); 770 } 771 772 /* 773 * Allocate General Control I/O register in PCH 774 * Private Configuration Space (PCR). 775 */ 776 sc->gc_rid = 1; 777 sc->gc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->gc_rid, 778 RF_ACTIVE | RF_SHAREABLE); 779 if (sc->gc_res == NULL) { 780 device_printf(dev, "unable to reserve hidden P2SB registers\n"); 781 return (ENXIO); 782 } 783 784 /* Get ACPI base address. */ 785 isab = device_get_parent(device_get_parent(dev)); 786 pmdev = pci_find_dbsf(pci_get_domain(isab), pci_get_bus(isab), 31, 2); 787 if (pmdev == NULL) { 788 device_printf(dev, "unable to find Power Management device\n"); 789 return (ENXIO); 790 } 791 acpi_base = pci_read_config(pmdev, ICH_PMBASE, 4) & 0xffffff00; 792 if (acpi_base == 0) { 793 device_printf(dev, "ACPI base address is not set\n"); 794 return (ENXIO); 795 } 796 797 /* Allocate SMI control I/O register space. */ 798 sc->smi_rid = 2; 799 sc->smi_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->smi_rid, 800 acpi_base + SMI_BASE, acpi_base + SMI_BASE + SMI_LEN - 1, SMI_LEN, 801 RF_ACTIVE | RF_SHAREABLE); 802 if (sc->smi_res == NULL) { 803 device_printf(dev, "unable to reserve SMI registers\n"); 804 return (ENXIO); 805 } 806 807 return (0); 808} 809 810static int 811ichwd_lpc_attach(device_t dev) 812{ 813 struct ichwd_softc *sc; 814 struct ichwd_device *id_p; 815 device_t ich; 816 unsigned int pmbase = 0; 817 818 sc = device_get_softc(dev); 819 820 ich = ichwd_find_ich_lpc_bridge(device_get_parent(dev), &id_p); 821 if (ich == NULL) 822 return (ENXIO); 823 824 sc->ich = ich; 825 sc->ich_version = id_p->ich_version; 826 sc->tco_version = id_p->tco_version; 827 828 /* get ACPI base address */ 829 pmbase = pci_read_config(ich, ICH_PMBASE, 2) & ICH_PMBASE_MASK; 830 if (pmbase == 0) { 831 device_printf(dev, "ICH PMBASE register is empty\n"); 832 return (ENXIO); 833 } 834 835 /* allocate I/O register space */ 836 sc->smi_rid = 0; 837 sc->smi_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->smi_rid, 838 pmbase + SMI_BASE, pmbase + SMI_BASE + SMI_LEN - 1, SMI_LEN, 839 RF_ACTIVE | RF_SHAREABLE); 840 if (sc->smi_res == NULL) { 841 device_printf(dev, "unable to reserve SMI registers\n"); 842 return (ENXIO); 843 } 844 845 sc->tco_rid = 1; 846 sc->tco_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->tco_rid, 847 pmbase + TCO_BASE, pmbase + TCO_BASE + TCO_LEN - 1, TCO_LEN, 848 RF_ACTIVE | RF_SHAREABLE); 849 if (sc->tco_res == NULL) { 850 device_printf(dev, "unable to reserve TCO registers\n"); 851 return (ENXIO); 852 } 853 854 sc->gcs_rid = 0; 855 if (sc->tco_version >= 2) { 856 sc->gcs_res = bus_alloc_resource_any(ich, SYS_RES_MEMORY, 857 &sc->gcs_rid, RF_ACTIVE|RF_SHAREABLE); 858 if (sc->gcs_res == NULL) { 859 device_printf(dev, "unable to reserve GCS registers\n"); 860 return (ENXIO); 861 } 862 } 863 864 return (0); 865} 866 867static int 868ichwd_attach(device_t dev) 869{ 870 struct ichwd_softc *sc; 871 872 sc = device_get_softc(dev); 873 sc->device = dev; 874 875 if (ichwd_lpc_attach(dev) != 0 && ichwd_smb_attach(dev) != 0) 876 goto fail; 877 878 if (ichwd_clear_noreboot(sc) != 0) 879 goto fail; 880 881 /* 882 * Determine if we are coming up after a watchdog-induced reset. Some 883 * BIOSes may clear this bit at bootup, preventing us from reporting 884 * this case on such systems. We clear this bit in ichwd_sts_reset(). 885 */ 886 if ((ichwd_read_tco_2(sc, TCO2_STS) & TCO_SECOND_TO_STS) != 0) 887 device_printf(dev, 888 "resuming after hardware watchdog timeout\n"); 889 890 /* reset the watchdog status registers */ 891 ichwd_sts_reset(sc); 892 893 /* make sure the WDT starts out inactive */ 894 ichwd_tmr_disable(sc); 895 896 /* register the watchdog event handler */ 897 sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, ichwd_event, sc, 0); 898 899 /* disable the SMI handler */ 900 sc->smi_enabled = ichwd_smi_is_enabled(sc); 901 ichwd_smi_disable(sc); 902 903 return (0); 904 fail: 905 sc = device_get_softc(dev); 906 if (sc->tco_res != NULL) 907 bus_release_resource(dev, SYS_RES_IOPORT, 908 sc->tco_rid, sc->tco_res); 909 if (sc->smi_res != NULL) 910 bus_release_resource(dev, SYS_RES_IOPORT, 911 sc->smi_rid, sc->smi_res); 912 if (sc->gcs_res != NULL) 913 bus_release_resource(sc->ich, SYS_RES_MEMORY, 914 sc->gcs_rid, sc->gcs_res); 915 if (sc->gc_res != NULL) 916 bus_release_resource(dev, SYS_RES_MEMORY, 917 sc->gc_rid, sc->gc_res); 918 919 return (ENXIO); 920} 921 922static int 923ichwd_detach(device_t dev) 924{ 925 struct ichwd_softc *sc; 926 927 sc = device_get_softc(dev); 928 929 /* halt the watchdog timer */ 930 if (sc->active) 931 ichwd_tmr_disable(sc); 932 933 /* enable the SMI handler */ 934 if (sc->smi_enabled != 0) 935 ichwd_smi_enable(sc); 936 937 /* deregister event handler */ 938 if (sc->ev_tag != NULL) 939 EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag); 940 sc->ev_tag = NULL; 941 942 /* reset the watchdog status registers */ 943 ichwd_sts_reset(sc); 944 945 /* deallocate I/O register space */ 946 bus_release_resource(dev, SYS_RES_IOPORT, sc->tco_rid, sc->tco_res); 947 bus_release_resource(dev, SYS_RES_IOPORT, sc->smi_rid, sc->smi_res); 948 949 /* deallocate memory resource */ 950 if (sc->gcs_res) 951 bus_release_resource(sc->ich, SYS_RES_MEMORY, sc->gcs_rid, 952 sc->gcs_res); 953 if (sc->gc_res) 954 bus_release_resource(dev, SYS_RES_MEMORY, sc->gc_rid, 955 sc->gc_res); 956 957 return (0); 958} 959 960static device_method_t ichwd_methods[] = { 961 DEVMETHOD(device_identify, ichwd_identify), 962 DEVMETHOD(device_probe, ichwd_probe), 963 DEVMETHOD(device_attach, ichwd_attach), 964 DEVMETHOD(device_detach, ichwd_detach), 965 DEVMETHOD(device_shutdown, ichwd_detach), 966 {0,0} 967}; 968 969static driver_t ichwd_driver = { 970 "ichwd", 971 ichwd_methods, 972 sizeof(struct ichwd_softc), 973}; 974 975DRIVER_MODULE(ichwd, isa, ichwd_driver, ichwd_devclass, NULL, NULL); 976