1/*- 2 * Copyright (c) 2003-2008, Joseph Koshy 3 * Copyright (c) 2007 The FreeBSD Foundation 4 * All rights reserved. 5 * 6 * Portions of this software were developed by A. Joseph Koshy under 7 * sponsorship from the FreeBSD Foundation and Google, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD$ 31 */ 32 33#ifndef _SYS_PMC_H_ 34#define _SYS_PMC_H_ 35 36#include <dev/hwpmc/pmc_events.h> 37 38#include <machine/pmc_mdep.h> 39#include <machine/profile.h> 40 41#define PMC_MODULE_NAME "hwpmc" 42#define PMC_NAME_MAX 64 /* HW counter name size */ 43#define PMC_CLASS_MAX 8 /* max #classes of PMCs per-system */ 44 45/* 46 * Kernel<->userland API version number [MMmmpppp] 47 * 48 * Major numbers are to be incremented when an incompatible change to 49 * the ABI occurs that older clients will not be able to handle. 50 * 51 * Minor numbers are incremented when a backwards compatible change 52 * occurs that allows older correct programs to run unchanged. For 53 * example, when support for a new PMC type is added. 54 * 55 * The patch version is incremented for every bug fix. 56 */ 57#define PMC_VERSION_MAJOR 0x03 58#define PMC_VERSION_MINOR 0x01 59#define PMC_VERSION_PATCH 0x0000 60 61#define PMC_VERSION (PMC_VERSION_MAJOR << 24 | \ 62 PMC_VERSION_MINOR << 16 | PMC_VERSION_PATCH) 63 64/* 65 * Kinds of CPUs known. 66 * 67 * We keep track of CPU variants that need to be distinguished in 68 * some way for PMC operations. CPU names are grouped by manufacturer 69 * and numbered sparsely in order to minimize changes to the ABI involved 70 * when new CPUs are added. 71 */ 72 73#define __PMC_CPUS() \ 74 __PMC_CPU(AMD_K7, 0x00, "AMD K7") \ 75 __PMC_CPU(AMD_K8, 0x01, "AMD K8") \ 76 __PMC_CPU(INTEL_P5, 0x80, "Intel Pentium") \ 77 __PMC_CPU(INTEL_P6, 0x81, "Intel Pentium Pro") \ 78 __PMC_CPU(INTEL_CL, 0x82, "Intel Celeron") \ 79 __PMC_CPU(INTEL_PII, 0x83, "Intel Pentium II") \ 80 __PMC_CPU(INTEL_PIII, 0x84, "Intel Pentium III") \ 81 __PMC_CPU(INTEL_PM, 0x85, "Intel Pentium M") \ 82 __PMC_CPU(INTEL_PIV, 0x86, "Intel Pentium IV") \ 83 __PMC_CPU(INTEL_CORE, 0x87, "Intel Core Solo/Duo") \ 84 __PMC_CPU(INTEL_CORE2, 0x88, "Intel Core2") \ 85 __PMC_CPU(INTEL_CORE2EXTREME, 0x89, "Intel Core2 Extreme") \ 86 __PMC_CPU(INTEL_ATOM, 0x8A, "Intel Atom") \ 87 __PMC_CPU(INTEL_COREI7, 0x8B, "Intel Core i7") \ 88 __PMC_CPU(INTEL_WESTMERE, 0x8C, "Intel Westmere") \ 89 __PMC_CPU(INTEL_SANDYBRIDGE, 0x8D, "Intel Sandy Bridge") \ 90 __PMC_CPU(INTEL_IVYBRIDGE, 0x8E, "Intel Ivy Bridge") \ 91 __PMC_CPU(INTEL_SANDYBRIDGE_XEON, 0x8F, "Intel Sandy Bridge Xeon") \ 92 __PMC_CPU(INTEL_IVYBRIDGE_XEON, 0x90, "Intel Ivy Bridge Xeon") \ 93 __PMC_CPU(INTEL_HASWELL, 0x91, "Intel Haswell") \ 94 __PMC_CPU(INTEL_ATOM_SILVERMONT, 0x92, "Intel Atom Silvermont") \ 95 __PMC_CPU(INTEL_NEHALEM_EX, 0x93, "Intel Nehalem Xeon 7500") \ 96 __PMC_CPU(INTEL_WESTMERE_EX, 0x94, "Intel Westmere Xeon E7") \ 97 __PMC_CPU(INTEL_XSCALE, 0x100, "Intel XScale") \ 98 __PMC_CPU(MIPS_24K, 0x200, "MIPS 24K") \ 99 __PMC_CPU(MIPS_OCTEON, 0x201, "Cavium Octeon") \ 100 __PMC_CPU(PPC_7450, 0x300, "PowerPC MPC7450") \ 101 __PMC_CPU(PPC_970, 0x380, "IBM PowerPC 970") \ 102 __PMC_CPU(GENERIC, 0x400, "Generic") 103 104enum pmc_cputype { 105#undef __PMC_CPU 106#define __PMC_CPU(S,V,D) PMC_CPU_##S = V, 107 __PMC_CPUS() 108}; 109 110#define PMC_CPU_FIRST PMC_CPU_AMD_K7 111#define PMC_CPU_LAST PMC_CPU_GENERIC 112 113/* 114 * Classes of PMCs 115 */ 116 117#define __PMC_CLASSES() \ 118 __PMC_CLASS(TSC) /* CPU Timestamp counter */ \ 119 __PMC_CLASS(K7) /* AMD K7 performance counters */ \ 120 __PMC_CLASS(K8) /* AMD K8 performance counters */ \ 121 __PMC_CLASS(P5) /* Intel Pentium counters */ \ 122 __PMC_CLASS(P6) /* Intel Pentium Pro counters */ \ 123 __PMC_CLASS(P4) /* Intel Pentium-IV counters */ \ 124 __PMC_CLASS(IAF) /* Intel Core2/Atom, fixed function */ \ 125 __PMC_CLASS(IAP) /* Intel Core...Atom, programmable */ \ 126 __PMC_CLASS(UCF) /* Intel Uncore fixed function */ \ 127 __PMC_CLASS(UCP) /* Intel Uncore programmable */ \ 128 __PMC_CLASS(XSCALE) /* Intel XScale counters */ \ 129 __PMC_CLASS(MIPS24K) /* MIPS 24K */ \ 130 __PMC_CLASS(OCTEON) /* Cavium Octeon */ \ 131 __PMC_CLASS(PPC7450) /* Motorola MPC7450 class */ \ 132 __PMC_CLASS(PPC970) /* IBM PowerPC 970 class */ \ 133 __PMC_CLASS(SOFT) /* Software events */ 134 135enum pmc_class { 136#undef __PMC_CLASS 137#define __PMC_CLASS(N) PMC_CLASS_##N , 138 __PMC_CLASSES() 139}; 140 141#define PMC_CLASS_FIRST PMC_CLASS_TSC 142#define PMC_CLASS_LAST PMC_CLASS_SOFT 143 144/* 145 * A PMC can be in the following states: 146 * 147 * Hardware states: 148 * DISABLED -- administratively prohibited from being used. 149 * FREE -- HW available for use 150 * Software states: 151 * ALLOCATED -- allocated 152 * STOPPED -- allocated, but not counting events 153 * RUNNING -- allocated, and in operation; 'pm_runcount' 154 * holds the number of CPUs using this PMC at 155 * a given instant 156 * DELETED -- being destroyed 157 */ 158 159#define __PMC_HWSTATES() \ 160 __PMC_STATE(DISABLED) \ 161 __PMC_STATE(FREE) 162 163#define __PMC_SWSTATES() \ 164 __PMC_STATE(ALLOCATED) \ 165 __PMC_STATE(STOPPED) \ 166 __PMC_STATE(RUNNING) \ 167 __PMC_STATE(DELETED) 168 169#define __PMC_STATES() \ 170 __PMC_HWSTATES() \ 171 __PMC_SWSTATES() 172 173enum pmc_state { 174#undef __PMC_STATE 175#define __PMC_STATE(S) PMC_STATE_##S, 176 __PMC_STATES() 177 __PMC_STATE(MAX) 178}; 179 180#define PMC_STATE_FIRST PMC_STATE_DISABLED 181#define PMC_STATE_LAST PMC_STATE_DELETED 182 183/* 184 * An allocated PMC may used as a 'global' counter or as a 185 * 'thread-private' one. Each such mode of use can be in either 186 * statistical sampling mode or in counting mode. Thus a PMC in use 187 * 188 * SS i.e., SYSTEM STATISTICAL -- system-wide statistical profiling 189 * SC i.e., SYSTEM COUNTER -- system-wide counting mode 190 * TS i.e., THREAD STATISTICAL -- thread virtual, statistical profiling 191 * TC i.e., THREAD COUNTER -- thread virtual, counting mode 192 * 193 * Statistical profiling modes rely on the PMC periodically delivering 194 * a interrupt to the CPU (when the configured number of events have 195 * been measured), so the PMC must have the ability to generate 196 * interrupts. 197 * 198 * In counting modes, the PMC counts its configured events, with the 199 * value of the PMC being read whenever needed by its owner process. 200 * 201 * The thread specific modes "virtualize" the PMCs -- the PMCs appear 202 * to be thread private and count events only when the profiled thread 203 * actually executes on the CPU. 204 * 205 * The system-wide "global" modes keep the PMCs running all the time 206 * and are used to measure the behaviour of the whole system. 207 */ 208 209#define __PMC_MODES() \ 210 __PMC_MODE(SS, 0) \ 211 __PMC_MODE(SC, 1) \ 212 __PMC_MODE(TS, 2) \ 213 __PMC_MODE(TC, 3) 214 215enum pmc_mode { 216#undef __PMC_MODE 217#define __PMC_MODE(M,N) PMC_MODE_##M = N, 218 __PMC_MODES() 219}; 220 221#define PMC_MODE_FIRST PMC_MODE_SS 222#define PMC_MODE_LAST PMC_MODE_TC 223 224#define PMC_IS_COUNTING_MODE(mode) \ 225 ((mode) == PMC_MODE_SC || (mode) == PMC_MODE_TC) 226#define PMC_IS_SYSTEM_MODE(mode) \ 227 ((mode) == PMC_MODE_SS || (mode) == PMC_MODE_SC) 228#define PMC_IS_SAMPLING_MODE(mode) \ 229 ((mode) == PMC_MODE_SS || (mode) == PMC_MODE_TS) 230#define PMC_IS_VIRTUAL_MODE(mode) \ 231 ((mode) == PMC_MODE_TS || (mode) == PMC_MODE_TC) 232 233/* 234 * PMC row disposition 235 */ 236 237#define __PMC_DISPOSITIONS(N) \ 238 __PMC_DISP(STANDALONE) /* global/disabled counters */ \ 239 __PMC_DISP(FREE) /* free/available */ \ 240 __PMC_DISP(THREAD) /* thread-virtual PMCs */ \ 241 __PMC_DISP(UNKNOWN) /* sentinel */ 242 243enum pmc_disp { 244#undef __PMC_DISP 245#define __PMC_DISP(D) PMC_DISP_##D , 246 __PMC_DISPOSITIONS() 247}; 248 249#define PMC_DISP_FIRST PMC_DISP_STANDALONE 250#define PMC_DISP_LAST PMC_DISP_THREAD 251 252/* 253 * Counter capabilities 254 * 255 * __PMC_CAPS(NAME, VALUE, DESCRIPTION) 256 */ 257 258#define __PMC_CAPS() \ 259 __PMC_CAP(INTERRUPT, 0, "generate interrupts") \ 260 __PMC_CAP(USER, 1, "count user-mode events") \ 261 __PMC_CAP(SYSTEM, 2, "count system-mode events") \ 262 __PMC_CAP(EDGE, 3, "do edge detection of events") \ 263 __PMC_CAP(THRESHOLD, 4, "ignore events below a threshold") \ 264 __PMC_CAP(READ, 5, "read PMC counter") \ 265 __PMC_CAP(WRITE, 6, "reprogram PMC counter") \ 266 __PMC_CAP(INVERT, 7, "invert comparision sense") \ 267 __PMC_CAP(QUALIFIER, 8, "further qualify monitored events") \ 268 __PMC_CAP(PRECISE, 9, "perform precise sampling") \ 269 __PMC_CAP(TAGGING, 10, "tag upstream events") \ 270 __PMC_CAP(CASCADE, 11, "cascade counters") 271 272enum pmc_caps 273{ 274#undef __PMC_CAP 275#define __PMC_CAP(NAME, VALUE, DESCR) PMC_CAP_##NAME = (1 << VALUE) , 276 __PMC_CAPS() 277}; 278 279#define PMC_CAP_FIRST PMC_CAP_INTERRUPT 280#define PMC_CAP_LAST PMC_CAP_CASCADE 281 282/* 283 * PMC Event Numbers 284 * 285 * These are generated from the definitions in "dev/hwpmc/pmc_events.h". 286 */ 287 288enum pmc_event { 289#undef __PMC_EV 290#undef __PMC_EV_BLOCK 291#define __PMC_EV_BLOCK(C,V) PMC_EV_ ## C ## __BLOCK_START = (V) - 1 , 292#define __PMC_EV(C,N) PMC_EV_ ## C ## _ ## N , 293 __PMC_EVENTS() 294}; 295 296/* 297 * PMC SYSCALL INTERFACE 298 */ 299 300/* 301 * "PMC_OPS" -- these are the commands recognized by the kernel 302 * module, and are used when performing a system call from userland. 303 */ 304#define __PMC_OPS() \ 305 __PMC_OP(CONFIGURELOG, "Set log file") \ 306 __PMC_OP(FLUSHLOG, "Flush log file") \ 307 __PMC_OP(GETCPUINFO, "Get system CPU information") \ 308 __PMC_OP(GETDRIVERSTATS, "Get driver statistics") \ 309 __PMC_OP(GETMODULEVERSION, "Get module version") \ 310 __PMC_OP(GETPMCINFO, "Get per-cpu PMC information") \ 311 __PMC_OP(PMCADMIN, "Set PMC state") \ 312 __PMC_OP(PMCALLOCATE, "Allocate and configure a PMC") \ 313 __PMC_OP(PMCATTACH, "Attach a PMC to a process") \ 314 __PMC_OP(PMCDETACH, "Detach a PMC from a process") \ 315 __PMC_OP(PMCGETMSR, "Get a PMC's hardware address") \ 316 __PMC_OP(PMCRELEASE, "Release a PMC") \ 317 __PMC_OP(PMCRW, "Read/Set a PMC") \ 318 __PMC_OP(PMCSETCOUNT, "Set initial count/sampling rate") \ 319 __PMC_OP(PMCSTART, "Start a PMC") \ 320 __PMC_OP(PMCSTOP, "Stop a PMC") \ 321 __PMC_OP(WRITELOG, "Write a cookie to the log file") \ 322 __PMC_OP(CLOSELOG, "Close log file") \ 323 __PMC_OP(GETDYNEVENTINFO, "Get dynamic events list") 324 325 326enum pmc_ops { 327#undef __PMC_OP 328#define __PMC_OP(N, D) PMC_OP_##N, 329 __PMC_OPS() 330}; 331 332 333/* 334 * Flags used in operations on PMCs. 335 */ 336 337#define PMC_F_FORCE 0x00000001 /*OP ADMIN force operation */ 338#define PMC_F_DESCENDANTS 0x00000002 /*OP ALLOCATE track descendants */ 339#define PMC_F_LOG_PROCCSW 0x00000004 /*OP ALLOCATE track ctx switches */ 340#define PMC_F_LOG_PROCEXIT 0x00000008 /*OP ALLOCATE log proc exits */ 341#define PMC_F_NEWVALUE 0x00000010 /*OP RW write new value */ 342#define PMC_F_OLDVALUE 0x00000020 /*OP RW get old value */ 343#define PMC_F_KGMON 0x00000040 /*OP ALLOCATE kgmon(8) profiling */ 344/* V2 API */ 345#define PMC_F_CALLCHAIN 0x00000080 /*OP ALLOCATE capture callchains */ 346 347/* internal flags */ 348#define PMC_F_ATTACHED_TO_OWNER 0x00010000 /*attached to owner*/ 349#define PMC_F_NEEDS_LOGFILE 0x00020000 /*needs log file */ 350#define PMC_F_ATTACH_DONE 0x00040000 /*attached at least once */ 351 352#define PMC_CALLCHAIN_DEPTH_MAX 32 353 354#define PMC_CC_F_USERSPACE 0x01 /*userspace callchain*/ 355 356/* 357 * Cookies used to denote allocated PMCs, and the values of PMCs. 358 */ 359 360typedef uint32_t pmc_id_t; 361typedef uint64_t pmc_value_t; 362 363#define PMC_ID_INVALID (~ (pmc_id_t) 0) 364 365/* 366 * PMC IDs have the following format: 367 * 368 * +--------+----------+-----------+-----------+ 369 * | CPU | PMC MODE | PMC CLASS | ROW INDEX | 370 * +--------+----------+-----------+-----------+ 371 * 372 * where each field is 8 bits wide. Field 'CPU' is set to the 373 * requested CPU for system-wide PMCs or PMC_CPU_ANY for process-mode 374 * PMCs. Field 'PMC MODE' is the allocated PMC mode. Field 'PMC 375 * CLASS' is the class of the PMC. Field 'ROW INDEX' is the row index 376 * for the PMC. 377 * 378 * The 'ROW INDEX' ranges over 0..NWPMCS where NHWPMCS is the total 379 * number of hardware PMCs on this cpu. 380 */ 381 382 383#define PMC_ID_TO_ROWINDEX(ID) ((ID) & 0xFF) 384#define PMC_ID_TO_CLASS(ID) (((ID) & 0xFF00) >> 8) 385#define PMC_ID_TO_MODE(ID) (((ID) & 0xFF0000) >> 16) 386#define PMC_ID_TO_CPU(ID) (((ID) & 0xFF000000) >> 24) 387#define PMC_ID_MAKE_ID(CPU,MODE,CLASS,ROWINDEX) \ 388 ((((CPU) & 0xFF) << 24) | (((MODE) & 0xFF) << 16) | \ 389 (((CLASS) & 0xFF) << 8) | ((ROWINDEX) & 0xFF)) 390 391/* 392 * Data structures for system calls supported by the pmc driver. 393 */ 394 395/* 396 * OP PMCALLOCATE 397 * 398 * Allocate a PMC on the named CPU. 399 */ 400 401#define PMC_CPU_ANY ~0 402 403struct pmc_op_pmcallocate { 404 uint32_t pm_caps; /* PMC_CAP_* */ 405 uint32_t pm_cpu; /* CPU number or PMC_CPU_ANY */ 406 enum pmc_class pm_class; /* class of PMC desired */ 407 enum pmc_event pm_ev; /* [enum pmc_event] desired */ 408 uint32_t pm_flags; /* additional modifiers PMC_F_* */ 409 enum pmc_mode pm_mode; /* desired mode */ 410 pmc_id_t pm_pmcid; /* [return] process pmc id */ 411 412 union pmc_md_op_pmcallocate pm_md; /* MD layer extensions */ 413}; 414 415/* 416 * OP PMCADMIN 417 * 418 * Set the administrative state (i.e., whether enabled or disabled) of 419 * a PMC 'pm_pmc' on CPU 'pm_cpu'. Note that 'pm_pmc' specifies an 420 * absolute PMC number and need not have been first allocated by the 421 * calling process. 422 */ 423 424struct pmc_op_pmcadmin { 425 int pm_cpu; /* CPU# */ 426 uint32_t pm_flags; /* flags */ 427 int pm_pmc; /* PMC# */ 428 enum pmc_state pm_state; /* desired state */ 429}; 430 431/* 432 * OP PMCATTACH / OP PMCDETACH 433 * 434 * Attach/detach a PMC and a process. 435 */ 436 437struct pmc_op_pmcattach { 438 pmc_id_t pm_pmc; /* PMC to attach to */ 439 pid_t pm_pid; /* target process */ 440}; 441 442/* 443 * OP PMCSETCOUNT 444 * 445 * Set the sampling rate (i.e., the reload count) for statistical counters. 446 * 'pm_pmcid' need to have been previously allocated using PMCALLOCATE. 447 */ 448 449struct pmc_op_pmcsetcount { 450 pmc_value_t pm_count; /* initial/sample count */ 451 pmc_id_t pm_pmcid; /* PMC id to set */ 452}; 453 454 455/* 456 * OP PMCRW 457 * 458 * Read the value of a PMC named by 'pm_pmcid'. 'pm_pmcid' needs 459 * to have been previously allocated using PMCALLOCATE. 460 */ 461 462 463struct pmc_op_pmcrw { 464 uint32_t pm_flags; /* PMC_F_{OLD,NEW}VALUE*/ 465 pmc_id_t pm_pmcid; /* pmc id */ 466 pmc_value_t pm_value; /* new&returned value */ 467}; 468 469 470/* 471 * OP GETPMCINFO 472 * 473 * retrieve PMC state for a named CPU. The caller is expected to 474 * allocate 'npmc' * 'struct pmc_info' bytes of space for the return 475 * values. 476 */ 477 478struct pmc_info { 479 char pm_name[PMC_NAME_MAX]; /* pmc name */ 480 enum pmc_class pm_class; /* enum pmc_class */ 481 int pm_enabled; /* whether enabled */ 482 enum pmc_disp pm_rowdisp; /* FREE, THREAD or STANDLONE */ 483 pid_t pm_ownerpid; /* owner, or -1 */ 484 enum pmc_mode pm_mode; /* current mode [enum pmc_mode] */ 485 enum pmc_event pm_event; /* current event */ 486 uint32_t pm_flags; /* current flags */ 487 pmc_value_t pm_reloadcount; /* sampling counters only */ 488}; 489 490struct pmc_op_getpmcinfo { 491 int32_t pm_cpu; /* 0 <= cpu < mp_maxid */ 492 struct pmc_info pm_pmcs[]; /* space for 'npmc' structures */ 493}; 494 495 496/* 497 * OP GETCPUINFO 498 * 499 * Retrieve system CPU information. 500 */ 501 502 503struct pmc_classinfo { 504 enum pmc_class pm_class; /* class id */ 505 uint32_t pm_caps; /* counter capabilities */ 506 uint32_t pm_width; /* width of the PMC */ 507 uint32_t pm_num; /* number of PMCs in class */ 508}; 509 510struct pmc_op_getcpuinfo { 511 enum pmc_cputype pm_cputype; /* what kind of CPU */ 512 uint32_t pm_ncpu; /* max CPU number */ 513 uint32_t pm_npmc; /* #PMCs per CPU */ 514 uint32_t pm_nclass; /* #classes of PMCs */ 515 struct pmc_classinfo pm_classes[PMC_CLASS_MAX]; 516}; 517 518/* 519 * OP CONFIGURELOG 520 * 521 * Configure a log file for writing system-wide statistics to. 522 */ 523 524struct pmc_op_configurelog { 525 int pm_flags; 526 int pm_logfd; /* logfile fd (or -1) */ 527}; 528 529/* 530 * OP GETDRIVERSTATS 531 * 532 * Retrieve pmc(4) driver-wide statistics. 533 */ 534 535struct pmc_op_getdriverstats { 536 int pm_intr_ignored; /* #interrupts ignored */ 537 int pm_intr_processed; /* #interrupts processed */ 538 int pm_intr_bufferfull; /* #interrupts with ENOSPC */ 539 int pm_syscalls; /* #syscalls */ 540 int pm_syscall_errors; /* #syscalls with errors */ 541 int pm_buffer_requests; /* #buffer requests */ 542 int pm_buffer_requests_failed; /* #failed buffer requests */ 543 int pm_log_sweeps; /* #sample buffer processing passes */ 544}; 545 546/* 547 * OP RELEASE / OP START / OP STOP 548 * 549 * Simple operations on a PMC id. 550 */ 551 552struct pmc_op_simple { 553 pmc_id_t pm_pmcid; 554}; 555 556/* 557 * OP WRITELOG 558 * 559 * Flush the current log buffer and write 4 bytes of user data to it. 560 */ 561 562struct pmc_op_writelog { 563 uint32_t pm_userdata; 564}; 565 566/* 567 * OP GETMSR 568 * 569 * Retrieve the machine specific address assoicated with the allocated 570 * PMC. This number can be used subsequently with a read-performance-counter 571 * instruction. 572 */ 573 574struct pmc_op_getmsr { 575 uint32_t pm_msr; /* machine specific address */ 576 pmc_id_t pm_pmcid; /* allocated pmc id */ 577}; 578 579/* 580 * OP GETDYNEVENTINFO 581 * 582 * Retrieve a PMC dynamic class events list. 583 */ 584 585struct pmc_dyn_event_descr { 586 char pm_ev_name[PMC_NAME_MAX]; 587 enum pmc_event pm_ev_code; 588}; 589 590struct pmc_op_getdyneventinfo { 591 enum pmc_class pm_class; 592 unsigned int pm_nevent; 593 struct pmc_dyn_event_descr pm_events[PMC_EV_DYN_COUNT]; 594}; 595 596#ifdef _KERNEL 597 598#include <sys/malloc.h> 599#include <sys/sysctl.h> 600 601#include <machine/frame.h> 602 603#define PMC_HASH_SIZE 1024 604#define PMC_MTXPOOL_SIZE 2048 605#define PMC_LOG_BUFFER_SIZE 4 606#define PMC_NLOGBUFFERS 1024 607#define PMC_NSAMPLES 1024 608#define PMC_CALLCHAIN_DEPTH 16 609 610#define PMC_SYSCTL_NAME_PREFIX "kern." PMC_MODULE_NAME "." 611 612/* 613 * Locking keys 614 * 615 * (b) - pmc_bufferlist_mtx (spin lock) 616 * (k) - pmc_kthread_mtx (sleep lock) 617 * (o) - po->po_mtx (spin lock) 618 */ 619 620/* 621 * PMC commands 622 */ 623 624struct pmc_syscall_args { 625 register_t pmop_code; /* one of PMC_OP_* */ 626 void *pmop_data; /* syscall parameter */ 627}; 628 629/* 630 * Interface to processor specific s1tuff 631 */ 632 633/* 634 * struct pmc_descr 635 * 636 * Machine independent (i.e., the common parts) of a human readable 637 * PMC description. 638 */ 639 640struct pmc_descr { 641 char pd_name[PMC_NAME_MAX]; /* name */ 642 uint32_t pd_caps; /* capabilities */ 643 enum pmc_class pd_class; /* class of the PMC */ 644 uint32_t pd_width; /* width in bits */ 645}; 646 647/* 648 * struct pmc_target 649 * 650 * This structure records all the target processes associated with a 651 * PMC. 652 */ 653 654struct pmc_target { 655 LIST_ENTRY(pmc_target) pt_next; 656 struct pmc_process *pt_process; /* target descriptor */ 657}; 658 659/* 660 * struct pmc 661 * 662 * Describes each allocated PMC. 663 * 664 * Each PMC has precisely one owner, namely the process that allocated 665 * the PMC. 666 * 667 * A PMC may be attached to multiple target processes. The 668 * 'pm_targets' field links all the target processes being monitored 669 * by this PMC. 670 * 671 * The 'pm_savedvalue' field is protected by a mutex. 672 * 673 * On a multi-cpu machine, multiple target threads associated with a 674 * process-virtual PMC could be concurrently executing on different 675 * CPUs. The 'pm_runcount' field is atomically incremented every time 676 * the PMC gets scheduled on a CPU and atomically decremented when it 677 * get descheduled. Deletion of a PMC is only permitted when this 678 * field is '0'. 679 * 680 */ 681 682struct pmc { 683 LIST_HEAD(,pmc_target) pm_targets; /* list of target processes */ 684 LIST_ENTRY(pmc) pm_next; /* owner's list */ 685 686 /* 687 * System-wide PMCs are allocated on a CPU and are not moved 688 * around. For system-wide PMCs we record the CPU the PMC was 689 * allocated on in the 'CPU' field of the pmc ID. 690 * 691 * Virtual PMCs run on whichever CPU is currently executing 692 * their targets' threads. For these PMCs we need to save 693 * their current PMC counter values when they are taken off 694 * CPU. 695 */ 696 697 union { 698 pmc_value_t pm_savedvalue; /* Virtual PMCS */ 699 } pm_gv; 700 701 /* 702 * For sampling mode PMCs, we keep track of the PMC's "reload 703 * count", which is the counter value to be loaded in when 704 * arming the PMC for the next counting session. For counting 705 * modes on PMCs that are read-only (e.g., the x86 TSC), we 706 * keep track of the initial value at the start of 707 * counting-mode operation. 708 */ 709 710 union { 711 pmc_value_t pm_reloadcount; /* sampling PMC modes */ 712 pmc_value_t pm_initial; /* counting PMC modes */ 713 } pm_sc; 714 715 uint32_t pm_stalled; /* marks stalled sampling PMCs */ 716 uint32_t pm_caps; /* PMC capabilities */ 717 enum pmc_event pm_event; /* event being measured */ 718 uint32_t pm_flags; /* additional flags PMC_F_... */ 719 struct pmc_owner *pm_owner; /* owner thread state */ 720 int pm_runcount; /* #cpus currently on */ 721 enum pmc_state pm_state; /* current PMC state */ 722 723 /* 724 * The PMC ID field encodes the row-index for the PMC, its 725 * mode, class and the CPU# associated with the PMC. 726 */ 727 728 pmc_id_t pm_id; /* allocated PMC id */ 729 730 /* md extensions */ 731 union pmc_md_pmc pm_md; 732}; 733 734/* 735 * Accessor macros for 'struct pmc' 736 */ 737 738#define PMC_TO_MODE(P) PMC_ID_TO_MODE((P)->pm_id) 739#define PMC_TO_CLASS(P) PMC_ID_TO_CLASS((P)->pm_id) 740#define PMC_TO_ROWINDEX(P) PMC_ID_TO_ROWINDEX((P)->pm_id) 741#define PMC_TO_CPU(P) PMC_ID_TO_CPU((P)->pm_id) 742 743 744/* 745 * struct pmc_process 746 * 747 * Record a 'target' process being profiled. 748 * 749 * The target process being profiled could be different from the owner 750 * process which allocated the PMCs. Each target process descriptor 751 * is associated with NHWPMC 'struct pmc *' pointers. Each PMC at a 752 * given hardware row-index 'n' will use slot 'n' of the 'pp_pmcs[]' 753 * array. The size of this structure is thus PMC architecture 754 * dependent. 755 * 756 */ 757 758struct pmc_targetstate { 759 struct pmc *pp_pmc; /* target PMC */ 760 pmc_value_t pp_pmcval; /* per-process value */ 761}; 762 763struct pmc_process { 764 LIST_ENTRY(pmc_process) pp_next; /* hash chain */ 765 int pp_refcnt; /* reference count */ 766 uint32_t pp_flags; /* flags PMC_PP_* */ 767 struct proc *pp_proc; /* target thread */ 768 struct pmc_targetstate pp_pmcs[]; /* NHWPMCs */ 769}; 770 771#define PMC_PP_ENABLE_MSR_ACCESS 0x00000001 772 773/* 774 * struct pmc_owner 775 * 776 * We associate a PMC with an 'owner' process. 777 * 778 * A process can be associated with 0..NCPUS*NHWPMC PMCs during its 779 * lifetime, where NCPUS is the numbers of CPUS in the system and 780 * NHWPMC is the number of hardware PMCs per CPU. These are 781 * maintained in the list headed by the 'po_pmcs' to save on space. 782 * 783 */ 784 785struct pmc_owner { 786 LIST_ENTRY(pmc_owner) po_next; /* hash chain */ 787 LIST_ENTRY(pmc_owner) po_ssnext; /* list of SS PMC owners */ 788 LIST_HEAD(, pmc) po_pmcs; /* owned PMC list */ 789 TAILQ_HEAD(, pmclog_buffer) po_logbuffers; /* (o) logbuffer list */ 790 struct mtx po_mtx; /* spin lock for (o) */ 791 struct proc *po_owner; /* owner proc */ 792 uint32_t po_flags; /* (k) flags PMC_PO_* */ 793 struct proc *po_kthread; /* (k) helper kthread */ 794 struct pmclog_buffer *po_curbuf; /* current log buffer */ 795 struct file *po_file; /* file reference */ 796 int po_error; /* recorded error */ 797 short po_sscount; /* # SS PMCs owned */ 798 short po_logprocmaps; /* global mappings done */ 799}; 800 801#define PMC_PO_OWNS_LOGFILE 0x00000001 /* has a log file */ 802#define PMC_PO_SHUTDOWN 0x00000010 /* in the process of shutdown */ 803#define PMC_PO_INITIAL_MAPPINGS_DONE 0x00000020 804 805/* 806 * struct pmc_hw -- describe the state of the PMC hardware 807 * 808 * When in use, a HW PMC is associated with one allocated 'struct pmc' 809 * pointed to by field 'phw_pmc'. When inactive, this field is NULL. 810 * 811 * On an SMP box, one or more HW PMC's in process virtual mode with 812 * the same 'phw_pmc' could be executing on different CPUs. In order 813 * to handle this case correctly, we need to ensure that only 814 * incremental counts get added to the saved value in the associated 815 * 'struct pmc'. The 'phw_save' field is used to keep the saved PMC 816 * value at the time the hardware is started during this context 817 * switch (i.e., the difference between the new (hardware) count and 818 * the saved count is atomically added to the count field in 'struct 819 * pmc' at context switch time). 820 * 821 */ 822 823struct pmc_hw { 824 uint32_t phw_state; /* see PHW_* macros below */ 825 struct pmc *phw_pmc; /* current thread PMC */ 826}; 827 828#define PMC_PHW_RI_MASK 0x000000FF 829#define PMC_PHW_CPU_SHIFT 8 830#define PMC_PHW_CPU_MASK 0x0000FF00 831#define PMC_PHW_FLAGS_SHIFT 16 832#define PMC_PHW_FLAGS_MASK 0xFFFF0000 833 834#define PMC_PHW_INDEX_TO_STATE(ri) ((ri) & PMC_PHW_RI_MASK) 835#define PMC_PHW_STATE_TO_INDEX(state) ((state) & PMC_PHW_RI_MASK) 836#define PMC_PHW_CPU_TO_STATE(cpu) (((cpu) << PMC_PHW_CPU_SHIFT) & \ 837 PMC_PHW_CPU_MASK) 838#define PMC_PHW_STATE_TO_CPU(state) (((state) & PMC_PHW_CPU_MASK) >> \ 839 PMC_PHW_CPU_SHIFT) 840#define PMC_PHW_FLAGS_TO_STATE(flags) (((flags) << PMC_PHW_FLAGS_SHIFT) & \ 841 PMC_PHW_FLAGS_MASK) 842#define PMC_PHW_STATE_TO_FLAGS(state) (((state) & PMC_PHW_FLAGS_MASK) >> \ 843 PMC_PHW_FLAGS_SHIFT) 844#define PMC_PHW_FLAG_IS_ENABLED (PMC_PHW_FLAGS_TO_STATE(0x01)) 845#define PMC_PHW_FLAG_IS_SHAREABLE (PMC_PHW_FLAGS_TO_STATE(0x02)) 846 847/* 848 * struct pmc_sample 849 * 850 * Space for N (tunable) PC samples and associated control data. 851 */ 852 853struct pmc_sample { 854 uint16_t ps_nsamples; /* callchain depth */ 855 uint8_t ps_cpu; /* cpu number */ 856 uint8_t ps_flags; /* other flags */ 857 pid_t ps_pid; /* process PID or -1 */ 858 struct thread *ps_td; /* which thread */ 859 struct pmc *ps_pmc; /* interrupting PMC */ 860 uintptr_t *ps_pc; /* (const) callchain start */ 861}; 862 863#define PMC_SAMPLE_FREE ((uint16_t) 0) 864#define PMC_SAMPLE_INUSE ((uint16_t) 0xFFFF) 865 866struct pmc_samplebuffer { 867 struct pmc_sample * volatile ps_read; /* read pointer */ 868 struct pmc_sample * volatile ps_write; /* write pointer */ 869 uintptr_t *ps_callchains; /* all saved call chains */ 870 struct pmc_sample *ps_fence; /* one beyond ps_samples[] */ 871 struct pmc_sample ps_samples[]; /* array of sample entries */ 872}; 873 874 875/* 876 * struct pmc_cpustate 877 * 878 * A CPU is modelled as a collection of HW PMCs with space for additional 879 * flags. 880 */ 881 882struct pmc_cpu { 883 uint32_t pc_state; /* physical cpu number + flags */ 884 struct pmc_samplebuffer *pc_sb[2]; /* space for samples */ 885 struct pmc_hw *pc_hwpmcs[]; /* 'npmc' pointers */ 886}; 887 888#define PMC_PCPU_CPU_MASK 0x000000FF 889#define PMC_PCPU_FLAGS_MASK 0xFFFFFF00 890#define PMC_PCPU_FLAGS_SHIFT 8 891#define PMC_PCPU_STATE_TO_CPU(S) ((S) & PMC_PCPU_CPU_MASK) 892#define PMC_PCPU_STATE_TO_FLAGS(S) (((S) & PMC_PCPU_FLAGS_MASK) >> PMC_PCPU_FLAGS_SHIFT) 893#define PMC_PCPU_FLAGS_TO_STATE(F) (((F) << PMC_PCPU_FLAGS_SHIFT) & PMC_PCPU_FLAGS_MASK) 894#define PMC_PCPU_CPU_TO_STATE(C) ((C) & PMC_PCPU_CPU_MASK) 895#define PMC_PCPU_FLAG_HTT (PMC_PCPU_FLAGS_TO_STATE(0x1)) 896 897/* 898 * struct pmc_binding 899 * 900 * CPU binding information. 901 */ 902 903struct pmc_binding { 904 int pb_bound; /* is bound? */ 905 int pb_cpu; /* if so, to which CPU */ 906}; 907 908 909struct pmc_mdep; 910 911/* 912 * struct pmc_classdep 913 * 914 * PMC class-dependent operations. 915 */ 916struct pmc_classdep { 917 uint32_t pcd_caps; /* class capabilities */ 918 enum pmc_class pcd_class; /* class id */ 919 int pcd_num; /* number of PMCs */ 920 int pcd_ri; /* row index of the first PMC in class */ 921 int pcd_width; /* width of the PMC */ 922 923 /* configuring/reading/writing the hardware PMCs */ 924 int (*pcd_config_pmc)(int _cpu, int _ri, struct pmc *_pm); 925 int (*pcd_get_config)(int _cpu, int _ri, struct pmc **_ppm); 926 int (*pcd_read_pmc)(int _cpu, int _ri, pmc_value_t *_value); 927 int (*pcd_write_pmc)(int _cpu, int _ri, pmc_value_t _value); 928 929 /* pmc allocation/release */ 930 int (*pcd_allocate_pmc)(int _cpu, int _ri, struct pmc *_t, 931 const struct pmc_op_pmcallocate *_a); 932 int (*pcd_release_pmc)(int _cpu, int _ri, struct pmc *_pm); 933 934 /* starting and stopping PMCs */ 935 int (*pcd_start_pmc)(int _cpu, int _ri); 936 int (*pcd_stop_pmc)(int _cpu, int _ri); 937 938 /* description */ 939 int (*pcd_describe)(int _cpu, int _ri, struct pmc_info *_pi, 940 struct pmc **_ppmc); 941 942 /* class-dependent initialization & finalization */ 943 int (*pcd_pcpu_init)(struct pmc_mdep *_md, int _cpu); 944 int (*pcd_pcpu_fini)(struct pmc_mdep *_md, int _cpu); 945 946 /* machine-specific interface */ 947 int (*pcd_get_msr)(int _ri, uint32_t *_msr); 948}; 949 950/* 951 * struct pmc_mdep 952 * 953 * Machine dependent bits needed per CPU type. 954 */ 955 956struct pmc_mdep { 957 uint32_t pmd_cputype; /* from enum pmc_cputype */ 958 uint32_t pmd_npmc; /* number of PMCs per CPU */ 959 uint32_t pmd_nclass; /* number of PMC classes present */ 960 961 /* 962 * Machine dependent methods. 963 */ 964 965 /* per-cpu initialization and finalization */ 966 int (*pmd_pcpu_init)(struct pmc_mdep *_md, int _cpu); 967 int (*pmd_pcpu_fini)(struct pmc_mdep *_md, int _cpu); 968 969 /* thread context switch in/out */ 970 int (*pmd_switch_in)(struct pmc_cpu *_p, struct pmc_process *_pp); 971 int (*pmd_switch_out)(struct pmc_cpu *_p, struct pmc_process *_pp); 972 973 /* handle a PMC interrupt */ 974 int (*pmd_intr)(int _cpu, struct trapframe *_tf); 975 976 /* 977 * PMC class dependent information. 978 */ 979 struct pmc_classdep pmd_classdep[]; 980}; 981 982/* 983 * Per-CPU state. This is an array of 'mp_ncpu' pointers 984 * to struct pmc_cpu descriptors. 985 */ 986 987extern struct pmc_cpu **pmc_pcpu; 988 989/* driver statistics */ 990extern struct pmc_op_getdriverstats pmc_stats; 991 992#if defined(DEBUG) 993 994/* debug flags, major flag groups */ 995struct pmc_debugflags { 996 int pdb_CPU; 997 int pdb_CSW; 998 int pdb_LOG; 999 int pdb_MDP; 1000 int pdb_MOD; 1001 int pdb_OWN; 1002 int pdb_PMC; 1003 int pdb_PRC; 1004 int pdb_SAM; 1005}; 1006 1007extern struct pmc_debugflags pmc_debugflags; 1008 1009#define PMC_DEBUG_STRSIZE 128 1010#define PMC_DEBUG_DEFAULT_FLAGS { 0, 0, 0, 0, 0, 0, 0, 0 } 1011 1012#define PMCDBG(M,N,L,F,...) do { \ 1013 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1014 printf(#M ":" #N ":" #L ": " F "\n", __VA_ARGS__); \ 1015} while (0) 1016 1017/* Major numbers */ 1018#define PMC_DEBUG_MAJ_CPU 0 /* cpu switches */ 1019#define PMC_DEBUG_MAJ_CSW 1 /* context switches */ 1020#define PMC_DEBUG_MAJ_LOG 2 /* logging */ 1021#define PMC_DEBUG_MAJ_MDP 3 /* machine dependent */ 1022#define PMC_DEBUG_MAJ_MOD 4 /* misc module infrastructure */ 1023#define PMC_DEBUG_MAJ_OWN 5 /* owner */ 1024#define PMC_DEBUG_MAJ_PMC 6 /* pmc management */ 1025#define PMC_DEBUG_MAJ_PRC 7 /* processes */ 1026#define PMC_DEBUG_MAJ_SAM 8 /* sampling */ 1027 1028/* Minor numbers */ 1029 1030/* Common (8 bits) */ 1031#define PMC_DEBUG_MIN_ALL 0 /* allocation */ 1032#define PMC_DEBUG_MIN_REL 1 /* release */ 1033#define PMC_DEBUG_MIN_OPS 2 /* ops: start, stop, ... */ 1034#define PMC_DEBUG_MIN_INI 3 /* init */ 1035#define PMC_DEBUG_MIN_FND 4 /* find */ 1036 1037/* MODULE */ 1038#define PMC_DEBUG_MIN_PMH 14 /* pmc_hook */ 1039#define PMC_DEBUG_MIN_PMS 15 /* pmc_syscall */ 1040 1041/* OWN */ 1042#define PMC_DEBUG_MIN_ORM 8 /* owner remove */ 1043#define PMC_DEBUG_MIN_OMR 9 /* owner maybe remove */ 1044 1045/* PROCESSES */ 1046#define PMC_DEBUG_MIN_TLK 8 /* link target */ 1047#define PMC_DEBUG_MIN_TUL 9 /* unlink target */ 1048#define PMC_DEBUG_MIN_EXT 10 /* process exit */ 1049#define PMC_DEBUG_MIN_EXC 11 /* process exec */ 1050#define PMC_DEBUG_MIN_FRK 12 /* process fork */ 1051#define PMC_DEBUG_MIN_ATT 13 /* attach/detach */ 1052#define PMC_DEBUG_MIN_SIG 14 /* signalling */ 1053 1054/* CONTEXT SWITCHES */ 1055#define PMC_DEBUG_MIN_SWI 8 /* switch in */ 1056#define PMC_DEBUG_MIN_SWO 9 /* switch out */ 1057 1058/* PMC */ 1059#define PMC_DEBUG_MIN_REG 8 /* pmc register */ 1060#define PMC_DEBUG_MIN_ALR 9 /* allocate row */ 1061 1062/* MACHINE DEPENDENT LAYER */ 1063#define PMC_DEBUG_MIN_REA 8 /* read */ 1064#define PMC_DEBUG_MIN_WRI 9 /* write */ 1065#define PMC_DEBUG_MIN_CFG 10 /* config */ 1066#define PMC_DEBUG_MIN_STA 11 /* start */ 1067#define PMC_DEBUG_MIN_STO 12 /* stop */ 1068#define PMC_DEBUG_MIN_INT 13 /* interrupts */ 1069 1070/* CPU */ 1071#define PMC_DEBUG_MIN_BND 8 /* bind */ 1072#define PMC_DEBUG_MIN_SEL 9 /* select */ 1073 1074/* LOG */ 1075#define PMC_DEBUG_MIN_GTB 8 /* get buf */ 1076#define PMC_DEBUG_MIN_SIO 9 /* schedule i/o */ 1077#define PMC_DEBUG_MIN_FLS 10 /* flush */ 1078#define PMC_DEBUG_MIN_SAM 11 /* sample */ 1079#define PMC_DEBUG_MIN_CLO 12 /* close */ 1080 1081#else 1082#define PMCDBG(M,N,L,F,...) /* nothing */ 1083#endif 1084 1085/* declare a dedicated memory pool */ 1086MALLOC_DECLARE(M_PMC); 1087 1088/* 1089 * Functions 1090 */ 1091 1092struct pmc_mdep *pmc_md_initialize(void); /* MD init function */ 1093void pmc_md_finalize(struct pmc_mdep *_md); /* MD fini function */ 1094int pmc_getrowdisp(int _ri); 1095int pmc_process_interrupt(int _cpu, int _soft, struct pmc *_pm, 1096 struct trapframe *_tf, int _inuserspace); 1097int pmc_save_kernel_callchain(uintptr_t *_cc, int _maxsamples, 1098 struct trapframe *_tf); 1099int pmc_save_user_callchain(uintptr_t *_cc, int _maxsamples, 1100 struct trapframe *_tf); 1101struct pmc_mdep *pmc_mdep_alloc(int nclasses); 1102void pmc_mdep_free(struct pmc_mdep *md); 1103#endif /* _KERNEL */ 1104#endif /* _SYS_PMC_H_ */ 1105