1/************************************************************************** 2** 3** $FreeBSD$ 4** 5** Device driver for the NCR 53C810 PCI-SCSI-Controller. 6** 7** 386bsd / FreeBSD / NetBSD 8** 9**------------------------------------------------------------------------- 10** 11** Written for 386bsd and FreeBSD by 12** wolf@cologne.de Wolfgang Stanglmeier 13** se@mi.Uni-Koeln.de Stefan Esser 14** 15** Ported to NetBSD by 16** mycroft@gnu.ai.mit.edu 17** 18**------------------------------------------------------------------------- 19*/ 20/*- 21** Copyright (c) 1994 Wolfgang Stanglmeier. All rights reserved. 22** 23** Redistribution and use in source and binary forms, with or without 24** modification, are permitted provided that the following conditions 25** are met: 26** 1. Redistributions of source code must retain the above copyright 27** notice, this list of conditions and the following disclaimer. 28** 2. Redistributions in binary form must reproduce the above copyright 29** notice, this list of conditions and the following disclaimer in the 30** documentation and/or other materials provided with the distribution. 31** 3. The name of the author may not be used to endorse or promote products 32** derived from this software without specific prior written permission. 33** 34** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 35** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 36** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 37** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 38** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 39** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 40** DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 41** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 42** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 43** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 44** 45*************************************************************************** 46*/ 47 48#ifndef __NCR_REG_H__ 49#define __NCR_REG_H__ 50 51/*----------------------------------------------------------------- 52** 53** The ncr 53c810 register structure. 54** 55**----------------------------------------------------------------- 56*/ 57 58struct ncr_reg { 59/*00*/ u_char nc_scntl0; /* full arb., ena parity, par->ATN */ 60 61/*01*/ u_char nc_scntl1; /* no reset */ 62 #define ISCON 0x10 /* connected to scsi */ 63 #define CRST 0x08 /* force reset */ 64 65/*02*/ u_char nc_scntl2; /* no disconnect expected */ 66 #define SDU 0x80 /* cmd: disconnect will raise error */ 67 #define CHM 0x40 /* sta: chained mode */ 68 #define WSS 0x08 /* sta: wide scsi send [W]*/ 69 #define WSR 0x01 /* sta: wide scsi received [W]*/ 70 71/*03*/ u_char nc_scntl3; /* cnf system clock dependent */ 72 #define EWS 0x08 /* cmd: enable wide scsi [W]*/ 73 74/*04*/ u_char nc_scid; /* cnf host adapter scsi address */ 75 #define RRE 0x40 /* r/w:e enable response to resel. */ 76 #define SRE 0x20 /* r/w:e enable response to select */ 77 78/*05*/ u_char nc_sxfer; /* ### Sync speed and count */ 79 80/*06*/ u_char nc_sdid; /* ### Destination-ID */ 81 82/*07*/ u_char nc_gpreg; /* ??? IO-Pins */ 83 84/*08*/ u_char nc_sfbr; /* ### First byte in phase */ 85 86/*09*/ u_char nc_socl; 87 #define CREQ 0x80 /* r/w: SCSI-REQ */ 88 #define CACK 0x40 /* r/w: SCSI-ACK */ 89 #define CBSY 0x20 /* r/w: SCSI-BSY */ 90 #define CSEL 0x10 /* r/w: SCSI-SEL */ 91 #define CATN 0x08 /* r/w: SCSI-ATN */ 92 #define CMSG 0x04 /* r/w: SCSI-MSG */ 93 #define CC_D 0x02 /* r/w: SCSI-C_D */ 94 #define CI_O 0x01 /* r/w: SCSI-I_O */ 95 96/*0a*/ u_char nc_ssid; 97 98/*0b*/ u_char nc_sbcl; 99 100/*0c*/ u_char nc_dstat; 101 #define DFE 0x80 /* sta: dma fifo empty */ 102 #define MDPE 0x40 /* int: master data parity error */ 103 #define BF 0x20 /* int: script: bus fault */ 104 #define ABRT 0x10 /* int: script: command aborted */ 105 #define SSI 0x08 /* int: script: single step */ 106 #define SIR 0x04 /* int: script: interrupt instruct. */ 107 #define IID 0x01 /* int: script: illegal instruct. */ 108 109/*0d*/ u_char nc_sstat0; 110 #define ILF 0x80 /* sta: data in SIDL register lsb */ 111 #define ORF 0x40 /* sta: data in SODR register lsb */ 112 #define OLF 0x20 /* sta: data in SODL register lsb */ 113 #define AIP 0x10 /* sta: arbitration in progress */ 114 #define LOA 0x08 /* sta: arbitration lost */ 115 #define WOA 0x04 /* sta: arbitration won */ 116 #define IRST 0x02 /* sta: scsi reset signal */ 117 #define SDP 0x01 /* sta: scsi parity signal */ 118 119/*0e*/ u_char nc_sstat1; 120 #define FF3210 0xf0 /* sta: bytes in the scsi fifo */ 121 122/*0f*/ u_char nc_sstat2; 123 #define ILF1 0x80 /* sta: data in SIDL register msb[W]*/ 124 #define ORF1 0x40 /* sta: data in SODR register msb[W]*/ 125 #define OLF1 0x20 /* sta: data in SODL register msb[W]*/ 126 #define LDSC 0x02 /* sta: disconnect & reconnect */ 127 128/*10*/ u_int32_t nc_dsa; /* --> Base page */ 129 130/*14*/ u_char nc_istat; /* --> Main Command and status */ 131 #define CABRT 0x80 /* cmd: abort current operation */ 132 #define SRST 0x40 /* mod: reset chip */ 133 #define SIGP 0x20 /* r/w: message from host to ncr */ 134 #define SEM 0x10 /* r/w: message between host + ncr */ 135 #define CON 0x08 /* sta: connected to scsi */ 136 #define INTF 0x04 /* sta: int on the fly (reset by wr)*/ 137 #define SIP 0x02 /* sta: scsi-interrupt */ 138 #define DIP 0x01 /* sta: host/script interrupt */ 139 140/*15*/ u_char nc_15_; 141/*16*/ u_char nc_16_; 142/*17*/ u_char nc_17_; 143 144/*18*/ u_char nc_ctest0; 145/*19*/ u_char nc_ctest1; 146 147/*1a*/ u_char nc_ctest2; 148 #define CSIGP 0x40 149 150/*1b*/ u_char nc_ctest3; 151 #define FLF 0x08 /* cmd: flush dma fifo */ 152 #define CLF 0x04 /* cmd: clear dma fifo */ 153 #define FM 0x02 /* mod: fetch pin mode */ 154 #define WRIE 0x01 /* mod: write and invalidate enable */ 155 156/*1c*/ u_int32_t nc_temp; /* ### Temporary stack */ 157 158/*20*/ u_char nc_dfifo; 159/*21*/ u_char nc_ctest4; 160 #define BDIS 0x80 /* mod: burst disable */ 161 #define MPEE 0x08 /* mod: master parity error enable */ 162 163/*22*/ u_char nc_ctest5; 164 #define DFS 0x20 /* mod: dma fifo size */ 165/*23*/ u_char nc_ctest6; 166 167/*24*/ u_int32_t nc_dbc; /* ### Byte count and command */ 168/*28*/ u_int32_t nc_dnad; /* ### Next command register */ 169/*2c*/ u_int32_t nc_dsp; /* --> Script Pointer */ 170/*30*/ u_int32_t nc_dsps; /* --> Script pointer save/opcode#2 */ 171/*34*/ u_int32_t nc_scratcha; /* ??? Temporary register a */ 172 173/*38*/ u_char nc_dmode; 174 #define BL_2 0x80 /* mod: burst length shift value +2 */ 175 #define BL_1 0x40 /* mod: burst length shift value +1 */ 176 #define ERL 0x08 /* mod: enable read line */ 177 #define ERMP 0x04 /* mod: enable read multiple */ 178 #define BOF 0x02 /* mod: burst op code fetch */ 179 180/*39*/ u_char nc_dien; 181/*3a*/ u_char nc_dwt; 182 183/*3b*/ u_char nc_dcntl; /* --> Script execution control */ 184 #define CLSE 0x80 /* mod: cache line size enable */ 185 #define PFF 0x40 /* cmd: pre-fetch flush */ 186 #define PFEN 0x20 /* mod: pre-fetch enable */ 187 #define SSM 0x10 /* mod: single step mode */ 188 #define IRQM 0x08 /* mod: irq mode (1 = totem pole !) */ 189 #define STD 0x04 /* cmd: start dma mode */ 190 #define IRQD 0x02 /* mod: irq disable */ 191 #define NOCOM 0x01 /* cmd: protect sfbr while reselect */ 192 193/*3c*/ u_int32_t nc_adder; 194 195/*40*/ u_short nc_sien; /* -->: interrupt enable */ 196/*42*/ u_short nc_sist; /* <--: interrupt status */ 197 #define STO 0x0400/* sta: timeout (select) */ 198 #define GEN 0x0200/* sta: timeout (general) */ 199 #define HTH 0x0100/* sta: timeout (handshake) */ 200 #define MA 0x80 /* sta: phase mismatch */ 201 #define CMP 0x40 /* sta: arbitration complete */ 202 #define SEL 0x20 /* sta: selected by another device */ 203 #define RSL 0x10 /* sta: reselected by another device*/ 204 #define SGE 0x08 /* sta: gross error (over/underflow)*/ 205 #define UDC 0x04 /* sta: unexpected disconnect */ 206 #define RST 0x02 /* sta: scsi bus reset detected */ 207 #define PAR 0x01 /* sta: scsi parity error */ 208 209/*44*/ u_char nc_slpar; 210/*45*/ u_char nc_swide; 211/*46*/ u_char nc_macntl; 212/*47*/ u_char nc_gpcntl; 213/*48*/ u_char nc_stime0; /* cmd: timeout for select&handshake*/ 214/*49*/ u_char nc_stime1; /* cmd: timeout user defined */ 215/*4a*/ u_short nc_respid; /* sta: Reselect-IDs */ 216 217/*4c*/ u_char nc_stest0; 218 219/*4d*/ u_char nc_stest1; 220 #define DBLEN 0x08 /* clock doubler running */ 221 #define DBLSEL 0x04 /* clock doubler selected */ 222 223/*4e*/ u_char nc_stest2; 224 #define ROF 0x40 /* reset scsi offset (after gross error!) */ 225 #define EXT 0x02 /* extended filtering */ 226 227/*4f*/ u_char nc_stest3; 228 #define TE 0x80 /* c: tolerAnt enable */ 229 #define HSC 0x20 /* c: Halt SCSI Clock */ 230 #define CSF 0x02 /* c: clear scsi fifo */ 231 232/*50*/ u_short nc_sidl; /* Lowlevel: latched from scsi data */ 233/*52*/ u_char nc_stest4; 234 #define SMODE 0xc0 /* SCSI bus mode (895/6 only) */ 235 #define SMODE_HVD 0x40 /* High Voltage Differential */ 236 #define SMODE_SE 0x80 /* Single Ended */ 237 #define SMODE_LVD 0xc0 /* Low Voltage Differential */ 238 #define LCKFRQ 0x20 /* Frequency Lock (895/6 only) */ 239 240/*53*/ u_char nc_53_; 241/*54*/ u_short nc_sodl; /* Lowlevel: data out to scsi data */ 242/*56*/ u_short nc_56_; 243/*58*/ u_short nc_sbdl; /* Lowlevel: data from scsi data */ 244/*5a*/ u_short nc_5a_; 245/*5c*/ u_char nc_scr0; /* Working register B */ 246/*5d*/ u_char nc_scr1; /* */ 247/*5e*/ u_char nc_scr2; /* */ 248/*5f*/ u_char nc_scr3; /* */ 249/*60*/ 250}; 251 252/*----------------------------------------------------------- 253** 254** Utility macros for the script. 255** 256**----------------------------------------------------------- 257*/ 258 259#define REGJ(p,r) (offsetof(struct ncr_reg, p ## r)) 260#define REG(r) REGJ (nc_, r) 261 262#ifndef TARGET_MODE 263#define TARGET_MODE 0 264#endif 265 266typedef u_int32_t ncrcmd; 267 268/*----------------------------------------------------------- 269** 270** SCSI phases 271** 272**----------------------------------------------------------- 273*/ 274 275#define SCR_DATA_OUT 0x00000000 276#define SCR_DATA_IN 0x01000000 277#define SCR_COMMAND 0x02000000 278#define SCR_STATUS 0x03000000 279#define SCR_ILG_OUT 0x04000000 280#define SCR_ILG_IN 0x05000000 281#define SCR_MSG_OUT 0x06000000 282#define SCR_MSG_IN 0x07000000 283 284/*----------------------------------------------------------- 285** 286** Data transfer via SCSI. 287** 288**----------------------------------------------------------- 289** 290** MOVE_ABS (LEN) 291** <<start address>> 292** 293** MOVE_IND (LEN) 294** <<dnad_offset>> 295** 296** MOVE_TBL 297** <<dnad_offset>> 298** 299**----------------------------------------------------------- 300*/ 301 302#define SCR_MOVE_ABS(l) ((0x08000000 ^ (TARGET_MODE << 1ul)) | (l)) 303#define SCR_MOVE_IND(l) ((0x28000000 ^ (TARGET_MODE << 1ul)) | (l)) 304#define SCR_MOVE_TBL (0x18000000 ^ (TARGET_MODE << 1ul)) 305 306struct scr_tblmove { 307 u_int32_t size; 308 u_int32_t addr; 309}; 310 311/*----------------------------------------------------------- 312** 313** Selection 314** 315**----------------------------------------------------------- 316** 317** SEL_ABS | SCR_ID (0..7) [ | REL_JMP] 318** <<alternate_address>> 319** 320** SEL_TBL | << dnad_offset>> [ | REL_JMP] 321** <<alternate_address>> 322** 323**----------------------------------------------------------- 324*/ 325 326#define SCR_SEL_ABS 0x40000000 327#define SCR_SEL_ABS_ATN 0x41000000 328#define SCR_SEL_TBL 0x42000000 329#define SCR_SEL_TBL_ATN 0x43000000 330 331struct scr_tblsel { 332 u_char sel_0; 333 u_char sel_sxfer; 334 u_char sel_id; 335 u_char sel_scntl3; 336}; 337 338#define SCR_JMP_REL 0x04000000 339#define SCR_ID(id) (((u_int32_t)(id)) << 16) 340 341/*----------------------------------------------------------- 342** 343** Waiting for Disconnect or Reselect 344** 345**----------------------------------------------------------- 346** 347** WAIT_DISC 348** dummy: <<alternate_address>> 349** 350** WAIT_RESEL 351** <<alternate_address>> 352** 353**----------------------------------------------------------- 354*/ 355 356#define SCR_WAIT_DISC 0x48000000 357#define SCR_WAIT_RESEL 0x50000000 358 359/*----------------------------------------------------------- 360** 361** Bit Set / Reset 362** 363**----------------------------------------------------------- 364** 365** SET (flags {|.. }) 366** 367** CLR (flags {|.. }) 368** 369**----------------------------------------------------------- 370*/ 371 372#define SCR_SET(f) (0x58000000 | (f)) 373#define SCR_CLR(f) (0x60000000 | (f)) 374 375#define SCR_CARRY 0x00000400 376#define SCR_TRG 0x00000200 377#define SCR_ACK 0x00000040 378#define SCR_ATN 0x00000008 379 380 381/*----------------------------------------------------------- 382** 383** Memory to memory move 384** 385**----------------------------------------------------------- 386** 387** COPY (bytecount) 388** << source_address >> 389** << destination_address >> 390** 391** SCR_COPY sets the NO FLUSH option by default. 392** SCR_COPY_F does not set this option. 393** 394** For chips which do not support this option, 395** ncr_copy_and_bind() will remove this bit. 396**----------------------------------------------------------- 397*/ 398 399#define SCR_NO_FLUSH 0x01000000 400 401#define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n)) 402#define SCR_COPY_F(n) (0xc0000000 | (n)) 403 404 405/*----------------------------------------------------------- 406** 407** Register move and binary operations 408** 409**----------------------------------------------------------- 410** 411** SFBR_REG (reg, op, data) reg = SFBR op data 412** << 0 >> 413** 414** REG_SFBR (reg, op, data) SFBR = reg op data 415** << 0 >> 416** 417** REG_REG (reg, op, data) reg = reg op data 418** << 0 >> 419** 420**----------------------------------------------------------- 421*/ 422 423#define SCR_REG_OFS(ofs) ((ofs) << 16ul) 424 425#define SCR_SFBR_REG(reg,op,data) \ 426 (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | ((data)<<8ul)) 427 428#define SCR_REG_SFBR(reg,op,data) \ 429 (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | ((data)<<8ul)) 430 431#define SCR_REG_REG(reg,op,data) \ 432 (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | ((data)<<8ul)) 433 434 435#define SCR_LOAD 0x00000000 436#define SCR_SHL 0x01000000 437#define SCR_OR 0x02000000 438#define SCR_XOR 0x03000000 439#define SCR_AND 0x04000000 440#define SCR_SHR 0x05000000 441#define SCR_ADD 0x06000000 442#define SCR_ADDC 0x07000000 443 444/*----------------------------------------------------------- 445** 446** FROM_REG (reg) reg = SFBR 447** << 0 >> 448** 449** TO_REG (reg) SFBR = reg 450** << 0 >> 451** 452** LOAD_REG (reg, data) reg = <data> 453** << 0 >> 454** 455** LOAD_SFBR(data) SFBR = <data> 456** << 0 >> 457** 458**----------------------------------------------------------- 459*/ 460 461#define SCR_FROM_REG(reg) \ 462 SCR_REG_SFBR(reg,SCR_OR,0) 463 464#define SCR_TO_REG(reg) \ 465 SCR_SFBR_REG(reg,SCR_OR,0) 466 467#define SCR_LOAD_REG(reg,data) \ 468 SCR_REG_REG(reg,SCR_LOAD,data) 469 470#define SCR_LOAD_SFBR(data) \ 471 (SCR_REG_SFBR (gpreg, SCR_LOAD, data)) 472 473/*----------------------------------------------------------- 474** 475** Waiting for Disconnect or Reselect 476** 477**----------------------------------------------------------- 478** 479** JUMP [ | IFTRUE/IFFALSE ( ... ) ] 480** <<address>> 481** 482** JUMPR [ | IFTRUE/IFFALSE ( ... ) ] 483** <<distance>> 484** 485** CALL [ | IFTRUE/IFFALSE ( ... ) ] 486** <<address>> 487** 488** CALLR [ | IFTRUE/IFFALSE ( ... ) ] 489** <<distance>> 490** 491** RETURN [ | IFTRUE/IFFALSE ( ... ) ] 492** <<dummy>> 493** 494** INT [ | IFTRUE/IFFALSE ( ... ) ] 495** <<ident>> 496** 497** INT_FLY [ | IFTRUE/IFFALSE ( ... ) ] 498** <<ident>> 499** 500** Conditions: 501** WHEN (phase) 502** IF (phase) 503** CARRY 504** DATA (data, mask) 505** 506**----------------------------------------------------------- 507*/ 508 509#define SCR_NO_OP 0x80000000 510#define SCR_JUMP 0x80080000 511#define SCR_JUMPR 0x80880000 512#define SCR_CALL 0x88080000 513#define SCR_CALLR 0x88880000 514#define SCR_RETURN 0x90080000 515#define SCR_INT 0x98080000 516#define SCR_INT_FLY 0x98180000 517 518#define IFFALSE(arg) (0x00080000 | (arg)) 519#define IFTRUE(arg) (0x00000000 | (arg)) 520 521#define WHEN(phase) (0x00030000 | (phase)) 522#define IF(phase) (0x00020000 | (phase)) 523 524#define DATA(D) (0x00040000 | ((D) & 0xff)) 525#define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff)) 526 527#define CARRYSET (0x00200000) 528 529/*----------------------------------------------------------- 530** 531** SCSI constants. 532** 533**----------------------------------------------------------- 534*/ 535 536/* 537** Messages 538*/ 539#define M_X_MODIFY_DP (0x00) 540 541/* 542** Status 543*/ 544#define SCSI_STATUS_ILLEGAL (0xff) 545#define SCSI_STATUS_SENSE (0x80) 546 547/* 548** Bits defining chip features. 549** For now only some of them are used, since we explicitely 550** deal with PCI device id and revision id. 551*/ 552#define FE_LED0 (1<<0) 553#define FE_WIDE (1<<1) 554#define FE_ULTRA (1<<2) 555#define FE_ULTRA2 (1<<3) 556#define FE_DBLR (1<<4) 557#define FE_QUAD (1<<5) 558#define FE_ERL (1<<6) 559#define FE_CLSE (1<<7) 560#define FE_WRIE (1<<8) 561#define FE_ERMP (1<<9) 562#define FE_BOF (1<<10) 563#define FE_DFS (1<<11) 564#define FE_PFEN (1<<12) 565#define FE_LDSTR (1<<13) 566#define FE_RAM (1<<14) 567#define FE_CLK80 (1<<15) 568#define FE_DIFF (1<<16) 569#define FE_BIOS (1<<17) 570#define FE_CACHE_SET (FE_ERL|FE_CLSE|FE_WRIE|FE_ERMP) 571#define FE_SCSI_SET (FE_WIDE|FE_ULTRA|FE_ULTRA2|FE_DBLR|FE_QUAD|F_CLK80) 572#define FE_SPECIAL_SET (FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM) 573 574#endif /*__NCR_REG_H__*/ 575