ncr.c revision 142398
1/************************************************************************** 2** 3** 4** Device driver for the NCR 53C8XX PCI-SCSI-Controller Family. 5** 6**------------------------------------------------------------------------- 7** 8** Written for 386bsd and FreeBSD by 9** Wolfgang Stanglmeier <wolf@cologne.de> 10** Stefan Esser <se@mi.Uni-Koeln.de> 11** 12**------------------------------------------------------------------------- 13*/ 14/*- 15** Copyright (c) 1994 Wolfgang Stanglmeier. All rights reserved. 16** 17** Redistribution and use in source and binary forms, with or without 18** modification, are permitted provided that the following conditions 19** are met: 20** 1. Redistributions of source code must retain the above copyright 21** notice, this list of conditions and the following disclaimer. 22** 2. Redistributions in binary form must reproduce the above copyright 23** notice, this list of conditions and the following disclaimer in the 24** documentation and/or other materials provided with the distribution. 25** 3. The name of the author may not be used to endorse or promote products 26** derived from this software without specific prior written permission. 27** 28** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 29** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 30** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 31** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 32** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 33** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34** DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 37** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38** 39*************************************************************************** 40*/ 41 42#include <sys/cdefs.h> 43__FBSDID("$FreeBSD: head/sys/pci/ncr.c 142398 2005-02-24 21:32:56Z imp $"); 44 45 46#define NCR_DATE "pl30 98/1/1" 47 48#define NCR_VERSION (2) 49#define MAX_UNITS (16) 50 51#define NCR_GETCC_WITHMSG 52 53#if defined (__FreeBSD__) && defined(_KERNEL) 54#include "opt_ncr.h" 55#endif 56 57/*========================================================== 58** 59** Configuration and Debugging 60** 61** May be overwritten in <arch/conf/xxxx> 62** 63**========================================================== 64*/ 65 66/* 67** SCSI address of this device. 68** The boot routines should have set it. 69** If not, use this. 70*/ 71 72#ifndef SCSI_NCR_MYADDR 73#define SCSI_NCR_MYADDR (7) 74#endif /* SCSI_NCR_MYADDR */ 75 76/* 77** The default synchronous period factor 78** (0=asynchronous) 79** If maximum synchronous frequency is defined, use it instead. 80*/ 81 82#ifndef SCSI_NCR_MAX_SYNC 83 84#ifndef SCSI_NCR_DFLT_SYNC 85#define SCSI_NCR_DFLT_SYNC (12) 86#endif /* SCSI_NCR_DFLT_SYNC */ 87 88#else 89 90#if SCSI_NCR_MAX_SYNC == 0 91#define SCSI_NCR_DFLT_SYNC 0 92#else 93#define SCSI_NCR_DFLT_SYNC (250000 / SCSI_NCR_MAX_SYNC) 94#endif 95 96#endif 97 98/* 99** The minimal asynchronous pre-scaler period (ns) 100** Shall be 40. 101*/ 102 103#ifndef SCSI_NCR_MIN_ASYNC 104#define SCSI_NCR_MIN_ASYNC (40) 105#endif /* SCSI_NCR_MIN_ASYNC */ 106 107/* 108** The maximal bus with (in log2 byte) 109** (0=8 bit, 1=16 bit) 110*/ 111 112#ifndef SCSI_NCR_MAX_WIDE 113#define SCSI_NCR_MAX_WIDE (1) 114#endif /* SCSI_NCR_MAX_WIDE */ 115 116/*========================================================== 117** 118** Configuration and Debugging 119** 120**========================================================== 121*/ 122 123/* 124** Number of targets supported by the driver. 125** n permits target numbers 0..n-1. 126** Default is 7, meaning targets #0..#6. 127** #7 .. is myself. 128*/ 129 130#define MAX_TARGET (16) 131 132/* 133** Number of logic units supported by the driver. 134** n enables logic unit numbers 0..n-1. 135** The common SCSI devices require only 136** one lun, so take 1 as the default. 137*/ 138 139#ifndef MAX_LUN 140#define MAX_LUN (8) 141#endif /* MAX_LUN */ 142 143/* 144** The maximum number of jobs scheduled for starting. 145** There should be one slot per target, and one slot 146** for each tag of each target in use. 147*/ 148 149#define MAX_START (256) 150 151/* 152** The maximum number of segments a transfer is split into. 153*/ 154 155#define MAX_SCATTER (33) 156 157/* 158** The maximum transfer length (should be >= 64k). 159** MUST NOT be greater than (MAX_SCATTER-1) * PAGE_SIZE. 160*/ 161 162#define MAX_SIZE ((MAX_SCATTER-1) * (long) PAGE_SIZE) 163 164/* 165** other 166*/ 167 168#define NCR_SNOOP_TIMEOUT (1000000) 169 170/*========================================================== 171** 172** Include files 173** 174**========================================================== 175*/ 176 177#include <sys/param.h> 178#include <sys/time.h> 179 180#ifdef _KERNEL 181#include <sys/systm.h> 182#include <sys/malloc.h> 183#include <sys/kdb.h> 184#include <sys/kernel.h> 185#include <sys/module.h> 186#include <sys/sysctl.h> 187#include <sys/bus.h> 188#include <machine/md_var.h> 189#include <machine/bus.h> 190#include <machine/resource.h> 191#include <sys/rman.h> 192#include <vm/vm.h> 193#include <vm/pmap.h> 194#include <vm/vm_extern.h> 195#endif 196 197#include <dev/pci/pcivar.h> 198#include <dev/pci/pcireg.h> 199#include <pci/ncrreg.h> 200 201#include <cam/cam.h> 202#include <cam/cam_ccb.h> 203#include <cam/cam_sim.h> 204#include <cam/cam_xpt_sim.h> 205#include <cam/cam_debug.h> 206 207#include <cam/scsi/scsi_all.h> 208#include <cam/scsi/scsi_message.h> 209 210/*========================================================== 211** 212** Debugging tags 213** 214**========================================================== 215*/ 216 217#define DEBUG_ALLOC (0x0001) 218#define DEBUG_PHASE (0x0002) 219#define DEBUG_POLL (0x0004) 220#define DEBUG_QUEUE (0x0008) 221#define DEBUG_RESULT (0x0010) 222#define DEBUG_SCATTER (0x0020) 223#define DEBUG_SCRIPT (0x0040) 224#define DEBUG_TINY (0x0080) 225#define DEBUG_TIMING (0x0100) 226#define DEBUG_NEGO (0x0200) 227#define DEBUG_TAGS (0x0400) 228#define DEBUG_FREEZE (0x0800) 229#define DEBUG_RESTART (0x1000) 230 231/* 232** Enable/Disable debug messages. 233** Can be changed at runtime too. 234*/ 235#ifdef SCSI_NCR_DEBUG 236 #define DEBUG_FLAGS ncr_debug 237#else /* SCSI_NCR_DEBUG */ 238 #define SCSI_NCR_DEBUG 0 239 #define DEBUG_FLAGS 0 240#endif /* SCSI_NCR_DEBUG */ 241 242 243 244/*========================================================== 245** 246** assert () 247** 248**========================================================== 249** 250** modified copy from 386bsd:/usr/include/sys/assert.h 251** 252**---------------------------------------------------------- 253*/ 254 255#ifdef DIAGNOSTIC 256#define assert(expression) { \ 257 if (!(expression)) { \ 258 (void)printf("assertion \"%s\" failed: " \ 259 "file \"%s\", line %d\n", \ 260 #expression, __FILE__, __LINE__); \ 261 kdb_enter(""); \ 262 } \ 263} 264#else 265#define assert(expression) { \ 266 if (!(expression)) { \ 267 (void)printf("assertion \"%s\" failed: " \ 268 "file \"%s\", line %d\n", \ 269 #expression, __FILE__, __LINE__); \ 270 } \ 271} 272#endif 273 274/*========================================================== 275** 276** Access to the controller chip. 277** 278**========================================================== 279*/ 280 281#ifdef __alpha__ 282/* XXX */ 283#undef vtophys 284#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 285#endif 286 287#define INB(r) bus_space_read_1(np->bst, np->bsh, offsetof(struct ncr_reg, r)) 288#define INW(r) bus_space_read_2(np->bst, np->bsh, offsetof(struct ncr_reg, r)) 289#define INL(r) bus_space_read_4(np->bst, np->bsh, offsetof(struct ncr_reg, r)) 290 291#define OUTB(r, val) bus_space_write_1(np->bst, np->bsh, \ 292 offsetof(struct ncr_reg, r), val) 293#define OUTW(r, val) bus_space_write_2(np->bst, np->bsh, \ 294 offsetof(struct ncr_reg, r), val) 295#define OUTL(r, val) bus_space_write_4(np->bst, np->bsh, \ 296 offsetof(struct ncr_reg, r), val) 297#define OUTL_OFF(o, val) bus_space_write_4(np->bst, np->bsh, o, val) 298 299#define INB_OFF(o) bus_space_read_1(np->bst, np->bsh, o) 300#define INW_OFF(o) bus_space_read_2(np->bst, np->bsh, o) 301#define INL_OFF(o) bus_space_read_4(np->bst, np->bsh, o) 302 303#define READSCRIPT_OFF(base, off) \ 304 (base ? *((volatile u_int32_t *)((volatile char *)base + (off))) : \ 305 bus_space_read_4(np->bst2, np->bsh2, off)) 306 307#define WRITESCRIPT_OFF(base, off, val) \ 308 do { \ 309 if (base) \ 310 *((volatile u_int32_t *) \ 311 ((volatile char *)base + (off))) = (val); \ 312 else \ 313 bus_space_write_4(np->bst2, np->bsh2, off, val); \ 314 } while (0) 315 316#define READSCRIPT(r) \ 317 READSCRIPT_OFF(np->script, offsetof(struct script, r)) 318 319#define WRITESCRIPT(r, val) \ 320 WRITESCRIPT_OFF(np->script, offsetof(struct script, r), val) 321 322/* 323** Set bit field ON, OFF 324*/ 325 326#define OUTONB(r, m) OUTB(r, INB(r) | (m)) 327#define OUTOFFB(r, m) OUTB(r, INB(r) & ~(m)) 328#define OUTONW(r, m) OUTW(r, INW(r) | (m)) 329#define OUTOFFW(r, m) OUTW(r, INW(r) & ~(m)) 330#define OUTONL(r, m) OUTL(r, INL(r) | (m)) 331#define OUTOFFL(r, m) OUTL(r, INL(r) & ~(m)) 332 333/*========================================================== 334** 335** Command control block states. 336** 337**========================================================== 338*/ 339 340#define HS_IDLE (0) 341#define HS_BUSY (1) 342#define HS_NEGOTIATE (2) /* sync/wide data transfer*/ 343#define HS_DISCONNECT (3) /* Disconnected by target */ 344 345#define HS_COMPLETE (4) 346#define HS_SEL_TIMEOUT (5) /* Selection timeout */ 347#define HS_RESET (6) /* SCSI reset */ 348#define HS_ABORTED (7) /* Transfer aborted */ 349#define HS_TIMEOUT (8) /* Software timeout */ 350#define HS_FAIL (9) /* SCSI or PCI bus errors */ 351#define HS_UNEXPECTED (10) /* Unexpected disconnect */ 352#define HS_STALL (11) /* QUEUE FULL or BUSY */ 353 354#define HS_DONEMASK (0xfc) 355 356/*========================================================== 357** 358** Software Interrupt Codes 359** 360**========================================================== 361*/ 362 363#define SIR_SENSE_RESTART (1) 364#define SIR_SENSE_FAILED (2) 365#define SIR_STALL_RESTART (3) 366#define SIR_STALL_QUEUE (4) 367#define SIR_NEGO_SYNC (5) 368#define SIR_NEGO_WIDE (6) 369#define SIR_NEGO_FAILED (7) 370#define SIR_NEGO_PROTO (8) 371#define SIR_REJECT_RECEIVED (9) 372#define SIR_REJECT_SENT (10) 373#define SIR_IGN_RESIDUE (11) 374#define SIR_MISSING_SAVE (12) 375#define SIR_MAX (12) 376 377/*========================================================== 378** 379** Extended error codes. 380** xerr_status field of struct nccb. 381** 382**========================================================== 383*/ 384 385#define XE_OK (0) 386#define XE_EXTRA_DATA (1) /* unexpected data phase */ 387#define XE_BAD_PHASE (2) /* illegal phase (4/5) */ 388 389/*========================================================== 390** 391** Negotiation status. 392** nego_status field of struct nccb. 393** 394**========================================================== 395*/ 396 397#define NS_SYNC (1) 398#define NS_WIDE (2) 399 400/*========================================================== 401** 402** XXX These are no longer used. Remove once the 403** script is updated. 404** "Special features" of targets. 405** quirks field of struct tcb. 406** actualquirks field of struct nccb. 407** 408**========================================================== 409*/ 410 411#define QUIRK_AUTOSAVE (0x01) 412#define QUIRK_NOMSG (0x02) 413#define QUIRK_NOSYNC (0x10) 414#define QUIRK_NOWIDE16 (0x20) 415#define QUIRK_NOTAGS (0x40) 416#define QUIRK_UPDATE (0x80) 417 418/*========================================================== 419** 420** Misc. 421** 422**========================================================== 423*/ 424 425#define CCB_MAGIC (0xf2691ad2) 426#define MAX_TAGS (32) /* hard limit */ 427 428/*========================================================== 429** 430** OS dependencies. 431** 432**========================================================== 433*/ 434 435#define PRINT_ADDR(ccb) xpt_print_path((ccb)->ccb_h.path) 436 437/*========================================================== 438** 439** Declaration of structs. 440** 441**========================================================== 442*/ 443 444struct tcb; 445struct lcb; 446struct nccb; 447struct ncb; 448struct script; 449 450typedef struct ncb * ncb_p; 451typedef struct tcb * tcb_p; 452typedef struct lcb * lcb_p; 453typedef struct nccb * nccb_p; 454 455struct link { 456 ncrcmd l_cmd; 457 ncrcmd l_paddr; 458}; 459 460struct usrcmd { 461 u_long target; 462 u_long lun; 463 u_long data; 464 u_long cmd; 465}; 466 467#define UC_SETSYNC 10 468#define UC_SETTAGS 11 469#define UC_SETDEBUG 12 470#define UC_SETORDER 13 471#define UC_SETWIDE 14 472#define UC_SETFLAG 15 473 474#define UF_TRACE (0x01) 475 476/*--------------------------------------- 477** 478** Timestamps for profiling 479** 480**--------------------------------------- 481*/ 482 483/* Type of the kernel variable `ticks'. XXX should be declared with the var. */ 484typedef int ticks_t; 485 486struct tstamp { 487 ticks_t start; 488 ticks_t end; 489 ticks_t select; 490 ticks_t command; 491 ticks_t data; 492 ticks_t status; 493 ticks_t disconnect; 494}; 495 496/* 497** profiling data (per device) 498*/ 499 500struct profile { 501 u_long num_trans; 502 u_long num_bytes; 503 u_long num_disc; 504 u_long num_break; 505 u_long num_int; 506 u_long num_fly; 507 u_long ms_setup; 508 u_long ms_data; 509 u_long ms_disc; 510 u_long ms_post; 511}; 512 513/*========================================================== 514** 515** Declaration of structs: target control block 516** 517**========================================================== 518*/ 519 520#define NCR_TRANS_CUR 0x01 /* Modify current neogtiation status */ 521#define NCR_TRANS_ACTIVE 0x03 /* Assume this is the active target */ 522#define NCR_TRANS_GOAL 0x04 /* Modify negotiation goal */ 523#define NCR_TRANS_USER 0x08 /* Modify user negotiation settings */ 524 525struct ncr_transinfo { 526 u_int8_t width; 527 u_int8_t period; 528 u_int8_t offset; 529}; 530 531struct ncr_target_tinfo { 532 /* Hardware version of our sync settings */ 533 u_int8_t disc_tag; 534#define NCR_CUR_DISCENB 0x01 535#define NCR_CUR_TAGENB 0x02 536#define NCR_USR_DISCENB 0x04 537#define NCR_USR_TAGENB 0x08 538 u_int8_t sval; 539 struct ncr_transinfo current; 540 struct ncr_transinfo goal; 541 struct ncr_transinfo user; 542 /* Hardware version of our wide settings */ 543 u_int8_t wval; 544}; 545 546struct tcb { 547 /* 548 ** during reselection the ncr jumps to this point 549 ** with SFBR set to the encoded target number 550 ** with bit 7 set. 551 ** if it's not this target, jump to the next. 552 ** 553 ** JUMP IF (SFBR != #target#) 554 ** @(next tcb) 555 */ 556 557 struct link jump_tcb; 558 559 /* 560 ** load the actual values for the sxfer and the scntl3 561 ** register (sync/wide mode). 562 ** 563 ** SCR_COPY (1); 564 ** @(sval field of this tcb) 565 ** @(sxfer register) 566 ** SCR_COPY (1); 567 ** @(wval field of this tcb) 568 ** @(scntl3 register) 569 */ 570 571 ncrcmd getscr[6]; 572 573 /* 574 ** if next message is "identify" 575 ** then load the message to SFBR, 576 ** else load 0 to SFBR. 577 ** 578 ** CALL 579 ** <RESEL_LUN> 580 */ 581 582 struct link call_lun; 583 584 /* 585 ** now look for the right lun. 586 ** 587 ** JUMP 588 ** @(first nccb of this lun) 589 */ 590 591 struct link jump_lcb; 592 593 /* 594 ** pointer to interrupted getcc nccb 595 */ 596 597 nccb_p hold_cp; 598 599 /* 600 ** pointer to nccb used for negotiating. 601 ** Avoid to start a nego for all queued commands 602 ** when tagged command queuing is enabled. 603 */ 604 605 nccb_p nego_cp; 606 607 /* 608 ** statistical data 609 */ 610 611 u_long transfers; 612 u_long bytes; 613 614 /* 615 ** user settable limits for sync transfer 616 ** and tagged commands. 617 */ 618 619 struct ncr_target_tinfo tinfo; 620 621 /* 622 ** the lcb's of this tcb 623 */ 624 625 lcb_p lp[MAX_LUN]; 626}; 627 628/*========================================================== 629** 630** Declaration of structs: lun control block 631** 632**========================================================== 633*/ 634 635struct lcb { 636 /* 637 ** during reselection the ncr jumps to this point 638 ** with SFBR set to the "Identify" message. 639 ** if it's not this lun, jump to the next. 640 ** 641 ** JUMP IF (SFBR != #lun#) 642 ** @(next lcb of this target) 643 */ 644 645 struct link jump_lcb; 646 647 /* 648 ** if next message is "simple tag", 649 ** then load the tag to SFBR, 650 ** else load 0 to SFBR. 651 ** 652 ** CALL 653 ** <RESEL_TAG> 654 */ 655 656 struct link call_tag; 657 658 /* 659 ** now look for the right nccb. 660 ** 661 ** JUMP 662 ** @(first nccb of this lun) 663 */ 664 665 struct link jump_nccb; 666 667 /* 668 ** start of the nccb chain 669 */ 670 671 nccb_p next_nccb; 672 673 /* 674 ** Control of tagged queueing 675 */ 676 677 u_char reqnccbs; 678 u_char reqlink; 679 u_char actlink; 680 u_char usetags; 681 u_char lasttag; 682}; 683 684/*========================================================== 685** 686** Declaration of structs: COMMAND control block 687** 688**========================================================== 689** 690** This substructure is copied from the nccb to a 691** global address after selection (or reselection) 692** and copied back before disconnect. 693** 694** These fields are accessible to the script processor. 695** 696**---------------------------------------------------------- 697*/ 698 699struct head { 700 /* 701 ** Execution of a nccb starts at this point. 702 ** It's a jump to the "SELECT" label 703 ** of the script. 704 ** 705 ** After successful selection the script 706 ** processor overwrites it with a jump to 707 ** the IDLE label of the script. 708 */ 709 710 struct link launch; 711 712 /* 713 ** Saved data pointer. 714 ** Points to the position in the script 715 ** responsible for the actual transfer 716 ** of data. 717 ** It's written after reception of a 718 ** "SAVE_DATA_POINTER" message. 719 ** The goalpointer points after 720 ** the last transfer command. 721 */ 722 723 u_int32_t savep; 724 u_int32_t lastp; 725 u_int32_t goalp; 726 727 /* 728 ** The virtual address of the nccb 729 ** containing this header. 730 */ 731 732 nccb_p cp; 733 734 /* 735 ** space for some timestamps to gather 736 ** profiling data about devices and this driver. 737 */ 738 739 struct tstamp stamp; 740 741 /* 742 ** status fields. 743 */ 744 745 u_char status[8]; 746}; 747 748/* 749** The status bytes are used by the host and the script processor. 750** 751** The first four byte are copied to the scratchb register 752** (declared as scr0..scr3 in ncr_reg.h) just after the select/reselect, 753** and copied back just after disconnecting. 754** Inside the script the XX_REG are used. 755** 756** The last four bytes are used inside the script by "COPY" commands. 757** Because source and destination must have the same alignment 758** in a longword, the fields HAVE to be at the choosen offsets. 759** xerr_st (4) 0 (0x34) scratcha 760** sync_st (5) 1 (0x05) sxfer 761** wide_st (7) 3 (0x03) scntl3 762*/ 763 764/* 765** First four bytes (script) 766*/ 767#define QU_REG scr0 768#define HS_REG scr1 769#define HS_PRT nc_scr1 770#define SS_REG scr2 771#define PS_REG scr3 772 773/* 774** First four bytes (host) 775*/ 776#define actualquirks phys.header.status[0] 777#define host_status phys.header.status[1] 778#define s_status phys.header.status[2] 779#define parity_status phys.header.status[3] 780 781/* 782** Last four bytes (script) 783*/ 784#define xerr_st header.status[4] /* MUST be ==0 mod 4 */ 785#define sync_st header.status[5] /* MUST be ==1 mod 4 */ 786#define nego_st header.status[6] 787#define wide_st header.status[7] /* MUST be ==3 mod 4 */ 788 789/* 790** Last four bytes (host) 791*/ 792#define xerr_status phys.xerr_st 793#define sync_status phys.sync_st 794#define nego_status phys.nego_st 795#define wide_status phys.wide_st 796 797/*========================================================== 798** 799** Declaration of structs: Data structure block 800** 801**========================================================== 802** 803** During execution of a nccb by the script processor, 804** the DSA (data structure address) register points 805** to this substructure of the nccb. 806** This substructure contains the header with 807** the script-processor-changable data and 808** data blocks for the indirect move commands. 809** 810**---------------------------------------------------------- 811*/ 812 813struct dsb { 814 815 /* 816 ** Header. 817 ** Has to be the first entry, 818 ** because it's jumped to by the 819 ** script processor 820 */ 821 822 struct head header; 823 824 /* 825 ** Table data for Script 826 */ 827 828 struct scr_tblsel select; 829 struct scr_tblmove smsg ; 830 struct scr_tblmove smsg2 ; 831 struct scr_tblmove cmd ; 832 struct scr_tblmove scmd ; 833 struct scr_tblmove sense ; 834 struct scr_tblmove data [MAX_SCATTER]; 835}; 836 837/*========================================================== 838** 839** Declaration of structs: Command control block. 840** 841**========================================================== 842** 843** During execution of a nccb by the script processor, 844** the DSA (data structure address) register points 845** to this substructure of the nccb. 846** This substructure contains the header with 847** the script-processor-changable data and then 848** data blocks for the indirect move commands. 849** 850**---------------------------------------------------------- 851*/ 852 853 854struct nccb { 855 /* 856 ** This filler ensures that the global header is 857 ** cache line size aligned. 858 */ 859 ncrcmd filler[4]; 860 861 /* 862 ** during reselection the ncr jumps to this point. 863 ** If a "SIMPLE_TAG" message was received, 864 ** then SFBR is set to the tag. 865 ** else SFBR is set to 0 866 ** If looking for another tag, jump to the next nccb. 867 ** 868 ** JUMP IF (SFBR != #TAG#) 869 ** @(next nccb of this lun) 870 */ 871 872 struct link jump_nccb; 873 874 /* 875 ** After execution of this call, the return address 876 ** (in the TEMP register) points to the following 877 ** data structure block. 878 ** So copy it to the DSA register, and start 879 ** processing of this data structure. 880 ** 881 ** CALL 882 ** <RESEL_TMP> 883 */ 884 885 struct link call_tmp; 886 887 /* 888 ** This is the data structure which is 889 ** to be executed by the script processor. 890 */ 891 892 struct dsb phys; 893 894 /* 895 ** If a data transfer phase is terminated too early 896 ** (after reception of a message (i.e. DISCONNECT)), 897 ** we have to prepare a mini script to transfer 898 ** the rest of the data. 899 */ 900 901 ncrcmd patch[8]; 902 903 /* 904 ** The general SCSI driver provides a 905 ** pointer to a control block. 906 */ 907 908 union ccb *ccb; 909 910 /* 911 ** We prepare a message to be sent after selection, 912 ** and a second one to be sent after getcc selection. 913 ** Contents are IDENTIFY and SIMPLE_TAG. 914 ** While negotiating sync or wide transfer, 915 ** a SDTM or WDTM message is appended. 916 */ 917 918 u_char scsi_smsg [8]; 919 u_char scsi_smsg2[8]; 920 921 /* 922 ** Lock this nccb. 923 ** Flag is used while looking for a free nccb. 924 */ 925 926 u_long magic; 927 928 /* 929 ** Physical address of this instance of nccb 930 */ 931 932 u_long p_nccb; 933 934 /* 935 ** Completion time out for this job. 936 ** It's set to time of start + allowed number of seconds. 937 */ 938 939 time_t tlimit; 940 941 /* 942 ** All nccbs of one hostadapter are chained. 943 */ 944 945 nccb_p link_nccb; 946 947 /* 948 ** All nccbs of one target/lun are chained. 949 */ 950 951 nccb_p next_nccb; 952 953 /* 954 ** Sense command 955 */ 956 957 u_char sensecmd[6]; 958 959 /* 960 ** Tag for this transfer. 961 ** It's patched into jump_nccb. 962 ** If it's not zero, a SIMPLE_TAG 963 ** message is included in smsg. 964 */ 965 966 u_char tag; 967}; 968 969#define CCB_PHYS(cp,lbl) (cp->p_nccb + offsetof(struct nccb, lbl)) 970 971/*========================================================== 972** 973** Declaration of structs: NCR device descriptor 974** 975**========================================================== 976*/ 977 978struct ncb { 979 /* 980 ** The global header. 981 ** Accessible to both the host and the 982 ** script-processor. 983 ** We assume it is cache line size aligned. 984 */ 985 struct head header; 986 987 int unit; 988 989 /*----------------------------------------------- 990 ** Scripts .. 991 **----------------------------------------------- 992 ** 993 ** During reselection the ncr jumps to this point. 994 ** The SFBR register is loaded with the encoded target id. 995 ** 996 ** Jump to the first target. 997 ** 998 ** JUMP 999 ** @(next tcb) 1000 */ 1001 struct link jump_tcb; 1002 1003 /*----------------------------------------------- 1004 ** Configuration .. 1005 **----------------------------------------------- 1006 ** 1007 ** virtual and physical addresses 1008 ** of the 53c810 chip. 1009 */ 1010 int reg_rid; 1011 struct resource *reg_res; 1012 bus_space_tag_t bst; 1013 bus_space_handle_t bsh; 1014 1015 int sram_rid; 1016 struct resource *sram_res; 1017 bus_space_tag_t bst2; 1018 bus_space_handle_t bsh2; 1019 1020 struct resource *irq_res; 1021 void *irq_handle; 1022 1023 /* 1024 ** Scripts instance virtual address. 1025 */ 1026 struct script *script; 1027 struct scripth *scripth; 1028 1029 /* 1030 ** Scripts instance physical address. 1031 */ 1032 u_long p_script; 1033 u_long p_scripth; 1034 1035 /* 1036 ** The SCSI address of the host adapter. 1037 */ 1038 u_char myaddr; 1039 1040 /* 1041 ** timing parameters 1042 */ 1043 u_char minsync; /* Minimum sync period factor */ 1044 u_char maxsync; /* Maximum sync period factor */ 1045 u_char maxoffs; /* Max scsi offset */ 1046 u_char clock_divn; /* Number of clock divisors */ 1047 u_long clock_khz; /* SCSI clock frequency in KHz */ 1048 u_long features; /* Chip features map */ 1049 u_char multiplier; /* Clock multiplier (1,2,4) */ 1050 1051 u_char maxburst; /* log base 2 of dwords burst */ 1052 1053 /* 1054 ** BIOS supplied PCI bus options 1055 */ 1056 u_char rv_scntl3; 1057 u_char rv_dcntl; 1058 u_char rv_dmode; 1059 u_char rv_ctest3; 1060 u_char rv_ctest4; 1061 u_char rv_ctest5; 1062 u_char rv_gpcntl; 1063 u_char rv_stest2; 1064 1065 /*----------------------------------------------- 1066 ** CAM SIM information for this instance 1067 **----------------------------------------------- 1068 */ 1069 1070 struct cam_sim *sim; 1071 struct cam_path *path; 1072 1073 /*----------------------------------------------- 1074 ** Job control 1075 **----------------------------------------------- 1076 ** 1077 ** Commands from user 1078 */ 1079 struct usrcmd user; 1080 1081 /* 1082 ** Target data 1083 */ 1084 struct tcb target[MAX_TARGET]; 1085 1086 /* 1087 ** Start queue. 1088 */ 1089 u_int32_t squeue [MAX_START]; 1090 u_short squeueput; 1091 1092 /* 1093 ** Timeout handler 1094 */ 1095 time_t heartbeat; 1096 u_short ticks; 1097 u_short latetime; 1098 time_t lasttime; 1099 struct callout_handle timeout_ch; 1100 1101 /*----------------------------------------------- 1102 ** Debug and profiling 1103 **----------------------------------------------- 1104 ** 1105 ** register dump 1106 */ 1107 struct ncr_reg regdump; 1108 time_t regtime; 1109 1110 /* 1111 ** Profiling data 1112 */ 1113 struct profile profile; 1114 u_long disc_phys; 1115 u_long disc_ref; 1116 1117 /* 1118 ** Head of list of all nccbs for this controller. 1119 */ 1120 nccb_p link_nccb; 1121 1122 /* 1123 ** message buffers. 1124 ** Should be longword aligned, 1125 ** because they're written with a 1126 ** COPY script command. 1127 */ 1128 u_char msgout[8]; 1129 u_char msgin [8]; 1130 u_int32_t lastmsg; 1131 1132 /* 1133 ** Buffer for STATUS_IN phase. 1134 */ 1135 u_char scratch; 1136 1137 /* 1138 ** controller chip dependent maximal transfer width. 1139 */ 1140 u_char maxwide; 1141 1142#ifdef NCR_IOMAPPED 1143 /* 1144 ** address of the ncr control registers in io space 1145 */ 1146 pci_port_t port; 1147#endif 1148}; 1149 1150#define NCB_SCRIPT_PHYS(np,lbl) (np->p_script + offsetof (struct script, lbl)) 1151#define NCB_SCRIPTH_PHYS(np,lbl) (np->p_scripth + offsetof (struct scripth,lbl)) 1152 1153/*========================================================== 1154** 1155** 1156** Script for NCR-Processor. 1157** 1158** Use ncr_script_fill() to create the variable parts. 1159** Use ncr_script_copy_and_bind() to make a copy and 1160** bind to physical addresses. 1161** 1162** 1163**========================================================== 1164** 1165** We have to know the offsets of all labels before 1166** we reach them (for forward jumps). 1167** Therefore we declare a struct here. 1168** If you make changes inside the script, 1169** DONT FORGET TO CHANGE THE LENGTHS HERE! 1170** 1171**---------------------------------------------------------- 1172*/ 1173 1174/* 1175** Script fragments which are loaded into the on-board RAM 1176** of 825A, 875 and 895 chips. 1177*/ 1178struct script { 1179 ncrcmd start [ 7]; 1180 ncrcmd start0 [ 2]; 1181 ncrcmd start1 [ 3]; 1182 ncrcmd startpos [ 1]; 1183 ncrcmd trysel [ 8]; 1184 ncrcmd skip [ 8]; 1185 ncrcmd skip2 [ 3]; 1186 ncrcmd idle [ 2]; 1187 ncrcmd select [ 18]; 1188 ncrcmd prepare [ 4]; 1189 ncrcmd loadpos [ 14]; 1190 ncrcmd prepare2 [ 24]; 1191 ncrcmd setmsg [ 5]; 1192 ncrcmd clrack [ 2]; 1193 ncrcmd dispatch [ 33]; 1194 ncrcmd no_data [ 17]; 1195 ncrcmd checkatn [ 10]; 1196 ncrcmd command [ 15]; 1197 ncrcmd status [ 27]; 1198 ncrcmd msg_in [ 26]; 1199 ncrcmd msg_bad [ 6]; 1200 ncrcmd complete [ 13]; 1201 ncrcmd cleanup [ 12]; 1202 ncrcmd cleanup0 [ 9]; 1203 ncrcmd signal [ 12]; 1204 ncrcmd save_dp [ 5]; 1205 ncrcmd restore_dp [ 5]; 1206 ncrcmd disconnect [ 12]; 1207 ncrcmd disconnect0 [ 5]; 1208 ncrcmd disconnect1 [ 23]; 1209 ncrcmd msg_out [ 9]; 1210 ncrcmd msg_out_done [ 7]; 1211 ncrcmd badgetcc [ 6]; 1212 ncrcmd reselect [ 8]; 1213 ncrcmd reselect1 [ 8]; 1214 ncrcmd reselect2 [ 8]; 1215 ncrcmd resel_tmp [ 5]; 1216 ncrcmd resel_lun [ 18]; 1217 ncrcmd resel_tag [ 24]; 1218 ncrcmd data_in [MAX_SCATTER * 4 + 7]; 1219 ncrcmd data_out [MAX_SCATTER * 4 + 7]; 1220}; 1221 1222/* 1223** Script fragments which stay in main memory for all chips. 1224*/ 1225struct scripth { 1226 ncrcmd tryloop [MAX_START*5+2]; 1227 ncrcmd msg_parity [ 6]; 1228 ncrcmd msg_reject [ 8]; 1229 ncrcmd msg_ign_residue [ 32]; 1230 ncrcmd msg_extended [ 18]; 1231 ncrcmd msg_ext_2 [ 18]; 1232 ncrcmd msg_wdtr [ 27]; 1233 ncrcmd msg_ext_3 [ 18]; 1234 ncrcmd msg_sdtr [ 27]; 1235 ncrcmd msg_out_abort [ 10]; 1236 ncrcmd getcc [ 4]; 1237 ncrcmd getcc1 [ 5]; 1238#ifdef NCR_GETCC_WITHMSG 1239 ncrcmd getcc2 [ 29]; 1240#else 1241 ncrcmd getcc2 [ 14]; 1242#endif 1243 ncrcmd getcc3 [ 6]; 1244 ncrcmd aborttag [ 4]; 1245 ncrcmd abort [ 22]; 1246 ncrcmd snooptest [ 9]; 1247 ncrcmd snoopend [ 2]; 1248}; 1249 1250/*========================================================== 1251** 1252** 1253** Function headers. 1254** 1255** 1256**========================================================== 1257*/ 1258 1259#ifdef _KERNEL 1260static nccb_p ncr_alloc_nccb (ncb_p np, u_long target, u_long lun); 1261static void ncr_complete (ncb_p np, nccb_p cp); 1262static int ncr_delta (int * from, int * to); 1263static void ncr_exception (ncb_p np); 1264static void ncr_free_nccb (ncb_p np, nccb_p cp); 1265static void ncr_freeze_devq (ncb_p np, struct cam_path *path); 1266static void ncr_selectclock (ncb_p np, u_char scntl3); 1267static void ncr_getclock (ncb_p np, u_char multiplier); 1268static nccb_p ncr_get_nccb (ncb_p np, u_long t,u_long l); 1269#if 0 1270static u_int32_t ncr_info (int unit); 1271#endif 1272static void ncr_init (ncb_p np, char * msg, u_long code); 1273static void ncr_intr (void *vnp); 1274static void ncr_int_ma (ncb_p np, u_char dstat); 1275static void ncr_int_sir (ncb_p np); 1276static void ncr_int_sto (ncb_p np); 1277#if 0 1278static void ncr_min_phys (struct buf *bp); 1279#endif 1280static void ncr_poll (struct cam_sim *sim); 1281static void ncb_profile (ncb_p np, nccb_p cp); 1282static void ncr_script_copy_and_bind 1283 (ncb_p np, ncrcmd *src, ncrcmd *dst, int len); 1284static void ncr_script_fill (struct script * scr, struct scripth *scrh); 1285static int ncr_scatter (struct dsb* phys, vm_offset_t vaddr, 1286 vm_size_t datalen); 1287static void ncr_getsync (ncb_p np, u_char sfac, u_char *fakp, 1288 u_char *scntl3p); 1289static void ncr_setsync (ncb_p np, nccb_p cp,u_char scntl3,u_char sxfer, 1290 u_char period); 1291static void ncr_setwide (ncb_p np, nccb_p cp, u_char wide, u_char ack); 1292static int ncr_show_msg (u_char * msg); 1293static int ncr_snooptest (ncb_p np); 1294static void ncr_action (struct cam_sim *sim, union ccb *ccb); 1295static void ncr_timeout (void *arg); 1296static void ncr_wakeup (ncb_p np, u_long code); 1297 1298static int ncr_probe (device_t dev); 1299static int ncr_attach (device_t dev); 1300 1301#endif /* _KERNEL */ 1302 1303/*========================================================== 1304** 1305** 1306** Global static data. 1307** 1308** 1309**========================================================== 1310*/ 1311 1312static const u_long ncr_version = NCR_VERSION * 11 1313 + (u_long) sizeof (struct ncb) * 7 1314 + (u_long) sizeof (struct nccb) * 5 1315 + (u_long) sizeof (struct lcb) * 3 1316 + (u_long) sizeof (struct tcb) * 2; 1317 1318#ifdef _KERNEL 1319 1320static int ncr_debug = SCSI_NCR_DEBUG; 1321SYSCTL_INT(_debug, OID_AUTO, ncr_debug, CTLFLAG_RW, &ncr_debug, 0, ""); 1322 1323static int ncr_cache; /* to be aligned _NOT_ static */ 1324 1325/*========================================================== 1326** 1327** 1328** Global static data: auto configure 1329** 1330** 1331**========================================================== 1332*/ 1333 1334#define NCR_810_ID (0x00011000ul) 1335#define NCR_815_ID (0x00041000ul) 1336#define NCR_820_ID (0x00021000ul) 1337#define NCR_825_ID (0x00031000ul) 1338#define NCR_860_ID (0x00061000ul) 1339#define NCR_875_ID (0x000f1000ul) 1340#define NCR_875_ID2 (0x008f1000ul) 1341#define NCR_885_ID (0x000d1000ul) 1342#define NCR_895_ID (0x000c1000ul) 1343#define NCR_896_ID (0x000b1000ul) 1344#define NCR_895A_ID (0x00121000ul) 1345#define NCR_1510D_ID (0x000a1000ul) 1346 1347 1348static char *ncr_name (ncb_p np) 1349{ 1350 static char name[10]; 1351 snprintf(name, sizeof(name), "ncr%d", np->unit); 1352 return (name); 1353} 1354 1355/*========================================================== 1356** 1357** 1358** Scripts for NCR-Processor. 1359** 1360** Use ncr_script_bind for binding to physical addresses. 1361** 1362** 1363**========================================================== 1364** 1365** NADDR generates a reference to a field of the controller data. 1366** PADDR generates a reference to another part of the script. 1367** RADDR generates a reference to a script processor register. 1368** FADDR generates a reference to a script processor register 1369** with offset. 1370** 1371**---------------------------------------------------------- 1372*/ 1373 1374#define RELOC_SOFTC 0x40000000 1375#define RELOC_LABEL 0x50000000 1376#define RELOC_REGISTER 0x60000000 1377#define RELOC_KVAR 0x70000000 1378#define RELOC_LABELH 0x80000000 1379#define RELOC_MASK 0xf0000000 1380 1381#define NADDR(label) (RELOC_SOFTC | offsetof(struct ncb, label)) 1382#define PADDR(label) (RELOC_LABEL | offsetof(struct script, label)) 1383#define PADDRH(label) (RELOC_LABELH | offsetof(struct scripth, label)) 1384#define RADDR(label) (RELOC_REGISTER | REG(label)) 1385#define FADDR(label,ofs)(RELOC_REGISTER | ((REG(label))+(ofs))) 1386#define KVAR(which) (RELOC_KVAR | (which)) 1387 1388#define KVAR_SECOND (0) 1389#define KVAR_TICKS (1) 1390#define KVAR_NCR_CACHE (2) 1391 1392#define SCRIPT_KVAR_FIRST (0) 1393#define SCRIPT_KVAR_LAST (3) 1394 1395/* 1396 * Kernel variables referenced in the scripts. 1397 * THESE MUST ALL BE ALIGNED TO A 4-BYTE BOUNDARY. 1398 */ 1399static void *script_kvars[] = 1400 { &time_second, &ticks, &ncr_cache }; 1401 1402static struct script script0 = { 1403/*--------------------------< START >-----------------------*/ { 1404 /* 1405 ** Claim to be still alive ... 1406 */ 1407 SCR_COPY (sizeof (((struct ncb *)0)->heartbeat)), 1408 KVAR (KVAR_SECOND), 1409 NADDR (heartbeat), 1410 /* 1411 ** Make data structure address invalid. 1412 ** clear SIGP. 1413 */ 1414 SCR_LOAD_REG (dsa, 0xff), 1415 0, 1416 SCR_FROM_REG (ctest2), 1417 0, 1418}/*-------------------------< START0 >----------------------*/,{ 1419 /* 1420 ** Hook for interrupted GetConditionCode. 1421 ** Will be patched to ... IFTRUE by 1422 ** the interrupt handler. 1423 */ 1424 SCR_INT ^ IFFALSE (0), 1425 SIR_SENSE_RESTART, 1426 1427}/*-------------------------< START1 >----------------------*/,{ 1428 /* 1429 ** Hook for stalled start queue. 1430 ** Will be patched to IFTRUE by the interrupt handler. 1431 */ 1432 SCR_INT ^ IFFALSE (0), 1433 SIR_STALL_RESTART, 1434 /* 1435 ** Then jump to a certain point in tryloop. 1436 ** Due to the lack of indirect addressing the code 1437 ** is self modifying here. 1438 */ 1439 SCR_JUMP, 1440}/*-------------------------< STARTPOS >--------------------*/,{ 1441 PADDRH(tryloop), 1442 1443}/*-------------------------< TRYSEL >----------------------*/,{ 1444 /* 1445 ** Now: 1446 ** DSA: Address of a Data Structure 1447 ** or Address of the IDLE-Label. 1448 ** 1449 ** TEMP: Address of a script, which tries to 1450 ** start the NEXT entry. 1451 ** 1452 ** Save the TEMP register into the SCRATCHA register. 1453 ** Then copy the DSA to TEMP and RETURN. 1454 ** This is kind of an indirect jump. 1455 ** (The script processor has NO stack, so the 1456 ** CALL is actually a jump and link, and the 1457 ** RETURN is an indirect jump.) 1458 ** 1459 ** If the slot was empty, DSA contains the address 1460 ** of the IDLE part of this script. The processor 1461 ** jumps to IDLE and waits for a reselect. 1462 ** It will wake up and try the same slot again 1463 ** after the SIGP bit becomes set by the host. 1464 ** 1465 ** If the slot was not empty, DSA contains 1466 ** the address of the phys-part of a nccb. 1467 ** The processor jumps to this address. 1468 ** phys starts with head, 1469 ** head starts with launch, 1470 ** so actually the processor jumps to 1471 ** the lauch part. 1472 ** If the entry is scheduled for execution, 1473 ** then launch contains a jump to SELECT. 1474 ** If it's not scheduled, it contains a jump to IDLE. 1475 */ 1476 SCR_COPY (4), 1477 RADDR (temp), 1478 RADDR (scratcha), 1479 SCR_COPY (4), 1480 RADDR (dsa), 1481 RADDR (temp), 1482 SCR_RETURN, 1483 0 1484 1485}/*-------------------------< SKIP >------------------------*/,{ 1486 /* 1487 ** This entry has been canceled. 1488 ** Next time use the next slot. 1489 */ 1490 SCR_COPY (4), 1491 RADDR (scratcha), 1492 PADDR (startpos), 1493 /* 1494 ** patch the launch field. 1495 ** should look like an idle process. 1496 */ 1497 SCR_COPY_F (4), 1498 RADDR (dsa), 1499 PADDR (skip2), 1500 SCR_COPY (8), 1501 PADDR (idle), 1502}/*-------------------------< SKIP2 >-----------------------*/,{ 1503 0, 1504 SCR_JUMP, 1505 PADDR(start), 1506}/*-------------------------< IDLE >------------------------*/,{ 1507 /* 1508 ** Nothing to do? 1509 ** Wait for reselect. 1510 */ 1511 SCR_JUMP, 1512 PADDR(reselect), 1513 1514}/*-------------------------< SELECT >----------------------*/,{ 1515 /* 1516 ** DSA contains the address of a scheduled 1517 ** data structure. 1518 ** 1519 ** SCRATCHA contains the address of the script, 1520 ** which starts the next entry. 1521 ** 1522 ** Set Initiator mode. 1523 ** 1524 ** (Target mode is left as an exercise for the reader) 1525 */ 1526 1527 SCR_CLR (SCR_TRG), 1528 0, 1529 SCR_LOAD_REG (HS_REG, 0xff), 1530 0, 1531 1532 /* 1533 ** And try to select this target. 1534 */ 1535 SCR_SEL_TBL_ATN ^ offsetof (struct dsb, select), 1536 PADDR (reselect), 1537 1538 /* 1539 ** Now there are 4 possibilities: 1540 ** 1541 ** (1) The ncr looses arbitration. 1542 ** This is ok, because it will try again, 1543 ** when the bus becomes idle. 1544 ** (But beware of the timeout function!) 1545 ** 1546 ** (2) The ncr is reselected. 1547 ** Then the script processor takes the jump 1548 ** to the RESELECT label. 1549 ** 1550 ** (3) The ncr completes the selection. 1551 ** Then it will execute the next statement. 1552 ** 1553 ** (4) There is a selection timeout. 1554 ** Then the ncr should interrupt the host and stop. 1555 ** Unfortunately, it seems to continue execution 1556 ** of the script. But it will fail with an 1557 ** IID-interrupt on the next WHEN. 1558 */ 1559 1560 SCR_JUMPR ^ IFTRUE (WHEN (SCR_MSG_IN)), 1561 0, 1562 1563 /* 1564 ** Send the IDENTIFY and SIMPLE_TAG messages 1565 ** (and the MSG_EXT_SDTR message) 1566 */ 1567 SCR_MOVE_TBL ^ SCR_MSG_OUT, 1568 offsetof (struct dsb, smsg), 1569#ifdef undef /* XXX better fail than try to deal with this ... */ 1570 SCR_JUMPR ^ IFTRUE (WHEN (SCR_MSG_OUT)), 1571 -16, 1572#endif 1573 SCR_CLR (SCR_ATN), 1574 0, 1575 SCR_COPY (1), 1576 RADDR (sfbr), 1577 NADDR (lastmsg), 1578 /* 1579 ** Selection complete. 1580 ** Next time use the next slot. 1581 */ 1582 SCR_COPY (4), 1583 RADDR (scratcha), 1584 PADDR (startpos), 1585}/*-------------------------< PREPARE >----------------------*/,{ 1586 /* 1587 ** The ncr doesn't have an indirect load 1588 ** or store command. So we have to 1589 ** copy part of the control block to a 1590 ** fixed place, where we can access it. 1591 ** 1592 ** We patch the address part of a 1593 ** COPY command with the DSA-register. 1594 */ 1595 SCR_COPY_F (4), 1596 RADDR (dsa), 1597 PADDR (loadpos), 1598 /* 1599 ** then we do the actual copy. 1600 */ 1601 SCR_COPY (sizeof (struct head)), 1602 /* 1603 ** continued after the next label ... 1604 */ 1605 1606}/*-------------------------< LOADPOS >---------------------*/,{ 1607 0, 1608 NADDR (header), 1609 /* 1610 ** Mark this nccb as not scheduled. 1611 */ 1612 SCR_COPY (8), 1613 PADDR (idle), 1614 NADDR (header.launch), 1615 /* 1616 ** Set a time stamp for this selection 1617 */ 1618 SCR_COPY (sizeof (ticks)), 1619 KVAR (KVAR_TICKS), 1620 NADDR (header.stamp.select), 1621 /* 1622 ** load the savep (saved pointer) into 1623 ** the TEMP register (actual pointer) 1624 */ 1625 SCR_COPY (4), 1626 NADDR (header.savep), 1627 RADDR (temp), 1628 /* 1629 ** Initialize the status registers 1630 */ 1631 SCR_COPY (4), 1632 NADDR (header.status), 1633 RADDR (scr0), 1634 1635}/*-------------------------< PREPARE2 >---------------------*/,{ 1636 /* 1637 ** Load the synchronous mode register 1638 */ 1639 SCR_COPY (1), 1640 NADDR (sync_st), 1641 RADDR (sxfer), 1642 /* 1643 ** Load the wide mode and timing register 1644 */ 1645 SCR_COPY (1), 1646 NADDR (wide_st), 1647 RADDR (scntl3), 1648 /* 1649 ** Initialize the msgout buffer with a NOOP message. 1650 */ 1651 SCR_LOAD_REG (scratcha, MSG_NOOP), 1652 0, 1653 SCR_COPY (1), 1654 RADDR (scratcha), 1655 NADDR (msgout), 1656 SCR_COPY (1), 1657 RADDR (scratcha), 1658 NADDR (msgin), 1659 /* 1660 ** Message in phase ? 1661 */ 1662 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)), 1663 PADDR (dispatch), 1664 /* 1665 ** Extended or reject message ? 1666 */ 1667 SCR_FROM_REG (sbdl), 1668 0, 1669 SCR_JUMP ^ IFTRUE (DATA (MSG_EXTENDED)), 1670 PADDR (msg_in), 1671 SCR_JUMP ^ IFTRUE (DATA (MSG_MESSAGE_REJECT)), 1672 PADDRH (msg_reject), 1673 /* 1674 ** normal processing 1675 */ 1676 SCR_JUMP, 1677 PADDR (dispatch), 1678}/*-------------------------< SETMSG >----------------------*/,{ 1679 SCR_COPY (1), 1680 RADDR (scratcha), 1681 NADDR (msgout), 1682 SCR_SET (SCR_ATN), 1683 0, 1684}/*-------------------------< CLRACK >----------------------*/,{ 1685 /* 1686 ** Terminate possible pending message phase. 1687 */ 1688 SCR_CLR (SCR_ACK), 1689 0, 1690 1691}/*-----------------------< DISPATCH >----------------------*/,{ 1692 SCR_FROM_REG (HS_REG), 1693 0, 1694 SCR_INT ^ IFTRUE (DATA (HS_NEGOTIATE)), 1695 SIR_NEGO_FAILED, 1696 /* 1697 ** remove bogus output signals 1698 */ 1699 SCR_REG_REG (socl, SCR_AND, CACK|CATN), 1700 0, 1701 SCR_RETURN ^ IFTRUE (WHEN (SCR_DATA_OUT)), 1702 0, 1703 SCR_RETURN ^ IFTRUE (IF (SCR_DATA_IN)), 1704 0, 1705 SCR_JUMP ^ IFTRUE (IF (SCR_MSG_OUT)), 1706 PADDR (msg_out), 1707 SCR_JUMP ^ IFTRUE (IF (SCR_MSG_IN)), 1708 PADDR (msg_in), 1709 SCR_JUMP ^ IFTRUE (IF (SCR_COMMAND)), 1710 PADDR (command), 1711 SCR_JUMP ^ IFTRUE (IF (SCR_STATUS)), 1712 PADDR (status), 1713 /* 1714 ** Discard one illegal phase byte, if required. 1715 */ 1716 SCR_LOAD_REG (scratcha, XE_BAD_PHASE), 1717 0, 1718 SCR_COPY (1), 1719 RADDR (scratcha), 1720 NADDR (xerr_st), 1721 SCR_JUMPR ^ IFFALSE (IF (SCR_ILG_OUT)), 1722 8, 1723 SCR_MOVE_ABS (1) ^ SCR_ILG_OUT, 1724 NADDR (scratch), 1725 SCR_JUMPR ^ IFFALSE (IF (SCR_ILG_IN)), 1726 8, 1727 SCR_MOVE_ABS (1) ^ SCR_ILG_IN, 1728 NADDR (scratch), 1729 SCR_JUMP, 1730 PADDR (dispatch), 1731 1732}/*-------------------------< NO_DATA >--------------------*/,{ 1733 /* 1734 ** The target wants to tranfer too much data 1735 ** or in the wrong direction. 1736 ** Remember that in extended error. 1737 */ 1738 SCR_LOAD_REG (scratcha, XE_EXTRA_DATA), 1739 0, 1740 SCR_COPY (1), 1741 RADDR (scratcha), 1742 NADDR (xerr_st), 1743 /* 1744 ** Discard one data byte, if required. 1745 */ 1746 SCR_JUMPR ^ IFFALSE (WHEN (SCR_DATA_OUT)), 1747 8, 1748 SCR_MOVE_ABS (1) ^ SCR_DATA_OUT, 1749 NADDR (scratch), 1750 SCR_JUMPR ^ IFFALSE (IF (SCR_DATA_IN)), 1751 8, 1752 SCR_MOVE_ABS (1) ^ SCR_DATA_IN, 1753 NADDR (scratch), 1754 /* 1755 ** .. and repeat as required. 1756 */ 1757 SCR_CALL, 1758 PADDR (dispatch), 1759 SCR_JUMP, 1760 PADDR (no_data), 1761}/*-------------------------< CHECKATN >--------------------*/,{ 1762 /* 1763 ** If AAP (bit 1 of scntl0 register) is set 1764 ** and a parity error is detected, 1765 ** the script processor asserts ATN. 1766 ** 1767 ** The target should switch to a MSG_OUT phase 1768 ** to get the message. 1769 */ 1770 SCR_FROM_REG (socl), 1771 0, 1772 SCR_JUMP ^ IFFALSE (MASK (CATN, CATN)), 1773 PADDR (dispatch), 1774 /* 1775 ** count it 1776 */ 1777 SCR_REG_REG (PS_REG, SCR_ADD, 1), 1778 0, 1779 /* 1780 ** Prepare a MSG_INITIATOR_DET_ERR message 1781 ** (initiator detected error). 1782 ** The target should retry the transfer. 1783 */ 1784 SCR_LOAD_REG (scratcha, MSG_INITIATOR_DET_ERR), 1785 0, 1786 SCR_JUMP, 1787 PADDR (setmsg), 1788 1789}/*-------------------------< COMMAND >--------------------*/,{ 1790 /* 1791 ** If this is not a GETCC transfer ... 1792 */ 1793 SCR_FROM_REG (SS_REG), 1794 0, 1795/*<<<*/ SCR_JUMPR ^ IFTRUE (DATA (SCSI_STATUS_CHECK_COND)), 1796 28, 1797 /* 1798 ** ... set a timestamp ... 1799 */ 1800 SCR_COPY (sizeof (ticks)), 1801 KVAR (KVAR_TICKS), 1802 NADDR (header.stamp.command), 1803 /* 1804 ** ... and send the command 1805 */ 1806 SCR_MOVE_TBL ^ SCR_COMMAND, 1807 offsetof (struct dsb, cmd), 1808 SCR_JUMP, 1809 PADDR (dispatch), 1810 /* 1811 ** Send the GETCC command 1812 */ 1813/*>>>*/ SCR_MOVE_TBL ^ SCR_COMMAND, 1814 offsetof (struct dsb, scmd), 1815 SCR_JUMP, 1816 PADDR (dispatch), 1817 1818}/*-------------------------< STATUS >--------------------*/,{ 1819 /* 1820 ** set the timestamp. 1821 */ 1822 SCR_COPY (sizeof (ticks)), 1823 KVAR (KVAR_TICKS), 1824 NADDR (header.stamp.status), 1825 /* 1826 ** If this is a GETCC transfer, 1827 */ 1828 SCR_FROM_REG (SS_REG), 1829 0, 1830/*<<<*/ SCR_JUMPR ^ IFFALSE (DATA (SCSI_STATUS_CHECK_COND)), 1831 40, 1832 /* 1833 ** get the status 1834 */ 1835 SCR_MOVE_ABS (1) ^ SCR_STATUS, 1836 NADDR (scratch), 1837 /* 1838 ** Save status to scsi_status. 1839 ** Mark as complete. 1840 ** And wait for disconnect. 1841 */ 1842 SCR_TO_REG (SS_REG), 1843 0, 1844 SCR_REG_REG (SS_REG, SCR_OR, SCSI_STATUS_SENSE), 1845 0, 1846 SCR_LOAD_REG (HS_REG, HS_COMPLETE), 1847 0, 1848 SCR_JUMP, 1849 PADDR (checkatn), 1850 /* 1851 ** If it was no GETCC transfer, 1852 ** save the status to scsi_status. 1853 */ 1854/*>>>*/ SCR_MOVE_ABS (1) ^ SCR_STATUS, 1855 NADDR (scratch), 1856 SCR_TO_REG (SS_REG), 1857 0, 1858 /* 1859 ** if it was no check condition ... 1860 */ 1861 SCR_JUMP ^ IFTRUE (DATA (SCSI_STATUS_CHECK_COND)), 1862 PADDR (checkatn), 1863 /* 1864 ** ... mark as complete. 1865 */ 1866 SCR_LOAD_REG (HS_REG, HS_COMPLETE), 1867 0, 1868 SCR_JUMP, 1869 PADDR (checkatn), 1870 1871}/*-------------------------< MSG_IN >--------------------*/,{ 1872 /* 1873 ** Get the first byte of the message 1874 ** and save it to SCRATCHA. 1875 ** 1876 ** The script processor doesn't negate the 1877 ** ACK signal after this transfer. 1878 */ 1879 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 1880 NADDR (msgin[0]), 1881 /* 1882 ** Check for message parity error. 1883 */ 1884 SCR_TO_REG (scratcha), 1885 0, 1886 SCR_FROM_REG (socl), 1887 0, 1888 SCR_JUMP ^ IFTRUE (MASK (CATN, CATN)), 1889 PADDRH (msg_parity), 1890 SCR_FROM_REG (scratcha), 1891 0, 1892 /* 1893 ** Parity was ok, handle this message. 1894 */ 1895 SCR_JUMP ^ IFTRUE (DATA (MSG_CMDCOMPLETE)), 1896 PADDR (complete), 1897 SCR_JUMP ^ IFTRUE (DATA (MSG_SAVEDATAPOINTER)), 1898 PADDR (save_dp), 1899 SCR_JUMP ^ IFTRUE (DATA (MSG_RESTOREPOINTERS)), 1900 PADDR (restore_dp), 1901 SCR_JUMP ^ IFTRUE (DATA (MSG_DISCONNECT)), 1902 PADDR (disconnect), 1903 SCR_JUMP ^ IFTRUE (DATA (MSG_EXTENDED)), 1904 PADDRH (msg_extended), 1905 SCR_JUMP ^ IFTRUE (DATA (MSG_NOOP)), 1906 PADDR (clrack), 1907 SCR_JUMP ^ IFTRUE (DATA (MSG_MESSAGE_REJECT)), 1908 PADDRH (msg_reject), 1909 SCR_JUMP ^ IFTRUE (DATA (MSG_IGN_WIDE_RESIDUE)), 1910 PADDRH (msg_ign_residue), 1911 /* 1912 ** Rest of the messages left as 1913 ** an exercise ... 1914 ** 1915 ** Unimplemented messages: 1916 ** fall through to MSG_BAD. 1917 */ 1918}/*-------------------------< MSG_BAD >------------------*/,{ 1919 /* 1920 ** unimplemented message - reject it. 1921 */ 1922 SCR_INT, 1923 SIR_REJECT_SENT, 1924 SCR_LOAD_REG (scratcha, MSG_MESSAGE_REJECT), 1925 0, 1926 SCR_JUMP, 1927 PADDR (setmsg), 1928 1929}/*-------------------------< COMPLETE >-----------------*/,{ 1930 /* 1931 ** Complete message. 1932 ** 1933 ** If it's not the get condition code, 1934 ** copy TEMP register to LASTP in header. 1935 */ 1936 SCR_FROM_REG (SS_REG), 1937 0, 1938/*<<<*/ SCR_JUMPR ^ IFTRUE (MASK (SCSI_STATUS_SENSE, SCSI_STATUS_SENSE)), 1939 12, 1940 SCR_COPY (4), 1941 RADDR (temp), 1942 NADDR (header.lastp), 1943/*>>>*/ /* 1944 ** When we terminate the cycle by clearing ACK, 1945 ** the target may disconnect immediately. 1946 ** 1947 ** We don't want to be told of an 1948 ** "unexpected disconnect", 1949 ** so we disable this feature. 1950 */ 1951 SCR_REG_REG (scntl2, SCR_AND, 0x7f), 1952 0, 1953 /* 1954 ** Terminate cycle ... 1955 */ 1956 SCR_CLR (SCR_ACK|SCR_ATN), 1957 0, 1958 /* 1959 ** ... and wait for the disconnect. 1960 */ 1961 SCR_WAIT_DISC, 1962 0, 1963}/*-------------------------< CLEANUP >-------------------*/,{ 1964 /* 1965 ** dsa: Pointer to nccb 1966 ** or xxxxxxFF (no nccb) 1967 ** 1968 ** HS_REG: Host-Status (<>0!) 1969 */ 1970 SCR_FROM_REG (dsa), 1971 0, 1972 SCR_JUMP ^ IFTRUE (DATA (0xff)), 1973 PADDR (signal), 1974 /* 1975 ** dsa is valid. 1976 ** save the status registers 1977 */ 1978 SCR_COPY (4), 1979 RADDR (scr0), 1980 NADDR (header.status), 1981 /* 1982 ** and copy back the header to the nccb. 1983 */ 1984 SCR_COPY_F (4), 1985 RADDR (dsa), 1986 PADDR (cleanup0), 1987 SCR_COPY (sizeof (struct head)), 1988 NADDR (header), 1989}/*-------------------------< CLEANUP0 >--------------------*/,{ 1990 0, 1991 1992 /* 1993 ** If command resulted in "check condition" 1994 ** status and is not yet completed, 1995 ** try to get the condition code. 1996 */ 1997 SCR_FROM_REG (HS_REG), 1998 0, 1999/*<<<*/ SCR_JUMPR ^ IFFALSE (MASK (0, HS_DONEMASK)), 2000 16, 2001 SCR_FROM_REG (SS_REG), 2002 0, 2003 SCR_JUMP ^ IFTRUE (DATA (SCSI_STATUS_CHECK_COND)), 2004 PADDRH(getcc2), 2005}/*-------------------------< SIGNAL >----------------------*/,{ 2006 /* 2007 ** if status = queue full, 2008 ** reinsert in startqueue and stall queue. 2009 */ 2010/*>>>*/ SCR_FROM_REG (SS_REG), 2011 0, 2012 SCR_INT ^ IFTRUE (DATA (SCSI_STATUS_QUEUE_FULL)), 2013 SIR_STALL_QUEUE, 2014 /* 2015 ** And make the DSA register invalid. 2016 */ 2017 SCR_LOAD_REG (dsa, 0xff), /* invalid */ 2018 0, 2019 /* 2020 ** if job completed ... 2021 */ 2022 SCR_FROM_REG (HS_REG), 2023 0, 2024 /* 2025 ** ... signal completion to the host 2026 */ 2027 SCR_INT_FLY ^ IFFALSE (MASK (0, HS_DONEMASK)), 2028 0, 2029 /* 2030 ** Auf zu neuen Schandtaten! 2031 */ 2032 SCR_JUMP, 2033 PADDR(start), 2034 2035}/*-------------------------< SAVE_DP >------------------*/,{ 2036 /* 2037 ** SAVE_DP message: 2038 ** Copy TEMP register to SAVEP in header. 2039 */ 2040 SCR_COPY (4), 2041 RADDR (temp), 2042 NADDR (header.savep), 2043 SCR_JUMP, 2044 PADDR (clrack), 2045}/*-------------------------< RESTORE_DP >---------------*/,{ 2046 /* 2047 ** RESTORE_DP message: 2048 ** Copy SAVEP in header to TEMP register. 2049 */ 2050 SCR_COPY (4), 2051 NADDR (header.savep), 2052 RADDR (temp), 2053 SCR_JUMP, 2054 PADDR (clrack), 2055 2056}/*-------------------------< DISCONNECT >---------------*/,{ 2057 /* 2058 ** If QUIRK_AUTOSAVE is set, 2059 ** do a "save pointer" operation. 2060 */ 2061 SCR_FROM_REG (QU_REG), 2062 0, 2063/*<<<*/ SCR_JUMPR ^ IFFALSE (MASK (QUIRK_AUTOSAVE, QUIRK_AUTOSAVE)), 2064 12, 2065 /* 2066 ** like SAVE_DP message: 2067 ** Copy TEMP register to SAVEP in header. 2068 */ 2069 SCR_COPY (4), 2070 RADDR (temp), 2071 NADDR (header.savep), 2072/*>>>*/ /* 2073 ** Check if temp==savep or temp==goalp: 2074 ** if not, log a missing save pointer message. 2075 ** In fact, it's a comparison mod 256. 2076 ** 2077 ** Hmmm, I hadn't thought that I would be urged to 2078 ** write this kind of ugly self modifying code. 2079 ** 2080 ** It's unbelievable, but the ncr53c8xx isn't able 2081 ** to subtract one register from another. 2082 */ 2083 SCR_FROM_REG (temp), 2084 0, 2085 /* 2086 ** You are not expected to understand this .. 2087 ** 2088 ** CAUTION: only little endian architectures supported! XXX 2089 */ 2090 SCR_COPY_F (1), 2091 NADDR (header.savep), 2092 PADDR (disconnect0), 2093}/*-------------------------< DISCONNECT0 >--------------*/,{ 2094/*<<<*/ SCR_JUMPR ^ IFTRUE (DATA (1)), 2095 20, 2096 /* 2097 ** neither this 2098 */ 2099 SCR_COPY_F (1), 2100 NADDR (header.goalp), 2101 PADDR (disconnect1), 2102}/*-------------------------< DISCONNECT1 >--------------*/,{ 2103 SCR_INT ^ IFFALSE (DATA (1)), 2104 SIR_MISSING_SAVE, 2105/*>>>*/ 2106 2107 /* 2108 ** DISCONNECTing ... 2109 ** 2110 ** disable the "unexpected disconnect" feature, 2111 ** and remove the ACK signal. 2112 */ 2113 SCR_REG_REG (scntl2, SCR_AND, 0x7f), 2114 0, 2115 SCR_CLR (SCR_ACK|SCR_ATN), 2116 0, 2117 /* 2118 ** Wait for the disconnect. 2119 */ 2120 SCR_WAIT_DISC, 2121 0, 2122 /* 2123 ** Profiling: 2124 ** Set a time stamp, 2125 ** and count the disconnects. 2126 */ 2127 SCR_COPY (sizeof (ticks)), 2128 KVAR (KVAR_TICKS), 2129 NADDR (header.stamp.disconnect), 2130 SCR_COPY (4), 2131 NADDR (disc_phys), 2132 RADDR (temp), 2133 SCR_REG_REG (temp, SCR_ADD, 0x01), 2134 0, 2135 SCR_COPY (4), 2136 RADDR (temp), 2137 NADDR (disc_phys), 2138 /* 2139 ** Status is: DISCONNECTED. 2140 */ 2141 SCR_LOAD_REG (HS_REG, HS_DISCONNECT), 2142 0, 2143 SCR_JUMP, 2144 PADDR (cleanup), 2145 2146}/*-------------------------< MSG_OUT >-------------------*/,{ 2147 /* 2148 ** The target requests a message. 2149 */ 2150 SCR_MOVE_ABS (1) ^ SCR_MSG_OUT, 2151 NADDR (msgout), 2152 SCR_COPY (1), 2153 RADDR (sfbr), 2154 NADDR (lastmsg), 2155 /* 2156 ** If it was no ABORT message ... 2157 */ 2158 SCR_JUMP ^ IFTRUE (DATA (MSG_ABORT)), 2159 PADDRH (msg_out_abort), 2160 /* 2161 ** ... wait for the next phase 2162 ** if it's a message out, send it again, ... 2163 */ 2164 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_OUT)), 2165 PADDR (msg_out), 2166}/*-------------------------< MSG_OUT_DONE >--------------*/,{ 2167 /* 2168 ** ... else clear the message ... 2169 */ 2170 SCR_LOAD_REG (scratcha, MSG_NOOP), 2171 0, 2172 SCR_COPY (4), 2173 RADDR (scratcha), 2174 NADDR (msgout), 2175 /* 2176 ** ... and process the next phase 2177 */ 2178 SCR_JUMP, 2179 PADDR (dispatch), 2180 2181}/*------------------------< BADGETCC >---------------------*/,{ 2182 /* 2183 ** If SIGP was set, clear it and try again. 2184 */ 2185 SCR_FROM_REG (ctest2), 2186 0, 2187 SCR_JUMP ^ IFTRUE (MASK (CSIGP,CSIGP)), 2188 PADDRH (getcc2), 2189 SCR_INT, 2190 SIR_SENSE_FAILED, 2191}/*-------------------------< RESELECT >--------------------*/,{ 2192 /* 2193 ** This NOP will be patched with LED OFF 2194 ** SCR_REG_REG (gpreg, SCR_OR, 0x01) 2195 */ 2196 SCR_NO_OP, 2197 0, 2198 2199 /* 2200 ** make the DSA invalid. 2201 */ 2202 SCR_LOAD_REG (dsa, 0xff), 2203 0, 2204 SCR_CLR (SCR_TRG), 2205 0, 2206 /* 2207 ** Sleep waiting for a reselection. 2208 ** If SIGP is set, special treatment. 2209 ** 2210 ** Zu allem bereit .. 2211 */ 2212 SCR_WAIT_RESEL, 2213 PADDR(reselect2), 2214}/*-------------------------< RESELECT1 >--------------------*/,{ 2215 /* 2216 ** This NOP will be patched with LED ON 2217 ** SCR_REG_REG (gpreg, SCR_AND, 0xfe) 2218 */ 2219 SCR_NO_OP, 2220 0, 2221 /* 2222 ** ... zu nichts zu gebrauchen ? 2223 ** 2224 ** load the target id into the SFBR 2225 ** and jump to the control block. 2226 ** 2227 ** Look at the declarations of 2228 ** - struct ncb 2229 ** - struct tcb 2230 ** - struct lcb 2231 ** - struct nccb 2232 ** to understand what's going on. 2233 */ 2234 SCR_REG_SFBR (ssid, SCR_AND, 0x8F), 2235 0, 2236 SCR_TO_REG (sdid), 2237 0, 2238 SCR_JUMP, 2239 NADDR (jump_tcb), 2240}/*-------------------------< RESELECT2 >-------------------*/,{ 2241 /* 2242 ** This NOP will be patched with LED ON 2243 ** SCR_REG_REG (gpreg, SCR_AND, 0xfe) 2244 */ 2245 SCR_NO_OP, 2246 0, 2247 /* 2248 ** If it's not connected :( 2249 ** -> interrupted by SIGP bit. 2250 ** Jump to start. 2251 */ 2252 SCR_FROM_REG (ctest2), 2253 0, 2254 SCR_JUMP ^ IFTRUE (MASK (CSIGP,CSIGP)), 2255 PADDR (start), 2256 SCR_JUMP, 2257 PADDR (reselect), 2258 2259}/*-------------------------< RESEL_TMP >-------------------*/,{ 2260 /* 2261 ** The return address in TEMP 2262 ** is in fact the data structure address, 2263 ** so copy it to the DSA register. 2264 */ 2265 SCR_COPY (4), 2266 RADDR (temp), 2267 RADDR (dsa), 2268 SCR_JUMP, 2269 PADDR (prepare), 2270 2271}/*-------------------------< RESEL_LUN >-------------------*/,{ 2272 /* 2273 ** come back to this point 2274 ** to get an IDENTIFY message 2275 ** Wait for a msg_in phase. 2276 */ 2277/*<<<*/ SCR_JUMPR ^ IFFALSE (WHEN (SCR_MSG_IN)), 2278 48, 2279 /* 2280 ** message phase 2281 ** It's not a sony, it's a trick: 2282 ** read the data without acknowledging it. 2283 */ 2284 SCR_FROM_REG (sbdl), 2285 0, 2286/*<<<*/ SCR_JUMPR ^ IFFALSE (MASK (MSG_IDENTIFYFLAG, 0x98)), 2287 32, 2288 /* 2289 ** It WAS an Identify message. 2290 ** get it and ack it! 2291 */ 2292 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 2293 NADDR (msgin), 2294 SCR_CLR (SCR_ACK), 2295 0, 2296 /* 2297 ** Mask out the lun. 2298 */ 2299 SCR_REG_REG (sfbr, SCR_AND, 0x07), 2300 0, 2301 SCR_RETURN, 2302 0, 2303 /* 2304 ** No message phase or no IDENTIFY message: 2305 ** return 0. 2306 */ 2307/*>>>*/ SCR_LOAD_SFBR (0), 2308 0, 2309 SCR_RETURN, 2310 0, 2311 2312}/*-------------------------< RESEL_TAG >-------------------*/,{ 2313 /* 2314 ** come back to this point 2315 ** to get a SIMPLE_TAG message 2316 ** Wait for a MSG_IN phase. 2317 */ 2318/*<<<*/ SCR_JUMPR ^ IFFALSE (WHEN (SCR_MSG_IN)), 2319 64, 2320 /* 2321 ** message phase 2322 ** It's a trick - read the data 2323 ** without acknowledging it. 2324 */ 2325 SCR_FROM_REG (sbdl), 2326 0, 2327/*<<<*/ SCR_JUMPR ^ IFFALSE (DATA (MSG_SIMPLE_Q_TAG)), 2328 48, 2329 /* 2330 ** It WAS a SIMPLE_TAG message. 2331 ** get it and ack it! 2332 */ 2333 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 2334 NADDR (msgin), 2335 SCR_CLR (SCR_ACK), 2336 0, 2337 /* 2338 ** Wait for the second byte (the tag) 2339 */ 2340/*<<<*/ SCR_JUMPR ^ IFFALSE (WHEN (SCR_MSG_IN)), 2341 24, 2342 /* 2343 ** Get it and ack it! 2344 */ 2345 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 2346 NADDR (msgin), 2347 SCR_CLR (SCR_ACK|SCR_CARRY), 2348 0, 2349 SCR_RETURN, 2350 0, 2351 /* 2352 ** No message phase or no SIMPLE_TAG message 2353 ** or no second byte: return 0. 2354 */ 2355/*>>>*/ SCR_LOAD_SFBR (0), 2356 0, 2357 SCR_SET (SCR_CARRY), 2358 0, 2359 SCR_RETURN, 2360 0, 2361 2362}/*-------------------------< DATA_IN >--------------------*/,{ 2363/* 2364** Because the size depends on the 2365** #define MAX_SCATTER parameter, 2366** it is filled in at runtime. 2367** 2368** SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_IN)), 2369** PADDR (no_data), 2370** SCR_COPY (sizeof (ticks)), 2371** KVAR (KVAR_TICKS), 2372** NADDR (header.stamp.data), 2373** SCR_MOVE_TBL ^ SCR_DATA_IN, 2374** offsetof (struct dsb, data[ 0]), 2375** 2376** ##===========< i=1; i<MAX_SCATTER >========= 2377** || SCR_CALL ^ IFFALSE (WHEN (SCR_DATA_IN)), 2378** || PADDR (checkatn), 2379** || SCR_MOVE_TBL ^ SCR_DATA_IN, 2380** || offsetof (struct dsb, data[ i]), 2381** ##========================================== 2382** 2383** SCR_CALL, 2384** PADDR (checkatn), 2385** SCR_JUMP, 2386** PADDR (no_data), 2387*/ 23880 2389}/*-------------------------< DATA_OUT >-------------------*/,{ 2390/* 2391** Because the size depends on the 2392** #define MAX_SCATTER parameter, 2393** it is filled in at runtime. 2394** 2395** SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_OUT)), 2396** PADDR (no_data), 2397** SCR_COPY (sizeof (ticks)), 2398** KVAR (KVAR_TICKS), 2399** NADDR (header.stamp.data), 2400** SCR_MOVE_TBL ^ SCR_DATA_OUT, 2401** offsetof (struct dsb, data[ 0]), 2402** 2403** ##===========< i=1; i<MAX_SCATTER >========= 2404** || SCR_CALL ^ IFFALSE (WHEN (SCR_DATA_OUT)), 2405** || PADDR (dispatch), 2406** || SCR_MOVE_TBL ^ SCR_DATA_OUT, 2407** || offsetof (struct dsb, data[ i]), 2408** ##========================================== 2409** 2410** SCR_CALL, 2411** PADDR (dispatch), 2412** SCR_JUMP, 2413** PADDR (no_data), 2414** 2415**--------------------------------------------------------- 2416*/ 2417(u_long)0 2418 2419}/*--------------------------------------------------------*/ 2420}; 2421 2422 2423static struct scripth scripth0 = { 2424/*-------------------------< TRYLOOP >---------------------*/{ 2425/* 2426** Load an entry of the start queue into dsa 2427** and try to start it by jumping to TRYSEL. 2428** 2429** Because the size depends on the 2430** #define MAX_START parameter, it is filled 2431** in at runtime. 2432** 2433**----------------------------------------------------------- 2434** 2435** ##===========< I=0; i<MAX_START >=========== 2436** || SCR_COPY (4), 2437** || NADDR (squeue[i]), 2438** || RADDR (dsa), 2439** || SCR_CALL, 2440** || PADDR (trysel), 2441** ##========================================== 2442** 2443** SCR_JUMP, 2444** PADDRH(tryloop), 2445** 2446**----------------------------------------------------------- 2447*/ 24480 2449}/*-------------------------< MSG_PARITY >---------------*/,{ 2450 /* 2451 ** count it 2452 */ 2453 SCR_REG_REG (PS_REG, SCR_ADD, 0x01), 2454 0, 2455 /* 2456 ** send a "message parity error" message. 2457 */ 2458 SCR_LOAD_REG (scratcha, MSG_PARITY_ERROR), 2459 0, 2460 SCR_JUMP, 2461 PADDR (setmsg), 2462}/*-------------------------< MSG_MESSAGE_REJECT >---------------*/,{ 2463 /* 2464 ** If a negotiation was in progress, 2465 ** negotiation failed. 2466 */ 2467 SCR_FROM_REG (HS_REG), 2468 0, 2469 SCR_INT ^ IFTRUE (DATA (HS_NEGOTIATE)), 2470 SIR_NEGO_FAILED, 2471 /* 2472 ** else make host log this message 2473 */ 2474 SCR_INT ^ IFFALSE (DATA (HS_NEGOTIATE)), 2475 SIR_REJECT_RECEIVED, 2476 SCR_JUMP, 2477 PADDR (clrack), 2478 2479}/*-------------------------< MSG_IGN_RESIDUE >----------*/,{ 2480 /* 2481 ** Terminate cycle 2482 */ 2483 SCR_CLR (SCR_ACK), 2484 0, 2485 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)), 2486 PADDR (dispatch), 2487 /* 2488 ** get residue size. 2489 */ 2490 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 2491 NADDR (msgin[1]), 2492 /* 2493 ** Check for message parity error. 2494 */ 2495 SCR_TO_REG (scratcha), 2496 0, 2497 SCR_FROM_REG (socl), 2498 0, 2499 SCR_JUMP ^ IFTRUE (MASK (CATN, CATN)), 2500 PADDRH (msg_parity), 2501 SCR_FROM_REG (scratcha), 2502 0, 2503 /* 2504 ** Size is 0 .. ignore message. 2505 */ 2506 SCR_JUMP ^ IFTRUE (DATA (0)), 2507 PADDR (clrack), 2508 /* 2509 ** Size is not 1 .. have to interrupt. 2510 */ 2511/*<<<*/ SCR_JUMPR ^ IFFALSE (DATA (1)), 2512 40, 2513 /* 2514 ** Check for residue byte in swide register 2515 */ 2516 SCR_FROM_REG (scntl2), 2517 0, 2518/*<<<*/ SCR_JUMPR ^ IFFALSE (MASK (WSR, WSR)), 2519 16, 2520 /* 2521 ** There IS data in the swide register. 2522 ** Discard it. 2523 */ 2524 SCR_REG_REG (scntl2, SCR_OR, WSR), 2525 0, 2526 SCR_JUMP, 2527 PADDR (clrack), 2528 /* 2529 ** Load again the size to the sfbr register. 2530 */ 2531/*>>>*/ SCR_FROM_REG (scratcha), 2532 0, 2533/*>>>*/ SCR_INT, 2534 SIR_IGN_RESIDUE, 2535 SCR_JUMP, 2536 PADDR (clrack), 2537 2538}/*-------------------------< MSG_EXTENDED >-------------*/,{ 2539 /* 2540 ** Terminate cycle 2541 */ 2542 SCR_CLR (SCR_ACK), 2543 0, 2544 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)), 2545 PADDR (dispatch), 2546 /* 2547 ** get length. 2548 */ 2549 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 2550 NADDR (msgin[1]), 2551 /* 2552 ** Check for message parity error. 2553 */ 2554 SCR_TO_REG (scratcha), 2555 0, 2556 SCR_FROM_REG (socl), 2557 0, 2558 SCR_JUMP ^ IFTRUE (MASK (CATN, CATN)), 2559 PADDRH (msg_parity), 2560 SCR_FROM_REG (scratcha), 2561 0, 2562 /* 2563 */ 2564 SCR_JUMP ^ IFTRUE (DATA (3)), 2565 PADDRH (msg_ext_3), 2566 SCR_JUMP ^ IFFALSE (DATA (2)), 2567 PADDR (msg_bad), 2568}/*-------------------------< MSG_EXT_2 >----------------*/,{ 2569 SCR_CLR (SCR_ACK), 2570 0, 2571 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)), 2572 PADDR (dispatch), 2573 /* 2574 ** get extended message code. 2575 */ 2576 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 2577 NADDR (msgin[2]), 2578 /* 2579 ** Check for message parity error. 2580 */ 2581 SCR_TO_REG (scratcha), 2582 0, 2583 SCR_FROM_REG (socl), 2584 0, 2585 SCR_JUMP ^ IFTRUE (MASK (CATN, CATN)), 2586 PADDRH (msg_parity), 2587 SCR_FROM_REG (scratcha), 2588 0, 2589 SCR_JUMP ^ IFTRUE (DATA (MSG_EXT_WDTR)), 2590 PADDRH (msg_wdtr), 2591 /* 2592 ** unknown extended message 2593 */ 2594 SCR_JUMP, 2595 PADDR (msg_bad) 2596}/*-------------------------< MSG_WDTR >-----------------*/,{ 2597 SCR_CLR (SCR_ACK), 2598 0, 2599 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)), 2600 PADDR (dispatch), 2601 /* 2602 ** get data bus width 2603 */ 2604 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 2605 NADDR (msgin[3]), 2606 SCR_FROM_REG (socl), 2607 0, 2608 SCR_JUMP ^ IFTRUE (MASK (CATN, CATN)), 2609 PADDRH (msg_parity), 2610 /* 2611 ** let the host do the real work. 2612 */ 2613 SCR_INT, 2614 SIR_NEGO_WIDE, 2615 /* 2616 ** let the target fetch our answer. 2617 */ 2618 SCR_SET (SCR_ATN), 2619 0, 2620 SCR_CLR (SCR_ACK), 2621 0, 2622 2623 SCR_INT ^ IFFALSE (WHEN (SCR_MSG_OUT)), 2624 SIR_NEGO_PROTO, 2625 /* 2626 ** Send the MSG_EXT_WDTR 2627 */ 2628 SCR_MOVE_ABS (4) ^ SCR_MSG_OUT, 2629 NADDR (msgout), 2630 SCR_CLR (SCR_ATN), 2631 0, 2632 SCR_COPY (1), 2633 RADDR (sfbr), 2634 NADDR (lastmsg), 2635 SCR_JUMP, 2636 PADDR (msg_out_done), 2637 2638}/*-------------------------< MSG_EXT_3 >----------------*/,{ 2639 SCR_CLR (SCR_ACK), 2640 0, 2641 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)), 2642 PADDR (dispatch), 2643 /* 2644 ** get extended message code. 2645 */ 2646 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 2647 NADDR (msgin[2]), 2648 /* 2649 ** Check for message parity error. 2650 */ 2651 SCR_TO_REG (scratcha), 2652 0, 2653 SCR_FROM_REG (socl), 2654 0, 2655 SCR_JUMP ^ IFTRUE (MASK (CATN, CATN)), 2656 PADDRH (msg_parity), 2657 SCR_FROM_REG (scratcha), 2658 0, 2659 SCR_JUMP ^ IFTRUE (DATA (MSG_EXT_SDTR)), 2660 PADDRH (msg_sdtr), 2661 /* 2662 ** unknown extended message 2663 */ 2664 SCR_JUMP, 2665 PADDR (msg_bad) 2666 2667}/*-------------------------< MSG_SDTR >-----------------*/,{ 2668 SCR_CLR (SCR_ACK), 2669 0, 2670 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)), 2671 PADDR (dispatch), 2672 /* 2673 ** get period and offset 2674 */ 2675 SCR_MOVE_ABS (2) ^ SCR_MSG_IN, 2676 NADDR (msgin[3]), 2677 SCR_FROM_REG (socl), 2678 0, 2679 SCR_JUMP ^ IFTRUE (MASK (CATN, CATN)), 2680 PADDRH (msg_parity), 2681 /* 2682 ** let the host do the real work. 2683 */ 2684 SCR_INT, 2685 SIR_NEGO_SYNC, 2686 /* 2687 ** let the target fetch our answer. 2688 */ 2689 SCR_SET (SCR_ATN), 2690 0, 2691 SCR_CLR (SCR_ACK), 2692 0, 2693 2694 SCR_INT ^ IFFALSE (WHEN (SCR_MSG_OUT)), 2695 SIR_NEGO_PROTO, 2696 /* 2697 ** Send the MSG_EXT_SDTR 2698 */ 2699 SCR_MOVE_ABS (5) ^ SCR_MSG_OUT, 2700 NADDR (msgout), 2701 SCR_CLR (SCR_ATN), 2702 0, 2703 SCR_COPY (1), 2704 RADDR (sfbr), 2705 NADDR (lastmsg), 2706 SCR_JUMP, 2707 PADDR (msg_out_done), 2708 2709}/*-------------------------< MSG_OUT_ABORT >-------------*/,{ 2710 /* 2711 ** After ABORT message, 2712 ** 2713 ** expect an immediate disconnect, ... 2714 */ 2715 SCR_REG_REG (scntl2, SCR_AND, 0x7f), 2716 0, 2717 SCR_CLR (SCR_ACK|SCR_ATN), 2718 0, 2719 SCR_WAIT_DISC, 2720 0, 2721 /* 2722 ** ... and set the status to "ABORTED" 2723 */ 2724 SCR_LOAD_REG (HS_REG, HS_ABORTED), 2725 0, 2726 SCR_JUMP, 2727 PADDR (cleanup), 2728 2729}/*-------------------------< GETCC >-----------------------*/,{ 2730 /* 2731 ** The ncr doesn't have an indirect load 2732 ** or store command. So we have to 2733 ** copy part of the control block to a 2734 ** fixed place, where we can modify it. 2735 ** 2736 ** We patch the address part of a COPY command 2737 ** with the address of the dsa register ... 2738 */ 2739 SCR_COPY_F (4), 2740 RADDR (dsa), 2741 PADDRH (getcc1), 2742 /* 2743 ** ... then we do the actual copy. 2744 */ 2745 SCR_COPY (sizeof (struct head)), 2746}/*-------------------------< GETCC1 >----------------------*/,{ 2747 0, 2748 NADDR (header), 2749 /* 2750 ** Initialize the status registers 2751 */ 2752 SCR_COPY (4), 2753 NADDR (header.status), 2754 RADDR (scr0), 2755}/*-------------------------< GETCC2 >----------------------*/,{ 2756 /* 2757 ** Get the condition code from a target. 2758 ** 2759 ** DSA points to a data structure. 2760 ** Set TEMP to the script location 2761 ** that receives the condition code. 2762 ** 2763 ** Because there is no script command 2764 ** to load a longword into a register, 2765 ** we use a CALL command. 2766 */ 2767/*<<<*/ SCR_CALLR, 2768 24, 2769 /* 2770 ** Get the condition code. 2771 */ 2772 SCR_MOVE_TBL ^ SCR_DATA_IN, 2773 offsetof (struct dsb, sense), 2774 /* 2775 ** No data phase may follow! 2776 */ 2777 SCR_CALL, 2778 PADDR (checkatn), 2779 SCR_JUMP, 2780 PADDR (no_data), 2781/*>>>*/ 2782 2783 /* 2784 ** The CALL jumps to this point. 2785 ** Prepare for a RESTORE_POINTER message. 2786 ** Save the TEMP register into the saved pointer. 2787 */ 2788 SCR_COPY (4), 2789 RADDR (temp), 2790 NADDR (header.savep), 2791 /* 2792 ** Load scratcha, because in case of a selection timeout, 2793 ** the host will expect a new value for startpos in 2794 ** the scratcha register. 2795 */ 2796 SCR_COPY (4), 2797 PADDR (startpos), 2798 RADDR (scratcha), 2799#ifdef NCR_GETCC_WITHMSG 2800 /* 2801 ** If QUIRK_NOMSG is set, select without ATN. 2802 ** and don't send a message. 2803 */ 2804 SCR_FROM_REG (QU_REG), 2805 0, 2806 SCR_JUMP ^ IFTRUE (MASK (QUIRK_NOMSG, QUIRK_NOMSG)), 2807 PADDRH(getcc3), 2808 /* 2809 ** Then try to connect to the target. 2810 ** If we are reselected, special treatment 2811 ** of the current job is required before 2812 ** accepting the reselection. 2813 */ 2814 SCR_SEL_TBL_ATN ^ offsetof (struct dsb, select), 2815 PADDR(badgetcc), 2816 /* 2817 ** Send the IDENTIFY message. 2818 ** In case of short transfer, remove ATN. 2819 */ 2820 SCR_MOVE_TBL ^ SCR_MSG_OUT, 2821 offsetof (struct dsb, smsg2), 2822 SCR_CLR (SCR_ATN), 2823 0, 2824 /* 2825 ** save the first byte of the message. 2826 */ 2827 SCR_COPY (1), 2828 RADDR (sfbr), 2829 NADDR (lastmsg), 2830 SCR_JUMP, 2831 PADDR (prepare2), 2832 2833#endif 2834}/*-------------------------< GETCC3 >----------------------*/,{ 2835 /* 2836 ** Try to connect to the target. 2837 ** If we are reselected, special treatment 2838 ** of the current job is required before 2839 ** accepting the reselection. 2840 ** 2841 ** Silly target won't accept a message. 2842 ** Select without ATN. 2843 */ 2844 SCR_SEL_TBL ^ offsetof (struct dsb, select), 2845 PADDR(badgetcc), 2846 /* 2847 ** Force error if selection timeout 2848 */ 2849 SCR_JUMPR ^ IFTRUE (WHEN (SCR_MSG_IN)), 2850 0, 2851 /* 2852 ** don't negotiate. 2853 */ 2854 SCR_JUMP, 2855 PADDR (prepare2), 2856}/*-------------------------< ABORTTAG >-------------------*/,{ 2857 /* 2858 ** Abort a bad reselection. 2859 ** Set the message to ABORT vs. ABORT_TAG 2860 */ 2861 SCR_LOAD_REG (scratcha, MSG_ABORT_TAG), 2862 0, 2863 SCR_JUMPR ^ IFFALSE (CARRYSET), 2864 8, 2865}/*-------------------------< ABORT >----------------------*/,{ 2866 SCR_LOAD_REG (scratcha, MSG_ABORT), 2867 0, 2868 SCR_COPY (1), 2869 RADDR (scratcha), 2870 NADDR (msgout), 2871 SCR_SET (SCR_ATN), 2872 0, 2873 SCR_CLR (SCR_ACK), 2874 0, 2875 /* 2876 ** and send it. 2877 ** we expect an immediate disconnect 2878 */ 2879 SCR_REG_REG (scntl2, SCR_AND, 0x7f), 2880 0, 2881 SCR_MOVE_ABS (1) ^ SCR_MSG_OUT, 2882 NADDR (msgout), 2883 SCR_COPY (1), 2884 RADDR (sfbr), 2885 NADDR (lastmsg), 2886 SCR_CLR (SCR_ACK|SCR_ATN), 2887 0, 2888 SCR_WAIT_DISC, 2889 0, 2890 SCR_JUMP, 2891 PADDR (start), 2892}/*-------------------------< SNOOPTEST >-------------------*/,{ 2893 /* 2894 ** Read the variable. 2895 */ 2896 SCR_COPY (4), 2897 KVAR (KVAR_NCR_CACHE), 2898 RADDR (scratcha), 2899 /* 2900 ** Write the variable. 2901 */ 2902 SCR_COPY (4), 2903 RADDR (temp), 2904 KVAR (KVAR_NCR_CACHE), 2905 /* 2906 ** Read back the variable. 2907 */ 2908 SCR_COPY (4), 2909 KVAR (KVAR_NCR_CACHE), 2910 RADDR (temp), 2911}/*-------------------------< SNOOPEND >-------------------*/,{ 2912 /* 2913 ** And stop. 2914 */ 2915 SCR_INT, 2916 99, 2917}/*--------------------------------------------------------*/ 2918}; 2919 2920 2921/*========================================================== 2922** 2923** 2924** Fill in #define dependent parts of the script 2925** 2926** 2927**========================================================== 2928*/ 2929 2930static void ncr_script_fill (struct script * scr, struct scripth * scrh) 2931{ 2932 int i; 2933 ncrcmd *p; 2934 2935 p = scrh->tryloop; 2936 for (i=0; i<MAX_START; i++) { 2937 *p++ =SCR_COPY (4); 2938 *p++ =NADDR (squeue[i]); 2939 *p++ =RADDR (dsa); 2940 *p++ =SCR_CALL; 2941 *p++ =PADDR (trysel); 2942 }; 2943 *p++ =SCR_JUMP; 2944 *p++ =PADDRH(tryloop); 2945 2946 assert ((char *)p == (char *)&scrh->tryloop + sizeof (scrh->tryloop)); 2947 2948 p = scr->data_in; 2949 2950 *p++ =SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_IN)); 2951 *p++ =PADDR (no_data); 2952 *p++ =SCR_COPY (sizeof (ticks)); 2953 *p++ =(ncrcmd) KVAR (KVAR_TICKS); 2954 *p++ =NADDR (header.stamp.data); 2955 *p++ =SCR_MOVE_TBL ^ SCR_DATA_IN; 2956 *p++ =offsetof (struct dsb, data[ 0]); 2957 2958 for (i=1; i<MAX_SCATTER; i++) { 2959 *p++ =SCR_CALL ^ IFFALSE (WHEN (SCR_DATA_IN)); 2960 *p++ =PADDR (checkatn); 2961 *p++ =SCR_MOVE_TBL ^ SCR_DATA_IN; 2962 *p++ =offsetof (struct dsb, data[i]); 2963 }; 2964 2965 *p++ =SCR_CALL; 2966 *p++ =PADDR (checkatn); 2967 *p++ =SCR_JUMP; 2968 *p++ =PADDR (no_data); 2969 2970 assert ((char *)p == (char *)&scr->data_in + sizeof (scr->data_in)); 2971 2972 p = scr->data_out; 2973 2974 *p++ =SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_OUT)); 2975 *p++ =PADDR (no_data); 2976 *p++ =SCR_COPY (sizeof (ticks)); 2977 *p++ =(ncrcmd) KVAR (KVAR_TICKS); 2978 *p++ =NADDR (header.stamp.data); 2979 *p++ =SCR_MOVE_TBL ^ SCR_DATA_OUT; 2980 *p++ =offsetof (struct dsb, data[ 0]); 2981 2982 for (i=1; i<MAX_SCATTER; i++) { 2983 *p++ =SCR_CALL ^ IFFALSE (WHEN (SCR_DATA_OUT)); 2984 *p++ =PADDR (dispatch); 2985 *p++ =SCR_MOVE_TBL ^ SCR_DATA_OUT; 2986 *p++ =offsetof (struct dsb, data[i]); 2987 }; 2988 2989 *p++ =SCR_CALL; 2990 *p++ =PADDR (dispatch); 2991 *p++ =SCR_JUMP; 2992 *p++ =PADDR (no_data); 2993 2994 assert ((char *)p == (char *)&scr->data_out + sizeof (scr->data_out)); 2995} 2996 2997/*========================================================== 2998** 2999** 3000** Copy and rebind a script. 3001** 3002** 3003**========================================================== 3004*/ 3005 3006static void ncr_script_copy_and_bind (ncb_p np, ncrcmd *src, ncrcmd *dst, int len) 3007{ 3008 ncrcmd opcode, new, old, tmp1, tmp2; 3009 ncrcmd *start, *end; 3010 int relocs, offset; 3011 3012 start = src; 3013 end = src + len/4; 3014 offset = 0; 3015 3016 while (src < end) { 3017 3018 opcode = *src++; 3019 WRITESCRIPT_OFF(dst, offset, opcode); 3020 offset += 4; 3021 3022 /* 3023 ** If we forget to change the length 3024 ** in struct script, a field will be 3025 ** padded with 0. This is an illegal 3026 ** command. 3027 */ 3028 3029 if (opcode == 0) { 3030 printf ("%s: ERROR0 IN SCRIPT at %d.\n", 3031 ncr_name(np), (int) (src-start-1)); 3032 DELAY (1000000); 3033 }; 3034 3035 if (DEBUG_FLAGS & DEBUG_SCRIPT) 3036 printf ("%p: <%x>\n", 3037 (src-1), (unsigned)opcode); 3038 3039 /* 3040 ** We don't have to decode ALL commands 3041 */ 3042 switch (opcode >> 28) { 3043 3044 case 0xc: 3045 /* 3046 ** COPY has TWO arguments. 3047 */ 3048 relocs = 2; 3049 tmp1 = src[0]; 3050 if ((tmp1 & RELOC_MASK) == RELOC_KVAR) 3051 tmp1 = 0; 3052 tmp2 = src[1]; 3053 if ((tmp2 & RELOC_MASK) == RELOC_KVAR) 3054 tmp2 = 0; 3055 if ((tmp1 ^ tmp2) & 3) { 3056 printf ("%s: ERROR1 IN SCRIPT at %d.\n", 3057 ncr_name(np), (int) (src-start-1)); 3058 DELAY (1000000); 3059 } 3060 /* 3061 ** If PREFETCH feature not enabled, remove 3062 ** the NO FLUSH bit if present. 3063 */ 3064 if ((opcode & SCR_NO_FLUSH) && !(np->features&FE_PFEN)) 3065 WRITESCRIPT_OFF(dst, offset - 4, 3066 (opcode & ~SCR_NO_FLUSH)); 3067 break; 3068 3069 case 0x0: 3070 /* 3071 ** MOVE (absolute address) 3072 */ 3073 relocs = 1; 3074 break; 3075 3076 case 0x8: 3077 /* 3078 ** JUMP / CALL 3079 ** dont't relocate if relative :-) 3080 */ 3081 if (opcode & 0x00800000) 3082 relocs = 0; 3083 else 3084 relocs = 1; 3085 break; 3086 3087 case 0x4: 3088 case 0x5: 3089 case 0x6: 3090 case 0x7: 3091 relocs = 1; 3092 break; 3093 3094 default: 3095 relocs = 0; 3096 break; 3097 }; 3098 3099 if (relocs) { 3100 while (relocs--) { 3101 old = *src++; 3102 3103 switch (old & RELOC_MASK) { 3104 case RELOC_REGISTER: 3105 new = (old & ~RELOC_MASK) + rman_get_start(np->reg_res); 3106 break; 3107 case RELOC_LABEL: 3108 new = (old & ~RELOC_MASK) + np->p_script; 3109 break; 3110 case RELOC_LABELH: 3111 new = (old & ~RELOC_MASK) + np->p_scripth; 3112 break; 3113 case RELOC_SOFTC: 3114 new = (old & ~RELOC_MASK) + vtophys(np); 3115 break; 3116 case RELOC_KVAR: 3117 if (((old & ~RELOC_MASK) < 3118 SCRIPT_KVAR_FIRST) || 3119 ((old & ~RELOC_MASK) > 3120 SCRIPT_KVAR_LAST)) 3121 panic("ncr KVAR out of range"); 3122 new = vtophys(script_kvars[old & 3123 ~RELOC_MASK]); 3124 break; 3125 case 0: 3126 /* Don't relocate a 0 address. */ 3127 if (old == 0) { 3128 new = old; 3129 break; 3130 } 3131 /* FALLTHROUGH */ 3132 default: 3133 panic("ncr_script_copy_and_bind: weird relocation %x @ %d\n", old, (int)(src - start)); 3134 break; 3135 } 3136 3137 WRITESCRIPT_OFF(dst, offset, new); 3138 offset += 4; 3139 } 3140 } else { 3141 WRITESCRIPT_OFF(dst, offset, *src++); 3142 offset += 4; 3143 } 3144 3145 }; 3146} 3147 3148/*========================================================== 3149** 3150** 3151** Auto configuration. 3152** 3153** 3154**========================================================== 3155*/ 3156 3157#if 0 3158/*---------------------------------------------------------- 3159** 3160** Reduce the transfer length to the max value 3161** we can transfer safely. 3162** 3163** Reading a block greater then MAX_SIZE from the 3164** raw (character) device exercises a memory leak 3165** in the vm subsystem. This is common to ALL devices. 3166** We have submitted a description of this bug to 3167** <FreeBSD-bugs@freefall.cdrom.com>. 3168** It should be fixed in the current release. 3169** 3170**---------------------------------------------------------- 3171*/ 3172 3173void ncr_min_phys (struct buf *bp) 3174{ 3175 if ((unsigned long)bp->b_bcount > MAX_SIZE) bp->b_bcount = MAX_SIZE; 3176} 3177 3178#endif 3179 3180#if 0 3181/*---------------------------------------------------------- 3182** 3183** Maximal number of outstanding requests per target. 3184** 3185**---------------------------------------------------------- 3186*/ 3187 3188u_int32_t ncr_info (int unit) 3189{ 3190 return (1); /* may be changed later */ 3191} 3192 3193#endif 3194 3195/*---------------------------------------------------------- 3196** 3197** NCR chip devices table and chip look up function. 3198** Features bit are defined in ncrreg.h. Is it the 3199** right place? 3200** 3201**---------------------------------------------------------- 3202*/ 3203typedef struct { 3204 unsigned long device_id; 3205 unsigned short minrevid; 3206 char *name; 3207 unsigned char maxburst; 3208 unsigned char maxoffs; 3209 unsigned char clock_divn; 3210 unsigned int features; 3211} ncr_chip; 3212 3213static ncr_chip ncr_chip_table[] = { 3214 {NCR_810_ID, 0x00, "ncr 53c810 fast10 scsi", 4, 8, 4, 3215 FE_ERL} 3216 , 3217 {NCR_810_ID, 0x10, "ncr 53c810a fast10 scsi", 4, 8, 4, 3218 FE_ERL|FE_LDSTR|FE_PFEN|FE_BOF} 3219 , 3220 {NCR_815_ID, 0x00, "ncr 53c815 fast10 scsi", 4, 8, 4, 3221 FE_ERL|FE_BOF} 3222 , 3223 {NCR_820_ID, 0x00, "ncr 53c820 fast10 wide scsi", 4, 8, 4, 3224 FE_WIDE|FE_ERL} 3225 , 3226 {NCR_825_ID, 0x00, "ncr 53c825 fast10 wide scsi", 4, 8, 4, 3227 FE_WIDE|FE_ERL|FE_BOF} 3228 , 3229 {NCR_825_ID, 0x10, "ncr 53c825a fast10 wide scsi", 7, 8, 4, 3230 FE_WIDE|FE_CACHE_SET|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM} 3231 , 3232 {NCR_860_ID, 0x00, "ncr 53c860 fast20 scsi", 4, 8, 5, 3233 FE_ULTRA|FE_CLK80|FE_CACHE_SET|FE_LDSTR|FE_PFEN} 3234 , 3235 {NCR_875_ID, 0x00, "ncr 53c875 fast20 wide scsi", 7, 16, 5, 3236 FE_WIDE|FE_ULTRA|FE_CLK80|FE_CACHE_SET|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM} 3237 , 3238 {NCR_875_ID, 0x02, "ncr 53c875 fast20 wide scsi", 7, 16, 5, 3239 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE_SET|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM} 3240 , 3241 {NCR_875_ID2, 0x00, "ncr 53c875j fast20 wide scsi", 7, 16, 5, 3242 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE_SET|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM} 3243 , 3244 {NCR_885_ID, 0x00, "ncr 53c885 fast20 wide scsi", 7, 16, 5, 3245 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE_SET|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM} 3246 , 3247 {NCR_895_ID, 0x00, "ncr 53c895 fast40 wide scsi", 7, 31, 7, 3248 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM} 3249 , 3250 {NCR_896_ID, 0x00, "ncr 53c896 fast40 wide scsi", 7, 31, 7, 3251 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM} 3252 , 3253 {NCR_895A_ID, 0x00, "ncr 53c895a fast40 wide scsi", 7, 31, 7, 3254 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM} 3255 , 3256 {NCR_1510D_ID, 0x00, "ncr 53c1510d fast40 wide scsi", 7, 31, 7, 3257 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM} 3258}; 3259 3260static int ncr_chip_lookup(u_long device_id, u_char revision_id) 3261{ 3262 int i, found; 3263 3264 found = -1; 3265 for (i = 0; i < sizeof(ncr_chip_table)/sizeof(ncr_chip_table[0]); i++) { 3266 if (device_id == ncr_chip_table[i].device_id && 3267 ncr_chip_table[i].minrevid <= revision_id) { 3268 if (found < 0 || 3269 ncr_chip_table[found].minrevid 3270 < ncr_chip_table[i].minrevid) { 3271 found = i; 3272 } 3273 } 3274 } 3275 return found; 3276} 3277 3278/*---------------------------------------------------------- 3279** 3280** Probe the hostadapter. 3281** 3282**---------------------------------------------------------- 3283*/ 3284 3285 3286 3287static int ncr_probe (device_t dev) 3288{ 3289 int i; 3290 3291 i = ncr_chip_lookup(pci_get_devid(dev), pci_get_revid(dev)); 3292 if (i >= 0) { 3293 device_set_desc(dev, ncr_chip_table[i].name); 3294 return (BUS_PROBE_DEFAULT); 3295 } 3296 3297 return (ENXIO); 3298} 3299 3300 3301 3302/*========================================================== 3303** 3304** NCR chip clock divisor table. 3305** Divisors are multiplied by 10,000,000 in order to make 3306** calculations more simple. 3307** 3308**========================================================== 3309*/ 3310 3311#define _5M 5000000 3312static u_long div_10M[] = 3313 {2*_5M, 3*_5M, 4*_5M, 6*_5M, 8*_5M, 12*_5M, 16*_5M}; 3314 3315/*=============================================================== 3316** 3317** NCR chips allow burst lengths of 2, 4, 8, 16, 32, 64, 128 3318** transfers. 32,64,128 are only supported by 875 and 895 chips. 3319** We use log base 2 (burst length) as internal code, with 3320** value 0 meaning "burst disabled". 3321** 3322**=============================================================== 3323*/ 3324 3325/* 3326 * Burst length from burst code. 3327 */ 3328#define burst_length(bc) (!(bc))? 0 : 1 << (bc) 3329 3330/* 3331 * Burst code from io register bits. 3332 */ 3333#define burst_code(dmode, ctest4, ctest5) \ 3334 (ctest4) & 0x80? 0 : (((dmode) & 0xc0) >> 6) + ((ctest5) & 0x04) + 1 3335 3336/* 3337 * Set initial io register bits from burst code. 3338 */ 3339static void 3340ncr_init_burst(ncb_p np, u_char bc) 3341{ 3342 np->rv_ctest4 &= ~0x80; 3343 np->rv_dmode &= ~(0x3 << 6); 3344 np->rv_ctest5 &= ~0x4; 3345 3346 if (!bc) { 3347 np->rv_ctest4 |= 0x80; 3348 } 3349 else { 3350 --bc; 3351 np->rv_dmode |= ((bc & 0x3) << 6); 3352 np->rv_ctest5 |= (bc & 0x4); 3353 } 3354} 3355 3356/*========================================================== 3357** 3358** 3359** Auto configuration: attach and init a host adapter. 3360** 3361** 3362**========================================================== 3363*/ 3364 3365 3366static int 3367ncr_attach (device_t dev) 3368{ 3369 ncb_p np = (struct ncb*) device_get_softc(dev); 3370 u_char rev = 0; 3371 u_long period; 3372 int i, rid; 3373 u_int8_t usrsync; 3374 u_int8_t usrwide; 3375 struct cam_devq *devq; 3376 3377 /* 3378 ** allocate and initialize structures. 3379 */ 3380 3381 np->unit = device_get_unit(dev); 3382 3383 /* 3384 ** Try to map the controller chip to 3385 ** virtual and physical memory. 3386 */ 3387 3388 np->reg_rid = 0x14; 3389 np->reg_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 3390 &np->reg_rid, RF_ACTIVE); 3391 if (!np->reg_res) { 3392 device_printf(dev, "could not map memory\n"); 3393 return ENXIO; 3394 } 3395 3396 /* 3397 ** Make the controller's registers available. 3398 ** Now the INB INW INL OUTB OUTW OUTL macros 3399 ** can be used safely. 3400 */ 3401 3402 np->bst = rman_get_bustag(np->reg_res); 3403 np->bsh = rman_get_bushandle(np->reg_res); 3404 3405 3406#ifdef NCR_IOMAPPED 3407 /* 3408 ** Try to map the controller chip into iospace. 3409 */ 3410 3411 if (!pci_map_port (config_id, 0x10, &np->port)) 3412 return; 3413#endif 3414 3415 3416 /* 3417 ** Save some controller register default values 3418 */ 3419 3420 np->rv_scntl3 = INB(nc_scntl3) & 0x77; 3421 np->rv_dmode = INB(nc_dmode) & 0xce; 3422 np->rv_dcntl = INB(nc_dcntl) & 0xa9; 3423 np->rv_ctest3 = INB(nc_ctest3) & 0x01; 3424 np->rv_ctest4 = INB(nc_ctest4) & 0x88; 3425 np->rv_ctest5 = INB(nc_ctest5) & 0x24; 3426 np->rv_gpcntl = INB(nc_gpcntl); 3427 np->rv_stest2 = INB(nc_stest2) & 0x20; 3428 3429 if (bootverbose >= 2) { 3430 printf ("\tBIOS values: SCNTL3:%02x DMODE:%02x DCNTL:%02x\n", 3431 np->rv_scntl3, np->rv_dmode, np->rv_dcntl); 3432 printf ("\t CTEST3:%02x CTEST4:%02x CTEST5:%02x\n", 3433 np->rv_ctest3, np->rv_ctest4, np->rv_ctest5); 3434 } 3435 3436 np->rv_dcntl |= NOCOM; 3437 3438 /* 3439 ** Do chip dependent initialization. 3440 */ 3441 3442 rev = pci_get_revid(dev); 3443 3444 /* 3445 ** Get chip features from chips table. 3446 */ 3447 i = ncr_chip_lookup(pci_get_devid(dev), rev); 3448 3449 if (i >= 0) { 3450 np->maxburst = ncr_chip_table[i].maxburst; 3451 np->maxoffs = ncr_chip_table[i].maxoffs; 3452 np->clock_divn = ncr_chip_table[i].clock_divn; 3453 np->features = ncr_chip_table[i].features; 3454 } else { /* Should'nt happen if probe() is ok */ 3455 np->maxburst = 4; 3456 np->maxoffs = 8; 3457 np->clock_divn = 4; 3458 np->features = FE_ERL; 3459 } 3460 3461 np->maxwide = np->features & FE_WIDE ? 1 : 0; 3462 np->clock_khz = np->features & FE_CLK80 ? 80000 : 40000; 3463 if (np->features & FE_QUAD) np->multiplier = 4; 3464 else if (np->features & FE_DBLR) np->multiplier = 2; 3465 else np->multiplier = 1; 3466 3467 /* 3468 ** Get the frequency of the chip's clock. 3469 ** Find the right value for scntl3. 3470 */ 3471 if (np->features & (FE_ULTRA|FE_ULTRA2)) 3472 ncr_getclock(np, np->multiplier); 3473 3474#ifdef NCR_TEKRAM_EEPROM 3475 if (bootverbose) { 3476 printf ("%s: Tekram EEPROM read %s\n", 3477 ncr_name(np), 3478 read_tekram_eeprom (np, NULL) ? 3479 "succeeded" : "failed"); 3480 } 3481#endif /* NCR_TEKRAM_EEPROM */ 3482 3483 /* 3484 * If scntl3 != 0, we assume BIOS is present. 3485 */ 3486 if (np->rv_scntl3) 3487 np->features |= FE_BIOS; 3488 3489 /* 3490 * Divisor to be used for async (timer pre-scaler). 3491 */ 3492 i = np->clock_divn - 1; 3493 while (i >= 0) { 3494 --i; 3495 if (10ul * SCSI_NCR_MIN_ASYNC * np->clock_khz > div_10M[i]) { 3496 ++i; 3497 break; 3498 } 3499 } 3500 np->rv_scntl3 = i+1; 3501 3502 /* 3503 * Minimum synchronous period factor supported by the chip. 3504 * Btw, 'period' is in tenths of nanoseconds. 3505 */ 3506 3507 period = (4 * div_10M[0] + np->clock_khz - 1) / np->clock_khz; 3508 if (period <= 250) np->minsync = 10; 3509 else if (period <= 303) np->minsync = 11; 3510 else if (period <= 500) np->minsync = 12; 3511 else np->minsync = (period + 40 - 1) / 40; 3512 3513 /* 3514 * Check against chip SCSI standard support (SCSI-2,ULTRA,ULTRA2). 3515 */ 3516 3517 if (np->minsync < 25 && !(np->features & (FE_ULTRA|FE_ULTRA2))) 3518 np->minsync = 25; 3519 else if (np->minsync < 12 && !(np->features & FE_ULTRA2)) 3520 np->minsync = 12; 3521 3522 /* 3523 * Maximum synchronous period factor supported by the chip. 3524 */ 3525 3526 period = (11 * div_10M[np->clock_divn - 1]) / (4 * np->clock_khz); 3527 np->maxsync = period > 2540 ? 254 : period / 10; 3528 3529 /* 3530 * Now, some features available with Symbios compatible boards. 3531 * LED support through GPIO0 and DIFF support. 3532 */ 3533 3534#ifdef SCSI_NCR_SYMBIOS_COMPAT 3535 if (!(np->rv_gpcntl & 0x01)) 3536 np->features |= FE_LED0; 3537#if 0 /* Not safe enough without NVRAM support or user settable option */ 3538 if (!(INB(nc_gpreg) & 0x08)) 3539 np->features |= FE_DIFF; 3540#endif 3541#endif /* SCSI_NCR_SYMBIOS_COMPAT */ 3542 3543 /* 3544 * Prepare initial IO registers settings. 3545 * Trust BIOS only if we believe we have one and if we want to. 3546 */ 3547#ifdef SCSI_NCR_TRUST_BIOS 3548 if (!(np->features & FE_BIOS)) { 3549#else 3550 if (1) { 3551#endif 3552 np->rv_dmode = 0; 3553 np->rv_dcntl = NOCOM; 3554 np->rv_ctest3 = 0; 3555 np->rv_ctest4 = MPEE; 3556 np->rv_ctest5 = 0; 3557 np->rv_stest2 = 0; 3558 3559 if (np->features & FE_ERL) 3560 np->rv_dmode |= ERL; /* Enable Read Line */ 3561 if (np->features & FE_BOF) 3562 np->rv_dmode |= BOF; /* Burst Opcode Fetch */ 3563 if (np->features & FE_ERMP) 3564 np->rv_dmode |= ERMP; /* Enable Read Multiple */ 3565 if (np->features & FE_CLSE) 3566 np->rv_dcntl |= CLSE; /* Cache Line Size Enable */ 3567 if (np->features & FE_WRIE) 3568 np->rv_ctest3 |= WRIE; /* Write and Invalidate */ 3569 if (np->features & FE_PFEN) 3570 np->rv_dcntl |= PFEN; /* Prefetch Enable */ 3571 if (np->features & FE_DFS) 3572 np->rv_ctest5 |= DFS; /* Dma Fifo Size */ 3573 if (np->features & FE_DIFF) 3574 np->rv_stest2 |= 0x20; /* Differential mode */ 3575 ncr_init_burst(np, np->maxburst); /* Max dwords burst length */ 3576 } else { 3577 np->maxburst = 3578 burst_code(np->rv_dmode, np->rv_ctest4, np->rv_ctest5); 3579 } 3580 3581 /* 3582 ** Get on-chip SRAM address, if supported 3583 */ 3584 if ((np->features & FE_RAM) && sizeof(struct script) <= 4096) { 3585 np->sram_rid = 0x18; 3586 np->sram_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 3587 &np->sram_rid, 3588 RF_ACTIVE); 3589 } 3590 3591 /* 3592 ** Allocate structure for script relocation. 3593 */ 3594 if (np->sram_res != NULL) { 3595 np->script = NULL; 3596 np->p_script = rman_get_start(np->sram_res); 3597 np->bst2 = rman_get_bustag(np->sram_res); 3598 np->bsh2 = rman_get_bushandle(np->sram_res); 3599 } else if (sizeof (struct script) > PAGE_SIZE) { 3600 np->script = (struct script*) contigmalloc 3601 (round_page(sizeof (struct script)), M_DEVBUF, M_WAITOK, 3602 0, 0xffffffff, PAGE_SIZE, 0); 3603 } else { 3604 np->script = (struct script *) 3605 malloc (sizeof (struct script), M_DEVBUF, M_WAITOK); 3606 } 3607 3608 if (sizeof (struct scripth) > PAGE_SIZE) { 3609 np->scripth = (struct scripth*) contigmalloc 3610 (round_page(sizeof (struct scripth)), M_DEVBUF, M_WAITOK, 3611 0, 0xffffffff, PAGE_SIZE, 0); 3612 } else 3613 { 3614 np->scripth = (struct scripth *) 3615 malloc (sizeof (struct scripth), M_DEVBUF, M_WAITOK); 3616 } 3617 3618#ifdef SCSI_NCR_PCI_CONFIG_FIXUP 3619 /* 3620 ** If cache line size is enabled, check PCI config space and 3621 ** try to fix it up if necessary. 3622 */ 3623#ifdef PCIR_CACHELNSZ /* To be sure that new PCI stuff is present */ 3624 { 3625 u_char cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 3626 u_short command = pci_read_config(dev, PCIR_COMMAND, 2); 3627 3628 if (!cachelnsz) { 3629 cachelnsz = 8; 3630 printf("%s: setting PCI cache line size register to %d.\n", 3631 ncr_name(np), (int)cachelnsz); 3632 pci_write_config(dev, PCIR_CACHELNSZ, cachelnsz, 1); 3633 } 3634 3635 if (!(command & (1<<4))) { 3636 command |= (1<<4); 3637 printf("%s: setting PCI command write and invalidate.\n", 3638 ncr_name(np)); 3639 pci_write_config(dev, PCIR_COMMAND, command, 2); 3640 } 3641 } 3642#endif /* PCIR_CACHELNSZ */ 3643 3644#endif /* SCSI_NCR_PCI_CONFIG_FIXUP */ 3645 3646 /* Initialize per-target user settings */ 3647 usrsync = 0; 3648 if (SCSI_NCR_DFLT_SYNC) { 3649 usrsync = SCSI_NCR_DFLT_SYNC; 3650 if (usrsync > np->maxsync) 3651 usrsync = np->maxsync; 3652 if (usrsync < np->minsync) 3653 usrsync = np->minsync; 3654 }; 3655 3656 usrwide = (SCSI_NCR_MAX_WIDE); 3657 if (usrwide > np->maxwide) usrwide=np->maxwide; 3658 3659 for (i=0;i<MAX_TARGET;i++) { 3660 tcb_p tp = &np->target[i]; 3661 3662 tp->tinfo.user.period = usrsync; 3663 tp->tinfo.user.offset = usrsync != 0 ? np->maxoffs : 0; 3664 tp->tinfo.user.width = usrwide; 3665 tp->tinfo.disc_tag = NCR_CUR_DISCENB 3666 | NCR_CUR_TAGENB 3667 | NCR_USR_DISCENB 3668 | NCR_USR_TAGENB; 3669 } 3670 3671 /* 3672 ** Bells and whistles ;-) 3673 */ 3674 if (bootverbose) 3675 printf("%s: minsync=%d, maxsync=%d, maxoffs=%d, %d dwords burst, %s dma fifo\n", 3676 ncr_name(np), np->minsync, np->maxsync, np->maxoffs, 3677 burst_length(np->maxburst), 3678 (np->rv_ctest5 & DFS) ? "large" : "normal"); 3679 3680 /* 3681 ** Print some complementary information that can be helpfull. 3682 */ 3683 if (bootverbose) 3684 printf("%s: %s, %s IRQ driver%s\n", 3685 ncr_name(np), 3686 np->rv_stest2 & 0x20 ? "differential" : "single-ended", 3687 np->rv_dcntl & IRQM ? "totem pole" : "open drain", 3688 np->sram_res ? ", using on-chip SRAM" : ""); 3689 3690 /* 3691 ** Patch scripts to physical addresses 3692 */ 3693 ncr_script_fill (&script0, &scripth0); 3694 3695 if (np->script) 3696 np->p_script = vtophys(np->script); 3697 np->p_scripth = vtophys(np->scripth); 3698 3699 ncr_script_copy_and_bind (np, (ncrcmd *) &script0, 3700 (ncrcmd *) np->script, sizeof(struct script)); 3701 3702 ncr_script_copy_and_bind (np, (ncrcmd *) &scripth0, 3703 (ncrcmd *) np->scripth, sizeof(struct scripth)); 3704 3705 /* 3706 ** Patch the script for LED support. 3707 */ 3708 3709 if (np->features & FE_LED0) { 3710 WRITESCRIPT(reselect[0], SCR_REG_REG(gpreg, SCR_OR, 0x01)); 3711 WRITESCRIPT(reselect1[0], SCR_REG_REG(gpreg, SCR_AND, 0xfe)); 3712 WRITESCRIPT(reselect2[0], SCR_REG_REG(gpreg, SCR_AND, 0xfe)); 3713 } 3714 3715 /* 3716 ** init data structure 3717 */ 3718 3719 np->jump_tcb.l_cmd = SCR_JUMP; 3720 np->jump_tcb.l_paddr = NCB_SCRIPTH_PHYS (np, abort); 3721 3722 /* 3723 ** Get SCSI addr of host adapter (set by bios?). 3724 */ 3725 3726 np->myaddr = INB(nc_scid) & 0x07; 3727 if (!np->myaddr) np->myaddr = SCSI_NCR_MYADDR; 3728 3729#ifdef NCR_DUMP_REG 3730 /* 3731 ** Log the initial register contents 3732 */ 3733 { 3734 int reg; 3735 for (reg=0; reg<256; reg+=4) { 3736 if (reg%16==0) printf ("reg[%2x]", reg); 3737 printf (" %08x", (int)pci_conf_read (config_id, reg)); 3738 if (reg%16==12) printf ("\n"); 3739 } 3740 } 3741#endif /* NCR_DUMP_REG */ 3742 3743 /* 3744 ** Reset chip. 3745 */ 3746 3747 OUTB (nc_istat, SRST); 3748 DELAY (1000); 3749 OUTB (nc_istat, 0 ); 3750 3751 3752 /* 3753 ** Now check the cache handling of the pci chipset. 3754 */ 3755 3756 if (ncr_snooptest (np)) { 3757 printf ("CACHE INCORRECTLY CONFIGURED.\n"); 3758 return EINVAL; 3759 }; 3760 3761 /* 3762 ** Install the interrupt handler. 3763 */ 3764 3765 rid = 0; 3766 np->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 3767 RF_SHAREABLE | RF_ACTIVE); 3768 if (np->irq_res == NULL) { 3769 device_printf(dev, 3770 "interruptless mode: reduced performance.\n"); 3771 } else { 3772 bus_setup_intr(dev, np->irq_res, INTR_TYPE_CAM | INTR_ENTROPY, 3773 ncr_intr, np, &np->irq_handle); 3774 } 3775 3776 /* 3777 ** Create the device queue. We only allow MAX_START-1 concurrent 3778 ** transactions so we can be sure to have one element free in our 3779 ** start queue to reset to the idle loop. 3780 */ 3781 devq = cam_simq_alloc(MAX_START - 1); 3782 if (devq == NULL) 3783 return ENOMEM; 3784 3785 /* 3786 ** Now tell the generic SCSI layer 3787 ** about our bus. 3788 */ 3789 np->sim = cam_sim_alloc(ncr_action, ncr_poll, "ncr", np, np->unit, 3790 1, MAX_TAGS, devq); 3791 if (np->sim == NULL) { 3792 cam_simq_free(devq); 3793 return ENOMEM; 3794 } 3795 3796 3797 if (xpt_bus_register(np->sim, 0) != CAM_SUCCESS) { 3798 cam_sim_free(np->sim, /*free_devq*/ TRUE); 3799 return ENOMEM; 3800 } 3801 3802 if (xpt_create_path(&np->path, /*periph*/NULL, 3803 cam_sim_path(np->sim), CAM_TARGET_WILDCARD, 3804 CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 3805 xpt_bus_deregister(cam_sim_path(np->sim)); 3806 cam_sim_free(np->sim, /*free_devq*/TRUE); 3807 return ENOMEM; 3808 } 3809 3810 /* 3811 ** start the timeout daemon 3812 */ 3813 ncr_timeout (np); 3814 np->lasttime=0; 3815 3816 return 0; 3817} 3818 3819/*========================================================== 3820** 3821** 3822** Process pending device interrupts. 3823** 3824** 3825**========================================================== 3826*/ 3827 3828static void 3829ncr_intr(vnp) 3830 void *vnp; 3831{ 3832 ncb_p np = vnp; 3833 int oldspl = splcam(); 3834 3835 if (DEBUG_FLAGS & DEBUG_TINY) printf ("["); 3836 3837 if (INB(nc_istat) & (INTF|SIP|DIP)) { 3838 /* 3839 ** Repeat until no outstanding ints 3840 */ 3841 do { 3842 ncr_exception (np); 3843 } while (INB(nc_istat) & (INTF|SIP|DIP)); 3844 3845 np->ticks = 100; 3846 }; 3847 3848 if (DEBUG_FLAGS & DEBUG_TINY) printf ("]\n"); 3849 3850 splx (oldspl); 3851} 3852 3853/*========================================================== 3854** 3855** 3856** Start execution of a SCSI command. 3857** This is called from the generic SCSI driver. 3858** 3859** 3860**========================================================== 3861*/ 3862 3863static void 3864ncr_action (struct cam_sim *sim, union ccb *ccb) 3865{ 3866 ncb_p np; 3867 3868 np = (ncb_p) cam_sim_softc(sim); 3869 3870 switch (ccb->ccb_h.func_code) { 3871 /* Common cases first */ 3872 case XPT_SCSI_IO: /* Execute the requested I/O operation */ 3873 { 3874 nccb_p cp; 3875 lcb_p lp; 3876 tcb_p tp; 3877 int oldspl; 3878 struct ccb_scsiio *csio; 3879 u_int8_t *msgptr; 3880 u_int msglen; 3881 u_int msglen2; 3882 int segments; 3883 u_int8_t nego; 3884 u_int8_t idmsg; 3885 int qidx; 3886 3887 tp = &np->target[ccb->ccb_h.target_id]; 3888 csio = &ccb->csio; 3889 3890 oldspl = splcam(); 3891 3892 /* 3893 * Last time we need to check if this CCB needs to 3894 * be aborted. 3895 */ 3896 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_INPROG) { 3897 xpt_done(ccb); 3898 splx(oldspl); 3899 return; 3900 } 3901 ccb->ccb_h.status |= CAM_SIM_QUEUED; 3902 3903 /*--------------------------------------------------- 3904 ** 3905 ** Assign an nccb / bind ccb 3906 ** 3907 **---------------------------------------------------- 3908 */ 3909 cp = ncr_get_nccb (np, ccb->ccb_h.target_id, 3910 ccb->ccb_h.target_lun); 3911 if (cp == NULL) { 3912 /* XXX JGibbs - Freeze SIMQ */ 3913 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 3914 xpt_done(ccb); 3915 return; 3916 }; 3917 3918 cp->ccb = ccb; 3919 3920 /*--------------------------------------------------- 3921 ** 3922 ** timestamp 3923 ** 3924 **---------------------------------------------------- 3925 */ 3926 /* 3927 ** XXX JGibbs - Isn't this expensive 3928 ** enough to be conditionalized?? 3929 */ 3930 3931 bzero (&cp->phys.header.stamp, sizeof (struct tstamp)); 3932 cp->phys.header.stamp.start = ticks; 3933 3934 nego = 0; 3935 if (tp->nego_cp == NULL) { 3936 3937 if (tp->tinfo.current.width 3938 != tp->tinfo.goal.width) { 3939 tp->nego_cp = cp; 3940 nego = NS_WIDE; 3941 } else if ((tp->tinfo.current.period 3942 != tp->tinfo.goal.period) 3943 || (tp->tinfo.current.offset 3944 != tp->tinfo.goal.offset)) { 3945 tp->nego_cp = cp; 3946 nego = NS_SYNC; 3947 }; 3948 }; 3949 3950 /*--------------------------------------------------- 3951 ** 3952 ** choose a new tag ... 3953 ** 3954 **---------------------------------------------------- 3955 */ 3956 lp = tp->lp[ccb->ccb_h.target_lun]; 3957 3958 if ((ccb->ccb_h.flags & CAM_TAG_ACTION_VALID) != 0 3959 && (ccb->csio.tag_action != CAM_TAG_ACTION_NONE) 3960 && (nego == 0)) { 3961 /* 3962 ** assign a tag to this nccb 3963 */ 3964 while (!cp->tag) { 3965 nccb_p cp2 = lp->next_nccb; 3966 lp->lasttag = lp->lasttag % 255 + 1; 3967 while (cp2 && cp2->tag != lp->lasttag) 3968 cp2 = cp2->next_nccb; 3969 if (cp2) continue; 3970 cp->tag=lp->lasttag; 3971 if (DEBUG_FLAGS & DEBUG_TAGS) { 3972 PRINT_ADDR(ccb); 3973 printf ("using tag #%d.\n", cp->tag); 3974 }; 3975 }; 3976 } else { 3977 cp->tag=0; 3978 }; 3979 3980 /*---------------------------------------------------- 3981 ** 3982 ** Build the identify / tag / sdtr message 3983 ** 3984 **---------------------------------------------------- 3985 */ 3986 idmsg = MSG_IDENTIFYFLAG | ccb->ccb_h.target_lun; 3987 if (tp->tinfo.disc_tag & NCR_CUR_DISCENB) 3988 idmsg |= MSG_IDENTIFY_DISCFLAG; 3989 3990 msgptr = cp->scsi_smsg; 3991 msglen = 0; 3992 msgptr[msglen++] = idmsg; 3993 3994 if (cp->tag) { 3995 msgptr[msglen++] = ccb->csio.tag_action; 3996 msgptr[msglen++] = cp->tag; 3997 } 3998 3999 switch (nego) { 4000 case NS_SYNC: 4001 msgptr[msglen++] = MSG_EXTENDED; 4002 msgptr[msglen++] = MSG_EXT_SDTR_LEN; 4003 msgptr[msglen++] = MSG_EXT_SDTR; 4004 msgptr[msglen++] = tp->tinfo.goal.period; 4005 msgptr[msglen++] = tp->tinfo.goal.offset;; 4006 if (DEBUG_FLAGS & DEBUG_NEGO) { 4007 PRINT_ADDR(ccb); 4008 printf ("sync msgout: "); 4009 ncr_show_msg (&cp->scsi_smsg [msglen-5]); 4010 printf (".\n"); 4011 }; 4012 break; 4013 case NS_WIDE: 4014 msgptr[msglen++] = MSG_EXTENDED; 4015 msgptr[msglen++] = MSG_EXT_WDTR_LEN; 4016 msgptr[msglen++] = MSG_EXT_WDTR; 4017 msgptr[msglen++] = tp->tinfo.goal.width; 4018 if (DEBUG_FLAGS & DEBUG_NEGO) { 4019 PRINT_ADDR(ccb); 4020 printf ("wide msgout: "); 4021 ncr_show_msg (&cp->scsi_smsg [msglen-4]); 4022 printf (".\n"); 4023 }; 4024 break; 4025 }; 4026 4027 /*---------------------------------------------------- 4028 ** 4029 ** Build the identify message for getcc. 4030 ** 4031 **---------------------------------------------------- 4032 */ 4033 4034 cp->scsi_smsg2 [0] = idmsg; 4035 msglen2 = 1; 4036 4037 /*---------------------------------------------------- 4038 ** 4039 ** Build the data descriptors 4040 ** 4041 **---------------------------------------------------- 4042 */ 4043 4044 /* XXX JGibbs - Handle other types of I/O */ 4045 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 4046 segments = ncr_scatter(&cp->phys, 4047 (vm_offset_t)csio->data_ptr, 4048 (vm_size_t)csio->dxfer_len); 4049 4050 if (segments < 0) { 4051 ccb->ccb_h.status = CAM_REQ_TOO_BIG; 4052 ncr_free_nccb(np, cp); 4053 splx(oldspl); 4054 xpt_done(ccb); 4055 return; 4056 } 4057 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 4058 cp->phys.header.savep = NCB_SCRIPT_PHYS (np, data_in); 4059 cp->phys.header.goalp = cp->phys.header.savep +20 +segments*16; 4060 } else { /* CAM_DIR_OUT */ 4061 cp->phys.header.savep = NCB_SCRIPT_PHYS (np, data_out); 4062 cp->phys.header.goalp = cp->phys.header.savep +20 +segments*16; 4063 } 4064 } else { 4065 cp->phys.header.savep = NCB_SCRIPT_PHYS (np, no_data); 4066 cp->phys.header.goalp = cp->phys.header.savep; 4067 } 4068 4069 cp->phys.header.lastp = cp->phys.header.savep; 4070 4071 4072 /*---------------------------------------------------- 4073 ** 4074 ** fill in nccb 4075 ** 4076 **---------------------------------------------------- 4077 ** 4078 ** 4079 ** physical -> virtual backlink 4080 ** Generic SCSI command 4081 */ 4082 cp->phys.header.cp = cp; 4083 /* 4084 ** Startqueue 4085 */ 4086 cp->phys.header.launch.l_paddr = NCB_SCRIPT_PHYS (np, select); 4087 cp->phys.header.launch.l_cmd = SCR_JUMP; 4088 /* 4089 ** select 4090 */ 4091 cp->phys.select.sel_id = ccb->ccb_h.target_id; 4092 cp->phys.select.sel_scntl3 = tp->tinfo.wval; 4093 cp->phys.select.sel_sxfer = tp->tinfo.sval; 4094 /* 4095 ** message 4096 */ 4097 cp->phys.smsg.addr = CCB_PHYS (cp, scsi_smsg); 4098 cp->phys.smsg.size = msglen; 4099 4100 cp->phys.smsg2.addr = CCB_PHYS (cp, scsi_smsg2); 4101 cp->phys.smsg2.size = msglen2; 4102 /* 4103 ** command 4104 */ 4105 /* XXX JGibbs - Support other command types */ 4106 cp->phys.cmd.addr = vtophys (csio->cdb_io.cdb_bytes); 4107 cp->phys.cmd.size = csio->cdb_len; 4108 /* 4109 ** sense command 4110 */ 4111 cp->phys.scmd.addr = CCB_PHYS (cp, sensecmd); 4112 cp->phys.scmd.size = 6; 4113 /* 4114 ** patch requested size into sense command 4115 */ 4116 cp->sensecmd[0] = 0x03; 4117 cp->sensecmd[1] = ccb->ccb_h.target_lun << 5; 4118 cp->sensecmd[4] = sizeof(struct scsi_sense_data); 4119 cp->sensecmd[4] = csio->sense_len; 4120 /* 4121 ** sense data 4122 */ 4123 cp->phys.sense.addr = vtophys (&csio->sense_data); 4124 cp->phys.sense.size = csio->sense_len; 4125 /* 4126 ** status 4127 */ 4128 cp->actualquirks = QUIRK_NOMSG; 4129 cp->host_status = nego ? HS_NEGOTIATE : HS_BUSY; 4130 cp->s_status = SCSI_STATUS_ILLEGAL; 4131 cp->parity_status = 0; 4132 4133 cp->xerr_status = XE_OK; 4134 cp->sync_status = tp->tinfo.sval; 4135 cp->nego_status = nego; 4136 cp->wide_status = tp->tinfo.wval; 4137 4138 /*---------------------------------------------------- 4139 ** 4140 ** Critical region: start this job. 4141 ** 4142 **---------------------------------------------------- 4143 */ 4144 4145 /* 4146 ** reselect pattern and activate this job. 4147 */ 4148 4149 cp->jump_nccb.l_cmd = (SCR_JUMP ^ IFFALSE (DATA (cp->tag))); 4150 cp->tlimit = time_second 4151 + ccb->ccb_h.timeout / 1000 + 2; 4152 cp->magic = CCB_MAGIC; 4153 4154 /* 4155 ** insert into start queue. 4156 */ 4157 4158 qidx = np->squeueput + 1; 4159 if (qidx >= MAX_START) 4160 qidx = 0; 4161 np->squeue [qidx ] = NCB_SCRIPT_PHYS (np, idle); 4162 np->squeue [np->squeueput] = CCB_PHYS (cp, phys); 4163 np->squeueput = qidx; 4164 4165 if(DEBUG_FLAGS & DEBUG_QUEUE) 4166 printf("%s: queuepos=%d tryoffset=%d.\n", 4167 ncr_name (np), np->squeueput, 4168 (unsigned)(READSCRIPT(startpos[0]) - 4169 (NCB_SCRIPTH_PHYS (np, tryloop)))); 4170 4171 /* 4172 ** Script processor may be waiting for reselect. 4173 ** Wake it up. 4174 */ 4175 OUTB (nc_istat, SIGP); 4176 4177 /* 4178 ** and reenable interrupts 4179 */ 4180 splx (oldspl); 4181 break; 4182 } 4183 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 4184 case XPT_EN_LUN: /* Enable LUN as a target */ 4185 case XPT_TARGET_IO: /* Execute target I/O request */ 4186 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 4187 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/ 4188 case XPT_ABORT: /* Abort the specified CCB */ 4189 /* XXX Implement */ 4190 ccb->ccb_h.status = CAM_REQ_INVALID; 4191 xpt_done(ccb); 4192 break; 4193 case XPT_SET_TRAN_SETTINGS: 4194 { 4195 struct ccb_trans_settings *cts; 4196 tcb_p tp; 4197 u_int update_type; 4198 int s; 4199 4200 cts = &ccb->cts; 4201 update_type = 0; 4202 if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) 4203 update_type |= NCR_TRANS_GOAL; 4204 if ((cts->flags & CCB_TRANS_USER_SETTINGS) != 0) 4205 update_type |= NCR_TRANS_USER; 4206 4207 s = splcam(); 4208 tp = &np->target[ccb->ccb_h.target_id]; 4209 /* Tag and disc enables */ 4210 if ((cts->valid & CCB_TRANS_DISC_VALID) != 0) { 4211 if (update_type & NCR_TRANS_GOAL) { 4212 if ((cts->flags & CCB_TRANS_DISC_ENB) != 0) 4213 tp->tinfo.disc_tag |= NCR_CUR_DISCENB; 4214 else 4215 tp->tinfo.disc_tag &= ~NCR_CUR_DISCENB; 4216 } 4217 4218 if (update_type & NCR_TRANS_USER) { 4219 if ((cts->flags & CCB_TRANS_DISC_ENB) != 0) 4220 tp->tinfo.disc_tag |= NCR_USR_DISCENB; 4221 else 4222 tp->tinfo.disc_tag &= ~NCR_USR_DISCENB; 4223 } 4224 4225 } 4226 4227 if ((cts->valid & CCB_TRANS_TQ_VALID) != 0) { 4228 if (update_type & NCR_TRANS_GOAL) { 4229 if ((cts->flags & CCB_TRANS_TAG_ENB) != 0) 4230 tp->tinfo.disc_tag |= NCR_CUR_TAGENB; 4231 else 4232 tp->tinfo.disc_tag &= ~NCR_CUR_TAGENB; 4233 } 4234 4235 if (update_type & NCR_TRANS_USER) { 4236 if ((cts->flags & CCB_TRANS_TAG_ENB) != 0) 4237 tp->tinfo.disc_tag |= NCR_USR_TAGENB; 4238 else 4239 tp->tinfo.disc_tag &= ~NCR_USR_TAGENB; 4240 } 4241 } 4242 4243 /* Filter bus width and sync negotiation settings */ 4244 if ((cts->valid & CCB_TRANS_BUS_WIDTH_VALID) != 0) { 4245 if (cts->bus_width > np->maxwide) 4246 cts->bus_width = np->maxwide; 4247 } 4248 4249 if (((cts->valid & CCB_TRANS_SYNC_RATE_VALID) != 0) 4250 || ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) != 0)) { 4251 if ((cts->valid & CCB_TRANS_SYNC_RATE_VALID) != 0) { 4252 if (cts->sync_period != 0 4253 && (cts->sync_period < np->minsync)) 4254 cts->sync_period = np->minsync; 4255 } 4256 if ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) != 0) { 4257 if (cts->sync_offset == 0) 4258 cts->sync_period = 0; 4259 if (cts->sync_offset > np->maxoffs) 4260 cts->sync_offset = np->maxoffs; 4261 } 4262 } 4263 if ((update_type & NCR_TRANS_USER) != 0) { 4264 if ((cts->valid & CCB_TRANS_SYNC_RATE_VALID) != 0) 4265 tp->tinfo.user.period = cts->sync_period; 4266 if ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) != 0) 4267 tp->tinfo.user.offset = cts->sync_offset; 4268 if ((cts->valid & CCB_TRANS_BUS_WIDTH_VALID) != 0) 4269 tp->tinfo.user.width = cts->bus_width; 4270 } 4271 if ((update_type & NCR_TRANS_GOAL) != 0) { 4272 if ((cts->valid & CCB_TRANS_SYNC_RATE_VALID) != 0) 4273 tp->tinfo.goal.period = cts->sync_period; 4274 4275 if ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) != 0) 4276 tp->tinfo.goal.offset = cts->sync_offset; 4277 4278 if ((cts->valid & CCB_TRANS_BUS_WIDTH_VALID) != 0) 4279 tp->tinfo.goal.width = cts->bus_width; 4280 } 4281 splx(s); 4282 ccb->ccb_h.status = CAM_REQ_CMP; 4283 xpt_done(ccb); 4284 break; 4285 } 4286 case XPT_GET_TRAN_SETTINGS: 4287 /* Get default/user set transfer settings for the target */ 4288 { 4289 struct ccb_trans_settings *cts; 4290 struct ncr_transinfo *tinfo; 4291 tcb_p tp; 4292 int s; 4293 4294 cts = &ccb->cts; 4295 tp = &np->target[ccb->ccb_h.target_id]; 4296 4297 s = splcam(); 4298 if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) { 4299 tinfo = &tp->tinfo.current; 4300 if (tp->tinfo.disc_tag & NCR_CUR_DISCENB) 4301 cts->flags |= CCB_TRANS_DISC_ENB; 4302 else 4303 cts->flags &= ~CCB_TRANS_DISC_ENB; 4304 4305 if (tp->tinfo.disc_tag & NCR_CUR_TAGENB) 4306 cts->flags |= CCB_TRANS_TAG_ENB; 4307 else 4308 cts->flags &= ~CCB_TRANS_TAG_ENB; 4309 } else { 4310 tinfo = &tp->tinfo.user; 4311 if (tp->tinfo.disc_tag & NCR_USR_DISCENB) 4312 cts->flags |= CCB_TRANS_DISC_ENB; 4313 else 4314 cts->flags &= ~CCB_TRANS_DISC_ENB; 4315 4316 if (tp->tinfo.disc_tag & NCR_USR_TAGENB) 4317 cts->flags |= CCB_TRANS_TAG_ENB; 4318 else 4319 cts->flags &= ~CCB_TRANS_TAG_ENB; 4320 } 4321 4322 cts->sync_period = tinfo->period; 4323 cts->sync_offset = tinfo->offset; 4324 cts->bus_width = tinfo->width; 4325 4326 splx(s); 4327 4328 cts->valid = CCB_TRANS_SYNC_RATE_VALID 4329 | CCB_TRANS_SYNC_OFFSET_VALID 4330 | CCB_TRANS_BUS_WIDTH_VALID 4331 | CCB_TRANS_DISC_VALID 4332 | CCB_TRANS_TQ_VALID; 4333 4334 ccb->ccb_h.status = CAM_REQ_CMP; 4335 xpt_done(ccb); 4336 break; 4337 } 4338 case XPT_CALC_GEOMETRY: 4339 { 4340 /* XXX JGibbs - I'm sure the NCR uses a different strategy, 4341 * but it should be able to deal with Adaptec 4342 * geometry too. 4343 */ 4344 cam_calc_geometry(&ccb->ccg, /*extended*/1); 4345 xpt_done(ccb); 4346 break; 4347 } 4348 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 4349 { 4350 OUTB (nc_scntl1, CRST); 4351 ccb->ccb_h.status = CAM_REQ_CMP; 4352 DELAY(10000); /* Wait until our interrupt handler sees it */ 4353 xpt_done(ccb); 4354 break; 4355 } 4356 case XPT_TERM_IO: /* Terminate the I/O process */ 4357 /* XXX Implement */ 4358 ccb->ccb_h.status = CAM_REQ_INVALID; 4359 xpt_done(ccb); 4360 break; 4361 case XPT_PATH_INQ: /* Path routing inquiry */ 4362 { 4363 struct ccb_pathinq *cpi = &ccb->cpi; 4364 4365 cpi->version_num = 1; /* XXX??? */ 4366 cpi->hba_inquiry = PI_SDTR_ABLE|PI_TAG_ABLE; 4367 if ((np->features & FE_WIDE) != 0) 4368 cpi->hba_inquiry |= PI_WIDE_16; 4369 cpi->target_sprt = 0; 4370 cpi->hba_misc = 0; 4371 cpi->hba_eng_cnt = 0; 4372 cpi->max_target = (np->features & FE_WIDE) ? 15 : 7; 4373 cpi->max_lun = MAX_LUN - 1; 4374 cpi->initiator_id = np->myaddr; 4375 cpi->bus_id = cam_sim_bus(sim); 4376 cpi->base_transfer_speed = 3300; 4377 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 4378 strncpy(cpi->hba_vid, "Symbios", HBA_IDLEN); 4379 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 4380 cpi->unit_number = cam_sim_unit(sim); 4381 cpi->ccb_h.status = CAM_REQ_CMP; 4382 xpt_done(ccb); 4383 break; 4384 } 4385 default: 4386 ccb->ccb_h.status = CAM_REQ_INVALID; 4387 xpt_done(ccb); 4388 break; 4389 } 4390} 4391 4392/*========================================================== 4393** 4394** 4395** Complete execution of a SCSI command. 4396** Signal completion to the generic SCSI driver. 4397** 4398** 4399**========================================================== 4400*/ 4401 4402static void 4403ncr_complete (ncb_p np, nccb_p cp) 4404{ 4405 union ccb *ccb; 4406 tcb_p tp; 4407 4408 /* 4409 ** Sanity check 4410 */ 4411 4412 if (!cp || (cp->magic!=CCB_MAGIC) || !cp->ccb) return; 4413 cp->magic = 1; 4414 cp->tlimit= 0; 4415 4416 /* 4417 ** No Reselect anymore. 4418 */ 4419 cp->jump_nccb.l_cmd = (SCR_JUMP); 4420 4421 /* 4422 ** No starting. 4423 */ 4424 cp->phys.header.launch.l_paddr= NCB_SCRIPT_PHYS (np, idle); 4425 4426 /* 4427 ** timestamp 4428 */ 4429 ncb_profile (np, cp); 4430 4431 if (DEBUG_FLAGS & DEBUG_TINY) 4432 printf ("CCB=%x STAT=%x/%x\n", (int)(intptr_t)cp & 0xfff, 4433 cp->host_status,cp->s_status); 4434 4435 ccb = cp->ccb; 4436 cp->ccb = NULL; 4437 tp = &np->target[ccb->ccb_h.target_id]; 4438 4439 /* 4440 ** We do not queue more than 1 nccb per target 4441 ** with negotiation at any time. If this nccb was 4442 ** used for negotiation, clear this info in the tcb. 4443 */ 4444 4445 if (cp == tp->nego_cp) 4446 tp->nego_cp = NULL; 4447 4448 /* 4449 ** Check for parity errors. 4450 */ 4451 /* XXX JGibbs - What about reporting them??? */ 4452 4453 if (cp->parity_status) { 4454 PRINT_ADDR(ccb); 4455 printf ("%d parity error(s), fallback.\n", cp->parity_status); 4456 /* 4457 ** fallback to asynch transfer. 4458 */ 4459 tp->tinfo.goal.period = 0; 4460 tp->tinfo.goal.offset = 0; 4461 }; 4462 4463 /* 4464 ** Check for extended errors. 4465 */ 4466 4467 if (cp->xerr_status != XE_OK) { 4468 PRINT_ADDR(ccb); 4469 switch (cp->xerr_status) { 4470 case XE_EXTRA_DATA: 4471 printf ("extraneous data discarded.\n"); 4472 break; 4473 case XE_BAD_PHASE: 4474 printf ("illegal scsi phase (4/5).\n"); 4475 break; 4476 default: 4477 printf ("extended error %d.\n", cp->xerr_status); 4478 break; 4479 }; 4480 if (cp->host_status==HS_COMPLETE) 4481 cp->host_status = HS_FAIL; 4482 }; 4483 4484 /* 4485 ** Check the status. 4486 */ 4487 if (cp->host_status == HS_COMPLETE) { 4488 4489 if (cp->s_status == SCSI_STATUS_OK) { 4490 4491 /* 4492 ** All went well. 4493 */ 4494 /* XXX JGibbs - Properly calculate residual */ 4495 4496 tp->bytes += ccb->csio.dxfer_len; 4497 tp->transfers ++; 4498 4499 ccb->ccb_h.status = CAM_REQ_CMP; 4500 } else if ((cp->s_status & SCSI_STATUS_SENSE) != 0) { 4501 4502 /* 4503 * XXX Could be TERMIO too. Should record 4504 * original status. 4505 */ 4506 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 4507 cp->s_status &= ~SCSI_STATUS_SENSE; 4508 if (cp->s_status == SCSI_STATUS_OK) { 4509 ccb->ccb_h.status = 4510 CAM_AUTOSNS_VALID|CAM_SCSI_STATUS_ERROR; 4511 } else { 4512 ccb->ccb_h.status = CAM_AUTOSENSE_FAIL; 4513 } 4514 } else { 4515 ccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; 4516 ccb->csio.scsi_status = cp->s_status; 4517 } 4518 4519 4520 } else if (cp->host_status == HS_SEL_TIMEOUT) { 4521 4522 /* 4523 ** Device failed selection 4524 */ 4525 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 4526 4527 } else if (cp->host_status == HS_TIMEOUT) { 4528 4529 /* 4530 ** No response 4531 */ 4532 ccb->ccb_h.status = CAM_CMD_TIMEOUT; 4533 } else if (cp->host_status == HS_STALL) { 4534 ccb->ccb_h.status = CAM_REQUEUE_REQ; 4535 } else { 4536 4537 /* 4538 ** Other protocol messes 4539 */ 4540 PRINT_ADDR(ccb); 4541 printf ("COMMAND FAILED (%x %x) @%p.\n", 4542 cp->host_status, cp->s_status, cp); 4543 4544 ccb->ccb_h.status = CAM_CMD_TIMEOUT; 4545 } 4546 4547 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP) { 4548 xpt_freeze_devq(ccb->ccb_h.path, /*count*/1); 4549 ccb->ccb_h.status |= CAM_DEV_QFRZN; 4550 } 4551 4552 /* 4553 ** Free this nccb 4554 */ 4555 ncr_free_nccb (np, cp); 4556 4557 /* 4558 ** signal completion to generic driver. 4559 */ 4560 xpt_done (ccb); 4561} 4562 4563/*========================================================== 4564** 4565** 4566** Signal all (or one) control block done. 4567** 4568** 4569**========================================================== 4570*/ 4571 4572static void 4573ncr_wakeup (ncb_p np, u_long code) 4574{ 4575 /* 4576 ** Starting at the default nccb and following 4577 ** the links, complete all jobs with a 4578 ** host_status greater than "disconnect". 4579 ** 4580 ** If the "code" parameter is not zero, 4581 ** complete all jobs that are not IDLE. 4582 */ 4583 4584 nccb_p cp = np->link_nccb; 4585 while (cp) { 4586 switch (cp->host_status) { 4587 4588 case HS_IDLE: 4589 break; 4590 4591 case HS_DISCONNECT: 4592 if(DEBUG_FLAGS & DEBUG_TINY) printf ("D"); 4593 /* FALLTHROUGH */ 4594 4595 case HS_BUSY: 4596 case HS_NEGOTIATE: 4597 if (!code) break; 4598 cp->host_status = code; 4599 4600 /* FALLTHROUGH */ 4601 4602 default: 4603 ncr_complete (np, cp); 4604 break; 4605 }; 4606 cp = cp -> link_nccb; 4607 }; 4608} 4609 4610static void 4611ncr_freeze_devq (ncb_p np, struct cam_path *path) 4612{ 4613 nccb_p cp; 4614 int i; 4615 int count; 4616 int firstskip; 4617 /* 4618 ** Starting at the first nccb and following 4619 ** the links, complete all jobs that match 4620 ** the passed in path and are in the start queue. 4621 */ 4622 4623 cp = np->link_nccb; 4624 count = 0; 4625 firstskip = 0; 4626 while (cp) { 4627 switch (cp->host_status) { 4628 4629 case HS_BUSY: 4630 case HS_NEGOTIATE: 4631 if ((cp->phys.header.launch.l_paddr 4632 == NCB_SCRIPT_PHYS (np, select)) 4633 && (xpt_path_comp(path, cp->ccb->ccb_h.path) >= 0)) { 4634 4635 /* Mark for removal from the start queue */ 4636 for (i = 1; i < MAX_START; i++) { 4637 int idx; 4638 4639 idx = np->squeueput - i; 4640 4641 if (idx < 0) 4642 idx = MAX_START + idx; 4643 if (np->squeue[idx] 4644 == CCB_PHYS(cp, phys)) { 4645 np->squeue[idx] = 4646 NCB_SCRIPT_PHYS (np, skip); 4647 if (i > firstskip) 4648 firstskip = i; 4649 break; 4650 } 4651 } 4652 cp->host_status=HS_STALL; 4653 ncr_complete (np, cp); 4654 count++; 4655 } 4656 break; 4657 default: 4658 break; 4659 } 4660 cp = cp->link_nccb; 4661 } 4662 4663 if (count > 0) { 4664 int j; 4665 int bidx; 4666 4667 /* Compress the start queue */ 4668 j = 0; 4669 bidx = np->squeueput; 4670 i = np->squeueput - firstskip; 4671 if (i < 0) 4672 i = MAX_START + i; 4673 for (;;) { 4674 4675 bidx = i - j; 4676 if (bidx < 0) 4677 bidx = MAX_START + bidx; 4678 4679 if (np->squeue[i] == NCB_SCRIPT_PHYS (np, skip)) { 4680 j++; 4681 } else if (j != 0) { 4682 np->squeue[bidx] = np->squeue[i]; 4683 if (np->squeue[bidx] 4684 == NCB_SCRIPT_PHYS(np, idle)) 4685 break; 4686 } 4687 i = (i + 1) % MAX_START; 4688 } 4689 np->squeueput = bidx; 4690 } 4691} 4692 4693/*========================================================== 4694** 4695** 4696** Start NCR chip. 4697** 4698** 4699**========================================================== 4700*/ 4701 4702static void 4703ncr_init(ncb_p np, char * msg, u_long code) 4704{ 4705 int i; 4706 4707 /* 4708 ** Reset chip. 4709 */ 4710 4711 OUTB (nc_istat, SRST); 4712 DELAY (1000); 4713 OUTB (nc_istat, 0); 4714 4715 /* 4716 ** Message. 4717 */ 4718 4719 if (msg) printf ("%s: restart (%s).\n", ncr_name (np), msg); 4720 4721 /* 4722 ** Clear Start Queue 4723 */ 4724 4725 for (i=0;i<MAX_START;i++) 4726 np -> squeue [i] = NCB_SCRIPT_PHYS (np, idle); 4727 4728 /* 4729 ** Start at first entry. 4730 */ 4731 4732 np->squeueput = 0; 4733 WRITESCRIPT(startpos[0], NCB_SCRIPTH_PHYS (np, tryloop)); 4734 WRITESCRIPT(start0 [0], SCR_INT ^ IFFALSE (0)); 4735 4736 /* 4737 ** Wakeup all pending jobs. 4738 */ 4739 4740 ncr_wakeup (np, code); 4741 4742 /* 4743 ** Init chip. 4744 */ 4745 4746 OUTB (nc_istat, 0x00 ); /* Remove Reset, abort ... */ 4747 OUTB (nc_scntl0, 0xca ); /* full arb., ena parity, par->ATN */ 4748 OUTB (nc_scntl1, 0x00 ); /* odd parity, and remove CRST!! */ 4749 ncr_selectclock(np, np->rv_scntl3); /* Select SCSI clock */ 4750 OUTB (nc_scid , RRE|np->myaddr);/* host adapter SCSI address */ 4751 OUTW (nc_respid, 1ul<<np->myaddr);/* id to respond to */ 4752 OUTB (nc_istat , SIGP ); /* Signal Process */ 4753 OUTB (nc_dmode , np->rv_dmode); /* XXX modify burstlen ??? */ 4754 OUTB (nc_dcntl , np->rv_dcntl); 4755 OUTB (nc_ctest3, np->rv_ctest3); 4756 OUTB (nc_ctest5, np->rv_ctest5); 4757 OUTB (nc_ctest4, np->rv_ctest4);/* enable master parity checking */ 4758 OUTB (nc_stest2, np->rv_stest2|EXT); /* Extended Sreq/Sack filtering */ 4759 OUTB (nc_stest3, TE ); /* TolerANT enable */ 4760 OUTB (nc_stime0, 0x0b ); /* HTH = disabled, STO = 0.1 sec. */ 4761 4762 if (bootverbose >= 2) { 4763 printf ("\tACTUAL values:SCNTL3:%02x DMODE:%02x DCNTL:%02x\n", 4764 np->rv_scntl3, np->rv_dmode, np->rv_dcntl); 4765 printf ("\t CTEST3:%02x CTEST4:%02x CTEST5:%02x\n", 4766 np->rv_ctest3, np->rv_ctest4, np->rv_ctest5); 4767 } 4768 4769 /* 4770 ** Enable GPIO0 pin for writing if LED support. 4771 */ 4772 4773 if (np->features & FE_LED0) { 4774 OUTOFFB (nc_gpcntl, 0x01); 4775 } 4776 4777 /* 4778 ** Fill in target structure. 4779 */ 4780 for (i=0;i<MAX_TARGET;i++) { 4781 tcb_p tp = &np->target[i]; 4782 4783 tp->tinfo.sval = 0; 4784 tp->tinfo.wval = np->rv_scntl3; 4785 4786 tp->tinfo.current.period = 0; 4787 tp->tinfo.current.offset = 0; 4788 tp->tinfo.current.width = MSG_EXT_WDTR_BUS_8_BIT; 4789 } 4790 4791 /* 4792 ** enable ints 4793 */ 4794 4795 OUTW (nc_sien , STO|HTH|MA|SGE|UDC|RST); 4796 OUTB (nc_dien , MDPE|BF|ABRT|SSI|SIR|IID); 4797 4798 /* 4799 ** Start script processor. 4800 */ 4801 4802 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, start)); 4803 4804 /* 4805 * Notify the XPT of the event 4806 */ 4807 if (code == HS_RESET) 4808 xpt_async(AC_BUS_RESET, np->path, NULL); 4809} 4810 4811static void 4812ncr_poll(struct cam_sim *sim) 4813{ 4814 ncr_intr(cam_sim_softc(sim)); 4815} 4816 4817 4818/*========================================================== 4819** 4820** Get clock factor and sync divisor for a given 4821** synchronous factor period. 4822** Returns the clock factor (in sxfer) and scntl3 4823** synchronous divisor field. 4824** 4825**========================================================== 4826*/ 4827 4828static void ncr_getsync(ncb_p np, u_char sfac, u_char *fakp, u_char *scntl3p) 4829{ 4830 u_long clk = np->clock_khz; /* SCSI clock frequency in kHz */ 4831 int div = np->clock_divn; /* Number of divisors supported */ 4832 u_long fak; /* Sync factor in sxfer */ 4833 u_long per; /* Period in tenths of ns */ 4834 u_long kpc; /* (per * clk) */ 4835 4836 /* 4837 ** Compute the synchronous period in tenths of nano-seconds 4838 */ 4839 if (sfac <= 10) per = 250; 4840 else if (sfac == 11) per = 303; 4841 else if (sfac == 12) per = 500; 4842 else per = 40 * sfac; 4843 4844 /* 4845 ** Look for the greatest clock divisor that allows an 4846 ** input speed faster than the period. 4847 */ 4848 kpc = per * clk; 4849 while (--div >= 0) 4850 if (kpc >= (div_10M[div] * 4)) break; 4851 4852 /* 4853 ** Calculate the lowest clock factor that allows an output 4854 ** speed not faster than the period. 4855 */ 4856 fak = (kpc - 1) / div_10M[div] + 1; 4857 4858#if 0 /* You can #if 1 if you think this optimization is usefull */ 4859 4860 per = (fak * div_10M[div]) / clk; 4861 4862 /* 4863 ** Why not to try the immediate lower divisor and to choose 4864 ** the one that allows the fastest output speed ? 4865 ** We dont want input speed too much greater than output speed. 4866 */ 4867 if (div >= 1 && fak < 6) { 4868 u_long fak2, per2; 4869 fak2 = (kpc - 1) / div_10M[div-1] + 1; 4870 per2 = (fak2 * div_10M[div-1]) / clk; 4871 if (per2 < per && fak2 <= 6) { 4872 fak = fak2; 4873 per = per2; 4874 --div; 4875 } 4876 } 4877#endif 4878 4879 if (fak < 4) fak = 4; /* Should never happen, too bad ... */ 4880 4881 /* 4882 ** Compute and return sync parameters for the ncr 4883 */ 4884 *fakp = fak - 4; 4885 *scntl3p = ((div+1) << 4) + (sfac < 25 ? 0x80 : 0); 4886} 4887 4888/*========================================================== 4889** 4890** Switch sync mode for current job and its target 4891** 4892**========================================================== 4893*/ 4894 4895static void 4896ncr_setsync(ncb_p np, nccb_p cp, u_char scntl3, u_char sxfer, u_char period) 4897{ 4898 union ccb *ccb; 4899 struct ccb_trans_settings neg; 4900 tcb_p tp; 4901 int div; 4902 u_int target = INB (nc_sdid) & 0x0f; 4903 u_int period_10ns; 4904 4905 assert (cp); 4906 if (!cp) return; 4907 4908 ccb = cp->ccb; 4909 assert (ccb); 4910 if (!ccb) return; 4911 assert (target == ccb->ccb_h.target_id); 4912 4913 tp = &np->target[target]; 4914 4915 if (!scntl3 || !(sxfer & 0x1f)) 4916 scntl3 = np->rv_scntl3; 4917 scntl3 = (scntl3 & 0xf0) | (tp->tinfo.wval & EWS) 4918 | (np->rv_scntl3 & 0x07); 4919 4920 /* 4921 ** Deduce the value of controller sync period from scntl3. 4922 ** period is in tenths of nano-seconds. 4923 */ 4924 4925 div = ((scntl3 >> 4) & 0x7); 4926 if ((sxfer & 0x1f) && div) 4927 period_10ns = 4928 (((sxfer>>5)+4)*div_10M[div-1])/np->clock_khz; 4929 else 4930 period_10ns = 0; 4931 4932 tp->tinfo.goal.period = period; 4933 tp->tinfo.goal.offset = sxfer & 0x1f; 4934 tp->tinfo.current.period = period; 4935 tp->tinfo.current.offset = sxfer & 0x1f; 4936 4937 /* 4938 ** Stop there if sync parameters are unchanged 4939 */ 4940 if (tp->tinfo.sval == sxfer && tp->tinfo.wval == scntl3) return; 4941 tp->tinfo.sval = sxfer; 4942 tp->tinfo.wval = scntl3; 4943 4944 if (sxfer & 0x1f) { 4945 /* 4946 ** Disable extended Sreq/Sack filtering 4947 */ 4948 if (period_10ns <= 2000) OUTOFFB (nc_stest2, EXT); 4949 } 4950 4951 /* 4952 ** Tell the SCSI layer about the 4953 ** new transfer parameters. 4954 */ 4955 neg.sync_period = period; 4956 neg.sync_offset = sxfer & 0x1f; 4957 neg.valid = CCB_TRANS_SYNC_RATE_VALID 4958 | CCB_TRANS_SYNC_OFFSET_VALID; 4959 xpt_setup_ccb(&neg.ccb_h, ccb->ccb_h.path, 4960 /*priority*/1); 4961 xpt_async(AC_TRANSFER_NEG, ccb->ccb_h.path, &neg); 4962 4963 /* 4964 ** set actual value and sync_status 4965 */ 4966 OUTB (nc_sxfer, sxfer); 4967 np->sync_st = sxfer; 4968 OUTB (nc_scntl3, scntl3); 4969 np->wide_st = scntl3; 4970 4971 /* 4972 ** patch ALL nccbs of this target. 4973 */ 4974 for (cp = np->link_nccb; cp; cp = cp->link_nccb) { 4975 if (!cp->ccb) continue; 4976 if (cp->ccb->ccb_h.target_id != target) continue; 4977 cp->sync_status = sxfer; 4978 cp->wide_status = scntl3; 4979 }; 4980} 4981 4982/*========================================================== 4983** 4984** Switch wide mode for current job and its target 4985** SCSI specs say: a SCSI device that accepts a WDTR 4986** message shall reset the synchronous agreement to 4987** asynchronous mode. 4988** 4989**========================================================== 4990*/ 4991 4992static void ncr_setwide (ncb_p np, nccb_p cp, u_char wide, u_char ack) 4993{ 4994 union ccb *ccb; 4995 struct ccb_trans_settings neg; 4996 u_int target = INB (nc_sdid) & 0x0f; 4997 tcb_p tp; 4998 u_char scntl3; 4999 u_char sxfer; 5000 5001 assert (cp); 5002 if (!cp) return; 5003 5004 ccb = cp->ccb; 5005 assert (ccb); 5006 if (!ccb) return; 5007 assert (target == ccb->ccb_h.target_id); 5008 5009 tp = &np->target[target]; 5010 tp->tinfo.current.width = wide; 5011 tp->tinfo.goal.width = wide; 5012 tp->tinfo.current.period = 0; 5013 tp->tinfo.current.offset = 0; 5014 5015 scntl3 = (tp->tinfo.wval & (~EWS)) | (wide ? EWS : 0); 5016 5017 sxfer = ack ? 0 : tp->tinfo.sval; 5018 5019 /* 5020 ** Stop there if sync/wide parameters are unchanged 5021 */ 5022 if (tp->tinfo.sval == sxfer && tp->tinfo.wval == scntl3) return; 5023 tp->tinfo.sval = sxfer; 5024 tp->tinfo.wval = scntl3; 5025 5026 /* Tell the SCSI layer about the new transfer params */ 5027 neg.bus_width = (scntl3 & EWS) ? MSG_EXT_WDTR_BUS_16_BIT 5028 : MSG_EXT_WDTR_BUS_8_BIT; 5029 neg.sync_period = 0; 5030 neg.sync_offset = 0; 5031 neg.valid = CCB_TRANS_BUS_WIDTH_VALID 5032 | CCB_TRANS_SYNC_RATE_VALID 5033 | CCB_TRANS_SYNC_OFFSET_VALID; 5034 xpt_setup_ccb(&neg.ccb_h, ccb->ccb_h.path, 5035 /*priority*/1); 5036 xpt_async(AC_TRANSFER_NEG, ccb->ccb_h.path, &neg); 5037 5038 /* 5039 ** set actual value and sync_status 5040 */ 5041 OUTB (nc_sxfer, sxfer); 5042 np->sync_st = sxfer; 5043 OUTB (nc_scntl3, scntl3); 5044 np->wide_st = scntl3; 5045 5046 /* 5047 ** patch ALL nccbs of this target. 5048 */ 5049 for (cp = np->link_nccb; cp; cp = cp->link_nccb) { 5050 if (!cp->ccb) continue; 5051 if (cp->ccb->ccb_h.target_id != target) continue; 5052 cp->sync_status = sxfer; 5053 cp->wide_status = scntl3; 5054 }; 5055} 5056 5057/*========================================================== 5058** 5059** 5060** ncr timeout handler. 5061** 5062** 5063**========================================================== 5064** 5065** Misused to keep the driver running when 5066** interrupts are not configured correctly. 5067** 5068**---------------------------------------------------------- 5069*/ 5070 5071static void 5072ncr_timeout (void *arg) 5073{ 5074 ncb_p np = arg; 5075 time_t thistime = time_second; 5076 ticks_t step = np->ticks; 5077 u_long count = 0; 5078 long signed t; 5079 nccb_p cp; 5080 5081 if (np->lasttime != thistime) { 5082 /* 5083 ** block ncr interrupts 5084 */ 5085 int oldspl = splcam(); 5086 np->lasttime = thistime; 5087 5088 /*---------------------------------------------------- 5089 ** 5090 ** handle ncr chip timeouts 5091 ** 5092 ** Assumption: 5093 ** We have a chance to arbitrate for the 5094 ** SCSI bus at least every 10 seconds. 5095 ** 5096 **---------------------------------------------------- 5097 */ 5098 5099 t = thistime - np->heartbeat; 5100 5101 if (t<2) np->latetime=0; else np->latetime++; 5102 5103 if (np->latetime>2) { 5104 /* 5105 ** If there are no requests, the script 5106 ** processor will sleep on SEL_WAIT_RESEL. 5107 ** But we have to check whether it died. 5108 ** Let's try to wake it up. 5109 */ 5110 OUTB (nc_istat, SIGP); 5111 }; 5112 5113 /*---------------------------------------------------- 5114 ** 5115 ** handle nccb timeouts 5116 ** 5117 **---------------------------------------------------- 5118 */ 5119 5120 for (cp=np->link_nccb; cp; cp=cp->link_nccb) { 5121 /* 5122 ** look for timed out nccbs. 5123 */ 5124 if (!cp->host_status) continue; 5125 count++; 5126 if (cp->tlimit > thistime) continue; 5127 5128 /* 5129 ** Disable reselect. 5130 ** Remove it from startqueue. 5131 */ 5132 cp->jump_nccb.l_cmd = (SCR_JUMP); 5133 if (cp->phys.header.launch.l_paddr == 5134 NCB_SCRIPT_PHYS (np, select)) { 5135 printf ("%s: timeout nccb=%p (skip)\n", 5136 ncr_name (np), cp); 5137 cp->phys.header.launch.l_paddr 5138 = NCB_SCRIPT_PHYS (np, skip); 5139 }; 5140 5141 switch (cp->host_status) { 5142 5143 case HS_BUSY: 5144 case HS_NEGOTIATE: 5145 /* FALLTHROUGH */ 5146 case HS_DISCONNECT: 5147 cp->host_status=HS_TIMEOUT; 5148 }; 5149 cp->tag = 0; 5150 5151 /* 5152 ** wakeup this nccb. 5153 */ 5154 ncr_complete (np, cp); 5155 }; 5156 splx (oldspl); 5157 } 5158 5159 np->timeout_ch = 5160 timeout (ncr_timeout, (caddr_t) np, step ? step : 1); 5161 5162 if (INB(nc_istat) & (INTF|SIP|DIP)) { 5163 5164 /* 5165 ** Process pending interrupts. 5166 */ 5167 5168 int oldspl = splcam(); 5169 if (DEBUG_FLAGS & DEBUG_TINY) printf ("{"); 5170 ncr_exception (np); 5171 if (DEBUG_FLAGS & DEBUG_TINY) printf ("}"); 5172 splx (oldspl); 5173 }; 5174} 5175 5176/*========================================================== 5177** 5178** log message for real hard errors 5179** 5180** "ncr0 targ 0?: ERROR (ds:si) (so-si-sd) (sxfer/scntl3) @ name (dsp:dbc)." 5181** " reg: r0 r1 r2 r3 r4 r5 r6 ..... rf." 5182** 5183** exception register: 5184** ds: dstat 5185** si: sist 5186** 5187** SCSI bus lines: 5188** so: control lines as driver by NCR. 5189** si: control lines as seen by NCR. 5190** sd: scsi data lines as seen by NCR. 5191** 5192** wide/fastmode: 5193** sxfer: (see the manual) 5194** scntl3: (see the manual) 5195** 5196** current script command: 5197** dsp: script address (relative to start of script). 5198** dbc: first word of script command. 5199** 5200** First 16 register of the chip: 5201** r0..rf 5202** 5203**========================================================== 5204*/ 5205 5206static void ncr_log_hard_error(ncb_p np, u_short sist, u_char dstat) 5207{ 5208 u_int32_t dsp; 5209 int script_ofs; 5210 int script_size; 5211 char *script_name; 5212 u_char *script_base; 5213 int i; 5214 5215 dsp = INL (nc_dsp); 5216 5217 if (np->p_script < dsp && 5218 dsp <= np->p_script + sizeof(struct script)) { 5219 script_ofs = dsp - np->p_script; 5220 script_size = sizeof(struct script); 5221 script_base = (u_char *) np->script; 5222 script_name = "script"; 5223 } 5224 else if (np->p_scripth < dsp && 5225 dsp <= np->p_scripth + sizeof(struct scripth)) { 5226 script_ofs = dsp - np->p_scripth; 5227 script_size = sizeof(struct scripth); 5228 script_base = (u_char *) np->scripth; 5229 script_name = "scripth"; 5230 } else { 5231 script_ofs = dsp; 5232 script_size = 0; 5233 script_base = 0; 5234 script_name = "mem"; 5235 } 5236 5237 printf ("%s:%d: ERROR (%x:%x) (%x-%x-%x) (%x/%x) @ (%s %x:%08x).\n", 5238 ncr_name (np), (unsigned)INB (nc_sdid)&0x0f, dstat, sist, 5239 (unsigned)INB (nc_socl), (unsigned)INB (nc_sbcl), (unsigned)INB (nc_sbdl), 5240 (unsigned)INB (nc_sxfer),(unsigned)INB (nc_scntl3), script_name, script_ofs, 5241 (unsigned)INL (nc_dbc)); 5242 5243 if (((script_ofs & 3) == 0) && 5244 (unsigned)script_ofs < script_size) { 5245 printf ("%s: script cmd = %08x\n", ncr_name(np), 5246 (int)READSCRIPT_OFF(script_base, script_ofs)); 5247 } 5248 5249 printf ("%s: regdump:", ncr_name(np)); 5250 for (i=0; i<16;i++) 5251 printf (" %02x", (unsigned)INB_OFF(i)); 5252 printf (".\n"); 5253} 5254 5255/*========================================================== 5256** 5257** 5258** ncr chip exception handler. 5259** 5260** 5261**========================================================== 5262*/ 5263 5264static void ncr_exception (ncb_p np) 5265{ 5266 u_char istat, dstat; 5267 u_short sist; 5268 5269 /* 5270 ** interrupt on the fly ? 5271 */ 5272 while ((istat = INB (nc_istat)) & INTF) { 5273 if (DEBUG_FLAGS & DEBUG_TINY) printf ("F "); 5274 OUTB (nc_istat, INTF); 5275 np->profile.num_fly++; 5276 ncr_wakeup (np, 0); 5277 }; 5278 if (!(istat & (SIP|DIP))) { 5279 return; 5280 } 5281 5282 /* 5283 ** Steinbach's Guideline for Systems Programming: 5284 ** Never test for an error condition you don't know how to handle. 5285 */ 5286 5287 sist = (istat & SIP) ? INW (nc_sist) : 0; 5288 dstat = (istat & DIP) ? INB (nc_dstat) : 0; 5289 np->profile.num_int++; 5290 5291 if (DEBUG_FLAGS & DEBUG_TINY) 5292 printf ("<%d|%x:%x|%x:%x>", 5293 INB(nc_scr0), 5294 dstat,sist, 5295 (unsigned)INL(nc_dsp), 5296 (unsigned)INL(nc_dbc)); 5297 if ((dstat==DFE) && (sist==PAR)) return; 5298 5299/*========================================================== 5300** 5301** First the normal cases. 5302** 5303**========================================================== 5304*/ 5305 /*------------------------------------------- 5306 ** SCSI reset 5307 **------------------------------------------- 5308 */ 5309 5310 if (sist & RST) { 5311 ncr_init (np, bootverbose ? "scsi reset" : NULL, HS_RESET); 5312 return; 5313 }; 5314 5315 /*------------------------------------------- 5316 ** selection timeout 5317 ** 5318 ** IID excluded from dstat mask! 5319 ** (chip bug) 5320 **------------------------------------------- 5321 */ 5322 5323 if ((sist & STO) && 5324 !(sist & (GEN|HTH|MA|SGE|UDC|RST|PAR)) && 5325 !(dstat & (MDPE|BF|ABRT|SIR))) { 5326 ncr_int_sto (np); 5327 return; 5328 }; 5329 5330 /*------------------------------------------- 5331 ** Phase mismatch. 5332 **------------------------------------------- 5333 */ 5334 5335 if ((sist & MA) && 5336 !(sist & (STO|GEN|HTH|SGE|UDC|RST|PAR)) && 5337 !(dstat & (MDPE|BF|ABRT|SIR|IID))) { 5338 ncr_int_ma (np, dstat); 5339 return; 5340 }; 5341 5342 /*---------------------------------------- 5343 ** move command with length 0 5344 **---------------------------------------- 5345 */ 5346 5347 if ((dstat & IID) && 5348 !(sist & (STO|GEN|HTH|MA|SGE|UDC|RST|PAR)) && 5349 !(dstat & (MDPE|BF|ABRT|SIR)) && 5350 ((INL(nc_dbc) & 0xf8000000) == SCR_MOVE_TBL)) { 5351 /* 5352 ** Target wants more data than available. 5353 ** The "no_data" script will do it. 5354 */ 5355 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, no_data)); 5356 return; 5357 }; 5358 5359 /*------------------------------------------- 5360 ** Programmed interrupt 5361 **------------------------------------------- 5362 */ 5363 5364 if ((dstat & SIR) && 5365 !(sist & (STO|GEN|HTH|MA|SGE|UDC|RST|PAR)) && 5366 !(dstat & (MDPE|BF|ABRT|IID)) && 5367 (INB(nc_dsps) <= SIR_MAX)) { 5368 ncr_int_sir (np); 5369 return; 5370 }; 5371 5372 /*======================================== 5373 ** log message for real hard errors 5374 **======================================== 5375 */ 5376 5377 ncr_log_hard_error(np, sist, dstat); 5378 5379 /*======================================== 5380 ** do the register dump 5381 **======================================== 5382 */ 5383 5384 if (time_second - np->regtime > 10) { 5385 int i; 5386 np->regtime = time_second; 5387 for (i=0; i<sizeof(np->regdump); i++) 5388 ((volatile char*)&np->regdump)[i] = INB_OFF(i); 5389 np->regdump.nc_dstat = dstat; 5390 np->regdump.nc_sist = sist; 5391 }; 5392 5393 5394 /*---------------------------------------- 5395 ** clean up the dma fifo 5396 **---------------------------------------- 5397 */ 5398 5399 if ( (INB(nc_sstat0) & (ILF|ORF|OLF) ) || 5400 (INB(nc_sstat1) & (FF3210) ) || 5401 (INB(nc_sstat2) & (ILF1|ORF1|OLF1)) || /* wide .. */ 5402 !(dstat & DFE)) { 5403 printf ("%s: have to clear fifos.\n", ncr_name (np)); 5404 OUTB (nc_stest3, TE|CSF); /* clear scsi fifo */ 5405 OUTB (nc_ctest3, np->rv_ctest3 | CLF); 5406 /* clear dma fifo */ 5407 } 5408 5409 /*---------------------------------------- 5410 ** handshake timeout 5411 **---------------------------------------- 5412 */ 5413 5414 if (sist & HTH) { 5415 printf ("%s: handshake timeout\n", ncr_name(np)); 5416 OUTB (nc_scntl1, CRST); 5417 DELAY (1000); 5418 OUTB (nc_scntl1, 0x00); 5419 OUTB (nc_scr0, HS_FAIL); 5420 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, cleanup)); 5421 return; 5422 } 5423 5424 /*---------------------------------------- 5425 ** unexpected disconnect 5426 **---------------------------------------- 5427 */ 5428 5429 if ((sist & UDC) && 5430 !(sist & (STO|GEN|HTH|MA|SGE|RST|PAR)) && 5431 !(dstat & (MDPE|BF|ABRT|SIR|IID))) { 5432 OUTB (nc_scr0, HS_UNEXPECTED); 5433 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, cleanup)); 5434 return; 5435 }; 5436 5437 /*---------------------------------------- 5438 ** cannot disconnect 5439 **---------------------------------------- 5440 */ 5441 5442 if ((dstat & IID) && 5443 !(sist & (STO|GEN|HTH|MA|SGE|UDC|RST|PAR)) && 5444 !(dstat & (MDPE|BF|ABRT|SIR)) && 5445 ((INL(nc_dbc) & 0xf8000000) == SCR_WAIT_DISC)) { 5446 /* 5447 ** Unexpected data cycle while waiting for disconnect. 5448 */ 5449 if (INB(nc_sstat2) & LDSC) { 5450 /* 5451 ** It's an early reconnect. 5452 ** Let's continue ... 5453 */ 5454 OUTB (nc_dcntl, np->rv_dcntl | STD); 5455 /* 5456 ** info message 5457 */ 5458 printf ("%s: INFO: LDSC while IID.\n", 5459 ncr_name (np)); 5460 return; 5461 }; 5462 printf ("%s: target %d doesn't release the bus.\n", 5463 ncr_name (np), INB (nc_sdid)&0x0f); 5464 /* 5465 ** return without restarting the NCR. 5466 ** timeout will do the real work. 5467 */ 5468 return; 5469 }; 5470 5471 /*---------------------------------------- 5472 ** single step 5473 **---------------------------------------- 5474 */ 5475 5476 if ((dstat & SSI) && 5477 !(sist & (STO|GEN|HTH|MA|SGE|UDC|RST|PAR)) && 5478 !(dstat & (MDPE|BF|ABRT|SIR|IID))) { 5479 OUTB (nc_dcntl, np->rv_dcntl | STD); 5480 return; 5481 }; 5482 5483/* 5484** @RECOVER@ HTH, SGE, ABRT. 5485** 5486** We should try to recover from these interrupts. 5487** They may occur if there are problems with synch transfers, or 5488** if targets are switched on or off while the driver is running. 5489*/ 5490 5491 if (sist & SGE) { 5492 /* clear scsi offsets */ 5493 OUTB (nc_ctest3, np->rv_ctest3 | CLF); 5494 } 5495 5496 /* 5497 ** Freeze controller to be able to read the messages. 5498 */ 5499 5500 if (DEBUG_FLAGS & DEBUG_FREEZE) { 5501 int i; 5502 unsigned char val; 5503 for (i=0; i<0x60; i++) { 5504 switch (i%16) { 5505 5506 case 0: 5507 printf ("%s: reg[%d0]: ", 5508 ncr_name(np),i/16); 5509 break; 5510 case 4: 5511 case 8: 5512 case 12: 5513 printf (" "); 5514 break; 5515 }; 5516 val = bus_space_read_1(np->bst, np->bsh, i); 5517 printf (" %x%x", val/16, val%16); 5518 if (i%16==15) printf (".\n"); 5519 }; 5520 5521 untimeout (ncr_timeout, (caddr_t) np, np->timeout_ch); 5522 5523 printf ("%s: halted!\n", ncr_name(np)); 5524 /* 5525 ** don't restart controller ... 5526 */ 5527 OUTB (nc_istat, SRST); 5528 return; 5529 }; 5530 5531#ifdef NCR_FREEZE 5532 /* 5533 ** Freeze system to be able to read the messages. 5534 */ 5535 printf ("ncr: fatal error: system halted - press reset to reboot ..."); 5536 (void) splhigh(); 5537 for (;;); 5538#endif 5539 5540 /* 5541 ** sorry, have to kill ALL jobs ... 5542 */ 5543 5544 ncr_init (np, "fatal error", HS_FAIL); 5545} 5546 5547/*========================================================== 5548** 5549** ncr chip exception handler for selection timeout 5550** 5551**========================================================== 5552** 5553** There seems to be a bug in the 53c810. 5554** Although a STO-Interrupt is pending, 5555** it continues executing script commands. 5556** But it will fail and interrupt (IID) on 5557** the next instruction where it's looking 5558** for a valid phase. 5559** 5560**---------------------------------------------------------- 5561*/ 5562 5563static void ncr_int_sto (ncb_p np) 5564{ 5565 u_long dsa, scratcha, diff; 5566 nccb_p cp; 5567 if (DEBUG_FLAGS & DEBUG_TINY) printf ("T"); 5568 5569 /* 5570 ** look for nccb and set the status. 5571 */ 5572 5573 dsa = INL (nc_dsa); 5574 cp = np->link_nccb; 5575 while (cp && (CCB_PHYS (cp, phys) != dsa)) 5576 cp = cp->link_nccb; 5577 5578 if (cp) { 5579 cp-> host_status = HS_SEL_TIMEOUT; 5580 ncr_complete (np, cp); 5581 }; 5582 5583 /* 5584 ** repair start queue 5585 */ 5586 5587 scratcha = INL (nc_scratcha); 5588 diff = scratcha - NCB_SCRIPTH_PHYS (np, tryloop); 5589 5590/* assert ((diff <= MAX_START * 20) && !(diff % 20));*/ 5591 5592 if ((diff <= MAX_START * 20) && !(diff % 20)) { 5593 WRITESCRIPT(startpos[0], scratcha); 5594 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, start)); 5595 return; 5596 }; 5597 ncr_init (np, "selection timeout", HS_FAIL); 5598} 5599 5600/*========================================================== 5601** 5602** 5603** ncr chip exception handler for phase errors. 5604** 5605** 5606**========================================================== 5607** 5608** We have to construct a new transfer descriptor, 5609** to transfer the rest of the current block. 5610** 5611**---------------------------------------------------------- 5612*/ 5613 5614static void ncr_int_ma (ncb_p np, u_char dstat) 5615{ 5616 u_int32_t dbc; 5617 u_int32_t rest; 5618 u_int32_t dsa; 5619 u_int32_t dsp; 5620 u_int32_t nxtdsp; 5621 volatile void *vdsp_base; 5622 size_t vdsp_off; 5623 u_int32_t oadr, olen; 5624 u_int32_t *tblp, *newcmd; 5625 u_char cmd, sbcl, ss0, ss2, ctest5; 5626 u_short delta; 5627 nccb_p cp; 5628 5629 dsp = INL (nc_dsp); 5630 dsa = INL (nc_dsa); 5631 dbc = INL (nc_dbc); 5632 ss0 = INB (nc_sstat0); 5633 ss2 = INB (nc_sstat2); 5634 sbcl= INB (nc_sbcl); 5635 5636 cmd = dbc >> 24; 5637 rest= dbc & 0xffffff; 5638 5639 ctest5 = (np->rv_ctest5 & DFS) ? INB (nc_ctest5) : 0; 5640 if (ctest5 & DFS) 5641 delta=(((ctest5<<8) | (INB (nc_dfifo) & 0xff)) - rest) & 0x3ff; 5642 else 5643 delta=(INB (nc_dfifo) - rest) & 0x7f; 5644 5645 5646 /* 5647 ** The data in the dma fifo has not been transfered to 5648 ** the target -> add the amount to the rest 5649 ** and clear the data. 5650 ** Check the sstat2 register in case of wide transfer. 5651 */ 5652 5653 if (!(dstat & DFE)) rest += delta; 5654 if (ss0 & OLF) rest++; 5655 if (ss0 & ORF) rest++; 5656 if (INB(nc_scntl3) & EWS) { 5657 if (ss2 & OLF1) rest++; 5658 if (ss2 & ORF1) rest++; 5659 }; 5660 OUTB (nc_ctest3, np->rv_ctest3 | CLF); /* clear dma fifo */ 5661 OUTB (nc_stest3, TE|CSF); /* clear scsi fifo */ 5662 5663 /* 5664 ** locate matching cp 5665 */ 5666 cp = np->link_nccb; 5667 while (cp && (CCB_PHYS (cp, phys) != dsa)) 5668 cp = cp->link_nccb; 5669 5670 if (!cp) { 5671 printf ("%s: SCSI phase error fixup: CCB already dequeued (%p)\n", 5672 ncr_name (np), (void *) np->header.cp); 5673 return; 5674 } 5675 if (cp != np->header.cp) { 5676 printf ("%s: SCSI phase error fixup: CCB address mismatch " 5677 "(%p != %p) np->nccb = %p\n", 5678 ncr_name (np), (void *)cp, (void *)np->header.cp, 5679 (void *)np->link_nccb); 5680/* return;*/ 5681 } 5682 5683 /* 5684 ** find the interrupted script command, 5685 ** and the address at which to continue. 5686 */ 5687 5688 if (dsp == vtophys (&cp->patch[2])) { 5689 vdsp_base = cp; 5690 vdsp_off = offsetof(struct nccb, patch[0]); 5691 nxtdsp = READSCRIPT_OFF(vdsp_base, vdsp_off + 3*4); 5692 } else if (dsp == vtophys (&cp->patch[6])) { 5693 vdsp_base = cp; 5694 vdsp_off = offsetof(struct nccb, patch[4]); 5695 nxtdsp = READSCRIPT_OFF(vdsp_base, vdsp_off + 3*4); 5696 } else if (dsp > np->p_script && 5697 dsp <= np->p_script + sizeof(struct script)) { 5698 vdsp_base = np->script; 5699 vdsp_off = dsp - np->p_script - 8; 5700 nxtdsp = dsp; 5701 } else { 5702 vdsp_base = np->scripth; 5703 vdsp_off = dsp - np->p_scripth - 8; 5704 nxtdsp = dsp; 5705 }; 5706 5707 /* 5708 ** log the information 5709 */ 5710 if (DEBUG_FLAGS & (DEBUG_TINY|DEBUG_PHASE)) { 5711 printf ("P%x%x ",cmd&7, sbcl&7); 5712 printf ("RL=%d D=%d SS0=%x ", 5713 (unsigned) rest, (unsigned) delta, ss0); 5714 }; 5715 if (DEBUG_FLAGS & DEBUG_PHASE) { 5716 printf ("\nCP=%p CP2=%p DSP=%x NXT=%x VDSP=%p CMD=%x ", 5717 cp, np->header.cp, 5718 dsp, 5719 nxtdsp, (volatile char*)vdsp_base+vdsp_off, cmd); 5720 }; 5721 5722 /* 5723 ** get old startaddress and old length. 5724 */ 5725 5726 oadr = READSCRIPT_OFF(vdsp_base, vdsp_off + 1*4); 5727 5728 if (cmd & 0x10) { /* Table indirect */ 5729 tblp = (u_int32_t *) ((char*) &cp->phys + oadr); 5730 olen = tblp[0]; 5731 oadr = tblp[1]; 5732 } else { 5733 tblp = (u_int32_t *) 0; 5734 olen = READSCRIPT_OFF(vdsp_base, vdsp_off) & 0xffffff; 5735 }; 5736 5737 if (DEBUG_FLAGS & DEBUG_PHASE) { 5738 printf ("OCMD=%x\nTBLP=%p OLEN=%lx OADR=%lx\n", 5739 (unsigned) (READSCRIPT_OFF(vdsp_base, vdsp_off) >> 24), 5740 (void *) tblp, 5741 (u_long) olen, 5742 (u_long) oadr); 5743 }; 5744 5745 /* 5746 ** if old phase not dataphase, leave here. 5747 */ 5748 5749 if (cmd != (READSCRIPT_OFF(vdsp_base, vdsp_off) >> 24)) { 5750 PRINT_ADDR(cp->ccb); 5751 printf ("internal error: cmd=%02x != %02x=(vdsp[0] >> 24)\n", 5752 (unsigned)cmd, 5753 (unsigned)READSCRIPT_OFF(vdsp_base, vdsp_off) >> 24); 5754 5755 return; 5756 } 5757 if (cmd & 0x06) { 5758 PRINT_ADDR(cp->ccb); 5759 printf ("phase change %x-%x %d@%08x resid=%d.\n", 5760 cmd&7, sbcl&7, (unsigned)olen, 5761 (unsigned)oadr, (unsigned)rest); 5762 5763 OUTB (nc_dcntl, np->rv_dcntl | STD); 5764 return; 5765 }; 5766 5767 /* 5768 ** choose the correct patch area. 5769 ** if savep points to one, choose the other. 5770 */ 5771 5772 newcmd = cp->patch; 5773 if (cp->phys.header.savep == vtophys (newcmd)) newcmd+=4; 5774 5775 /* 5776 ** fillin the commands 5777 */ 5778 5779 newcmd[0] = ((cmd & 0x0f) << 24) | rest; 5780 newcmd[1] = oadr + olen - rest; 5781 newcmd[2] = SCR_JUMP; 5782 newcmd[3] = nxtdsp; 5783 5784 if (DEBUG_FLAGS & DEBUG_PHASE) { 5785 PRINT_ADDR(cp->ccb); 5786 printf ("newcmd[%d] %x %x %x %x.\n", 5787 (int)(newcmd - cp->patch), 5788 (unsigned)newcmd[0], 5789 (unsigned)newcmd[1], 5790 (unsigned)newcmd[2], 5791 (unsigned)newcmd[3]); 5792 } 5793 /* 5794 ** fake the return address (to the patch). 5795 ** and restart script processor at dispatcher. 5796 */ 5797 np->profile.num_break++; 5798 OUTL (nc_temp, vtophys (newcmd)); 5799 if ((cmd & 7) == 0) 5800 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, dispatch)); 5801 else 5802 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, checkatn)); 5803} 5804 5805/*========================================================== 5806** 5807** 5808** ncr chip exception handler for programmed interrupts. 5809** 5810** 5811**========================================================== 5812*/ 5813 5814static int ncr_show_msg (u_char * msg) 5815{ 5816 u_char i; 5817 printf ("%x",*msg); 5818 if (*msg==MSG_EXTENDED) { 5819 for (i=1;i<8;i++) { 5820 if (i-1>msg[1]) break; 5821 printf ("-%x",msg[i]); 5822 }; 5823 return (i+1); 5824 } else if ((*msg & 0xf0) == 0x20) { 5825 printf ("-%x",msg[1]); 5826 return (2); 5827 }; 5828 return (1); 5829} 5830 5831static void ncr_int_sir (ncb_p np) 5832{ 5833 u_char scntl3; 5834 u_char chg, ofs, per, fak, wide; 5835 u_char num = INB (nc_dsps); 5836 nccb_p cp=0; 5837 u_long dsa; 5838 u_int target = INB (nc_sdid) & 0x0f; 5839 tcb_p tp = &np->target[target]; 5840 int i; 5841 if (DEBUG_FLAGS & DEBUG_TINY) printf ("I#%d", num); 5842 5843 switch (num) { 5844 case SIR_SENSE_RESTART: 5845 case SIR_STALL_RESTART: 5846 break; 5847 5848 default: 5849 /* 5850 ** lookup the nccb 5851 */ 5852 dsa = INL (nc_dsa); 5853 cp = np->link_nccb; 5854 while (cp && (CCB_PHYS (cp, phys) != dsa)) 5855 cp = cp->link_nccb; 5856 5857 assert (cp); 5858 if (!cp) 5859 goto out; 5860 assert (cp == np->header.cp); 5861 if (cp != np->header.cp) 5862 goto out; 5863 } 5864 5865 switch (num) { 5866 5867/*-------------------------------------------------------------------- 5868** 5869** Processing of interrupted getcc selects 5870** 5871**-------------------------------------------------------------------- 5872*/ 5873 5874 case SIR_SENSE_RESTART: 5875 /*------------------------------------------ 5876 ** Script processor is idle. 5877 ** Look for interrupted "check cond" 5878 **------------------------------------------ 5879 */ 5880 5881 if (DEBUG_FLAGS & DEBUG_RESTART) 5882 printf ("%s: int#%d",ncr_name (np),num); 5883 cp = (nccb_p) 0; 5884 for (i=0; i<MAX_TARGET; i++) { 5885 if (DEBUG_FLAGS & DEBUG_RESTART) printf (" t%d", i); 5886 tp = &np->target[i]; 5887 if (DEBUG_FLAGS & DEBUG_RESTART) printf ("+"); 5888 cp = tp->hold_cp; 5889 if (!cp) continue; 5890 if (DEBUG_FLAGS & DEBUG_RESTART) printf ("+"); 5891 if ((cp->host_status==HS_BUSY) && 5892 (cp->s_status==SCSI_STATUS_CHECK_COND)) 5893 break; 5894 if (DEBUG_FLAGS & DEBUG_RESTART) printf ("- (remove)"); 5895 tp->hold_cp = cp = (nccb_p) 0; 5896 }; 5897 5898 if (cp) { 5899 if (DEBUG_FLAGS & DEBUG_RESTART) 5900 printf ("+ restart job ..\n"); 5901 OUTL (nc_dsa, CCB_PHYS (cp, phys)); 5902 OUTL (nc_dsp, NCB_SCRIPTH_PHYS (np, getcc)); 5903 return; 5904 }; 5905 5906 /* 5907 ** no job, resume normal processing 5908 */ 5909 if (DEBUG_FLAGS & DEBUG_RESTART) printf (" -- remove trap\n"); 5910 WRITESCRIPT(start0[0], SCR_INT ^ IFFALSE (0)); 5911 break; 5912 5913 case SIR_SENSE_FAILED: 5914 /*------------------------------------------- 5915 ** While trying to select for 5916 ** getting the condition code, 5917 ** a target reselected us. 5918 **------------------------------------------- 5919 */ 5920 if (DEBUG_FLAGS & DEBUG_RESTART) { 5921 PRINT_ADDR(cp->ccb); 5922 printf ("in getcc reselect by t%d.\n", 5923 INB(nc_ssid) & 0x0f); 5924 } 5925 5926 /* 5927 ** Mark this job 5928 */ 5929 cp->host_status = HS_BUSY; 5930 cp->s_status = SCSI_STATUS_CHECK_COND; 5931 np->target[cp->ccb->ccb_h.target_id].hold_cp = cp; 5932 5933 /* 5934 ** And patch code to restart it. 5935 */ 5936 WRITESCRIPT(start0[0], SCR_INT); 5937 break; 5938 5939/*----------------------------------------------------------------------------- 5940** 5941** Was Sie schon immer ueber transfermode negotiation wissen wollten ... 5942** 5943** We try to negotiate sync and wide transfer only after 5944** a successfull inquire command. We look at byte 7 of the 5945** inquire data to determine the capabilities if the target. 5946** 5947** When we try to negotiate, we append the negotiation message 5948** to the identify and (maybe) simple tag message. 5949** The host status field is set to HS_NEGOTIATE to mark this 5950** situation. 5951** 5952** If the target doesn't answer this message immidiately 5953** (as required by the standard), the SIR_NEGO_FAIL interrupt 5954** will be raised eventually. 5955** The handler removes the HS_NEGOTIATE status, and sets the 5956** negotiated value to the default (async / nowide). 5957** 5958** If we receive a matching answer immediately, we check it 5959** for validity, and set the values. 5960** 5961** If we receive a Reject message immediately, we assume the 5962** negotiation has failed, and fall back to standard values. 5963** 5964** If we receive a negotiation message while not in HS_NEGOTIATE 5965** state, it's a target initiated negotiation. We prepare a 5966** (hopefully) valid answer, set our parameters, and send back 5967** this answer to the target. 5968** 5969** If the target doesn't fetch the answer (no message out phase), 5970** we assume the negotiation has failed, and fall back to default 5971** settings. 5972** 5973** When we set the values, we adjust them in all nccbs belonging 5974** to this target, in the controller's register, and in the "phys" 5975** field of the controller's struct ncb. 5976** 5977** Possible cases: hs sir msg_in value send goto 5978** We try try to negotiate: 5979** -> target doesnt't msgin NEG FAIL noop defa. - dispatch 5980** -> target rejected our msg NEG FAIL reject defa. - dispatch 5981** -> target answered (ok) NEG SYNC sdtr set - clrack 5982** -> target answered (!ok) NEG SYNC sdtr defa. REJ--->msg_bad 5983** -> target answered (ok) NEG WIDE wdtr set - clrack 5984** -> target answered (!ok) NEG WIDE wdtr defa. REJ--->msg_bad 5985** -> any other msgin NEG FAIL noop defa. - dispatch 5986** 5987** Target tries to negotiate: 5988** -> incoming message --- SYNC sdtr set SDTR - 5989** -> incoming message --- WIDE wdtr set WDTR - 5990** We sent our answer: 5991** -> target doesn't msgout --- PROTO ? defa. - dispatch 5992** 5993**----------------------------------------------------------------------------- 5994*/ 5995 5996 case SIR_NEGO_FAILED: 5997 /*------------------------------------------------------- 5998 ** 5999 ** Negotiation failed. 6000 ** Target doesn't send an answer message, 6001 ** or target rejected our message. 6002 ** 6003 ** Remove negotiation request. 6004 ** 6005 **------------------------------------------------------- 6006 */ 6007 OUTB (HS_PRT, HS_BUSY); 6008 6009 /* FALLTHROUGH */ 6010 6011 case SIR_NEGO_PROTO: 6012 /*------------------------------------------------------- 6013 ** 6014 ** Negotiation failed. 6015 ** Target doesn't fetch the answer message. 6016 ** 6017 **------------------------------------------------------- 6018 */ 6019 6020 if (DEBUG_FLAGS & DEBUG_NEGO) { 6021 PRINT_ADDR(cp->ccb); 6022 printf ("negotiation failed sir=%x status=%x.\n", 6023 num, cp->nego_status); 6024 }; 6025 6026 /* 6027 ** any error in negotiation: 6028 ** fall back to default mode. 6029 */ 6030 switch (cp->nego_status) { 6031 6032 case NS_SYNC: 6033 ncr_setsync (np, cp, 0, 0xe0, 0); 6034 break; 6035 6036 case NS_WIDE: 6037 ncr_setwide (np, cp, 0, 0); 6038 break; 6039 6040 }; 6041 np->msgin [0] = MSG_NOOP; 6042 np->msgout[0] = MSG_NOOP; 6043 cp->nego_status = 0; 6044 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, dispatch)); 6045 break; 6046 6047 case SIR_NEGO_SYNC: 6048 /* 6049 ** Synchronous request message received. 6050 */ 6051 6052 if (DEBUG_FLAGS & DEBUG_NEGO) { 6053 PRINT_ADDR(cp->ccb); 6054 printf ("sync msgin: "); 6055 (void) ncr_show_msg (np->msgin); 6056 printf (".\n"); 6057 }; 6058 6059 /* 6060 ** get requested values. 6061 */ 6062 6063 chg = 0; 6064 per = np->msgin[3]; 6065 ofs = np->msgin[4]; 6066 if (ofs==0) per=255; 6067 6068 /* 6069 ** check values against driver limits. 6070 */ 6071 if (per < np->minsync) 6072 {chg = 1; per = np->minsync;} 6073 if (per < tp->tinfo.user.period) 6074 {chg = 1; per = tp->tinfo.user.period;} 6075 if (ofs > tp->tinfo.user.offset) 6076 {chg = 1; ofs = tp->tinfo.user.offset;} 6077 6078 /* 6079 ** Check against controller limits. 6080 */ 6081 6082 fak = 7; 6083 scntl3 = 0; 6084 if (ofs != 0) { 6085 ncr_getsync(np, per, &fak, &scntl3); 6086 if (fak > 7) { 6087 chg = 1; 6088 ofs = 0; 6089 } 6090 } 6091 if (ofs == 0) { 6092 fak = 7; 6093 per = 0; 6094 scntl3 = 0; 6095 } 6096 6097 if (DEBUG_FLAGS & DEBUG_NEGO) { 6098 PRINT_ADDR(cp->ccb); 6099 printf ("sync: per=%d scntl3=0x%x ofs=%d fak=%d chg=%d.\n", 6100 per, scntl3, ofs, fak, chg); 6101 } 6102 6103 if (INB (HS_PRT) == HS_NEGOTIATE) { 6104 OUTB (HS_PRT, HS_BUSY); 6105 switch (cp->nego_status) { 6106 6107 case NS_SYNC: 6108 /* 6109 ** This was an answer message 6110 */ 6111 if (chg) { 6112 /* 6113 ** Answer wasn't acceptable. 6114 */ 6115 ncr_setsync (np, cp, 0, 0xe0, 0); 6116 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, msg_bad)); 6117 } else { 6118 /* 6119 ** Answer is ok. 6120 */ 6121 ncr_setsync (np,cp,scntl3,(fak<<5)|ofs, per); 6122 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, clrack)); 6123 }; 6124 return; 6125 6126 case NS_WIDE: 6127 ncr_setwide (np, cp, 0, 0); 6128 break; 6129 }; 6130 }; 6131 6132 /* 6133 ** It was a request. Set value and 6134 ** prepare an answer message 6135 */ 6136 6137 ncr_setsync (np, cp, scntl3, (fak<<5)|ofs, per); 6138 6139 np->msgout[0] = MSG_EXTENDED; 6140 np->msgout[1] = 3; 6141 np->msgout[2] = MSG_EXT_SDTR; 6142 np->msgout[3] = per; 6143 np->msgout[4] = ofs; 6144 6145 cp->nego_status = NS_SYNC; 6146 6147 if (DEBUG_FLAGS & DEBUG_NEGO) { 6148 PRINT_ADDR(cp->ccb); 6149 printf ("sync msgout: "); 6150 (void) ncr_show_msg (np->msgout); 6151 printf (".\n"); 6152 } 6153 6154 if (!ofs) { 6155 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, msg_bad)); 6156 return; 6157 } 6158 np->msgin [0] = MSG_NOOP; 6159 6160 break; 6161 6162 case SIR_NEGO_WIDE: 6163 /* 6164 ** Wide request message received. 6165 */ 6166 if (DEBUG_FLAGS & DEBUG_NEGO) { 6167 PRINT_ADDR(cp->ccb); 6168 printf ("wide msgin: "); 6169 (void) ncr_show_msg (np->msgin); 6170 printf (".\n"); 6171 }; 6172 6173 /* 6174 ** get requested values. 6175 */ 6176 6177 chg = 0; 6178 wide = np->msgin[3]; 6179 6180 /* 6181 ** check values against driver limits. 6182 */ 6183 6184 if (wide > tp->tinfo.user.width) 6185 {chg = 1; wide = tp->tinfo.user.width;} 6186 6187 if (DEBUG_FLAGS & DEBUG_NEGO) { 6188 PRINT_ADDR(cp->ccb); 6189 printf ("wide: wide=%d chg=%d.\n", wide, chg); 6190 } 6191 6192 if (INB (HS_PRT) == HS_NEGOTIATE) { 6193 OUTB (HS_PRT, HS_BUSY); 6194 switch (cp->nego_status) { 6195 6196 case NS_WIDE: 6197 /* 6198 ** This was an answer message 6199 */ 6200 if (chg) { 6201 /* 6202 ** Answer wasn't acceptable. 6203 */ 6204 ncr_setwide (np, cp, 0, 1); 6205 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, msg_bad)); 6206 } else { 6207 /* 6208 ** Answer is ok. 6209 */ 6210 ncr_setwide (np, cp, wide, 1); 6211 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, clrack)); 6212 }; 6213 return; 6214 6215 case NS_SYNC: 6216 ncr_setsync (np, cp, 0, 0xe0, 0); 6217 break; 6218 }; 6219 }; 6220 6221 /* 6222 ** It was a request, set value and 6223 ** prepare an answer message 6224 */ 6225 6226 ncr_setwide (np, cp, wide, 1); 6227 6228 np->msgout[0] = MSG_EXTENDED; 6229 np->msgout[1] = 2; 6230 np->msgout[2] = MSG_EXT_WDTR; 6231 np->msgout[3] = wide; 6232 6233 np->msgin [0] = MSG_NOOP; 6234 6235 cp->nego_status = NS_WIDE; 6236 6237 if (DEBUG_FLAGS & DEBUG_NEGO) { 6238 PRINT_ADDR(cp->ccb); 6239 printf ("wide msgout: "); 6240 (void) ncr_show_msg (np->msgout); 6241 printf (".\n"); 6242 } 6243 break; 6244 6245/*-------------------------------------------------------------------- 6246** 6247** Processing of special messages 6248** 6249**-------------------------------------------------------------------- 6250*/ 6251 6252 case SIR_REJECT_RECEIVED: 6253 /*----------------------------------------------- 6254 ** 6255 ** We received a MSG_MESSAGE_REJECT message. 6256 ** 6257 **----------------------------------------------- 6258 */ 6259 6260 PRINT_ADDR(cp->ccb); 6261 printf ("MSG_MESSAGE_REJECT received (%x:%x).\n", 6262 (unsigned)np->lastmsg, np->msgout[0]); 6263 break; 6264 6265 case SIR_REJECT_SENT: 6266 /*----------------------------------------------- 6267 ** 6268 ** We received an unknown message 6269 ** 6270 **----------------------------------------------- 6271 */ 6272 6273 PRINT_ADDR(cp->ccb); 6274 printf ("MSG_MESSAGE_REJECT sent for "); 6275 (void) ncr_show_msg (np->msgin); 6276 printf (".\n"); 6277 break; 6278 6279/*-------------------------------------------------------------------- 6280** 6281** Processing of special messages 6282** 6283**-------------------------------------------------------------------- 6284*/ 6285 6286 case SIR_IGN_RESIDUE: 6287 /*----------------------------------------------- 6288 ** 6289 ** We received an IGNORE RESIDUE message, 6290 ** which couldn't be handled by the script. 6291 ** 6292 **----------------------------------------------- 6293 */ 6294 6295 PRINT_ADDR(cp->ccb); 6296 printf ("MSG_IGN_WIDE_RESIDUE received, but not yet implemented.\n"); 6297 break; 6298 6299 case SIR_MISSING_SAVE: 6300 /*----------------------------------------------- 6301 ** 6302 ** We received an DISCONNECT message, 6303 ** but the datapointer wasn't saved before. 6304 ** 6305 **----------------------------------------------- 6306 */ 6307 6308 PRINT_ADDR(cp->ccb); 6309 printf ("MSG_DISCONNECT received, but datapointer not saved:\n" 6310 "\tdata=%x save=%x goal=%x.\n", 6311 (unsigned) INL (nc_temp), 6312 (unsigned) np->header.savep, 6313 (unsigned) np->header.goalp); 6314 break; 6315 6316/*-------------------------------------------------------------------- 6317** 6318** Processing of a "SCSI_STATUS_QUEUE_FULL" status. 6319** 6320** XXX JGibbs - We should do the same thing for BUSY status. 6321** 6322** The current command has been rejected, 6323** because there are too many in the command queue. 6324** We have started too many commands for that target. 6325** 6326**-------------------------------------------------------------------- 6327*/ 6328 case SIR_STALL_QUEUE: 6329 cp->xerr_status = XE_OK; 6330 cp->host_status = HS_COMPLETE; 6331 cp->s_status = SCSI_STATUS_QUEUE_FULL; 6332 ncr_freeze_devq(np, cp->ccb->ccb_h.path); 6333 ncr_complete(np, cp); 6334 6335 /* FALLTHROUGH */ 6336 6337 case SIR_STALL_RESTART: 6338 /*----------------------------------------------- 6339 ** 6340 ** Enable selecting again, 6341 ** if NO disconnected jobs. 6342 ** 6343 **----------------------------------------------- 6344 */ 6345 /* 6346 ** Look for a disconnected job. 6347 */ 6348 cp = np->link_nccb; 6349 while (cp && cp->host_status != HS_DISCONNECT) 6350 cp = cp->link_nccb; 6351 6352 /* 6353 ** if there is one, ... 6354 */ 6355 if (cp) { 6356 /* 6357 ** wait for reselection 6358 */ 6359 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, reselect)); 6360 return; 6361 }; 6362 6363 /* 6364 ** else remove the interrupt. 6365 */ 6366 6367 printf ("%s: queue empty.\n", ncr_name (np)); 6368 WRITESCRIPT(start1[0], SCR_INT ^ IFFALSE (0)); 6369 break; 6370 }; 6371 6372out: 6373 OUTB (nc_dcntl, np->rv_dcntl | STD); 6374} 6375 6376/*========================================================== 6377** 6378** 6379** Aquire a control block 6380** 6381** 6382**========================================================== 6383*/ 6384 6385static nccb_p ncr_get_nccb 6386 (ncb_p np, u_long target, u_long lun) 6387{ 6388 lcb_p lp; 6389 int s; 6390 nccb_p cp = NULL; 6391 6392 /* Keep our timeout handler out */ 6393 s = splsoftclock(); 6394 6395 /* 6396 ** Lun structure available ? 6397 */ 6398 6399 lp = np->target[target].lp[lun]; 6400 if (lp) { 6401 cp = lp->next_nccb; 6402 6403 /* 6404 ** Look for free CCB 6405 */ 6406 6407 while (cp && cp->magic) { 6408 cp = cp->next_nccb; 6409 } 6410 } 6411 6412 /* 6413 ** if nothing available, create one. 6414 */ 6415 6416 if (cp == NULL) 6417 cp = ncr_alloc_nccb(np, target, lun); 6418 6419 if (cp != NULL) { 6420 if (cp->magic) { 6421 printf("%s: Bogus free cp found\n", ncr_name(np)); 6422 splx(s); 6423 return (NULL); 6424 } 6425 cp->magic = 1; 6426 } 6427 splx(s); 6428 return (cp); 6429} 6430 6431/*========================================================== 6432** 6433** 6434** Release one control block 6435** 6436** 6437**========================================================== 6438*/ 6439 6440static void ncr_free_nccb (ncb_p np, nccb_p cp) 6441{ 6442 /* 6443 ** sanity 6444 */ 6445 6446 assert (cp != NULL); 6447 6448 cp -> host_status = HS_IDLE; 6449 cp -> magic = 0; 6450} 6451 6452/*========================================================== 6453** 6454** 6455** Allocation of resources for Targets/Luns/Tags. 6456** 6457** 6458**========================================================== 6459*/ 6460 6461static nccb_p 6462ncr_alloc_nccb (ncb_p np, u_long target, u_long lun) 6463{ 6464 tcb_p tp; 6465 lcb_p lp; 6466 nccb_p cp; 6467 6468 assert (np != NULL); 6469 6470 if (target>=MAX_TARGET) return(NULL); 6471 if (lun >=MAX_LUN ) return(NULL); 6472 6473 tp=&np->target[target]; 6474 6475 if (!tp->jump_tcb.l_cmd) { 6476 6477 /* 6478 ** initialize it. 6479 */ 6480 tp->jump_tcb.l_cmd = (SCR_JUMP^IFFALSE (DATA (0x80 + target))); 6481 tp->jump_tcb.l_paddr = np->jump_tcb.l_paddr; 6482 6483 tp->getscr[0] = 6484 (np->features & FE_PFEN)? SCR_COPY(1) : SCR_COPY_F(1); 6485 tp->getscr[1] = vtophys (&tp->tinfo.sval); 6486 tp->getscr[2] = rman_get_start(np->reg_res) + offsetof (struct ncr_reg, nc_sxfer); 6487 tp->getscr[3] = 6488 (np->features & FE_PFEN)? SCR_COPY(1) : SCR_COPY_F(1); 6489 tp->getscr[4] = vtophys (&tp->tinfo.wval); 6490 tp->getscr[5] = rman_get_start(np->reg_res) + offsetof (struct ncr_reg, nc_scntl3); 6491 6492 assert (((offsetof(struct ncr_reg, nc_sxfer) ^ 6493 (offsetof(struct tcb ,tinfo) 6494 + offsetof(struct ncr_target_tinfo, sval))) & 3) == 0); 6495 assert (((offsetof(struct ncr_reg, nc_scntl3) ^ 6496 (offsetof(struct tcb, tinfo) 6497 + offsetof(struct ncr_target_tinfo, wval))) &3) == 0); 6498 6499 tp->call_lun.l_cmd = (SCR_CALL); 6500 tp->call_lun.l_paddr = NCB_SCRIPT_PHYS (np, resel_lun); 6501 6502 tp->jump_lcb.l_cmd = (SCR_JUMP); 6503 tp->jump_lcb.l_paddr = NCB_SCRIPTH_PHYS (np, abort); 6504 np->jump_tcb.l_paddr = vtophys (&tp->jump_tcb); 6505 } 6506 6507 /* 6508 ** Logic unit control block 6509 */ 6510 lp = tp->lp[lun]; 6511 if (!lp) { 6512 /* 6513 ** Allocate a lcb 6514 */ 6515 lp = (lcb_p) malloc (sizeof (struct lcb), M_DEVBUF, 6516 M_NOWAIT | M_ZERO); 6517 if (!lp) return(NULL); 6518 6519 /* 6520 ** Initialize it 6521 */ 6522 lp->jump_lcb.l_cmd = (SCR_JUMP ^ IFFALSE (DATA (lun))); 6523 lp->jump_lcb.l_paddr = tp->jump_lcb.l_paddr; 6524 6525 lp->call_tag.l_cmd = (SCR_CALL); 6526 lp->call_tag.l_paddr = NCB_SCRIPT_PHYS (np, resel_tag); 6527 6528 lp->jump_nccb.l_cmd = (SCR_JUMP); 6529 lp->jump_nccb.l_paddr = NCB_SCRIPTH_PHYS (np, aborttag); 6530 6531 lp->actlink = 1; 6532 6533 /* 6534 ** Chain into LUN list 6535 */ 6536 tp->jump_lcb.l_paddr = vtophys (&lp->jump_lcb); 6537 tp->lp[lun] = lp; 6538 6539 } 6540 6541 /* 6542 ** Allocate a nccb 6543 */ 6544 cp = (nccb_p) malloc (sizeof (struct nccb), M_DEVBUF, M_NOWAIT|M_ZERO); 6545 6546 if (!cp) 6547 return (NULL); 6548 6549 if (DEBUG_FLAGS & DEBUG_ALLOC) { 6550 printf ("new nccb @%p.\n", cp); 6551 } 6552 6553 /* 6554 ** Fill in physical addresses 6555 */ 6556 6557 cp->p_nccb = vtophys (cp); 6558 6559 /* 6560 ** Chain into reselect list 6561 */ 6562 cp->jump_nccb.l_cmd = SCR_JUMP; 6563 cp->jump_nccb.l_paddr = lp->jump_nccb.l_paddr; 6564 lp->jump_nccb.l_paddr = CCB_PHYS (cp, jump_nccb); 6565 cp->call_tmp.l_cmd = SCR_CALL; 6566 cp->call_tmp.l_paddr = NCB_SCRIPT_PHYS (np, resel_tmp); 6567 6568 /* 6569 ** Chain into wakeup list 6570 */ 6571 cp->link_nccb = np->link_nccb; 6572 np->link_nccb = cp; 6573 6574 /* 6575 ** Chain into CCB list 6576 */ 6577 cp->next_nccb = lp->next_nccb; 6578 lp->next_nccb = cp; 6579 6580 return (cp); 6581} 6582 6583/*========================================================== 6584** 6585** 6586** Build Scatter Gather Block 6587** 6588** 6589**========================================================== 6590** 6591** The transfer area may be scattered among 6592** several non adjacent physical pages. 6593** 6594** We may use MAX_SCATTER blocks. 6595** 6596**---------------------------------------------------------- 6597*/ 6598 6599static int ncr_scatter 6600 (struct dsb* phys, vm_offset_t vaddr, vm_size_t datalen) 6601{ 6602 u_long paddr, pnext; 6603 6604 u_short segment = 0; 6605 u_long segsize, segaddr; 6606 u_long size, csize = 0; 6607 u_long chunk = MAX_SIZE; 6608 int free; 6609 6610 bzero (&phys->data, sizeof (phys->data)); 6611 if (!datalen) return (0); 6612 6613 paddr = vtophys (vaddr); 6614 6615 /* 6616 ** insert extra break points at a distance of chunk. 6617 ** We try to reduce the number of interrupts caused 6618 ** by unexpected phase changes due to disconnects. 6619 ** A typical harddisk may disconnect before ANY block. 6620 ** If we wanted to avoid unexpected phase changes at all 6621 ** we had to use a break point every 512 bytes. 6622 ** Of course the number of scatter/gather blocks is 6623 ** limited. 6624 */ 6625 6626 free = MAX_SCATTER - 1; 6627 6628 if (vaddr & PAGE_MASK) free -= datalen / PAGE_SIZE; 6629 6630 if (free>1) 6631 while ((chunk * free >= 2 * datalen) && (chunk>=1024)) 6632 chunk /= 2; 6633 6634 if(DEBUG_FLAGS & DEBUG_SCATTER) 6635 printf("ncr?:\tscattering virtual=%p size=%d chunk=%d.\n", 6636 (void *) vaddr, (unsigned) datalen, (unsigned) chunk); 6637 6638 /* 6639 ** Build data descriptors. 6640 */ 6641 while (datalen && (segment < MAX_SCATTER)) { 6642 6643 /* 6644 ** this segment is empty 6645 */ 6646 segsize = 0; 6647 segaddr = paddr; 6648 pnext = paddr; 6649 6650 if (!csize) csize = chunk; 6651 6652 while ((datalen) && (paddr == pnext) && (csize)) { 6653 6654 /* 6655 ** continue this segment 6656 */ 6657 pnext = (paddr & (~PAGE_MASK)) + PAGE_SIZE; 6658 6659 /* 6660 ** Compute max size 6661 */ 6662 6663 size = pnext - paddr; /* page size */ 6664 if (size > datalen) size = datalen; /* data size */ 6665 if (size > csize ) size = csize ; /* chunksize */ 6666 6667 segsize += size; 6668 vaddr += size; 6669 csize -= size; 6670 datalen -= size; 6671 paddr = vtophys (vaddr); 6672 }; 6673 6674 if(DEBUG_FLAGS & DEBUG_SCATTER) 6675 printf ("\tseg #%d addr=%x size=%d (rest=%d).\n", 6676 segment, 6677 (unsigned) segaddr, 6678 (unsigned) segsize, 6679 (unsigned) datalen); 6680 6681 phys->data[segment].addr = segaddr; 6682 phys->data[segment].size = segsize; 6683 segment++; 6684 } 6685 6686 if (datalen) { 6687 printf("ncr?: scatter/gather failed (residue=%d).\n", 6688 (unsigned) datalen); 6689 return (-1); 6690 }; 6691 6692 return (segment); 6693} 6694 6695/*========================================================== 6696** 6697** 6698** Test the pci bus snoop logic :-( 6699** 6700** Has to be called with interrupts disabled. 6701** 6702** 6703**========================================================== 6704*/ 6705 6706#ifndef NCR_IOMAPPED 6707static int ncr_regtest (struct ncb* np) 6708{ 6709 register volatile u_int32_t data; 6710 /* 6711 ** ncr registers may NOT be cached. 6712 ** write 0xffffffff to a read only register area, 6713 ** and try to read it back. 6714 */ 6715 data = 0xffffffff; 6716 OUTL_OFF(offsetof(struct ncr_reg, nc_dstat), data); 6717 data = INL_OFF(offsetof(struct ncr_reg, nc_dstat)); 6718#if 1 6719 if (data == 0xffffffff) { 6720#else 6721 if ((data & 0xe2f0fffd) != 0x02000080) { 6722#endif 6723 printf ("CACHE TEST FAILED: reg dstat-sstat2 readback %x.\n", 6724 (unsigned) data); 6725 return (0x10); 6726 }; 6727 return (0); 6728} 6729#endif 6730 6731static int ncr_snooptest (struct ncb* np) 6732{ 6733 u_int32_t ncr_rd, ncr_wr, ncr_bk, host_rd, host_wr, pc; 6734 int i, err=0; 6735#ifndef NCR_IOMAPPED 6736 err |= ncr_regtest (np); 6737 if (err) return (err); 6738#endif 6739 /* 6740 ** init 6741 */ 6742 pc = NCB_SCRIPTH_PHYS (np, snooptest); 6743 host_wr = 1; 6744 ncr_wr = 2; 6745 /* 6746 ** Set memory and register. 6747 */ 6748 ncr_cache = host_wr; 6749 OUTL (nc_temp, ncr_wr); 6750 /* 6751 ** Start script (exchange values) 6752 */ 6753 OUTL (nc_dsp, pc); 6754 /* 6755 ** Wait 'til done (with timeout) 6756 */ 6757 for (i=0; i<NCR_SNOOP_TIMEOUT; i++) 6758 if (INB(nc_istat) & (INTF|SIP|DIP)) 6759 break; 6760 /* 6761 ** Save termination position. 6762 */ 6763 pc = INL (nc_dsp); 6764 /* 6765 ** Read memory and register. 6766 */ 6767 host_rd = ncr_cache; 6768 ncr_rd = INL (nc_scratcha); 6769 ncr_bk = INL (nc_temp); 6770 /* 6771 ** Reset ncr chip 6772 */ 6773 OUTB (nc_istat, SRST); 6774 DELAY (1000); 6775 OUTB (nc_istat, 0 ); 6776 /* 6777 ** check for timeout 6778 */ 6779 if (i>=NCR_SNOOP_TIMEOUT) { 6780 printf ("CACHE TEST FAILED: timeout.\n"); 6781 return (0x20); 6782 }; 6783 /* 6784 ** Check termination position. 6785 */ 6786 if (pc != NCB_SCRIPTH_PHYS (np, snoopend)+8) { 6787 printf ("CACHE TEST FAILED: script execution failed.\n"); 6788 printf ("start=%08lx, pc=%08lx, end=%08lx\n", 6789 (u_long) NCB_SCRIPTH_PHYS (np, snooptest), (u_long) pc, 6790 (u_long) NCB_SCRIPTH_PHYS (np, snoopend) +8); 6791 return (0x40); 6792 }; 6793 /* 6794 ** Show results. 6795 */ 6796 if (host_wr != ncr_rd) { 6797 printf ("CACHE TEST FAILED: host wrote %d, ncr read %d.\n", 6798 (int) host_wr, (int) ncr_rd); 6799 err |= 1; 6800 }; 6801 if (host_rd != ncr_wr) { 6802 printf ("CACHE TEST FAILED: ncr wrote %d, host read %d.\n", 6803 (int) ncr_wr, (int) host_rd); 6804 err |= 2; 6805 }; 6806 if (ncr_bk != ncr_wr) { 6807 printf ("CACHE TEST FAILED: ncr wrote %d, read back %d.\n", 6808 (int) ncr_wr, (int) ncr_bk); 6809 err |= 4; 6810 }; 6811 return (err); 6812} 6813 6814/*========================================================== 6815** 6816** 6817** Profiling the drivers and targets performance. 6818** 6819** 6820**========================================================== 6821*/ 6822 6823/* 6824** Compute the difference in milliseconds. 6825**/ 6826 6827static int ncr_delta (int *from, int *to) 6828{ 6829 if (!from) return (-1); 6830 if (!to) return (-2); 6831 return ((to - from) * 1000 / hz); 6832} 6833 6834#define PROFILE cp->phys.header.stamp 6835static void ncb_profile (ncb_p np, nccb_p cp) 6836{ 6837 int co, da, st, en, di, se, post,work,disc; 6838 u_long diff; 6839 6840 PROFILE.end = ticks; 6841 6842 st = ncr_delta (&PROFILE.start,&PROFILE.status); 6843 if (st<0) return; /* status not reached */ 6844 6845 da = ncr_delta (&PROFILE.start,&PROFILE.data); 6846 if (da<0) return; /* No data transfer phase */ 6847 6848 co = ncr_delta (&PROFILE.start,&PROFILE.command); 6849 if (co<0) return; /* command not executed */ 6850 6851 en = ncr_delta (&PROFILE.start,&PROFILE.end), 6852 di = ncr_delta (&PROFILE.start,&PROFILE.disconnect), 6853 se = ncr_delta (&PROFILE.start,&PROFILE.select); 6854 post = en - st; 6855 6856 /* 6857 ** @PROFILE@ Disconnect time invalid if multiple disconnects 6858 */ 6859 6860 if (di>=0) disc = se-di; else disc = 0; 6861 6862 work = (st - co) - disc; 6863 6864 diff = (np->disc_phys - np->disc_ref) & 0xff; 6865 np->disc_ref += diff; 6866 6867 np->profile.num_trans += 1; 6868 if (cp->ccb) 6869 np->profile.num_bytes += cp->ccb->csio.dxfer_len; 6870 np->profile.num_disc += diff; 6871 np->profile.ms_setup += co; 6872 np->profile.ms_data += work; 6873 np->profile.ms_disc += disc; 6874 np->profile.ms_post += post; 6875} 6876#undef PROFILE 6877 6878/*========================================================== 6879** 6880** Determine the ncr's clock frequency. 6881** This is essential for the negotiation 6882** of the synchronous transfer rate. 6883** 6884**========================================================== 6885** 6886** Note: we have to return the correct value. 6887** THERE IS NO SAVE DEFAULT VALUE. 6888** 6889** Most NCR/SYMBIOS boards are delivered with a 40 Mhz clock. 6890** 53C860 and 53C875 rev. 1 support fast20 transfers but 6891** do not have a clock doubler and so are provided with a 6892** 80 MHz clock. All other fast20 boards incorporate a doubler 6893** and so should be delivered with a 40 MHz clock. 6894** The future fast40 chips (895/895) use a 40 Mhz base clock 6895** and provide a clock quadrupler (160 Mhz). The code below 6896** tries to deal as cleverly as possible with all this stuff. 6897** 6898**---------------------------------------------------------- 6899*/ 6900 6901/* 6902 * Select NCR SCSI clock frequency 6903 */ 6904static void ncr_selectclock(ncb_p np, u_char scntl3) 6905{ 6906 if (np->multiplier < 2) { 6907 OUTB(nc_scntl3, scntl3); 6908 return; 6909 } 6910 6911 if (bootverbose >= 2) 6912 printf ("%s: enabling clock multiplier\n", ncr_name(np)); 6913 6914 OUTB(nc_stest1, DBLEN); /* Enable clock multiplier */ 6915 if (np->multiplier > 2) { /* Poll bit 5 of stest4 for quadrupler */ 6916 int i = 20; 6917 while (!(INB(nc_stest4) & LCKFRQ) && --i > 0) 6918 DELAY(20); 6919 if (!i) 6920 printf("%s: the chip cannot lock the frequency\n", ncr_name(np)); 6921 } else /* Wait 20 micro-seconds for doubler */ 6922 DELAY(20); 6923 OUTB(nc_stest3, HSC); /* Halt the scsi clock */ 6924 OUTB(nc_scntl3, scntl3); 6925 OUTB(nc_stest1, (DBLEN|DBLSEL));/* Select clock multiplier */ 6926 OUTB(nc_stest3, 0x00); /* Restart scsi clock */ 6927} 6928 6929/* 6930 * calculate NCR SCSI clock frequency (in KHz) 6931 */ 6932static unsigned 6933ncrgetfreq (ncb_p np, int gen) 6934{ 6935 int ms = 0; 6936 /* 6937 * Measure GEN timer delay in order 6938 * to calculate SCSI clock frequency 6939 * 6940 * This code will never execute too 6941 * many loop iterations (if DELAY is 6942 * reasonably correct). It could get 6943 * too low a delay (too high a freq.) 6944 * if the CPU is slow executing the 6945 * loop for some reason (an NMI, for 6946 * example). For this reason we will 6947 * if multiple measurements are to be 6948 * performed trust the higher delay 6949 * (lower frequency returned). 6950 */ 6951 OUTB (nc_stest1, 0); /* make sure clock doubler is OFF */ 6952 OUTW (nc_sien , 0); /* mask all scsi interrupts */ 6953 (void) INW (nc_sist); /* clear pending scsi interrupt */ 6954 OUTB (nc_dien , 0); /* mask all dma interrupts */ 6955 (void) INW (nc_sist); /* another one, just to be sure :) */ 6956 OUTB (nc_scntl3, 4); /* set pre-scaler to divide by 3 */ 6957 OUTB (nc_stime1, 0); /* disable general purpose timer */ 6958 OUTB (nc_stime1, gen); /* set to nominal delay of (1<<gen) * 125us */ 6959 while (!(INW(nc_sist) & GEN) && ms++ < 1000) 6960 DELAY(1000); /* count ms */ 6961 OUTB (nc_stime1, 0); /* disable general purpose timer */ 6962 OUTB (nc_scntl3, 0); 6963 /* 6964 * Set prescaler to divide by whatever "0" means. 6965 * "0" ought to choose divide by 2, but appears 6966 * to set divide by 3.5 mode in my 53c810 ... 6967 */ 6968 OUTB (nc_scntl3, 0); 6969 6970 if (bootverbose >= 2) 6971 printf ("\tDelay (GEN=%d): %u msec\n", gen, ms); 6972 /* 6973 * adjust for prescaler, and convert into KHz 6974 */ 6975 return ms ? ((1 << gen) * 4440) / ms : 0; 6976} 6977 6978static void ncr_getclock (ncb_p np, u_char multiplier) 6979{ 6980 unsigned char scntl3; 6981 unsigned char stest1; 6982 scntl3 = INB(nc_scntl3); 6983 stest1 = INB(nc_stest1); 6984 6985 np->multiplier = 1; 6986 6987 if (multiplier > 1) { 6988 np->multiplier = multiplier; 6989 np->clock_khz = 40000 * multiplier; 6990 } else { 6991 if ((scntl3 & 7) == 0) { 6992 unsigned f1, f2; 6993 /* throw away first result */ 6994 (void) ncrgetfreq (np, 11); 6995 f1 = ncrgetfreq (np, 11); 6996 f2 = ncrgetfreq (np, 11); 6997 6998 if (bootverbose >= 2) 6999 printf ("\tNCR clock is %uKHz, %uKHz\n", f1, f2); 7000 if (f1 > f2) f1 = f2; /* trust lower result */ 7001 if (f1 > 45000) { 7002 scntl3 = 5; /* >45Mhz: assume 80MHz */ 7003 } else { 7004 scntl3 = 3; /* <45Mhz: assume 40MHz */ 7005 } 7006 } 7007 else if ((scntl3 & 7) == 5) 7008 np->clock_khz = 80000; /* Probably a 875 rev. 1 ? */ 7009 } 7010} 7011 7012/*=========================================================================*/ 7013 7014#ifdef NCR_TEKRAM_EEPROM 7015 7016struct tekram_eeprom_dev { 7017 u_char devmode; 7018#define TKR_PARCHK 0x01 7019#define TKR_TRYSYNC 0x02 7020#define TKR_ENDISC 0x04 7021#define TKR_STARTUNIT 0x08 7022#define TKR_USETAGS 0x10 7023#define TKR_TRYWIDE 0x20 7024 u_char syncparam; /* max. sync transfer rate (table ?) */ 7025 u_char filler1; 7026 u_char filler2; 7027}; 7028 7029 7030struct tekram_eeprom { 7031 struct tekram_eeprom_dev 7032 dev[16]; 7033 u_char adaptid; 7034 u_char adaptmode; 7035#define TKR_ADPT_GT2DRV 0x01 7036#define TKR_ADPT_GT1GB 0x02 7037#define TKR_ADPT_RSTBUS 0x04 7038#define TKR_ADPT_ACTNEG 0x08 7039#define TKR_ADPT_NOSEEK 0x10 7040#define TKR_ADPT_MORLUN 0x20 7041 u_char delay; /* unit ? ( table ??? ) */ 7042 u_char tags; /* use 4 times as many ... */ 7043 u_char filler[60]; 7044}; 7045 7046static void 7047tekram_write_bit (ncb_p np, int bit) 7048{ 7049 u_char val = 0x10 + ((bit & 1) << 1); 7050 7051 DELAY(10); 7052 OUTB (nc_gpreg, val); 7053 DELAY(10); 7054 OUTB (nc_gpreg, val | 0x04); 7055 DELAY(10); 7056 OUTB (nc_gpreg, val); 7057 DELAY(10); 7058} 7059 7060static int 7061tekram_read_bit (ncb_p np) 7062{ 7063 OUTB (nc_gpreg, 0x10); 7064 DELAY(10); 7065 OUTB (nc_gpreg, 0x14); 7066 DELAY(10); 7067 return INB (nc_gpreg) & 1; 7068} 7069 7070static u_short 7071read_tekram_eeprom_reg (ncb_p np, int reg) 7072{ 7073 int bit; 7074 u_short result = 0; 7075 int cmd = 0x80 | reg; 7076 7077 OUTB (nc_gpreg, 0x10); 7078 7079 tekram_write_bit (np, 1); 7080 for (bit = 7; bit >= 0; bit--) 7081 { 7082 tekram_write_bit (np, cmd >> bit); 7083 } 7084 7085 for (bit = 0; bit < 16; bit++) 7086 { 7087 result <<= 1; 7088 result |= tekram_read_bit (np); 7089 } 7090 7091 OUTB (nc_gpreg, 0x00); 7092 return result; 7093} 7094 7095static int 7096read_tekram_eeprom(ncb_p np, struct tekram_eeprom *buffer) 7097{ 7098 u_short *p = (u_short *) buffer; 7099 u_short sum = 0; 7100 int i; 7101 7102 if (INB (nc_gpcntl) != 0x09) 7103 { 7104 return 0; 7105 } 7106 for (i = 0; i < 64; i++) 7107 { 7108 u_short val; 7109if((i&0x0f) == 0) printf ("%02x:", i*2); 7110 val = read_tekram_eeprom_reg (np, i); 7111 if (p) 7112 *p++ = val; 7113 sum += val; 7114if((i&0x01) == 0x00) printf (" "); 7115 printf ("%02x%02x", val & 0xff, (val >> 8) & 0xff); 7116if((i&0x0f) == 0x0f) printf ("\n"); 7117 } 7118printf ("Sum = %04x\n", sum); 7119 return sum == 0x1234; 7120} 7121#endif /* NCR_TEKRAM_EEPROM */ 7122 7123static device_method_t ncr_methods[] = { 7124 /* Device interface */ 7125 DEVMETHOD(device_probe, ncr_probe), 7126 DEVMETHOD(device_attach, ncr_attach), 7127 7128 { 0, 0 } 7129}; 7130 7131static driver_t ncr_driver = { 7132 "ncr", 7133 ncr_methods, 7134 sizeof(struct ncb), 7135}; 7136 7137static devclass_t ncr_devclass; 7138 7139DRIVER_MODULE(ncr, pci, ncr_driver, ncr_devclass, 0, 0); 7140MODULE_DEPEND(ncr, cam, 1, 1, 1); 7141MODULE_DEPEND(ncr, pci, 1, 1, 1); 7142 7143/*=========================================================================*/ 7144#endif /* _KERNEL */ 7145