1/************************************************************************** 2** 3** 4** Device driver for the NCR 53C8XX PCI-SCSI-Controller Family. 5** 6**------------------------------------------------------------------------- 7** 8** Written for 386bsd and FreeBSD by 9** Wolfgang Stanglmeier <wolf@cologne.de> 10** Stefan Esser <se@mi.Uni-Koeln.de> 11** 12**------------------------------------------------------------------------- 13*/ 14/*- 15** Copyright (c) 1994 Wolfgang Stanglmeier. All rights reserved. 16** 17** Redistribution and use in source and binary forms, with or without 18** modification, are permitted provided that the following conditions 19** are met: 20** 1. Redistributions of source code must retain the above copyright 21** notice, this list of conditions and the following disclaimer. 22** 2. Redistributions in binary form must reproduce the above copyright 23** notice, this list of conditions and the following disclaimer in the 24** documentation and/or other materials provided with the distribution. 25** 3. The name of the author may not be used to endorse or promote products 26** derived from this software without specific prior written permission. 27** 28** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 29** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 30** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 31** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 32** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 33** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34** DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 37** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38** 39*************************************************************************** 40*/ 41 42#include <sys/cdefs.h> 43__FBSDID("$FreeBSD$"); 44 45 46#define NCR_DATE "pl30 98/1/1" 47 48#define NCR_VERSION (2) 49#define MAX_UNITS (16) 50 51#define NCR_GETCC_WITHMSG 52 53#if defined (__FreeBSD__) && defined(_KERNEL) 54#include "opt_ncr.h" 55#endif 56 57/*========================================================== 58** 59** Configuration and Debugging 60** 61** May be overwritten in <arch/conf/xxxx> 62** 63**========================================================== 64*/ 65 66/* 67** SCSI address of this device. 68** The boot routines should have set it. 69** If not, use this. 70*/ 71 72#ifndef SCSI_NCR_MYADDR 73#define SCSI_NCR_MYADDR (7) 74#endif /* SCSI_NCR_MYADDR */ 75 76/* 77** The default synchronous period factor 78** (0=asynchronous) 79** If maximum synchronous frequency is defined, use it instead. 80*/ 81 82#ifndef SCSI_NCR_MAX_SYNC 83 84#ifndef SCSI_NCR_DFLT_SYNC 85#define SCSI_NCR_DFLT_SYNC (12) 86#endif /* SCSI_NCR_DFLT_SYNC */ 87 88#else 89 90#if SCSI_NCR_MAX_SYNC == 0 91#define SCSI_NCR_DFLT_SYNC 0 92#else 93#define SCSI_NCR_DFLT_SYNC (250000 / SCSI_NCR_MAX_SYNC) 94#endif 95 96#endif 97 98/* 99** The minimal asynchronous pre-scaler period (ns) 100** Shall be 40. 101*/ 102 103#ifndef SCSI_NCR_MIN_ASYNC 104#define SCSI_NCR_MIN_ASYNC (40) 105#endif /* SCSI_NCR_MIN_ASYNC */ 106 107/* 108** The maximal bus with (in log2 byte) 109** (0=8 bit, 1=16 bit) 110*/ 111 112#ifndef SCSI_NCR_MAX_WIDE 113#define SCSI_NCR_MAX_WIDE (1) 114#endif /* SCSI_NCR_MAX_WIDE */ 115 116/*========================================================== 117** 118** Configuration and Debugging 119** 120**========================================================== 121*/ 122 123/* 124** Number of targets supported by the driver. 125** n permits target numbers 0..n-1. 126** Default is 7, meaning targets #0..#6. 127** #7 .. is myself. 128*/ 129 130#define MAX_TARGET (16) 131 132/* 133** Number of logic units supported by the driver. 134** n enables logic unit numbers 0..n-1. 135** The common SCSI devices require only 136** one lun, so take 1 as the default. 137*/ 138 139#ifndef MAX_LUN 140#define MAX_LUN (8) 141#endif /* MAX_LUN */ 142 143/* 144** The maximum number of jobs scheduled for starting. 145** There should be one slot per target, and one slot 146** for each tag of each target in use. 147*/ 148 149#define MAX_START (256) 150 151/* 152** The maximum number of segments a transfer is split into. 153*/ 154 155#define MAX_SCATTER (33) 156 157/* 158** The maximum transfer length (should be >= 64k). 159** MUST NOT be greater than (MAX_SCATTER-1) * PAGE_SIZE. 160*/ 161 162#define MAX_SIZE ((MAX_SCATTER-1) * (long) PAGE_SIZE) 163 164/* 165** other 166*/ 167 168#define NCR_SNOOP_TIMEOUT (1000000) 169 170/*========================================================== 171** 172** Include files 173** 174**========================================================== 175*/ 176 177#include <sys/param.h> 178#include <sys/time.h> 179 180#ifdef _KERNEL 181#include <sys/systm.h> 182#include <sys/malloc.h> 183#include <sys/kernel.h> 184#include <sys/module.h> 185#include <sys/sysctl.h> 186#include <sys/lock.h> 187#include <sys/mutex.h> 188#include <sys/bus.h> 189#include <machine/md_var.h> 190#include <machine/bus.h> 191#include <machine/resource.h> 192#include <sys/rman.h> 193#include <vm/vm.h> 194#include <vm/pmap.h> 195#include <vm/vm_extern.h> 196#endif 197 198#include <dev/pci/pcivar.h> 199#include <dev/pci/pcireg.h> 200#include <pci/ncrreg.h> 201 202#include <cam/cam.h> 203#include <cam/cam_ccb.h> 204#include <cam/cam_sim.h> 205#include <cam/cam_xpt_sim.h> 206#include <cam/cam_debug.h> 207 208#include <cam/scsi/scsi_all.h> 209#include <cam/scsi/scsi_message.h> 210 211/*========================================================== 212** 213** Debugging tags 214** 215**========================================================== 216*/ 217 218#define DEBUG_ALLOC (0x0001) 219#define DEBUG_PHASE (0x0002) 220#define DEBUG_POLL (0x0004) 221#define DEBUG_QUEUE (0x0008) 222#define DEBUG_RESULT (0x0010) 223#define DEBUG_SCATTER (0x0020) 224#define DEBUG_SCRIPT (0x0040) 225#define DEBUG_TINY (0x0080) 226#define DEBUG_TIMING (0x0100) 227#define DEBUG_NEGO (0x0200) 228#define DEBUG_TAGS (0x0400) 229#define DEBUG_FREEZE (0x0800) 230#define DEBUG_RESTART (0x1000) 231 232/* 233** Enable/Disable debug messages. 234** Can be changed at runtime too. 235*/ 236#ifdef SCSI_NCR_DEBUG 237 #define DEBUG_FLAGS ncr_debug 238#else /* SCSI_NCR_DEBUG */ 239 #define SCSI_NCR_DEBUG 0 240 #define DEBUG_FLAGS 0 241#endif /* SCSI_NCR_DEBUG */ 242 243 244 245/*========================================================== 246** 247** assert () 248** 249**========================================================== 250** 251** modified copy from 386bsd:/usr/include/sys/assert.h 252** 253**---------------------------------------------------------- 254*/ 255 256#ifdef DIAGNOSTIC 257#define assert(expression) { \ 258 KASSERT(expression, ("%s", #expression)); \ 259} 260#else 261#define assert(expression) { \ 262 if (!(expression)) { \ 263 (void)printf("assertion \"%s\" failed: " \ 264 "file \"%s\", line %d\n", \ 265 #expression, __FILE__, __LINE__); \ 266 } \ 267} 268#endif 269 270/*========================================================== 271** 272** Access to the controller chip. 273** 274**========================================================== 275*/ 276 277#define INB(r) bus_space_read_1(np->bst, np->bsh, offsetof(struct ncr_reg, r)) 278#define INW(r) bus_space_read_2(np->bst, np->bsh, offsetof(struct ncr_reg, r)) 279#define INL(r) bus_space_read_4(np->bst, np->bsh, offsetof(struct ncr_reg, r)) 280 281#define OUTB(r, val) bus_space_write_1(np->bst, np->bsh, \ 282 offsetof(struct ncr_reg, r), val) 283#define OUTW(r, val) bus_space_write_2(np->bst, np->bsh, \ 284 offsetof(struct ncr_reg, r), val) 285#define OUTL(r, val) bus_space_write_4(np->bst, np->bsh, \ 286 offsetof(struct ncr_reg, r), val) 287#define OUTL_OFF(o, val) bus_space_write_4(np->bst, np->bsh, o, val) 288 289#define INB_OFF(o) bus_space_read_1(np->bst, np->bsh, o) 290#define INW_OFF(o) bus_space_read_2(np->bst, np->bsh, o) 291#define INL_OFF(o) bus_space_read_4(np->bst, np->bsh, o) 292 293#define READSCRIPT_OFF(base, off) \ 294 (base ? *((volatile u_int32_t *)((volatile char *)base + (off))) : \ 295 bus_space_read_4(np->bst2, np->bsh2, off)) 296 297#define WRITESCRIPT_OFF(base, off, val) \ 298 do { \ 299 if (base) \ 300 *((volatile u_int32_t *) \ 301 ((volatile char *)base + (off))) = (val); \ 302 else \ 303 bus_space_write_4(np->bst2, np->bsh2, off, val); \ 304 } while (0) 305 306#define READSCRIPT(r) \ 307 READSCRIPT_OFF(np->script, offsetof(struct script, r)) 308 309#define WRITESCRIPT(r, val) \ 310 WRITESCRIPT_OFF(np->script, offsetof(struct script, r), val) 311 312/* 313** Set bit field ON, OFF 314*/ 315 316#define OUTONB(r, m) OUTB(r, INB(r) | (m)) 317#define OUTOFFB(r, m) OUTB(r, INB(r) & ~(m)) 318#define OUTONW(r, m) OUTW(r, INW(r) | (m)) 319#define OUTOFFW(r, m) OUTW(r, INW(r) & ~(m)) 320#define OUTONL(r, m) OUTL(r, INL(r) | (m)) 321#define OUTOFFL(r, m) OUTL(r, INL(r) & ~(m)) 322 323/*========================================================== 324** 325** Command control block states. 326** 327**========================================================== 328*/ 329 330#define HS_IDLE (0) 331#define HS_BUSY (1) 332#define HS_NEGOTIATE (2) /* sync/wide data transfer*/ 333#define HS_DISCONNECT (3) /* Disconnected by target */ 334 335#define HS_COMPLETE (4) 336#define HS_SEL_TIMEOUT (5) /* Selection timeout */ 337#define HS_RESET (6) /* SCSI reset */ 338#define HS_ABORTED (7) /* Transfer aborted */ 339#define HS_TIMEOUT (8) /* Software timeout */ 340#define HS_FAIL (9) /* SCSI or PCI bus errors */ 341#define HS_UNEXPECTED (10) /* Unexpected disconnect */ 342#define HS_STALL (11) /* QUEUE FULL or BUSY */ 343 344#define HS_DONEMASK (0xfc) 345 346/*========================================================== 347** 348** Software Interrupt Codes 349** 350**========================================================== 351*/ 352 353#define SIR_SENSE_RESTART (1) 354#define SIR_SENSE_FAILED (2) 355#define SIR_STALL_RESTART (3) 356#define SIR_STALL_QUEUE (4) 357#define SIR_NEGO_SYNC (5) 358#define SIR_NEGO_WIDE (6) 359#define SIR_NEGO_FAILED (7) 360#define SIR_NEGO_PROTO (8) 361#define SIR_REJECT_RECEIVED (9) 362#define SIR_REJECT_SENT (10) 363#define SIR_IGN_RESIDUE (11) 364#define SIR_MISSING_SAVE (12) 365#define SIR_MAX (12) 366 367/*========================================================== 368** 369** Extended error codes. 370** xerr_status field of struct nccb. 371** 372**========================================================== 373*/ 374 375#define XE_OK (0) 376#define XE_EXTRA_DATA (1) /* unexpected data phase */ 377#define XE_BAD_PHASE (2) /* illegal phase (4/5) */ 378 379/*========================================================== 380** 381** Negotiation status. 382** nego_status field of struct nccb. 383** 384**========================================================== 385*/ 386 387#define NS_SYNC (1) 388#define NS_WIDE (2) 389 390/*========================================================== 391** 392** XXX These are no longer used. Remove once the 393** script is updated. 394** "Special features" of targets. 395** quirks field of struct tcb. 396** actualquirks field of struct nccb. 397** 398**========================================================== 399*/ 400 401#define QUIRK_AUTOSAVE (0x01) 402#define QUIRK_NOMSG (0x02) 403#define QUIRK_NOSYNC (0x10) 404#define QUIRK_NOWIDE16 (0x20) 405#define QUIRK_NOTAGS (0x40) 406#define QUIRK_UPDATE (0x80) 407 408/*========================================================== 409** 410** Misc. 411** 412**========================================================== 413*/ 414 415#define CCB_MAGIC (0xf2691ad2) 416#define MAX_TAGS (32) /* hard limit */ 417 418/*========================================================== 419** 420** OS dependencies. 421** 422**========================================================== 423*/ 424 425#define PRINT_ADDR(ccb) xpt_print_path((ccb)->ccb_h.path) 426 427/*========================================================== 428** 429** Declaration of structs. 430** 431**========================================================== 432*/ 433 434struct tcb; 435struct lcb; 436struct nccb; 437struct ncb; 438struct script; 439 440typedef struct ncb * ncb_p; 441typedef struct tcb * tcb_p; 442typedef struct lcb * lcb_p; 443typedef struct nccb * nccb_p; 444 445struct link { 446 ncrcmd l_cmd; 447 ncrcmd l_paddr; 448}; 449 450struct usrcmd { 451 u_long target; 452 u_long lun; 453 u_long data; 454 u_long cmd; 455}; 456 457#define UC_SETSYNC 10 458#define UC_SETTAGS 11 459#define UC_SETDEBUG 12 460#define UC_SETORDER 13 461#define UC_SETWIDE 14 462#define UC_SETFLAG 15 463 464#define UF_TRACE (0x01) 465 466/*--------------------------------------- 467** 468** Timestamps for profiling 469** 470**--------------------------------------- 471*/ 472 473/* Type of the kernel variable `ticks'. XXX should be declared with the var. */ 474typedef int ticks_t; 475 476struct tstamp { 477 ticks_t start; 478 ticks_t end; 479 ticks_t select; 480 ticks_t command; 481 ticks_t data; 482 ticks_t status; 483 ticks_t disconnect; 484}; 485 486/* 487** profiling data (per device) 488*/ 489 490struct profile { 491 u_long num_trans; 492 u_long num_bytes; 493 u_long num_disc; 494 u_long num_break; 495 u_long num_int; 496 u_long num_fly; 497 u_long ms_setup; 498 u_long ms_data; 499 u_long ms_disc; 500 u_long ms_post; 501}; 502 503/*========================================================== 504** 505** Declaration of structs: target control block 506** 507**========================================================== 508*/ 509 510#define NCR_TRANS_CUR 0x01 /* Modify current neogtiation status */ 511#define NCR_TRANS_ACTIVE 0x03 /* Assume this is the active target */ 512#define NCR_TRANS_GOAL 0x04 /* Modify negotiation goal */ 513#define NCR_TRANS_USER 0x08 /* Modify user negotiation settings */ 514 515struct ncr_transinfo { 516 u_int8_t width; 517 u_int8_t period; 518 u_int8_t offset; 519}; 520 521struct ncr_target_tinfo { 522 /* Hardware version of our sync settings */ 523 u_int8_t disc_tag; 524#define NCR_CUR_DISCENB 0x01 525#define NCR_CUR_TAGENB 0x02 526#define NCR_USR_DISCENB 0x04 527#define NCR_USR_TAGENB 0x08 528 u_int8_t sval; 529 struct ncr_transinfo current; 530 struct ncr_transinfo goal; 531 struct ncr_transinfo user; 532 /* Hardware version of our wide settings */ 533 u_int8_t wval; 534}; 535 536struct tcb { 537 /* 538 ** during reselection the ncr jumps to this point 539 ** with SFBR set to the encoded target number 540 ** with bit 7 set. 541 ** if it's not this target, jump to the next. 542 ** 543 ** JUMP IF (SFBR != #target#) 544 ** @(next tcb) 545 */ 546 547 struct link jump_tcb; 548 549 /* 550 ** load the actual values for the sxfer and the scntl3 551 ** register (sync/wide mode). 552 ** 553 ** SCR_COPY (1); 554 ** @(sval field of this tcb) 555 ** @(sxfer register) 556 ** SCR_COPY (1); 557 ** @(wval field of this tcb) 558 ** @(scntl3 register) 559 */ 560 561 ncrcmd getscr[6]; 562 563 /* 564 ** if next message is "identify" 565 ** then load the message to SFBR, 566 ** else load 0 to SFBR. 567 ** 568 ** CALL 569 ** <RESEL_LUN> 570 */ 571 572 struct link call_lun; 573 574 /* 575 ** now look for the right lun. 576 ** 577 ** JUMP 578 ** @(first nccb of this lun) 579 */ 580 581 struct link jump_lcb; 582 583 /* 584 ** pointer to interrupted getcc nccb 585 */ 586 587 nccb_p hold_cp; 588 589 /* 590 ** pointer to nccb used for negotiating. 591 ** Avoid to start a nego for all queued commands 592 ** when tagged command queuing is enabled. 593 */ 594 595 nccb_p nego_cp; 596 597 /* 598 ** statistical data 599 */ 600 601 u_long transfers; 602 u_long bytes; 603 604 /* 605 ** user settable limits for sync transfer 606 ** and tagged commands. 607 */ 608 609 struct ncr_target_tinfo tinfo; 610 611 /* 612 ** the lcb's of this tcb 613 */ 614 615 lcb_p lp[MAX_LUN]; 616}; 617 618/*========================================================== 619** 620** Declaration of structs: lun control block 621** 622**========================================================== 623*/ 624 625struct lcb { 626 /* 627 ** during reselection the ncr jumps to this point 628 ** with SFBR set to the "Identify" message. 629 ** if it's not this lun, jump to the next. 630 ** 631 ** JUMP IF (SFBR != #lun#) 632 ** @(next lcb of this target) 633 */ 634 635 struct link jump_lcb; 636 637 /* 638 ** if next message is "simple tag", 639 ** then load the tag to SFBR, 640 ** else load 0 to SFBR. 641 ** 642 ** CALL 643 ** <RESEL_TAG> 644 */ 645 646 struct link call_tag; 647 648 /* 649 ** now look for the right nccb. 650 ** 651 ** JUMP 652 ** @(first nccb of this lun) 653 */ 654 655 struct link jump_nccb; 656 657 /* 658 ** start of the nccb chain 659 */ 660 661 nccb_p next_nccb; 662 663 /* 664 ** Control of tagged queueing 665 */ 666 667 u_char reqnccbs; 668 u_char reqlink; 669 u_char actlink; 670 u_char usetags; 671 u_char lasttag; 672}; 673 674/*========================================================== 675** 676** Declaration of structs: COMMAND control block 677** 678**========================================================== 679** 680** This substructure is copied from the nccb to a 681** global address after selection (or reselection) 682** and copied back before disconnect. 683** 684** These fields are accessible to the script processor. 685** 686**---------------------------------------------------------- 687*/ 688 689struct head { 690 /* 691 ** Execution of a nccb starts at this point. 692 ** It's a jump to the "SELECT" label 693 ** of the script. 694 ** 695 ** After successful selection the script 696 ** processor overwrites it with a jump to 697 ** the IDLE label of the script. 698 */ 699 700 struct link launch; 701 702 /* 703 ** Saved data pointer. 704 ** Points to the position in the script 705 ** responsible for the actual transfer 706 ** of data. 707 ** It's written after reception of a 708 ** "SAVE_DATA_POINTER" message. 709 ** The goalpointer points after 710 ** the last transfer command. 711 */ 712 713 u_int32_t savep; 714 u_int32_t lastp; 715 u_int32_t goalp; 716 717 /* 718 ** The virtual address of the nccb 719 ** containing this header. 720 */ 721 722 nccb_p cp; 723 724 /* 725 ** space for some timestamps to gather 726 ** profiling data about devices and this driver. 727 */ 728 729 struct tstamp stamp; 730 731 /* 732 ** status fields. 733 */ 734 735 u_char status[8]; 736}; 737 738/* 739** The status bytes are used by the host and the script processor. 740** 741** The first four byte are copied to the scratchb register 742** (declared as scr0..scr3 in ncr_reg.h) just after the select/reselect, 743** and copied back just after disconnecting. 744** Inside the script the XX_REG are used. 745** 746** The last four bytes are used inside the script by "COPY" commands. 747** Because source and destination must have the same alignment 748** in a longword, the fields HAVE to be at the choosen offsets. 749** xerr_st (4) 0 (0x34) scratcha 750** sync_st (5) 1 (0x05) sxfer 751** wide_st (7) 3 (0x03) scntl3 752*/ 753 754/* 755** First four bytes (script) 756*/ 757#define QU_REG scr0 758#define HS_REG scr1 759#define HS_PRT nc_scr1 760#define SS_REG scr2 761#define PS_REG scr3 762 763/* 764** First four bytes (host) 765*/ 766#define actualquirks phys.header.status[0] 767#define host_status phys.header.status[1] 768#define s_status phys.header.status[2] 769#define parity_status phys.header.status[3] 770 771/* 772** Last four bytes (script) 773*/ 774#define xerr_st header.status[4] /* MUST be ==0 mod 4 */ 775#define sync_st header.status[5] /* MUST be ==1 mod 4 */ 776#define nego_st header.status[6] 777#define wide_st header.status[7] /* MUST be ==3 mod 4 */ 778 779/* 780** Last four bytes (host) 781*/ 782#define xerr_status phys.xerr_st 783#define sync_status phys.sync_st 784#define nego_status phys.nego_st 785#define wide_status phys.wide_st 786 787/*========================================================== 788** 789** Declaration of structs: Data structure block 790** 791**========================================================== 792** 793** During execution of a nccb by the script processor, 794** the DSA (data structure address) register points 795** to this substructure of the nccb. 796** This substructure contains the header with 797** the script-processor-changable data and 798** data blocks for the indirect move commands. 799** 800**---------------------------------------------------------- 801*/ 802 803struct dsb { 804 805 /* 806 ** Header. 807 ** Has to be the first entry, 808 ** because it's jumped to by the 809 ** script processor 810 */ 811 812 struct head header; 813 814 /* 815 ** Table data for Script 816 */ 817 818 struct scr_tblsel select; 819 struct scr_tblmove smsg ; 820 struct scr_tblmove smsg2 ; 821 struct scr_tblmove cmd ; 822 struct scr_tblmove scmd ; 823 struct scr_tblmove sense ; 824 struct scr_tblmove data [MAX_SCATTER]; 825}; 826 827/*========================================================== 828** 829** Declaration of structs: Command control block. 830** 831**========================================================== 832** 833** During execution of a nccb by the script processor, 834** the DSA (data structure address) register points 835** to this substructure of the nccb. 836** This substructure contains the header with 837** the script-processor-changable data and then 838** data blocks for the indirect move commands. 839** 840**---------------------------------------------------------- 841*/ 842 843 844struct nccb { 845 /* 846 ** This filler ensures that the global header is 847 ** cache line size aligned. 848 */ 849 ncrcmd filler[4]; 850 851 /* 852 ** during reselection the ncr jumps to this point. 853 ** If a "SIMPLE_TAG" message was received, 854 ** then SFBR is set to the tag. 855 ** else SFBR is set to 0 856 ** If looking for another tag, jump to the next nccb. 857 ** 858 ** JUMP IF (SFBR != #TAG#) 859 ** @(next nccb of this lun) 860 */ 861 862 struct link jump_nccb; 863 864 /* 865 ** After execution of this call, the return address 866 ** (in the TEMP register) points to the following 867 ** data structure block. 868 ** So copy it to the DSA register, and start 869 ** processing of this data structure. 870 ** 871 ** CALL 872 ** <RESEL_TMP> 873 */ 874 875 struct link call_tmp; 876 877 /* 878 ** This is the data structure which is 879 ** to be executed by the script processor. 880 */ 881 882 struct dsb phys; 883 884 /* 885 ** If a data transfer phase is terminated too early 886 ** (after reception of a message (i.e. DISCONNECT)), 887 ** we have to prepare a mini script to transfer 888 ** the rest of the data. 889 */ 890 891 ncrcmd patch[8]; 892 893 /* 894 ** The general SCSI driver provides a 895 ** pointer to a control block. 896 */ 897 898 union ccb *ccb; 899 900 /* 901 ** We prepare a message to be sent after selection, 902 ** and a second one to be sent after getcc selection. 903 ** Contents are IDENTIFY and SIMPLE_TAG. 904 ** While negotiating sync or wide transfer, 905 ** a SDTM or WDTM message is appended. 906 */ 907 908 u_char scsi_smsg [8]; 909 u_char scsi_smsg2[8]; 910 911 /* 912 ** Lock this nccb. 913 ** Flag is used while looking for a free nccb. 914 */ 915 916 u_long magic; 917 918 /* 919 ** Physical address of this instance of nccb 920 */ 921 922 u_long p_nccb; 923 924 /* 925 ** Completion time out for this job. 926 ** It's set to time of start + allowed number of seconds. 927 */ 928 929 time_t tlimit; 930 931 /* 932 ** All nccbs of one hostadapter are chained. 933 */ 934 935 nccb_p link_nccb; 936 937 /* 938 ** All nccbs of one target/lun are chained. 939 */ 940 941 nccb_p next_nccb; 942 943 /* 944 ** Sense command 945 */ 946 947 u_char sensecmd[6]; 948 949 /* 950 ** Tag for this transfer. 951 ** It's patched into jump_nccb. 952 ** If it's not zero, a SIMPLE_TAG 953 ** message is included in smsg. 954 */ 955 956 u_char tag; 957}; 958 959#define CCB_PHYS(cp,lbl) (cp->p_nccb + offsetof(struct nccb, lbl)) 960 961/*========================================================== 962** 963** Declaration of structs: NCR device descriptor 964** 965**========================================================== 966*/ 967 968struct ncb { 969 /* 970 ** The global header. 971 ** Accessible to both the host and the 972 ** script-processor. 973 ** We assume it is cache line size aligned. 974 */ 975 struct head header; 976 977 int unit; 978 979 /*----------------------------------------------- 980 ** Scripts .. 981 **----------------------------------------------- 982 ** 983 ** During reselection the ncr jumps to this point. 984 ** The SFBR register is loaded with the encoded target id. 985 ** 986 ** Jump to the first target. 987 ** 988 ** JUMP 989 ** @(next tcb) 990 */ 991 struct link jump_tcb; 992 993 /*----------------------------------------------- 994 ** Configuration .. 995 **----------------------------------------------- 996 ** 997 ** virtual and physical addresses 998 ** of the 53c810 chip. 999 */ 1000 int reg_rid; 1001 struct resource *reg_res; 1002 bus_space_tag_t bst; 1003 bus_space_handle_t bsh; 1004 1005 int sram_rid; 1006 struct resource *sram_res; 1007 bus_space_tag_t bst2; 1008 bus_space_handle_t bsh2; 1009 1010 struct resource *irq_res; 1011 void *irq_handle; 1012 1013 /* 1014 ** Scripts instance virtual address. 1015 */ 1016 struct script *script; 1017 struct scripth *scripth; 1018 1019 /* 1020 ** Scripts instance physical address. 1021 */ 1022 u_long p_script; 1023 u_long p_scripth; 1024 1025 /* 1026 ** The SCSI address of the host adapter. 1027 */ 1028 u_char myaddr; 1029 1030 /* 1031 ** timing parameters 1032 */ 1033 u_char minsync; /* Minimum sync period factor */ 1034 u_char maxsync; /* Maximum sync period factor */ 1035 u_char maxoffs; /* Max scsi offset */ 1036 u_char clock_divn; /* Number of clock divisors */ 1037 u_long clock_khz; /* SCSI clock frequency in KHz */ 1038 u_long features; /* Chip features map */ 1039 u_char multiplier; /* Clock multiplier (1,2,4) */ 1040 1041 u_char maxburst; /* log base 2 of dwords burst */ 1042 1043 /* 1044 ** BIOS supplied PCI bus options 1045 */ 1046 u_char rv_scntl3; 1047 u_char rv_dcntl; 1048 u_char rv_dmode; 1049 u_char rv_ctest3; 1050 u_char rv_ctest4; 1051 u_char rv_ctest5; 1052 u_char rv_gpcntl; 1053 u_char rv_stest2; 1054 1055 /*----------------------------------------------- 1056 ** CAM SIM information for this instance 1057 **----------------------------------------------- 1058 */ 1059 1060 struct cam_sim *sim; 1061 struct cam_path *path; 1062 1063 /*----------------------------------------------- 1064 ** Job control 1065 **----------------------------------------------- 1066 ** 1067 ** Commands from user 1068 */ 1069 struct usrcmd user; 1070 1071 /* 1072 ** Target data 1073 */ 1074 struct tcb target[MAX_TARGET]; 1075 1076 /* 1077 ** Start queue. 1078 */ 1079 u_int32_t squeue [MAX_START]; 1080 u_short squeueput; 1081 1082 /* 1083 ** Timeout handler 1084 */ 1085 time_t heartbeat; 1086 u_short ticks; 1087 u_short latetime; 1088 time_t lasttime; 1089 struct callout_handle timeout_ch; 1090 1091 /*----------------------------------------------- 1092 ** Debug and profiling 1093 **----------------------------------------------- 1094 ** 1095 ** register dump 1096 */ 1097 struct ncr_reg regdump; 1098 time_t regtime; 1099 1100 /* 1101 ** Profiling data 1102 */ 1103 struct profile profile; 1104 u_long disc_phys; 1105 u_long disc_ref; 1106 1107 /* 1108 ** Head of list of all nccbs for this controller. 1109 */ 1110 nccb_p link_nccb; 1111 1112 /* 1113 ** message buffers. 1114 ** Should be longword aligned, 1115 ** because they're written with a 1116 ** COPY script command. 1117 */ 1118 u_char msgout[8]; 1119 u_char msgin [8]; 1120 u_int32_t lastmsg; 1121 1122 /* 1123 ** Buffer for STATUS_IN phase. 1124 */ 1125 u_char scratch; 1126 1127 /* 1128 ** controller chip dependent maximal transfer width. 1129 */ 1130 u_char maxwide; 1131 1132#ifdef NCR_IOMAPPED 1133 /* 1134 ** address of the ncr control registers in io space 1135 */ 1136 pci_port_t port; 1137#endif 1138}; 1139 1140#define NCB_SCRIPT_PHYS(np,lbl) (np->p_script + offsetof (struct script, lbl)) 1141#define NCB_SCRIPTH_PHYS(np,lbl) (np->p_scripth + offsetof (struct scripth,lbl)) 1142 1143/*========================================================== 1144** 1145** 1146** Script for NCR-Processor. 1147** 1148** Use ncr_script_fill() to create the variable parts. 1149** Use ncr_script_copy_and_bind() to make a copy and 1150** bind to physical addresses. 1151** 1152** 1153**========================================================== 1154** 1155** We have to know the offsets of all labels before 1156** we reach them (for forward jumps). 1157** Therefore we declare a struct here. 1158** If you make changes inside the script, 1159** DONT FORGET TO CHANGE THE LENGTHS HERE! 1160** 1161**---------------------------------------------------------- 1162*/ 1163 1164/* 1165** Script fragments which are loaded into the on-board RAM 1166** of 825A, 875 and 895 chips. 1167*/ 1168struct script { 1169 ncrcmd start [ 7]; 1170 ncrcmd start0 [ 2]; 1171 ncrcmd start1 [ 3]; 1172 ncrcmd startpos [ 1]; 1173 ncrcmd trysel [ 8]; 1174 ncrcmd skip [ 8]; 1175 ncrcmd skip2 [ 3]; 1176 ncrcmd idle [ 2]; 1177 ncrcmd select [ 18]; 1178 ncrcmd prepare [ 4]; 1179 ncrcmd loadpos [ 14]; 1180 ncrcmd prepare2 [ 24]; 1181 ncrcmd setmsg [ 5]; 1182 ncrcmd clrack [ 2]; 1183 ncrcmd dispatch [ 33]; 1184 ncrcmd no_data [ 17]; 1185 ncrcmd checkatn [ 10]; 1186 ncrcmd command [ 15]; 1187 ncrcmd status [ 27]; 1188 ncrcmd msg_in [ 26]; 1189 ncrcmd msg_bad [ 6]; 1190 ncrcmd complete [ 13]; 1191 ncrcmd cleanup [ 12]; 1192 ncrcmd cleanup0 [ 9]; 1193 ncrcmd signal [ 12]; 1194 ncrcmd save_dp [ 5]; 1195 ncrcmd restore_dp [ 5]; 1196 ncrcmd disconnect [ 12]; 1197 ncrcmd disconnect0 [ 5]; 1198 ncrcmd disconnect1 [ 23]; 1199 ncrcmd msg_out [ 9]; 1200 ncrcmd msg_out_done [ 7]; 1201 ncrcmd badgetcc [ 6]; 1202 ncrcmd reselect [ 8]; 1203 ncrcmd reselect1 [ 8]; 1204 ncrcmd reselect2 [ 8]; 1205 ncrcmd resel_tmp [ 5]; 1206 ncrcmd resel_lun [ 18]; 1207 ncrcmd resel_tag [ 24]; 1208 ncrcmd data_in [MAX_SCATTER * 4 + 7]; 1209 ncrcmd data_out [MAX_SCATTER * 4 + 7]; 1210}; 1211 1212/* 1213** Script fragments which stay in main memory for all chips. 1214*/ 1215struct scripth { 1216 ncrcmd tryloop [MAX_START*5+2]; 1217 ncrcmd msg_parity [ 6]; 1218 ncrcmd msg_reject [ 8]; 1219 ncrcmd msg_ign_residue [ 32]; 1220 ncrcmd msg_extended [ 18]; 1221 ncrcmd msg_ext_2 [ 18]; 1222 ncrcmd msg_wdtr [ 27]; 1223 ncrcmd msg_ext_3 [ 18]; 1224 ncrcmd msg_sdtr [ 27]; 1225 ncrcmd msg_out_abort [ 10]; 1226 ncrcmd getcc [ 4]; 1227 ncrcmd getcc1 [ 5]; 1228#ifdef NCR_GETCC_WITHMSG 1229 ncrcmd getcc2 [ 29]; 1230#else 1231 ncrcmd getcc2 [ 14]; 1232#endif 1233 ncrcmd getcc3 [ 6]; 1234 ncrcmd aborttag [ 4]; 1235 ncrcmd abort [ 22]; 1236 ncrcmd snooptest [ 9]; 1237 ncrcmd snoopend [ 2]; 1238}; 1239 1240/*========================================================== 1241** 1242** 1243** Function headers. 1244** 1245** 1246**========================================================== 1247*/ 1248 1249#ifdef _KERNEL 1250static nccb_p ncr_alloc_nccb(ncb_p np, u_long target, u_long lun); 1251static void ncr_complete(ncb_p np, nccb_p cp); 1252static int ncr_delta(int * from, int * to); 1253static void ncr_exception(ncb_p np); 1254static void ncr_free_nccb(ncb_p np, nccb_p cp); 1255static void ncr_freeze_devq(ncb_p np, struct cam_path *path); 1256static void ncr_selectclock(ncb_p np, u_char scntl3); 1257static void ncr_getclock(ncb_p np, u_char multiplier); 1258static nccb_p ncr_get_nccb(ncb_p np, u_long t,u_long l); 1259#if 0 1260static u_int32_t ncr_info(int unit); 1261#endif 1262static void ncr_init(ncb_p np, char * msg, u_long code); 1263static void ncr_intr(void *vnp); 1264static void ncr_int_ma(ncb_p np, u_char dstat); 1265static void ncr_int_sir(ncb_p np); 1266static void ncr_int_sto(ncb_p np); 1267#if 0 1268static void ncr_min_phys(struct buf *bp); 1269#endif 1270static void ncr_poll(struct cam_sim *sim); 1271static void ncb_profile(ncb_p np, nccb_p cp); 1272static void ncr_script_copy_and_bind(ncb_p np, ncrcmd *src, ncrcmd *dst, 1273 int len); 1274static void ncr_script_fill(struct script * scr, struct scripth *scrh); 1275static int ncr_scatter(struct dsb* phys, vm_offset_t vaddr, 1276 vm_size_t datalen); 1277static void ncr_getsync(ncb_p np, u_char sfac, u_char *fakp, 1278 u_char *scntl3p); 1279static void ncr_setsync(ncb_p np, nccb_p cp,u_char scntl3,u_char sxfer, 1280 u_char period); 1281static void ncr_setwide(ncb_p np, nccb_p cp, u_char wide, u_char ack); 1282static int ncr_show_msg(u_char * msg); 1283static int ncr_snooptest(ncb_p np); 1284static void ncr_action(struct cam_sim *sim, union ccb *ccb); 1285static void ncr_timeout(void *arg); 1286static void ncr_wakeup(ncb_p np, u_long code); 1287 1288static int ncr_probe(device_t dev); 1289static int ncr_attach(device_t dev); 1290 1291#endif /* _KERNEL */ 1292 1293/*========================================================== 1294** 1295** 1296** Global static data. 1297** 1298** 1299**========================================================== 1300*/ 1301 1302static const u_long ncr_version = NCR_VERSION * 11 1303 + (u_long) sizeof (struct ncb) * 7 1304 + (u_long) sizeof (struct nccb) * 5 1305 + (u_long) sizeof (struct lcb) * 3 1306 + (u_long) sizeof (struct tcb) * 2; 1307 1308#ifdef _KERNEL 1309 1310static int ncr_debug = SCSI_NCR_DEBUG; 1311SYSCTL_INT(_debug, OID_AUTO, ncr_debug, CTLFLAG_RW, &ncr_debug, 0, ""); 1312 1313static int ncr_cache; /* to be aligned _NOT_ static */ 1314 1315/*========================================================== 1316** 1317** 1318** Global static data: auto configure 1319** 1320** 1321**========================================================== 1322*/ 1323 1324#define NCR_810_ID (0x00011000ul) 1325#define NCR_815_ID (0x00041000ul) 1326#define NCR_820_ID (0x00021000ul) 1327#define NCR_825_ID (0x00031000ul) 1328#define NCR_860_ID (0x00061000ul) 1329#define NCR_875_ID (0x000f1000ul) 1330#define NCR_875_ID2 (0x008f1000ul) 1331#define NCR_885_ID (0x000d1000ul) 1332#define NCR_895_ID (0x000c1000ul) 1333#define NCR_896_ID (0x000b1000ul) 1334#define NCR_895A_ID (0x00121000ul) 1335#define NCR_1510D_ID (0x000a1000ul) 1336 1337 1338static char *ncr_name (ncb_p np) 1339{ 1340 static char name[10]; 1341 snprintf(name, sizeof(name), "ncr%d", np->unit); 1342 return (name); 1343} 1344 1345/*========================================================== 1346** 1347** 1348** Scripts for NCR-Processor. 1349** 1350** Use ncr_script_bind for binding to physical addresses. 1351** 1352** 1353**========================================================== 1354** 1355** NADDR generates a reference to a field of the controller data. 1356** PADDR generates a reference to another part of the script. 1357** RADDR generates a reference to a script processor register. 1358** FADDR generates a reference to a script processor register 1359** with offset. 1360** 1361**---------------------------------------------------------- 1362*/ 1363 1364#define RELOC_SOFTC 0x40000000 1365#define RELOC_LABEL 0x50000000 1366#define RELOC_REGISTER 0x60000000 1367#define RELOC_KVAR 0x70000000 1368#define RELOC_LABELH 0x80000000 1369#define RELOC_MASK 0xf0000000 1370 1371#define NADDR(label) (RELOC_SOFTC | offsetof(struct ncb, label)) 1372#define PADDR(label) (RELOC_LABEL | offsetof(struct script, label)) 1373#define PADDRH(label) (RELOC_LABELH | offsetof(struct scripth, label)) 1374#define RADDR(label) (RELOC_REGISTER | REG(label)) 1375#define FADDR(label,ofs)(RELOC_REGISTER | ((REG(label))+(ofs))) 1376#define KVAR(which) (RELOC_KVAR | (which)) 1377 1378#define KVAR_SECOND (0) 1379#define KVAR_TICKS (1) 1380#define KVAR_NCR_CACHE (2) 1381 1382#define SCRIPT_KVAR_FIRST (0) 1383#define SCRIPT_KVAR_LAST (3) 1384 1385/* 1386 * Kernel variables referenced in the scripts. 1387 * THESE MUST ALL BE ALIGNED TO A 4-BYTE BOUNDARY. 1388 */ 1389static volatile void *script_kvars[] = 1390 { &time_second, &ticks, &ncr_cache }; 1391 1392static struct script script0 = { 1393/*--------------------------< START >-----------------------*/ { 1394 /* 1395 ** Claim to be still alive ... 1396 */ 1397 SCR_COPY (sizeof (((struct ncb *)0)->heartbeat)), 1398 KVAR (KVAR_SECOND), 1399 NADDR (heartbeat), 1400 /* 1401 ** Make data structure address invalid. 1402 ** clear SIGP. 1403 */ 1404 SCR_LOAD_REG (dsa, 0xff), 1405 0, 1406 SCR_FROM_REG (ctest2), 1407 0, 1408}/*-------------------------< START0 >----------------------*/,{ 1409 /* 1410 ** Hook for interrupted GetConditionCode. 1411 ** Will be patched to ... IFTRUE by 1412 ** the interrupt handler. 1413 */ 1414 SCR_INT ^ IFFALSE (0), 1415 SIR_SENSE_RESTART, 1416 1417}/*-------------------------< START1 >----------------------*/,{ 1418 /* 1419 ** Hook for stalled start queue. 1420 ** Will be patched to IFTRUE by the interrupt handler. 1421 */ 1422 SCR_INT ^ IFFALSE (0), 1423 SIR_STALL_RESTART, 1424 /* 1425 ** Then jump to a certain point in tryloop. 1426 ** Due to the lack of indirect addressing the code 1427 ** is self modifying here. 1428 */ 1429 SCR_JUMP, 1430}/*-------------------------< STARTPOS >--------------------*/,{ 1431 PADDRH(tryloop), 1432 1433}/*-------------------------< TRYSEL >----------------------*/,{ 1434 /* 1435 ** Now: 1436 ** DSA: Address of a Data Structure 1437 ** or Address of the IDLE-Label. 1438 ** 1439 ** TEMP: Address of a script, which tries to 1440 ** start the NEXT entry. 1441 ** 1442 ** Save the TEMP register into the SCRATCHA register. 1443 ** Then copy the DSA to TEMP and RETURN. 1444 ** This is kind of an indirect jump. 1445 ** (The script processor has NO stack, so the 1446 ** CALL is actually a jump and link, and the 1447 ** RETURN is an indirect jump.) 1448 ** 1449 ** If the slot was empty, DSA contains the address 1450 ** of the IDLE part of this script. The processor 1451 ** jumps to IDLE and waits for a reselect. 1452 ** It will wake up and try the same slot again 1453 ** after the SIGP bit becomes set by the host. 1454 ** 1455 ** If the slot was not empty, DSA contains 1456 ** the address of the phys-part of a nccb. 1457 ** The processor jumps to this address. 1458 ** phys starts with head, 1459 ** head starts with launch, 1460 ** so actually the processor jumps to 1461 ** the lauch part. 1462 ** If the entry is scheduled for execution, 1463 ** then launch contains a jump to SELECT. 1464 ** If it's not scheduled, it contains a jump to IDLE. 1465 */ 1466 SCR_COPY (4), 1467 RADDR (temp), 1468 RADDR (scratcha), 1469 SCR_COPY (4), 1470 RADDR (dsa), 1471 RADDR (temp), 1472 SCR_RETURN, 1473 0 1474 1475}/*-------------------------< SKIP >------------------------*/,{ 1476 /* 1477 ** This entry has been canceled. 1478 ** Next time use the next slot. 1479 */ 1480 SCR_COPY (4), 1481 RADDR (scratcha), 1482 PADDR (startpos), 1483 /* 1484 ** patch the launch field. 1485 ** should look like an idle process. 1486 */ 1487 SCR_COPY_F (4), 1488 RADDR (dsa), 1489 PADDR (skip2), 1490 SCR_COPY (8), 1491 PADDR (idle), 1492}/*-------------------------< SKIP2 >-----------------------*/,{ 1493 0, 1494 SCR_JUMP, 1495 PADDR(start), 1496}/*-------------------------< IDLE >------------------------*/,{ 1497 /* 1498 ** Nothing to do? 1499 ** Wait for reselect. 1500 */ 1501 SCR_JUMP, 1502 PADDR(reselect), 1503 1504}/*-------------------------< SELECT >----------------------*/,{ 1505 /* 1506 ** DSA contains the address of a scheduled 1507 ** data structure. 1508 ** 1509 ** SCRATCHA contains the address of the script, 1510 ** which starts the next entry. 1511 ** 1512 ** Set Initiator mode. 1513 ** 1514 ** (Target mode is left as an exercise for the reader) 1515 */ 1516 1517 SCR_CLR (SCR_TRG), 1518 0, 1519 SCR_LOAD_REG (HS_REG, 0xff), 1520 0, 1521 1522 /* 1523 ** And try to select this target. 1524 */ 1525 SCR_SEL_TBL_ATN ^ offsetof (struct dsb, select), 1526 PADDR (reselect), 1527 1528 /* 1529 ** Now there are 4 possibilities: 1530 ** 1531 ** (1) The ncr loses arbitration. 1532 ** This is ok, because it will try again, 1533 ** when the bus becomes idle. 1534 ** (But beware of the timeout function!) 1535 ** 1536 ** (2) The ncr is reselected. 1537 ** Then the script processor takes the jump 1538 ** to the RESELECT label. 1539 ** 1540 ** (3) The ncr completes the selection. 1541 ** Then it will execute the next statement. 1542 ** 1543 ** (4) There is a selection timeout. 1544 ** Then the ncr should interrupt the host and stop. 1545 ** Unfortunately, it seems to continue execution 1546 ** of the script. But it will fail with an 1547 ** IID-interrupt on the next WHEN. 1548 */ 1549 1550 SCR_JUMPR ^ IFTRUE (WHEN (SCR_MSG_IN)), 1551 0, 1552 1553 /* 1554 ** Send the IDENTIFY and SIMPLE_TAG messages 1555 ** (and the MSG_EXT_SDTR message) 1556 */ 1557 SCR_MOVE_TBL ^ SCR_MSG_OUT, 1558 offsetof (struct dsb, smsg), 1559#ifdef undef /* XXX better fail than try to deal with this ... */ 1560 SCR_JUMPR ^ IFTRUE (WHEN (SCR_MSG_OUT)), 1561 -16, 1562#endif 1563 SCR_CLR (SCR_ATN), 1564 0, 1565 SCR_COPY (1), 1566 RADDR (sfbr), 1567 NADDR (lastmsg), 1568 /* 1569 ** Selection complete. 1570 ** Next time use the next slot. 1571 */ 1572 SCR_COPY (4), 1573 RADDR (scratcha), 1574 PADDR (startpos), 1575}/*-------------------------< PREPARE >----------------------*/,{ 1576 /* 1577 ** The ncr doesn't have an indirect load 1578 ** or store command. So we have to 1579 ** copy part of the control block to a 1580 ** fixed place, where we can access it. 1581 ** 1582 ** We patch the address part of a 1583 ** COPY command with the DSA-register. 1584 */ 1585 SCR_COPY_F (4), 1586 RADDR (dsa), 1587 PADDR (loadpos), 1588 /* 1589 ** then we do the actual copy. 1590 */ 1591 SCR_COPY (sizeof (struct head)), 1592 /* 1593 ** continued after the next label ... 1594 */ 1595 1596}/*-------------------------< LOADPOS >---------------------*/,{ 1597 0, 1598 NADDR (header), 1599 /* 1600 ** Mark this nccb as not scheduled. 1601 */ 1602 SCR_COPY (8), 1603 PADDR (idle), 1604 NADDR (header.launch), 1605 /* 1606 ** Set a time stamp for this selection 1607 */ 1608 SCR_COPY (sizeof (ticks)), 1609 KVAR (KVAR_TICKS), 1610 NADDR (header.stamp.select), 1611 /* 1612 ** load the savep (saved pointer) into 1613 ** the TEMP register (actual pointer) 1614 */ 1615 SCR_COPY (4), 1616 NADDR (header.savep), 1617 RADDR (temp), 1618 /* 1619 ** Initialize the status registers 1620 */ 1621 SCR_COPY (4), 1622 NADDR (header.status), 1623 RADDR (scr0), 1624 1625}/*-------------------------< PREPARE2 >---------------------*/,{ 1626 /* 1627 ** Load the synchronous mode register 1628 */ 1629 SCR_COPY (1), 1630 NADDR (sync_st), 1631 RADDR (sxfer), 1632 /* 1633 ** Load the wide mode and timing register 1634 */ 1635 SCR_COPY (1), 1636 NADDR (wide_st), 1637 RADDR (scntl3), 1638 /* 1639 ** Initialize the msgout buffer with a NOOP message. 1640 */ 1641 SCR_LOAD_REG (scratcha, MSG_NOOP), 1642 0, 1643 SCR_COPY (1), 1644 RADDR (scratcha), 1645 NADDR (msgout), 1646 SCR_COPY (1), 1647 RADDR (scratcha), 1648 NADDR (msgin), 1649 /* 1650 ** Message in phase ? 1651 */ 1652 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)), 1653 PADDR (dispatch), 1654 /* 1655 ** Extended or reject message ? 1656 */ 1657 SCR_FROM_REG (sbdl), 1658 0, 1659 SCR_JUMP ^ IFTRUE (DATA (MSG_EXTENDED)), 1660 PADDR (msg_in), 1661 SCR_JUMP ^ IFTRUE (DATA (MSG_MESSAGE_REJECT)), 1662 PADDRH (msg_reject), 1663 /* 1664 ** normal processing 1665 */ 1666 SCR_JUMP, 1667 PADDR (dispatch), 1668}/*-------------------------< SETMSG >----------------------*/,{ 1669 SCR_COPY (1), 1670 RADDR (scratcha), 1671 NADDR (msgout), 1672 SCR_SET (SCR_ATN), 1673 0, 1674}/*-------------------------< CLRACK >----------------------*/,{ 1675 /* 1676 ** Terminate possible pending message phase. 1677 */ 1678 SCR_CLR (SCR_ACK), 1679 0, 1680 1681}/*-----------------------< DISPATCH >----------------------*/,{ 1682 SCR_FROM_REG (HS_REG), 1683 0, 1684 SCR_INT ^ IFTRUE (DATA (HS_NEGOTIATE)), 1685 SIR_NEGO_FAILED, 1686 /* 1687 ** remove bogus output signals 1688 */ 1689 SCR_REG_REG (socl, SCR_AND, CACK|CATN), 1690 0, 1691 SCR_RETURN ^ IFTRUE (WHEN (SCR_DATA_OUT)), 1692 0, 1693 SCR_RETURN ^ IFTRUE (IF (SCR_DATA_IN)), 1694 0, 1695 SCR_JUMP ^ IFTRUE (IF (SCR_MSG_OUT)), 1696 PADDR (msg_out), 1697 SCR_JUMP ^ IFTRUE (IF (SCR_MSG_IN)), 1698 PADDR (msg_in), 1699 SCR_JUMP ^ IFTRUE (IF (SCR_COMMAND)), 1700 PADDR (command), 1701 SCR_JUMP ^ IFTRUE (IF (SCR_STATUS)), 1702 PADDR (status), 1703 /* 1704 ** Discard one illegal phase byte, if required. 1705 */ 1706 SCR_LOAD_REG (scratcha, XE_BAD_PHASE), 1707 0, 1708 SCR_COPY (1), 1709 RADDR (scratcha), 1710 NADDR (xerr_st), 1711 SCR_JUMPR ^ IFFALSE (IF (SCR_ILG_OUT)), 1712 8, 1713 SCR_MOVE_ABS (1) ^ SCR_ILG_OUT, 1714 NADDR (scratch), 1715 SCR_JUMPR ^ IFFALSE (IF (SCR_ILG_IN)), 1716 8, 1717 SCR_MOVE_ABS (1) ^ SCR_ILG_IN, 1718 NADDR (scratch), 1719 SCR_JUMP, 1720 PADDR (dispatch), 1721 1722}/*-------------------------< NO_DATA >--------------------*/,{ 1723 /* 1724 ** The target wants to tranfer too much data 1725 ** or in the wrong direction. 1726 ** Remember that in extended error. 1727 */ 1728 SCR_LOAD_REG (scratcha, XE_EXTRA_DATA), 1729 0, 1730 SCR_COPY (1), 1731 RADDR (scratcha), 1732 NADDR (xerr_st), 1733 /* 1734 ** Discard one data byte, if required. 1735 */ 1736 SCR_JUMPR ^ IFFALSE (WHEN (SCR_DATA_OUT)), 1737 8, 1738 SCR_MOVE_ABS (1) ^ SCR_DATA_OUT, 1739 NADDR (scratch), 1740 SCR_JUMPR ^ IFFALSE (IF (SCR_DATA_IN)), 1741 8, 1742 SCR_MOVE_ABS (1) ^ SCR_DATA_IN, 1743 NADDR (scratch), 1744 /* 1745 ** .. and repeat as required. 1746 */ 1747 SCR_CALL, 1748 PADDR (dispatch), 1749 SCR_JUMP, 1750 PADDR (no_data), 1751}/*-------------------------< CHECKATN >--------------------*/,{ 1752 /* 1753 ** If AAP (bit 1 of scntl0 register) is set 1754 ** and a parity error is detected, 1755 ** the script processor asserts ATN. 1756 ** 1757 ** The target should switch to a MSG_OUT phase 1758 ** to get the message. 1759 */ 1760 SCR_FROM_REG (socl), 1761 0, 1762 SCR_JUMP ^ IFFALSE (MASK (CATN, CATN)), 1763 PADDR (dispatch), 1764 /* 1765 ** count it 1766 */ 1767 SCR_REG_REG (PS_REG, SCR_ADD, 1), 1768 0, 1769 /* 1770 ** Prepare a MSG_INITIATOR_DET_ERR message 1771 ** (initiator detected error). 1772 ** The target should retry the transfer. 1773 */ 1774 SCR_LOAD_REG (scratcha, MSG_INITIATOR_DET_ERR), 1775 0, 1776 SCR_JUMP, 1777 PADDR (setmsg), 1778 1779}/*-------------------------< COMMAND >--------------------*/,{ 1780 /* 1781 ** If this is not a GETCC transfer ... 1782 */ 1783 SCR_FROM_REG (SS_REG), 1784 0, 1785/*<<<*/ SCR_JUMPR ^ IFTRUE (DATA (SCSI_STATUS_CHECK_COND)), 1786 28, 1787 /* 1788 ** ... set a timestamp ... 1789 */ 1790 SCR_COPY (sizeof (ticks)), 1791 KVAR (KVAR_TICKS), 1792 NADDR (header.stamp.command), 1793 /* 1794 ** ... and send the command 1795 */ 1796 SCR_MOVE_TBL ^ SCR_COMMAND, 1797 offsetof (struct dsb, cmd), 1798 SCR_JUMP, 1799 PADDR (dispatch), 1800 /* 1801 ** Send the GETCC command 1802 */ 1803/*>>>*/ SCR_MOVE_TBL ^ SCR_COMMAND, 1804 offsetof (struct dsb, scmd), 1805 SCR_JUMP, 1806 PADDR (dispatch), 1807 1808}/*-------------------------< STATUS >--------------------*/,{ 1809 /* 1810 ** set the timestamp. 1811 */ 1812 SCR_COPY (sizeof (ticks)), 1813 KVAR (KVAR_TICKS), 1814 NADDR (header.stamp.status), 1815 /* 1816 ** If this is a GETCC transfer, 1817 */ 1818 SCR_FROM_REG (SS_REG), 1819 0, 1820/*<<<*/ SCR_JUMPR ^ IFFALSE (DATA (SCSI_STATUS_CHECK_COND)), 1821 40, 1822 /* 1823 ** get the status 1824 */ 1825 SCR_MOVE_ABS (1) ^ SCR_STATUS, 1826 NADDR (scratch), 1827 /* 1828 ** Save status to scsi_status. 1829 ** Mark as complete. 1830 ** And wait for disconnect. 1831 */ 1832 SCR_TO_REG (SS_REG), 1833 0, 1834 SCR_REG_REG (SS_REG, SCR_OR, SCSI_STATUS_SENSE), 1835 0, 1836 SCR_LOAD_REG (HS_REG, HS_COMPLETE), 1837 0, 1838 SCR_JUMP, 1839 PADDR (checkatn), 1840 /* 1841 ** If it was no GETCC transfer, 1842 ** save the status to scsi_status. 1843 */ 1844/*>>>*/ SCR_MOVE_ABS (1) ^ SCR_STATUS, 1845 NADDR (scratch), 1846 SCR_TO_REG (SS_REG), 1847 0, 1848 /* 1849 ** if it was no check condition ... 1850 */ 1851 SCR_JUMP ^ IFTRUE (DATA (SCSI_STATUS_CHECK_COND)), 1852 PADDR (checkatn), 1853 /* 1854 ** ... mark as complete. 1855 */ 1856 SCR_LOAD_REG (HS_REG, HS_COMPLETE), 1857 0, 1858 SCR_JUMP, 1859 PADDR (checkatn), 1860 1861}/*-------------------------< MSG_IN >--------------------*/,{ 1862 /* 1863 ** Get the first byte of the message 1864 ** and save it to SCRATCHA. 1865 ** 1866 ** The script processor doesn't negate the 1867 ** ACK signal after this transfer. 1868 */ 1869 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 1870 NADDR (msgin[0]), 1871 /* 1872 ** Check for message parity error. 1873 */ 1874 SCR_TO_REG (scratcha), 1875 0, 1876 SCR_FROM_REG (socl), 1877 0, 1878 SCR_JUMP ^ IFTRUE (MASK (CATN, CATN)), 1879 PADDRH (msg_parity), 1880 SCR_FROM_REG (scratcha), 1881 0, 1882 /* 1883 ** Parity was ok, handle this message. 1884 */ 1885 SCR_JUMP ^ IFTRUE (DATA (MSG_CMDCOMPLETE)), 1886 PADDR (complete), 1887 SCR_JUMP ^ IFTRUE (DATA (MSG_SAVEDATAPOINTER)), 1888 PADDR (save_dp), 1889 SCR_JUMP ^ IFTRUE (DATA (MSG_RESTOREPOINTERS)), 1890 PADDR (restore_dp), 1891 SCR_JUMP ^ IFTRUE (DATA (MSG_DISCONNECT)), 1892 PADDR (disconnect), 1893 SCR_JUMP ^ IFTRUE (DATA (MSG_EXTENDED)), 1894 PADDRH (msg_extended), 1895 SCR_JUMP ^ IFTRUE (DATA (MSG_NOOP)), 1896 PADDR (clrack), 1897 SCR_JUMP ^ IFTRUE (DATA (MSG_MESSAGE_REJECT)), 1898 PADDRH (msg_reject), 1899 SCR_JUMP ^ IFTRUE (DATA (MSG_IGN_WIDE_RESIDUE)), 1900 PADDRH (msg_ign_residue), 1901 /* 1902 ** Rest of the messages left as 1903 ** an exercise ... 1904 ** 1905 ** Unimplemented messages: 1906 ** fall through to MSG_BAD. 1907 */ 1908}/*-------------------------< MSG_BAD >------------------*/,{ 1909 /* 1910 ** unimplemented message - reject it. 1911 */ 1912 SCR_INT, 1913 SIR_REJECT_SENT, 1914 SCR_LOAD_REG (scratcha, MSG_MESSAGE_REJECT), 1915 0, 1916 SCR_JUMP, 1917 PADDR (setmsg), 1918 1919}/*-------------------------< COMPLETE >-----------------*/,{ 1920 /* 1921 ** Complete message. 1922 ** 1923 ** If it's not the get condition code, 1924 ** copy TEMP register to LASTP in header. 1925 */ 1926 SCR_FROM_REG (SS_REG), 1927 0, 1928/*<<<*/ SCR_JUMPR ^ IFTRUE (MASK (SCSI_STATUS_SENSE, SCSI_STATUS_SENSE)), 1929 12, 1930 SCR_COPY (4), 1931 RADDR (temp), 1932 NADDR (header.lastp), 1933/*>>>*/ /* 1934 ** When we terminate the cycle by clearing ACK, 1935 ** the target may disconnect immediately. 1936 ** 1937 ** We don't want to be told of an 1938 ** "unexpected disconnect", 1939 ** so we disable this feature. 1940 */ 1941 SCR_REG_REG (scntl2, SCR_AND, 0x7f), 1942 0, 1943 /* 1944 ** Terminate cycle ... 1945 */ 1946 SCR_CLR (SCR_ACK|SCR_ATN), 1947 0, 1948 /* 1949 ** ... and wait for the disconnect. 1950 */ 1951 SCR_WAIT_DISC, 1952 0, 1953}/*-------------------------< CLEANUP >-------------------*/,{ 1954 /* 1955 ** dsa: Pointer to nccb 1956 ** or xxxxxxFF (no nccb) 1957 ** 1958 ** HS_REG: Host-Status (<>0!) 1959 */ 1960 SCR_FROM_REG (dsa), 1961 0, 1962 SCR_JUMP ^ IFTRUE (DATA (0xff)), 1963 PADDR (signal), 1964 /* 1965 ** dsa is valid. 1966 ** save the status registers 1967 */ 1968 SCR_COPY (4), 1969 RADDR (scr0), 1970 NADDR (header.status), 1971 /* 1972 ** and copy back the header to the nccb. 1973 */ 1974 SCR_COPY_F (4), 1975 RADDR (dsa), 1976 PADDR (cleanup0), 1977 SCR_COPY (sizeof (struct head)), 1978 NADDR (header), 1979}/*-------------------------< CLEANUP0 >--------------------*/,{ 1980 0, 1981 1982 /* 1983 ** If command resulted in "check condition" 1984 ** status and is not yet completed, 1985 ** try to get the condition code. 1986 */ 1987 SCR_FROM_REG (HS_REG), 1988 0, 1989/*<<<*/ SCR_JUMPR ^ IFFALSE (MASK (0, HS_DONEMASK)), 1990 16, 1991 SCR_FROM_REG (SS_REG), 1992 0, 1993 SCR_JUMP ^ IFTRUE (DATA (SCSI_STATUS_CHECK_COND)), 1994 PADDRH(getcc2), 1995}/*-------------------------< SIGNAL >----------------------*/,{ 1996 /* 1997 ** if status = queue full, 1998 ** reinsert in startqueue and stall queue. 1999 */ 2000/*>>>*/ SCR_FROM_REG (SS_REG), 2001 0, 2002 SCR_INT ^ IFTRUE (DATA (SCSI_STATUS_QUEUE_FULL)), 2003 SIR_STALL_QUEUE, 2004 /* 2005 ** And make the DSA register invalid. 2006 */ 2007 SCR_LOAD_REG (dsa, 0xff), /* invalid */ 2008 0, 2009 /* 2010 ** if job completed ... 2011 */ 2012 SCR_FROM_REG (HS_REG), 2013 0, 2014 /* 2015 ** ... signal completion to the host 2016 */ 2017 SCR_INT_FLY ^ IFFALSE (MASK (0, HS_DONEMASK)), 2018 0, 2019 /* 2020 ** Auf zu neuen Schandtaten! 2021 */ 2022 SCR_JUMP, 2023 PADDR(start), 2024 2025}/*-------------------------< SAVE_DP >------------------*/,{ 2026 /* 2027 ** SAVE_DP message: 2028 ** Copy TEMP register to SAVEP in header. 2029 */ 2030 SCR_COPY (4), 2031 RADDR (temp), 2032 NADDR (header.savep), 2033 SCR_JUMP, 2034 PADDR (clrack), 2035}/*-------------------------< RESTORE_DP >---------------*/,{ 2036 /* 2037 ** RESTORE_DP message: 2038 ** Copy SAVEP in header to TEMP register. 2039 */ 2040 SCR_COPY (4), 2041 NADDR (header.savep), 2042 RADDR (temp), 2043 SCR_JUMP, 2044 PADDR (clrack), 2045 2046}/*-------------------------< DISCONNECT >---------------*/,{ 2047 /* 2048 ** If QUIRK_AUTOSAVE is set, 2049 ** do a "save pointer" operation. 2050 */ 2051 SCR_FROM_REG (QU_REG), 2052 0, 2053/*<<<*/ SCR_JUMPR ^ IFFALSE (MASK (QUIRK_AUTOSAVE, QUIRK_AUTOSAVE)), 2054 12, 2055 /* 2056 ** like SAVE_DP message: 2057 ** Copy TEMP register to SAVEP in header. 2058 */ 2059 SCR_COPY (4), 2060 RADDR (temp), 2061 NADDR (header.savep), 2062/*>>>*/ /* 2063 ** Check if temp==savep or temp==goalp: 2064 ** if not, log a missing save pointer message. 2065 ** In fact, it's a comparison mod 256. 2066 ** 2067 ** Hmmm, I hadn't thought that I would be urged to 2068 ** write this kind of ugly self modifying code. 2069 ** 2070 ** It's unbelievable, but the ncr53c8xx isn't able 2071 ** to subtract one register from another. 2072 */ 2073 SCR_FROM_REG (temp), 2074 0, 2075 /* 2076 ** You are not expected to understand this .. 2077 ** 2078 ** CAUTION: only little endian architectures supported! XXX 2079 */ 2080 SCR_COPY_F (1), 2081 NADDR (header.savep), 2082 PADDR (disconnect0), 2083}/*-------------------------< DISCONNECT0 >--------------*/,{ 2084/*<<<*/ SCR_JUMPR ^ IFTRUE (DATA (1)), 2085 20, 2086 /* 2087 ** neither this 2088 */ 2089 SCR_COPY_F (1), 2090 NADDR (header.goalp), 2091 PADDR (disconnect1), 2092}/*-------------------------< DISCONNECT1 >--------------*/,{ 2093 SCR_INT ^ IFFALSE (DATA (1)), 2094 SIR_MISSING_SAVE, 2095/*>>>*/ 2096 2097 /* 2098 ** DISCONNECTing ... 2099 ** 2100 ** disable the "unexpected disconnect" feature, 2101 ** and remove the ACK signal. 2102 */ 2103 SCR_REG_REG (scntl2, SCR_AND, 0x7f), 2104 0, 2105 SCR_CLR (SCR_ACK|SCR_ATN), 2106 0, 2107 /* 2108 ** Wait for the disconnect. 2109 */ 2110 SCR_WAIT_DISC, 2111 0, 2112 /* 2113 ** Profiling: 2114 ** Set a time stamp, 2115 ** and count the disconnects. 2116 */ 2117 SCR_COPY (sizeof (ticks)), 2118 KVAR (KVAR_TICKS), 2119 NADDR (header.stamp.disconnect), 2120 SCR_COPY (4), 2121 NADDR (disc_phys), 2122 RADDR (temp), 2123 SCR_REG_REG (temp, SCR_ADD, 0x01), 2124 0, 2125 SCR_COPY (4), 2126 RADDR (temp), 2127 NADDR (disc_phys), 2128 /* 2129 ** Status is: DISCONNECTED. 2130 */ 2131 SCR_LOAD_REG (HS_REG, HS_DISCONNECT), 2132 0, 2133 SCR_JUMP, 2134 PADDR (cleanup), 2135 2136}/*-------------------------< MSG_OUT >-------------------*/,{ 2137 /* 2138 ** The target requests a message. 2139 */ 2140 SCR_MOVE_ABS (1) ^ SCR_MSG_OUT, 2141 NADDR (msgout), 2142 SCR_COPY (1), 2143 RADDR (sfbr), 2144 NADDR (lastmsg), 2145 /* 2146 ** If it was no ABORT message ... 2147 */ 2148 SCR_JUMP ^ IFTRUE (DATA (MSG_ABORT)), 2149 PADDRH (msg_out_abort), 2150 /* 2151 ** ... wait for the next phase 2152 ** if it's a message out, send it again, ... 2153 */ 2154 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_OUT)), 2155 PADDR (msg_out), 2156}/*-------------------------< MSG_OUT_DONE >--------------*/,{ 2157 /* 2158 ** ... else clear the message ... 2159 */ 2160 SCR_LOAD_REG (scratcha, MSG_NOOP), 2161 0, 2162 SCR_COPY (4), 2163 RADDR (scratcha), 2164 NADDR (msgout), 2165 /* 2166 ** ... and process the next phase 2167 */ 2168 SCR_JUMP, 2169 PADDR (dispatch), 2170 2171}/*------------------------< BADGETCC >---------------------*/,{ 2172 /* 2173 ** If SIGP was set, clear it and try again. 2174 */ 2175 SCR_FROM_REG (ctest2), 2176 0, 2177 SCR_JUMP ^ IFTRUE (MASK (CSIGP,CSIGP)), 2178 PADDRH (getcc2), 2179 SCR_INT, 2180 SIR_SENSE_FAILED, 2181}/*-------------------------< RESELECT >--------------------*/,{ 2182 /* 2183 ** This NOP will be patched with LED OFF 2184 ** SCR_REG_REG (gpreg, SCR_OR, 0x01) 2185 */ 2186 SCR_NO_OP, 2187 0, 2188 2189 /* 2190 ** make the DSA invalid. 2191 */ 2192 SCR_LOAD_REG (dsa, 0xff), 2193 0, 2194 SCR_CLR (SCR_TRG), 2195 0, 2196 /* 2197 ** Sleep waiting for a reselection. 2198 ** If SIGP is set, special treatment. 2199 ** 2200 ** Zu allem bereit .. 2201 */ 2202 SCR_WAIT_RESEL, 2203 PADDR(reselect2), 2204}/*-------------------------< RESELECT1 >--------------------*/,{ 2205 /* 2206 ** This NOP will be patched with LED ON 2207 ** SCR_REG_REG (gpreg, SCR_AND, 0xfe) 2208 */ 2209 SCR_NO_OP, 2210 0, 2211 /* 2212 ** ... zu nichts zu gebrauchen ? 2213 ** 2214 ** load the target id into the SFBR 2215 ** and jump to the control block. 2216 ** 2217 ** Look at the declarations of 2218 ** - struct ncb 2219 ** - struct tcb 2220 ** - struct lcb 2221 ** - struct nccb 2222 ** to understand what's going on. 2223 */ 2224 SCR_REG_SFBR (ssid, SCR_AND, 0x8F), 2225 0, 2226 SCR_TO_REG (sdid), 2227 0, 2228 SCR_JUMP, 2229 NADDR (jump_tcb), 2230}/*-------------------------< RESELECT2 >-------------------*/,{ 2231 /* 2232 ** This NOP will be patched with LED ON 2233 ** SCR_REG_REG (gpreg, SCR_AND, 0xfe) 2234 */ 2235 SCR_NO_OP, 2236 0, 2237 /* 2238 ** If it's not connected :( 2239 ** -> interrupted by SIGP bit. 2240 ** Jump to start. 2241 */ 2242 SCR_FROM_REG (ctest2), 2243 0, 2244 SCR_JUMP ^ IFTRUE (MASK (CSIGP,CSIGP)), 2245 PADDR (start), 2246 SCR_JUMP, 2247 PADDR (reselect), 2248 2249}/*-------------------------< RESEL_TMP >-------------------*/,{ 2250 /* 2251 ** The return address in TEMP 2252 ** is in fact the data structure address, 2253 ** so copy it to the DSA register. 2254 */ 2255 SCR_COPY (4), 2256 RADDR (temp), 2257 RADDR (dsa), 2258 SCR_JUMP, 2259 PADDR (prepare), 2260 2261}/*-------------------------< RESEL_LUN >-------------------*/,{ 2262 /* 2263 ** come back to this point 2264 ** to get an IDENTIFY message 2265 ** Wait for a msg_in phase. 2266 */ 2267/*<<<*/ SCR_JUMPR ^ IFFALSE (WHEN (SCR_MSG_IN)), 2268 48, 2269 /* 2270 ** message phase 2271 ** It's not a sony, it's a trick: 2272 ** read the data without acknowledging it. 2273 */ 2274 SCR_FROM_REG (sbdl), 2275 0, 2276/*<<<*/ SCR_JUMPR ^ IFFALSE (MASK (MSG_IDENTIFYFLAG, 0x98)), 2277 32, 2278 /* 2279 ** It WAS an Identify message. 2280 ** get it and ack it! 2281 */ 2282 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 2283 NADDR (msgin), 2284 SCR_CLR (SCR_ACK), 2285 0, 2286 /* 2287 ** Mask out the lun. 2288 */ 2289 SCR_REG_REG (sfbr, SCR_AND, 0x07), 2290 0, 2291 SCR_RETURN, 2292 0, 2293 /* 2294 ** No message phase or no IDENTIFY message: 2295 ** return 0. 2296 */ 2297/*>>>*/ SCR_LOAD_SFBR (0), 2298 0, 2299 SCR_RETURN, 2300 0, 2301 2302}/*-------------------------< RESEL_TAG >-------------------*/,{ 2303 /* 2304 ** come back to this point 2305 ** to get a SIMPLE_TAG message 2306 ** Wait for a MSG_IN phase. 2307 */ 2308/*<<<*/ SCR_JUMPR ^ IFFALSE (WHEN (SCR_MSG_IN)), 2309 64, 2310 /* 2311 ** message phase 2312 ** It's a trick - read the data 2313 ** without acknowledging it. 2314 */ 2315 SCR_FROM_REG (sbdl), 2316 0, 2317/*<<<*/ SCR_JUMPR ^ IFFALSE (DATA (MSG_SIMPLE_Q_TAG)), 2318 48, 2319 /* 2320 ** It WAS a SIMPLE_TAG message. 2321 ** get it and ack it! 2322 */ 2323 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 2324 NADDR (msgin), 2325 SCR_CLR (SCR_ACK), 2326 0, 2327 /* 2328 ** Wait for the second byte (the tag) 2329 */ 2330/*<<<*/ SCR_JUMPR ^ IFFALSE (WHEN (SCR_MSG_IN)), 2331 24, 2332 /* 2333 ** Get it and ack it! 2334 */ 2335 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 2336 NADDR (msgin), 2337 SCR_CLR (SCR_ACK|SCR_CARRY), 2338 0, 2339 SCR_RETURN, 2340 0, 2341 /* 2342 ** No message phase or no SIMPLE_TAG message 2343 ** or no second byte: return 0. 2344 */ 2345/*>>>*/ SCR_LOAD_SFBR (0), 2346 0, 2347 SCR_SET (SCR_CARRY), 2348 0, 2349 SCR_RETURN, 2350 0, 2351 2352}/*-------------------------< DATA_IN >--------------------*/,{ 2353/* 2354** Because the size depends on the 2355** #define MAX_SCATTER parameter, 2356** it is filled in at runtime. 2357** 2358** SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_IN)), 2359** PADDR (no_data), 2360** SCR_COPY (sizeof (ticks)), 2361** KVAR (KVAR_TICKS), 2362** NADDR (header.stamp.data), 2363** SCR_MOVE_TBL ^ SCR_DATA_IN, 2364** offsetof (struct dsb, data[ 0]), 2365** 2366** ##===========< i=1; i<MAX_SCATTER >========= 2367** || SCR_CALL ^ IFFALSE (WHEN (SCR_DATA_IN)), 2368** || PADDR (checkatn), 2369** || SCR_MOVE_TBL ^ SCR_DATA_IN, 2370** || offsetof (struct dsb, data[ i]), 2371** ##========================================== 2372** 2373** SCR_CALL, 2374** PADDR (checkatn), 2375** SCR_JUMP, 2376** PADDR (no_data), 2377*/ 23780 2379}/*-------------------------< DATA_OUT >-------------------*/,{ 2380/* 2381** Because the size depends on the 2382** #define MAX_SCATTER parameter, 2383** it is filled in at runtime. 2384** 2385** SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_OUT)), 2386** PADDR (no_data), 2387** SCR_COPY (sizeof (ticks)), 2388** KVAR (KVAR_TICKS), 2389** NADDR (header.stamp.data), 2390** SCR_MOVE_TBL ^ SCR_DATA_OUT, 2391** offsetof (struct dsb, data[ 0]), 2392** 2393** ##===========< i=1; i<MAX_SCATTER >========= 2394** || SCR_CALL ^ IFFALSE (WHEN (SCR_DATA_OUT)), 2395** || PADDR (dispatch), 2396** || SCR_MOVE_TBL ^ SCR_DATA_OUT, 2397** || offsetof (struct dsb, data[ i]), 2398** ##========================================== 2399** 2400** SCR_CALL, 2401** PADDR (dispatch), 2402** SCR_JUMP, 2403** PADDR (no_data), 2404** 2405**--------------------------------------------------------- 2406*/ 2407(u_long)0 2408 2409}/*--------------------------------------------------------*/ 2410}; 2411 2412 2413static struct scripth scripth0 = { 2414/*-------------------------< TRYLOOP >---------------------*/{ 2415/* 2416** Load an entry of the start queue into dsa 2417** and try to start it by jumping to TRYSEL. 2418** 2419** Because the size depends on the 2420** #define MAX_START parameter, it is filled 2421** in at runtime. 2422** 2423**----------------------------------------------------------- 2424** 2425** ##===========< I=0; i<MAX_START >=========== 2426** || SCR_COPY (4), 2427** || NADDR (squeue[i]), 2428** || RADDR (dsa), 2429** || SCR_CALL, 2430** || PADDR (trysel), 2431** ##========================================== 2432** 2433** SCR_JUMP, 2434** PADDRH(tryloop), 2435** 2436**----------------------------------------------------------- 2437*/ 24380 2439}/*-------------------------< MSG_PARITY >---------------*/,{ 2440 /* 2441 ** count it 2442 */ 2443 SCR_REG_REG (PS_REG, SCR_ADD, 0x01), 2444 0, 2445 /* 2446 ** send a "message parity error" message. 2447 */ 2448 SCR_LOAD_REG (scratcha, MSG_PARITY_ERROR), 2449 0, 2450 SCR_JUMP, 2451 PADDR (setmsg), 2452}/*-------------------------< MSG_MESSAGE_REJECT >---------------*/,{ 2453 /* 2454 ** If a negotiation was in progress, 2455 ** negotiation failed. 2456 */ 2457 SCR_FROM_REG (HS_REG), 2458 0, 2459 SCR_INT ^ IFTRUE (DATA (HS_NEGOTIATE)), 2460 SIR_NEGO_FAILED, 2461 /* 2462 ** else make host log this message 2463 */ 2464 SCR_INT ^ IFFALSE (DATA (HS_NEGOTIATE)), 2465 SIR_REJECT_RECEIVED, 2466 SCR_JUMP, 2467 PADDR (clrack), 2468 2469}/*-------------------------< MSG_IGN_RESIDUE >----------*/,{ 2470 /* 2471 ** Terminate cycle 2472 */ 2473 SCR_CLR (SCR_ACK), 2474 0, 2475 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)), 2476 PADDR (dispatch), 2477 /* 2478 ** get residue size. 2479 */ 2480 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 2481 NADDR (msgin[1]), 2482 /* 2483 ** Check for message parity error. 2484 */ 2485 SCR_TO_REG (scratcha), 2486 0, 2487 SCR_FROM_REG (socl), 2488 0, 2489 SCR_JUMP ^ IFTRUE (MASK (CATN, CATN)), 2490 PADDRH (msg_parity), 2491 SCR_FROM_REG (scratcha), 2492 0, 2493 /* 2494 ** Size is 0 .. ignore message. 2495 */ 2496 SCR_JUMP ^ IFTRUE (DATA (0)), 2497 PADDR (clrack), 2498 /* 2499 ** Size is not 1 .. have to interrupt. 2500 */ 2501/*<<<*/ SCR_JUMPR ^ IFFALSE (DATA (1)), 2502 40, 2503 /* 2504 ** Check for residue byte in swide register 2505 */ 2506 SCR_FROM_REG (scntl2), 2507 0, 2508/*<<<*/ SCR_JUMPR ^ IFFALSE (MASK (WSR, WSR)), 2509 16, 2510 /* 2511 ** There IS data in the swide register. 2512 ** Discard it. 2513 */ 2514 SCR_REG_REG (scntl2, SCR_OR, WSR), 2515 0, 2516 SCR_JUMP, 2517 PADDR (clrack), 2518 /* 2519 ** Load again the size to the sfbr register. 2520 */ 2521/*>>>*/ SCR_FROM_REG (scratcha), 2522 0, 2523/*>>>*/ SCR_INT, 2524 SIR_IGN_RESIDUE, 2525 SCR_JUMP, 2526 PADDR (clrack), 2527 2528}/*-------------------------< MSG_EXTENDED >-------------*/,{ 2529 /* 2530 ** Terminate cycle 2531 */ 2532 SCR_CLR (SCR_ACK), 2533 0, 2534 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)), 2535 PADDR (dispatch), 2536 /* 2537 ** get length. 2538 */ 2539 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 2540 NADDR (msgin[1]), 2541 /* 2542 ** Check for message parity error. 2543 */ 2544 SCR_TO_REG (scratcha), 2545 0, 2546 SCR_FROM_REG (socl), 2547 0, 2548 SCR_JUMP ^ IFTRUE (MASK (CATN, CATN)), 2549 PADDRH (msg_parity), 2550 SCR_FROM_REG (scratcha), 2551 0, 2552 /* 2553 */ 2554 SCR_JUMP ^ IFTRUE (DATA (3)), 2555 PADDRH (msg_ext_3), 2556 SCR_JUMP ^ IFFALSE (DATA (2)), 2557 PADDR (msg_bad), 2558}/*-------------------------< MSG_EXT_2 >----------------*/,{ 2559 SCR_CLR (SCR_ACK), 2560 0, 2561 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)), 2562 PADDR (dispatch), 2563 /* 2564 ** get extended message code. 2565 */ 2566 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 2567 NADDR (msgin[2]), 2568 /* 2569 ** Check for message parity error. 2570 */ 2571 SCR_TO_REG (scratcha), 2572 0, 2573 SCR_FROM_REG (socl), 2574 0, 2575 SCR_JUMP ^ IFTRUE (MASK (CATN, CATN)), 2576 PADDRH (msg_parity), 2577 SCR_FROM_REG (scratcha), 2578 0, 2579 SCR_JUMP ^ IFTRUE (DATA (MSG_EXT_WDTR)), 2580 PADDRH (msg_wdtr), 2581 /* 2582 ** unknown extended message 2583 */ 2584 SCR_JUMP, 2585 PADDR (msg_bad) 2586}/*-------------------------< MSG_WDTR >-----------------*/,{ 2587 SCR_CLR (SCR_ACK), 2588 0, 2589 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)), 2590 PADDR (dispatch), 2591 /* 2592 ** get data bus width 2593 */ 2594 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 2595 NADDR (msgin[3]), 2596 SCR_FROM_REG (socl), 2597 0, 2598 SCR_JUMP ^ IFTRUE (MASK (CATN, CATN)), 2599 PADDRH (msg_parity), 2600 /* 2601 ** let the host do the real work. 2602 */ 2603 SCR_INT, 2604 SIR_NEGO_WIDE, 2605 /* 2606 ** let the target fetch our answer. 2607 */ 2608 SCR_SET (SCR_ATN), 2609 0, 2610 SCR_CLR (SCR_ACK), 2611 0, 2612 2613 SCR_INT ^ IFFALSE (WHEN (SCR_MSG_OUT)), 2614 SIR_NEGO_PROTO, 2615 /* 2616 ** Send the MSG_EXT_WDTR 2617 */ 2618 SCR_MOVE_ABS (4) ^ SCR_MSG_OUT, 2619 NADDR (msgout), 2620 SCR_CLR (SCR_ATN), 2621 0, 2622 SCR_COPY (1), 2623 RADDR (sfbr), 2624 NADDR (lastmsg), 2625 SCR_JUMP, 2626 PADDR (msg_out_done), 2627 2628}/*-------------------------< MSG_EXT_3 >----------------*/,{ 2629 SCR_CLR (SCR_ACK), 2630 0, 2631 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)), 2632 PADDR (dispatch), 2633 /* 2634 ** get extended message code. 2635 */ 2636 SCR_MOVE_ABS (1) ^ SCR_MSG_IN, 2637 NADDR (msgin[2]), 2638 /* 2639 ** Check for message parity error. 2640 */ 2641 SCR_TO_REG (scratcha), 2642 0, 2643 SCR_FROM_REG (socl), 2644 0, 2645 SCR_JUMP ^ IFTRUE (MASK (CATN, CATN)), 2646 PADDRH (msg_parity), 2647 SCR_FROM_REG (scratcha), 2648 0, 2649 SCR_JUMP ^ IFTRUE (DATA (MSG_EXT_SDTR)), 2650 PADDRH (msg_sdtr), 2651 /* 2652 ** unknown extended message 2653 */ 2654 SCR_JUMP, 2655 PADDR (msg_bad) 2656 2657}/*-------------------------< MSG_SDTR >-----------------*/,{ 2658 SCR_CLR (SCR_ACK), 2659 0, 2660 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)), 2661 PADDR (dispatch), 2662 /* 2663 ** get period and offset 2664 */ 2665 SCR_MOVE_ABS (2) ^ SCR_MSG_IN, 2666 NADDR (msgin[3]), 2667 SCR_FROM_REG (socl), 2668 0, 2669 SCR_JUMP ^ IFTRUE (MASK (CATN, CATN)), 2670 PADDRH (msg_parity), 2671 /* 2672 ** let the host do the real work. 2673 */ 2674 SCR_INT, 2675 SIR_NEGO_SYNC, 2676 /* 2677 ** let the target fetch our answer. 2678 */ 2679 SCR_SET (SCR_ATN), 2680 0, 2681 SCR_CLR (SCR_ACK), 2682 0, 2683 2684 SCR_INT ^ IFFALSE (WHEN (SCR_MSG_OUT)), 2685 SIR_NEGO_PROTO, 2686 /* 2687 ** Send the MSG_EXT_SDTR 2688 */ 2689 SCR_MOVE_ABS (5) ^ SCR_MSG_OUT, 2690 NADDR (msgout), 2691 SCR_CLR (SCR_ATN), 2692 0, 2693 SCR_COPY (1), 2694 RADDR (sfbr), 2695 NADDR (lastmsg), 2696 SCR_JUMP, 2697 PADDR (msg_out_done), 2698 2699}/*-------------------------< MSG_OUT_ABORT >-------------*/,{ 2700 /* 2701 ** After ABORT message, 2702 ** 2703 ** expect an immediate disconnect, ... 2704 */ 2705 SCR_REG_REG (scntl2, SCR_AND, 0x7f), 2706 0, 2707 SCR_CLR (SCR_ACK|SCR_ATN), 2708 0, 2709 SCR_WAIT_DISC, 2710 0, 2711 /* 2712 ** ... and set the status to "ABORTED" 2713 */ 2714 SCR_LOAD_REG (HS_REG, HS_ABORTED), 2715 0, 2716 SCR_JUMP, 2717 PADDR (cleanup), 2718 2719}/*-------------------------< GETCC >-----------------------*/,{ 2720 /* 2721 ** The ncr doesn't have an indirect load 2722 ** or store command. So we have to 2723 ** copy part of the control block to a 2724 ** fixed place, where we can modify it. 2725 ** 2726 ** We patch the address part of a COPY command 2727 ** with the address of the dsa register ... 2728 */ 2729 SCR_COPY_F (4), 2730 RADDR (dsa), 2731 PADDRH (getcc1), 2732 /* 2733 ** ... then we do the actual copy. 2734 */ 2735 SCR_COPY (sizeof (struct head)), 2736}/*-------------------------< GETCC1 >----------------------*/,{ 2737 0, 2738 NADDR (header), 2739 /* 2740 ** Initialize the status registers 2741 */ 2742 SCR_COPY (4), 2743 NADDR (header.status), 2744 RADDR (scr0), 2745}/*-------------------------< GETCC2 >----------------------*/,{ 2746 /* 2747 ** Get the condition code from a target. 2748 ** 2749 ** DSA points to a data structure. 2750 ** Set TEMP to the script location 2751 ** that receives the condition code. 2752 ** 2753 ** Because there is no script command 2754 ** to load a longword into a register, 2755 ** we use a CALL command. 2756 */ 2757/*<<<*/ SCR_CALLR, 2758 24, 2759 /* 2760 ** Get the condition code. 2761 */ 2762 SCR_MOVE_TBL ^ SCR_DATA_IN, 2763 offsetof (struct dsb, sense), 2764 /* 2765 ** No data phase may follow! 2766 */ 2767 SCR_CALL, 2768 PADDR (checkatn), 2769 SCR_JUMP, 2770 PADDR (no_data), 2771/*>>>*/ 2772 2773 /* 2774 ** The CALL jumps to this point. 2775 ** Prepare for a RESTORE_POINTER message. 2776 ** Save the TEMP register into the saved pointer. 2777 */ 2778 SCR_COPY (4), 2779 RADDR (temp), 2780 NADDR (header.savep), 2781 /* 2782 ** Load scratcha, because in case of a selection timeout, 2783 ** the host will expect a new value for startpos in 2784 ** the scratcha register. 2785 */ 2786 SCR_COPY (4), 2787 PADDR (startpos), 2788 RADDR (scratcha), 2789#ifdef NCR_GETCC_WITHMSG 2790 /* 2791 ** If QUIRK_NOMSG is set, select without ATN. 2792 ** and don't send a message. 2793 */ 2794 SCR_FROM_REG (QU_REG), 2795 0, 2796 SCR_JUMP ^ IFTRUE (MASK (QUIRK_NOMSG, QUIRK_NOMSG)), 2797 PADDRH(getcc3), 2798 /* 2799 ** Then try to connect to the target. 2800 ** If we are reselected, special treatment 2801 ** of the current job is required before 2802 ** accepting the reselection. 2803 */ 2804 SCR_SEL_TBL_ATN ^ offsetof (struct dsb, select), 2805 PADDR(badgetcc), 2806 /* 2807 ** Send the IDENTIFY message. 2808 ** In case of short transfer, remove ATN. 2809 */ 2810 SCR_MOVE_TBL ^ SCR_MSG_OUT, 2811 offsetof (struct dsb, smsg2), 2812 SCR_CLR (SCR_ATN), 2813 0, 2814 /* 2815 ** save the first byte of the message. 2816 */ 2817 SCR_COPY (1), 2818 RADDR (sfbr), 2819 NADDR (lastmsg), 2820 SCR_JUMP, 2821 PADDR (prepare2), 2822 2823#endif 2824}/*-------------------------< GETCC3 >----------------------*/,{ 2825 /* 2826 ** Try to connect to the target. 2827 ** If we are reselected, special treatment 2828 ** of the current job is required before 2829 ** accepting the reselection. 2830 ** 2831 ** Silly target won't accept a message. 2832 ** Select without ATN. 2833 */ 2834 SCR_SEL_TBL ^ offsetof (struct dsb, select), 2835 PADDR(badgetcc), 2836 /* 2837 ** Force error if selection timeout 2838 */ 2839 SCR_JUMPR ^ IFTRUE (WHEN (SCR_MSG_IN)), 2840 0, 2841 /* 2842 ** don't negotiate. 2843 */ 2844 SCR_JUMP, 2845 PADDR (prepare2), 2846}/*-------------------------< ABORTTAG >-------------------*/,{ 2847 /* 2848 ** Abort a bad reselection. 2849 ** Set the message to ABORT vs. ABORT_TAG 2850 */ 2851 SCR_LOAD_REG (scratcha, MSG_ABORT_TAG), 2852 0, 2853 SCR_JUMPR ^ IFFALSE (CARRYSET), 2854 8, 2855}/*-------------------------< ABORT >----------------------*/,{ 2856 SCR_LOAD_REG (scratcha, MSG_ABORT), 2857 0, 2858 SCR_COPY (1), 2859 RADDR (scratcha), 2860 NADDR (msgout), 2861 SCR_SET (SCR_ATN), 2862 0, 2863 SCR_CLR (SCR_ACK), 2864 0, 2865 /* 2866 ** and send it. 2867 ** we expect an immediate disconnect 2868 */ 2869 SCR_REG_REG (scntl2, SCR_AND, 0x7f), 2870 0, 2871 SCR_MOVE_ABS (1) ^ SCR_MSG_OUT, 2872 NADDR (msgout), 2873 SCR_COPY (1), 2874 RADDR (sfbr), 2875 NADDR (lastmsg), 2876 SCR_CLR (SCR_ACK|SCR_ATN), 2877 0, 2878 SCR_WAIT_DISC, 2879 0, 2880 SCR_JUMP, 2881 PADDR (start), 2882}/*-------------------------< SNOOPTEST >-------------------*/,{ 2883 /* 2884 ** Read the variable. 2885 */ 2886 SCR_COPY (4), 2887 KVAR (KVAR_NCR_CACHE), 2888 RADDR (scratcha), 2889 /* 2890 ** Write the variable. 2891 */ 2892 SCR_COPY (4), 2893 RADDR (temp), 2894 KVAR (KVAR_NCR_CACHE), 2895 /* 2896 ** Read back the variable. 2897 */ 2898 SCR_COPY (4), 2899 KVAR (KVAR_NCR_CACHE), 2900 RADDR (temp), 2901}/*-------------------------< SNOOPEND >-------------------*/,{ 2902 /* 2903 ** And stop. 2904 */ 2905 SCR_INT, 2906 99, 2907}/*--------------------------------------------------------*/ 2908}; 2909 2910 2911/*========================================================== 2912** 2913** 2914** Fill in #define dependent parts of the script 2915** 2916** 2917**========================================================== 2918*/ 2919 2920static void ncr_script_fill (struct script * scr, struct scripth * scrh) 2921{ 2922 int i; 2923 ncrcmd *p; 2924 2925 p = scrh->tryloop; 2926 for (i=0; i<MAX_START; i++) { 2927 *p++ =SCR_COPY (4); 2928 *p++ =NADDR (squeue[i]); 2929 *p++ =RADDR (dsa); 2930 *p++ =SCR_CALL; 2931 *p++ =PADDR (trysel); 2932 }; 2933 *p++ =SCR_JUMP; 2934 *p++ =PADDRH(tryloop); 2935 2936 assert ((char *)p == (char *)&scrh->tryloop + sizeof (scrh->tryloop)); 2937 2938 p = scr->data_in; 2939 2940 *p++ =SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_IN)); 2941 *p++ =PADDR (no_data); 2942 *p++ =SCR_COPY (sizeof (ticks)); 2943 *p++ =(ncrcmd) KVAR (KVAR_TICKS); 2944 *p++ =NADDR (header.stamp.data); 2945 *p++ =SCR_MOVE_TBL ^ SCR_DATA_IN; 2946 *p++ =offsetof (struct dsb, data[ 0]); 2947 2948 for (i=1; i<MAX_SCATTER; i++) { 2949 *p++ =SCR_CALL ^ IFFALSE (WHEN (SCR_DATA_IN)); 2950 *p++ =PADDR (checkatn); 2951 *p++ =SCR_MOVE_TBL ^ SCR_DATA_IN; 2952 *p++ =offsetof (struct dsb, data[i]); 2953 }; 2954 2955 *p++ =SCR_CALL; 2956 *p++ =PADDR (checkatn); 2957 *p++ =SCR_JUMP; 2958 *p++ =PADDR (no_data); 2959 2960 assert ((char *)p == (char *)&scr->data_in + sizeof (scr->data_in)); 2961 2962 p = scr->data_out; 2963 2964 *p++ =SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_OUT)); 2965 *p++ =PADDR (no_data); 2966 *p++ =SCR_COPY (sizeof (ticks)); 2967 *p++ =(ncrcmd) KVAR (KVAR_TICKS); 2968 *p++ =NADDR (header.stamp.data); 2969 *p++ =SCR_MOVE_TBL ^ SCR_DATA_OUT; 2970 *p++ =offsetof (struct dsb, data[ 0]); 2971 2972 for (i=1; i<MAX_SCATTER; i++) { 2973 *p++ =SCR_CALL ^ IFFALSE (WHEN (SCR_DATA_OUT)); 2974 *p++ =PADDR (dispatch); 2975 *p++ =SCR_MOVE_TBL ^ SCR_DATA_OUT; 2976 *p++ =offsetof (struct dsb, data[i]); 2977 }; 2978 2979 *p++ =SCR_CALL; 2980 *p++ =PADDR (dispatch); 2981 *p++ =SCR_JUMP; 2982 *p++ =PADDR (no_data); 2983 2984 assert ((char *)p == (char *)&scr->data_out + sizeof (scr->data_out)); 2985} 2986 2987/*========================================================== 2988** 2989** 2990** Copy and rebind a script. 2991** 2992** 2993**========================================================== 2994*/ 2995 2996static void ncr_script_copy_and_bind (ncb_p np, ncrcmd *src, ncrcmd *dst, int len) 2997{ 2998 ncrcmd opcode, new, old, tmp1, tmp2; 2999 ncrcmd *start, *end; 3000 int relocs, offset; 3001 3002 start = src; 3003 end = src + len/4; 3004 offset = 0; 3005 3006 while (src < end) { 3007 3008 opcode = *src++; 3009 WRITESCRIPT_OFF(dst, offset, opcode); 3010 offset += 4; 3011 3012 /* 3013 ** If we forget to change the length 3014 ** in struct script, a field will be 3015 ** padded with 0. This is an illegal 3016 ** command. 3017 */ 3018 3019 if (opcode == 0) { 3020 printf ("%s: ERROR0 IN SCRIPT at %d.\n", 3021 ncr_name(np), (int) (src-start-1)); 3022 DELAY (1000000); 3023 }; 3024 3025 if (DEBUG_FLAGS & DEBUG_SCRIPT) 3026 printf ("%p: <%x>\n", 3027 (src-1), (unsigned)opcode); 3028 3029 /* 3030 ** We don't have to decode ALL commands 3031 */ 3032 switch (opcode >> 28) { 3033 3034 case 0xc: 3035 /* 3036 ** COPY has TWO arguments. 3037 */ 3038 relocs = 2; 3039 tmp1 = src[0]; 3040 if ((tmp1 & RELOC_MASK) == RELOC_KVAR) 3041 tmp1 = 0; 3042 tmp2 = src[1]; 3043 if ((tmp2 & RELOC_MASK) == RELOC_KVAR) 3044 tmp2 = 0; 3045 if ((tmp1 ^ tmp2) & 3) { 3046 printf ("%s: ERROR1 IN SCRIPT at %d.\n", 3047 ncr_name(np), (int) (src-start-1)); 3048 DELAY (1000000); 3049 } 3050 /* 3051 ** If PREFETCH feature not enabled, remove 3052 ** the NO FLUSH bit if present. 3053 */ 3054 if ((opcode & SCR_NO_FLUSH) && !(np->features&FE_PFEN)) 3055 WRITESCRIPT_OFF(dst, offset - 4, 3056 (opcode & ~SCR_NO_FLUSH)); 3057 break; 3058 3059 case 0x0: 3060 /* 3061 ** MOVE (absolute address) 3062 */ 3063 relocs = 1; 3064 break; 3065 3066 case 0x8: 3067 /* 3068 ** JUMP / CALL 3069 ** dont't relocate if relative :-) 3070 */ 3071 if (opcode & 0x00800000) 3072 relocs = 0; 3073 else 3074 relocs = 1; 3075 break; 3076 3077 case 0x4: 3078 case 0x5: 3079 case 0x6: 3080 case 0x7: 3081 relocs = 1; 3082 break; 3083 3084 default: 3085 relocs = 0; 3086 break; 3087 }; 3088 3089 if (relocs) { 3090 while (relocs--) { 3091 old = *src++; 3092 3093 switch (old & RELOC_MASK) { 3094 case RELOC_REGISTER: 3095 new = (old & ~RELOC_MASK) + rman_get_start(np->reg_res); 3096 break; 3097 case RELOC_LABEL: 3098 new = (old & ~RELOC_MASK) + np->p_script; 3099 break; 3100 case RELOC_LABELH: 3101 new = (old & ~RELOC_MASK) + np->p_scripth; 3102 break; 3103 case RELOC_SOFTC: 3104 new = (old & ~RELOC_MASK) + vtophys(np); 3105 break; 3106 case RELOC_KVAR: 3107 if (((old & ~RELOC_MASK) < 3108 SCRIPT_KVAR_FIRST) || 3109 ((old & ~RELOC_MASK) > 3110 SCRIPT_KVAR_LAST)) 3111 panic("ncr KVAR out of range"); 3112 new = vtophys(script_kvars[old & 3113 ~RELOC_MASK]); 3114 break; 3115 case 0: 3116 /* Don't relocate a 0 address. */ 3117 if (old == 0) { 3118 new = old; 3119 break; 3120 } 3121 /* FALLTHROUGH */ 3122 default: 3123 panic("ncr_script_copy_and_bind: weird relocation %x @ %d\n", old, (int)(src - start)); 3124 break; 3125 } 3126 3127 WRITESCRIPT_OFF(dst, offset, new); 3128 offset += 4; 3129 } 3130 } else { 3131 WRITESCRIPT_OFF(dst, offset, *src++); 3132 offset += 4; 3133 } 3134 3135 }; 3136} 3137 3138/*========================================================== 3139** 3140** 3141** Auto configuration. 3142** 3143** 3144**========================================================== 3145*/ 3146 3147#if 0 3148/*---------------------------------------------------------- 3149** 3150** Reduce the transfer length to the max value 3151** we can transfer safely. 3152** 3153** Reading a block greater then MAX_SIZE from the 3154** raw (character) device exercises a memory leak 3155** in the vm subsystem. This is common to ALL devices. 3156** We have submitted a description of this bug to 3157** <FreeBSD-bugs@freefall.cdrom.com>. 3158** It should be fixed in the current release. 3159** 3160**---------------------------------------------------------- 3161*/ 3162 3163void ncr_min_phys (struct buf *bp) 3164{ 3165 if ((unsigned long)bp->b_bcount > MAX_SIZE) bp->b_bcount = MAX_SIZE; 3166} 3167 3168#endif 3169 3170#if 0 3171/*---------------------------------------------------------- 3172** 3173** Maximal number of outstanding requests per target. 3174** 3175**---------------------------------------------------------- 3176*/ 3177 3178u_int32_t ncr_info (int unit) 3179{ 3180 return (1); /* may be changed later */ 3181} 3182 3183#endif 3184 3185/*---------------------------------------------------------- 3186** 3187** NCR chip devices table and chip look up function. 3188** Features bit are defined in ncrreg.h. Is it the 3189** right place? 3190** 3191**---------------------------------------------------------- 3192*/ 3193typedef struct { 3194 unsigned long device_id; 3195 unsigned short minrevid; 3196 char *name; 3197 unsigned char maxburst; 3198 unsigned char maxoffs; 3199 unsigned char clock_divn; 3200 unsigned int features; 3201} ncr_chip; 3202 3203static ncr_chip ncr_chip_table[] = { 3204 {NCR_810_ID, 0x00, "ncr 53c810 fast10 scsi", 4, 8, 4, 3205 FE_ERL} 3206 , 3207 {NCR_810_ID, 0x10, "ncr 53c810a fast10 scsi", 4, 8, 4, 3208 FE_ERL|FE_LDSTR|FE_PFEN|FE_BOF} 3209 , 3210 {NCR_815_ID, 0x00, "ncr 53c815 fast10 scsi", 4, 8, 4, 3211 FE_ERL|FE_BOF} 3212 , 3213 {NCR_820_ID, 0x00, "ncr 53c820 fast10 wide scsi", 4, 8, 4, 3214 FE_WIDE|FE_ERL} 3215 , 3216 {NCR_825_ID, 0x00, "ncr 53c825 fast10 wide scsi", 4, 8, 4, 3217 FE_WIDE|FE_ERL|FE_BOF} 3218 , 3219 {NCR_825_ID, 0x10, "ncr 53c825a fast10 wide scsi", 7, 8, 4, 3220 FE_WIDE|FE_CACHE_SET|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM} 3221 , 3222 {NCR_860_ID, 0x00, "ncr 53c860 fast20 scsi", 4, 8, 5, 3223 FE_ULTRA|FE_CLK80|FE_CACHE_SET|FE_LDSTR|FE_PFEN} 3224 , 3225 {NCR_875_ID, 0x00, "ncr 53c875 fast20 wide scsi", 7, 16, 5, 3226 FE_WIDE|FE_ULTRA|FE_CLK80|FE_CACHE_SET|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM} 3227 , 3228 {NCR_875_ID, 0x02, "ncr 53c875 fast20 wide scsi", 7, 16, 5, 3229 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE_SET|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM} 3230 , 3231 {NCR_875_ID2, 0x00, "ncr 53c875j fast20 wide scsi", 7, 16, 5, 3232 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE_SET|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM} 3233 , 3234 {NCR_885_ID, 0x00, "ncr 53c885 fast20 wide scsi", 7, 16, 5, 3235 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE_SET|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM} 3236 , 3237 {NCR_895_ID, 0x00, "ncr 53c895 fast40 wide scsi", 7, 31, 7, 3238 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM} 3239 , 3240 {NCR_896_ID, 0x00, "ncr 53c896 fast40 wide scsi", 7, 31, 7, 3241 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM} 3242 , 3243 {NCR_895A_ID, 0x00, "ncr 53c895a fast40 wide scsi", 7, 31, 7, 3244 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM} 3245 , 3246 {NCR_1510D_ID, 0x00, "ncr 53c1510d fast40 wide scsi", 7, 31, 7, 3247 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM} 3248}; 3249 3250static int ncr_chip_lookup(u_long device_id, u_char revision_id) 3251{ 3252 int i, found; 3253 3254 found = -1; 3255 for (i = 0; i < sizeof(ncr_chip_table)/sizeof(ncr_chip_table[0]); i++) { 3256 if (device_id == ncr_chip_table[i].device_id && 3257 ncr_chip_table[i].minrevid <= revision_id) { 3258 if (found < 0 || 3259 ncr_chip_table[found].minrevid 3260 < ncr_chip_table[i].minrevid) { 3261 found = i; 3262 } 3263 } 3264 } 3265 return found; 3266} 3267 3268/*---------------------------------------------------------- 3269** 3270** Probe the hostadapter. 3271** 3272**---------------------------------------------------------- 3273*/ 3274 3275 3276 3277static int ncr_probe (device_t dev) 3278{ 3279 int i; 3280 3281 i = ncr_chip_lookup(pci_get_devid(dev), pci_get_revid(dev)); 3282 if (i >= 0) { 3283 device_set_desc(dev, ncr_chip_table[i].name); 3284 return (BUS_PROBE_DEFAULT); 3285 } 3286 3287 return (ENXIO); 3288} 3289 3290 3291 3292/*========================================================== 3293** 3294** NCR chip clock divisor table. 3295** Divisors are multiplied by 10,000,000 in order to make 3296** calculations more simple. 3297** 3298**========================================================== 3299*/ 3300 3301#define _5M 5000000 3302static u_long div_10M[] = 3303 {2*_5M, 3*_5M, 4*_5M, 6*_5M, 8*_5M, 12*_5M, 16*_5M}; 3304 3305/*=============================================================== 3306** 3307** NCR chips allow burst lengths of 2, 4, 8, 16, 32, 64, 128 3308** transfers. 32,64,128 are only supported by 875 and 895 chips. 3309** We use log base 2 (burst length) as internal code, with 3310** value 0 meaning "burst disabled". 3311** 3312**=============================================================== 3313*/ 3314 3315/* 3316 * Burst length from burst code. 3317 */ 3318#define burst_length(bc) (!(bc))? 0 : 1 << (bc) 3319 3320/* 3321 * Burst code from io register bits. 3322 */ 3323#define burst_code(dmode, ctest4, ctest5) \ 3324 (ctest4) & 0x80? 0 : (((dmode) & 0xc0) >> 6) + ((ctest5) & 0x04) + 1 3325 3326/* 3327 * Set initial io register bits from burst code. 3328 */ 3329static void 3330ncr_init_burst(ncb_p np, u_char bc) 3331{ 3332 np->rv_ctest4 &= ~0x80; 3333 np->rv_dmode &= ~(0x3 << 6); 3334 np->rv_ctest5 &= ~0x4; 3335 3336 if (!bc) { 3337 np->rv_ctest4 |= 0x80; 3338 } 3339 else { 3340 --bc; 3341 np->rv_dmode |= ((bc & 0x3) << 6); 3342 np->rv_ctest5 |= (bc & 0x4); 3343 } 3344} 3345 3346/*========================================================== 3347** 3348** 3349** Auto configuration: attach and init a host adapter. 3350** 3351** 3352**========================================================== 3353*/ 3354 3355 3356static int 3357ncr_attach (device_t dev) 3358{ 3359 ncb_p np = (struct ncb*) device_get_softc(dev); 3360 u_char rev = 0; 3361 u_long period; 3362 int i, rid; 3363 u_int8_t usrsync; 3364 u_int8_t usrwide; 3365 struct cam_devq *devq; 3366 3367 /* 3368 ** allocate and initialize structures. 3369 */ 3370 3371 np->unit = device_get_unit(dev); 3372 3373 /* 3374 ** Try to map the controller chip to 3375 ** virtual and physical memory. 3376 */ 3377 3378 np->reg_rid = 0x14; 3379 np->reg_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 3380 &np->reg_rid, RF_ACTIVE); 3381 if (!np->reg_res) { 3382 device_printf(dev, "could not map memory\n"); 3383 return ENXIO; 3384 } 3385 3386 /* 3387 ** Make the controller's registers available. 3388 ** Now the INB INW INL OUTB OUTW OUTL macros 3389 ** can be used safely. 3390 */ 3391 3392 np->bst = rman_get_bustag(np->reg_res); 3393 np->bsh = rman_get_bushandle(np->reg_res); 3394 3395 3396#ifdef NCR_IOMAPPED 3397 /* 3398 ** Try to map the controller chip into iospace. 3399 */ 3400 3401 if (!pci_map_port (config_id, 0x10, &np->port)) 3402 return; 3403#endif 3404 3405 3406 /* 3407 ** Save some controller register default values 3408 */ 3409 3410 np->rv_scntl3 = INB(nc_scntl3) & 0x77; 3411 np->rv_dmode = INB(nc_dmode) & 0xce; 3412 np->rv_dcntl = INB(nc_dcntl) & 0xa9; 3413 np->rv_ctest3 = INB(nc_ctest3) & 0x01; 3414 np->rv_ctest4 = INB(nc_ctest4) & 0x88; 3415 np->rv_ctest5 = INB(nc_ctest5) & 0x24; 3416 np->rv_gpcntl = INB(nc_gpcntl); 3417 np->rv_stest2 = INB(nc_stest2) & 0x20; 3418 3419 if (bootverbose >= 2) { 3420 printf ("\tBIOS values: SCNTL3:%02x DMODE:%02x DCNTL:%02x\n", 3421 np->rv_scntl3, np->rv_dmode, np->rv_dcntl); 3422 printf ("\t CTEST3:%02x CTEST4:%02x CTEST5:%02x\n", 3423 np->rv_ctest3, np->rv_ctest4, np->rv_ctest5); 3424 } 3425 3426 np->rv_dcntl |= NOCOM; 3427 3428 /* 3429 ** Do chip dependent initialization. 3430 */ 3431 3432 rev = pci_get_revid(dev); 3433 3434 /* 3435 ** Get chip features from chips table. 3436 */ 3437 i = ncr_chip_lookup(pci_get_devid(dev), rev); 3438 3439 if (i >= 0) { 3440 np->maxburst = ncr_chip_table[i].maxburst; 3441 np->maxoffs = ncr_chip_table[i].maxoffs; 3442 np->clock_divn = ncr_chip_table[i].clock_divn; 3443 np->features = ncr_chip_table[i].features; 3444 } else { /* Should'nt happen if probe() is ok */ 3445 np->maxburst = 4; 3446 np->maxoffs = 8; 3447 np->clock_divn = 4; 3448 np->features = FE_ERL; 3449 } 3450 3451 np->maxwide = np->features & FE_WIDE ? 1 : 0; 3452 np->clock_khz = np->features & FE_CLK80 ? 80000 : 40000; 3453 if (np->features & FE_QUAD) np->multiplier = 4; 3454 else if (np->features & FE_DBLR) np->multiplier = 2; 3455 else np->multiplier = 1; 3456 3457 /* 3458 ** Get the frequency of the chip's clock. 3459 ** Find the right value for scntl3. 3460 */ 3461 if (np->features & (FE_ULTRA|FE_ULTRA2)) 3462 ncr_getclock(np, np->multiplier); 3463 3464#ifdef NCR_TEKRAM_EEPROM 3465 if (bootverbose) { 3466 printf ("%s: Tekram EEPROM read %s\n", 3467 ncr_name(np), 3468 read_tekram_eeprom (np, NULL) ? 3469 "succeeded" : "failed"); 3470 } 3471#endif /* NCR_TEKRAM_EEPROM */ 3472 3473 /* 3474 * If scntl3 != 0, we assume BIOS is present. 3475 */ 3476 if (np->rv_scntl3) 3477 np->features |= FE_BIOS; 3478 3479 /* 3480 * Divisor to be used for async (timer pre-scaler). 3481 */ 3482 i = np->clock_divn - 1; 3483 while (i >= 0) { 3484 --i; 3485 if (10ul * SCSI_NCR_MIN_ASYNC * np->clock_khz > div_10M[i]) { 3486 ++i; 3487 break; 3488 } 3489 } 3490 np->rv_scntl3 = i+1; 3491 3492 /* 3493 * Minimum synchronous period factor supported by the chip. 3494 * Btw, 'period' is in tenths of nanoseconds. 3495 */ 3496 3497 period = (4 * div_10M[0] + np->clock_khz - 1) / np->clock_khz; 3498 if (period <= 250) np->minsync = 10; 3499 else if (period <= 303) np->minsync = 11; 3500 else if (period <= 500) np->minsync = 12; 3501 else np->minsync = (period + 40 - 1) / 40; 3502 3503 /* 3504 * Check against chip SCSI standard support (SCSI-2,ULTRA,ULTRA2). 3505 */ 3506 3507 if (np->minsync < 25 && !(np->features & (FE_ULTRA|FE_ULTRA2))) 3508 np->minsync = 25; 3509 else if (np->minsync < 12 && !(np->features & FE_ULTRA2)) 3510 np->minsync = 12; 3511 3512 /* 3513 * Maximum synchronous period factor supported by the chip. 3514 */ 3515 3516 period = (11 * div_10M[np->clock_divn - 1]) / (4 * np->clock_khz); 3517 np->maxsync = period > 2540 ? 254 : period / 10; 3518 3519 /* 3520 * Now, some features available with Symbios compatible boards. 3521 * LED support through GPIO0 and DIFF support. 3522 */ 3523 3524#ifdef SCSI_NCR_SYMBIOS_COMPAT 3525 if (!(np->rv_gpcntl & 0x01)) 3526 np->features |= FE_LED0; 3527#if 0 /* Not safe enough without NVRAM support or user settable option */ 3528 if (!(INB(nc_gpreg) & 0x08)) 3529 np->features |= FE_DIFF; 3530#endif 3531#endif /* SCSI_NCR_SYMBIOS_COMPAT */ 3532 3533 /* 3534 * Prepare initial IO registers settings. 3535 * Trust BIOS only if we believe we have one and if we want to. 3536 */ 3537#ifdef SCSI_NCR_TRUST_BIOS 3538 if (!(np->features & FE_BIOS)) { 3539#else 3540 if (1) { 3541#endif 3542 np->rv_dmode = 0; 3543 np->rv_dcntl = NOCOM; 3544 np->rv_ctest3 = 0; 3545 np->rv_ctest4 = MPEE; 3546 np->rv_ctest5 = 0; 3547 np->rv_stest2 = 0; 3548 3549 if (np->features & FE_ERL) 3550 np->rv_dmode |= ERL; /* Enable Read Line */ 3551 if (np->features & FE_BOF) 3552 np->rv_dmode |= BOF; /* Burst Opcode Fetch */ 3553 if (np->features & FE_ERMP) 3554 np->rv_dmode |= ERMP; /* Enable Read Multiple */ 3555 if (np->features & FE_CLSE) 3556 np->rv_dcntl |= CLSE; /* Cache Line Size Enable */ 3557 if (np->features & FE_WRIE) 3558 np->rv_ctest3 |= WRIE; /* Write and Invalidate */ 3559 if (np->features & FE_PFEN) 3560 np->rv_dcntl |= PFEN; /* Prefetch Enable */ 3561 if (np->features & FE_DFS) 3562 np->rv_ctest5 |= DFS; /* Dma Fifo Size */ 3563 if (np->features & FE_DIFF) 3564 np->rv_stest2 |= 0x20; /* Differential mode */ 3565 ncr_init_burst(np, np->maxburst); /* Max dwords burst length */ 3566 } else { 3567 np->maxburst = 3568 burst_code(np->rv_dmode, np->rv_ctest4, np->rv_ctest5); 3569 } 3570 3571 /* 3572 ** Get on-chip SRAM address, if supported 3573 */ 3574 if ((np->features & FE_RAM) && sizeof(struct script) <= 4096) { 3575 np->sram_rid = 0x18; 3576 np->sram_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 3577 &np->sram_rid, 3578 RF_ACTIVE); 3579 } 3580 3581 /* 3582 ** Allocate structure for script relocation. 3583 */ 3584 if (np->sram_res != NULL) { 3585 np->script = NULL; 3586 np->p_script = rman_get_start(np->sram_res); 3587 np->bst2 = rman_get_bustag(np->sram_res); 3588 np->bsh2 = rman_get_bushandle(np->sram_res); 3589 } else if (sizeof (struct script) > PAGE_SIZE) { 3590 np->script = (struct script*) contigmalloc 3591 (round_page(sizeof (struct script)), M_DEVBUF, M_WAITOK, 3592 0, 0xffffffff, PAGE_SIZE, 0); 3593 } else { 3594 np->script = (struct script *) 3595 malloc (sizeof (struct script), M_DEVBUF, M_WAITOK); 3596 } 3597 3598 if (sizeof (struct scripth) > PAGE_SIZE) { 3599 np->scripth = (struct scripth*) contigmalloc 3600 (round_page(sizeof (struct scripth)), M_DEVBUF, M_WAITOK, 3601 0, 0xffffffff, PAGE_SIZE, 0); 3602 } else 3603 { 3604 np->scripth = (struct scripth *) 3605 malloc (sizeof (struct scripth), M_DEVBUF, M_WAITOK); 3606 } 3607 3608#ifdef SCSI_NCR_PCI_CONFIG_FIXUP 3609 /* 3610 ** If cache line size is enabled, check PCI config space and 3611 ** try to fix it up if necessary. 3612 */ 3613#ifdef PCIR_CACHELNSZ /* To be sure that new PCI stuff is present */ 3614 { 3615 u_char cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 3616 u_short command = pci_read_config(dev, PCIR_COMMAND, 2); 3617 3618 if (!cachelnsz) { 3619 cachelnsz = 8; 3620 printf("%s: setting PCI cache line size register to %d.\n", 3621 ncr_name(np), (int)cachelnsz); 3622 pci_write_config(dev, PCIR_CACHELNSZ, cachelnsz, 1); 3623 } 3624 3625 if (!(command & PCIM_CMD_MWRICEN)) { 3626 command |= PCIM_CMD_MWRICEN; 3627 printf("%s: setting PCI command write and invalidate.\n", 3628 ncr_name(np)); 3629 pci_write_config(dev, PCIR_COMMAND, command, 2); 3630 } 3631 } 3632#endif /* PCIR_CACHELNSZ */ 3633 3634#endif /* SCSI_NCR_PCI_CONFIG_FIXUP */ 3635 3636 /* Initialize per-target user settings */ 3637 usrsync = 0; 3638 if (SCSI_NCR_DFLT_SYNC) { 3639 usrsync = SCSI_NCR_DFLT_SYNC; 3640 if (usrsync > np->maxsync) 3641 usrsync = np->maxsync; 3642 if (usrsync < np->minsync) 3643 usrsync = np->minsync; 3644 }; 3645 3646 usrwide = (SCSI_NCR_MAX_WIDE); 3647 if (usrwide > np->maxwide) usrwide=np->maxwide; 3648 3649 for (i=0;i<MAX_TARGET;i++) { 3650 tcb_p tp = &np->target[i]; 3651 3652 tp->tinfo.user.period = usrsync; 3653 tp->tinfo.user.offset = usrsync != 0 ? np->maxoffs : 0; 3654 tp->tinfo.user.width = usrwide; 3655 tp->tinfo.disc_tag = NCR_CUR_DISCENB 3656 | NCR_CUR_TAGENB 3657 | NCR_USR_DISCENB 3658 | NCR_USR_TAGENB; 3659 } 3660 3661 /* 3662 ** Bells and whistles ;-) 3663 */ 3664 if (bootverbose) 3665 printf("%s: minsync=%d, maxsync=%d, maxoffs=%d, %d dwords burst, %s dma fifo\n", 3666 ncr_name(np), np->minsync, np->maxsync, np->maxoffs, 3667 burst_length(np->maxburst), 3668 (np->rv_ctest5 & DFS) ? "large" : "normal"); 3669 3670 /* 3671 ** Print some complementary information that can be helpfull. 3672 */ 3673 if (bootverbose) 3674 printf("%s: %s, %s IRQ driver%s\n", 3675 ncr_name(np), 3676 np->rv_stest2 & 0x20 ? "differential" : "single-ended", 3677 np->rv_dcntl & IRQM ? "totem pole" : "open drain", 3678 np->sram_res ? ", using on-chip SRAM" : ""); 3679 3680 /* 3681 ** Patch scripts to physical addresses 3682 */ 3683 ncr_script_fill (&script0, &scripth0); 3684 3685 if (np->script) 3686 np->p_script = vtophys(np->script); 3687 np->p_scripth = vtophys(np->scripth); 3688 3689 ncr_script_copy_and_bind (np, (ncrcmd *) &script0, 3690 (ncrcmd *) np->script, sizeof(struct script)); 3691 3692 ncr_script_copy_and_bind (np, (ncrcmd *) &scripth0, 3693 (ncrcmd *) np->scripth, sizeof(struct scripth)); 3694 3695 /* 3696 ** Patch the script for LED support. 3697 */ 3698 3699 if (np->features & FE_LED0) { 3700 WRITESCRIPT(reselect[0], SCR_REG_REG(gpreg, SCR_OR, 0x01)); 3701 WRITESCRIPT(reselect1[0], SCR_REG_REG(gpreg, SCR_AND, 0xfe)); 3702 WRITESCRIPT(reselect2[0], SCR_REG_REG(gpreg, SCR_AND, 0xfe)); 3703 } 3704 3705 /* 3706 ** init data structure 3707 */ 3708 3709 np->jump_tcb.l_cmd = SCR_JUMP; 3710 np->jump_tcb.l_paddr = NCB_SCRIPTH_PHYS (np, abort); 3711 3712 /* 3713 ** Get SCSI addr of host adapter (set by bios?). 3714 */ 3715 3716 np->myaddr = INB(nc_scid) & 0x07; 3717 if (!np->myaddr) np->myaddr = SCSI_NCR_MYADDR; 3718 3719#ifdef NCR_DUMP_REG 3720 /* 3721 ** Log the initial register contents 3722 */ 3723 { 3724 int reg; 3725 for (reg=0; reg<256; reg+=4) { 3726 if (reg%16==0) printf ("reg[%2x]", reg); 3727 printf (" %08x", (int)pci_conf_read (config_id, reg)); 3728 if (reg%16==12) printf ("\n"); 3729 } 3730 } 3731#endif /* NCR_DUMP_REG */ 3732 3733 /* 3734 ** Reset chip. 3735 */ 3736 3737 OUTB (nc_istat, SRST); 3738 DELAY (1000); 3739 OUTB (nc_istat, 0 ); 3740 3741 3742 /* 3743 ** Now check the cache handling of the pci chipset. 3744 */ 3745 3746 if (ncr_snooptest (np)) { 3747 printf ("CACHE INCORRECTLY CONFIGURED.\n"); 3748 return EINVAL; 3749 }; 3750 3751 /* 3752 ** Install the interrupt handler. 3753 */ 3754 3755 rid = 0; 3756 np->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 3757 RF_SHAREABLE | RF_ACTIVE); 3758 if (np->irq_res == NULL) { 3759 device_printf(dev, 3760 "interruptless mode: reduced performance.\n"); 3761 } else { 3762 bus_setup_intr(dev, np->irq_res, INTR_TYPE_CAM | INTR_ENTROPY, 3763 NULL, ncr_intr, np, &np->irq_handle); 3764 } 3765 3766 /* 3767 ** Create the device queue. We only allow MAX_START-1 concurrent 3768 ** transactions so we can be sure to have one element free in our 3769 ** start queue to reset to the idle loop. 3770 */ 3771 devq = cam_simq_alloc(MAX_START - 1); 3772 if (devq == NULL) 3773 return ENOMEM; 3774 3775 /* 3776 ** Now tell the generic SCSI layer 3777 ** about our bus. 3778 */ 3779 np->sim = cam_sim_alloc(ncr_action, ncr_poll, "ncr", np, np->unit, 3780 &Giant, 1, MAX_TAGS, devq); 3781 if (np->sim == NULL) { 3782 cam_simq_free(devq); 3783 return ENOMEM; 3784 } 3785 3786 3787 if (xpt_bus_register(np->sim, dev, 0) != CAM_SUCCESS) { 3788 cam_sim_free(np->sim, /*free_devq*/ TRUE); 3789 return ENOMEM; 3790 } 3791 3792 if (xpt_create_path(&np->path, /*periph*/NULL, 3793 cam_sim_path(np->sim), CAM_TARGET_WILDCARD, 3794 CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 3795 xpt_bus_deregister(cam_sim_path(np->sim)); 3796 cam_sim_free(np->sim, /*free_devq*/TRUE); 3797 return ENOMEM; 3798 } 3799 3800 /* 3801 ** start the timeout daemon 3802 */ 3803 ncr_timeout (np); 3804 np->lasttime=0; 3805 3806 return 0; 3807} 3808 3809/*========================================================== 3810** 3811** 3812** Process pending device interrupts. 3813** 3814** 3815**========================================================== 3816*/ 3817 3818static void 3819ncr_intr(vnp) 3820 void *vnp; 3821{ 3822 ncb_p np = vnp; 3823 int oldspl = splcam(); 3824 3825 if (DEBUG_FLAGS & DEBUG_TINY) printf ("["); 3826 3827 if (INB(nc_istat) & (INTF|SIP|DIP)) { 3828 /* 3829 ** Repeat until no outstanding ints 3830 */ 3831 do { 3832 ncr_exception (np); 3833 } while (INB(nc_istat) & (INTF|SIP|DIP)); 3834 3835 np->ticks = 100; 3836 }; 3837 3838 if (DEBUG_FLAGS & DEBUG_TINY) printf ("]\n"); 3839 3840 splx (oldspl); 3841} 3842 3843/*========================================================== 3844** 3845** 3846** Start execution of a SCSI command. 3847** This is called from the generic SCSI driver. 3848** 3849** 3850**========================================================== 3851*/ 3852 3853static void 3854ncr_action (struct cam_sim *sim, union ccb *ccb) 3855{ 3856 ncb_p np; 3857 3858 np = (ncb_p) cam_sim_softc(sim); 3859 3860 switch (ccb->ccb_h.func_code) { 3861 /* Common cases first */ 3862 case XPT_SCSI_IO: /* Execute the requested I/O operation */ 3863 { 3864 nccb_p cp; 3865 lcb_p lp; 3866 tcb_p tp; 3867 int oldspl; 3868 struct ccb_scsiio *csio; 3869 u_int8_t *msgptr; 3870 u_int msglen; 3871 u_int msglen2; 3872 int segments; 3873 u_int8_t nego; 3874 u_int8_t idmsg; 3875 int qidx; 3876 3877 tp = &np->target[ccb->ccb_h.target_id]; 3878 csio = &ccb->csio; 3879 3880 oldspl = splcam(); 3881 3882 /* 3883 * Last time we need to check if this CCB needs to 3884 * be aborted. 3885 */ 3886 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_INPROG) { 3887 xpt_done(ccb); 3888 splx(oldspl); 3889 return; 3890 } 3891 ccb->ccb_h.status |= CAM_SIM_QUEUED; 3892 3893 /*--------------------------------------------------- 3894 ** 3895 ** Assign an nccb / bind ccb 3896 ** 3897 **---------------------------------------------------- 3898 */ 3899 cp = ncr_get_nccb (np, ccb->ccb_h.target_id, 3900 ccb->ccb_h.target_lun); 3901 if (cp == NULL) { 3902 /* XXX JGibbs - Freeze SIMQ */ 3903 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 3904 xpt_done(ccb); 3905 return; 3906 }; 3907 3908 cp->ccb = ccb; 3909 3910 /*--------------------------------------------------- 3911 ** 3912 ** timestamp 3913 ** 3914 **---------------------------------------------------- 3915 */ 3916 /* 3917 ** XXX JGibbs - Isn't this expensive 3918 ** enough to be conditionalized?? 3919 */ 3920 3921 bzero (&cp->phys.header.stamp, sizeof (struct tstamp)); 3922 cp->phys.header.stamp.start = ticks; 3923 3924 nego = 0; 3925 if (tp->nego_cp == NULL) { 3926 3927 if (tp->tinfo.current.width 3928 != tp->tinfo.goal.width) { 3929 tp->nego_cp = cp; 3930 nego = NS_WIDE; 3931 } else if ((tp->tinfo.current.period 3932 != tp->tinfo.goal.period) 3933 || (tp->tinfo.current.offset 3934 != tp->tinfo.goal.offset)) { 3935 tp->nego_cp = cp; 3936 nego = NS_SYNC; 3937 }; 3938 }; 3939 3940 /*--------------------------------------------------- 3941 ** 3942 ** choose a new tag ... 3943 ** 3944 **---------------------------------------------------- 3945 */ 3946 lp = tp->lp[ccb->ccb_h.target_lun]; 3947 3948 if ((ccb->ccb_h.flags & CAM_TAG_ACTION_VALID) != 0 3949 && (ccb->csio.tag_action != CAM_TAG_ACTION_NONE) 3950 && (nego == 0)) { 3951 /* 3952 ** assign a tag to this nccb 3953 */ 3954 while (!cp->tag) { 3955 nccb_p cp2 = lp->next_nccb; 3956 lp->lasttag = lp->lasttag % 255 + 1; 3957 while (cp2 && cp2->tag != lp->lasttag) 3958 cp2 = cp2->next_nccb; 3959 if (cp2) continue; 3960 cp->tag=lp->lasttag; 3961 if (DEBUG_FLAGS & DEBUG_TAGS) { 3962 PRINT_ADDR(ccb); 3963 printf ("using tag #%d.\n", cp->tag); 3964 }; 3965 }; 3966 } else { 3967 cp->tag=0; 3968 }; 3969 3970 /*---------------------------------------------------- 3971 ** 3972 ** Build the identify / tag / sdtr message 3973 ** 3974 **---------------------------------------------------- 3975 */ 3976 idmsg = MSG_IDENTIFYFLAG | ccb->ccb_h.target_lun; 3977 if (tp->tinfo.disc_tag & NCR_CUR_DISCENB) 3978 idmsg |= MSG_IDENTIFY_DISCFLAG; 3979 3980 msgptr = cp->scsi_smsg; 3981 msglen = 0; 3982 msgptr[msglen++] = idmsg; 3983 3984 if (cp->tag) { 3985 msgptr[msglen++] = ccb->csio.tag_action; 3986 msgptr[msglen++] = cp->tag; 3987 } 3988 3989 switch (nego) { 3990 case NS_SYNC: 3991 msgptr[msglen++] = MSG_EXTENDED; 3992 msgptr[msglen++] = MSG_EXT_SDTR_LEN; 3993 msgptr[msglen++] = MSG_EXT_SDTR; 3994 msgptr[msglen++] = tp->tinfo.goal.period; 3995 msgptr[msglen++] = tp->tinfo.goal.offset; 3996 if (DEBUG_FLAGS & DEBUG_NEGO) { 3997 PRINT_ADDR(ccb); 3998 printf ("sync msgout: "); 3999 ncr_show_msg (&cp->scsi_smsg [msglen-5]); 4000 printf (".\n"); 4001 }; 4002 break; 4003 case NS_WIDE: 4004 msgptr[msglen++] = MSG_EXTENDED; 4005 msgptr[msglen++] = MSG_EXT_WDTR_LEN; 4006 msgptr[msglen++] = MSG_EXT_WDTR; 4007 msgptr[msglen++] = tp->tinfo.goal.width; 4008 if (DEBUG_FLAGS & DEBUG_NEGO) { 4009 PRINT_ADDR(ccb); 4010 printf ("wide msgout: "); 4011 ncr_show_msg (&cp->scsi_smsg [msglen-4]); 4012 printf (".\n"); 4013 }; 4014 break; 4015 }; 4016 4017 /*---------------------------------------------------- 4018 ** 4019 ** Build the identify message for getcc. 4020 ** 4021 **---------------------------------------------------- 4022 */ 4023 4024 cp->scsi_smsg2 [0] = idmsg; 4025 msglen2 = 1; 4026 4027 /*---------------------------------------------------- 4028 ** 4029 ** Build the data descriptors 4030 ** 4031 **---------------------------------------------------- 4032 */ 4033 4034 /* XXX JGibbs - Handle other types of I/O */ 4035 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 4036 segments = ncr_scatter(&cp->phys, 4037 (vm_offset_t)csio->data_ptr, 4038 (vm_size_t)csio->dxfer_len); 4039 4040 if (segments < 0) { 4041 ccb->ccb_h.status = CAM_REQ_TOO_BIG; 4042 ncr_free_nccb(np, cp); 4043 splx(oldspl); 4044 xpt_done(ccb); 4045 return; 4046 } 4047 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 4048 cp->phys.header.savep = NCB_SCRIPT_PHYS (np, data_in); 4049 cp->phys.header.goalp = cp->phys.header.savep +20 +segments*16; 4050 } else { /* CAM_DIR_OUT */ 4051 cp->phys.header.savep = NCB_SCRIPT_PHYS (np, data_out); 4052 cp->phys.header.goalp = cp->phys.header.savep +20 +segments*16; 4053 } 4054 } else { 4055 cp->phys.header.savep = NCB_SCRIPT_PHYS (np, no_data); 4056 cp->phys.header.goalp = cp->phys.header.savep; 4057 } 4058 4059 cp->phys.header.lastp = cp->phys.header.savep; 4060 4061 4062 /*---------------------------------------------------- 4063 ** 4064 ** fill in nccb 4065 ** 4066 **---------------------------------------------------- 4067 ** 4068 ** 4069 ** physical -> virtual backlink 4070 ** Generic SCSI command 4071 */ 4072 cp->phys.header.cp = cp; 4073 /* 4074 ** Startqueue 4075 */ 4076 cp->phys.header.launch.l_paddr = NCB_SCRIPT_PHYS (np, select); 4077 cp->phys.header.launch.l_cmd = SCR_JUMP; 4078 /* 4079 ** select 4080 */ 4081 cp->phys.select.sel_id = ccb->ccb_h.target_id; 4082 cp->phys.select.sel_scntl3 = tp->tinfo.wval; 4083 cp->phys.select.sel_sxfer = tp->tinfo.sval; 4084 /* 4085 ** message 4086 */ 4087 cp->phys.smsg.addr = CCB_PHYS (cp, scsi_smsg); 4088 cp->phys.smsg.size = msglen; 4089 4090 cp->phys.smsg2.addr = CCB_PHYS (cp, scsi_smsg2); 4091 cp->phys.smsg2.size = msglen2; 4092 /* 4093 ** command 4094 */ 4095 /* XXX JGibbs - Support other command types */ 4096 cp->phys.cmd.addr = vtophys (csio->cdb_io.cdb_bytes); 4097 cp->phys.cmd.size = csio->cdb_len; 4098 /* 4099 ** sense command 4100 */ 4101 cp->phys.scmd.addr = CCB_PHYS (cp, sensecmd); 4102 cp->phys.scmd.size = 6; 4103 /* 4104 ** patch requested size into sense command 4105 */ 4106 cp->sensecmd[0] = 0x03; 4107 cp->sensecmd[1] = ccb->ccb_h.target_lun << 5; 4108 cp->sensecmd[4] = sizeof(struct scsi_sense_data); 4109 cp->sensecmd[4] = csio->sense_len; 4110 /* 4111 ** sense data 4112 */ 4113 cp->phys.sense.addr = vtophys (&csio->sense_data); 4114 cp->phys.sense.size = csio->sense_len; 4115 /* 4116 ** status 4117 */ 4118 cp->actualquirks = QUIRK_NOMSG; 4119 cp->host_status = nego ? HS_NEGOTIATE : HS_BUSY; 4120 cp->s_status = SCSI_STATUS_ILLEGAL; 4121 cp->parity_status = 0; 4122 4123 cp->xerr_status = XE_OK; 4124 cp->sync_status = tp->tinfo.sval; 4125 cp->nego_status = nego; 4126 cp->wide_status = tp->tinfo.wval; 4127 4128 /*---------------------------------------------------- 4129 ** 4130 ** Critical region: start this job. 4131 ** 4132 **---------------------------------------------------- 4133 */ 4134 4135 /* 4136 ** reselect pattern and activate this job. 4137 */ 4138 4139 cp->jump_nccb.l_cmd = (SCR_JUMP ^ IFFALSE (DATA (cp->tag))); 4140 cp->tlimit = time_second 4141 + ccb->ccb_h.timeout / 1000 + 2; 4142 cp->magic = CCB_MAGIC; 4143 4144 /* 4145 ** insert into start queue. 4146 */ 4147 4148 qidx = np->squeueput + 1; 4149 if (qidx >= MAX_START) 4150 qidx = 0; 4151 np->squeue [qidx ] = NCB_SCRIPT_PHYS (np, idle); 4152 np->squeue [np->squeueput] = CCB_PHYS (cp, phys); 4153 np->squeueput = qidx; 4154 4155 if(DEBUG_FLAGS & DEBUG_QUEUE) 4156 printf("%s: queuepos=%d tryoffset=%d.\n", 4157 ncr_name (np), np->squeueput, 4158 (unsigned)(READSCRIPT(startpos[0]) - 4159 (NCB_SCRIPTH_PHYS (np, tryloop)))); 4160 4161 /* 4162 ** Script processor may be waiting for reselect. 4163 ** Wake it up. 4164 */ 4165 OUTB (nc_istat, SIGP); 4166 4167 /* 4168 ** and reenable interrupts 4169 */ 4170 splx (oldspl); 4171 break; 4172 } 4173 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 4174 case XPT_EN_LUN: /* Enable LUN as a target */ 4175 case XPT_TARGET_IO: /* Execute target I/O request */ 4176 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 4177 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/ 4178 case XPT_ABORT: /* Abort the specified CCB */ 4179 /* XXX Implement */ 4180 ccb->ccb_h.status = CAM_REQ_INVALID; 4181 xpt_done(ccb); 4182 break; 4183 case XPT_SET_TRAN_SETTINGS: 4184 { 4185 struct ccb_trans_settings *cts = &ccb->cts; 4186 tcb_p tp; 4187 u_int update_type; 4188 int s; 4189 struct ccb_trans_settings_scsi *scsi = 4190 &cts->proto_specific.scsi; 4191 struct ccb_trans_settings_spi *spi = 4192 &cts->xport_specific.spi; 4193 4194 update_type = 0; 4195 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 4196 update_type |= NCR_TRANS_GOAL; 4197 if (cts->type == CTS_TYPE_USER_SETTINGS) 4198 update_type |= NCR_TRANS_USER; 4199 4200 s = splcam(); 4201 tp = &np->target[ccb->ccb_h.target_id]; 4202 /* Tag and disc enables */ 4203 if ((spi->valid & CTS_SPI_VALID_DISC) != 0) { 4204 if (update_type & NCR_TRANS_GOAL) { 4205 if ((spi->flags & CTS_SPI_FLAGS_DISC_ENB) != 0) 4206 tp->tinfo.disc_tag |= NCR_CUR_DISCENB; 4207 else 4208 tp->tinfo.disc_tag &= ~NCR_CUR_DISCENB; 4209 } 4210 4211 if (update_type & NCR_TRANS_USER) { 4212 if ((spi->flags & CTS_SPI_FLAGS_DISC_ENB) != 0) 4213 tp->tinfo.disc_tag |= NCR_USR_DISCENB; 4214 else 4215 tp->tinfo.disc_tag &= ~NCR_USR_DISCENB; 4216 } 4217 4218 } 4219 4220 if ((scsi->valid & CTS_SCSI_VALID_TQ) != 0) { 4221 if (update_type & NCR_TRANS_GOAL) { 4222 if ((scsi->flags & CTS_SCSI_FLAGS_TAG_ENB) != 0) 4223 tp->tinfo.disc_tag |= NCR_CUR_TAGENB; 4224 else 4225 tp->tinfo.disc_tag &= ~NCR_CUR_TAGENB; 4226 } 4227 4228 if (update_type & NCR_TRANS_USER) { 4229 if ((scsi->flags & CTS_SCSI_FLAGS_TAG_ENB) != 0) 4230 tp->tinfo.disc_tag |= NCR_USR_TAGENB; 4231 else 4232 tp->tinfo.disc_tag &= ~NCR_USR_TAGENB; 4233 } 4234 } 4235 4236 /* Filter bus width and sync negotiation settings */ 4237 if ((spi->valid & CTS_SPI_VALID_BUS_WIDTH) != 0) { 4238 if (spi->bus_width > np->maxwide) 4239 spi->bus_width = np->maxwide; 4240 } 4241 4242 if (((spi->valid & CTS_SPI_VALID_SYNC_RATE) != 0) 4243 || ((spi->valid & CTS_SPI_VALID_SYNC_OFFSET) != 0)) { 4244 if ((spi->valid & CTS_SPI_VALID_SYNC_RATE) != 0) { 4245 if (spi->sync_period != 0 4246 && (spi->sync_period < np->minsync)) 4247 spi->sync_period = np->minsync; 4248 } 4249 if ((spi->valid & CTS_SPI_VALID_SYNC_OFFSET) != 0) { 4250 if (spi->sync_offset == 0) 4251 spi->sync_period = 0; 4252 if (spi->sync_offset > np->maxoffs) 4253 spi->sync_offset = np->maxoffs; 4254 } 4255 } 4256 if ((update_type & NCR_TRANS_USER) != 0) { 4257 if ((spi->valid & CTS_SPI_VALID_SYNC_RATE) != 0) 4258 tp->tinfo.user.period = spi->sync_period; 4259 if ((spi->valid & CTS_SPI_VALID_SYNC_OFFSET) != 0) 4260 tp->tinfo.user.offset = spi->sync_offset; 4261 if ((spi->valid & CTS_SPI_VALID_BUS_WIDTH) != 0) 4262 tp->tinfo.user.width = spi->bus_width; 4263 } 4264 if ((update_type & NCR_TRANS_GOAL) != 0) { 4265 if ((spi->valid & CTS_SPI_VALID_SYNC_RATE) != 0) 4266 tp->tinfo.goal.period = spi->sync_period; 4267 4268 if ((spi->valid & CTS_SPI_VALID_SYNC_OFFSET) != 0) 4269 tp->tinfo.goal.offset = spi->sync_offset; 4270 4271 if ((spi->valid & CTS_SPI_VALID_BUS_WIDTH) != 0) 4272 tp->tinfo.goal.width = spi->bus_width; 4273 } 4274 splx(s); 4275 ccb->ccb_h.status = CAM_REQ_CMP; 4276 xpt_done(ccb); 4277 break; 4278 } 4279 case XPT_GET_TRAN_SETTINGS: 4280 /* Get default/user set transfer settings for the target */ 4281 { 4282 struct ccb_trans_settings *cts = &ccb->cts; 4283 struct ncr_transinfo *tinfo; 4284 tcb_p tp = &np->target[ccb->ccb_h.target_id]; 4285 int s; 4286 struct ccb_trans_settings_scsi *scsi = 4287 &cts->proto_specific.scsi; 4288 struct ccb_trans_settings_spi *spi = 4289 &cts->xport_specific.spi; 4290 4291 cts->protocol = PROTO_SCSI; 4292 cts->protocol_version = SCSI_REV_2; 4293 cts->transport = XPORT_SPI; 4294 cts->transport_version = 2; 4295 4296 s = splcam(); 4297 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) { 4298 tinfo = &tp->tinfo.current; 4299 if (tp->tinfo.disc_tag & NCR_CUR_DISCENB) 4300 spi->flags |= CTS_SPI_FLAGS_DISC_ENB; 4301 else 4302 spi->flags &= ~CTS_SPI_FLAGS_DISC_ENB; 4303 4304 if (tp->tinfo.disc_tag & NCR_CUR_TAGENB) 4305 scsi->flags |= CTS_SCSI_FLAGS_TAG_ENB; 4306 else 4307 scsi->flags &= ~CTS_SCSI_FLAGS_TAG_ENB; 4308 } else { 4309 tinfo = &tp->tinfo.user; 4310 if (tp->tinfo.disc_tag & NCR_USR_DISCENB) 4311 spi->flags |= CTS_SPI_FLAGS_DISC_ENB; 4312 else 4313 spi->flags &= ~CTS_SPI_FLAGS_DISC_ENB; 4314 4315 if (tp->tinfo.disc_tag & NCR_USR_TAGENB) 4316 scsi->flags |= CTS_SCSI_FLAGS_TAG_ENB; 4317 else 4318 scsi->flags &= ~CTS_SCSI_FLAGS_TAG_ENB; 4319 } 4320 4321 spi->sync_period = tinfo->period; 4322 spi->sync_offset = tinfo->offset; 4323 spi->bus_width = tinfo->width; 4324 4325 splx(s); 4326 spi->valid = CTS_SPI_VALID_SYNC_RATE 4327 | CTS_SPI_VALID_SYNC_OFFSET 4328 | CTS_SPI_VALID_BUS_WIDTH 4329 | CTS_SPI_VALID_DISC; 4330 scsi->valid = CTS_SCSI_VALID_TQ; 4331 4332 ccb->ccb_h.status = CAM_REQ_CMP; 4333 xpt_done(ccb); 4334 break; 4335 } 4336 case XPT_CALC_GEOMETRY: 4337 { 4338 /* XXX JGibbs - I'm sure the NCR uses a different strategy, 4339 * but it should be able to deal with Adaptec 4340 * geometry too. 4341 */ 4342 cam_calc_geometry(&ccb->ccg, /*extended*/1); 4343 xpt_done(ccb); 4344 break; 4345 } 4346 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 4347 { 4348 OUTB (nc_scntl1, CRST); 4349 ccb->ccb_h.status = CAM_REQ_CMP; 4350 DELAY(10000); /* Wait until our interrupt handler sees it */ 4351 xpt_done(ccb); 4352 break; 4353 } 4354 case XPT_TERM_IO: /* Terminate the I/O process */ 4355 /* XXX Implement */ 4356 ccb->ccb_h.status = CAM_REQ_INVALID; 4357 xpt_done(ccb); 4358 break; 4359 case XPT_PATH_INQ: /* Path routing inquiry */ 4360 { 4361 struct ccb_pathinq *cpi = &ccb->cpi; 4362 4363 cpi->version_num = 1; /* XXX??? */ 4364 cpi->hba_inquiry = PI_SDTR_ABLE|PI_TAG_ABLE; 4365 if ((np->features & FE_WIDE) != 0) 4366 cpi->hba_inquiry |= PI_WIDE_16; 4367 cpi->target_sprt = 0; 4368 cpi->hba_misc = 0; 4369 cpi->hba_eng_cnt = 0; 4370 cpi->max_target = (np->features & FE_WIDE) ? 15 : 7; 4371 cpi->max_lun = MAX_LUN - 1; 4372 cpi->initiator_id = np->myaddr; 4373 cpi->bus_id = cam_sim_bus(sim); 4374 cpi->base_transfer_speed = 3300; 4375 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 4376 strncpy(cpi->hba_vid, "Symbios", HBA_IDLEN); 4377 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 4378 cpi->unit_number = cam_sim_unit(sim); 4379 cpi->transport = XPORT_SPI; 4380 cpi->transport_version = 2; 4381 cpi->protocol = PROTO_SCSI; 4382 cpi->protocol_version = SCSI_REV_2; 4383 cpi->ccb_h.status = CAM_REQ_CMP; 4384 xpt_done(ccb); 4385 break; 4386 } 4387 default: 4388 ccb->ccb_h.status = CAM_REQ_INVALID; 4389 xpt_done(ccb); 4390 break; 4391 } 4392} 4393 4394/*========================================================== 4395** 4396** 4397** Complete execution of a SCSI command. 4398** Signal completion to the generic SCSI driver. 4399** 4400** 4401**========================================================== 4402*/ 4403 4404static void 4405ncr_complete (ncb_p np, nccb_p cp) 4406{ 4407 union ccb *ccb; 4408 tcb_p tp; 4409 4410 /* 4411 ** Sanity check 4412 */ 4413 4414 if (!cp || (cp->magic!=CCB_MAGIC) || !cp->ccb) return; 4415 cp->magic = 1; 4416 cp->tlimit= 0; 4417 4418 /* 4419 ** No Reselect anymore. 4420 */ 4421 cp->jump_nccb.l_cmd = (SCR_JUMP); 4422 4423 /* 4424 ** No starting. 4425 */ 4426 cp->phys.header.launch.l_paddr= NCB_SCRIPT_PHYS (np, idle); 4427 4428 /* 4429 ** timestamp 4430 */ 4431 ncb_profile (np, cp); 4432 4433 if (DEBUG_FLAGS & DEBUG_TINY) 4434 printf ("CCB=%x STAT=%x/%x\n", (int)(intptr_t)cp & 0xfff, 4435 cp->host_status,cp->s_status); 4436 4437 ccb = cp->ccb; 4438 cp->ccb = NULL; 4439 tp = &np->target[ccb->ccb_h.target_id]; 4440 4441 /* 4442 ** We do not queue more than 1 nccb per target 4443 ** with negotiation at any time. If this nccb was 4444 ** used for negotiation, clear this info in the tcb. 4445 */ 4446 4447 if (cp == tp->nego_cp) 4448 tp->nego_cp = NULL; 4449 4450 /* 4451 ** Check for parity errors. 4452 */ 4453 /* XXX JGibbs - What about reporting them??? */ 4454 4455 if (cp->parity_status) { 4456 PRINT_ADDR(ccb); 4457 printf ("%d parity error(s), fallback.\n", cp->parity_status); 4458 /* 4459 ** fallback to asynch transfer. 4460 */ 4461 tp->tinfo.goal.period = 0; 4462 tp->tinfo.goal.offset = 0; 4463 }; 4464 4465 /* 4466 ** Check for extended errors. 4467 */ 4468 4469 if (cp->xerr_status != XE_OK) { 4470 PRINT_ADDR(ccb); 4471 switch (cp->xerr_status) { 4472 case XE_EXTRA_DATA: 4473 printf ("extraneous data discarded.\n"); 4474 break; 4475 case XE_BAD_PHASE: 4476 printf ("illegal scsi phase (4/5).\n"); 4477 break; 4478 default: 4479 printf ("extended error %d.\n", cp->xerr_status); 4480 break; 4481 }; 4482 if (cp->host_status==HS_COMPLETE) 4483 cp->host_status = HS_FAIL; 4484 }; 4485 4486 /* 4487 ** Check the status. 4488 */ 4489 if (cp->host_status == HS_COMPLETE) { 4490 4491 if (cp->s_status == SCSI_STATUS_OK) { 4492 4493 /* 4494 ** All went well. 4495 */ 4496 /* XXX JGibbs - Properly calculate residual */ 4497 4498 tp->bytes += ccb->csio.dxfer_len; 4499 tp->transfers ++; 4500 4501 ccb->ccb_h.status = CAM_REQ_CMP; 4502 } else if ((cp->s_status & SCSI_STATUS_SENSE) != 0) { 4503 4504 /* 4505 * XXX Could be TERMIO too. Should record 4506 * original status. 4507 */ 4508 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 4509 cp->s_status &= ~SCSI_STATUS_SENSE; 4510 if (cp->s_status == SCSI_STATUS_OK) { 4511 ccb->ccb_h.status = 4512 CAM_AUTOSNS_VALID|CAM_SCSI_STATUS_ERROR; 4513 } else { 4514 ccb->ccb_h.status = CAM_AUTOSENSE_FAIL; 4515 } 4516 } else { 4517 ccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; 4518 ccb->csio.scsi_status = cp->s_status; 4519 } 4520 4521 4522 } else if (cp->host_status == HS_SEL_TIMEOUT) { 4523 4524 /* 4525 ** Device failed selection 4526 */ 4527 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 4528 4529 } else if (cp->host_status == HS_TIMEOUT) { 4530 4531 /* 4532 ** No response 4533 */ 4534 ccb->ccb_h.status = CAM_CMD_TIMEOUT; 4535 } else if (cp->host_status == HS_STALL) { 4536 ccb->ccb_h.status = CAM_REQUEUE_REQ; 4537 } else { 4538 4539 /* 4540 ** Other protocol messes 4541 */ 4542 PRINT_ADDR(ccb); 4543 printf ("COMMAND FAILED (%x %x) @%p.\n", 4544 cp->host_status, cp->s_status, cp); 4545 4546 ccb->ccb_h.status = CAM_CMD_TIMEOUT; 4547 } 4548 4549 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP) { 4550 xpt_freeze_devq(ccb->ccb_h.path, /*count*/1); 4551 ccb->ccb_h.status |= CAM_DEV_QFRZN; 4552 } 4553 4554 /* 4555 ** Free this nccb 4556 */ 4557 ncr_free_nccb (np, cp); 4558 4559 /* 4560 ** signal completion to generic driver. 4561 */ 4562 xpt_done (ccb); 4563} 4564 4565/*========================================================== 4566** 4567** 4568** Signal all (or one) control block done. 4569** 4570** 4571**========================================================== 4572*/ 4573 4574static void 4575ncr_wakeup (ncb_p np, u_long code) 4576{ 4577 /* 4578 ** Starting at the default nccb and following 4579 ** the links, complete all jobs with a 4580 ** host_status greater than "disconnect". 4581 ** 4582 ** If the "code" parameter is not zero, 4583 ** complete all jobs that are not IDLE. 4584 */ 4585 4586 nccb_p cp = np->link_nccb; 4587 while (cp) { 4588 switch (cp->host_status) { 4589 4590 case HS_IDLE: 4591 break; 4592 4593 case HS_DISCONNECT: 4594 if(DEBUG_FLAGS & DEBUG_TINY) printf ("D"); 4595 /* FALLTHROUGH */ 4596 4597 case HS_BUSY: 4598 case HS_NEGOTIATE: 4599 if (!code) break; 4600 cp->host_status = code; 4601 4602 /* FALLTHROUGH */ 4603 4604 default: 4605 ncr_complete (np, cp); 4606 break; 4607 }; 4608 cp = cp -> link_nccb; 4609 }; 4610} 4611 4612static void 4613ncr_freeze_devq (ncb_p np, struct cam_path *path) 4614{ 4615 nccb_p cp; 4616 int i; 4617 int count; 4618 int firstskip; 4619 /* 4620 ** Starting at the first nccb and following 4621 ** the links, complete all jobs that match 4622 ** the passed in path and are in the start queue. 4623 */ 4624 4625 cp = np->link_nccb; 4626 count = 0; 4627 firstskip = 0; 4628 while (cp) { 4629 switch (cp->host_status) { 4630 4631 case HS_BUSY: 4632 case HS_NEGOTIATE: 4633 if ((cp->phys.header.launch.l_paddr 4634 == NCB_SCRIPT_PHYS (np, select)) 4635 && (xpt_path_comp(path, cp->ccb->ccb_h.path) >= 0)) { 4636 4637 /* Mark for removal from the start queue */ 4638 for (i = 1; i < MAX_START; i++) { 4639 int idx; 4640 4641 idx = np->squeueput - i; 4642 4643 if (idx < 0) 4644 idx = MAX_START + idx; 4645 if (np->squeue[idx] 4646 == CCB_PHYS(cp, phys)) { 4647 np->squeue[idx] = 4648 NCB_SCRIPT_PHYS (np, skip); 4649 if (i > firstskip) 4650 firstskip = i; 4651 break; 4652 } 4653 } 4654 cp->host_status=HS_STALL; 4655 ncr_complete (np, cp); 4656 count++; 4657 } 4658 break; 4659 default: 4660 break; 4661 } 4662 cp = cp->link_nccb; 4663 } 4664 4665 if (count > 0) { 4666 int j; 4667 int bidx; 4668 4669 /* Compress the start queue */ 4670 j = 0; 4671 bidx = np->squeueput; 4672 i = np->squeueput - firstskip; 4673 if (i < 0) 4674 i = MAX_START + i; 4675 for (;;) { 4676 4677 bidx = i - j; 4678 if (bidx < 0) 4679 bidx = MAX_START + bidx; 4680 4681 if (np->squeue[i] == NCB_SCRIPT_PHYS (np, skip)) { 4682 j++; 4683 } else if (j != 0) { 4684 np->squeue[bidx] = np->squeue[i]; 4685 if (np->squeue[bidx] 4686 == NCB_SCRIPT_PHYS(np, idle)) 4687 break; 4688 } 4689 i = (i + 1) % MAX_START; 4690 } 4691 np->squeueput = bidx; 4692 } 4693} 4694 4695/*========================================================== 4696** 4697** 4698** Start NCR chip. 4699** 4700** 4701**========================================================== 4702*/ 4703 4704static void 4705ncr_init(ncb_p np, char * msg, u_long code) 4706{ 4707 int i; 4708 4709 /* 4710 ** Reset chip. 4711 */ 4712 4713 OUTB (nc_istat, SRST); 4714 DELAY (1000); 4715 OUTB (nc_istat, 0); 4716 4717 /* 4718 ** Message. 4719 */ 4720 4721 if (msg) printf ("%s: restart (%s).\n", ncr_name (np), msg); 4722 4723 /* 4724 ** Clear Start Queue 4725 */ 4726 4727 for (i=0;i<MAX_START;i++) 4728 np -> squeue [i] = NCB_SCRIPT_PHYS (np, idle); 4729 4730 /* 4731 ** Start at first entry. 4732 */ 4733 4734 np->squeueput = 0; 4735 WRITESCRIPT(startpos[0], NCB_SCRIPTH_PHYS (np, tryloop)); 4736 WRITESCRIPT(start0 [0], SCR_INT ^ IFFALSE (0)); 4737 4738 /* 4739 ** Wakeup all pending jobs. 4740 */ 4741 4742 ncr_wakeup (np, code); 4743 4744 /* 4745 ** Init chip. 4746 */ 4747 4748 OUTB (nc_istat, 0x00 ); /* Remove Reset, abort ... */ 4749 OUTB (nc_scntl0, 0xca ); /* full arb., ena parity, par->ATN */ 4750 OUTB (nc_scntl1, 0x00 ); /* odd parity, and remove CRST!! */ 4751 ncr_selectclock(np, np->rv_scntl3); /* Select SCSI clock */ 4752 OUTB (nc_scid , RRE|np->myaddr);/* host adapter SCSI address */ 4753 OUTW (nc_respid, 1ul<<np->myaddr);/* id to respond to */ 4754 OUTB (nc_istat , SIGP ); /* Signal Process */ 4755 OUTB (nc_dmode , np->rv_dmode); /* XXX modify burstlen ??? */ 4756 OUTB (nc_dcntl , np->rv_dcntl); 4757 OUTB (nc_ctest3, np->rv_ctest3); 4758 OUTB (nc_ctest5, np->rv_ctest5); 4759 OUTB (nc_ctest4, np->rv_ctest4);/* enable master parity checking */ 4760 OUTB (nc_stest2, np->rv_stest2|EXT); /* Extended Sreq/Sack filtering */ 4761 OUTB (nc_stest3, TE ); /* TolerANT enable */ 4762 OUTB (nc_stime0, 0x0b ); /* HTH = disabled, STO = 0.1 sec. */ 4763 4764 if (bootverbose >= 2) { 4765 printf ("\tACTUAL values:SCNTL3:%02x DMODE:%02x DCNTL:%02x\n", 4766 np->rv_scntl3, np->rv_dmode, np->rv_dcntl); 4767 printf ("\t CTEST3:%02x CTEST4:%02x CTEST5:%02x\n", 4768 np->rv_ctest3, np->rv_ctest4, np->rv_ctest5); 4769 } 4770 4771 /* 4772 ** Enable GPIO0 pin for writing if LED support. 4773 */ 4774 4775 if (np->features & FE_LED0) { 4776 OUTOFFB (nc_gpcntl, 0x01); 4777 } 4778 4779 /* 4780 ** Fill in target structure. 4781 */ 4782 for (i=0;i<MAX_TARGET;i++) { 4783 tcb_p tp = &np->target[i]; 4784 4785 tp->tinfo.sval = 0; 4786 tp->tinfo.wval = np->rv_scntl3; 4787 4788 tp->tinfo.current.period = 0; 4789 tp->tinfo.current.offset = 0; 4790 tp->tinfo.current.width = MSG_EXT_WDTR_BUS_8_BIT; 4791 } 4792 4793 /* 4794 ** enable ints 4795 */ 4796 4797 OUTW (nc_sien , STO|HTH|MA|SGE|UDC|RST); 4798 OUTB (nc_dien , MDPE|BF|ABRT|SSI|SIR|IID); 4799 4800 /* 4801 ** Start script processor. 4802 */ 4803 4804 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, start)); 4805 4806 /* 4807 * Notify the XPT of the event 4808 */ 4809 if (code == HS_RESET) 4810 xpt_async(AC_BUS_RESET, np->path, NULL); 4811} 4812 4813static void 4814ncr_poll(struct cam_sim *sim) 4815{ 4816 ncr_intr(cam_sim_softc(sim)); 4817} 4818 4819 4820/*========================================================== 4821** 4822** Get clock factor and sync divisor for a given 4823** synchronous factor period. 4824** Returns the clock factor (in sxfer) and scntl3 4825** synchronous divisor field. 4826** 4827**========================================================== 4828*/ 4829 4830static void ncr_getsync(ncb_p np, u_char sfac, u_char *fakp, u_char *scntl3p) 4831{ 4832 u_long clk = np->clock_khz; /* SCSI clock frequency in kHz */ 4833 int div = np->clock_divn; /* Number of divisors supported */ 4834 u_long fak; /* Sync factor in sxfer */ 4835 u_long per; /* Period in tenths of ns */ 4836 u_long kpc; /* (per * clk) */ 4837 4838 /* 4839 ** Compute the synchronous period in tenths of nano-seconds 4840 */ 4841 if (sfac <= 10) per = 250; 4842 else if (sfac == 11) per = 303; 4843 else if (sfac == 12) per = 500; 4844 else per = 40 * sfac; 4845 4846 /* 4847 ** Look for the greatest clock divisor that allows an 4848 ** input speed faster than the period. 4849 */ 4850 kpc = per * clk; 4851 while (--div >= 0) 4852 if (kpc >= (div_10M[div] * 4)) break; 4853 4854 /* 4855 ** Calculate the lowest clock factor that allows an output 4856 ** speed not faster than the period. 4857 */ 4858 fak = (kpc - 1) / div_10M[div] + 1; 4859 4860#if 0 /* You can #if 1 if you think this optimization is useful */ 4861 4862 per = (fak * div_10M[div]) / clk; 4863 4864 /* 4865 ** Why not to try the immediate lower divisor and to choose 4866 ** the one that allows the fastest output speed ? 4867 ** We dont want input speed too much greater than output speed. 4868 */ 4869 if (div >= 1 && fak < 6) { 4870 u_long fak2, per2; 4871 fak2 = (kpc - 1) / div_10M[div-1] + 1; 4872 per2 = (fak2 * div_10M[div-1]) / clk; 4873 if (per2 < per && fak2 <= 6) { 4874 fak = fak2; 4875 per = per2; 4876 --div; 4877 } 4878 } 4879#endif 4880 4881 if (fak < 4) fak = 4; /* Should never happen, too bad ... */ 4882 4883 /* 4884 ** Compute and return sync parameters for the ncr 4885 */ 4886 *fakp = fak - 4; 4887 *scntl3p = ((div+1) << 4) + (sfac < 25 ? 0x80 : 0); 4888} 4889 4890/*========================================================== 4891** 4892** Switch sync mode for current job and its target 4893** 4894**========================================================== 4895*/ 4896 4897static void 4898ncr_setsync(ncb_p np, nccb_p cp, u_char scntl3, u_char sxfer, u_char period) 4899{ 4900 union ccb *ccb; 4901 struct ccb_trans_settings neg; 4902 tcb_p tp; 4903 int div; 4904 u_int target = INB (nc_sdid) & 0x0f; 4905 u_int period_10ns; 4906 4907 assert (cp); 4908 if (!cp) return; 4909 4910 ccb = cp->ccb; 4911 assert (ccb); 4912 if (!ccb) return; 4913 assert (target == ccb->ccb_h.target_id); 4914 4915 tp = &np->target[target]; 4916 4917 if (!scntl3 || !(sxfer & 0x1f)) 4918 scntl3 = np->rv_scntl3; 4919 scntl3 = (scntl3 & 0xf0) | (tp->tinfo.wval & EWS) 4920 | (np->rv_scntl3 & 0x07); 4921 4922 /* 4923 ** Deduce the value of controller sync period from scntl3. 4924 ** period is in tenths of nano-seconds. 4925 */ 4926 4927 div = ((scntl3 >> 4) & 0x7); 4928 if ((sxfer & 0x1f) && div) 4929 period_10ns = 4930 (((sxfer>>5)+4)*div_10M[div-1])/np->clock_khz; 4931 else 4932 period_10ns = 0; 4933 4934 tp->tinfo.goal.period = period; 4935 tp->tinfo.goal.offset = sxfer & 0x1f; 4936 tp->tinfo.current.period = period; 4937 tp->tinfo.current.offset = sxfer & 0x1f; 4938 4939 /* 4940 ** Stop there if sync parameters are unchanged 4941 */ 4942 if (tp->tinfo.sval == sxfer && tp->tinfo.wval == scntl3) return; 4943 tp->tinfo.sval = sxfer; 4944 tp->tinfo.wval = scntl3; 4945 4946 if (sxfer & 0x1f) { 4947 /* 4948 ** Disable extended Sreq/Sack filtering 4949 */ 4950 if (period_10ns <= 2000) OUTOFFB (nc_stest2, EXT); 4951 } 4952 4953 /* 4954 ** Tell the SCSI layer about the 4955 ** new transfer parameters. 4956 */ 4957 memset(&neg, 0, sizeof (neg)); 4958 neg.protocol = PROTO_SCSI; 4959 neg.protocol_version = SCSI_REV_2; 4960 neg.transport = XPORT_SPI; 4961 neg.transport_version = 2; 4962 neg.xport_specific.spi.sync_period = period; 4963 neg.xport_specific.spi.sync_offset = sxfer & 0x1f; 4964 neg.xport_specific.spi.valid = CTS_SPI_VALID_SYNC_RATE 4965 | CTS_SPI_VALID_SYNC_OFFSET; 4966 xpt_setup_ccb(&neg.ccb_h, ccb->ccb_h.path, 4967 /*priority*/1); 4968 xpt_async(AC_TRANSFER_NEG, ccb->ccb_h.path, &neg); 4969 4970 /* 4971 ** set actual value and sync_status 4972 */ 4973 OUTB (nc_sxfer, sxfer); 4974 np->sync_st = sxfer; 4975 OUTB (nc_scntl3, scntl3); 4976 np->wide_st = scntl3; 4977 4978 /* 4979 ** patch ALL nccbs of this target. 4980 */ 4981 for (cp = np->link_nccb; cp; cp = cp->link_nccb) { 4982 if (!cp->ccb) continue; 4983 if (cp->ccb->ccb_h.target_id != target) continue; 4984 cp->sync_status = sxfer; 4985 cp->wide_status = scntl3; 4986 }; 4987} 4988 4989/*========================================================== 4990** 4991** Switch wide mode for current job and its target 4992** SCSI specs say: a SCSI device that accepts a WDTR 4993** message shall reset the synchronous agreement to 4994** asynchronous mode. 4995** 4996**========================================================== 4997*/ 4998 4999static void ncr_setwide (ncb_p np, nccb_p cp, u_char wide, u_char ack) 5000{ 5001 union ccb *ccb; 5002 struct ccb_trans_settings neg; 5003 u_int target = INB (nc_sdid) & 0x0f; 5004 tcb_p tp; 5005 u_char scntl3; 5006 u_char sxfer; 5007 5008 assert (cp); 5009 if (!cp) return; 5010 5011 ccb = cp->ccb; 5012 assert (ccb); 5013 if (!ccb) return; 5014 assert (target == ccb->ccb_h.target_id); 5015 5016 tp = &np->target[target]; 5017 tp->tinfo.current.width = wide; 5018 tp->tinfo.goal.width = wide; 5019 tp->tinfo.current.period = 0; 5020 tp->tinfo.current.offset = 0; 5021 5022 scntl3 = (tp->tinfo.wval & (~EWS)) | (wide ? EWS : 0); 5023 5024 sxfer = ack ? 0 : tp->tinfo.sval; 5025 5026 /* 5027 ** Stop there if sync/wide parameters are unchanged 5028 */ 5029 if (tp->tinfo.sval == sxfer && tp->tinfo.wval == scntl3) return; 5030 tp->tinfo.sval = sxfer; 5031 tp->tinfo.wval = scntl3; 5032 5033 /* Tell the SCSI layer about the new transfer params */ 5034 memset(&neg, 0, sizeof (neg)); 5035 neg.protocol = PROTO_SCSI; 5036 neg.protocol_version = SCSI_REV_2; 5037 neg.transport = XPORT_SPI; 5038 neg.transport_version = 2; 5039 neg.xport_specific.spi.bus_width = (scntl3 & EWS) ? 5040 MSG_EXT_WDTR_BUS_16_BIT : MSG_EXT_WDTR_BUS_8_BIT; 5041 neg.xport_specific.spi.sync_period = 0; 5042 neg.xport_specific.spi.sync_offset = 0; 5043 neg.xport_specific.spi.valid = CTS_SPI_VALID_SYNC_RATE 5044 | CTS_SPI_VALID_SYNC_OFFSET 5045 | CTS_SPI_VALID_BUS_WIDTH; 5046 xpt_setup_ccb(&neg.ccb_h, ccb->ccb_h.path, /*priority*/1); 5047 xpt_async(AC_TRANSFER_NEG, ccb->ccb_h.path, &neg); 5048 5049 /* 5050 ** set actual value and sync_status 5051 */ 5052 OUTB (nc_sxfer, sxfer); 5053 np->sync_st = sxfer; 5054 OUTB (nc_scntl3, scntl3); 5055 np->wide_st = scntl3; 5056 5057 /* 5058 ** patch ALL nccbs of this target. 5059 */ 5060 for (cp = np->link_nccb; cp; cp = cp->link_nccb) { 5061 if (!cp->ccb) continue; 5062 if (cp->ccb->ccb_h.target_id != target) continue; 5063 cp->sync_status = sxfer; 5064 cp->wide_status = scntl3; 5065 }; 5066} 5067 5068/*========================================================== 5069** 5070** 5071** ncr timeout handler. 5072** 5073** 5074**========================================================== 5075** 5076** Misused to keep the driver running when 5077** interrupts are not configured correctly. 5078** 5079**---------------------------------------------------------- 5080*/ 5081 5082static void 5083ncr_timeout (void *arg) 5084{ 5085 ncb_p np = arg; 5086 time_t thistime = time_second; 5087 ticks_t step = np->ticks; 5088 u_long count = 0; 5089 long signed t; 5090 nccb_p cp; 5091 5092 if (np->lasttime != thistime) { 5093 /* 5094 ** block ncr interrupts 5095 */ 5096 int oldspl = splcam(); 5097 np->lasttime = thistime; 5098 5099 /*---------------------------------------------------- 5100 ** 5101 ** handle ncr chip timeouts 5102 ** 5103 ** Assumption: 5104 ** We have a chance to arbitrate for the 5105 ** SCSI bus at least every 10 seconds. 5106 ** 5107 **---------------------------------------------------- 5108 */ 5109 5110 t = thistime - np->heartbeat; 5111 5112 if (t<2) np->latetime=0; else np->latetime++; 5113 5114 if (np->latetime>2) { 5115 /* 5116 ** If there are no requests, the script 5117 ** processor will sleep on SEL_WAIT_RESEL. 5118 ** But we have to check whether it died. 5119 ** Let's try to wake it up. 5120 */ 5121 OUTB (nc_istat, SIGP); 5122 }; 5123 5124 /*---------------------------------------------------- 5125 ** 5126 ** handle nccb timeouts 5127 ** 5128 **---------------------------------------------------- 5129 */ 5130 5131 for (cp=np->link_nccb; cp; cp=cp->link_nccb) { 5132 /* 5133 ** look for timed out nccbs. 5134 */ 5135 if (!cp->host_status) continue; 5136 count++; 5137 if (cp->tlimit > thistime) continue; 5138 5139 /* 5140 ** Disable reselect. 5141 ** Remove it from startqueue. 5142 */ 5143 cp->jump_nccb.l_cmd = (SCR_JUMP); 5144 if (cp->phys.header.launch.l_paddr == 5145 NCB_SCRIPT_PHYS (np, select)) { 5146 printf ("%s: timeout nccb=%p (skip)\n", 5147 ncr_name (np), cp); 5148 cp->phys.header.launch.l_paddr 5149 = NCB_SCRIPT_PHYS (np, skip); 5150 }; 5151 5152 switch (cp->host_status) { 5153 5154 case HS_BUSY: 5155 case HS_NEGOTIATE: 5156 /* FALLTHROUGH */ 5157 case HS_DISCONNECT: 5158 cp->host_status=HS_TIMEOUT; 5159 }; 5160 cp->tag = 0; 5161 5162 /* 5163 ** wakeup this nccb. 5164 */ 5165 ncr_complete (np, cp); 5166 }; 5167 splx (oldspl); 5168 } 5169 5170 np->timeout_ch = 5171 timeout (ncr_timeout, (caddr_t) np, step ? step : 1); 5172 5173 if (INB(nc_istat) & (INTF|SIP|DIP)) { 5174 5175 /* 5176 ** Process pending interrupts. 5177 */ 5178 5179 int oldspl = splcam(); 5180 if (DEBUG_FLAGS & DEBUG_TINY) printf ("{"); 5181 ncr_exception (np); 5182 if (DEBUG_FLAGS & DEBUG_TINY) printf ("}"); 5183 splx (oldspl); 5184 }; 5185} 5186 5187/*========================================================== 5188** 5189** log message for real hard errors 5190** 5191** "ncr0 targ 0?: ERROR (ds:si) (so-si-sd) (sxfer/scntl3) @ name (dsp:dbc)." 5192** " reg: r0 r1 r2 r3 r4 r5 r6 ..... rf." 5193** 5194** exception register: 5195** ds: dstat 5196** si: sist 5197** 5198** SCSI bus lines: 5199** so: control lines as driver by NCR. 5200** si: control lines as seen by NCR. 5201** sd: scsi data lines as seen by NCR. 5202** 5203** wide/fastmode: 5204** sxfer: (see the manual) 5205** scntl3: (see the manual) 5206** 5207** current script command: 5208** dsp: script address (relative to start of script). 5209** dbc: first word of script command. 5210** 5211** First 16 register of the chip: 5212** r0..rf 5213** 5214**========================================================== 5215*/ 5216 5217static void ncr_log_hard_error(ncb_p np, u_short sist, u_char dstat) 5218{ 5219 u_int32_t dsp; 5220 int script_ofs; 5221 int script_size; 5222 char *script_name; 5223 u_char *script_base; 5224 int i; 5225 5226 dsp = INL (nc_dsp); 5227 5228 if (np->p_script < dsp && 5229 dsp <= np->p_script + sizeof(struct script)) { 5230 script_ofs = dsp - np->p_script; 5231 script_size = sizeof(struct script); 5232 script_base = (u_char *) np->script; 5233 script_name = "script"; 5234 } 5235 else if (np->p_scripth < dsp && 5236 dsp <= np->p_scripth + sizeof(struct scripth)) { 5237 script_ofs = dsp - np->p_scripth; 5238 script_size = sizeof(struct scripth); 5239 script_base = (u_char *) np->scripth; 5240 script_name = "scripth"; 5241 } else { 5242 script_ofs = dsp; 5243 script_size = 0; 5244 script_base = 0; 5245 script_name = "mem"; 5246 } 5247 5248 printf ("%s:%d: ERROR (%x:%x) (%x-%x-%x) (%x/%x) @ (%s %x:%08x).\n", 5249 ncr_name (np), (unsigned)INB (nc_sdid)&0x0f, dstat, sist, 5250 (unsigned)INB (nc_socl), (unsigned)INB (nc_sbcl), (unsigned)INB (nc_sbdl), 5251 (unsigned)INB (nc_sxfer),(unsigned)INB (nc_scntl3), script_name, script_ofs, 5252 (unsigned)INL (nc_dbc)); 5253 5254 if (((script_ofs & 3) == 0) && 5255 (unsigned)script_ofs < script_size) { 5256 printf ("%s: script cmd = %08x\n", ncr_name(np), 5257 (int)READSCRIPT_OFF(script_base, script_ofs)); 5258 } 5259 5260 printf ("%s: regdump:", ncr_name(np)); 5261 for (i=0; i<16;i++) 5262 printf (" %02x", (unsigned)INB_OFF(i)); 5263 printf (".\n"); 5264} 5265 5266/*========================================================== 5267** 5268** 5269** ncr chip exception handler. 5270** 5271** 5272**========================================================== 5273*/ 5274 5275static void ncr_exception (ncb_p np) 5276{ 5277 u_char istat, dstat; 5278 u_short sist; 5279 5280 /* 5281 ** interrupt on the fly ? 5282 */ 5283 while ((istat = INB (nc_istat)) & INTF) { 5284 if (DEBUG_FLAGS & DEBUG_TINY) printf ("F "); 5285 OUTB (nc_istat, INTF); 5286 np->profile.num_fly++; 5287 ncr_wakeup (np, 0); 5288 }; 5289 if (!(istat & (SIP|DIP))) { 5290 return; 5291 } 5292 5293 /* 5294 ** Steinbach's Guideline for Systems Programming: 5295 ** Never test for an error condition you don't know how to handle. 5296 */ 5297 5298 sist = (istat & SIP) ? INW (nc_sist) : 0; 5299 dstat = (istat & DIP) ? INB (nc_dstat) : 0; 5300 np->profile.num_int++; 5301 5302 if (DEBUG_FLAGS & DEBUG_TINY) 5303 printf ("<%d|%x:%x|%x:%x>", 5304 INB(nc_scr0), 5305 dstat,sist, 5306 (unsigned)INL(nc_dsp), 5307 (unsigned)INL(nc_dbc)); 5308 if ((dstat==DFE) && (sist==PAR)) return; 5309 5310/*========================================================== 5311** 5312** First the normal cases. 5313** 5314**========================================================== 5315*/ 5316 /*------------------------------------------- 5317 ** SCSI reset 5318 **------------------------------------------- 5319 */ 5320 5321 if (sist & RST) { 5322 ncr_init (np, bootverbose ? "scsi reset" : NULL, HS_RESET); 5323 return; 5324 }; 5325 5326 /*------------------------------------------- 5327 ** selection timeout 5328 ** 5329 ** IID excluded from dstat mask! 5330 ** (chip bug) 5331 **------------------------------------------- 5332 */ 5333 5334 if ((sist & STO) && 5335 !(sist & (GEN|HTH|MA|SGE|UDC|RST|PAR)) && 5336 !(dstat & (MDPE|BF|ABRT|SIR))) { 5337 ncr_int_sto (np); 5338 return; 5339 }; 5340 5341 /*------------------------------------------- 5342 ** Phase mismatch. 5343 **------------------------------------------- 5344 */ 5345 5346 if ((sist & MA) && 5347 !(sist & (STO|GEN|HTH|SGE|UDC|RST|PAR)) && 5348 !(dstat & (MDPE|BF|ABRT|SIR|IID))) { 5349 ncr_int_ma (np, dstat); 5350 return; 5351 }; 5352 5353 /*---------------------------------------- 5354 ** move command with length 0 5355 **---------------------------------------- 5356 */ 5357 5358 if ((dstat & IID) && 5359 !(sist & (STO|GEN|HTH|MA|SGE|UDC|RST|PAR)) && 5360 !(dstat & (MDPE|BF|ABRT|SIR)) && 5361 ((INL(nc_dbc) & 0xf8000000) == SCR_MOVE_TBL)) { 5362 /* 5363 ** Target wants more data than available. 5364 ** The "no_data" script will do it. 5365 */ 5366 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, no_data)); 5367 return; 5368 }; 5369 5370 /*------------------------------------------- 5371 ** Programmed interrupt 5372 **------------------------------------------- 5373 */ 5374 5375 if ((dstat & SIR) && 5376 !(sist & (STO|GEN|HTH|MA|SGE|UDC|RST|PAR)) && 5377 !(dstat & (MDPE|BF|ABRT|IID)) && 5378 (INB(nc_dsps) <= SIR_MAX)) { 5379 ncr_int_sir (np); 5380 return; 5381 }; 5382 5383 /*======================================== 5384 ** log message for real hard errors 5385 **======================================== 5386 */ 5387 5388 ncr_log_hard_error(np, sist, dstat); 5389 5390 /*======================================== 5391 ** do the register dump 5392 **======================================== 5393 */ 5394 5395 if (time_second - np->regtime > 10) { 5396 int i; 5397 np->regtime = time_second; 5398 for (i=0; i<sizeof(np->regdump); i++) 5399 ((volatile char*)&np->regdump)[i] = INB_OFF(i); 5400 np->regdump.nc_dstat = dstat; 5401 np->regdump.nc_sist = sist; 5402 }; 5403 5404 5405 /*---------------------------------------- 5406 ** clean up the dma fifo 5407 **---------------------------------------- 5408 */ 5409 5410 if ( (INB(nc_sstat0) & (ILF|ORF|OLF) ) || 5411 (INB(nc_sstat1) & (FF3210) ) || 5412 (INB(nc_sstat2) & (ILF1|ORF1|OLF1)) || /* wide .. */ 5413 !(dstat & DFE)) { 5414 printf ("%s: have to clear fifos.\n", ncr_name (np)); 5415 OUTB (nc_stest3, TE|CSF); /* clear scsi fifo */ 5416 OUTB (nc_ctest3, np->rv_ctest3 | CLF); 5417 /* clear dma fifo */ 5418 } 5419 5420 /*---------------------------------------- 5421 ** handshake timeout 5422 **---------------------------------------- 5423 */ 5424 5425 if (sist & HTH) { 5426 printf ("%s: handshake timeout\n", ncr_name(np)); 5427 OUTB (nc_scntl1, CRST); 5428 DELAY (1000); 5429 OUTB (nc_scntl1, 0x00); 5430 OUTB (nc_scr0, HS_FAIL); 5431 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, cleanup)); 5432 return; 5433 } 5434 5435 /*---------------------------------------- 5436 ** unexpected disconnect 5437 **---------------------------------------- 5438 */ 5439 5440 if ((sist & UDC) && 5441 !(sist & (STO|GEN|HTH|MA|SGE|RST|PAR)) && 5442 !(dstat & (MDPE|BF|ABRT|SIR|IID))) { 5443 OUTB (nc_scr0, HS_UNEXPECTED); 5444 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, cleanup)); 5445 return; 5446 }; 5447 5448 /*---------------------------------------- 5449 ** cannot disconnect 5450 **---------------------------------------- 5451 */ 5452 5453 if ((dstat & IID) && 5454 !(sist & (STO|GEN|HTH|MA|SGE|UDC|RST|PAR)) && 5455 !(dstat & (MDPE|BF|ABRT|SIR)) && 5456 ((INL(nc_dbc) & 0xf8000000) == SCR_WAIT_DISC)) { 5457 /* 5458 ** Unexpected data cycle while waiting for disconnect. 5459 */ 5460 if (INB(nc_sstat2) & LDSC) { 5461 /* 5462 ** It's an early reconnect. 5463 ** Let's continue ... 5464 */ 5465 OUTB (nc_dcntl, np->rv_dcntl | STD); 5466 /* 5467 ** info message 5468 */ 5469 printf ("%s: INFO: LDSC while IID.\n", 5470 ncr_name (np)); 5471 return; 5472 }; 5473 printf ("%s: target %d doesn't release the bus.\n", 5474 ncr_name (np), INB (nc_sdid)&0x0f); 5475 /* 5476 ** return without restarting the NCR. 5477 ** timeout will do the real work. 5478 */ 5479 return; 5480 }; 5481 5482 /*---------------------------------------- 5483 ** single step 5484 **---------------------------------------- 5485 */ 5486 5487 if ((dstat & SSI) && 5488 !(sist & (STO|GEN|HTH|MA|SGE|UDC|RST|PAR)) && 5489 !(dstat & (MDPE|BF|ABRT|SIR|IID))) { 5490 OUTB (nc_dcntl, np->rv_dcntl | STD); 5491 return; 5492 }; 5493 5494/* 5495** @RECOVER@ HTH, SGE, ABRT. 5496** 5497** We should try to recover from these interrupts. 5498** They may occur if there are problems with synch transfers, or 5499** if targets are switched on or off while the driver is running. 5500*/ 5501 5502 if (sist & SGE) { 5503 /* clear scsi offsets */ 5504 OUTB (nc_ctest3, np->rv_ctest3 | CLF); 5505 } 5506 5507 /* 5508 ** Freeze controller to be able to read the messages. 5509 */ 5510 5511 if (DEBUG_FLAGS & DEBUG_FREEZE) { 5512 int i; 5513 unsigned char val; 5514 for (i=0; i<0x60; i++) { 5515 switch (i%16) { 5516 5517 case 0: 5518 printf ("%s: reg[%d0]: ", 5519 ncr_name(np),i/16); 5520 break; 5521 case 4: 5522 case 8: 5523 case 12: 5524 printf (" "); 5525 break; 5526 }; 5527 val = bus_space_read_1(np->bst, np->bsh, i); 5528 printf (" %x%x", val/16, val%16); 5529 if (i%16==15) printf (".\n"); 5530 }; 5531 5532 untimeout (ncr_timeout, (caddr_t) np, np->timeout_ch); 5533 5534 printf ("%s: halted!\n", ncr_name(np)); 5535 /* 5536 ** don't restart controller ... 5537 */ 5538 OUTB (nc_istat, SRST); 5539 return; 5540 }; 5541 5542#ifdef NCR_FREEZE 5543 /* 5544 ** Freeze system to be able to read the messages. 5545 */ 5546 printf ("ncr: fatal error: system halted - press reset to reboot ..."); 5547 for (;;); 5548#endif 5549 5550 /* 5551 ** sorry, have to kill ALL jobs ... 5552 */ 5553 5554 ncr_init (np, "fatal error", HS_FAIL); 5555} 5556 5557/*========================================================== 5558** 5559** ncr chip exception handler for selection timeout 5560** 5561**========================================================== 5562** 5563** There seems to be a bug in the 53c810. 5564** Although a STO-Interrupt is pending, 5565** it continues executing script commands. 5566** But it will fail and interrupt (IID) on 5567** the next instruction where it's looking 5568** for a valid phase. 5569** 5570**---------------------------------------------------------- 5571*/ 5572 5573static void ncr_int_sto (ncb_p np) 5574{ 5575 u_long dsa, scratcha, diff; 5576 nccb_p cp; 5577 if (DEBUG_FLAGS & DEBUG_TINY) printf ("T"); 5578 5579 /* 5580 ** look for nccb and set the status. 5581 */ 5582 5583 dsa = INL (nc_dsa); 5584 cp = np->link_nccb; 5585 while (cp && (CCB_PHYS (cp, phys) != dsa)) 5586 cp = cp->link_nccb; 5587 5588 if (cp) { 5589 cp-> host_status = HS_SEL_TIMEOUT; 5590 ncr_complete (np, cp); 5591 }; 5592 5593 /* 5594 ** repair start queue 5595 */ 5596 5597 scratcha = INL (nc_scratcha); 5598 diff = scratcha - NCB_SCRIPTH_PHYS (np, tryloop); 5599 5600/* assert ((diff <= MAX_START * 20) && !(diff % 20));*/ 5601 5602 if ((diff <= MAX_START * 20) && !(diff % 20)) { 5603 WRITESCRIPT(startpos[0], scratcha); 5604 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, start)); 5605 return; 5606 }; 5607 ncr_init (np, "selection timeout", HS_FAIL); 5608} 5609 5610/*========================================================== 5611** 5612** 5613** ncr chip exception handler for phase errors. 5614** 5615** 5616**========================================================== 5617** 5618** We have to construct a new transfer descriptor, 5619** to transfer the rest of the current block. 5620** 5621**---------------------------------------------------------- 5622*/ 5623 5624static void ncr_int_ma (ncb_p np, u_char dstat) 5625{ 5626 u_int32_t dbc; 5627 u_int32_t rest; 5628 u_int32_t dsa; 5629 u_int32_t dsp; 5630 u_int32_t nxtdsp; 5631 volatile void *vdsp_base; 5632 size_t vdsp_off; 5633 u_int32_t oadr, olen; 5634 u_int32_t *tblp, *newcmd; 5635 u_char cmd, sbcl, ss0, ss2, ctest5; 5636 u_short delta; 5637 nccb_p cp; 5638 5639 dsp = INL (nc_dsp); 5640 dsa = INL (nc_dsa); 5641 dbc = INL (nc_dbc); 5642 ss0 = INB (nc_sstat0); 5643 ss2 = INB (nc_sstat2); 5644 sbcl= INB (nc_sbcl); 5645 5646 cmd = dbc >> 24; 5647 rest= dbc & 0xffffff; 5648 5649 ctest5 = (np->rv_ctest5 & DFS) ? INB (nc_ctest5) : 0; 5650 if (ctest5 & DFS) 5651 delta=(((ctest5<<8) | (INB (nc_dfifo) & 0xff)) - rest) & 0x3ff; 5652 else 5653 delta=(INB (nc_dfifo) - rest) & 0x7f; 5654 5655 5656 /* 5657 ** The data in the dma fifo has not been transfered to 5658 ** the target -> add the amount to the rest 5659 ** and clear the data. 5660 ** Check the sstat2 register in case of wide transfer. 5661 */ 5662 5663 if (!(dstat & DFE)) rest += delta; 5664 if (ss0 & OLF) rest++; 5665 if (ss0 & ORF) rest++; 5666 if (INB(nc_scntl3) & EWS) { 5667 if (ss2 & OLF1) rest++; 5668 if (ss2 & ORF1) rest++; 5669 }; 5670 OUTB (nc_ctest3, np->rv_ctest3 | CLF); /* clear dma fifo */ 5671 OUTB (nc_stest3, TE|CSF); /* clear scsi fifo */ 5672 5673 /* 5674 ** locate matching cp 5675 */ 5676 cp = np->link_nccb; 5677 while (cp && (CCB_PHYS (cp, phys) != dsa)) 5678 cp = cp->link_nccb; 5679 5680 if (!cp) { 5681 printf ("%s: SCSI phase error fixup: CCB already dequeued (%p)\n", 5682 ncr_name (np), (void *) np->header.cp); 5683 return; 5684 } 5685 if (cp != np->header.cp) { 5686 printf ("%s: SCSI phase error fixup: CCB address mismatch " 5687 "(%p != %p) np->nccb = %p\n", 5688 ncr_name (np), (void *)cp, (void *)np->header.cp, 5689 (void *)np->link_nccb); 5690/* return;*/ 5691 } 5692 5693 /* 5694 ** find the interrupted script command, 5695 ** and the address at which to continue. 5696 */ 5697 5698 if (dsp == vtophys (&cp->patch[2])) { 5699 vdsp_base = cp; 5700 vdsp_off = offsetof(struct nccb, patch[0]); 5701 nxtdsp = READSCRIPT_OFF(vdsp_base, vdsp_off + 3*4); 5702 } else if (dsp == vtophys (&cp->patch[6])) { 5703 vdsp_base = cp; 5704 vdsp_off = offsetof(struct nccb, patch[4]); 5705 nxtdsp = READSCRIPT_OFF(vdsp_base, vdsp_off + 3*4); 5706 } else if (dsp > np->p_script && 5707 dsp <= np->p_script + sizeof(struct script)) { 5708 vdsp_base = np->script; 5709 vdsp_off = dsp - np->p_script - 8; 5710 nxtdsp = dsp; 5711 } else { 5712 vdsp_base = np->scripth; 5713 vdsp_off = dsp - np->p_scripth - 8; 5714 nxtdsp = dsp; 5715 }; 5716 5717 /* 5718 ** log the information 5719 */ 5720 if (DEBUG_FLAGS & (DEBUG_TINY|DEBUG_PHASE)) { 5721 printf ("P%x%x ",cmd&7, sbcl&7); 5722 printf ("RL=%d D=%d SS0=%x ", 5723 (unsigned) rest, (unsigned) delta, ss0); 5724 }; 5725 if (DEBUG_FLAGS & DEBUG_PHASE) { 5726 printf ("\nCP=%p CP2=%p DSP=%x NXT=%x VDSP=%p CMD=%x ", 5727 cp, np->header.cp, 5728 dsp, 5729 nxtdsp, (volatile char*)vdsp_base+vdsp_off, cmd); 5730 }; 5731 5732 /* 5733 ** get old startaddress and old length. 5734 */ 5735 5736 oadr = READSCRIPT_OFF(vdsp_base, vdsp_off + 1*4); 5737 5738 if (cmd & 0x10) { /* Table indirect */ 5739 tblp = (u_int32_t *) ((char*) &cp->phys + oadr); 5740 olen = tblp[0]; 5741 oadr = tblp[1]; 5742 } else { 5743 tblp = (u_int32_t *) 0; 5744 olen = READSCRIPT_OFF(vdsp_base, vdsp_off) & 0xffffff; 5745 }; 5746 5747 if (DEBUG_FLAGS & DEBUG_PHASE) { 5748 printf ("OCMD=%x\nTBLP=%p OLEN=%lx OADR=%lx\n", 5749 (unsigned) (READSCRIPT_OFF(vdsp_base, vdsp_off) >> 24), 5750 (void *) tblp, 5751 (u_long) olen, 5752 (u_long) oadr); 5753 }; 5754 5755 /* 5756 ** if old phase not dataphase, leave here. 5757 */ 5758 5759 if (cmd != (READSCRIPT_OFF(vdsp_base, vdsp_off) >> 24)) { 5760 PRINT_ADDR(cp->ccb); 5761 printf ("internal error: cmd=%02x != %02x=(vdsp[0] >> 24)\n", 5762 (unsigned)cmd, 5763 (unsigned)READSCRIPT_OFF(vdsp_base, vdsp_off) >> 24); 5764 5765 return; 5766 } 5767 if (cmd & 0x06) { 5768 PRINT_ADDR(cp->ccb); 5769 printf ("phase change %x-%x %d@%08x resid=%d.\n", 5770 cmd&7, sbcl&7, (unsigned)olen, 5771 (unsigned)oadr, (unsigned)rest); 5772 5773 OUTB (nc_dcntl, np->rv_dcntl | STD); 5774 return; 5775 }; 5776 5777 /* 5778 ** choose the correct patch area. 5779 ** if savep points to one, choose the other. 5780 */ 5781 5782 newcmd = cp->patch; 5783 if (cp->phys.header.savep == vtophys (newcmd)) newcmd+=4; 5784 5785 /* 5786 ** fillin the commands 5787 */ 5788 5789 newcmd[0] = ((cmd & 0x0f) << 24) | rest; 5790 newcmd[1] = oadr + olen - rest; 5791 newcmd[2] = SCR_JUMP; 5792 newcmd[3] = nxtdsp; 5793 5794 if (DEBUG_FLAGS & DEBUG_PHASE) { 5795 PRINT_ADDR(cp->ccb); 5796 printf ("newcmd[%d] %x %x %x %x.\n", 5797 (int)(newcmd - cp->patch), 5798 (unsigned)newcmd[0], 5799 (unsigned)newcmd[1], 5800 (unsigned)newcmd[2], 5801 (unsigned)newcmd[3]); 5802 } 5803 /* 5804 ** fake the return address (to the patch). 5805 ** and restart script processor at dispatcher. 5806 */ 5807 np->profile.num_break++; 5808 OUTL (nc_temp, vtophys (newcmd)); 5809 if ((cmd & 7) == 0) 5810 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, dispatch)); 5811 else 5812 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, checkatn)); 5813} 5814 5815/*========================================================== 5816** 5817** 5818** ncr chip exception handler for programmed interrupts. 5819** 5820** 5821**========================================================== 5822*/ 5823 5824static int ncr_show_msg (u_char * msg) 5825{ 5826 u_char i; 5827 printf ("%x",*msg); 5828 if (*msg==MSG_EXTENDED) { 5829 for (i=1;i<8;i++) { 5830 if (i-1>msg[1]) break; 5831 printf ("-%x",msg[i]); 5832 }; 5833 return (i+1); 5834 } else if ((*msg & 0xf0) == 0x20) { 5835 printf ("-%x",msg[1]); 5836 return (2); 5837 }; 5838 return (1); 5839} 5840 5841static void ncr_int_sir (ncb_p np) 5842{ 5843 u_char scntl3; 5844 u_char chg, ofs, per, fak, wide; 5845 u_char num = INB (nc_dsps); 5846 nccb_p cp=0; 5847 u_long dsa; 5848 u_int target = INB (nc_sdid) & 0x0f; 5849 tcb_p tp = &np->target[target]; 5850 int i; 5851 if (DEBUG_FLAGS & DEBUG_TINY) printf ("I#%d", num); 5852 5853 switch (num) { 5854 case SIR_SENSE_RESTART: 5855 case SIR_STALL_RESTART: 5856 break; 5857 5858 default: 5859 /* 5860 ** lookup the nccb 5861 */ 5862 dsa = INL (nc_dsa); 5863 cp = np->link_nccb; 5864 while (cp && (CCB_PHYS (cp, phys) != dsa)) 5865 cp = cp->link_nccb; 5866 5867 assert (cp); 5868 if (!cp) 5869 goto out; 5870 assert (cp == np->header.cp); 5871 if (cp != np->header.cp) 5872 goto out; 5873 } 5874 5875 switch (num) { 5876 5877/*-------------------------------------------------------------------- 5878** 5879** Processing of interrupted getcc selects 5880** 5881**-------------------------------------------------------------------- 5882*/ 5883 5884 case SIR_SENSE_RESTART: 5885 /*------------------------------------------ 5886 ** Script processor is idle. 5887 ** Look for interrupted "check cond" 5888 **------------------------------------------ 5889 */ 5890 5891 if (DEBUG_FLAGS & DEBUG_RESTART) 5892 printf ("%s: int#%d",ncr_name (np),num); 5893 cp = (nccb_p) 0; 5894 for (i=0; i<MAX_TARGET; i++) { 5895 if (DEBUG_FLAGS & DEBUG_RESTART) printf (" t%d", i); 5896 tp = &np->target[i]; 5897 if (DEBUG_FLAGS & DEBUG_RESTART) printf ("+"); 5898 cp = tp->hold_cp; 5899 if (!cp) continue; 5900 if (DEBUG_FLAGS & DEBUG_RESTART) printf ("+"); 5901 if ((cp->host_status==HS_BUSY) && 5902 (cp->s_status==SCSI_STATUS_CHECK_COND)) 5903 break; 5904 if (DEBUG_FLAGS & DEBUG_RESTART) printf ("- (remove)"); 5905 tp->hold_cp = cp = (nccb_p) 0; 5906 }; 5907 5908 if (cp) { 5909 if (DEBUG_FLAGS & DEBUG_RESTART) 5910 printf ("+ restart job ..\n"); 5911 OUTL (nc_dsa, CCB_PHYS (cp, phys)); 5912 OUTL (nc_dsp, NCB_SCRIPTH_PHYS (np, getcc)); 5913 return; 5914 }; 5915 5916 /* 5917 ** no job, resume normal processing 5918 */ 5919 if (DEBUG_FLAGS & DEBUG_RESTART) printf (" -- remove trap\n"); 5920 WRITESCRIPT(start0[0], SCR_INT ^ IFFALSE (0)); 5921 break; 5922 5923 case SIR_SENSE_FAILED: 5924 /*------------------------------------------- 5925 ** While trying to select for 5926 ** getting the condition code, 5927 ** a target reselected us. 5928 **------------------------------------------- 5929 */ 5930 if (DEBUG_FLAGS & DEBUG_RESTART) { 5931 PRINT_ADDR(cp->ccb); 5932 printf ("in getcc reselect by t%d.\n", 5933 INB(nc_ssid) & 0x0f); 5934 } 5935 5936 /* 5937 ** Mark this job 5938 */ 5939 cp->host_status = HS_BUSY; 5940 cp->s_status = SCSI_STATUS_CHECK_COND; 5941 np->target[cp->ccb->ccb_h.target_id].hold_cp = cp; 5942 5943 /* 5944 ** And patch code to restart it. 5945 */ 5946 WRITESCRIPT(start0[0], SCR_INT); 5947 break; 5948 5949/*----------------------------------------------------------------------------- 5950** 5951** Was Sie schon immer ueber transfermode negotiation wissen wollten ... 5952** 5953** We try to negotiate sync and wide transfer only after 5954** a successfull inquire command. We look at byte 7 of the 5955** inquire data to determine the capabilities if the target. 5956** 5957** When we try to negotiate, we append the negotiation message 5958** to the identify and (maybe) simple tag message. 5959** The host status field is set to HS_NEGOTIATE to mark this 5960** situation. 5961** 5962** If the target doesn't answer this message immidiately 5963** (as required by the standard), the SIR_NEGO_FAIL interrupt 5964** will be raised eventually. 5965** The handler removes the HS_NEGOTIATE status, and sets the 5966** negotiated value to the default (async / nowide). 5967** 5968** If we receive a matching answer immediately, we check it 5969** for validity, and set the values. 5970** 5971** If we receive a Reject message immediately, we assume the 5972** negotiation has failed, and fall back to standard values. 5973** 5974** If we receive a negotiation message while not in HS_NEGOTIATE 5975** state, it's a target initiated negotiation. We prepare a 5976** (hopefully) valid answer, set our parameters, and send back 5977** this answer to the target. 5978** 5979** If the target doesn't fetch the answer (no message out phase), 5980** we assume the negotiation has failed, and fall back to default 5981** settings. 5982** 5983** When we set the values, we adjust them in all nccbs belonging 5984** to this target, in the controller's register, and in the "phys" 5985** field of the controller's struct ncb. 5986** 5987** Possible cases: hs sir msg_in value send goto 5988** We try try to negotiate: 5989** -> target doesnt't msgin NEG FAIL noop defa. - dispatch 5990** -> target rejected our msg NEG FAIL reject defa. - dispatch 5991** -> target answered (ok) NEG SYNC sdtr set - clrack 5992** -> target answered (!ok) NEG SYNC sdtr defa. REJ--->msg_bad 5993** -> target answered (ok) NEG WIDE wdtr set - clrack 5994** -> target answered (!ok) NEG WIDE wdtr defa. REJ--->msg_bad 5995** -> any other msgin NEG FAIL noop defa. - dispatch 5996** 5997** Target tries to negotiate: 5998** -> incoming message --- SYNC sdtr set SDTR - 5999** -> incoming message --- WIDE wdtr set WDTR - 6000** We sent our answer: 6001** -> target doesn't msgout --- PROTO ? defa. - dispatch 6002** 6003**----------------------------------------------------------------------------- 6004*/ 6005 6006 case SIR_NEGO_FAILED: 6007 /*------------------------------------------------------- 6008 ** 6009 ** Negotiation failed. 6010 ** Target doesn't send an answer message, 6011 ** or target rejected our message. 6012 ** 6013 ** Remove negotiation request. 6014 ** 6015 **------------------------------------------------------- 6016 */ 6017 OUTB (HS_PRT, HS_BUSY); 6018 6019 /* FALLTHROUGH */ 6020 6021 case SIR_NEGO_PROTO: 6022 /*------------------------------------------------------- 6023 ** 6024 ** Negotiation failed. 6025 ** Target doesn't fetch the answer message. 6026 ** 6027 **------------------------------------------------------- 6028 */ 6029 6030 if (DEBUG_FLAGS & DEBUG_NEGO) { 6031 PRINT_ADDR(cp->ccb); 6032 printf ("negotiation failed sir=%x status=%x.\n", 6033 num, cp->nego_status); 6034 }; 6035 6036 /* 6037 ** any error in negotiation: 6038 ** fall back to default mode. 6039 */ 6040 switch (cp->nego_status) { 6041 6042 case NS_SYNC: 6043 ncr_setsync (np, cp, 0, 0xe0, 0); 6044 break; 6045 6046 case NS_WIDE: 6047 ncr_setwide (np, cp, 0, 0); 6048 break; 6049 6050 }; 6051 np->msgin [0] = MSG_NOOP; 6052 np->msgout[0] = MSG_NOOP; 6053 cp->nego_status = 0; 6054 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, dispatch)); 6055 break; 6056 6057 case SIR_NEGO_SYNC: 6058 /* 6059 ** Synchronous request message received. 6060 */ 6061 6062 if (DEBUG_FLAGS & DEBUG_NEGO) { 6063 PRINT_ADDR(cp->ccb); 6064 printf ("sync msgin: "); 6065 (void) ncr_show_msg (np->msgin); 6066 printf (".\n"); 6067 }; 6068 6069 /* 6070 ** get requested values. 6071 */ 6072 6073 chg = 0; 6074 per = np->msgin[3]; 6075 ofs = np->msgin[4]; 6076 if (ofs==0) per=255; 6077 6078 /* 6079 ** check values against driver limits. 6080 */ 6081 if (per < np->minsync) 6082 {chg = 1; per = np->minsync;} 6083 if (per < tp->tinfo.user.period) 6084 {chg = 1; per = tp->tinfo.user.period;} 6085 if (ofs > tp->tinfo.user.offset) 6086 {chg = 1; ofs = tp->tinfo.user.offset;} 6087 6088 /* 6089 ** Check against controller limits. 6090 */ 6091 6092 fak = 7; 6093 scntl3 = 0; 6094 if (ofs != 0) { 6095 ncr_getsync(np, per, &fak, &scntl3); 6096 if (fak > 7) { 6097 chg = 1; 6098 ofs = 0; 6099 } 6100 } 6101 if (ofs == 0) { 6102 fak = 7; 6103 per = 0; 6104 scntl3 = 0; 6105 } 6106 6107 if (DEBUG_FLAGS & DEBUG_NEGO) { 6108 PRINT_ADDR(cp->ccb); 6109 printf ("sync: per=%d scntl3=0x%x ofs=%d fak=%d chg=%d.\n", 6110 per, scntl3, ofs, fak, chg); 6111 } 6112 6113 if (INB (HS_PRT) == HS_NEGOTIATE) { 6114 OUTB (HS_PRT, HS_BUSY); 6115 switch (cp->nego_status) { 6116 6117 case NS_SYNC: 6118 /* 6119 ** This was an answer message 6120 */ 6121 if (chg) { 6122 /* 6123 ** Answer wasn't acceptable. 6124 */ 6125 ncr_setsync (np, cp, 0, 0xe0, 0); 6126 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, msg_bad)); 6127 } else { 6128 /* 6129 ** Answer is ok. 6130 */ 6131 ncr_setsync (np,cp,scntl3,(fak<<5)|ofs, per); 6132 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, clrack)); 6133 }; 6134 return; 6135 6136 case NS_WIDE: 6137 ncr_setwide (np, cp, 0, 0); 6138 break; 6139 }; 6140 }; 6141 6142 /* 6143 ** It was a request. Set value and 6144 ** prepare an answer message 6145 */ 6146 6147 ncr_setsync (np, cp, scntl3, (fak<<5)|ofs, per); 6148 6149 np->msgout[0] = MSG_EXTENDED; 6150 np->msgout[1] = 3; 6151 np->msgout[2] = MSG_EXT_SDTR; 6152 np->msgout[3] = per; 6153 np->msgout[4] = ofs; 6154 6155 cp->nego_status = NS_SYNC; 6156 6157 if (DEBUG_FLAGS & DEBUG_NEGO) { 6158 PRINT_ADDR(cp->ccb); 6159 printf ("sync msgout: "); 6160 (void) ncr_show_msg (np->msgout); 6161 printf (".\n"); 6162 } 6163 6164 if (!ofs) { 6165 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, msg_bad)); 6166 return; 6167 } 6168 np->msgin [0] = MSG_NOOP; 6169 6170 break; 6171 6172 case SIR_NEGO_WIDE: 6173 /* 6174 ** Wide request message received. 6175 */ 6176 if (DEBUG_FLAGS & DEBUG_NEGO) { 6177 PRINT_ADDR(cp->ccb); 6178 printf ("wide msgin: "); 6179 (void) ncr_show_msg (np->msgin); 6180 printf (".\n"); 6181 }; 6182 6183 /* 6184 ** get requested values. 6185 */ 6186 6187 chg = 0; 6188 wide = np->msgin[3]; 6189 6190 /* 6191 ** check values against driver limits. 6192 */ 6193 6194 if (wide > tp->tinfo.user.width) 6195 {chg = 1; wide = tp->tinfo.user.width;} 6196 6197 if (DEBUG_FLAGS & DEBUG_NEGO) { 6198 PRINT_ADDR(cp->ccb); 6199 printf ("wide: wide=%d chg=%d.\n", wide, chg); 6200 } 6201 6202 if (INB (HS_PRT) == HS_NEGOTIATE) { 6203 OUTB (HS_PRT, HS_BUSY); 6204 switch (cp->nego_status) { 6205 6206 case NS_WIDE: 6207 /* 6208 ** This was an answer message 6209 */ 6210 if (chg) { 6211 /* 6212 ** Answer wasn't acceptable. 6213 */ 6214 ncr_setwide (np, cp, 0, 1); 6215 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, msg_bad)); 6216 } else { 6217 /* 6218 ** Answer is ok. 6219 */ 6220 ncr_setwide (np, cp, wide, 1); 6221 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, clrack)); 6222 }; 6223 return; 6224 6225 case NS_SYNC: 6226 ncr_setsync (np, cp, 0, 0xe0, 0); 6227 break; 6228 }; 6229 }; 6230 6231 /* 6232 ** It was a request, set value and 6233 ** prepare an answer message 6234 */ 6235 6236 ncr_setwide (np, cp, wide, 1); 6237 6238 np->msgout[0] = MSG_EXTENDED; 6239 np->msgout[1] = 2; 6240 np->msgout[2] = MSG_EXT_WDTR; 6241 np->msgout[3] = wide; 6242 6243 np->msgin [0] = MSG_NOOP; 6244 6245 cp->nego_status = NS_WIDE; 6246 6247 if (DEBUG_FLAGS & DEBUG_NEGO) { 6248 PRINT_ADDR(cp->ccb); 6249 printf ("wide msgout: "); 6250 (void) ncr_show_msg (np->msgout); 6251 printf (".\n"); 6252 } 6253 break; 6254 6255/*-------------------------------------------------------------------- 6256** 6257** Processing of special messages 6258** 6259**-------------------------------------------------------------------- 6260*/ 6261 6262 case SIR_REJECT_RECEIVED: 6263 /*----------------------------------------------- 6264 ** 6265 ** We received a MSG_MESSAGE_REJECT message. 6266 ** 6267 **----------------------------------------------- 6268 */ 6269 6270 PRINT_ADDR(cp->ccb); 6271 printf ("MSG_MESSAGE_REJECT received (%x:%x).\n", 6272 (unsigned)np->lastmsg, np->msgout[0]); 6273 break; 6274 6275 case SIR_REJECT_SENT: 6276 /*----------------------------------------------- 6277 ** 6278 ** We received an unknown message 6279 ** 6280 **----------------------------------------------- 6281 */ 6282 6283 PRINT_ADDR(cp->ccb); 6284 printf ("MSG_MESSAGE_REJECT sent for "); 6285 (void) ncr_show_msg (np->msgin); 6286 printf (".\n"); 6287 break; 6288 6289/*-------------------------------------------------------------------- 6290** 6291** Processing of special messages 6292** 6293**-------------------------------------------------------------------- 6294*/ 6295 6296 case SIR_IGN_RESIDUE: 6297 /*----------------------------------------------- 6298 ** 6299 ** We received an IGNORE RESIDUE message, 6300 ** which couldn't be handled by the script. 6301 ** 6302 **----------------------------------------------- 6303 */ 6304 6305 PRINT_ADDR(cp->ccb); 6306 printf ("MSG_IGN_WIDE_RESIDUE received, but not yet implemented.\n"); 6307 break; 6308 6309 case SIR_MISSING_SAVE: 6310 /*----------------------------------------------- 6311 ** 6312 ** We received an DISCONNECT message, 6313 ** but the datapointer wasn't saved before. 6314 ** 6315 **----------------------------------------------- 6316 */ 6317 6318 PRINT_ADDR(cp->ccb); 6319 printf ("MSG_DISCONNECT received, but datapointer not saved:\n" 6320 "\tdata=%x save=%x goal=%x.\n", 6321 (unsigned) INL (nc_temp), 6322 (unsigned) np->header.savep, 6323 (unsigned) np->header.goalp); 6324 break; 6325 6326/*-------------------------------------------------------------------- 6327** 6328** Processing of a "SCSI_STATUS_QUEUE_FULL" status. 6329** 6330** XXX JGibbs - We should do the same thing for BUSY status. 6331** 6332** The current command has been rejected, 6333** because there are too many in the command queue. 6334** We have started too many commands for that target. 6335** 6336**-------------------------------------------------------------------- 6337*/ 6338 case SIR_STALL_QUEUE: 6339 cp->xerr_status = XE_OK; 6340 cp->host_status = HS_COMPLETE; 6341 cp->s_status = SCSI_STATUS_QUEUE_FULL; 6342 ncr_freeze_devq(np, cp->ccb->ccb_h.path); 6343 ncr_complete(np, cp); 6344 6345 /* FALLTHROUGH */ 6346 6347 case SIR_STALL_RESTART: 6348 /*----------------------------------------------- 6349 ** 6350 ** Enable selecting again, 6351 ** if NO disconnected jobs. 6352 ** 6353 **----------------------------------------------- 6354 */ 6355 /* 6356 ** Look for a disconnected job. 6357 */ 6358 cp = np->link_nccb; 6359 while (cp && cp->host_status != HS_DISCONNECT) 6360 cp = cp->link_nccb; 6361 6362 /* 6363 ** if there is one, ... 6364 */ 6365 if (cp) { 6366 /* 6367 ** wait for reselection 6368 */ 6369 OUTL (nc_dsp, NCB_SCRIPT_PHYS (np, reselect)); 6370 return; 6371 }; 6372 6373 /* 6374 ** else remove the interrupt. 6375 */ 6376 6377 printf ("%s: queue empty.\n", ncr_name (np)); 6378 WRITESCRIPT(start1[0], SCR_INT ^ IFFALSE (0)); 6379 break; 6380 }; 6381 6382out: 6383 OUTB (nc_dcntl, np->rv_dcntl | STD); 6384} 6385 6386/*========================================================== 6387** 6388** 6389** Aquire a control block 6390** 6391** 6392**========================================================== 6393*/ 6394 6395static nccb_p ncr_get_nccb 6396 (ncb_p np, u_long target, u_long lun) 6397{ 6398 lcb_p lp; 6399 nccb_p cp = NULL; 6400 6401 /* 6402 ** Lun structure available ? 6403 */ 6404 6405 lp = np->target[target].lp[lun]; 6406 if (lp) { 6407 cp = lp->next_nccb; 6408 6409 /* 6410 ** Look for free CCB 6411 */ 6412 6413 while (cp && cp->magic) { 6414 cp = cp->next_nccb; 6415 } 6416 } 6417 6418 /* 6419 ** if nothing available, create one. 6420 */ 6421 6422 if (cp == NULL) 6423 cp = ncr_alloc_nccb(np, target, lun); 6424 6425 if (cp != NULL) { 6426 if (cp->magic) { 6427 printf("%s: Bogus free cp found\n", ncr_name(np)); 6428 return (NULL); 6429 } 6430 cp->magic = 1; 6431 } 6432 return (cp); 6433} 6434 6435/*========================================================== 6436** 6437** 6438** Release one control block 6439** 6440** 6441**========================================================== 6442*/ 6443 6444static void ncr_free_nccb (ncb_p np, nccb_p cp) 6445{ 6446 /* 6447 ** sanity 6448 */ 6449 6450 assert (cp != NULL); 6451 6452 cp -> host_status = HS_IDLE; 6453 cp -> magic = 0; 6454} 6455 6456/*========================================================== 6457** 6458** 6459** Allocation of resources for Targets/Luns/Tags. 6460** 6461** 6462**========================================================== 6463*/ 6464 6465static nccb_p 6466ncr_alloc_nccb (ncb_p np, u_long target, u_long lun) 6467{ 6468 tcb_p tp; 6469 lcb_p lp; 6470 nccb_p cp; 6471 6472 assert (np != NULL); 6473 6474 if (target>=MAX_TARGET) return(NULL); 6475 if (lun >=MAX_LUN ) return(NULL); 6476 6477 tp=&np->target[target]; 6478 6479 if (!tp->jump_tcb.l_cmd) { 6480 6481 /* 6482 ** initialize it. 6483 */ 6484 tp->jump_tcb.l_cmd = (SCR_JUMP^IFFALSE (DATA (0x80 + target))); 6485 tp->jump_tcb.l_paddr = np->jump_tcb.l_paddr; 6486 6487 tp->getscr[0] = 6488 (np->features & FE_PFEN)? SCR_COPY(1) : SCR_COPY_F(1); 6489 tp->getscr[1] = vtophys (&tp->tinfo.sval); 6490 tp->getscr[2] = rman_get_start(np->reg_res) + offsetof (struct ncr_reg, nc_sxfer); 6491 tp->getscr[3] = 6492 (np->features & FE_PFEN)? SCR_COPY(1) : SCR_COPY_F(1); 6493 tp->getscr[4] = vtophys (&tp->tinfo.wval); 6494 tp->getscr[5] = rman_get_start(np->reg_res) + offsetof (struct ncr_reg, nc_scntl3); 6495 6496 assert (((offsetof(struct ncr_reg, nc_sxfer) ^ 6497 (offsetof(struct tcb ,tinfo) 6498 + offsetof(struct ncr_target_tinfo, sval))) & 3) == 0); 6499 assert (((offsetof(struct ncr_reg, nc_scntl3) ^ 6500 (offsetof(struct tcb, tinfo) 6501 + offsetof(struct ncr_target_tinfo, wval))) &3) == 0); 6502 6503 tp->call_lun.l_cmd = (SCR_CALL); 6504 tp->call_lun.l_paddr = NCB_SCRIPT_PHYS (np, resel_lun); 6505 6506 tp->jump_lcb.l_cmd = (SCR_JUMP); 6507 tp->jump_lcb.l_paddr = NCB_SCRIPTH_PHYS (np, abort); 6508 np->jump_tcb.l_paddr = vtophys (&tp->jump_tcb); 6509 } 6510 6511 /* 6512 ** Logic unit control block 6513 */ 6514 lp = tp->lp[lun]; 6515 if (!lp) { 6516 /* 6517 ** Allocate a lcb 6518 */ 6519 lp = (lcb_p) malloc (sizeof (struct lcb), M_DEVBUF, 6520 M_NOWAIT | M_ZERO); 6521 if (!lp) return(NULL); 6522 6523 /* 6524 ** Initialize it 6525 */ 6526 lp->jump_lcb.l_cmd = (SCR_JUMP ^ IFFALSE (DATA (lun))); 6527 lp->jump_lcb.l_paddr = tp->jump_lcb.l_paddr; 6528 6529 lp->call_tag.l_cmd = (SCR_CALL); 6530 lp->call_tag.l_paddr = NCB_SCRIPT_PHYS (np, resel_tag); 6531 6532 lp->jump_nccb.l_cmd = (SCR_JUMP); 6533 lp->jump_nccb.l_paddr = NCB_SCRIPTH_PHYS (np, aborttag); 6534 6535 lp->actlink = 1; 6536 6537 /* 6538 ** Chain into LUN list 6539 */ 6540 tp->jump_lcb.l_paddr = vtophys (&lp->jump_lcb); 6541 tp->lp[lun] = lp; 6542 6543 } 6544 6545 /* 6546 ** Allocate a nccb 6547 */ 6548 cp = (nccb_p) malloc (sizeof (struct nccb), M_DEVBUF, M_NOWAIT|M_ZERO); 6549 6550 if (!cp) 6551 return (NULL); 6552 6553 if (DEBUG_FLAGS & DEBUG_ALLOC) { 6554 printf ("new nccb @%p.\n", cp); 6555 } 6556 6557 /* 6558 ** Fill in physical addresses 6559 */ 6560 6561 cp->p_nccb = vtophys (cp); 6562 6563 /* 6564 ** Chain into reselect list 6565 */ 6566 cp->jump_nccb.l_cmd = SCR_JUMP; 6567 cp->jump_nccb.l_paddr = lp->jump_nccb.l_paddr; 6568 lp->jump_nccb.l_paddr = CCB_PHYS (cp, jump_nccb); 6569 cp->call_tmp.l_cmd = SCR_CALL; 6570 cp->call_tmp.l_paddr = NCB_SCRIPT_PHYS (np, resel_tmp); 6571 6572 /* 6573 ** Chain into wakeup list 6574 */ 6575 cp->link_nccb = np->link_nccb; 6576 np->link_nccb = cp; 6577 6578 /* 6579 ** Chain into CCB list 6580 */ 6581 cp->next_nccb = lp->next_nccb; 6582 lp->next_nccb = cp; 6583 6584 return (cp); 6585} 6586 6587/*========================================================== 6588** 6589** 6590** Build Scatter Gather Block 6591** 6592** 6593**========================================================== 6594** 6595** The transfer area may be scattered among 6596** several non adjacent physical pages. 6597** 6598** We may use MAX_SCATTER blocks. 6599** 6600**---------------------------------------------------------- 6601*/ 6602 6603static int ncr_scatter 6604 (struct dsb* phys, vm_offset_t vaddr, vm_size_t datalen) 6605{ 6606 u_long paddr, pnext; 6607 6608 u_short segment = 0; 6609 u_long segsize, segaddr; 6610 u_long size, csize = 0; 6611 u_long chunk = MAX_SIZE; 6612 int free; 6613 6614 bzero (&phys->data, sizeof (phys->data)); 6615 if (!datalen) return (0); 6616 6617 paddr = vtophys (vaddr); 6618 6619 /* 6620 ** insert extra break points at a distance of chunk. 6621 ** We try to reduce the number of interrupts caused 6622 ** by unexpected phase changes due to disconnects. 6623 ** A typical harddisk may disconnect before ANY block. 6624 ** If we wanted to avoid unexpected phase changes at all 6625 ** we had to use a break point every 512 bytes. 6626 ** Of course the number of scatter/gather blocks is 6627 ** limited. 6628 */ 6629 6630 free = MAX_SCATTER - 1; 6631 6632 if (vaddr & PAGE_MASK) free -= datalen / PAGE_SIZE; 6633 6634 if (free>1) 6635 while ((chunk * free >= 2 * datalen) && (chunk>=1024)) 6636 chunk /= 2; 6637 6638 if(DEBUG_FLAGS & DEBUG_SCATTER) 6639 printf("ncr?:\tscattering virtual=%p size=%d chunk=%d.\n", 6640 (void *) vaddr, (unsigned) datalen, (unsigned) chunk); 6641 6642 /* 6643 ** Build data descriptors. 6644 */ 6645 while (datalen && (segment < MAX_SCATTER)) { 6646 6647 /* 6648 ** this segment is empty 6649 */ 6650 segsize = 0; 6651 segaddr = paddr; 6652 pnext = paddr; 6653 6654 if (!csize) csize = chunk; 6655 6656 while ((datalen) && (paddr == pnext) && (csize)) { 6657 6658 /* 6659 ** continue this segment 6660 */ 6661 pnext = (paddr & (~PAGE_MASK)) + PAGE_SIZE; 6662 6663 /* 6664 ** Compute max size 6665 */ 6666 6667 size = pnext - paddr; /* page size */ 6668 if (size > datalen) size = datalen; /* data size */ 6669 if (size > csize ) size = csize ; /* chunksize */ 6670 6671 segsize += size; 6672 vaddr += size; 6673 csize -= size; 6674 datalen -= size; 6675 paddr = vtophys (vaddr); 6676 }; 6677 6678 if(DEBUG_FLAGS & DEBUG_SCATTER) 6679 printf ("\tseg #%d addr=%x size=%d (rest=%d).\n", 6680 segment, 6681 (unsigned) segaddr, 6682 (unsigned) segsize, 6683 (unsigned) datalen); 6684 6685 phys->data[segment].addr = segaddr; 6686 phys->data[segment].size = segsize; 6687 segment++; 6688 } 6689 6690 if (datalen) { 6691 printf("ncr?: scatter/gather failed (residue=%d).\n", 6692 (unsigned) datalen); 6693 return (-1); 6694 }; 6695 6696 return (segment); 6697} 6698 6699/*========================================================== 6700** 6701** 6702** Test the pci bus snoop logic :-( 6703** 6704** Has to be called with interrupts disabled. 6705** 6706** 6707**========================================================== 6708*/ 6709 6710#ifndef NCR_IOMAPPED 6711static int ncr_regtest (struct ncb* np) 6712{ 6713 register volatile u_int32_t data; 6714 /* 6715 ** ncr registers may NOT be cached. 6716 ** write 0xffffffff to a read only register area, 6717 ** and try to read it back. 6718 */ 6719 data = 0xffffffff; 6720 OUTL_OFF(offsetof(struct ncr_reg, nc_dstat), data); 6721 data = INL_OFF(offsetof(struct ncr_reg, nc_dstat)); 6722#if 1 6723 if (data == 0xffffffff) { 6724#else 6725 if ((data & 0xe2f0fffd) != 0x02000080) { 6726#endif 6727 printf ("CACHE TEST FAILED: reg dstat-sstat2 readback %x.\n", 6728 (unsigned) data); 6729 return (0x10); 6730 }; 6731 return (0); 6732} 6733#endif 6734 6735static int ncr_snooptest (struct ncb* np) 6736{ 6737 u_int32_t ncr_rd, ncr_wr, ncr_bk, host_rd, host_wr, pc; 6738 int i, err=0; 6739#ifndef NCR_IOMAPPED 6740 err |= ncr_regtest (np); 6741 if (err) return (err); 6742#endif 6743 /* 6744 ** init 6745 */ 6746 pc = NCB_SCRIPTH_PHYS (np, snooptest); 6747 host_wr = 1; 6748 ncr_wr = 2; 6749 /* 6750 ** Set memory and register. 6751 */ 6752 ncr_cache = host_wr; 6753 OUTL (nc_temp, ncr_wr); 6754 /* 6755 ** Start script (exchange values) 6756 */ 6757 OUTL (nc_dsp, pc); 6758 /* 6759 ** Wait 'til done (with timeout) 6760 */ 6761 for (i=0; i<NCR_SNOOP_TIMEOUT; i++) 6762 if (INB(nc_istat) & (INTF|SIP|DIP)) 6763 break; 6764 /* 6765 ** Save termination position. 6766 */ 6767 pc = INL (nc_dsp); 6768 /* 6769 ** Read memory and register. 6770 */ 6771 host_rd = ncr_cache; 6772 ncr_rd = INL (nc_scratcha); 6773 ncr_bk = INL (nc_temp); 6774 /* 6775 ** Reset ncr chip 6776 */ 6777 OUTB (nc_istat, SRST); 6778 DELAY (1000); 6779 OUTB (nc_istat, 0 ); 6780 /* 6781 ** check for timeout 6782 */ 6783 if (i>=NCR_SNOOP_TIMEOUT) { 6784 printf ("CACHE TEST FAILED: timeout.\n"); 6785 return (0x20); 6786 }; 6787 /* 6788 ** Check termination position. 6789 */ 6790 if (pc != NCB_SCRIPTH_PHYS (np, snoopend)+8) { 6791 printf ("CACHE TEST FAILED: script execution failed.\n"); 6792 printf ("start=%08lx, pc=%08lx, end=%08lx\n", 6793 (u_long) NCB_SCRIPTH_PHYS (np, snooptest), (u_long) pc, 6794 (u_long) NCB_SCRIPTH_PHYS (np, snoopend) +8); 6795 return (0x40); 6796 }; 6797 /* 6798 ** Show results. 6799 */ 6800 if (host_wr != ncr_rd) { 6801 printf ("CACHE TEST FAILED: host wrote %d, ncr read %d.\n", 6802 (int) host_wr, (int) ncr_rd); 6803 err |= 1; 6804 }; 6805 if (host_rd != ncr_wr) { 6806 printf ("CACHE TEST FAILED: ncr wrote %d, host read %d.\n", 6807 (int) ncr_wr, (int) host_rd); 6808 err |= 2; 6809 }; 6810 if (ncr_bk != ncr_wr) { 6811 printf ("CACHE TEST FAILED: ncr wrote %d, read back %d.\n", 6812 (int) ncr_wr, (int) ncr_bk); 6813 err |= 4; 6814 }; 6815 return (err); 6816} 6817 6818/*========================================================== 6819** 6820** 6821** Profiling the drivers and targets performance. 6822** 6823** 6824**========================================================== 6825*/ 6826 6827/* 6828** Compute the difference in milliseconds. 6829**/ 6830 6831static int ncr_delta (int *from, int *to) 6832{ 6833 if (!from) return (-1); 6834 if (!to) return (-2); 6835 return ((to - from) * 1000 / hz); 6836} 6837 6838#define PROFILE cp->phys.header.stamp 6839static void ncb_profile (ncb_p np, nccb_p cp) 6840{ 6841 int co, da, st, en, di, se, post,work,disc; 6842 u_long diff; 6843 6844 PROFILE.end = ticks; 6845 6846 st = ncr_delta (&PROFILE.start,&PROFILE.status); 6847 if (st<0) return; /* status not reached */ 6848 6849 da = ncr_delta (&PROFILE.start,&PROFILE.data); 6850 if (da<0) return; /* No data transfer phase */ 6851 6852 co = ncr_delta (&PROFILE.start,&PROFILE.command); 6853 if (co<0) return; /* command not executed */ 6854 6855 en = ncr_delta (&PROFILE.start,&PROFILE.end), 6856 di = ncr_delta (&PROFILE.start,&PROFILE.disconnect), 6857 se = ncr_delta (&PROFILE.start,&PROFILE.select); 6858 post = en - st; 6859 6860 /* 6861 ** @PROFILE@ Disconnect time invalid if multiple disconnects 6862 */ 6863 6864 if (di>=0) disc = se-di; else disc = 0; 6865 6866 work = (st - co) - disc; 6867 6868 diff = (np->disc_phys - np->disc_ref) & 0xff; 6869 np->disc_ref += diff; 6870 6871 np->profile.num_trans += 1; 6872 if (cp->ccb) 6873 np->profile.num_bytes += cp->ccb->csio.dxfer_len; 6874 np->profile.num_disc += diff; 6875 np->profile.ms_setup += co; 6876 np->profile.ms_data += work; 6877 np->profile.ms_disc += disc; 6878 np->profile.ms_post += post; 6879} 6880#undef PROFILE 6881 6882/*========================================================== 6883** 6884** Determine the ncr's clock frequency. 6885** This is essential for the negotiation 6886** of the synchronous transfer rate. 6887** 6888**========================================================== 6889** 6890** Note: we have to return the correct value. 6891** THERE IS NO SAVE DEFAULT VALUE. 6892** 6893** Most NCR/SYMBIOS boards are delivered with a 40 Mhz clock. 6894** 53C860 and 53C875 rev. 1 support fast20 transfers but 6895** do not have a clock doubler and so are provided with a 6896** 80 MHz clock. All other fast20 boards incorporate a doubler 6897** and so should be delivered with a 40 MHz clock. 6898** The future fast40 chips (895/895) use a 40 Mhz base clock 6899** and provide a clock quadrupler (160 Mhz). The code below 6900** tries to deal as cleverly as possible with all this stuff. 6901** 6902**---------------------------------------------------------- 6903*/ 6904 6905/* 6906 * Select NCR SCSI clock frequency 6907 */ 6908static void ncr_selectclock(ncb_p np, u_char scntl3) 6909{ 6910 if (np->multiplier < 2) { 6911 OUTB(nc_scntl3, scntl3); 6912 return; 6913 } 6914 6915 if (bootverbose >= 2) 6916 printf ("%s: enabling clock multiplier\n", ncr_name(np)); 6917 6918 OUTB(nc_stest1, DBLEN); /* Enable clock multiplier */ 6919 if (np->multiplier > 2) { /* Poll bit 5 of stest4 for quadrupler */ 6920 int i = 20; 6921 while (!(INB(nc_stest4) & LCKFRQ) && --i > 0) 6922 DELAY(20); 6923 if (!i) 6924 printf("%s: the chip cannot lock the frequency\n", ncr_name(np)); 6925 } else /* Wait 20 micro-seconds for doubler */ 6926 DELAY(20); 6927 OUTB(nc_stest3, HSC); /* Halt the scsi clock */ 6928 OUTB(nc_scntl3, scntl3); 6929 OUTB(nc_stest1, (DBLEN|DBLSEL));/* Select clock multiplier */ 6930 OUTB(nc_stest3, 0x00); /* Restart scsi clock */ 6931} 6932 6933/* 6934 * calculate NCR SCSI clock frequency (in KHz) 6935 */ 6936static unsigned 6937ncrgetfreq (ncb_p np, int gen) 6938{ 6939 int ms = 0; 6940 /* 6941 * Measure GEN timer delay in order 6942 * to calculate SCSI clock frequency 6943 * 6944 * This code will never execute too 6945 * many loop iterations (if DELAY is 6946 * reasonably correct). It could get 6947 * too low a delay (too high a freq.) 6948 * if the CPU is slow executing the 6949 * loop for some reason (an NMI, for 6950 * example). For this reason we will 6951 * if multiple measurements are to be 6952 * performed trust the higher delay 6953 * (lower frequency returned). 6954 */ 6955 OUTB (nc_stest1, 0); /* make sure clock doubler is OFF */ 6956 OUTW (nc_sien , 0); /* mask all scsi interrupts */ 6957 (void) INW (nc_sist); /* clear pending scsi interrupt */ 6958 OUTB (nc_dien , 0); /* mask all dma interrupts */ 6959 (void) INW (nc_sist); /* another one, just to be sure :) */ 6960 OUTB (nc_scntl3, 4); /* set pre-scaler to divide by 3 */ 6961 OUTB (nc_stime1, 0); /* disable general purpose timer */ 6962 OUTB (nc_stime1, gen); /* set to nominal delay of (1<<gen) * 125us */ 6963 while (!(INW(nc_sist) & GEN) && ms++ < 1000) 6964 DELAY(1000); /* count ms */ 6965 OUTB (nc_stime1, 0); /* disable general purpose timer */ 6966 OUTB (nc_scntl3, 0); 6967 /* 6968 * Set prescaler to divide by whatever "0" means. 6969 * "0" ought to choose divide by 2, but appears 6970 * to set divide by 3.5 mode in my 53c810 ... 6971 */ 6972 OUTB (nc_scntl3, 0); 6973 6974 if (bootverbose >= 2) 6975 printf ("\tDelay (GEN=%d): %u msec\n", gen, ms); 6976 /* 6977 * adjust for prescaler, and convert into KHz 6978 */ 6979 return ms ? ((1 << gen) * 4440) / ms : 0; 6980} 6981 6982static void ncr_getclock (ncb_p np, u_char multiplier) 6983{ 6984 unsigned char scntl3; 6985 unsigned char stest1; 6986 scntl3 = INB(nc_scntl3); 6987 stest1 = INB(nc_stest1); 6988 6989 np->multiplier = 1; 6990 6991 if (multiplier > 1) { 6992 np->multiplier = multiplier; 6993 np->clock_khz = 40000 * multiplier; 6994 } else { 6995 if ((scntl3 & 7) == 0) { 6996 unsigned f1, f2; 6997 /* throw away first result */ 6998 (void) ncrgetfreq (np, 11); 6999 f1 = ncrgetfreq (np, 11); 7000 f2 = ncrgetfreq (np, 11); 7001 7002 if (bootverbose >= 2) 7003 printf ("\tNCR clock is %uKHz, %uKHz\n", f1, f2); 7004 if (f1 > f2) f1 = f2; /* trust lower result */ 7005 if (f1 > 45000) { 7006 scntl3 = 5; /* >45Mhz: assume 80MHz */ 7007 } else { 7008 scntl3 = 3; /* <45Mhz: assume 40MHz */ 7009 } 7010 } 7011 else if ((scntl3 & 7) == 5) 7012 np->clock_khz = 80000; /* Probably a 875 rev. 1 ? */ 7013 } 7014} 7015 7016/*=========================================================================*/ 7017 7018#ifdef NCR_TEKRAM_EEPROM 7019 7020struct tekram_eeprom_dev { 7021 u_char devmode; 7022#define TKR_PARCHK 0x01 7023#define TKR_TRYSYNC 0x02 7024#define TKR_ENDISC 0x04 7025#define TKR_STARTUNIT 0x08 7026#define TKR_USETAGS 0x10 7027#define TKR_TRYWIDE 0x20 7028 u_char syncparam; /* max. sync transfer rate (table ?) */ 7029 u_char filler1; 7030 u_char filler2; 7031}; 7032 7033 7034struct tekram_eeprom { 7035 struct tekram_eeprom_dev 7036 dev[16]; 7037 u_char adaptid; 7038 u_char adaptmode; 7039#define TKR_ADPT_GT2DRV 0x01 7040#define TKR_ADPT_GT1GB 0x02 7041#define TKR_ADPT_RSTBUS 0x04 7042#define TKR_ADPT_ACTNEG 0x08 7043#define TKR_ADPT_NOSEEK 0x10 7044#define TKR_ADPT_MORLUN 0x20 7045 u_char delay; /* unit ? ( table ??? ) */ 7046 u_char tags; /* use 4 times as many ... */ 7047 u_char filler[60]; 7048}; 7049 7050static void 7051tekram_write_bit (ncb_p np, int bit) 7052{ 7053 u_char val = 0x10 + ((bit & 1) << 1); 7054 7055 DELAY(10); 7056 OUTB (nc_gpreg, val); 7057 DELAY(10); 7058 OUTB (nc_gpreg, val | 0x04); 7059 DELAY(10); 7060 OUTB (nc_gpreg, val); 7061 DELAY(10); 7062} 7063 7064static int 7065tekram_read_bit (ncb_p np) 7066{ 7067 OUTB (nc_gpreg, 0x10); 7068 DELAY(10); 7069 OUTB (nc_gpreg, 0x14); 7070 DELAY(10); 7071 return INB (nc_gpreg) & 1; 7072} 7073 7074static u_short 7075read_tekram_eeprom_reg (ncb_p np, int reg) 7076{ 7077 int bit; 7078 u_short result = 0; 7079 int cmd = 0x80 | reg; 7080 7081 OUTB (nc_gpreg, 0x10); 7082 7083 tekram_write_bit (np, 1); 7084 for (bit = 7; bit >= 0; bit--) 7085 { 7086 tekram_write_bit (np, cmd >> bit); 7087 } 7088 7089 for (bit = 0; bit < 16; bit++) 7090 { 7091 result <<= 1; 7092 result |= tekram_read_bit (np); 7093 } 7094 7095 OUTB (nc_gpreg, 0x00); 7096 return result; 7097} 7098 7099static int 7100read_tekram_eeprom(ncb_p np, struct tekram_eeprom *buffer) 7101{ 7102 u_short *p = (u_short *) buffer; 7103 u_short sum = 0; 7104 int i; 7105 7106 if (INB (nc_gpcntl) != 0x09) 7107 { 7108 return 0; 7109 } 7110 for (i = 0; i < 64; i++) 7111 { 7112 u_short val; 7113if((i&0x0f) == 0) printf ("%02x:", i*2); 7114 val = read_tekram_eeprom_reg (np, i); 7115 if (p) 7116 *p++ = val; 7117 sum += val; 7118if((i&0x01) == 0x00) printf (" "); 7119 printf ("%02x%02x", val & 0xff, (val >> 8) & 0xff); 7120if((i&0x0f) == 0x0f) printf ("\n"); 7121 } 7122printf ("Sum = %04x\n", sum); 7123 return sum == 0x1234; 7124} 7125#endif /* NCR_TEKRAM_EEPROM */ 7126 7127static device_method_t ncr_methods[] = { 7128 /* Device interface */ 7129 DEVMETHOD(device_probe, ncr_probe), 7130 DEVMETHOD(device_attach, ncr_attach), 7131 7132 { 0, 0 } 7133}; 7134 7135static driver_t ncr_driver = { 7136 "ncr", 7137 ncr_methods, 7138 sizeof(struct ncb), 7139}; 7140 7141static devclass_t ncr_devclass; 7142 7143DRIVER_MODULE(ncr, pci, ncr_driver, ncr_devclass, 0, 0); 7144MODULE_DEPEND(ncr, cam, 1, 1, 1); 7145MODULE_DEPEND(ncr, pci, 1, 1, 1); 7146 7147/*=========================================================================*/ 7148#endif /* _KERNEL */ 7149