1/*-
2 * Copyright (c) 2012 The FreeBSD Foundation
3 * All rights reserved.
4 *
5 * This software was developed by Oleksandr Rybalko under sponsorship
6 * from the FreeBSD Foundation.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1.	Redistributions of source code must retain the above copyright
12 *	notice, this list of conditions and the following disclaimer.
13 * 2.	Redistributions in binary form must reproduce the above copyright
14 *	notice, this list of conditions and the following disclaimer in the
15 *	documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * $FreeBSD$
30 */
31
32#ifndef	_UART_DEV_IMX5XX_H
33#define	_UART_DEV_IMX5XX_H
34
35#define	IMXUART_URXD_REG	0x0000 /* UART Receiver Register */
36#define		IMXUART_URXD_CHARRDY		(1 << 15)
37#define		IMXUART_URXD_ERR		(1 << 14)
38#define		IMXUART_URXD_OVRRUN		(1 << 13)
39#define		IMXUART_URXD_FRMERR		(1 << 12)
40#define		IMXUART_URXD_BRK		(1 << 11)
41#define		IMXUART_URXD_PRERR		(1 << 10)
42#define		IMXUART_URXD_RX_DATA_MASK	0xff
43
44#define	IMXUART_UTXD_REG	0x0040 /* UART Transmitter Register */
45#define		IMXUART_UTXD_TX_DATA_MASK	0xff
46
47#define	IMXUART_UCR1_REG	0x0080 /* UART Control Register 1 */
48#define		IMXUART_UCR1_ADEN		(1 << 15)
49#define		IMXUART_UCR1_ADBR		(1 << 14)
50#define		IMXUART_UCR1_TRDYEN		(1 << 13)
51#define		IMXUART_UCR1_IDEN		(1 << 12)
52#define		IMXUART_UCR1_ICD_MASK		(3 << 10)
53#define		IMXUART_UCR1_ICD_IDLE4		(0 << 10)
54#define		IMXUART_UCR1_ICD_IDLE8		(1 << 10)
55#define		IMXUART_UCR1_ICD_IDLE16		(2 << 10)
56#define		IMXUART_UCR1_ICD_IDLE32		(3 << 10)
57#define		IMXUART_UCR1_RRDYEN		(1 << 9)
58#define		IMXUART_UCR1_RXDMAEN		(1 << 8)
59#define		IMXUART_UCR1_IREN		(1 << 7)
60#define		IMXUART_UCR1_TXMPTYEN		(1 << 6)
61#define		IMXUART_UCR1_RTSDEN		(1 << 5)
62#define		IMXUART_UCR1_SNDBRK		(1 << 4)
63#define		IMXUART_UCR1_TXDMAEN		(1 << 3)
64#define		IMXUART_UCR1_ATDMAEN		(1 << 2)
65#define		IMXUART_UCR1_DOZE		(1 << 1)
66#define		IMXUART_UCR1_UARTEN		(1 << 0)
67
68#define	IMXUART_UCR2_REG	0x0084 /* UART Control Register 2 */
69#define		IMXUART_UCR2_ESCI		(1 << 15)
70#define		IMXUART_UCR2_IRTS		(1 << 14)
71#define		IMXUART_UCR2_CTSC		(1 << 13)
72#define		IMXUART_UCR2_CTS		(1 << 12)
73#define		IMXUART_UCR2_ESCEN		(1 << 11)
74#define		IMXUART_UCR2_RTEC_MASK		(3 << 9)
75#define		IMXUART_UCR2_RTEC_REDGE		(0 << 9)
76#define		IMXUART_UCR2_RTEC_FEDGE		(1 << 9)
77#define		IMXUART_UCR2_RTEC_EDGE		(2 << 9)
78#define		IMXUART_UCR2_PREN		(1 << 8)
79#define		IMXUART_UCR2_PROE		(1 << 7)
80#define		IMXUART_UCR2_STPB		(1 << 6)
81#define		IMXUART_UCR2_WS			(1 << 5)
82#define		IMXUART_UCR2_RTSEN		(1 << 4)
83#define		IMXUART_UCR2_ATEN		(1 << 3)
84#define		IMXUART_UCR2_TXEN		(1 << 2)
85#define		IMXUART_UCR2_RXEN		(1 << 1)
86#define		IMXUART_UCR2_N_SRST		(1 << 0)
87
88#define	IMXUART_UCR3_REG	0x0088 /* UART Control Register 3 */
89#define		IMXUART_UCR3_DPEC_MASK		(3 << 14)
90#define		IMXUART_UCR3_DPEC_REDGE		(0 << 14)
91#define		IMXUART_UCR3_DPEC_FEDGE		(1 << 14)
92#define		IMXUART_UCR3_DPEC_EDGE		(2 << 14)
93#define		IMXUART_UCR3_DTREN		(1 << 13)
94#define		IMXUART_UCR3_PARERREN		(1 << 12)
95#define		IMXUART_UCR3_FRAERREN		(1 << 11)
96#define		IMXUART_UCR3_DSR		(1 << 10)
97#define		IMXUART_UCR3_DCD		(1 << 9)
98#define		IMXUART_UCR3_RI			(1 << 8)
99#define		IMXUART_UCR3_ADNIMP		(1 << 7)
100#define		IMXUART_UCR3_RXDSEN		(1 << 6)
101#define		IMXUART_UCR3_AIRINTEN		(1 << 5)
102#define		IMXUART_UCR3_AWAKEN		(1 << 4)
103#define		IMXUART_UCR3_DTRDEN		(1 << 3)
104#define		IMXUART_UCR3_RXDMUXSEL		(1 << 2)
105#define		IMXUART_UCR3_INVT		(1 << 1)
106#define		IMXUART_UCR3_ACIEN		(1 << 0)
107
108#define	IMXUART_UCR4_REG	0x008c /* UART Control Register 4 */
109#define		IMXUART_UCR4_CTSTL_MASK		(0x3f << 10)
110#define		IMXUART_UCR4_CTSTL_SHIFT	10
111#define		IMXUART_UCR4_INVR		(1 << 9)
112#define		IMXUART_UCR4_ENIRI		(1 << 8)
113#define		IMXUART_UCR4_WKEN		(1 << 7)
114#define		IMXUART_UCR4_IDDMAEN		(1 << 6)
115#define		IMXUART_UCR4_IRSC		(1 << 5)
116#define		IMXUART_UCR4_LPBYP		(1 << 4)
117#define		IMXUART_UCR4_TCEN		(1 << 3)
118#define		IMXUART_UCR4_BKEN		(1 << 2)
119#define		IMXUART_UCR4_OREN		(1 << 1)
120#define		IMXUART_UCR4_DREN		(1 << 0)
121
122#define	IMXUART_UFCR_REG	0x0090 /* UART FIFO Control Register */
123#define		IMXUART_UFCR_TXTL_MASK		(0x3f << 10)
124#define		IMXUART_UFCR_TXTL_SHIFT		10
125#define		IMXUART_UFCR_RFDIV_MASK		(0x07 << 7)
126#define		IMXUART_UFCR_RFDIV_SHIFT	7
127#define		IMXUART_UFCR_RFDIV_SHIFT	7
128#define		IMXUART_UFCR_RFDIV_DIV6		(0 << 7)
129#define		IMXUART_UFCR_RFDIV_DIV5		(1 << 7)
130#define		IMXUART_UFCR_RFDIV_DIV4		(2 << 7)
131#define		IMXUART_UFCR_RFDIV_DIV3		(3 << 7)
132#define		IMXUART_UFCR_RFDIV_DIV2		(4 << 7)
133#define		IMXUART_UFCR_RFDIV_DIV1		(5 << 7)
134#define		IMXUART_UFCR_RFDIV_DIV7		(6 << 7)
135#define		IMXUART_UFCR_DCEDTE		(1 << 6)
136#define		IMXUART_UFCR_RXTL_MASK		0x0000003f
137#define		IMXUART_UFCR_RXTL_SHIFT		0
138
139#define	IMXUART_USR1_REG	0x0094 /* UART Status Register 1 */
140#define		IMXUART_USR1_PARITYERR		(1 << 15)
141#define		IMXUART_USR1_RTSS		(1 << 14)
142#define		IMXUART_USR1_TRDY		(1 << 13)
143#define		IMXUART_USR1_RTSD		(1 << 12)
144#define		IMXUART_USR1_ESCF		(1 << 11)
145#define		IMXUART_USR1_FRAMERR		(1 << 10)
146#define		IMXUART_USR1_RRDY		(1 << 9)
147#define		IMXUART_USR1_AGTIM		(1 << 8)
148#define		IMXUART_USR1_DTRD		(1 << 7)
149#define		IMXUART_USR1_RXDS		(1 << 6)
150#define		IMXUART_USR1_AIRINT		(1 << 5)
151#define		IMXUART_USR1_AWAKE		(1 << 4)
152/* 6040 5008 XXX */
153
154#define	IMXUART_USR2_REG	0x0098 /* UART Status Register 2 */
155#define		IMXUART_USR2_ADET		(1 << 15)
156#define		IMXUART_USR2_TXFE		(1 << 14)
157#define		IMXUART_USR2_DTRF		(1 << 13)
158#define		IMXUART_USR2_IDLE		(1 << 12)
159#define		IMXUART_USR2_ACST		(1 << 11)
160#define		IMXUART_USR2_RIDELT		(1 << 10)
161#define		IMXUART_USR2_RIIN		(1 << 9)
162#define		IMXUART_USR2_IRINT		(1 << 8)
163#define		IMXUART_USR2_WAKE		(1 << 7)
164#define		IMXUART_USR2_DCDDELT		(1 << 6)
165#define		IMXUART_USR2_DCDIN		(1 << 5)
166#define		IMXUART_USR2_RTSF		(1 << 4)
167#define		IMXUART_USR2_TXDC		(1 << 3)
168#define		IMXUART_USR2_BRCD		(1 << 2)
169#define		IMXUART_USR2_ORE		(1 << 1)
170#define		IMXUART_USR2_RDR		(1 << 0)
171
172#define	IMXUART_UESC_REG	0x009c /* UART Escape Character Register */
173#define		IMXUART_UESC_ESC_CHAR_MASK	0x000000ff
174
175#define	IMXUART_UTIM_REG	0x00a0 /* UART Escape Timer Register */
176#define		IMXUART_UTIM_TIM_MASK		0x00000fff
177
178#define	IMXUART_UBIR_REG	0x00a4 /* UART BRM Incremental Register */
179#define		IMXUART_UBIR_INC_MASK		0x0000ffff
180
181#define	IMXUART_UBMR_REG	0x00a8 /* UART BRM Modulator Register */
182#define		IMXUART_UBMR_MOD_MASK		0x0000ffff
183
184#define	IMXUART_UBRC_REG	0x00ac /* UART Baud Rate Count Register */
185#define		IMXUART_UBRC_BCNT_MASK		0x0000ffff
186
187#define	IMXUART_ONEMS_REG	0x00b0 /* UART One Millisecond Register */
188#define		IMXUART_ONEMS_ONEMS_MASK	0x00ffffff
189
190#define	IMXUART_UTS_REG		0x00b4 /* UART Test Register */
191#define		IMXUART_UTS_FRCPERR		(1 << 13)
192#define		IMXUART_UTS_LOOP		(1 << 12)
193#define		IMXUART_UTS_DBGEN		(1 << 11)
194#define		IMXUART_UTS_LOOPIR		(1 << 10)
195#define		IMXUART_UTS_RXDBG		(1 << 9)
196#define		IMXUART_UTS_TXEMPTY		(1 << 6)
197#define		IMXUART_UTS_RXEMPTY		(1 << 5)
198#define		IMXUART_UTS_TXFULL		(1 << 4)
199#define		IMXUART_UTS_RXFULL		(1 << 3)
200#define		IMXUART_UTS_SOFTRST		(1 << 0)
201
202#define	REG(_r)		IMXUART_ ## _r ## _REG
203#define	FLD(_r, _v)	IMXUART_ ## _r ## _ ## _v
204
205#define	GETREG(bas, reg)						\
206		bus_space_read_4((bas)->bst, (bas)->bsh, (reg))
207#define	SETREG(bas, reg, value)						\
208		bus_space_write_4((bas)->bst, (bas)->bsh, (reg), (value))
209
210#define	CLR(_bas, _r, _b)						\
211		SETREG((_bas), (_r), GETREG((_bas), (_r)) & ~(_b))
212#define	SET(_bas, _r, _b)						\
213		SETREG((_bas), (_r), GETREG((_bas), (_r)) | (_b))
214#define	IS_SET(_bas, _r, _b)						\
215		((GETREG((_bas), (_r)) & (_b)) ? 1 : 0)
216
217#define	ENA(_bas, _r, _b)	SET((_bas), REG(_r), FLD(_r, _b))
218#define	DIS(_bas, _r, _b)	CLR((_bas), REG(_r), FLD(_r, _b))
219#define	IS(_bas, _r, _b)	IS_SET((_bas), REG(_r), FLD(_r, _b))
220
221
222#endif	/* _UART_DEV_IMX5XX_H */
223