1/*- 2 * Copyright (c) 2003 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29#ifndef _DEV_UART_BUS_H_ 30#define _DEV_UART_BUS_H_ 31 32#ifndef KLD_MODULE 33#include "opt_uart.h" 34#endif 35 36#include <sys/serial.h> 37#include <sys/timepps.h> 38 39/* Drain and flush targets. */ 40#define UART_DRAIN_RECEIVER 0x0001 41#define UART_DRAIN_TRANSMITTER 0x0002 42#define UART_FLUSH_RECEIVER UART_DRAIN_RECEIVER 43#define UART_FLUSH_TRANSMITTER UART_DRAIN_TRANSMITTER 44 45/* Received character status bits. */ 46#define UART_STAT_BREAK 0x0100 47#define UART_STAT_FRAMERR 0x0200 48#define UART_STAT_OVERRUN 0x0400 49#define UART_STAT_PARERR 0x0800 50 51#ifdef UART_PPS_ON_CTS 52#define UART_SIG_DPPS SER_DCTS 53#define UART_SIG_PPS SER_CTS 54#else 55#define UART_SIG_DPPS SER_DDCD 56#define UART_SIG_PPS SER_DCD 57#endif 58 59/* UART_IOCTL() requests */ 60#define UART_IOCTL_BREAK 1 61#define UART_IOCTL_IFLOW 2 62#define UART_IOCTL_OFLOW 3 63#define UART_IOCTL_BAUD 4 64 65/* 66 * UART class & instance (=softc) 67 */ 68struct uart_class { 69 KOBJ_CLASS_FIELDS; 70 struct uart_ops *uc_ops; /* Low-level console operations. */ 71 u_int uc_range; /* Bus space address range. */ 72 u_int uc_rclk; /* Default rclk for this device. */ 73}; 74 75struct uart_softc { 76 KOBJ_FIELDS; 77 struct uart_class *sc_class; 78 struct uart_bas sc_bas; 79 device_t sc_dev; 80 81 struct mtx sc_hwmtx_s; /* Spinlock protecting hardware. */ 82 struct mtx *sc_hwmtx; 83 84 struct resource *sc_rres; /* Register resource. */ 85 int sc_rrid; 86 int sc_rtype; /* SYS_RES_{IOPORT|MEMORY}. */ 87 struct resource *sc_ires; /* Interrupt resource. */ 88 void *sc_icookie; 89 int sc_irid; 90 struct callout sc_timer; 91 92 int sc_callout:1; /* This UART is opened for callout. */ 93 int sc_fastintr:1; /* This UART uses fast interrupts. */ 94 int sc_hwiflow:1; /* This UART has HW input flow ctl. */ 95 int sc_hwoflow:1; /* This UART has HW output flow ctl. */ 96 int sc_leaving:1; /* This UART is going away. */ 97 int sc_opened:1; /* This UART is open for business. */ 98 int sc_polled:1; /* This UART has no interrupts. */ 99 int sc_txbusy:1; /* This UART is transmitting. */ 100 int sc_isquelch:1; /* This UART has input squelched. */ 101 102 struct uart_devinfo *sc_sysdev; /* System device (or NULL). */ 103 104 int sc_altbrk; /* State for alt break sequence. */ 105 uint32_t sc_hwsig; /* Signal state. Used by HW driver. */ 106 107 /* Receiver data. */ 108 uint16_t *sc_rxbuf; 109 int sc_rxbufsz; 110 int sc_rxput; 111 int sc_rxget; 112 int sc_rxfifosz; /* Size of RX FIFO. */ 113 114 /* Transmitter data. */ 115 uint8_t *sc_txbuf; 116 int sc_txdatasz; 117 int sc_txfifosz; /* Size of TX FIFO and buffer. */ 118 119 /* Pulse capturing support (PPS). */ 120 struct pps_state sc_pps; 121 122 /* Upper layer data. */ 123 void *sc_softih; 124 uint32_t sc_ttypend; 125 union { 126 /* TTY specific data. */ 127 struct { 128 struct tty *tp; 129 } u_tty; 130 /* Keyboard specific data. */ 131 struct { 132 } u_kbd; 133 } sc_u; 134}; 135 136extern devclass_t uart_devclass; 137extern char uart_driver_name[]; 138 139int uart_bus_attach(device_t dev); 140int uart_bus_detach(device_t dev); 141int uart_bus_resume(device_t dev); 142serdev_intr_t *uart_bus_ihand(device_t dev, int ipend); 143int uart_bus_ipend(device_t dev); 144int uart_bus_probe(device_t dev, int regshft, int rclk, int rid, int chan); 145int uart_bus_sysdev(device_t dev); 146 147void uart_sched_softih(struct uart_softc *, uint32_t); 148 149int uart_tty_attach(struct uart_softc *); 150int uart_tty_detach(struct uart_softc *); 151void uart_tty_intr(void *arg); 152 153/* 154 * Receive buffer operations. 155 */ 156static __inline int 157uart_rx_empty(struct uart_softc *sc) 158{ 159 return ((sc->sc_rxget == sc->sc_rxput) ? 1 : 0); 160} 161 162static __inline int 163uart_rx_full(struct uart_softc *sc) 164{ 165 return ((sc->sc_rxput + 1 < sc->sc_rxbufsz) 166 ? (sc->sc_rxput + 1 == sc->sc_rxget) : (sc->sc_rxget == 0)); 167} 168 169static __inline int 170uart_rx_get(struct uart_softc *sc) 171{ 172 int ptr, xc; 173 174 ptr = sc->sc_rxget; 175 if (ptr == sc->sc_rxput) 176 return (-1); 177 xc = sc->sc_rxbuf[ptr++]; 178 sc->sc_rxget = (ptr < sc->sc_rxbufsz) ? ptr : 0; 179 return (xc); 180} 181 182static __inline int 183uart_rx_next(struct uart_softc *sc) 184{ 185 int ptr; 186 187 ptr = sc->sc_rxget; 188 if (ptr == sc->sc_rxput) 189 return (-1); 190 ptr += 1; 191 sc->sc_rxget = (ptr < sc->sc_rxbufsz) ? ptr : 0; 192 return (0); 193} 194 195static __inline int 196uart_rx_peek(struct uart_softc *sc) 197{ 198 int ptr; 199 200 ptr = sc->sc_rxget; 201 return ((ptr == sc->sc_rxput) ? -1 : sc->sc_rxbuf[ptr]); 202} 203 204static __inline int 205uart_rx_put(struct uart_softc *sc, int xc) 206{ 207 int ptr; 208 209 ptr = (sc->sc_rxput + 1 < sc->sc_rxbufsz) ? sc->sc_rxput + 1 : 0; 210 if (ptr == sc->sc_rxget) 211 return (ENOSPC); 212 sc->sc_rxbuf[sc->sc_rxput] = xc; 213 sc->sc_rxput = ptr; 214 return (0); 215} 216 217#endif /* _DEV_UART_BUS_H_ */ 218