if_iwnreg.h revision 253897
1/* $FreeBSD: head/sys/dev/iwn/if_iwnreg.h 253897 2013-08-02 21:23:28Z adrian $ */ 2/* $OpenBSD: if_iwnreg.h,v 1.40 2010/05/05 19:41:57 damien Exp $ */ 3 4/*- 5 * Copyright (c) 2007, 2008 6 * Damien Bergamini <damien.bergamini@free.fr> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21#define IWN_TX_RING_COUNT 256 22#define IWN_TX_RING_LOMARK 192 23#define IWN_TX_RING_HIMARK 224 24#define IWN_RX_RING_COUNT_LOG 6 25#define IWN_RX_RING_COUNT (1 << IWN_RX_RING_COUNT_LOG) 26 27#define IWN4965_NTXQUEUES 16 28#define IWN5000_NTXQUEUES 20 29 30#define IWN4965_FIRSTAGGQUEUE 7 31#define IWN5000_FIRSTAGGQUEUE 10 32 33#define IWN4965_NDMACHNLS 7 34#define IWN5000_NDMACHNLS 8 35 36#define IWN_SRVC_DMACHNL 9 37 38#define IWN_ICT_SIZE 4096 39#define IWN_ICT_COUNT (IWN_ICT_SIZE / sizeof (uint32_t)) 40 41/* Maximum number of DMA segments for TX. */ 42#define IWN_MAX_SCATTER 20 43 44/* RX buffers must be large enough to hold a full 4K A-MPDU. */ 45#define IWN_RBUF_SIZE (4 * 1024) 46 47#if defined(__LP64__) 48/* HW supports 36-bit DMA addresses. */ 49#define IWN_LOADDR(paddr) ((uint32_t)(paddr)) 50#define IWN_HIADDR(paddr) (((paddr) >> 32) & 0xf) 51#else 52#define IWN_LOADDR(paddr) (paddr) 53#define IWN_HIADDR(paddr) (0) 54#endif 55 56/* 57 * Control and status registers. 58 */ 59#define IWN_HW_IF_CONFIG 0x000 60#define IWN_INT_COALESCING 0x004 61#define IWN_INT_PERIODIC 0x005 /* use IWN_WRITE_1 */ 62#define IWN_INT 0x008 63#define IWN_INT_MASK 0x00c 64#define IWN_FH_INT 0x010 65#define IWN_GPIO_IN 0x018 /* read external chip pins */ 66#define IWN_RESET 0x020 67#define IWN_GP_CNTRL 0x024 68#define IWN_HW_REV 0x028 69#define IWN_EEPROM 0x02c 70#define IWN_EEPROM_GP 0x030 71#define IWN_OTP_GP 0x034 72#define IWN_GIO 0x03c 73#define IWN_GP_UCODE 0x048 74#define IWN_GP_DRIVER 0x050 75#define IWN_UCODE_GP1 0x054 76#define IWN_UCODE_GP1_SET 0x058 77#define IWN_UCODE_GP1_CLR 0x05c 78#define IWN_UCODE_GP2 0x060 79#define IWN_LED 0x094 80#define IWN_DRAM_INT_TBL 0x0a0 81#define IWN_SHADOW_REG_CTRL 0x0a8 82#define IWN_GIO_CHICKEN 0x100 83#define IWN_ANA_PLL 0x20c 84#define IWN_HW_REV_WA 0x22c 85#define IWN_DBG_HPET_MEM 0x240 86#define IWN_DBG_LINK_PWR_MGMT 0x250 87/* Need nic_lock for use above */ 88#define IWN_MEM_RADDR 0x40c 89#define IWN_MEM_WADDR 0x410 90#define IWN_MEM_WDATA 0x418 91#define IWN_MEM_RDATA 0x41c 92#define IWN_PRPH_WADDR 0x444 93#define IWN_PRPH_RADDR 0x448 94#define IWN_PRPH_WDATA 0x44c 95#define IWN_PRPH_RDATA 0x450 96#define IWN_HBUS_TARG_WRPTR 0x460 97 98/* 99 * Flow-Handler registers. 100 */ 101#define IWN_FH_TFBD_CTRL0(qid) (0x1900 + (qid) * 8) 102#define IWN_FH_TFBD_CTRL1(qid) (0x1904 + (qid) * 8) 103#define IWN_FH_KW_ADDR 0x197c 104#define IWN_FH_SRAM_ADDR(qid) (0x19a4 + (qid) * 4) 105#define IWN_FH_CBBC_QUEUE(qid) (0x19d0 + (qid) * 4) 106#define IWN_FH_STATUS_WPTR 0x1bc0 107#define IWN_FH_RX_BASE 0x1bc4 108#define IWN_FH_RX_WPTR 0x1bc8 109#define IWN_FH_RX_CONFIG 0x1c00 110#define IWN_FH_RX_STATUS 0x1c44 111#define IWN_FH_TX_CONFIG(qid) (0x1d00 + (qid) * 32) 112#define IWN_FH_TXBUF_STATUS(qid) (0x1d08 + (qid) * 32) 113#define IWN_FH_TX_CHICKEN 0x1e98 114#define IWN_FH_TX_STATUS 0x1eb0 115 116/* 117 * TX scheduler registers. 118 */ 119#define IWN_SCHED_BASE 0xa02c00 120#define IWN_SCHED_SRAM_ADDR (IWN_SCHED_BASE + 0x000) 121#define IWN5000_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x008) 122#define IWN4965_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x010) 123#define IWN5000_SCHED_TXFACT (IWN_SCHED_BASE + 0x010) 124#define IWN4965_SCHED_TXFACT (IWN_SCHED_BASE + 0x01c) 125#define IWN4965_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x064 + (qid) * 4) 126#define IWN5000_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x068 + (qid) * 4) 127#define IWN4965_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0d0) 128#define IWN4965_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x0e4) 129#define IWN5000_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0e8) 130#define IWN4965_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x104 + (qid) * 4) 131#define IWN5000_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x108) 132#define IWN5000_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x10c + (qid) * 4) 133#define IWN5000_SCHED_AGGR_SEL (IWN_SCHED_BASE + 0x248) 134 135/* 136 * Offsets in TX scheduler's SRAM. 137 */ 138#define IWN4965_SCHED_CTX_OFF 0x380 139#define IWN4965_SCHED_CTX_LEN 416 140#define IWN4965_SCHED_QUEUE_OFFSET(qid) (0x380 + (qid) * 8) 141#define IWN4965_SCHED_TRANS_TBL(qid) (0x500 + (qid) * 2) 142#define IWN5000_SCHED_CTX_OFF 0x600 143#define IWN5000_SCHED_CTX_LEN 520 144#define IWN5000_SCHED_QUEUE_OFFSET(qid) (0x600 + (qid) * 8) 145#define IWN5000_SCHED_TRANS_TBL(qid) (0x7e0 + (qid) * 2) 146 147/* 148 * NIC internal memory offsets. 149 */ 150#define IWN_APMG_CLK_CTRL 0x3000 151#define IWN_APMG_CLK_EN 0x3004 152#define IWN_APMG_CLK_DIS 0x3008 153#define IWN_APMG_PS 0x300c 154#define IWN_APMG_DIGITAL_SVR 0x3058 155#define IWN_APMG_ANALOG_SVR 0x306c 156#define IWN_APMG_PCI_STT 0x3010 157#define IWN_BSM_WR_CTRL 0x3400 158#define IWN_BSM_WR_MEM_SRC 0x3404 159#define IWN_BSM_WR_MEM_DST 0x3408 160#define IWN_BSM_WR_DWCOUNT 0x340c 161#define IWN_BSM_DRAM_TEXT_ADDR 0x3490 162#define IWN_BSM_DRAM_TEXT_SIZE 0x3494 163#define IWN_BSM_DRAM_DATA_ADDR 0x3498 164#define IWN_BSM_DRAM_DATA_SIZE 0x349c 165#define IWN_BSM_SRAM_BASE 0x3800 166 167/* Possible flags for register IWN_HW_IF_CONFIG. */ 168#define IWN_HW_IF_CONFIG_4965_R (1 << 4) 169#define IWN_HW_IF_CONFIG_MAC_SI (1 << 8) 170#define IWN_HW_IF_CONFIG_RADIO_SI (1 << 9) 171#define IWN_HW_IF_CONFIG_EEPROM_LOCKED (1 << 21) 172#define IWN_HW_IF_CONFIG_NIC_READY (1 << 22) 173#define IWN_HW_IF_CONFIG_HAP_WAKE_L1A (1 << 23) 174#define IWN_HW_IF_CONFIG_PREPARE_DONE (1 << 25) 175#define IWN_HW_IF_CONFIG_PREPARE (1 << 27) 176 177/* Possible values for register IWN_INT_PERIODIC. */ 178#define IWN_INT_PERIODIC_DIS 0x00 179#define IWN_INT_PERIODIC_ENA 0xff 180 181/* Possible flags for registers IWN_PRPH_RADDR/IWN_PRPH_WADDR. */ 182#define IWN_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24) 183 184/* Possible values for IWN_BSM_WR_MEM_DST. */ 185#define IWN_FW_TEXT_BASE 0x00000000 186#define IWN_FW_DATA_BASE 0x00800000 187 188/* Possible flags for register IWN_RESET. */ 189#define IWN_RESET_NEVO (1 << 0) 190#define IWN_RESET_SW (1 << 7) 191#define IWN_RESET_MASTER_DISABLED (1 << 8) 192#define IWN_RESET_STOP_MASTER (1 << 9) 193#define IWN_RESET_LINK_PWR_MGMT_DIS (1 << 31) 194 195/* Possible flags for register IWN_GP_CNTRL. */ 196#define IWN_GP_CNTRL_MAC_ACCESS_ENA (1 << 0) 197#define IWN_GP_CNTRL_MAC_CLOCK_READY (1 << 0) 198#define IWN_GP_CNTRL_INIT_DONE (1 << 2) 199#define IWN_GP_CNTRL_MAC_ACCESS_REQ (1 << 3) 200#define IWN_GP_CNTRL_SLEEP (1 << 4) 201#define IWN_GP_CNTRL_RFKILL (1 << 27) 202 203/* Possible flags for register IWN_GIO_CHICKEN. */ 204#define IWN_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23) 205#define IWN_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29) 206 207/* Possible flags for register IWN_GIO. */ 208#define IWN_GIO_L0S_ENA (1 << 1) 209 210/* Possible flags for register IWN_GP_DRIVER. */ 211#define IWN_GP_DRIVER_RADIO_3X3_HYB (0 << 0) 212#define IWN_GP_DRIVER_RADIO_2X2_HYB (1 << 0) 213#define IWN_GP_DRIVER_RADIO_2X2_IPA (2 << 0) 214#define IWN_GP_DRIVER_CALIB_VER6 (1 << 2) 215#define IWN_GP_DRIVER_6050_1X2 (1 << 3) 216 217/* Possible flags for register IWN_UCODE_GP1_CLR. */ 218#define IWN_UCODE_GP1_RFKILL (1 << 1) 219#define IWN_UCODE_GP1_CMD_BLOCKED (1 << 2) 220#define IWN_UCODE_GP1_CTEMP_STOP_RF (1 << 3) 221 222/* Possible flags/values for register IWN_LED. */ 223#define IWN_LED_BSM_CTRL (1 << 5) 224#define IWN_LED_OFF 0x00000038 225#define IWN_LED_ON 0x00000078 226 227/* Possible flags for register IWN_DRAM_INT_TBL. */ 228#define IWN_DRAM_INT_TBL_WRAP_CHECK (1 << 27) 229#define IWN_DRAM_INT_TBL_ENABLE (1 << 31) 230 231/* Possible values for register IWN_ANA_PLL. */ 232#define IWN_ANA_PLL_INIT 0x00880300 233 234/* Possible flags for register IWN_FH_RX_STATUS. */ 235#define IWN_FH_RX_STATUS_IDLE (1 << 24) 236 237/* Possible flags for register IWN_BSM_WR_CTRL. */ 238#define IWN_BSM_WR_CTRL_START_EN (1 << 30) 239#define IWN_BSM_WR_CTRL_START (1 << 31) 240 241/* Possible flags for register IWN_INT. */ 242#define IWN_INT_ALIVE (1 << 0) 243#define IWN_INT_WAKEUP (1 << 1) 244#define IWN_INT_SW_RX (1 << 3) 245#define IWN_INT_CT_REACHED (1 << 6) 246#define IWN_INT_RF_TOGGLED (1 << 7) 247#define IWN_INT_SW_ERR (1 << 25) 248#define IWN_INT_SCHED (1 << 26) 249#define IWN_INT_FH_TX (1 << 27) 250#define IWN_INT_RX_PERIODIC (1 << 28) 251#define IWN_INT_HW_ERR (1 << 29) 252#define IWN_INT_FH_RX (1 << 31) 253 254/* Shortcut. */ 255#define IWN_INT_MASK_DEF \ 256 (IWN_INT_SW_ERR | IWN_INT_HW_ERR | IWN_INT_FH_TX | \ 257 IWN_INT_FH_RX | IWN_INT_ALIVE | IWN_INT_WAKEUP | \ 258 IWN_INT_SW_RX | IWN_INT_CT_REACHED | IWN_INT_RF_TOGGLED) 259 260/* Possible flags for register IWN_FH_INT. */ 261#define IWN_FH_INT_TX_CHNL(x) (1 << (x)) 262#define IWN_FH_INT_RX_CHNL(x) (1 << ((x) + 16)) 263#define IWN_FH_INT_HI_PRIOR (1 << 30) 264/* Shortcuts for the above. */ 265#define IWN_FH_INT_TX \ 266 (IWN_FH_INT_TX_CHNL(0) | IWN_FH_INT_TX_CHNL(1)) 267#define IWN_FH_INT_RX \ 268 (IWN_FH_INT_RX_CHNL(0) | IWN_FH_INT_RX_CHNL(1) | IWN_FH_INT_HI_PRIOR) 269 270/* Possible flags/values for register IWN_FH_TX_CONFIG. */ 271#define IWN_FH_TX_CONFIG_DMA_PAUSE 0 272#define IWN_FH_TX_CONFIG_DMA_ENA (1 << 31) 273#define IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD (1 << 20) 274 275/* Possible flags/values for register IWN_FH_TXBUF_STATUS. */ 276#define IWN_FH_TXBUF_STATUS_TBNUM(x) ((x) << 20) 277#define IWN_FH_TXBUF_STATUS_TBIDX(x) ((x) << 12) 278#define IWN_FH_TXBUF_STATUS_TFBD_VALID 3 279 280/* Possible flags for register IWN_FH_TX_CHICKEN. */ 281#define IWN_FH_TX_CHICKEN_SCHED_RETRY (1 << 1) 282 283/* Possible flags for register IWN_FH_TX_STATUS. */ 284#define IWN_FH_TX_STATUS_IDLE(chnl) (1 << ((chnl) + 16)) 285 286/* Possible flags for register IWN_FH_RX_CONFIG. */ 287#define IWN_FH_RX_CONFIG_ENA (1 << 31) 288#define IWN_FH_RX_CONFIG_NRBD(x) ((x) << 20) 289#define IWN_FH_RX_CONFIG_RB_SIZE_8K (1 << 16) 290#define IWN_FH_RX_CONFIG_SINGLE_FRAME (1 << 15) 291#define IWN_FH_RX_CONFIG_IRQ_DST_HOST (1 << 12) 292#define IWN_FH_RX_CONFIG_RB_TIMEOUT(x) ((x) << 4) 293#define IWN_FH_RX_CONFIG_IGN_RXF_EMPTY (1 << 2) 294 295/* Possible flags for register IWN_FH_TX_CONFIG. */ 296#define IWN_FH_TX_CONFIG_DMA_ENA (1 << 31) 297#define IWN_FH_TX_CONFIG_DMA_CREDIT_ENA (1 << 3) 298 299/* Possible flags for register IWN_EEPROM. */ 300#define IWN_EEPROM_READ_VALID (1 << 0) 301#define IWN_EEPROM_CMD (1 << 1) 302 303/* Possible flags for register IWN_EEPROM_GP. */ 304#define IWN_EEPROM_GP_IF_OWNER 0x00000180 305 306/* Possible flags for register IWN_OTP_GP. */ 307#define IWN_OTP_GP_DEV_SEL_OTP (1 << 16) 308#define IWN_OTP_GP_RELATIVE_ACCESS (1 << 17) 309#define IWN_OTP_GP_ECC_CORR_STTS (1 << 20) 310#define IWN_OTP_GP_ECC_UNCORR_STTS (1 << 21) 311 312/* Possible flags for register IWN_SCHED_QUEUE_STATUS. */ 313#define IWN4965_TXQ_STATUS_ACTIVE 0x0007fc01 314#define IWN4965_TXQ_STATUS_INACTIVE 0x0007fc00 315#define IWN4965_TXQ_STATUS_AGGR_ENA (1 << 5 | 1 << 8) 316#define IWN4965_TXQ_STATUS_CHGACT (1 << 10) 317#define IWN5000_TXQ_STATUS_ACTIVE 0x00ff0018 318#define IWN5000_TXQ_STATUS_INACTIVE 0x00ff0010 319#define IWN5000_TXQ_STATUS_CHGACT (1 << 19) 320 321/* Possible flags for registers IWN_APMG_CLK_*. */ 322#define IWN_APMG_CLK_CTRL_DMA_CLK_RQT (1 << 9) 323#define IWN_APMG_CLK_CTRL_BSM_CLK_RQT (1 << 11) 324 325/* Possible flags for register IWN_APMG_PS. */ 326#define IWN_APMG_PS_EARLY_PWROFF_DIS (1 << 22) 327#define IWN_APMG_PS_PWR_SRC(x) ((x) << 24) 328#define IWN_APMG_PS_PWR_SRC_VMAIN 0 329#define IWN_APMG_PS_PWR_SRC_VAUX 2 330#define IWN_APMG_PS_PWR_SRC_MASK IWN_APMG_PS_PWR_SRC(3) 331#define IWN_APMG_PS_RESET_REQ (1 << 26) 332 333/* Possible flags for register IWN_APMG_DIGITAL_SVR. */ 334#define IWN_APMG_DIGITAL_SVR_VOLTAGE(x) (((x) & 0xf) << 5) 335#define IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK \ 336 IWN_APMG_DIGITAL_SVR_VOLTAGE(0xf) 337#define IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32 \ 338 IWN_APMG_DIGITAL_SVR_VOLTAGE(3) 339 340/* Possible flags for IWN_APMG_PCI_STT. */ 341#define IWN_APMG_PCI_STT_L1A_DIS (1 << 11) 342 343/* Possible flags for register IWN_BSM_DRAM_TEXT_SIZE. */ 344#define IWN_FW_UPDATED (1 << 31) 345 346#define IWN_SCHED_WINSZ 64 347#define IWN_SCHED_LIMIT 64 348#define IWN4965_SCHED_COUNT 512 349#define IWN5000_SCHED_COUNT (IWN_TX_RING_COUNT + IWN_SCHED_WINSZ) 350#define IWN4965_SCHEDSZ (IWN4965_NTXQUEUES * IWN4965_SCHED_COUNT * 2) 351#define IWN5000_SCHEDSZ (IWN5000_NTXQUEUES * IWN5000_SCHED_COUNT * 2) 352 353struct iwn_tx_desc { 354 uint8_t reserved1[3]; 355 uint8_t nsegs; 356 struct { 357 uint32_t addr; 358 uint16_t len; 359 } __packed segs[IWN_MAX_SCATTER]; 360 /* Pad to 128 bytes. */ 361 uint32_t reserved2; 362} __packed; 363 364struct iwn_rx_status { 365 uint16_t closed_count; 366 uint16_t closed_rx_count; 367 uint16_t finished_count; 368 uint16_t finished_rx_count; 369 uint32_t reserved[2]; 370} __packed; 371 372struct iwn_rx_desc { 373 uint32_t len; 374 uint8_t type; 375#define IWN_UC_READY 1 376#define IWN_ADD_NODE_DONE 24 377#define IWN_TX_DONE 28 378#define IWN5000_CALIBRATION_RESULT 102 379#define IWN5000_CALIBRATION_DONE 103 380#define IWN_START_SCAN 130 381#define IWN_STOP_SCAN 132 382#define IWN_RX_STATISTICS 156 383#define IWN_BEACON_STATISTICS 157 384#define IWN_STATE_CHANGED 161 385#define IWN_BEACON_MISSED 162 386#define IWN_RX_PHY 192 387#define IWN_MPDU_RX_DONE 193 388#define IWN_RX_DONE 195 389#define IWN_RX_COMPRESSED_BA 197 390 391 uint8_t flags; 392 uint8_t idx; 393 uint8_t qid; 394} __packed; 395 396/* Possible RX status flags. */ 397#define IWN_RX_NO_CRC_ERR (1 << 0) 398#define IWN_RX_NO_OVFL_ERR (1 << 1) 399/* Shortcut for the above. */ 400#define IWN_RX_NOERROR (IWN_RX_NO_CRC_ERR | IWN_RX_NO_OVFL_ERR) 401#define IWN_RX_MPDU_MIC_OK (1 << 6) 402#define IWN_RX_CIPHER_MASK (7 << 8) 403#define IWN_RX_CIPHER_CCMP (2 << 8) 404#define IWN_RX_MPDU_DEC (1 << 11) 405#define IWN_RX_DECRYPT_MASK (3 << 11) 406#define IWN_RX_DECRYPT_OK (3 << 11) 407 408struct iwn_tx_cmd { 409 uint8_t code; 410#define IWN_CMD_RXON 16 411#define IWN_CMD_RXON_ASSOC 17 412#define IWN_CMD_EDCA_PARAMS 19 413#define IWN_CMD_TIMING 20 414#define IWN_CMD_ADD_NODE 24 415#define IWN_CMD_TX_DATA 28 416#define IWN_CMD_LINK_QUALITY 78 417#define IWN_CMD_SET_LED 72 418#define IWN5000_CMD_WIMAX_COEX 90 419#define IWN5000_CMD_CALIB_CONFIG 101 420#define IWN5000_CMD_CALIB_RESULT 102 421#define IWN5000_CMD_CALIB_COMPLETE 103 422#define IWN_CMD_SET_POWER_MODE 119 423#define IWN_CMD_SCAN 128 424#define IWN_CMD_SCAN_RESULTS 131 425#define IWN_CMD_TXPOWER_DBM 149 426#define IWN_CMD_TXPOWER 151 427#define IWN5000_CMD_TX_ANT_CONFIG 152 428#define IWN_CMD_BT_COEX 155 429#define IWN_CMD_GET_STATISTICS 156 430#define IWN_CMD_SET_CRITICAL_TEMP 164 431#define IWN_CMD_SET_SENSITIVITY 168 432#define IWN_CMD_PHY_CALIB 176 433#define IWN_CMD_BT_COEX_PRIOTABLE 204 434#define IWN_CMD_BT_COEX_PROT 205 435 436 uint8_t flags; 437 uint8_t idx; 438 uint8_t qid; 439 uint8_t data[136]; 440} __packed; 441 442/* Antenna flags, used in various commands. */ 443#define IWN_ANT_A (1 << 0) 444#define IWN_ANT_B (1 << 1) 445#define IWN_ANT_C (1 << 2) 446/* Shortcuts. */ 447#define IWN_ANT_AB (IWN_ANT_A | IWN_ANT_B) 448#define IWN_ANT_BC (IWN_ANT_B | IWN_ANT_C) 449#define IWN_ANT_ABC (IWN_ANT_A | IWN_ANT_B | IWN_ANT_C) 450 451/* Structure for command IWN_CMD_RXON. */ 452struct iwn_rxon { 453 uint8_t myaddr[IEEE80211_ADDR_LEN]; 454 uint16_t reserved1; 455 uint8_t bssid[IEEE80211_ADDR_LEN]; 456 uint16_t reserved2; 457 uint8_t wlap[IEEE80211_ADDR_LEN]; 458 uint16_t reserved3; 459 uint8_t mode; 460#define IWN_MODE_HOSTAP 1 461#define IWN_MODE_STA 3 462#define IWN_MODE_IBSS 4 463#define IWN_MODE_MONITOR 6 464 465 uint8_t air; 466 uint16_t rxchain; 467#define IWN_RXCHAIN_DRIVER_FORCE (1 << 0) 468#define IWN_RXCHAIN_VALID(x) (((x) & IWN_ANT_ABC) << 1) 469#define IWN_RXCHAIN_FORCE_SEL(x) (((x) & IWN_ANT_ABC) << 4) 470#define IWN_RXCHAIN_FORCE_MIMO_SEL(x) (((x) & IWN_ANT_ABC) << 7) 471#define IWN_RXCHAIN_IDLE_COUNT(x) ((x) << 10) 472#define IWN_RXCHAIN_MIMO_COUNT(x) ((x) << 12) 473#define IWN_RXCHAIN_MIMO_FORCE (1 << 14) 474 475 uint8_t ofdm_mask; 476 uint8_t cck_mask; 477 uint16_t associd; 478 uint32_t flags; 479#define IWN_RXON_24GHZ (1 << 0) 480#define IWN_RXON_CCK (1 << 1) 481#define IWN_RXON_AUTO (1 << 2) 482#define IWN_RXON_SHSLOT (1 << 4) 483#define IWN_RXON_SHPREAMBLE (1 << 5) 484#define IWN_RXON_NODIVERSITY (1 << 7) 485#define IWN_RXON_ANTENNA_A (1 << 8) 486#define IWN_RXON_ANTENNA_B (1 << 9) 487#define IWN_RXON_TSF (1 << 15) 488#define IWN_RXON_HT_HT40MINUS (1 << 22) 489#define IWN_RXON_HT_PROTMODE(x) (x << 23) 490#define IWN_RXON_HT_MODEPURE40 (1 << 25) 491#define IWN_RXON_HT_MODEMIXED (2 << 25) 492#define IWN_RXON_CTS_TO_SELF (1 << 30) 493 494 uint32_t filter; 495#define IWN_FILTER_PROMISC (1 << 0) 496#define IWN_FILTER_CTL (1 << 1) 497#define IWN_FILTER_MULTICAST (1 << 2) 498#define IWN_FILTER_NODECRYPT (1 << 3) 499#define IWN_FILTER_BSS (1 << 5) 500#define IWN_FILTER_BEACON (1 << 6) 501 502 uint8_t chan; 503 uint8_t reserved4; 504 uint8_t ht_single_mask; 505 uint8_t ht_dual_mask; 506 /* The following fields are for >=5000 Series only. */ 507 uint8_t ht_triple_mask; 508 uint8_t reserved5; 509 uint16_t acquisition; 510 uint16_t reserved6; 511} __packed; 512 513#define IWN4965_RXONSZ (sizeof (struct iwn_rxon) - 6) 514#define IWN5000_RXONSZ (sizeof (struct iwn_rxon)) 515 516/* Structure for command IWN_CMD_ASSOCIATE. */ 517struct iwn_assoc { 518 uint32_t flags; 519 uint32_t filter; 520 uint8_t ofdm_mask; 521 uint8_t cck_mask; 522 uint16_t reserved; 523} __packed; 524 525/* Structure for command IWN_CMD_EDCA_PARAMS. */ 526struct iwn_edca_params { 527 uint32_t flags; 528#define IWN_EDCA_UPDATE (1 << 0) 529#define IWN_EDCA_TXOP (1 << 4) 530 531 struct { 532 uint16_t cwmin; 533 uint16_t cwmax; 534 uint8_t aifsn; 535 uint8_t reserved; 536 uint16_t txoplimit; 537 } __packed ac[WME_NUM_AC]; 538} __packed; 539 540/* Structure for command IWN_CMD_TIMING. */ 541struct iwn_cmd_timing { 542 uint64_t tstamp; 543 uint16_t bintval; 544 uint16_t atim; 545 uint32_t binitval; 546 uint16_t lintval; 547 uint16_t reserved; 548} __packed; 549 550/* Structure for command IWN_CMD_ADD_NODE. */ 551struct iwn_node_info { 552 uint8_t control; 553#define IWN_NODE_UPDATE (1 << 0) 554 555 uint8_t reserved1[3]; 556 557 uint8_t macaddr[IEEE80211_ADDR_LEN]; 558 uint16_t reserved2; 559 uint8_t id; 560#define IWN_ID_BSS 0 561#define IWN5000_ID_BROADCAST 15 562#define IWN4965_ID_BROADCAST 31 563 564 uint8_t flags; 565#define IWN_FLAG_SET_KEY (1 << 0) 566#define IWN_FLAG_SET_DISABLE_TID (1 << 1) 567#define IWN_FLAG_SET_TXRATE (1 << 2) 568#define IWN_FLAG_SET_ADDBA (1 << 3) 569#define IWN_FLAG_SET_DELBA (1 << 4) 570 571 uint16_t reserved3; 572 uint16_t kflags; 573#define IWN_KFLAG_CCMP (1 << 1) 574#define IWN_KFLAG_MAP (1 << 3) 575#define IWN_KFLAG_KID(kid) ((kid) << 8) 576#define IWN_KFLAG_INVALID (1 << 11) 577#define IWN_KFLAG_GROUP (1 << 14) 578 579 uint8_t tsc2; /* TKIP TSC2 */ 580 uint8_t reserved4; 581 uint16_t ttak[5]; 582 uint8_t kid; 583 uint8_t reserved5; 584 uint8_t key[16]; 585 /* The following 3 fields are for 5000 Series only. */ 586 uint64_t tsc; 587 uint8_t rxmic[8]; 588 uint8_t txmic[8]; 589 590 uint32_t htflags; 591#define IWN_SMPS_MIMO_PROT (1 << 17) 592#define IWN_AMDPU_SIZE_FACTOR(x) ((x) << 19) 593#define IWN_NODE_HT40 (1 << 21) 594#define IWN_SMPS_MIMO_DIS (1 << 22) 595#define IWN_AMDPU_DENSITY(x) ((x) << 23) 596 597 uint32_t mask; 598 uint16_t disable_tid; 599 uint16_t reserved6; 600 uint8_t addba_tid; 601 uint8_t delba_tid; 602 uint16_t addba_ssn; 603 uint32_t reserved7; 604} __packed; 605 606struct iwn4965_node_info { 607 uint8_t control; 608 uint8_t reserved1[3]; 609 uint8_t macaddr[IEEE80211_ADDR_LEN]; 610 uint16_t reserved2; 611 uint8_t id; 612 uint8_t flags; 613 uint16_t reserved3; 614 uint16_t kflags; 615 uint8_t tsc2; /* TKIP TSC2 */ 616 uint8_t reserved4; 617 uint16_t ttak[5]; 618 uint8_t kid; 619 uint8_t reserved5; 620 uint8_t key[16]; 621 uint32_t htflags; 622 uint32_t mask; 623 uint16_t disable_tid; 624 uint16_t reserved6; 625 uint8_t addba_tid; 626 uint8_t delba_tid; 627 uint16_t addba_ssn; 628 uint32_t reserved7; 629} __packed; 630 631#define IWN_RFLAG_MCS (1 << 8) 632#define IWN_RFLAG_CCK (1 << 9) 633#define IWN_RFLAG_GREENFIELD (1 << 10) 634#define IWN_RFLAG_HT40 (1 << 11) 635#define IWN_RFLAG_DUPLICATE (1 << 12) 636#define IWN_RFLAG_SGI (1 << 13) 637#define IWN_RFLAG_ANT(x) ((x) << 14) 638 639/* Structure for command IWN_CMD_TX_DATA. */ 640struct iwn_cmd_data { 641 uint16_t len; 642 uint16_t lnext; 643 uint32_t flags; 644#define IWN_TX_NEED_PROTECTION (1 << 0) /* 5000 only */ 645#define IWN_TX_NEED_RTS (1 << 1) 646#define IWN_TX_NEED_CTS (1 << 2) 647#define IWN_TX_NEED_ACK (1 << 3) 648#define IWN_TX_LINKQ (1 << 4) 649#define IWN_TX_IMM_BA (1 << 6) 650#define IWN_TX_FULL_TXOP (1 << 7) 651#define IWN_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */ 652#define IWN_TX_AUTO_SEQ (1 << 13) 653#define IWN_TX_MORE_FRAG (1 << 14) 654#define IWN_TX_INSERT_TSTAMP (1 << 16) 655#define IWN_TX_NEED_PADDING (1 << 20) 656 657 uint32_t scratch; 658 uint32_t rate; 659 660 uint8_t id; 661 uint8_t security; 662#define IWN_CIPHER_WEP40 1 663#define IWN_CIPHER_CCMP 2 664#define IWN_CIPHER_TKIP 3 665#define IWN_CIPHER_WEP104 9 666 667 uint8_t linkq; 668 uint8_t reserved2; 669 uint8_t key[16]; 670 uint16_t fnext; 671 uint16_t reserved3; 672 uint32_t lifetime; 673#define IWN_LIFETIME_INFINITE 0xffffffff 674 675 uint32_t loaddr; 676 uint8_t hiaddr; 677 uint8_t rts_ntries; 678 uint8_t data_ntries; 679 uint8_t tid; 680 uint16_t timeout; 681 uint16_t txop; 682} __packed; 683 684/* Structure for command IWN_CMD_LINK_QUALITY. */ 685#define IWN_MAX_TX_RETRIES 16 686struct iwn_cmd_link_quality { 687 uint8_t id; 688 uint8_t reserved1; 689 uint16_t ctl; 690 uint8_t flags; 691 uint8_t mimo; 692 uint8_t antmsk_1stream; 693 uint8_t antmsk_2stream; 694 uint8_t ridx[WME_NUM_AC]; 695 uint16_t ampdu_limit; 696 uint8_t ampdu_threshold; 697 uint8_t ampdu_max; 698 uint32_t reserved2; 699 uint32_t retry[IWN_MAX_TX_RETRIES]; 700 uint32_t reserved3; 701} __packed; 702 703/* Structure for command IWN_CMD_SET_LED. */ 704struct iwn_cmd_led { 705 uint32_t unit; /* multiplier (in usecs) */ 706 uint8_t which; 707#define IWN_LED_ACTIVITY 1 708#define IWN_LED_LINK 2 709 710 uint8_t off; 711 uint8_t on; 712 uint8_t reserved; 713} __packed; 714 715/* Structure for command IWN5000_CMD_WIMAX_COEX. */ 716struct iwn5000_wimax_coex { 717 uint32_t flags; 718#define IWN_WIMAX_COEX_STA_TABLE_VALID (1 << 0) 719#define IWN_WIMAX_COEX_UNASSOC_WA_UNMASK (1 << 2) 720#define IWN_WIMAX_COEX_ASSOC_WA_UNMASK (1 << 3) 721#define IWN_WIMAX_COEX_ENABLE (1 << 7) 722 723 struct iwn5000_wimax_event { 724 uint8_t request; 725 uint8_t window; 726 uint8_t reserved; 727 uint8_t flags; 728 } __packed events[16]; 729} __packed; 730 731/* Structures for command IWN5000_CMD_CALIB_CONFIG. */ 732struct iwn5000_calib_elem { 733 uint32_t enable; 734 uint32_t start; 735#define IWN5000_CALIB_DC (1 << 1) 736 737 uint32_t send; 738 uint32_t apply; 739 uint32_t reserved; 740} __packed; 741 742struct iwn5000_calib_status { 743 struct iwn5000_calib_elem once; 744 struct iwn5000_calib_elem perd; 745 uint32_t flags; 746} __packed; 747 748struct iwn5000_calib_config { 749 struct iwn5000_calib_status ucode; 750 struct iwn5000_calib_status driver; 751 uint32_t reserved; 752} __packed; 753 754/* Structure for command IWN_CMD_SET_POWER_MODE. */ 755struct iwn_pmgt_cmd { 756 uint16_t flags; 757#define IWN_PS_ALLOW_SLEEP (1 << 0) 758#define IWN_PS_NOTIFY (1 << 1) 759#define IWN_PS_SLEEP_OVER_DTIM (1 << 2) 760#define IWN_PS_PCI_PMGT (1 << 3) 761#define IWN_PS_FAST_PD (1 << 4) 762 763 uint8_t keepalive; 764 uint8_t debug; 765 uint32_t rxtimeout; 766 uint32_t txtimeout; 767 uint32_t intval[5]; 768 uint32_t beacons; 769} __packed; 770 771/* Structures for command IWN_CMD_SCAN. */ 772struct iwn_scan_essid { 773 uint8_t id; 774 uint8_t len; 775 uint8_t data[IEEE80211_NWID_LEN]; 776} __packed; 777 778struct iwn_scan_hdr { 779 uint16_t len; 780 uint8_t reserved1; 781 uint8_t nchan; 782 uint16_t quiet_time; 783 uint16_t quiet_threshold; 784 uint16_t crc_threshold; 785 uint16_t rxchain; 786 uint32_t max_svc; /* background scans */ 787 uint32_t pause_svc; /* background scans */ 788 uint32_t flags; 789 uint32_t filter; 790 791 /* Followed by a struct iwn_cmd_data. */ 792 /* Followed by an array of 20 structs iwn_scan_essid. */ 793 /* Followed by probe request body. */ 794 /* Followed by an array of ``nchan'' structs iwn_scan_chan. */ 795} __packed; 796 797struct iwn_scan_chan { 798 uint32_t flags; 799#define IWN_CHAN_ACTIVE (1 << 0) 800#define IWN_CHAN_NPBREQS(x) (((1 << (x)) - 1) << 1) 801 802 uint16_t chan; 803 uint8_t rf_gain; 804 uint8_t dsp_gain; 805 uint16_t active; /* msecs */ 806 uint16_t passive; /* msecs */ 807} __packed; 808 809/* Maximum size of a scan command. */ 810#define IWN_SCAN_MAXSZ (MCLBYTES - 4) 811 812/* Structure for command IWN_CMD_TXPOWER (4965AGN only.) */ 813#define IWN_RIDX_MAX 32 814struct iwn4965_cmd_txpower { 815 uint8_t band; 816 uint8_t reserved1; 817 uint8_t chan; 818 uint8_t reserved2; 819 struct { 820 uint8_t rf_gain[2]; 821 uint8_t dsp_gain[2]; 822 } __packed power[IWN_RIDX_MAX + 1]; 823} __packed; 824 825/* Structure for command IWN_CMD_TXPOWER_DBM (5000 Series only.) */ 826struct iwn5000_cmd_txpower { 827 int8_t global_limit; /* in half-dBm */ 828#define IWN5000_TXPOWER_AUTO 0x7f 829#define IWN5000_TXPOWER_MAX_DBM 16 830 831 uint8_t flags; 832#define IWN5000_TXPOWER_NO_CLOSED (1 << 6) 833 834 int8_t srv_limit; /* in half-dBm */ 835 uint8_t reserved; 836} __packed; 837 838/* Structures for command IWN_CMD_BLUETOOTH. */ 839struct iwn_bluetooth { 840 uint8_t flags; 841#define IWN_BT_COEX_CHAN_ANN (1 << 0) 842#define IWN_BT_COEX_BT_PRIO (1 << 1) 843#define IWN_BT_COEX_2_WIRE (1 << 2) 844 845 uint8_t lead_time; 846#define IWN_BT_LEAD_TIME_DEF 30 847 848 uint8_t max_kill; 849#define IWN_BT_MAX_KILL_DEF 5 850 851 uint8_t reserved; 852 uint32_t kill_ack; 853 uint32_t kill_cts; 854} __packed; 855 856struct iwn6000_btcoex_config { 857 uint8_t flags; 858 uint8_t lead_time; 859 uint8_t max_kill; 860 uint8_t bt3_t7_timer; 861 uint32_t kill_ack; 862 uint32_t kill_cts; 863 uint8_t sample_time; 864 uint8_t bt3_t2_timer; 865 uint16_t bt4_reaction; 866 uint32_t lookup_table[12]; 867 uint16_t bt4_decision; 868 uint16_t valid; 869 uint8_t prio_boost; 870 uint8_t tx_prio_boost; 871 uint16_t rx_prio_boost; 872} __packed; 873 874struct iwn_btcoex_priotable { 875 uint8_t calib_init1; 876 uint8_t calib_init2; 877 uint8_t calib_periodic_low1; 878 uint8_t calib_periodic_low2; 879 uint8_t calib_periodic_high1; 880 uint8_t calib_periodic_high2; 881 uint8_t dtim; 882 uint8_t scan52; 883 uint8_t scan24; 884 uint8_t reserved[7]; 885} __packed; 886 887struct iwn_btcoex_prot { 888 uint8_t open; 889 uint8_t type; 890 uint8_t reserved[2]; 891} __packed; 892 893/* Structure for command IWN_CMD_SET_CRITICAL_TEMP. */ 894struct iwn_critical_temp { 895 uint32_t reserved; 896 uint32_t tempM; 897 uint32_t tempR; 898/* degK <-> degC conversion macros. */ 899#define IWN_CTOK(c) ((c) + 273) 900#define IWN_KTOC(k) ((k) - 273) 901#define IWN_CTOMUK(c) (((c) * 1000000) + 273150000) 902} __packed; 903 904/* Structures for command IWN_CMD_SET_SENSITIVITY. */ 905struct iwn_sensitivity_cmd { 906 uint16_t which; 907#define IWN_SENSITIVITY_DEFAULTTBL 0 908#define IWN_SENSITIVITY_WORKTBL 1 909 910 uint16_t energy_cck; 911 uint16_t energy_ofdm; 912 uint16_t corr_ofdm_x1; 913 uint16_t corr_ofdm_mrc_x1; 914 uint16_t corr_cck_mrc_x4; 915 uint16_t corr_ofdm_x4; 916 uint16_t corr_ofdm_mrc_x4; 917 uint16_t corr_barker; 918 uint16_t corr_barker_mrc; 919 uint16_t corr_cck_x4; 920 uint16_t energy_ofdm_th; 921} __packed; 922 923struct iwn_enhanced_sensitivity_cmd { 924 uint16_t which; 925 uint16_t energy_cck; 926 uint16_t energy_ofdm; 927 uint16_t corr_ofdm_x1; 928 uint16_t corr_ofdm_mrc_x1; 929 uint16_t corr_cck_mrc_x4; 930 uint16_t corr_ofdm_x4; 931 uint16_t corr_ofdm_mrc_x4; 932 uint16_t corr_barker; 933 uint16_t corr_barker_mrc; 934 uint16_t corr_cck_x4; 935 uint16_t energy_ofdm_th; 936 /* "Enhanced" part. */ 937 uint16_t ina_det_ofdm; 938 uint16_t ina_det_cck; 939 uint16_t corr_11_9_en; 940 uint16_t ofdm_det_slope_mrc; 941 uint16_t ofdm_det_icept_mrc; 942 uint16_t ofdm_det_slope; 943 uint16_t ofdm_det_icept; 944 uint16_t cck_det_slope_mrc; 945 uint16_t cck_det_icept_mrc; 946 uint16_t cck_det_slope; 947 uint16_t cck_det_icept; 948 uint16_t reserved; 949} __packed; 950 951/* Structures for command IWN_CMD_PHY_CALIB. */ 952struct iwn_phy_calib { 953 uint8_t code; 954#define IWN4965_PHY_CALIB_DIFF_GAIN 7 955#define IWN5000_PHY_CALIB_DC 8 956#define IWN5000_PHY_CALIB_LO 9 957#define IWN5000_PHY_CALIB_TX_IQ 11 958#define IWN5000_PHY_CALIB_CRYSTAL 15 959#define IWN5000_PHY_CALIB_BASE_BAND 16 960#define IWN5000_PHY_CALIB_TX_IQ_PERIODIC 17 961#define IWN5000_PHY_CALIB_TEMP_OFFSET 18 962 963#define IWN5000_PHY_CALIB_RESET_NOISE_GAIN 18 964#define IWN5000_PHY_CALIB_NOISE_GAIN 19 965 966 uint8_t group; 967 uint8_t ngroups; 968 uint8_t isvalid; 969} __packed; 970 971struct iwn5000_phy_calib_crystal { 972 uint8_t code; 973 uint8_t group; 974 uint8_t ngroups; 975 uint8_t isvalid; 976 977 uint8_t cap_pin[2]; 978 uint8_t reserved[2]; 979} __packed; 980 981struct iwn5000_phy_calib_temp_offset { 982 uint8_t code; 983 uint8_t group; 984 uint8_t ngroups; 985 uint8_t isvalid; 986 int16_t offset; 987#define IWN_DEFAULT_TEMP_OFFSET 2700 988 989 uint16_t reserved; 990} __packed; 991 992struct iwn_phy_calib_gain { 993 uint8_t code; 994 uint8_t group; 995 uint8_t ngroups; 996 uint8_t isvalid; 997 998 int8_t gain[3]; 999 uint8_t reserved; 1000} __packed; 1001 1002/* Structure for command IWN_CMD_SPECTRUM_MEASUREMENT. */ 1003struct iwn_spectrum_cmd { 1004 uint16_t len; 1005 uint8_t token; 1006 uint8_t id; 1007 uint8_t origin; 1008 uint8_t periodic; 1009 uint16_t timeout; 1010 uint32_t start; 1011 uint32_t reserved1; 1012 uint32_t flags; 1013 uint32_t filter; 1014 uint16_t nchan; 1015 uint16_t reserved2; 1016 struct { 1017 uint32_t duration; 1018 uint8_t chan; 1019 uint8_t type; 1020#define IWN_MEASUREMENT_BASIC (1 << 0) 1021#define IWN_MEASUREMENT_CCA (1 << 1) 1022#define IWN_MEASUREMENT_RPI_HISTOGRAM (1 << 2) 1023#define IWN_MEASUREMENT_NOISE_HISTOGRAM (1 << 3) 1024#define IWN_MEASUREMENT_FRAME (1 << 4) 1025#define IWN_MEASUREMENT_IDLE (1 << 7) 1026 1027 uint16_t reserved; 1028 } __packed chan[10]; 1029} __packed; 1030 1031/* Structure for IWN_UC_READY notification. */ 1032#define IWN_NATTEN_GROUPS 5 1033struct iwn_ucode_info { 1034 uint8_t minor; 1035 uint8_t major; 1036 uint16_t reserved1; 1037 uint8_t revision[8]; 1038 uint8_t type; 1039 uint8_t subtype; 1040#define IWN_UCODE_RUNTIME 0 1041#define IWN_UCODE_INIT 9 1042 1043 uint16_t reserved2; 1044 uint32_t logptr; 1045 uint32_t errptr; 1046 uint32_t tstamp; 1047 uint32_t valid; 1048 1049 /* The following fields are for UCODE_INIT only. */ 1050 int32_t volt; 1051 struct { 1052 int32_t chan20MHz; 1053 int32_t chan40MHz; 1054 } __packed temp[4]; 1055 int32_t atten[IWN_NATTEN_GROUPS][2]; 1056} __packed; 1057 1058/* Structures for IWN_TX_DONE notification. */ 1059#define IWN_TX_SUCCESS 0x00 1060#define IWN_TX_FAIL 0x80 /* all failures have 0x80 set */ 1061#define IWN_TX_FAIL_SHORT_LIMIT 0x82 /* too many RTS retries */ 1062#define IWN_TX_FAIL_LONG_LIMIT 0x83 /* too many retries */ 1063#define IWN_TX_FAIL_FIFO_UNDERRRUN 0x84 /* tx fifo not kept running */ 1064#define IWN_TX_FAIL_DEST_IN_PS 0x88 /* sta found in power save */ 1065#define IWN_TX_FAIL_TX_LOCKED 0x90 /* waiting to see traffic */ 1066 1067struct iwn4965_tx_stat { 1068 uint8_t nframes; 1069 uint8_t btkillcnt; 1070 uint8_t rtsfailcnt; 1071 uint8_t ackfailcnt; 1072 uint32_t rate; 1073 uint16_t duration; 1074 uint16_t reserved; 1075 uint32_t power[2]; 1076 uint32_t status; 1077} __packed; 1078 1079struct iwn5000_tx_stat { 1080 uint8_t nframes; 1081 uint8_t btkillcnt; 1082 uint8_t rtsfailcnt; 1083 uint8_t ackfailcnt; 1084 uint32_t rate; 1085 uint16_t duration; 1086 uint16_t reserved; 1087 uint32_t power[2]; 1088 uint32_t info; 1089 uint16_t seq; 1090 uint16_t len; 1091 uint8_t tlc; 1092 uint8_t ratid; 1093 uint8_t fc[2]; 1094 uint16_t status; 1095 uint16_t sequence; 1096} __packed; 1097 1098/* Structure for IWN_BEACON_MISSED notification. */ 1099struct iwn_beacon_missed { 1100 uint32_t consecutive; 1101 uint32_t total; 1102 uint32_t expected; 1103 uint32_t received; 1104} __packed; 1105 1106/* Structure for IWN_MPDU_RX_DONE notification. */ 1107struct iwn_rx_mpdu { 1108 uint16_t len; 1109 uint16_t reserved; 1110} __packed; 1111 1112/* Structures for IWN_RX_DONE and IWN_MPDU_RX_DONE notifications. */ 1113struct iwn4965_rx_phystat { 1114 uint16_t antenna; 1115 uint16_t agc; 1116 uint8_t rssi[6]; 1117} __packed; 1118 1119struct iwn5000_rx_phystat { 1120 uint32_t reserved1; 1121 uint32_t agc; 1122 uint16_t rssi[3]; 1123} __packed; 1124 1125struct iwn_rx_stat { 1126 uint8_t phy_len; 1127 uint8_t cfg_phy_len; 1128#define IWN_STAT_MAXLEN 20 1129 1130 uint8_t id; 1131 uint8_t reserved1; 1132 uint64_t tstamp; 1133 uint32_t beacon; 1134 uint16_t flags; 1135#define IWN_STAT_FLAG_SHPREAMBLE (1 << 2) 1136 1137 uint16_t chan; 1138 uint8_t phybuf[32]; 1139 uint32_t rate; 1140 uint16_t len; 1141 uint16_t reserve3; 1142} __packed; 1143 1144#define IWN_RSSI_TO_DBM 44 1145 1146/* Structure for IWN_RX_COMPRESSED_BA notification. */ 1147struct iwn_compressed_ba { 1148 uint8_t macaddr[IEEE80211_ADDR_LEN]; 1149 uint16_t reserved; 1150 uint8_t id; 1151 uint8_t tid; 1152 uint16_t seq; 1153 uint64_t bitmap; 1154 uint16_t qid; 1155 uint16_t ssn; 1156} __packed; 1157 1158/* Structure for IWN_START_SCAN notification. */ 1159struct iwn_start_scan { 1160 uint64_t tstamp; 1161 uint32_t tbeacon; 1162 uint8_t chan; 1163 uint8_t band; 1164 uint16_t reserved; 1165 uint32_t status; 1166} __packed; 1167 1168/* Structure for IWN_STOP_SCAN notification. */ 1169struct iwn_stop_scan { 1170 uint8_t nchan; 1171 uint8_t status; 1172 uint8_t reserved; 1173 uint8_t chan; 1174 uint64_t tsf; 1175} __packed; 1176 1177/* Structure for IWN_SPECTRUM_MEASUREMENT notification. */ 1178struct iwn_spectrum_notif { 1179 uint8_t id; 1180 uint8_t token; 1181 uint8_t idx; 1182 uint8_t state; 1183#define IWN_MEASUREMENT_START 0 1184#define IWN_MEASUREMENT_STOP 1 1185 1186 uint32_t start; 1187 uint8_t band; 1188 uint8_t chan; 1189 uint8_t type; 1190 uint8_t reserved1; 1191 uint32_t cca_ofdm; 1192 uint32_t cca_cck; 1193 uint32_t cca_time; 1194 uint8_t basic; 1195 uint8_t reserved2[3]; 1196 uint32_t ofdm[8]; 1197 uint32_t cck[8]; 1198 uint32_t stop; 1199 uint32_t status; 1200#define IWN_MEASUREMENT_OK 0 1201#define IWN_MEASUREMENT_CONCURRENT 1 1202#define IWN_MEASUREMENT_CSA_CONFLICT 2 1203#define IWN_MEASUREMENT_TGH_CONFLICT 3 1204#define IWN_MEASUREMENT_STOPPED 6 1205#define IWN_MEASUREMENT_TIMEOUT 7 1206#define IWN_MEASUREMENT_FAILED 8 1207} __packed; 1208 1209/* Structures for IWN_{RX,BEACON}_STATISTICS notification. */ 1210struct iwn_rx_phy_stats { 1211 uint32_t ina; 1212 uint32_t fina; 1213 uint32_t bad_plcp; 1214 uint32_t bad_crc32; 1215 uint32_t overrun; 1216 uint32_t eoverrun; 1217 uint32_t good_crc32; 1218 uint32_t fa; 1219 uint32_t bad_fina_sync; 1220 uint32_t sfd_timeout; 1221 uint32_t fina_timeout; 1222 uint32_t no_rts_ack; 1223 uint32_t rxe_limit; 1224 uint32_t ack; 1225 uint32_t cts; 1226 uint32_t ba_resp; 1227 uint32_t dsp_kill; 1228 uint32_t bad_mh; 1229 uint32_t rssi_sum; 1230 uint32_t reserved; 1231} __packed; 1232 1233struct iwn_rx_general_stats { 1234 uint32_t bad_cts; 1235 uint32_t bad_ack; 1236 uint32_t not_bss; 1237 uint32_t filtered; 1238 uint32_t bad_chan; 1239 uint32_t beacons; 1240 uint32_t missed_beacons; 1241 uint32_t adc_saturated; /* time in 0.8us */ 1242 uint32_t ina_searched; /* time in 0.8us */ 1243 uint32_t noise[3]; 1244 uint32_t flags; 1245 uint32_t load; 1246 uint32_t fa; 1247 uint32_t rssi[3]; 1248 uint32_t energy[3]; 1249} __packed; 1250 1251struct iwn_rx_ht_phy_stats { 1252 uint32_t bad_plcp; 1253 uint32_t overrun; 1254 uint32_t eoverrun; 1255 uint32_t good_crc32; 1256 uint32_t bad_crc32; 1257 uint32_t bad_mh; 1258 uint32_t good_ampdu_crc32; 1259 uint32_t ampdu; 1260 uint32_t fragment; 1261 uint32_t reserved; 1262} __packed; 1263 1264struct iwn_rx_stats { 1265 struct iwn_rx_phy_stats ofdm; 1266 struct iwn_rx_phy_stats cck; 1267 struct iwn_rx_general_stats general; 1268 struct iwn_rx_ht_phy_stats ht; 1269} __packed; 1270 1271struct iwn_tx_stats { 1272 uint32_t preamble; 1273 uint32_t rx_detected; 1274 uint32_t bt_defer; 1275 uint32_t bt_kill; 1276 uint32_t short_len; 1277 uint32_t cts_timeout; 1278 uint32_t ack_timeout; 1279 uint32_t exp_ack; 1280 uint32_t ack; 1281 uint32_t msdu; 1282 uint32_t busrt_err1; 1283 uint32_t burst_err2; 1284 uint32_t cts_collision; 1285 uint32_t ack_collision; 1286 uint32_t ba_timeout; 1287 uint32_t ba_resched; 1288 uint32_t query_ampdu; 1289 uint32_t query; 1290 uint32_t query_ampdu_frag; 1291 uint32_t query_mismatch; 1292 uint32_t not_ready; 1293 uint32_t underrun; 1294 uint32_t bt_ht_kill; 1295 uint32_t rx_ba_resp; 1296 uint32_t reserved[2]; 1297} __packed; 1298 1299struct iwn_general_stats { 1300 uint32_t temp; 1301 uint32_t temp_m; 1302 uint32_t burst_check; 1303 uint32_t burst; 1304 uint32_t reserved1[4]; 1305 uint32_t sleep; 1306 uint32_t slot_out; 1307 uint32_t slot_idle; 1308 uint32_t ttl_tstamp; 1309 uint32_t tx_ant_a; 1310 uint32_t tx_ant_b; 1311 uint32_t exec; 1312 uint32_t probe; 1313 uint32_t reserved2[2]; 1314 uint32_t rx_enabled; 1315 uint32_t reserved3[3]; 1316} __packed; 1317 1318struct iwn_stats { 1319 uint32_t flags; 1320 struct iwn_rx_stats rx; 1321 struct iwn_tx_stats tx; 1322 struct iwn_general_stats general; 1323} __packed; 1324 1325 1326/* Firmware error dump. */ 1327struct iwn_fw_dump { 1328 uint32_t valid; 1329 uint32_t id; 1330 uint32_t pc; 1331 uint32_t branch_link[2]; 1332 uint32_t interrupt_link[2]; 1333 uint32_t error_data[2]; 1334 uint32_t src_line; 1335 uint32_t tsf; 1336 uint32_t time[2]; 1337} __packed; 1338 1339/* TLV firmware header. */ 1340struct iwn_fw_tlv_hdr { 1341 uint32_t zero; /* Always 0, to differentiate from legacy. */ 1342 uint32_t signature; 1343#define IWN_FW_SIGNATURE 0x0a4c5749 /* "IWL\n" */ 1344 1345 uint8_t descr[64]; 1346 uint32_t rev; 1347#define IWN_FW_API(x) (((x) >> 8) & 0xff) 1348 1349 uint32_t build; 1350 uint64_t altmask; 1351} __packed; 1352 1353/* TLV header. */ 1354struct iwn_fw_tlv { 1355 uint16_t type; 1356#define IWN_FW_TLV_MAIN_TEXT 1 1357#define IWN_FW_TLV_MAIN_DATA 2 1358#define IWN_FW_TLV_INIT_TEXT 3 1359#define IWN_FW_TLV_INIT_DATA 4 1360#define IWN_FW_TLV_BOOT_TEXT 5 1361#define IWN_FW_TLV_PBREQ_MAXLEN 6 1362#define IWN_FW_TLV_ENH_SENS 14 1363#define IWN_FW_TLV_PHY_CALIB 15 1364 1365 uint16_t alt; 1366 uint32_t len; 1367} __packed; 1368 1369#define IWN4965_FW_TEXT_MAXSZ ( 96 * 1024) 1370#define IWN4965_FW_DATA_MAXSZ ( 40 * 1024) 1371#define IWN5000_FW_TEXT_MAXSZ (256 * 1024) 1372#define IWN5000_FW_DATA_MAXSZ ( 80 * 1024) 1373#define IWN_FW_BOOT_TEXT_MAXSZ 1024 1374#define IWN4965_FWSZ (IWN4965_FW_TEXT_MAXSZ + IWN4965_FW_DATA_MAXSZ) 1375#define IWN5000_FWSZ IWN5000_FW_TEXT_MAXSZ 1376 1377/* 1378 * Offsets into EEPROM. 1379 */ 1380#define IWN_EEPROM_MAC 0x015 1381#define IWN_EEPROM_SKU_CAP 0x045 1382#define IWN_EEPROM_RFCFG 0x048 1383#define IWN4965_EEPROM_DOMAIN 0x060 1384#define IWN4965_EEPROM_BAND1 0x063 1385#define IWN5000_EEPROM_REG 0x066 1386#define IWN5000_EEPROM_CAL 0x067 1387#define IWN4965_EEPROM_BAND2 0x072 1388#define IWN4965_EEPROM_BAND3 0x080 1389#define IWN4965_EEPROM_BAND4 0x08d 1390#define IWN4965_EEPROM_BAND5 0x099 1391#define IWN4965_EEPROM_BAND6 0x0a0 1392#define IWN4965_EEPROM_BAND7 0x0a8 1393#define IWN4965_EEPROM_MAXPOW 0x0e8 1394#define IWN4965_EEPROM_VOLTAGE 0x0e9 1395#define IWN4965_EEPROM_BANDS 0x0ea 1396/* Indirect offsets. */ 1397#define IWN5000_EEPROM_DOMAIN 0x001 1398#define IWN5000_EEPROM_BAND1 0x004 1399#define IWN5000_EEPROM_BAND2 0x013 1400#define IWN5000_EEPROM_BAND3 0x021 1401#define IWN5000_EEPROM_BAND4 0x02e 1402#define IWN5000_EEPROM_BAND5 0x03a 1403#define IWN5000_EEPROM_BAND6 0x041 1404#define IWN6000_EEPROM_BAND6 0x040 1405#define IWN5000_EEPROM_BAND7 0x049 1406#define IWN6000_EEPROM_ENHINFO 0x054 1407#define IWN5000_EEPROM_CRYSTAL 0x128 1408#define IWN5000_EEPROM_TEMP 0x12a 1409#define IWN5000_EEPROM_VOLT 0x12b 1410 1411/* Possible flags for IWN_EEPROM_SKU_CAP. */ 1412#define IWN_EEPROM_SKU_CAP_11N (1 << 6) 1413#define IWN_EEPROM_SKU_CAP_AMT (1 << 7) 1414#define IWN_EEPROM_SKU_CAP_IPAN (1 << 8) 1415 1416/* Possible flags for IWN_EEPROM_RFCFG. */ 1417#define IWN_RFCFG_TYPE(x) (((x) >> 0) & 0x3) 1418#define IWN_RFCFG_STEP(x) (((x) >> 2) & 0x3) 1419#define IWN_RFCFG_DASH(x) (((x) >> 4) & 0x3) 1420#define IWN_RFCFG_TXANTMSK(x) (((x) >> 8) & 0xf) 1421#define IWN_RFCFG_RXANTMSK(x) (((x) >> 12) & 0xf) 1422 1423struct iwn_eeprom_chan { 1424 uint8_t flags; 1425#define IWN_EEPROM_CHAN_VALID (1 << 0) 1426#define IWN_EEPROM_CHAN_IBSS (1 << 1) 1427#define IWN_EEPROM_CHAN_ACTIVE (1 << 3) 1428#define IWN_EEPROM_CHAN_RADAR (1 << 4) 1429 1430 int8_t maxpwr; 1431} __packed; 1432 1433struct iwn_eeprom_enhinfo { 1434 uint8_t flags; 1435#define IWN_ENHINFO_VALID 0x01 1436#define IWN_ENHINFO_5GHZ 0x02 1437#define IWN_ENHINFO_OFDM 0x04 1438#define IWN_ENHINFO_HT40 0x08 1439#define IWN_ENHINFO_HTAP 0x10 1440#define IWN_ENHINFO_RES1 0x20 1441#define IWN_ENHINFO_RES2 0x40 1442#define IWN_ENHINFO_COMMON 0x80 1443 1444 uint8_t chan; 1445 int8_t chain[3]; /* max power in half-dBm */ 1446 uint8_t reserved; 1447 int8_t mimo2; /* max power in half-dBm */ 1448 int8_t mimo3; /* max power in half-dBm */ 1449} __packed; 1450 1451struct iwn5000_eeprom_calib_hdr { 1452 uint8_t version; 1453 uint8_t pa_type; 1454 uint16_t volt; 1455} __packed; 1456 1457#define IWN_NSAMPLES 3 1458struct iwn4965_eeprom_chan_samples { 1459 uint8_t num; 1460 struct { 1461 uint8_t temp; 1462 uint8_t gain; 1463 uint8_t power; 1464 int8_t pa_det; 1465 } samples[2][IWN_NSAMPLES]; 1466} __packed; 1467 1468#define IWN_NBANDS 8 1469struct iwn4965_eeprom_band { 1470 uint8_t lo; /* low channel number */ 1471 uint8_t hi; /* high channel number */ 1472 struct iwn4965_eeprom_chan_samples chans[2]; 1473} __packed; 1474 1475/* 1476 * Offsets of channels descriptions in EEPROM. 1477 */ 1478static const uint32_t iwn4965_regulatory_bands[IWN_NBANDS] = { 1479 IWN4965_EEPROM_BAND1, 1480 IWN4965_EEPROM_BAND2, 1481 IWN4965_EEPROM_BAND3, 1482 IWN4965_EEPROM_BAND4, 1483 IWN4965_EEPROM_BAND5, 1484 IWN4965_EEPROM_BAND6, 1485 IWN4965_EEPROM_BAND7 1486}; 1487 1488static const uint32_t iwn5000_regulatory_bands[IWN_NBANDS] = { 1489 IWN5000_EEPROM_BAND1, 1490 IWN5000_EEPROM_BAND2, 1491 IWN5000_EEPROM_BAND3, 1492 IWN5000_EEPROM_BAND4, 1493 IWN5000_EEPROM_BAND5, 1494 IWN5000_EEPROM_BAND6, 1495 IWN5000_EEPROM_BAND7 1496}; 1497 1498static const uint32_t iwn6000_regulatory_bands[IWN_NBANDS] = { 1499 IWN5000_EEPROM_BAND1, 1500 IWN5000_EEPROM_BAND2, 1501 IWN5000_EEPROM_BAND3, 1502 IWN5000_EEPROM_BAND4, 1503 IWN5000_EEPROM_BAND5, 1504 IWN6000_EEPROM_BAND6, 1505 IWN5000_EEPROM_BAND7 1506}; 1507 1508#define IWN_CHAN_BANDS_COUNT 7 1509#define IWN_MAX_CHAN_PER_BAND 14 1510static const struct iwn_chan_band { 1511 uint8_t nchan; 1512 uint8_t chan[IWN_MAX_CHAN_PER_BAND]; 1513} iwn_bands[] = { 1514 /* 20MHz channels, 2GHz band. */ 1515 { 14, { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } }, 1516 /* 20MHz channels, 5GHz band. */ 1517 { 13, { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } }, 1518 { 12, { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } }, 1519 { 11, { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } }, 1520 { 6, { 145, 149, 153, 157, 161, 165 } }, 1521 /* 40MHz channels (primary channels), 2GHz band. */ 1522 { 7, { 1, 2, 3, 4, 5, 6, 7 } }, 1523 /* 40MHz channels (primary channels), 5GHz band. */ 1524 { 11, { 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157 } } 1525}; 1526 1527#define IWN1000_OTP_NBLOCKS 3 1528#define IWN6000_OTP_NBLOCKS 4 1529#define IWN6050_OTP_NBLOCKS 7 1530 1531/* HW rate indices. */ 1532#define IWN_RIDX_CCK1 0 1533#define IWN_RIDX_OFDM6 4 1534 1535#define IWN4965_MAX_PWR_INDEX 107 1536 1537/* 1538 * RF Tx gain values from highest to lowest power (values obtained from 1539 * the reference driver.) 1540 */ 1541static const uint8_t iwn4965_rf_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1542 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, 1543 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 0x39, 0x38, 1544 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 0x35, 0x35, 1545 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x31, 0x31, 1546 0x31, 0x30, 0x30, 0x30, 0x06, 0x06, 0x06, 0x05, 0x05, 0x05, 0x04, 1547 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01, 1548 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1549 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1550 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1551 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1552}; 1553 1554static const uint8_t iwn4965_rf_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1555 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 1556 0x3c, 0x3c, 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 1557 0x39, 0x38, 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 1558 0x35, 0x35, 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 1559 0x31, 0x31, 0x31, 0x30, 0x30, 0x30, 0x25, 0x25, 0x25, 0x24, 0x24, 1560 0x24, 0x23, 0x23, 0x23, 0x22, 0x18, 0x18, 0x17, 0x17, 0x17, 0x16, 1561 0x16, 0x16, 0x15, 0x15, 0x15, 0x14, 0x14, 0x14, 0x13, 0x13, 0x13, 1562 0x12, 0x08, 0x08, 0x07, 0x07, 0x07, 0x06, 0x06, 0x06, 0x05, 0x05, 1563 0x05, 0x04, 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 1564 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1565}; 1566 1567/* 1568 * DSP pre-DAC gain values from highest to lowest power (values obtained 1569 * from the reference driver.) 1570 */ 1571static const uint8_t iwn4965_dsp_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1572 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1573 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1574 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1575 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1576 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1577 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1578 0x6e, 0x68, 0x62, 0x61, 0x60, 0x5f, 0x5e, 0x5d, 0x5c, 0x5b, 0x5a, 1579 0x59, 0x58, 0x57, 0x56, 0x55, 0x54, 0x53, 0x52, 0x51, 0x50, 0x4f, 1580 0x4e, 0x4d, 0x4c, 0x4b, 0x4a, 0x49, 0x48, 0x47, 0x46, 0x45, 0x44, 1581 0x43, 0x42, 0x41, 0x40, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b 1582}; 1583 1584static const uint8_t iwn4965_dsp_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1585 0x7b, 0x75, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1586 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1587 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1588 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1589 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1590 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1591 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1592 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1593 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1594 0x68, 0x62, 0x6e, 0x68, 0x62, 0x5d, 0x58, 0x53, 0x4e 1595}; 1596 1597/* 1598 * Power saving settings (values obtained from the reference driver.) 1599 */ 1600#define IWN_NDTIMRANGES 3 1601#define IWN_NPOWERLEVELS 6 1602static const struct iwn_pmgt { 1603 uint32_t rxtimeout; 1604 uint32_t txtimeout; 1605 uint32_t intval[5]; 1606 int skip_dtim; 1607} iwn_pmgt[IWN_NDTIMRANGES][IWN_NPOWERLEVELS] = { 1608 /* DTIM <= 2 */ 1609 { 1610 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1611 { 200, 500, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 1 */ 1612 { 200, 300, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 2 */ 1613 { 50, 100, { 2, 2, 2, 2, -1 }, 0 }, /* PS level 3 */ 1614 { 50, 25, { 2, 2, 4, 4, -1 }, 1 }, /* PS level 4 */ 1615 { 25, 25, { 2, 2, 4, 6, -1 }, 2 } /* PS level 5 */ 1616 }, 1617 /* 3 <= DTIM <= 10 */ 1618 { 1619 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1620 { 200, 500, { 1, 2, 3, 4, 4 }, 0 }, /* PS level 1 */ 1621 { 200, 300, { 1, 2, 3, 4, 7 }, 0 }, /* PS level 2 */ 1622 { 50, 100, { 2, 4, 6, 7, 9 }, 0 }, /* PS level 3 */ 1623 { 50, 25, { 2, 4, 6, 9, 10 }, 1 }, /* PS level 4 */ 1624 { 25, 25, { 2, 4, 7, 10, 10 }, 2 } /* PS level 5 */ 1625 }, 1626 /* DTIM >= 11 */ 1627 { 1628 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1629 { 200, 500, { 1, 2, 3, 4, -1 }, 0 }, /* PS level 1 */ 1630 { 200, 300, { 2, 4, 6, 7, -1 }, 0 }, /* PS level 2 */ 1631 { 50, 100, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 3 */ 1632 { 50, 25, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 4 */ 1633 { 25, 25, { 4, 7, 10, 10, -1 }, 0 } /* PS level 5 */ 1634 } 1635}; 1636 1637struct iwn_sensitivity_limits { 1638 uint32_t min_ofdm_x1; 1639 uint32_t max_ofdm_x1; 1640 uint32_t min_ofdm_mrc_x1; 1641 uint32_t max_ofdm_mrc_x1; 1642 uint32_t min_ofdm_x4; 1643 uint32_t max_ofdm_x4; 1644 uint32_t min_ofdm_mrc_x4; 1645 uint32_t max_ofdm_mrc_x4; 1646 uint32_t min_cck_x4; 1647 uint32_t max_cck_x4; 1648 uint32_t min_cck_mrc_x4; 1649 uint32_t max_cck_mrc_x4; 1650 uint32_t min_energy_cck; 1651 uint32_t energy_cck; 1652 uint32_t energy_ofdm; 1653}; 1654 1655/* 1656 * RX sensitivity limits (values obtained from the reference driver.) 1657 */ 1658static const struct iwn_sensitivity_limits iwn4965_sensitivity_limits = { 1659 105, 140, 1660 220, 270, 1661 85, 120, 1662 170, 210, 1663 125, 200, 1664 200, 400, 1665 97, 1666 100, 1667 100 1668}; 1669 1670static const struct iwn_sensitivity_limits iwn5000_sensitivity_limits = { 1671 120, 120, /* min = max for performance bug in DSP. */ 1672 240, 240, /* min = max for performance bug in DSP. */ 1673 90, 120, 1674 170, 210, 1675 125, 200, 1676 170, 400, 1677 95, 1678 95, 1679 95 1680}; 1681 1682static const struct iwn_sensitivity_limits iwn5150_sensitivity_limits = { 1683 105, 105, /* min = max for performance bug in DSP. */ 1684 220, 220, /* min = max for performance bug in DSP. */ 1685 90, 120, 1686 170, 210, 1687 125, 200, 1688 170, 400, 1689 95, 1690 95, 1691 95 1692}; 1693 1694static const struct iwn_sensitivity_limits iwn1000_sensitivity_limits = { 1695 120, 155, 1696 240, 290, 1697 90, 120, 1698 170, 210, 1699 125, 200, 1700 170, 400, 1701 95, 1702 95, 1703 95 1704}; 1705 1706static const struct iwn_sensitivity_limits iwn6000_sensitivity_limits = { 1707 105, 110, 1708 192, 232, 1709 80, 145, 1710 128, 232, 1711 125, 175, 1712 160, 310, 1713 97, 1714 97, 1715 100 1716}; 1717 1718/* Map TID to TX scheduler's FIFO. */ 1719static const uint8_t iwn_tid2fifo[] = { 1720 1, 0, 0, 1, 2, 2, 3, 3, 7, 7, 7, 7, 7, 7, 7, 7, 3 1721}; 1722 1723/* WiFi/WiMAX coexist event priority table for 6050. */ 1724static const struct iwn5000_wimax_event iwn6050_wimax_events[] = { 1725 { 0x04, 0x03, 0x00, 0x00 }, 1726 { 0x04, 0x03, 0x00, 0x03 }, 1727 { 0x04, 0x03, 0x00, 0x03 }, 1728 { 0x04, 0x03, 0x00, 0x03 }, 1729 { 0x04, 0x03, 0x00, 0x00 }, 1730 { 0x04, 0x03, 0x00, 0x07 }, 1731 { 0x04, 0x03, 0x00, 0x00 }, 1732 { 0x04, 0x03, 0x00, 0x03 }, 1733 { 0x04, 0x03, 0x00, 0x03 }, 1734 { 0x04, 0x03, 0x00, 0x00 }, 1735 { 0x06, 0x03, 0x00, 0x07 }, 1736 { 0x04, 0x03, 0x00, 0x00 }, 1737 { 0x06, 0x06, 0x00, 0x03 }, 1738 { 0x04, 0x03, 0x00, 0x07 }, 1739 { 0x04, 0x03, 0x00, 0x00 }, 1740 { 0x04, 0x03, 0x00, 0x00 } 1741}; 1742 1743/* Firmware errors. */ 1744static const char * const iwn_fw_errmsg[] = { 1745 "OK", 1746 "FAIL", 1747 "BAD_PARAM", 1748 "BAD_CHECKSUM", 1749 "NMI_INTERRUPT_WDG", 1750 "SYSASSERT", 1751 "FATAL_ERROR", 1752 "BAD_COMMAND", 1753 "HW_ERROR_TUNE_LOCK", 1754 "HW_ERROR_TEMPERATURE", 1755 "ILLEGAL_CHAN_FREQ", 1756 "VCC_NOT_STABLE", 1757 "FH_ERROR", 1758 "NMI_INTERRUPT_HOST", 1759 "NMI_INTERRUPT_ACTION_PT", 1760 "NMI_INTERRUPT_UNKNOWN", 1761 "UCODE_VERSION_MISMATCH", 1762 "HW_ERROR_ABS_LOCK", 1763 "HW_ERROR_CAL_LOCK_FAIL", 1764 "NMI_INTERRUPT_INST_ACTION_PT", 1765 "NMI_INTERRUPT_DATA_ACTION_PT", 1766 "NMI_TRM_HW_ER", 1767 "NMI_INTERRUPT_TRM", 1768 "NMI_INTERRUPT_BREAKPOINT" 1769 "DEBUG_0", 1770 "DEBUG_1", 1771 "DEBUG_2", 1772 "DEBUG_3", 1773 "ADVANCED_SYSASSERT" 1774}; 1775 1776/* Find least significant bit that is set. */ 1777#define IWN_LSB(x) ((((x) - 1) & (x)) ^ (x)) 1778 1779#define IWN_READ(sc, reg) \ 1780 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 1781 1782#define IWN_WRITE(sc, reg, val) \ 1783 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 1784 1785#define IWN_WRITE_1(sc, reg, val) \ 1786 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 1787 1788#define IWN_SETBITS(sc, reg, mask) \ 1789 IWN_WRITE(sc, reg, IWN_READ(sc, reg) | (mask)) 1790 1791#define IWN_CLRBITS(sc, reg, mask) \ 1792 IWN_WRITE(sc, reg, IWN_READ(sc, reg) & ~(mask)) 1793 1794#define IWN_BARRIER_WRITE(sc) \ 1795 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 1796 BUS_SPACE_BARRIER_WRITE) 1797 1798#define IWN_BARRIER_READ_WRITE(sc) \ 1799 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 1800 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 1801