1/* $FreeBSD$ */ 2/* $OpenBSD: if_iwnreg.h,v 1.40 2010/05/05 19:41:57 damien Exp $ */ 3 4/*- 5 * Copyright (c) 2007, 2008 6 * Damien Bergamini <damien.bergamini@free.fr> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21#define IWN_CT_KILL_THRESHOLD 114 /* in Celsius */ 22#define IWN_CT_KILL_EXIT_THRESHOLD 95 /* in Celsius */ 23 24#define IWN_TX_RING_COUNT 256 25#define IWN_TX_RING_LOMARK 192 26#define IWN_TX_RING_HIMARK 224 27#define IWN_RX_RING_COUNT_LOG 6 28#define IWN_RX_RING_COUNT (1 << IWN_RX_RING_COUNT_LOG) 29 30#define IWN4965_NTXQUEUES 16 31#define IWN5000_NTXQUEUES 20 32 33#define IWN4965_FIRSTAGGQUEUE 7 34#define IWN5000_FIRSTAGGQUEUE 10 35 36#define IWN4965_NDMACHNLS 7 37#define IWN5000_NDMACHNLS 8 38 39#define IWN_SRVC_DMACHNL 9 40 41#define IWN_ICT_SIZE 4096 42#define IWN_ICT_COUNT (IWN_ICT_SIZE / sizeof (uint32_t)) 43 44/* For cards with PAN command, default is IWN_CMD_QUEUE_NUM */ 45#define IWN_CMD_QUEUE_NUM 4 46#define IWN_PAN_CMD_QUEUE 9 47 48/* Maximum number of DMA segments for TX. */ 49#define IWN_MAX_SCATTER 20 50 51/* RX buffers must be large enough to hold a full 4K A-MPDU. */ 52#define IWN_RBUF_SIZE (4 * 1024) 53 54#if defined(__LP64__) 55/* HW supports 36-bit DMA addresses. */ 56#define IWN_LOADDR(paddr) ((uint32_t)(paddr)) 57#define IWN_HIADDR(paddr) (((paddr) >> 32) & 0xf) 58#else 59#define IWN_LOADDR(paddr) (paddr) 60#define IWN_HIADDR(paddr) (0) 61#endif 62 63/* 64 * Control and status registers. 65 */ 66#define IWN_HW_IF_CONFIG 0x000 67#define IWN_INT_COALESCING 0x004 68#define IWN_INT_PERIODIC 0x005 /* use IWN_WRITE_1 */ 69#define IWN_INT 0x008 70#define IWN_INT_MASK 0x00c 71#define IWN_FH_INT 0x010 72#define IWN_GPIO_IN 0x018 /* read external chip pins */ 73#define IWN_RESET 0x020 74#define IWN_GP_CNTRL 0x024 75#define IWN_HW_REV 0x028 76#define IWN_EEPROM 0x02c 77#define IWN_EEPROM_GP 0x030 78#define IWN_OTP_GP 0x034 79#define IWN_GIO 0x03c 80#define IWN_GP_UCODE 0x048 81#define IWN_GP_DRIVER 0x050 82#define IWN_UCODE_GP1 0x054 83#define IWN_UCODE_GP1_SET 0x058 84#define IWN_UCODE_GP1_CLR 0x05c 85#define IWN_UCODE_GP2 0x060 86#define IWN_LED 0x094 87#define IWN_DRAM_INT_TBL 0x0a0 88#define IWN_SHADOW_REG_CTRL 0x0a8 89#define IWN_GIO_CHICKEN 0x100 90#define IWN_ANA_PLL 0x20c 91#define IWN_HW_REV_WA 0x22c 92#define IWN_DBG_HPET_MEM 0x240 93#define IWN_DBG_LINK_PWR_MGMT 0x250 94/* Need nic_lock for use above */ 95#define IWN_MEM_RADDR 0x40c 96#define IWN_MEM_WADDR 0x410 97#define IWN_MEM_WDATA 0x418 98#define IWN_MEM_RDATA 0x41c 99#define IWN_TARG_MBX_C 0x430 100#define IWN_PRPH_WADDR 0x444 101#define IWN_PRPH_RADDR 0x448 102#define IWN_PRPH_WDATA 0x44c 103#define IWN_PRPH_RDATA 0x450 104#define IWN_HBUS_TARG_WRPTR 0x460 105 106/* 107 * Flow-Handler registers. 108 */ 109#define IWN_FH_TFBD_CTRL0(qid) (0x1900 + (qid) * 8) 110#define IWN_FH_TFBD_CTRL1(qid) (0x1904 + (qid) * 8) 111#define IWN_FH_KW_ADDR 0x197c 112#define IWN_FH_SRAM_ADDR(qid) (0x19a4 + (qid) * 4) 113#define IWN_FH_CBBC_QUEUE(qid) (0x19d0 + (qid) * 4) 114#define IWN_FH_STATUS_WPTR 0x1bc0 115#define IWN_FH_RX_BASE 0x1bc4 116#define IWN_FH_RX_WPTR 0x1bc8 117#define IWN_FH_RX_CONFIG 0x1c00 118#define IWN_FH_RX_STATUS 0x1c44 119#define IWN_FH_TX_CONFIG(qid) (0x1d00 + (qid) * 32) 120#define IWN_FH_TXBUF_STATUS(qid) (0x1d08 + (qid) * 32) 121#define IWN_FH_TX_CHICKEN 0x1e98 122#define IWN_FH_TX_STATUS 0x1eb0 123 124/* 125 * TX scheduler registers. 126 */ 127#define IWN_SCHED_BASE 0xa02c00 128#define IWN_SCHED_SRAM_ADDR (IWN_SCHED_BASE + 0x000) 129#define IWN5000_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x008) 130#define IWN4965_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x010) 131#define IWN5000_SCHED_TXFACT (IWN_SCHED_BASE + 0x010) 132#define IWN4965_SCHED_TXFACT (IWN_SCHED_BASE + 0x01c) 133#define IWN4965_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x064 + (qid) * 4) 134#define IWN5000_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x068 + (qid) * 4) 135#define IWN4965_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0d0) 136#define IWN4965_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x0e4) 137#define IWN5000_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0e8) 138#define IWN4965_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x104 + (qid) * 4) 139#define IWN5000_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x108) 140#define IWN5000_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x10c + (qid) * 4) 141#define IWN5000_SCHED_AGGR_SEL (IWN_SCHED_BASE + 0x248) 142 143/* 144 * Offsets in TX scheduler's SRAM. 145 */ 146#define IWN4965_SCHED_CTX_OFF 0x380 147#define IWN4965_SCHED_CTX_LEN 416 148#define IWN4965_SCHED_QUEUE_OFFSET(qid) (0x380 + (qid) * 8) 149#define IWN4965_SCHED_TRANS_TBL(qid) (0x500 + (qid) * 2) 150#define IWN5000_SCHED_CTX_OFF 0x600 151#define IWN5000_SCHED_CTX_LEN 520 152#define IWN5000_SCHED_QUEUE_OFFSET(qid) (0x600 + (qid) * 8) 153#define IWN5000_SCHED_TRANS_TBL(qid) (0x7e0 + (qid) * 2) 154 155/* 156 * NIC internal memory offsets. 157 */ 158#define IWN_APMG_CLK_CTRL 0x3000 159#define IWN_APMG_CLK_EN 0x3004 160#define IWN_APMG_CLK_DIS 0x3008 161#define IWN_APMG_PS 0x300c 162#define IWN_APMG_DIGITAL_SVR 0x3058 163#define IWN_APMG_ANALOG_SVR 0x306c 164#define IWN_APMG_PCI_STT 0x3010 165#define IWN_BSM_WR_CTRL 0x3400 166#define IWN_BSM_WR_MEM_SRC 0x3404 167#define IWN_BSM_WR_MEM_DST 0x3408 168#define IWN_BSM_WR_DWCOUNT 0x340c 169#define IWN_BSM_DRAM_TEXT_ADDR 0x3490 170#define IWN_BSM_DRAM_TEXT_SIZE 0x3494 171#define IWN_BSM_DRAM_DATA_ADDR 0x3498 172#define IWN_BSM_DRAM_DATA_SIZE 0x349c 173#define IWN_BSM_SRAM_BASE 0x3800 174 175/* Possible flags for register IWN_HW_IF_CONFIG. */ 176#define IWN_HW_IF_CONFIG_4965_R (1 << 4) 177#define IWN_HW_IF_CONFIG_MAC_SI (1 << 8) 178#define IWN_HW_IF_CONFIG_RADIO_SI (1 << 9) 179#define IWN_HW_IF_CONFIG_EEPROM_LOCKED (1 << 21) 180#define IWN_HW_IF_CONFIG_NIC_READY (1 << 22) 181#define IWN_HW_IF_CONFIG_HAP_WAKE_L1A (1 << 23) 182#define IWN_HW_IF_CONFIG_PREPARE_DONE (1 << 25) 183#define IWN_HW_IF_CONFIG_PREPARE (1 << 27) 184 185/* Possible values for register IWN_INT_PERIODIC. */ 186#define IWN_INT_PERIODIC_DIS 0x00 187#define IWN_INT_PERIODIC_ENA 0xff 188 189/* Possible flags for registers IWN_PRPH_RADDR/IWN_PRPH_WADDR. */ 190#define IWN_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24) 191 192/* Possible values for IWN_BSM_WR_MEM_DST. */ 193#define IWN_FW_TEXT_BASE 0x00000000 194#define IWN_FW_DATA_BASE 0x00800000 195 196/* Possible flags for register IWN_RESET. */ 197#define IWN_RESET_NEVO (1 << 0) 198#define IWN_RESET_SW (1 << 7) 199#define IWN_RESET_MASTER_DISABLED (1 << 8) 200#define IWN_RESET_STOP_MASTER (1 << 9) 201#define IWN_RESET_LINK_PWR_MGMT_DIS (1U << 31) 202 203/* Possible flags for register IWN_GP_CNTRL. */ 204#define IWN_GP_CNTRL_MAC_ACCESS_ENA (1 << 0) 205#define IWN_GP_CNTRL_MAC_CLOCK_READY (1 << 0) 206#define IWN_GP_CNTRL_INIT_DONE (1 << 2) 207#define IWN_GP_CNTRL_MAC_ACCESS_REQ (1 << 3) 208#define IWN_GP_CNTRL_SLEEP (1 << 4) 209#define IWN_GP_CNTRL_RFKILL (1 << 27) 210 211/* Possible flags for register IWN_GIO_CHICKEN. */ 212#define IWN_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23) 213#define IWN_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29) 214 215/* Possible flags for register IWN_GIO. */ 216#define IWN_GIO_L0S_ENA (1 << 1) 217 218/* Possible flags for register IWN_GP_DRIVER. */ 219#define IWN_GP_DRIVER_RADIO_3X3_HYB (0 << 0) 220#define IWN_GP_DRIVER_RADIO_2X2_HYB (1 << 0) 221#define IWN_GP_DRIVER_RADIO_2X2_IPA (2 << 0) 222#define IWN_GP_DRIVER_CALIB_VER6 (1 << 2) 223#define IWN_GP_DRIVER_6050_1X2 (1 << 3) 224#define IWN_GP_DRIVER_REG_BIT_RADIO_IQ_INVERT (1 << 7) 225 226/* Possible flags for register IWN_UCODE_GP1_CLR. */ 227#define IWN_UCODE_GP1_RFKILL (1 << 1) 228#define IWN_UCODE_GP1_CMD_BLOCKED (1 << 2) 229#define IWN_UCODE_GP1_CTEMP_STOP_RF (1 << 3) 230#define IWN_UCODE_GP1_CFG_COMPLETE (1 << 5) 231 232/* Possible flags/values for register IWN_LED. */ 233#define IWN_LED_BSM_CTRL (1 << 5) 234#define IWN_LED_OFF 0x00000038 235#define IWN_LED_ON 0x00000078 236 237#define IWN_MAX_BLINK_TBL 10 238#define IWN_LED_STATIC_ON 0 239#define IWN_LED_STATIC_OFF 1 240#define IWN_LED_SLOW_BLINK 2 241#define IWN_LED_INT_BLINK 3 242#define IWN_LED_UNIT 0x1388 /* 5 ms */ 243 244static const struct { 245 uint16_t tpt; /* Mb/s */ 246 uint8_t on_time; 247 uint8_t off_time; 248} blink_tbl[] = 249{ 250 {300, 5, 5}, 251 {200, 8, 8}, 252 {100, 11, 11}, 253 {70, 13, 13}, 254 {50, 15, 15}, 255 {20, 17, 17}, 256 {10, 19, 19}, 257 {5, 22, 22}, 258 {1, 26, 26}, 259 {0, 33, 33}, 260 /* SOLID_ON */ 261}; 262 263/* Possible flags for register IWN_DRAM_INT_TBL. */ 264#define IWN_DRAM_INT_TBL_WRAP_CHECK (1 << 27) 265#define IWN_DRAM_INT_TBL_ENABLE (1U << 31) 266 267/* Possible values for register IWN_ANA_PLL. */ 268#define IWN_ANA_PLL_INIT 0x00880300 269 270/* Possible flags for register IWN_FH_RX_STATUS. */ 271#define IWN_FH_RX_STATUS_IDLE (1 << 24) 272 273/* Possible flags for register IWN_BSM_WR_CTRL. */ 274#define IWN_BSM_WR_CTRL_START_EN (1 << 30) 275#define IWN_BSM_WR_CTRL_START (1U << 31) 276 277/* Possible flags for register IWN_INT. */ 278#define IWN_INT_ALIVE (1 << 0) 279#define IWN_INT_WAKEUP (1 << 1) 280#define IWN_INT_SW_RX (1 << 3) 281#define IWN_INT_CT_REACHED (1 << 6) 282#define IWN_INT_RF_TOGGLED (1 << 7) 283#define IWN_INT_SW_ERR (1 << 25) 284#define IWN_INT_SCHED (1 << 26) 285#define IWN_INT_FH_TX (1 << 27) 286#define IWN_INT_RX_PERIODIC (1 << 28) 287#define IWN_INT_HW_ERR (1 << 29) 288#define IWN_INT_FH_RX (1U << 31) 289 290/* Shortcut. */ 291#define IWN_INT_MASK_DEF \ 292 (IWN_INT_SW_ERR | IWN_INT_HW_ERR | IWN_INT_FH_TX | \ 293 IWN_INT_FH_RX | IWN_INT_ALIVE | IWN_INT_WAKEUP | \ 294 IWN_INT_SW_RX | IWN_INT_CT_REACHED | IWN_INT_RF_TOGGLED) 295 296/* Possible flags for register IWN_FH_INT. */ 297#define IWN_FH_INT_TX_CHNL(x) (1 << (x)) 298#define IWN_FH_INT_RX_CHNL(x) (1 << ((x) + 16)) 299#define IWN_FH_INT_HI_PRIOR (1 << 30) 300/* Shortcuts for the above. */ 301#define IWN_FH_INT_TX \ 302 (IWN_FH_INT_TX_CHNL(0) | IWN_FH_INT_TX_CHNL(1)) 303#define IWN_FH_INT_RX \ 304 (IWN_FH_INT_RX_CHNL(0) | IWN_FH_INT_RX_CHNL(1) | IWN_FH_INT_HI_PRIOR) 305 306/* Possible flags/values for register IWN_FH_TX_CONFIG. */ 307#define IWN_FH_TX_CONFIG_DMA_PAUSE 0 308#define IWN_FH_TX_CONFIG_DMA_ENA (1U << 31) 309#define IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD (1 << 20) 310 311/* Possible flags/values for register IWN_FH_TXBUF_STATUS. */ 312#define IWN_FH_TXBUF_STATUS_TBNUM(x) ((x) << 20) 313#define IWN_FH_TXBUF_STATUS_TBIDX(x) ((x) << 12) 314#define IWN_FH_TXBUF_STATUS_TFBD_VALID 3 315 316/* Possible flags for register IWN_FH_TX_CHICKEN. */ 317#define IWN_FH_TX_CHICKEN_SCHED_RETRY (1 << 1) 318 319/* Possible flags for register IWN_FH_TX_STATUS. */ 320#define IWN_FH_TX_STATUS_IDLE(chnl) (1 << ((chnl) + 16)) 321 322/* Possible flags for register IWN_FH_RX_CONFIG. */ 323#define IWN_FH_RX_CONFIG_ENA (1U << 31) 324#define IWN_FH_RX_CONFIG_NRBD(x) ((x) << 20) 325#define IWN_FH_RX_CONFIG_RB_SIZE_8K (1 << 16) 326#define IWN_FH_RX_CONFIG_SINGLE_FRAME (1 << 15) 327#define IWN_FH_RX_CONFIG_IRQ_DST_HOST (1 << 12) 328#define IWN_FH_RX_CONFIG_RB_TIMEOUT(x) ((x) << 4) 329#define IWN_FH_RX_CONFIG_IGN_RXF_EMPTY (1 << 2) 330 331/* Possible flags for register IWN_FH_TX_CONFIG. */ 332#define IWN_FH_TX_CONFIG_DMA_ENA (1U << 31) 333#define IWN_FH_TX_CONFIG_DMA_CREDIT_ENA (1 << 3) 334 335/* Possible flags for register IWN_EEPROM. */ 336#define IWN_EEPROM_READ_VALID (1 << 0) 337#define IWN_EEPROM_CMD (1 << 1) 338 339/* Possible flags for register IWN_EEPROM_GP. */ 340#define IWN_EEPROM_GP_IF_OWNER 0x00000180 341 342/* Possible flags for register IWN_OTP_GP. */ 343#define IWN_OTP_GP_DEV_SEL_OTP (1 << 16) 344#define IWN_OTP_GP_RELATIVE_ACCESS (1 << 17) 345#define IWN_OTP_GP_ECC_CORR_STTS (1 << 20) 346#define IWN_OTP_GP_ECC_UNCORR_STTS (1 << 21) 347 348/* Possible flags for register IWN_SCHED_QUEUE_STATUS. */ 349#define IWN4965_TXQ_STATUS_ACTIVE 0x0007fc01 350#define IWN4965_TXQ_STATUS_INACTIVE 0x0007fc00 351#define IWN4965_TXQ_STATUS_AGGR_ENA (1 << 5 | 1 << 8) 352#define IWN4965_TXQ_STATUS_CHGACT (1 << 10) 353#define IWN5000_TXQ_STATUS_ACTIVE 0x00ff0018 354#define IWN5000_TXQ_STATUS_INACTIVE 0x00ff0010 355#define IWN5000_TXQ_STATUS_CHGACT (1 << 19) 356 357/* Possible flags for registers IWN_APMG_CLK_*. */ 358#define IWN_APMG_CLK_CTRL_DMA_CLK_RQT (1 << 9) 359#define IWN_APMG_CLK_CTRL_BSM_CLK_RQT (1 << 11) 360 361/* Possible flags for register IWN_APMG_PS. */ 362#define IWN_APMG_PS_EARLY_PWROFF_DIS (1 << 22) 363#define IWN_APMG_PS_PWR_SRC(x) ((x) << 24) 364#define IWN_APMG_PS_PWR_SRC_VMAIN 0 365#define IWN_APMG_PS_PWR_SRC_VAUX 2 366#define IWN_APMG_PS_PWR_SRC_MASK IWN_APMG_PS_PWR_SRC(3) 367#define IWN_APMG_PS_RESET_REQ (1 << 26) 368 369/* Possible flags for register IWN_APMG_DIGITAL_SVR. */ 370#define IWN_APMG_DIGITAL_SVR_VOLTAGE(x) (((x) & 0xf) << 5) 371#define IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK \ 372 IWN_APMG_DIGITAL_SVR_VOLTAGE(0xf) 373#define IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32 \ 374 IWN_APMG_DIGITAL_SVR_VOLTAGE(3) 375 376/* Possible flags for IWN_APMG_PCI_STT. */ 377#define IWN_APMG_PCI_STT_L1A_DIS (1 << 11) 378 379/* Possible flags for register IWN_BSM_DRAM_TEXT_SIZE. */ 380#define IWN_FW_UPDATED (1U << 31) 381 382#define IWN_SCHED_WINSZ 64 383#define IWN_SCHED_LIMIT 64 384#define IWN4965_SCHED_COUNT 512 385#define IWN5000_SCHED_COUNT (IWN_TX_RING_COUNT + IWN_SCHED_WINSZ) 386#define IWN4965_SCHEDSZ (IWN4965_NTXQUEUES * IWN4965_SCHED_COUNT * 2) 387#define IWN5000_SCHEDSZ (IWN5000_NTXQUEUES * IWN5000_SCHED_COUNT * 2) 388 389struct iwn_tx_desc { 390 uint8_t reserved1[3]; 391 uint8_t nsegs; 392 struct { 393 uint32_t addr; 394 uint16_t len; 395 } __packed segs[IWN_MAX_SCATTER]; 396 /* Pad to 128 bytes. */ 397 uint32_t reserved2; 398} __packed; 399 400struct iwn_rx_status { 401 uint16_t closed_count; 402 uint16_t closed_rx_count; 403 uint16_t finished_count; 404 uint16_t finished_rx_count; 405 uint32_t reserved[2]; 406} __packed; 407 408struct iwn_rx_desc { 409 /* 410 * The first 4 bytes of the RX frame header contain both the RX frame 411 * size and some flags. 412 * Bit fields: 413 * 31: flag flush RB request 414 * 30: flag ignore TC (terminal counter) request 415 * 29: flag fast IRQ request 416 * 28-14: Reserved 417 * 13-00: RX frame size 418 */ 419 uint32_t len; 420 uint8_t type; 421#define IWN_UC_READY 1 422#define IWN_ADD_NODE_DONE 24 423#define IWN_TX_DONE 28 424#define IWN_REPLY_LED_CMD 72 425#define IWN5000_CALIBRATION_RESULT 102 426#define IWN5000_CALIBRATION_DONE 103 427#define IWN_START_SCAN 130 428#define IWN_NOTIF_SCAN_RESULT 131 429#define IWN_STOP_SCAN 132 430#define IWN_RX_STATISTICS 156 431#define IWN_BEACON_STATISTICS 157 432#define IWN_STATE_CHANGED 161 433#define IWN_BEACON_MISSED 162 434#define IWN_RX_PHY 192 435#define IWN_MPDU_RX_DONE 193 436#define IWN_RX_DONE 195 437#define IWN_RX_COMPRESSED_BA 197 438 439 uint8_t flags; /* 0:5 reserved, 6 abort, 7 internal */ 440 uint8_t idx; /* position within TX queue */ 441 uint8_t qid; 442 /* 0:4 TX queue id - 5:6 reserved - 7 unsolicited RX 443 * or uCode-originated notification 444 */ 445} __packed; 446 447#define IWN_RX_DESC_QID_MSK 0x1F 448#define IWN_UNSOLICITED_RX_NOTIF 0x80 449 450/* CARD_STATE_NOTIFICATION */ 451#define IWN_STATE_CHANGE_HW_CARD_DISABLED 0x01 452#define IWN_STATE_CHANGE_SW_CARD_DISABLED 0x02 453#define IWN_STATE_CHANGE_CT_CARD_DISABLED 0x04 454#define IWN_STATE_CHANGE_RXON_CARD_DISABLED 0x10 455 456/* Possible RX status flags. */ 457#define IWN_RX_NO_CRC_ERR (1 << 0) 458#define IWN_RX_NO_OVFL_ERR (1 << 1) 459/* Shortcut for the above. */ 460#define IWN_RX_NOERROR (IWN_RX_NO_CRC_ERR | IWN_RX_NO_OVFL_ERR) 461#define IWN_RX_MPDU_MIC_OK (1 << 6) 462#define IWN_RX_CIPHER_MASK (7 << 8) 463#define IWN_RX_CIPHER_CCMP (2 << 8) 464#define IWN_RX_MPDU_DEC (1 << 11) 465#define IWN_RX_DECRYPT_MASK (3 << 11) 466#define IWN_RX_DECRYPT_OK (3 << 11) 467 468struct iwn_tx_cmd { 469 uint8_t code; 470#define IWN_CMD_RXON 16 471#define IWN_CMD_RXON_ASSOC 17 472#define IWN_CMD_EDCA_PARAMS 19 473#define IWN_CMD_TIMING 20 474#define IWN_CMD_ADD_NODE 24 475#define IWN_CMD_TX_DATA 28 476#define IWN_CMD_LINK_QUALITY 78 477#define IWN_CMD_SET_LED 72 478#define IWN5000_CMD_WIMAX_COEX 90 479#define IWN_TEMP_NOTIFICATION 98 480#define IWN5000_CMD_CALIB_CONFIG 101 481#define IWN5000_CMD_CALIB_RESULT 102 482#define IWN5000_CMD_CALIB_COMPLETE 103 483#define IWN_CMD_SET_POWER_MODE 119 484#define IWN_CMD_SCAN 128 485#define IWN_CMD_SCAN_RESULTS 131 486#define IWN_CMD_TXPOWER_DBM 149 487#define IWN_CMD_TXPOWER 151 488#define IWN5000_CMD_TX_ANT_CONFIG 152 489#define IWN_CMD_BT_COEX 155 490#define IWN_CMD_GET_STATISTICS 156 491#define IWN_CMD_SET_CRITICAL_TEMP 164 492#define IWN_CMD_SET_SENSITIVITY 168 493#define IWN_CMD_PHY_CALIB 176 494#define IWN_CMD_BT_COEX_PRIOTABLE 204 495#define IWN_CMD_BT_COEX_PROT 205 496#define IWN_CMD_BT_COEX_NOTIF 206 497/* PAN commands */ 498#define IWN_CMD_WIPAN_PARAMS 0xb2 499#define IWN_CMD_WIPAN_RXON 0xb3 500#define IWN_CMD_WIPAN_RXON_TIMING 0xb4 501#define IWN_CMD_WIPAN_RXON_ASSOC 0xb6 502#define IWN_CMD_WIPAN_QOS_PARAM 0xb7 503#define IWN_CMD_WIPAN_WEPKEY 0xb8 504#define IWN_CMD_WIPAN_P2P_CHANNEL_SWITCH 0xb9 505#define IWN_CMD_WIPAN_NOA_NOTIFICATION 0xbc 506#define IWN_CMD_WIPAN_DEACTIVATION_COMPLETE 0xbd 507 508 uint8_t flags; 509 uint8_t idx; 510 uint8_t qid; 511 uint8_t data[136]; 512} __packed; 513 514/* 515 * Structure for IWN_CMD_GET_STATISTICS = (0x9c) 156 516 * all devices identical. 517 * 518 * This command triggers an immediate response containing uCode statistics. 519 * The response is in the same format as IWN_BEACON_STATISTICS (0x9d) 157. 520 * 521 * If the CLEAR_STATS configuration flag is set, uCode will clear its 522 * internal copy of the statistics (counters) after issuing the response. 523 * This flag does not affect IWN_BEACON_STATISTICS after beacons (see below). 524 * 525 * If the DISABLE_NOTIF configuration flag is set, uCode will not issue 526 * IWN_BEACON_STATISTICS after received beacons. This flag 527 * does not affect the response to the IWN_CMD_GET_STATISTICS 0x9c itself. 528 */ 529struct iwn_statistics_cmd { 530 uint32_t configuration_flags; 531#define IWN_STATS_CONF_CLEAR_STATS htole32(0x1) 532#define IWN_STATS_CONF_DISABLE_NOTIF htole32(0x2) 533} __packed; 534 535/* Antenna flags, used in various commands. */ 536#define IWN_ANT_A (1 << 0) 537#define IWN_ANT_B (1 << 1) 538#define IWN_ANT_C (1 << 2) 539/* Shortcuts. */ 540#define IWN_ANT_AB (IWN_ANT_A | IWN_ANT_B) 541#define IWN_ANT_BC (IWN_ANT_B | IWN_ANT_C) 542#define IWN_ANT_AC (IWN_ANT_A | IWN_ANT_C) 543#define IWN_ANT_ABC (IWN_ANT_A | IWN_ANT_B | IWN_ANT_C) 544 545/* Structure for command IWN_CMD_RXON. */ 546struct iwn_rxon { 547 uint8_t myaddr[IEEE80211_ADDR_LEN]; 548 uint16_t reserved1; 549 uint8_t bssid[IEEE80211_ADDR_LEN]; 550 uint16_t reserved2; 551 uint8_t wlap[IEEE80211_ADDR_LEN]; 552 uint16_t reserved3; 553 uint8_t mode; 554#define IWN_MODE_HOSTAP 1 555#define IWN_MODE_STA 3 556#define IWN_MODE_IBSS 4 557#define IWN_MODE_MONITOR 6 558#define IWN_MODE_2STA 8 559#define IWN_MODE_P2P 9 560 561 uint8_t air; 562 uint16_t rxchain; 563#define IWN_RXCHAIN_DRIVER_FORCE (1 << 0) 564#define IWN_RXCHAIN_VALID(x) (((x) & IWN_ANT_ABC) << 1) 565#define IWN_RXCHAIN_FORCE_SEL(x) (((x) & IWN_ANT_ABC) << 4) 566#define IWN_RXCHAIN_FORCE_MIMO_SEL(x) (((x) & IWN_ANT_ABC) << 7) 567#define IWN_RXCHAIN_IDLE_COUNT(x) ((x) << 10) 568#define IWN_RXCHAIN_MIMO_COUNT(x) ((x) << 12) 569#define IWN_RXCHAIN_MIMO_FORCE (1 << 14) 570 571 uint8_t ofdm_mask; 572 uint8_t cck_mask; 573 uint16_t associd; 574 uint32_t flags; 575#define IWN_RXON_24GHZ (1 << 0) 576#define IWN_RXON_CCK (1 << 1) 577#define IWN_RXON_AUTO (1 << 2) 578#define IWN_RXON_SHSLOT (1 << 4) 579#define IWN_RXON_SHPREAMBLE (1 << 5) 580#define IWN_RXON_NODIVERSITY (1 << 7) 581#define IWN_RXON_ANTENNA_A (1 << 8) 582#define IWN_RXON_ANTENNA_B (1 << 9) 583#define IWN_RXON_TSF (1 << 15) 584#define IWN_RXON_HT_HT40MINUS (1 << 22) 585#define IWN_RXON_HT_PROTMODE(x) (x << 23) 586#define IWN_RXON_HT_MODEPURE40 (1 << 25) 587#define IWN_RXON_HT_MODEMIXED (2 << 25) 588#define IWN_RXON_CTS_TO_SELF (1 << 30) 589 590 uint32_t filter; 591#define IWN_FILTER_PROMISC (1 << 0) 592#define IWN_FILTER_CTL (1 << 1) 593#define IWN_FILTER_MULTICAST (1 << 2) 594#define IWN_FILTER_NODECRYPT (1 << 3) 595#define IWN_FILTER_BSS (1 << 5) 596#define IWN_FILTER_BEACON (1 << 6) 597 598 uint8_t chan; 599 uint8_t reserved4; 600 uint8_t ht_single_mask; 601 uint8_t ht_dual_mask; 602 /* The following fields are for >=5000 Series only. */ 603 uint8_t ht_triple_mask; 604 uint8_t reserved5; 605 uint16_t acquisition; 606 uint16_t reserved6; 607} __packed; 608 609#define IWN4965_RXONSZ (sizeof (struct iwn_rxon) - 6) 610#define IWN5000_RXONSZ (sizeof (struct iwn_rxon)) 611 612/* Structure for command IWN_CMD_ASSOCIATE. */ 613struct iwn_assoc { 614 uint32_t flags; 615 uint32_t filter; 616 uint8_t ofdm_mask; 617 uint8_t cck_mask; 618 uint16_t reserved; 619} __packed; 620 621/* Structure for command IWN_CMD_EDCA_PARAMS. */ 622struct iwn_edca_params { 623 uint32_t flags; 624#define IWN_EDCA_UPDATE (1 << 0) 625#define IWN_EDCA_TXOP (1 << 4) 626 627 struct { 628 uint16_t cwmin; 629 uint16_t cwmax; 630 uint8_t aifsn; 631 uint8_t reserved; 632 uint16_t txoplimit; 633 } __packed ac[WME_NUM_AC]; 634} __packed; 635 636/* Structure for command IWN_CMD_TIMING. */ 637struct iwn_cmd_timing { 638 uint64_t tstamp; 639 uint16_t bintval; 640 uint16_t atim; 641 uint32_t binitval; 642 uint16_t lintval; 643 uint8_t dtim_period; 644 uint8_t delta_cp_bss_tbtts; 645} __packed; 646 647/* Structure for command IWN_CMD_ADD_NODE. */ 648struct iwn_node_info { 649 uint8_t control; 650#define IWN_NODE_UPDATE (1 << 0) 651 652 uint8_t reserved1[3]; 653 654 uint8_t macaddr[IEEE80211_ADDR_LEN]; 655 uint16_t reserved2; 656 uint8_t id; 657#define IWN_ID_BSS 0 658#define IWN_STA_ID 1 659 660#define IWN_PAN_ID_BCAST 14 661#define IWN5000_ID_BROADCAST 15 662#define IWN4965_ID_BROADCAST 31 663 664 uint8_t flags; 665#define IWN_FLAG_SET_KEY (1 << 0) 666#define IWN_FLAG_SET_DISABLE_TID (1 << 1) 667#define IWN_FLAG_SET_TXRATE (1 << 2) 668#define IWN_FLAG_SET_ADDBA (1 << 3) 669#define IWN_FLAG_SET_DELBA (1 << 4) 670 671 uint16_t reserved3; 672 uint16_t kflags; 673#define IWN_KFLAG_CCMP (1 << 1) 674#define IWN_KFLAG_MAP (1 << 3) 675#define IWN_KFLAG_KID(kid) ((kid) << 8) 676#define IWN_KFLAG_INVALID (1 << 11) 677#define IWN_KFLAG_GROUP (1 << 14) 678 679 uint8_t tsc2; /* TKIP TSC2 */ 680 uint8_t reserved4; 681 uint16_t ttak[5]; 682 uint8_t kid; 683 uint8_t reserved5; 684 uint8_t key[16]; 685 /* The following 3 fields are for 5000 Series only. */ 686 uint64_t tsc; 687 uint8_t rxmic[8]; 688 uint8_t txmic[8]; 689 690 uint32_t htflags; 691#define IWN_SMPS_MIMO_PROT (1 << 17) 692#define IWN_AMDPU_SIZE_FACTOR(x) ((x) << 19) 693#define IWN_NODE_HT40 (1 << 21) 694#define IWN_SMPS_MIMO_DIS (1 << 22) 695#define IWN_AMDPU_DENSITY(x) ((x) << 23) 696 697 uint32_t mask; 698 uint16_t disable_tid; 699 uint16_t reserved6; 700 uint8_t addba_tid; 701 uint8_t delba_tid; 702 uint16_t addba_ssn; 703 uint32_t reserved7; 704} __packed; 705 706struct iwn4965_node_info { 707 uint8_t control; 708 uint8_t reserved1[3]; 709 uint8_t macaddr[IEEE80211_ADDR_LEN]; 710 uint16_t reserved2; 711 uint8_t id; 712 uint8_t flags; 713 uint16_t reserved3; 714 uint16_t kflags; 715 uint8_t tsc2; /* TKIP TSC2 */ 716 uint8_t reserved4; 717 uint16_t ttak[5]; 718 uint8_t kid; 719 uint8_t reserved5; 720 uint8_t key[16]; 721 uint32_t htflags; 722 uint32_t mask; 723 uint16_t disable_tid; 724 uint16_t reserved6; 725 uint8_t addba_tid; 726 uint8_t delba_tid; 727 uint16_t addba_ssn; 728 uint32_t reserved7; 729} __packed; 730 731#define IWN_RFLAG_MCS (1 << 8) 732#define IWN_RFLAG_CCK (1 << 9) 733#define IWN_RFLAG_GREENFIELD (1 << 10) 734#define IWN_RFLAG_HT40 (1 << 11) 735#define IWN_RFLAG_DUPLICATE (1 << 12) 736#define IWN_RFLAG_SGI (1 << 13) 737#define IWN_RFLAG_ANT(x) ((x) << 14) 738 739/* Structure for command IWN_CMD_TX_DATA. */ 740struct iwn_cmd_data { 741 uint16_t len; 742 uint16_t lnext; 743 uint32_t flags; 744#define IWN_TX_NEED_PROTECTION (1 << 0) /* 5000 only */ 745#define IWN_TX_NEED_RTS (1 << 1) 746#define IWN_TX_NEED_CTS (1 << 2) 747#define IWN_TX_NEED_ACK (1 << 3) 748#define IWN_TX_LINKQ (1 << 4) 749#define IWN_TX_IMM_BA (1 << 6) 750#define IWN_TX_FULL_TXOP (1 << 7) 751#define IWN_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */ 752#define IWN_TX_AUTO_SEQ (1 << 13) 753#define IWN_TX_MORE_FRAG (1 << 14) 754#define IWN_TX_INSERT_TSTAMP (1 << 16) 755#define IWN_TX_NEED_PADDING (1 << 20) 756 757 uint32_t scratch; 758 uint32_t rate; 759 760 uint8_t id; 761 uint8_t security; 762#define IWN_CIPHER_WEP40 1 763#define IWN_CIPHER_CCMP 2 764#define IWN_CIPHER_TKIP 3 765#define IWN_CIPHER_WEP104 9 766 767 uint8_t linkq; 768 uint8_t reserved2; 769 uint8_t key[16]; 770 uint16_t fnext; 771 uint16_t reserved3; 772 uint32_t lifetime; 773#define IWN_LIFETIME_INFINITE 0xffffffff 774 775 uint32_t loaddr; 776 uint8_t hiaddr; 777 uint8_t rts_ntries; 778 uint8_t data_ntries; 779 uint8_t tid; 780 uint16_t timeout; 781 uint16_t txop; 782} __packed; 783 784/* Structure for command IWN_CMD_LINK_QUALITY. */ 785#define IWN_MAX_TX_RETRIES 16 786struct iwn_cmd_link_quality { 787 uint8_t id; 788 uint8_t reserved1; 789 uint16_t ctl; 790 uint8_t flags; 791 uint8_t mimo; 792 uint8_t antmsk_1stream; 793 uint8_t antmsk_2stream; 794 uint8_t ridx[WME_NUM_AC]; 795 uint16_t ampdu_limit; 796 uint8_t ampdu_threshold; 797 uint8_t ampdu_max; 798 uint32_t reserved2; 799 uint32_t retry[IWN_MAX_TX_RETRIES]; 800 uint32_t reserved3; 801} __packed; 802 803/* Structure for command IWN_CMD_SET_LED. */ 804struct iwn_cmd_led { 805 uint32_t unit; /* multiplier (in usecs) */ 806 uint8_t which; 807#define IWN_LED_ACTIVITY 1 808#define IWN_LED_LINK 2 809 810 uint8_t off; 811 uint8_t on; 812 uint8_t reserved; 813} __packed; 814 815/* Structure for command IWN5000_CMD_WIMAX_COEX. */ 816struct iwn5000_wimax_coex { 817 uint32_t flags; 818#define IWN_WIMAX_COEX_STA_TABLE_VALID (1 << 0) 819#define IWN_WIMAX_COEX_UNASSOC_WA_UNMASK (1 << 2) 820#define IWN_WIMAX_COEX_ASSOC_WA_UNMASK (1 << 3) 821#define IWN_WIMAX_COEX_ENABLE (1 << 7) 822 823 struct iwn5000_wimax_event { 824 uint8_t request; 825 uint8_t window; 826 uint8_t reserved; 827 uint8_t flags; 828 } __packed events[16]; 829} __packed; 830 831/* Structures for command IWN5000_CMD_CALIB_CONFIG. */ 832struct iwn5000_calib_elem { 833 uint32_t enable; 834 uint32_t start; 835#define IWN5000_CALIB_DC (1 << 1) 836 837 uint32_t send; 838 uint32_t apply; 839 uint32_t reserved; 840} __packed; 841 842struct iwn5000_calib_status { 843 struct iwn5000_calib_elem once; 844 struct iwn5000_calib_elem perd; 845 uint32_t flags; 846} __packed; 847 848struct iwn5000_calib_config { 849 struct iwn5000_calib_status ucode; 850 struct iwn5000_calib_status driver; 851 uint32_t reserved; 852} __packed; 853 854/* Structure for command IWN_CMD_SET_POWER_MODE. */ 855struct iwn_pmgt_cmd { 856 uint16_t flags; 857#define IWN_PS_ALLOW_SLEEP (1 << 0) 858#define IWN_PS_NOTIFY (1 << 1) 859#define IWN_PS_SLEEP_OVER_DTIM (1 << 2) 860#define IWN_PS_PCI_PMGT (1 << 3) 861#define IWN_PS_FAST_PD (1 << 4) 862#define IWN_PS_BEACON_FILTERING (1 << 5) 863#define IWN_PS_SHADOW_REG (1 << 6) 864#define IWN_PS_CT_KILL (1 << 7) 865#define IWN_PS_BT_SCD (1 << 8) 866#define IWN_PS_ADVANCED_PM (1 << 9) 867 868 uint8_t keepalive; 869 uint8_t debug; 870 uint32_t rxtimeout; 871 uint32_t txtimeout; 872 uint32_t intval[5]; 873 uint32_t beacons; 874} __packed; 875 876/* Structures for command IWN_CMD_SCAN. */ 877struct iwn_scan_essid { 878 uint8_t id; 879 uint8_t len; 880 uint8_t data[IEEE80211_NWID_LEN]; 881} __packed; 882 883struct iwn_scan_hdr { 884 uint16_t len; 885 uint8_t reserved1; 886 uint8_t nchan; 887 uint16_t quiet_time; 888 uint16_t quiet_threshold; 889 uint16_t crc_threshold; 890 uint16_t rxchain; 891 uint32_t max_svc; /* background scans */ 892 uint32_t pause_svc; /* background scans */ 893 uint32_t flags; 894 uint32_t filter; 895 896 /* Followed by a struct iwn_cmd_data. */ 897 /* Followed by an array of 20 structs iwn_scan_essid. */ 898 /* Followed by probe request body. */ 899 /* Followed by an array of ``nchan'' structs iwn_scan_chan. */ 900} __packed; 901 902struct iwn_scan_chan { 903 uint32_t flags; 904#define IWN_CHAN_PASSIVE (0 << 0) 905#define IWN_CHAN_ACTIVE (1 << 0) 906#define IWN_CHAN_NPBREQS(x) (((1 << (x)) - 1) << 1) 907 908 uint16_t chan; 909 uint8_t rf_gain; 910 uint8_t dsp_gain; 911 uint16_t active; /* msecs */ 912 uint16_t passive; /* msecs */ 913} __packed; 914 915#define IWN_SCAN_CRC_TH_DISABLED 0 916#define IWN_SCAN_CRC_TH_DEFAULT htole16(1) 917#define IWN_SCAN_CRC_TH_NEVER htole16(0xffff) 918 919/* Maximum size of a scan command. */ 920#define IWN_SCAN_MAXSZ (MCLBYTES - 4) 921 922#define IWN_ACTIVE_DWELL_TIME_24 (30) /* all times in msec */ 923#define IWN_ACTIVE_DWELL_TIME_52 (20) 924#define IWN_ACTIVE_DWELL_FACTOR_24 (3) 925#define IWN_ACTIVE_DWELL_FACTOR_52 (2) 926 927#define IWN_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */ 928#define IWN_PASSIVE_DWELL_TIME_52 (10) 929#define IWN_PASSIVE_DWELL_BASE (100) 930#define IWN_CHANNEL_TUNE_TIME (5) 931 932#define IWN_SCAN_CHAN_TIMEOUT 2 933 934/* Structure for command IWN_CMD_TXPOWER (4965AGN only.) */ 935#define IWN_RIDX_MAX 32 936struct iwn4965_cmd_txpower { 937 uint8_t band; 938 uint8_t reserved1; 939 uint8_t chan; 940 uint8_t reserved2; 941 struct { 942 uint8_t rf_gain[2]; 943 uint8_t dsp_gain[2]; 944 } __packed power[IWN_RIDX_MAX + 1]; 945} __packed; 946 947/* Structure for command IWN_CMD_TXPOWER_DBM (5000 Series only.) */ 948struct iwn5000_cmd_txpower { 949 int8_t global_limit; /* in half-dBm */ 950#define IWN5000_TXPOWER_AUTO 0x7f 951#define IWN5000_TXPOWER_MAX_DBM 16 952 953 uint8_t flags; 954#define IWN5000_TXPOWER_NO_CLOSED (1 << 6) 955 956 int8_t srv_limit; /* in half-dBm */ 957 uint8_t reserved; 958} __packed; 959 960/* Structures for command IWN_CMD_BLUETOOTH. */ 961struct iwn_bluetooth { 962 uint8_t flags; 963#define IWN_BT_COEX_CHAN_ANN (1 << 0) 964#define IWN_BT_COEX_BT_PRIO (1 << 1) 965#define IWN_BT_COEX_2_WIRE (1 << 2) 966 967 uint8_t lead_time; 968#define IWN_BT_LEAD_TIME_DEF 30 969 970 uint8_t max_kill; 971#define IWN_BT_MAX_KILL_DEF 5 972 973 uint8_t reserved; 974 uint32_t kill_ack; 975 uint32_t kill_cts; 976} __packed; 977 978struct iwn6000_btcoex_config { 979 uint8_t flags; 980#define IWN_BT_FLAG_COEX6000_CHAN_INHIBITION 1 981#define IWN_BT_FLAG_COEX6000_MODE_MASK ((1 << 3) | (1 << 4) | (1 << 5 )) 982#define IWN_BT_FLAG_COEX6000_MODE_SHIFT 3 983#define IWN_BT_FLAG_COEX6000_MODE_DISABLED 0 984#define IWN_BT_FLAG_COEX6000_MODE_LEGACY_2W 1 985#define IWN_BT_FLAG_COEX6000_MODE_3W 2 986#define IWN_BT_FLAG_COEX6000_MODE_4W 3 987 988#define IWN_BT_FLAG_UCODE_DEFAULT (1 << 6) 989#define IWN_BT_FLAG_SYNC_2_BT_DISABLE (1 << 7) 990 uint8_t lead_time; 991 uint8_t max_kill; 992 uint8_t bt3_t7_timer; 993 uint32_t kill_ack; 994 uint32_t kill_cts; 995 uint8_t sample_time; 996 uint8_t bt3_t2_timer; 997 uint16_t bt4_reaction; 998 uint32_t lookup_table[12]; 999 uint16_t bt4_decision; 1000 uint16_t valid; 1001 uint8_t prio_boost; 1002 uint8_t tx_prio_boost; 1003 uint16_t rx_prio_boost; 1004} __packed; 1005 1006/* Structure for enhanced command IWN_CMD_BLUETOOTH for 2000 Series. */ 1007struct iwn2000_btcoex_config { 1008 uint8_t flags; /* Cf Flags in iwn6000_btcoex_config */ 1009 uint8_t lead_time; 1010 uint8_t max_kill; 1011 uint8_t bt3_t7_timer; 1012 uint32_t kill_ack; 1013 uint32_t kill_cts; 1014 uint8_t sample_time; 1015 uint8_t bt3_t2_timer; 1016 uint16_t bt4_reaction; 1017 uint32_t lookup_table[12]; 1018 uint16_t bt4_decision; 1019 uint16_t valid; 1020 1021 uint32_t prio_boost; /* size change prior to iwn6000_btcoex_config */ 1022 uint8_t reserved; /* added prior to iwn6000_btcoex_config */ 1023 1024 uint8_t tx_prio_boost; 1025 uint16_t rx_prio_boost; 1026} __packed; 1027 1028struct iwn_btcoex_priotable { 1029 uint8_t calib_init1; 1030 uint8_t calib_init2; 1031 uint8_t calib_periodic_low1; 1032 uint8_t calib_periodic_low2; 1033 uint8_t calib_periodic_high1; 1034 uint8_t calib_periodic_high2; 1035 uint8_t dtim; 1036 uint8_t scan52; 1037 uint8_t scan24; 1038 uint8_t reserved[7]; 1039} __packed; 1040 1041struct iwn_btcoex_prot { 1042 uint8_t open; 1043 uint8_t type; 1044 uint8_t reserved[2]; 1045} __packed; 1046 1047/* Structure for command IWN_CMD_SET_CRITICAL_TEMP. */ 1048struct iwn_critical_temp { 1049 uint32_t reserved; 1050 uint32_t tempM; 1051 uint32_t tempR; 1052/* degK <-> degC conversion macros. */ 1053#define IWN_CTOK(c) ((c) + 273) 1054#define IWN_KTOC(k) ((k) - 273) 1055#define IWN_CTOMUK(c) (((c) * 1000000) + 273150000) 1056} __packed; 1057 1058/* Structures for command IWN_CMD_SET_SENSITIVITY. */ 1059struct iwn_sensitivity_cmd { 1060 uint16_t which; 1061#define IWN_SENSITIVITY_DEFAULTTBL 0 1062#define IWN_SENSITIVITY_WORKTBL 1 1063 1064 uint16_t energy_cck; 1065 uint16_t energy_ofdm; 1066 uint16_t corr_ofdm_x1; 1067 uint16_t corr_ofdm_mrc_x1; 1068 uint16_t corr_cck_mrc_x4; 1069 uint16_t corr_ofdm_x4; 1070 uint16_t corr_ofdm_mrc_x4; 1071 uint16_t corr_barker; 1072 uint16_t corr_barker_mrc; 1073 uint16_t corr_cck_x4; 1074 uint16_t energy_ofdm_th; 1075} __packed; 1076 1077struct iwn_enhanced_sensitivity_cmd { 1078 uint16_t which; 1079 uint16_t energy_cck; 1080 uint16_t energy_ofdm; 1081 uint16_t corr_ofdm_x1; 1082 uint16_t corr_ofdm_mrc_x1; 1083 uint16_t corr_cck_mrc_x4; 1084 uint16_t corr_ofdm_x4; 1085 uint16_t corr_ofdm_mrc_x4; 1086 uint16_t corr_barker; 1087 uint16_t corr_barker_mrc; 1088 uint16_t corr_cck_x4; 1089 uint16_t energy_ofdm_th; 1090 /* "Enhanced" part. */ 1091 uint16_t ina_det_ofdm; 1092 uint16_t ina_det_cck; 1093 uint16_t corr_11_9_en; 1094 uint16_t ofdm_det_slope_mrc; 1095 uint16_t ofdm_det_icept_mrc; 1096 uint16_t ofdm_det_slope; 1097 uint16_t ofdm_det_icept; 1098 uint16_t cck_det_slope_mrc; 1099 uint16_t cck_det_icept_mrc; 1100 uint16_t cck_det_slope; 1101 uint16_t cck_det_icept; 1102 uint16_t reserved; 1103} __packed; 1104 1105/* Structures for command IWN_CMD_PHY_CALIB. */ 1106struct iwn_phy_calib { 1107 uint8_t code; 1108#define IWN4965_PHY_CALIB_DIFF_GAIN 7 1109#define IWN5000_PHY_CALIB_DC 8 1110#define IWN5000_PHY_CALIB_LO 9 1111#define IWN5000_PHY_CALIB_TX_IQ 11 1112#define IWN5000_PHY_CALIB_CRYSTAL 15 1113#define IWN5000_PHY_CALIB_BASE_BAND 16 1114#define IWN5000_PHY_CALIB_TX_IQ_PERIODIC 17 1115#define IWN5000_PHY_CALIB_TEMP_OFFSET 18 1116 1117#define IWN5000_PHY_CALIB_RESET_NOISE_GAIN 18 1118#define IWN5000_PHY_CALIB_NOISE_GAIN 19 1119 1120 uint8_t group; 1121 uint8_t ngroups; 1122 uint8_t isvalid; 1123} __packed; 1124 1125struct iwn5000_phy_calib_crystal { 1126 uint8_t code; 1127 uint8_t group; 1128 uint8_t ngroups; 1129 uint8_t isvalid; 1130 1131 uint8_t cap_pin[2]; 1132 uint8_t reserved[2]; 1133} __packed; 1134 1135struct iwn5000_phy_calib_temp_offset { 1136 uint8_t code; 1137 uint8_t group; 1138 uint8_t ngroups; 1139 uint8_t isvalid; 1140 int16_t offset; 1141#define IWN_DEFAULT_TEMP_OFFSET 2700 1142 1143 uint16_t reserved; 1144} __packed; 1145 1146struct iwn5000_phy_calib_temp_offsetv2 { 1147 uint8_t code; 1148 uint8_t group; 1149 uint8_t ngroups; 1150 uint8_t isvalid; 1151 int16_t offset_high; 1152 int16_t offset_low; 1153 int16_t burnt_voltage_ref; 1154 int16_t reserved; 1155} __packed; 1156 1157struct iwn_phy_calib_gain { 1158 uint8_t code; 1159 uint8_t group; 1160 uint8_t ngroups; 1161 uint8_t isvalid; 1162 1163 int8_t gain[3]; 1164 uint8_t reserved; 1165} __packed; 1166 1167/* Structure for command IWN_CMD_SPECTRUM_MEASUREMENT. */ 1168struct iwn_spectrum_cmd { 1169 uint16_t len; 1170 uint8_t token; 1171 uint8_t id; 1172 uint8_t origin; 1173 uint8_t periodic; 1174 uint16_t timeout; 1175 uint32_t start; 1176 uint32_t reserved1; 1177 uint32_t flags; 1178 uint32_t filter; 1179 uint16_t nchan; 1180 uint16_t reserved2; 1181 struct { 1182 uint32_t duration; 1183 uint8_t chan; 1184 uint8_t type; 1185#define IWN_MEASUREMENT_BASIC (1 << 0) 1186#define IWN_MEASUREMENT_CCA (1 << 1) 1187#define IWN_MEASUREMENT_RPI_HISTOGRAM (1 << 2) 1188#define IWN_MEASUREMENT_NOISE_HISTOGRAM (1 << 3) 1189#define IWN_MEASUREMENT_FRAME (1 << 4) 1190#define IWN_MEASUREMENT_IDLE (1 << 7) 1191 1192 uint16_t reserved; 1193 } __packed chan[10]; 1194} __packed; 1195 1196/* Structure for IWN_UC_READY notification. */ 1197#define IWN_NATTEN_GROUPS 5 1198struct iwn_ucode_info { 1199 uint8_t minor; 1200 uint8_t major; 1201 uint16_t reserved1; 1202 uint8_t revision[8]; 1203 uint8_t type; 1204 uint8_t subtype; 1205#define IWN_UCODE_RUNTIME 0 1206#define IWN_UCODE_INIT 9 1207 1208 uint16_t reserved2; 1209 uint32_t logptr; 1210 uint32_t errptr; 1211 uint32_t tstamp; 1212 uint32_t valid; 1213 1214 /* The following fields are for UCODE_INIT only. */ 1215 int32_t volt; 1216 struct { 1217 int32_t chan20MHz; 1218 int32_t chan40MHz; 1219 } __packed temp[4]; 1220 int32_t atten[IWN_NATTEN_GROUPS][2]; 1221} __packed; 1222 1223/* Structures for IWN_TX_DONE notification. */ 1224#define IWN_TX_STATUS_MSK 0xff 1225#define TX_STATUS_SUCCESS 0x01 1226#define TX_STATUS_DIRECT_DONE 0x02 1227 1228#define IWN_TX_SUCCESS 0x00 1229#define IWN_TX_FAIL 0x80 /* all failures have 0x80 set */ 1230#define IWN_TX_FAIL_SHORT_LIMIT 0x82 /* too many RTS retries */ 1231#define IWN_TX_FAIL_LONG_LIMIT 0x83 /* too many retries */ 1232#define IWN_TX_FAIL_FIFO_UNDERRRUN 0x84 /* tx fifo not kept running */ 1233#define IWN_TX_FAIL_DEST_IN_PS 0x88 /* sta found in power save */ 1234#define IWN_TX_FAIL_TX_LOCKED 0x90 /* waiting to see traffic */ 1235 1236struct iwn4965_tx_stat { 1237 uint8_t nframes; 1238 uint8_t btkillcnt; 1239 uint8_t rtsfailcnt; 1240 uint8_t ackfailcnt; 1241 uint32_t rate; 1242 uint16_t duration; 1243 uint16_t reserved; 1244 uint32_t power[2]; 1245 uint32_t status; 1246} __packed; 1247 1248struct iwn5000_tx_stat { 1249 uint8_t nframes; /* 1 no aggregation, >1 aggregation */ 1250 uint8_t btkillcnt; 1251 uint8_t rtsfailcnt; 1252 uint8_t ackfailcnt; 1253 uint32_t rate; 1254 uint16_t duration; 1255 uint16_t reserved; 1256 uint32_t power[2]; 1257 uint32_t info; 1258 uint16_t seq; 1259 uint16_t len; 1260 uint8_t tlc; 1261 uint8_t ratid; /* tid (0:3), sta_id (4:7) */ 1262 uint8_t fc[2]; 1263 uint16_t status; 1264 uint16_t sequence; 1265} __packed; 1266 1267/* Structure for IWN_BEACON_MISSED notification. */ 1268struct iwn_beacon_missed { 1269 uint32_t consecutive; 1270 uint32_t total; 1271 uint32_t expected; 1272 uint32_t received; 1273} __packed; 1274 1275/* Structure for IWN_MPDU_RX_DONE notification. */ 1276struct iwn_rx_mpdu { 1277 uint16_t len; 1278 uint16_t reserved; 1279} __packed; 1280 1281/* Structures for IWN_RX_DONE and IWN_MPDU_RX_DONE notifications. */ 1282struct iwn4965_rx_phystat { 1283 uint16_t antenna; 1284 uint16_t agc; 1285 uint8_t rssi[6]; 1286} __packed; 1287 1288struct iwn5000_rx_phystat { 1289 uint32_t reserved1; 1290 uint32_t agc; 1291 uint16_t rssi[3]; 1292} __packed; 1293 1294struct iwn_rx_stat { 1295 uint8_t phy_len; 1296 uint8_t cfg_phy_len; 1297#define IWN_STAT_MAXLEN 20 1298 1299 uint8_t id; 1300 uint8_t reserved1; 1301 uint64_t tstamp; 1302 uint32_t beacon; 1303 uint16_t flags; 1304#define IWN_STAT_FLAG_SHPREAMBLE (1 << 2) 1305 1306 uint16_t chan; 1307 uint8_t phybuf[32]; 1308 uint32_t rate; 1309/* 1310 * rate bit fields 1311 * 1312 * High-throughput (HT) rate format for bits 7:0 (bit 8 must be "1"): 1313 * 2-0: 0) 6 Mbps 1314 * 1) 12 Mbps 1315 * 2) 18 Mbps 1316 * 3) 24 Mbps 1317 * 4) 36 Mbps 1318 * 5) 48 Mbps 1319 * 6) 54 Mbps 1320 * 7) 60 Mbps 1321 * 1322 * 4-3: 0) Single stream (SISO) 1323 * 1) Dual stream (MIMO) 1324 * 2) Triple stream (MIMO) 1325 * 1326 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data 1327 * 1328 * Legacy OFDM rate format for bits 7:0 (bit 8 must be "0", bit 9 "0"): 1329 * 3-0: 0xD) 6 Mbps 1330 * 0xF) 9 Mbps 1331 * 0x5) 12 Mbps 1332 * 0x7) 18 Mbps 1333 * 0x9) 24 Mbps 1334 * 0xB) 36 Mbps 1335 * 0x1) 48 Mbps 1336 * 0x3) 54 Mbps 1337 * 1338 * Legacy CCK rate format for bits 7:0 (bit 8 must be "0", bit 9 "1"): 1339 * 6-0: 10) 1 Mbps 1340 * 20) 2 Mbps 1341 * 55) 5.5 Mbps 1342 * 110) 11 Mbps 1343 * 1344 */ 1345 uint16_t len; 1346 uint16_t reserve3; 1347} __packed; 1348 1349#define IWN_RSSI_TO_DBM 44 1350 1351/* Structure for IWN_RX_COMPRESSED_BA notification. */ 1352struct iwn_compressed_ba { 1353 uint8_t macaddr[IEEE80211_ADDR_LEN]; 1354 uint16_t reserved; 1355 uint8_t id; 1356 uint8_t tid; 1357 uint16_t seq; 1358 uint64_t bitmap; 1359 uint16_t qid; 1360 uint16_t ssn; 1361} __packed; 1362 1363/* Structure for IWN_START_SCAN notification. */ 1364struct iwn_start_scan { 1365 uint64_t tstamp; 1366 uint32_t tbeacon; 1367 uint8_t chan; 1368 uint8_t band; 1369 uint16_t reserved; 1370 uint32_t status; 1371} __packed; 1372 1373/* Structure for IWN_STOP_SCAN notification. */ 1374struct iwn_stop_scan { 1375 uint8_t nchan; 1376 uint8_t status; 1377 uint8_t reserved; 1378 uint8_t chan; 1379 uint64_t tsf; 1380} __packed; 1381 1382/* Structure for IWN_SPECTRUM_MEASUREMENT notification. */ 1383struct iwn_spectrum_notif { 1384 uint8_t id; 1385 uint8_t token; 1386 uint8_t idx; 1387 uint8_t state; 1388#define IWN_MEASUREMENT_START 0 1389#define IWN_MEASUREMENT_STOP 1 1390 1391 uint32_t start; 1392 uint8_t band; 1393 uint8_t chan; 1394 uint8_t type; 1395 uint8_t reserved1; 1396 uint32_t cca_ofdm; 1397 uint32_t cca_cck; 1398 uint32_t cca_time; 1399 uint8_t basic; 1400 uint8_t reserved2[3]; 1401 uint32_t ofdm[8]; 1402 uint32_t cck[8]; 1403 uint32_t stop; 1404 uint32_t status; 1405#define IWN_MEASUREMENT_OK 0 1406#define IWN_MEASUREMENT_CONCURRENT 1 1407#define IWN_MEASUREMENT_CSA_CONFLICT 2 1408#define IWN_MEASUREMENT_TGH_CONFLICT 3 1409#define IWN_MEASUREMENT_STOPPED 6 1410#define IWN_MEASUREMENT_TIMEOUT 7 1411#define IWN_MEASUREMENT_FAILED 8 1412} __packed; 1413 1414/* Structures for IWN_{RX,BEACON}_STATISTICS notification. */ 1415struct iwn_rx_phy_stats { 1416 uint32_t ina; 1417 uint32_t fina; 1418 uint32_t bad_plcp; 1419 uint32_t bad_crc32; 1420 uint32_t overrun; 1421 uint32_t eoverrun; 1422 uint32_t good_crc32; 1423 uint32_t fa; 1424 uint32_t bad_fina_sync; 1425 uint32_t sfd_timeout; 1426 uint32_t fina_timeout; 1427 uint32_t no_rts_ack; 1428 uint32_t rxe_limit; 1429 uint32_t ack; 1430 uint32_t cts; 1431 uint32_t ba_resp; 1432 uint32_t dsp_kill; 1433 uint32_t bad_mh; 1434 uint32_t rssi_sum; 1435 uint32_t reserved; 1436} __packed; 1437 1438struct iwn_rx_general_stats { 1439 uint32_t bad_cts; 1440 uint32_t bad_ack; 1441 uint32_t not_bss; 1442 uint32_t filtered; 1443 uint32_t bad_chan; 1444 uint32_t beacons; 1445 uint32_t missed_beacons; 1446 uint32_t adc_saturated; /* time in 0.8us */ 1447 uint32_t ina_searched; /* time in 0.8us */ 1448 uint32_t noise[3]; 1449 uint32_t flags; 1450 uint32_t load; 1451 uint32_t fa; 1452 uint32_t rssi[3]; 1453 uint32_t energy[3]; 1454} __packed; 1455 1456struct iwn_rx_ht_phy_stats { 1457 uint32_t bad_plcp; 1458 uint32_t overrun; 1459 uint32_t eoverrun; 1460 uint32_t good_crc32; 1461 uint32_t bad_crc32; 1462 uint32_t bad_mh; 1463 uint32_t good_ampdu_crc32; 1464 uint32_t ampdu; 1465 uint32_t fragment; 1466 uint32_t reserved; 1467} __packed; 1468 1469struct iwn_rx_stats { 1470 struct iwn_rx_phy_stats ofdm; 1471 struct iwn_rx_phy_stats cck; 1472 struct iwn_rx_general_stats general; 1473 struct iwn_rx_ht_phy_stats ht; 1474} __packed; 1475 1476struct iwn_tx_stats { 1477 uint32_t preamble; 1478 uint32_t rx_detected; 1479 uint32_t bt_defer; 1480 uint32_t bt_kill; 1481 uint32_t short_len; 1482 uint32_t cts_timeout; 1483 uint32_t ack_timeout; 1484 uint32_t exp_ack; 1485 uint32_t ack; 1486 uint32_t msdu; 1487 uint32_t busrt_err1; 1488 uint32_t burst_err2; 1489 uint32_t cts_collision; 1490 uint32_t ack_collision; 1491 uint32_t ba_timeout; 1492 uint32_t ba_resched; 1493 uint32_t query_ampdu; 1494 uint32_t query; 1495 uint32_t query_ampdu_frag; 1496 uint32_t query_mismatch; 1497 uint32_t not_ready; 1498 uint32_t underrun; 1499 uint32_t bt_ht_kill; 1500 uint32_t rx_ba_resp; 1501 uint32_t reserved[2]; 1502} __packed; 1503 1504struct iwn_general_stats { 1505 uint32_t temp; 1506 uint32_t temp_m; 1507 uint32_t burst_check; 1508 uint32_t burst; 1509 uint32_t reserved1[4]; 1510 uint32_t sleep; 1511 uint32_t slot_out; 1512 uint32_t slot_idle; 1513 uint32_t ttl_tstamp; 1514 uint32_t tx_ant_a; 1515 uint32_t tx_ant_b; 1516 uint32_t exec; 1517 uint32_t probe; 1518 uint32_t reserved2[2]; 1519 uint32_t rx_enabled; 1520 uint32_t reserved3[3]; 1521} __packed; 1522 1523struct iwn_stats { 1524 uint32_t flags; 1525 struct iwn_rx_stats rx; 1526 struct iwn_tx_stats tx; 1527 struct iwn_general_stats general; 1528} __packed; 1529 1530 1531/* Firmware error dump. */ 1532struct iwn_fw_dump { 1533 uint32_t valid; 1534 uint32_t id; 1535 uint32_t pc; 1536 uint32_t branch_link[2]; 1537 uint32_t interrupt_link[2]; 1538 uint32_t error_data[2]; 1539 uint32_t src_line; 1540 uint32_t tsf; 1541 uint32_t time[2]; 1542} __packed; 1543 1544/* TLV firmware header. */ 1545struct iwn_fw_tlv_hdr { 1546 uint32_t zero; /* Always 0, to differentiate from legacy. */ 1547 uint32_t signature; 1548#define IWN_FW_SIGNATURE 0x0a4c5749 /* "IWL\n" */ 1549 1550 uint8_t descr[64]; 1551 uint32_t rev; 1552#define IWN_FW_API(x) (((x) >> 8) & 0xff) 1553 1554 uint32_t build; 1555 uint64_t altmask; 1556} __packed; 1557 1558/* TLV header. */ 1559struct iwn_fw_tlv { 1560 uint16_t type; 1561#define IWN_FW_TLV_MAIN_TEXT 1 1562#define IWN_FW_TLV_MAIN_DATA 2 1563#define IWN_FW_TLV_INIT_TEXT 3 1564#define IWN_FW_TLV_INIT_DATA 4 1565#define IWN_FW_TLV_BOOT_TEXT 5 1566#define IWN_FW_TLV_PBREQ_MAXLEN 6 1567#define IWN_FW_TLV_PAN 7 1568#define IWN_FW_TLV_RUNT_EVTLOG_PTR 8 1569#define IWN_FW_TLV_RUNT_EVTLOG_SIZE 9 1570#define IWN_FW_TLV_RUNT_ERRLOG_PTR 10 1571#define IWN_FW_TLV_INIT_EVTLOG_PTR 11 1572#define IWN_FW_TLV_INIT_EVTLOG_SIZE 12 1573#define IWN_FW_TLV_INIT_ERRLOG_PTR 13 1574#define IWN_FW_TLV_ENH_SENS 14 1575#define IWN_FW_TLV_PHY_CALIB 15 1576#define IWN_FW_TLV_WOWLAN_INST 16 1577#define IWN_FW_TLV_WOWLAN_DATA 17 1578#define IWN_FW_TLV_FLAGS 18 1579 1580 uint16_t alt; 1581 uint32_t len; 1582} __packed; 1583 1584#define IWN4965_FW_TEXT_MAXSZ ( 96 * 1024) 1585#define IWN4965_FW_DATA_MAXSZ ( 40 * 1024) 1586#define IWN5000_FW_TEXT_MAXSZ (256 * 1024) 1587#define IWN5000_FW_DATA_MAXSZ ( 80 * 1024) 1588#define IWN_FW_BOOT_TEXT_MAXSZ 1024 1589#define IWN4965_FWSZ (IWN4965_FW_TEXT_MAXSZ + IWN4965_FW_DATA_MAXSZ) 1590#define IWN5000_FWSZ IWN5000_FW_TEXT_MAXSZ 1591 1592/* 1593 * Offsets into EEPROM. 1594 */ 1595#define IWN_EEPROM_MAC 0x015 1596#define IWN_EEPROM_SKU_CAP 0x045 1597#define IWN_EEPROM_RFCFG 0x048 1598#define IWN4965_EEPROM_DOMAIN 0x060 1599#define IWN4965_EEPROM_BAND1 0x063 1600#define IWN5000_EEPROM_REG 0x066 1601#define IWN5000_EEPROM_CAL 0x067 1602#define IWN4965_EEPROM_BAND2 0x072 1603#define IWN4965_EEPROM_BAND3 0x080 1604#define IWN4965_EEPROM_BAND4 0x08d 1605#define IWN4965_EEPROM_BAND5 0x099 1606#define IWN4965_EEPROM_BAND6 0x0a0 1607#define IWN4965_EEPROM_BAND7 0x0a8 1608#define IWN4965_EEPROM_MAXPOW 0x0e8 1609#define IWN4965_EEPROM_VOLTAGE 0x0e9 1610#define IWN4965_EEPROM_BANDS 0x0ea 1611/* Indirect offsets. */ 1612#define IWN5000_EEPROM_NO_HT40 0x000 1613#define IWN5000_EEPROM_DOMAIN 0x001 1614#define IWN5000_EEPROM_BAND1 0x004 1615#define IWN5000_EEPROM_BAND2 0x013 1616#define IWN5000_EEPROM_BAND3 0x021 1617#define IWN5000_EEPROM_BAND4 0x02e 1618#define IWN5000_EEPROM_BAND5 0x03a 1619#define IWN5000_EEPROM_BAND6 0x041 1620#define IWN6000_EEPROM_BAND6 0x040 1621#define IWN5000_EEPROM_BAND7 0x049 1622#define IWN6000_EEPROM_ENHINFO 0x054 1623#define IWN5000_EEPROM_CRYSTAL 0x128 1624#define IWN5000_EEPROM_TEMP 0x12a 1625#define IWN5000_EEPROM_VOLT 0x12b 1626 1627/* Possible flags for IWN_EEPROM_SKU_CAP. */ 1628#define IWN_EEPROM_SKU_CAP_11N (1 << 6) 1629#define IWN_EEPROM_SKU_CAP_AMT (1 << 7) 1630#define IWN_EEPROM_SKU_CAP_IPAN (1 << 8) 1631 1632/* Possible flags for IWN_EEPROM_RFCFG. */ 1633#define IWN_RFCFG_TYPE(x) (((x) >> 0) & 0x3) 1634#define IWN_RFCFG_STEP(x) (((x) >> 2) & 0x3) 1635#define IWN_RFCFG_DASH(x) (((x) >> 4) & 0x3) 1636#define IWN_RFCFG_TXANTMSK(x) (((x) >> 8) & 0xf) 1637#define IWN_RFCFG_RXANTMSK(x) (((x) >> 12) & 0xf) 1638 1639struct iwn_eeprom_chan { 1640 uint8_t flags; 1641#define IWN_EEPROM_CHAN_VALID (1 << 0) 1642#define IWN_EEPROM_CHAN_IBSS (1 << 1) 1643#define IWN_EEPROM_CHAN_ACTIVE (1 << 3) 1644#define IWN_EEPROM_CHAN_RADAR (1 << 4) 1645 1646 int8_t maxpwr; 1647} __packed; 1648 1649struct iwn_eeprom_enhinfo { 1650 uint8_t flags; 1651#define IWN_ENHINFO_VALID 0x01 1652#define IWN_ENHINFO_5GHZ 0x02 1653#define IWN_ENHINFO_OFDM 0x04 1654#define IWN_ENHINFO_HT40 0x08 1655#define IWN_ENHINFO_HTAP 0x10 1656#define IWN_ENHINFO_RES1 0x20 1657#define IWN_ENHINFO_RES2 0x40 1658#define IWN_ENHINFO_COMMON 0x80 1659 1660 uint8_t chan; 1661 int8_t chain[3]; /* max power in half-dBm */ 1662 uint8_t reserved; 1663 int8_t mimo2; /* max power in half-dBm */ 1664 int8_t mimo3; /* max power in half-dBm */ 1665} __packed; 1666 1667struct iwn5000_eeprom_calib_hdr { 1668 uint8_t version; 1669 uint8_t pa_type; 1670 uint16_t volt; 1671} __packed; 1672 1673#define IWN_NSAMPLES 3 1674struct iwn4965_eeprom_chan_samples { 1675 uint8_t num; 1676 struct { 1677 uint8_t temp; 1678 uint8_t gain; 1679 uint8_t power; 1680 int8_t pa_det; 1681 } samples[2][IWN_NSAMPLES]; 1682} __packed; 1683 1684#define IWN_NBANDS 8 1685struct iwn4965_eeprom_band { 1686 uint8_t lo; /* low channel number */ 1687 uint8_t hi; /* high channel number */ 1688 struct iwn4965_eeprom_chan_samples chans[2]; 1689} __packed; 1690 1691/* 1692 * Offsets of channels descriptions in EEPROM. 1693 */ 1694static const uint32_t iwn4965_regulatory_bands[IWN_NBANDS] = { 1695 IWN4965_EEPROM_BAND1, 1696 IWN4965_EEPROM_BAND2, 1697 IWN4965_EEPROM_BAND3, 1698 IWN4965_EEPROM_BAND4, 1699 IWN4965_EEPROM_BAND5, 1700 IWN4965_EEPROM_BAND6, 1701 IWN4965_EEPROM_BAND7 1702}; 1703 1704static const uint32_t iwn5000_regulatory_bands[IWN_NBANDS] = { 1705 IWN5000_EEPROM_BAND1, 1706 IWN5000_EEPROM_BAND2, 1707 IWN5000_EEPROM_BAND3, 1708 IWN5000_EEPROM_BAND4, 1709 IWN5000_EEPROM_BAND5, 1710 IWN5000_EEPROM_BAND6, 1711 IWN5000_EEPROM_BAND7 1712}; 1713 1714static const uint32_t iwn6000_regulatory_bands[IWN_NBANDS] = { 1715 IWN5000_EEPROM_BAND1, 1716 IWN5000_EEPROM_BAND2, 1717 IWN5000_EEPROM_BAND3, 1718 IWN5000_EEPROM_BAND4, 1719 IWN5000_EEPROM_BAND5, 1720 IWN6000_EEPROM_BAND6, 1721 IWN5000_EEPROM_BAND7 1722}; 1723 1724static const uint32_t iwn1000_regulatory_bands[IWN_NBANDS] = { 1725 IWN5000_EEPROM_BAND1, 1726 IWN5000_EEPROM_BAND2, 1727 IWN5000_EEPROM_BAND3, 1728 IWN5000_EEPROM_BAND4, 1729 IWN5000_EEPROM_BAND5, 1730 IWN5000_EEPROM_BAND6, 1731 IWN5000_EEPROM_NO_HT40, 1732}; 1733 1734#define IWN_CHAN_BANDS_COUNT 7 1735#define IWN_MAX_CHAN_PER_BAND 14 1736static const struct iwn_chan_band { 1737 uint8_t nchan; 1738 uint8_t chan[IWN_MAX_CHAN_PER_BAND]; 1739} iwn_bands[] = { 1740 /* 20MHz channels, 2GHz band. */ 1741 { 14, { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } }, 1742 /* 20MHz channels, 5GHz band. */ 1743 { 13, { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } }, 1744 { 12, { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } }, 1745 { 11, { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } }, 1746 { 6, { 145, 149, 153, 157, 161, 165 } }, 1747 /* 40MHz channels (primary channels), 2GHz band. */ 1748 { 7, { 1, 2, 3, 4, 5, 6, 7 } }, 1749 /* 40MHz channels (primary channels), 5GHz band. */ 1750 { 11, { 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157 } } 1751}; 1752 1753static const uint8_t iwn_bss_ac_to_queue[] = { 1754 2, 3, 1, 0, 1755}; 1756 1757static const uint8_t iwn_pan_ac_to_queue[] = { 1758 5, 4, 6, 7, 1759}; 1760#define IWN1000_OTP_NBLOCKS 3 1761#define IWN6000_OTP_NBLOCKS 4 1762#define IWN6050_OTP_NBLOCKS 7 1763 1764/* HW rate indices. */ 1765#define IWN_RIDX_CCK1 0 1766#define IWN_RIDX_OFDM6 4 1767 1768#define IWN4965_MAX_PWR_INDEX 107 1769#define IWN_POWERSAVE_LVL_NONE 0 1770#define IWN_POWERSAVE_LVL_VOIP_COMPATIBLE 1 1771#define IWN_POWERSAVE_LVL_MAX 5 1772 1773#define IWN_POWERSAVE_LVL_DEFAULT IWN_POWERSAVE_LVL_NONE 1774 1775/* DTIM value to pass in for IWN_POWERSAVE_LVL_VOIP_COMPATIBLE */ 1776#define IWN_POWERSAVE_DTIM_VOIP_COMPATIBLE 2 1777 1778/* 1779 * RF Tx gain values from highest to lowest power (values obtained from 1780 * the reference driver.) 1781 */ 1782static const uint8_t iwn4965_rf_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1783 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, 1784 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 0x39, 0x38, 1785 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 0x35, 0x35, 1786 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x31, 0x31, 1787 0x31, 0x30, 0x30, 0x30, 0x06, 0x06, 0x06, 0x05, 0x05, 0x05, 0x04, 1788 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01, 1789 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1790 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1791 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1792 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1793}; 1794 1795static const uint8_t iwn4965_rf_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1796 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 1797 0x3c, 0x3c, 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 1798 0x39, 0x38, 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 1799 0x35, 0x35, 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 1800 0x31, 0x31, 0x31, 0x30, 0x30, 0x30, 0x25, 0x25, 0x25, 0x24, 0x24, 1801 0x24, 0x23, 0x23, 0x23, 0x22, 0x18, 0x18, 0x17, 0x17, 0x17, 0x16, 1802 0x16, 0x16, 0x15, 0x15, 0x15, 0x14, 0x14, 0x14, 0x13, 0x13, 0x13, 1803 0x12, 0x08, 0x08, 0x07, 0x07, 0x07, 0x06, 0x06, 0x06, 0x05, 0x05, 1804 0x05, 0x04, 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 1805 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1806}; 1807 1808/* 1809 * DSP pre-DAC gain values from highest to lowest power (values obtained 1810 * from the reference driver.) 1811 */ 1812static const uint8_t iwn4965_dsp_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1813 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1814 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1815 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1816 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1817 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1818 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1819 0x6e, 0x68, 0x62, 0x61, 0x60, 0x5f, 0x5e, 0x5d, 0x5c, 0x5b, 0x5a, 1820 0x59, 0x58, 0x57, 0x56, 0x55, 0x54, 0x53, 0x52, 0x51, 0x50, 0x4f, 1821 0x4e, 0x4d, 0x4c, 0x4b, 0x4a, 0x49, 0x48, 0x47, 0x46, 0x45, 0x44, 1822 0x43, 0x42, 0x41, 0x40, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b 1823}; 1824 1825static const uint8_t iwn4965_dsp_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1826 0x7b, 0x75, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1827 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1828 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1829 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1830 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1831 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1832 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1833 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1834 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1835 0x68, 0x62, 0x6e, 0x68, 0x62, 0x5d, 0x58, 0x53, 0x4e 1836}; 1837 1838/* 1839 * Power saving settings (values obtained from the reference driver.) 1840 */ 1841#define IWN_NDTIMRANGES 3 1842#define IWN_NPOWERLEVELS 6 1843static const struct iwn_pmgt { 1844 uint32_t rxtimeout; 1845 uint32_t txtimeout; 1846 uint32_t intval[5]; 1847 int skip_dtim; 1848} iwn_pmgt[IWN_NDTIMRANGES][IWN_NPOWERLEVELS] = { 1849 /* DTIM <= 2 */ 1850 { 1851 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1852 { 200, 500, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 1 */ 1853 { 200, 300, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 2 */ 1854 { 50, 100, { 2, 2, 2, 2, -1 }, 0 }, /* PS level 3 */ 1855 { 50, 25, { 2, 2, 4, 4, -1 }, 1 }, /* PS level 4 */ 1856 { 25, 25, { 2, 2, 4, 6, -1 }, 2 } /* PS level 5 */ 1857 }, 1858 /* 3 <= DTIM <= 10 */ 1859 { 1860 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1861 { 200, 500, { 1, 2, 3, 4, 4 }, 0 }, /* PS level 1 */ 1862 { 200, 300, { 1, 2, 3, 4, 7 }, 0 }, /* PS level 2 */ 1863 { 50, 100, { 2, 4, 6, 7, 9 }, 0 }, /* PS level 3 */ 1864 { 50, 25, { 2, 4, 6, 9, 10 }, 1 }, /* PS level 4 */ 1865 { 25, 25, { 2, 4, 7, 10, 10 }, 2 } /* PS level 5 */ 1866 }, 1867 /* DTIM >= 11 */ 1868 { 1869 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1870 { 200, 500, { 1, 2, 3, 4, -1 }, 0 }, /* PS level 1 */ 1871 { 200, 300, { 2, 4, 6, 7, -1 }, 0 }, /* PS level 2 */ 1872 { 50, 100, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 3 */ 1873 { 50, 25, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 4 */ 1874 { 25, 25, { 4, 7, 10, 10, -1 }, 0 } /* PS level 5 */ 1875 } 1876}; 1877 1878struct iwn_sensitivity_limits { 1879 uint32_t min_ofdm_x1; 1880 uint32_t max_ofdm_x1; 1881 uint32_t min_ofdm_mrc_x1; 1882 uint32_t max_ofdm_mrc_x1; 1883 uint32_t min_ofdm_x4; 1884 uint32_t max_ofdm_x4; 1885 uint32_t min_ofdm_mrc_x4; 1886 uint32_t max_ofdm_mrc_x4; 1887 uint32_t min_cck_x4; 1888 uint32_t max_cck_x4; 1889 uint32_t min_cck_mrc_x4; 1890 uint32_t max_cck_mrc_x4; 1891 uint32_t min_energy_cck; 1892 uint32_t energy_cck; 1893 uint32_t energy_ofdm; 1894}; 1895 1896/* 1897 * RX sensitivity limits (values obtained from the reference driver.) 1898 */ 1899static const struct iwn_sensitivity_limits iwn4965_sensitivity_limits = { 1900 105, 140, 1901 220, 270, 1902 85, 120, 1903 170, 210, 1904 125, 200, 1905 200, 400, 1906 97, 1907 100, 1908 100 1909}; 1910 1911static const struct iwn_sensitivity_limits iwn5000_sensitivity_limits = { 1912 120, 120, /* min = max for performance bug in DSP. */ 1913 240, 240, /* min = max for performance bug in DSP. */ 1914 90, 120, 1915 170, 210, 1916 125, 200, 1917 170, 400, 1918 95, 1919 95, 1920 95 1921}; 1922 1923static const struct iwn_sensitivity_limits iwn5150_sensitivity_limits = { 1924 105, 105, /* min = max for performance bug in DSP. */ 1925 220, 220, /* min = max for performance bug in DSP. */ 1926 90, 120, 1927 170, 210, 1928 125, 200, 1929 170, 400, 1930 95, 1931 95, 1932 95 1933}; 1934 1935static const struct iwn_sensitivity_limits iwn1000_sensitivity_limits = { 1936 120, 155, 1937 240, 290, 1938 90, 120, 1939 170, 210, 1940 125, 200, 1941 170, 400, 1942 95, 1943 95, 1944 95 1945}; 1946 1947static const struct iwn_sensitivity_limits iwn6000_sensitivity_limits = { 1948 105, 110, 1949 192, 232, 1950 80, 145, 1951 128, 232, 1952 125, 175, 1953 160, 310, 1954 97, 1955 97, 1956 100 1957}; 1958 1959/* Get value from linux kernel 3.2.+ in Drivers/net/wireless/iwlwifi/iwl-2000.c*/ 1960static const struct iwn_sensitivity_limits iwn2030_sensitivity_limits = { 1961 105,110, 1962 128,232, 1963 80,145, 1964 128,232, 1965 125,175, 1966 160,310, 1967 97, 1968 97, 1969 110 1970}; 1971 1972/* Map TID to TX scheduler's FIFO. */ 1973static const uint8_t iwn_tid2fifo[] = { 1974 1, 0, 0, 1, 2, 2, 3, 3, 7, 7, 7, 7, 7, 7, 7, 7, 3 1975}; 1976 1977/* WiFi/WiMAX coexist event priority table for 6050. */ 1978static const struct iwn5000_wimax_event iwn6050_wimax_events[] = { 1979 { 0x04, 0x03, 0x00, 0x00 }, 1980 { 0x04, 0x03, 0x00, 0x03 }, 1981 { 0x04, 0x03, 0x00, 0x03 }, 1982 { 0x04, 0x03, 0x00, 0x03 }, 1983 { 0x04, 0x03, 0x00, 0x00 }, 1984 { 0x04, 0x03, 0x00, 0x07 }, 1985 { 0x04, 0x03, 0x00, 0x00 }, 1986 { 0x04, 0x03, 0x00, 0x03 }, 1987 { 0x04, 0x03, 0x00, 0x03 }, 1988 { 0x04, 0x03, 0x00, 0x00 }, 1989 { 0x06, 0x03, 0x00, 0x07 }, 1990 { 0x04, 0x03, 0x00, 0x00 }, 1991 { 0x06, 0x06, 0x00, 0x03 }, 1992 { 0x04, 0x03, 0x00, 0x07 }, 1993 { 0x04, 0x03, 0x00, 0x00 }, 1994 { 0x04, 0x03, 0x00, 0x00 } 1995}; 1996 1997/* Firmware errors. */ 1998static const char * const iwn_fw_errmsg[] = { 1999 "OK", 2000 "FAIL", 2001 "BAD_PARAM", 2002 "BAD_CHECKSUM", 2003 "NMI_INTERRUPT_WDG", 2004 "SYSASSERT", 2005 "FATAL_ERROR", 2006 "BAD_COMMAND", 2007 "HW_ERROR_TUNE_LOCK", 2008 "HW_ERROR_TEMPERATURE", 2009 "ILLEGAL_CHAN_FREQ", 2010 "VCC_NOT_STABLE", 2011 "FH_ERROR", 2012 "NMI_INTERRUPT_HOST", 2013 "NMI_INTERRUPT_ACTION_PT", 2014 "NMI_INTERRUPT_UNKNOWN", 2015 "UCODE_VERSION_MISMATCH", 2016 "HW_ERROR_ABS_LOCK", 2017 "HW_ERROR_CAL_LOCK_FAIL", 2018 "NMI_INTERRUPT_INST_ACTION_PT", 2019 "NMI_INTERRUPT_DATA_ACTION_PT", 2020 "NMI_TRM_HW_ER", 2021 "NMI_INTERRUPT_TRM", 2022 "NMI_INTERRUPT_BREAKPOINT", 2023 "DEBUG_0", 2024 "DEBUG_1", 2025 "DEBUG_2", 2026 "DEBUG_3", 2027 "ADVANCED_SYSASSERT" 2028}; 2029 2030/* Find least significant bit that is set. */ 2031#define IWN_LSB(x) ((((x) - 1) & (x)) ^ (x)) 2032 2033#define IWN_READ(sc, reg) \ 2034 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 2035 2036#define IWN_WRITE(sc, reg, val) \ 2037 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 2038 2039#define IWN_WRITE_1(sc, reg, val) \ 2040 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 2041 2042#define IWN_SETBITS(sc, reg, mask) \ 2043 IWN_WRITE(sc, reg, IWN_READ(sc, reg) | (mask)) 2044 2045#define IWN_CLRBITS(sc, reg, mask) \ 2046 IWN_WRITE(sc, reg, IWN_READ(sc, reg) & ~(mask)) 2047 2048#define IWN_BARRIER_WRITE(sc) \ 2049 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 2050 BUS_SPACE_BARRIER_WRITE) 2051 2052#define IWN_BARRIER_READ_WRITE(sc) \ 2053 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 2054 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 2055