if_iwnreg.h revision 220729
1178676Ssam/* $FreeBSD: head/sys/dev/iwn/if_iwnreg.h 220729 2011-04-16 14:56:13Z bschmidt $ */ 2210111Sbschmidt/* $OpenBSD: if_iwnreg.h,v 1.40 2010/05/05 19:41:57 damien Exp $ */ 3178676Ssam 4178676Ssam/*- 5198429Srpaulo * Copyright (c) 2007, 2008 6178676Ssam * Damien Bergamini <damien.bergamini@free.fr> 7178676Ssam * 8178676Ssam * Permission to use, copy, modify, and distribute this software for any 9178676Ssam * purpose with or without fee is hereby granted, provided that the above 10178676Ssam * copyright notice and this permission notice appear in all copies. 11178676Ssam * 12178676Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13178676Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14178676Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15178676Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16178676Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17178676Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18178676Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19178676Ssam */ 20178676Ssam 21178676Ssam#define IWN_TX_RING_COUNT 256 22198429Srpaulo#define IWN_TX_RING_LOMARK 192 23198429Srpaulo#define IWN_TX_RING_HIMARK 224 24198429Srpaulo#define IWN_RX_RING_COUNT_LOG 6 25198429Srpaulo#define IWN_RX_RING_COUNT (1 << IWN_RX_RING_COUNT_LOG) 26178676Ssam 27198429Srpaulo#define IWN4965_NTXQUEUES 16 28198429Srpaulo#define IWN5000_NTXQUEUES 20 29178676Ssam 30198429Srpaulo#define IWN4965_NDMACHNLS 7 31198429Srpaulo#define IWN5000_NDMACHNLS 8 32178676Ssam 33198429Srpaulo#define IWN_SRVC_DMACHNL 9 34198429Srpaulo 35201209Srpaulo#define IWN_ICT_SIZE 4096 36201209Srpaulo#define IWN_ICT_COUNT (IWN_ICT_SIZE / sizeof (uint32_t)) 37201209Srpaulo 38198429Srpaulo/* Maximum number of DMA segments for TX. */ 39178676Ssam#define IWN_MAX_SCATTER 20 40178676Ssam 41198429Srpaulo/* RX buffers must be large enough to hold a full 4K A-MPDU. */ 42178676Ssam#define IWN_RBUF_SIZE (4 * 1024) 43178676Ssam 44198429Srpaulo#if defined(__LP64__) 45198429Srpaulo/* HW supports 36-bit DMA addresses. */ 46198429Srpaulo#define IWN_LOADDR(paddr) ((uint32_t)(paddr)) 47198429Srpaulo#define IWN_HIADDR(paddr) (((paddr) >> 32) & 0xf) 48198429Srpaulo#else 49198429Srpaulo#define IWN_LOADDR(paddr) (paddr) 50198429Srpaulo#define IWN_HIADDR(paddr) (0) 51198429Srpaulo#endif 52198429Srpaulo 53178676Ssam/* 54178676Ssam * Control and status registers. 55178676Ssam */ 56198429Srpaulo#define IWN_HW_IF_CONFIG 0x000 57198429Srpaulo#define IWN_INT_COALESCING 0x004 58201209Srpaulo#define IWN_INT_PERIODIC 0x005 /* use IWN_WRITE_1 */ 59198429Srpaulo#define IWN_INT 0x008 60201209Srpaulo#define IWN_INT_MASK 0x00c 61198429Srpaulo#define IWN_FH_INT 0x010 62178676Ssam#define IWN_RESET 0x020 63198429Srpaulo#define IWN_GP_CNTRL 0x024 64198429Srpaulo#define IWN_HW_REV 0x028 65198429Srpaulo#define IWN_EEPROM 0x02c 66198429Srpaulo#define IWN_EEPROM_GP 0x030 67198429Srpaulo#define IWN_OTP_GP 0x034 68198429Srpaulo#define IWN_GIO 0x03c 69201209Srpaulo#define IWN_GP_DRIVER 0x050 70198429Srpaulo#define IWN_UCODE_GP1_CLR 0x05c 71198429Srpaulo#define IWN_LED 0x094 72201209Srpaulo#define IWN_DRAM_INT_TBL 0x0a0 73220729Sbschmidt#define IWN_SHADOW_REG_CTRL 0x0a8 74198429Srpaulo#define IWN_GIO_CHICKEN 0x100 75198429Srpaulo#define IWN_ANA_PLL 0x20c 76201209Srpaulo#define IWN_HW_REV_WA 0x22c 77198429Srpaulo#define IWN_DBG_HPET_MEM 0x240 78201209Srpaulo#define IWN_DBG_LINK_PWR_MGMT 0x250 79198429Srpaulo#define IWN_MEM_RADDR 0x40c 80178676Ssam#define IWN_MEM_WADDR 0x410 81178676Ssam#define IWN_MEM_WDATA 0x418 82198429Srpaulo#define IWN_MEM_RDATA 0x41c 83220726Sbschmidt#define IWN_PRPH_WADDR 0x444 84220726Sbschmidt#define IWN_PRPH_RADDR 0x448 85220726Sbschmidt#define IWN_PRPH_WDATA 0x44c 86220726Sbschmidt#define IWN_PRPH_RDATA 0x450 87198429Srpaulo#define IWN_HBUS_TARG_WRPTR 0x460 88178676Ssam 89198429Srpaulo/* 90198429Srpaulo * Flow-Handler registers. 91198429Srpaulo */ 92198429Srpaulo#define IWN_FH_TFBD_CTRL0(qid) (0x1900 + (qid) * 8) 93198429Srpaulo#define IWN_FH_TFBD_CTRL1(qid) (0x1904 + (qid) * 8) 94198429Srpaulo#define IWN_FH_KW_ADDR 0x197c 95198429Srpaulo#define IWN_FH_SRAM_ADDR(qid) (0x19a4 + (qid) * 4) 96198429Srpaulo#define IWN_FH_CBBC_QUEUE(qid) (0x19d0 + (qid) * 4) 97198429Srpaulo#define IWN_FH_STATUS_WPTR 0x1bc0 98198429Srpaulo#define IWN_FH_RX_BASE 0x1bc4 99198429Srpaulo#define IWN_FH_RX_WPTR 0x1bc8 100198429Srpaulo#define IWN_FH_RX_CONFIG 0x1c00 101198429Srpaulo#define IWN_FH_RX_STATUS 0x1c44 102198429Srpaulo#define IWN_FH_TX_CONFIG(qid) (0x1d00 + (qid) * 32) 103198429Srpaulo#define IWN_FH_TXBUF_STATUS(qid) (0x1d08 + (qid) * 32) 104198429Srpaulo#define IWN_FH_TX_CHICKEN 0x1e98 105198429Srpaulo#define IWN_FH_TX_STATUS 0x1eb0 106178676Ssam 107198429Srpaulo/* 108198429Srpaulo * TX scheduler registers. 109198429Srpaulo */ 110198429Srpaulo#define IWN_SCHED_BASE 0xa02c00 111198429Srpaulo#define IWN_SCHED_SRAM_ADDR (IWN_SCHED_BASE + 0x000) 112198429Srpaulo#define IWN5000_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x008) 113198429Srpaulo#define IWN4965_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x010) 114198429Srpaulo#define IWN5000_SCHED_TXFACT (IWN_SCHED_BASE + 0x010) 115198429Srpaulo#define IWN4965_SCHED_TXFACT (IWN_SCHED_BASE + 0x01c) 116198429Srpaulo#define IWN4965_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x064 + (qid) * 4) 117198429Srpaulo#define IWN5000_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x068 + (qid) * 4) 118198429Srpaulo#define IWN4965_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0d0) 119198429Srpaulo#define IWN4965_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x0e4) 120198429Srpaulo#define IWN5000_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0e8) 121198429Srpaulo#define IWN4965_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x104 + (qid) * 4) 122198429Srpaulo#define IWN5000_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x108) 123198429Srpaulo#define IWN5000_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x10c + (qid) * 4) 124198429Srpaulo#define IWN5000_SCHED_AGGR_SEL (IWN_SCHED_BASE + 0x248) 125178676Ssam 126178676Ssam/* 127198429Srpaulo * Offsets in TX scheduler's SRAM. 128198429Srpaulo */ 129198429Srpaulo#define IWN4965_SCHED_CTX_OFF 0x380 130198429Srpaulo#define IWN4965_SCHED_CTX_LEN 416 131198429Srpaulo#define IWN4965_SCHED_QUEUE_OFFSET(qid) (0x380 + (qid) * 8) 132198429Srpaulo#define IWN4965_SCHED_TRANS_TBL(qid) (0x500 + (qid) * 2) 133198429Srpaulo#define IWN5000_SCHED_CTX_OFF 0x600 134198429Srpaulo#define IWN5000_SCHED_CTX_LEN 520 135198429Srpaulo#define IWN5000_SCHED_QUEUE_OFFSET(qid) (0x600 + (qid) * 8) 136198429Srpaulo#define IWN5000_SCHED_TRANS_TBL(qid) (0x7e0 + (qid) * 2) 137198429Srpaulo 138198429Srpaulo/* 139178676Ssam * NIC internal memory offsets. 140178676Ssam */ 141201209Srpaulo#define IWN_APMG_CLK_CTRL 0x3000 142201209Srpaulo#define IWN_APMG_CLK_EN 0x3004 143198429Srpaulo#define IWN_APMG_CLK_DIS 0x3008 144198429Srpaulo#define IWN_APMG_PS 0x300c 145201209Srpaulo#define IWN_APMG_DIGITAL_SVR 0x3058 146201209Srpaulo#define IWN_APMG_ANALOG_SVR 0x306c 147198429Srpaulo#define IWN_APMG_PCI_STT 0x3010 148198429Srpaulo#define IWN_BSM_WR_CTRL 0x3400 149198429Srpaulo#define IWN_BSM_WR_MEM_SRC 0x3404 150198429Srpaulo#define IWN_BSM_WR_MEM_DST 0x3408 151198429Srpaulo#define IWN_BSM_WR_DWCOUNT 0x340c 152198429Srpaulo#define IWN_BSM_DRAM_TEXT_ADDR 0x3490 153198429Srpaulo#define IWN_BSM_DRAM_TEXT_SIZE 0x3494 154198429Srpaulo#define IWN_BSM_DRAM_DATA_ADDR 0x3498 155198429Srpaulo#define IWN_BSM_DRAM_DATA_SIZE 0x349c 156198429Srpaulo#define IWN_BSM_SRAM_BASE 0x3800 157178676Ssam 158198429Srpaulo/* Possible flags for register IWN_HW_IF_CONFIG. */ 159198429Srpaulo#define IWN_HW_IF_CONFIG_4965_R (1 << 4) 160198429Srpaulo#define IWN_HW_IF_CONFIG_MAC_SI (1 << 8) 161198429Srpaulo#define IWN_HW_IF_CONFIG_RADIO_SI (1 << 9) 162198429Srpaulo#define IWN_HW_IF_CONFIG_EEPROM_LOCKED (1 << 21) 163198429Srpaulo#define IWN_HW_IF_CONFIG_NIC_READY (1 << 22) 164198429Srpaulo#define IWN_HW_IF_CONFIG_HAP_WAKE_L1A (1 << 23) 165198429Srpaulo#define IWN_HW_IF_CONFIG_PREPARE_DONE (1 << 25) 166198429Srpaulo#define IWN_HW_IF_CONFIG_PREPARE (1 << 27) 167178676Ssam 168201209Srpaulo/* Possible values for register IWN_INT_PERIODIC. */ 169201209Srpaulo#define IWN_INT_PERIODIC_DIS 0x00 170201209Srpaulo#define IWN_INT_PERIODIC_ENA 0xff 171201209Srpaulo 172198429Srpaulo/* Possible flags for registers IWN_PRPH_RADDR/IWN_PRPH_WADDR. */ 173198429Srpaulo#define IWN_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24) 174178676Ssam 175198429Srpaulo/* Possible values for IWN_BSM_WR_MEM_DST. */ 176198429Srpaulo#define IWN_FW_TEXT_BASE 0x00000000 177198429Srpaulo#define IWN_FW_DATA_BASE 0x00800000 178178676Ssam 179198429Srpaulo/* Possible flags for register IWN_RESET. */ 180198429Srpaulo#define IWN_RESET_NEVO (1 << 0) 181198429Srpaulo#define IWN_RESET_SW (1 << 7) 182198429Srpaulo#define IWN_RESET_MASTER_DISABLED (1 << 8) 183198429Srpaulo#define IWN_RESET_STOP_MASTER (1 << 9) 184201209Srpaulo#define IWN_RESET_LINK_PWR_MGMT_DIS (1 << 31) 185178676Ssam 186198429Srpaulo/* Possible flags for register IWN_GP_CNTRL. */ 187198429Srpaulo#define IWN_GP_CNTRL_MAC_ACCESS_ENA (1 << 0) 188198429Srpaulo#define IWN_GP_CNTRL_MAC_CLOCK_READY (1 << 0) 189198429Srpaulo#define IWN_GP_CNTRL_INIT_DONE (1 << 2) 190198429Srpaulo#define IWN_GP_CNTRL_MAC_ACCESS_REQ (1 << 3) 191198429Srpaulo#define IWN_GP_CNTRL_SLEEP (1 << 4) 192198429Srpaulo#define IWN_GP_CNTRL_RFKILL (1 << 27) 193178676Ssam 194198429Srpaulo/* Possible flags for register IWN_HW_REV. */ 195198429Srpaulo#define IWN_HW_REV_TYPE_SHIFT 4 196198429Srpaulo#define IWN_HW_REV_TYPE_MASK 0x000000f0 197198429Srpaulo#define IWN_HW_REV_TYPE_4965 0 198198429Srpaulo#define IWN_HW_REV_TYPE_5300 2 199198429Srpaulo#define IWN_HW_REV_TYPE_5350 3 200198429Srpaulo#define IWN_HW_REV_TYPE_5150 4 201198429Srpaulo#define IWN_HW_REV_TYPE_5100 5 202198429Srpaulo#define IWN_HW_REV_TYPE_1000 6 203198429Srpaulo#define IWN_HW_REV_TYPE_6000 7 204198429Srpaulo#define IWN_HW_REV_TYPE_6050 8 205210109Sbschmidt#define IWN_HW_REV_TYPE_6005 11 206178676Ssam 207198429Srpaulo/* Possible flags for register IWN_GIO_CHICKEN. */ 208198429Srpaulo#define IWN_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23) 209198429Srpaulo#define IWN_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29) 210178676Ssam 211198429Srpaulo/* Possible flags for register IWN_GIO. */ 212198429Srpaulo#define IWN_GIO_L0S_ENA (1 << 1) 213178676Ssam 214201209Srpaulo/* Possible flags for register IWN_GP_DRIVER. */ 215201209Srpaulo#define IWN_GP_DRIVER_RADIO_3X3_HYB (0 << 0) 216201209Srpaulo#define IWN_GP_DRIVER_RADIO_2X2_HYB (1 << 0) 217201209Srpaulo#define IWN_GP_DRIVER_RADIO_2X2_IPA (2 << 0) 218206444Sbschmidt#define IWN_GP_DRIVER_CALIB_VER6 (1 << 2) 219220729Sbschmidt#define IWN_GP_DRIVER_6050_1X2 (1 << 3) 220201209Srpaulo 221198429Srpaulo/* Possible flags for register IWN_UCODE_GP1_CLR. */ 222198429Srpaulo#define IWN_UCODE_GP1_RFKILL (1 << 1) 223198429Srpaulo#define IWN_UCODE_GP1_CMD_BLOCKED (1 << 2) 224198429Srpaulo#define IWN_UCODE_GP1_CTEMP_STOP_RF (1 << 3) 225178676Ssam 226198429Srpaulo/* Possible flags/values for register IWN_LED. */ 227198429Srpaulo#define IWN_LED_BSM_CTRL (1 << 5) 228198429Srpaulo#define IWN_LED_OFF 0x00000038 229198429Srpaulo#define IWN_LED_ON 0x00000078 230178676Ssam 231201209Srpaulo/* Possible flags for register IWN_DRAM_INT_TBL. */ 232201209Srpaulo#define IWN_DRAM_INT_TBL_WRAP_CHECK (1 << 27) 233201209Srpaulo#define IWN_DRAM_INT_TBL_ENABLE (1 << 31) 234201209Srpaulo 235198429Srpaulo/* Possible values for register IWN_ANA_PLL. */ 236198429Srpaulo#define IWN_ANA_PLL_INIT 0x00880300 237178676Ssam 238198429Srpaulo/* Possible flags for register IWN_FH_RX_STATUS. */ 239198429Srpaulo#define IWN_FH_RX_STATUS_IDLE (1 << 24) 240178676Ssam 241198429Srpaulo/* Possible flags for register IWN_BSM_WR_CTRL. */ 242198429Srpaulo#define IWN_BSM_WR_CTRL_START_EN (1 << 30) 243198429Srpaulo#define IWN_BSM_WR_CTRL_START (1 << 31) 244178676Ssam 245198429Srpaulo/* Possible flags for register IWN_INT. */ 246198429Srpaulo#define IWN_INT_ALIVE (1 << 0) 247198429Srpaulo#define IWN_INT_WAKEUP (1 << 1) 248198429Srpaulo#define IWN_INT_SW_RX (1 << 3) 249198429Srpaulo#define IWN_INT_CT_REACHED (1 << 6) 250198429Srpaulo#define IWN_INT_RF_TOGGLED (1 << 7) 251198429Srpaulo#define IWN_INT_SW_ERR (1 << 25) 252201209Srpaulo#define IWN_INT_SCHED (1 << 26) 253198429Srpaulo#define IWN_INT_FH_TX (1 << 27) 254201209Srpaulo#define IWN_INT_RX_PERIODIC (1 << 28) 255198429Srpaulo#define IWN_INT_HW_ERR (1 << 29) 256198429Srpaulo#define IWN_INT_FH_RX (1 << 31) 257178676Ssam 258198429Srpaulo/* Shortcut. */ 259201209Srpaulo#define IWN_INT_MASK_DEF \ 260198429Srpaulo (IWN_INT_SW_ERR | IWN_INT_HW_ERR | IWN_INT_FH_TX | \ 261198429Srpaulo IWN_INT_FH_RX | IWN_INT_ALIVE | IWN_INT_WAKEUP | \ 262198429Srpaulo IWN_INT_SW_RX | IWN_INT_CT_REACHED | IWN_INT_RF_TOGGLED) 263178676Ssam 264198429Srpaulo/* Possible flags for register IWN_FH_INT. */ 265198429Srpaulo#define IWN_FH_INT_TX_CHNL(x) (1 << (x)) 266198429Srpaulo#define IWN_FH_INT_RX_CHNL(x) (1 << ((x) + 16)) 267198429Srpaulo#define IWN_FH_INT_HI_PRIOR (1 << 30) 268198429Srpaulo/* Shortcuts for the above. */ 269198429Srpaulo#define IWN_FH_INT_TX \ 270198429Srpaulo (IWN_FH_INT_TX_CHNL(0) | IWN_FH_INT_TX_CHNL(1)) 271198429Srpaulo#define IWN_FH_INT_RX \ 272198429Srpaulo (IWN_FH_INT_RX_CHNL(0) | IWN_FH_INT_RX_CHNL(1) | IWN_FH_INT_HI_PRIOR) 273178676Ssam 274198429Srpaulo/* Possible flags/values for register IWN_FH_TX_CONFIG. */ 275198429Srpaulo#define IWN_FH_TX_CONFIG_DMA_PAUSE 0 276198429Srpaulo#define IWN_FH_TX_CONFIG_DMA_ENA (1 << 31) 277198429Srpaulo#define IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD (1 << 20) 278178676Ssam 279198429Srpaulo/* Possible flags/values for register IWN_FH_TXBUF_STATUS. */ 280198429Srpaulo#define IWN_FH_TXBUF_STATUS_TBNUM(x) ((x) << 20) 281198429Srpaulo#define IWN_FH_TXBUF_STATUS_TBIDX(x) ((x) << 12) 282198429Srpaulo#define IWN_FH_TXBUF_STATUS_TFBD_VALID 3 283198429Srpaulo 284198429Srpaulo/* Possible flags for register IWN_FH_TX_CHICKEN. */ 285198429Srpaulo#define IWN_FH_TX_CHICKEN_SCHED_RETRY (1 << 1) 286198429Srpaulo 287198429Srpaulo/* Possible flags for register IWN_FH_TX_STATUS. */ 288220659Sbschmidt#define IWN_FH_TX_STATUS_IDLE(chnl) (1 << ((chnl) + 16)) 289198429Srpaulo 290198429Srpaulo/* Possible flags for register IWN_FH_RX_CONFIG. */ 291198429Srpaulo#define IWN_FH_RX_CONFIG_ENA (1 << 31) 292198429Srpaulo#define IWN_FH_RX_CONFIG_NRBD(x) ((x) << 20) 293198429Srpaulo#define IWN_FH_RX_CONFIG_RB_SIZE_8K (1 << 16) 294198429Srpaulo#define IWN_FH_RX_CONFIG_SINGLE_FRAME (1 << 15) 295198429Srpaulo#define IWN_FH_RX_CONFIG_IRQ_DST_HOST (1 << 12) 296198429Srpaulo#define IWN_FH_RX_CONFIG_RB_TIMEOUT(x) ((x) << 4) 297198429Srpaulo#define IWN_FH_RX_CONFIG_IGN_RXF_EMPTY (1 << 2) 298198429Srpaulo 299198429Srpaulo/* Possible flags for register IWN_FH_TX_CONFIG. */ 300198429Srpaulo#define IWN_FH_TX_CONFIG_DMA_ENA (1 << 31) 301198429Srpaulo#define IWN_FH_TX_CONFIG_DMA_CREDIT_ENA (1 << 3) 302198429Srpaulo 303198429Srpaulo/* Possible flags for register IWN_EEPROM. */ 304198429Srpaulo#define IWN_EEPROM_READ_VALID (1 << 0) 305198429Srpaulo#define IWN_EEPROM_CMD (1 << 1) 306198429Srpaulo 307198429Srpaulo/* Possible flags for register IWN_EEPROM_GP. */ 308198429Srpaulo#define IWN_EEPROM_GP_IF_OWNER 0x00000180 309198429Srpaulo 310198429Srpaulo/* Possible flags for register IWN_OTP_GP. */ 311198429Srpaulo#define IWN_OTP_GP_DEV_SEL_OTP (1 << 16) 312198429Srpaulo#define IWN_OTP_GP_RELATIVE_ACCESS (1 << 17) 313198429Srpaulo#define IWN_OTP_GP_ECC_CORR_STTS (1 << 20) 314198429Srpaulo#define IWN_OTP_GP_ECC_UNCORR_STTS (1 << 21) 315198429Srpaulo 316198429Srpaulo/* Possible flags for register IWN_SCHED_QUEUE_STATUS. */ 317198429Srpaulo#define IWN4965_TXQ_STATUS_ACTIVE 0x0007fc01 318198429Srpaulo#define IWN4965_TXQ_STATUS_INACTIVE 0x0007fc00 319198429Srpaulo#define IWN4965_TXQ_STATUS_AGGR_ENA (1 << 5 | 1 << 8) 320198429Srpaulo#define IWN4965_TXQ_STATUS_CHGACT (1 << 10) 321198429Srpaulo#define IWN5000_TXQ_STATUS_ACTIVE 0x00ff0018 322198429Srpaulo#define IWN5000_TXQ_STATUS_INACTIVE 0x00ff0010 323198429Srpaulo#define IWN5000_TXQ_STATUS_CHGACT (1 << 19) 324198429Srpaulo 325201209Srpaulo/* Possible flags for registers IWN_APMG_CLK_*. */ 326198429Srpaulo#define IWN_APMG_CLK_CTRL_DMA_CLK_RQT (1 << 9) 327198429Srpaulo#define IWN_APMG_CLK_CTRL_BSM_CLK_RQT (1 << 11) 328198429Srpaulo 329198429Srpaulo/* Possible flags for register IWN_APMG_PS. */ 330198429Srpaulo#define IWN_APMG_PS_EARLY_PWROFF_DIS (1 << 22) 331198429Srpaulo#define IWN_APMG_PS_PWR_SRC(x) ((x) << 24) 332198429Srpaulo#define IWN_APMG_PS_PWR_SRC_VMAIN 0 333198429Srpaulo#define IWN_APMG_PS_PWR_SRC_VAUX 2 334198429Srpaulo#define IWN_APMG_PS_PWR_SRC_MASK IWN_APMG_PS_PWR_SRC(3) 335198429Srpaulo#define IWN_APMG_PS_RESET_REQ (1 << 26) 336198429Srpaulo 337201209Srpaulo/* Possible flags for register IWN_APMG_DIGITAL_SVR. */ 338201209Srpaulo#define IWN_APMG_DIGITAL_SVR_VOLTAGE(x) (((x) & 0xf) << 5) 339201209Srpaulo#define IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK \ 340201209Srpaulo IWN_APMG_DIGITAL_SVR_VOLTAGE(0xf) 341201209Srpaulo#define IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32 \ 342201209Srpaulo IWN_APMG_DIGITAL_SVR_VOLTAGE(3) 343201209Srpaulo 344198429Srpaulo/* Possible flags for IWN_APMG_PCI_STT. */ 345198429Srpaulo#define IWN_APMG_PCI_STT_L1A_DIS (1 << 11) 346198429Srpaulo 347198429Srpaulo/* Possible flags for register IWN_BSM_DRAM_TEXT_SIZE. */ 348178676Ssam#define IWN_FW_UPDATED (1 << 31) 349178676Ssam 350198429Srpaulo#define IWN_SCHED_WINSZ 64 351198429Srpaulo#define IWN_SCHED_LIMIT 64 352198429Srpaulo#define IWN4965_SCHED_COUNT 512 353198429Srpaulo#define IWN5000_SCHED_COUNT (IWN_TX_RING_COUNT + IWN_SCHED_WINSZ) 354198429Srpaulo#define IWN4965_SCHEDSZ (IWN4965_NTXQUEUES * IWN4965_SCHED_COUNT * 2) 355198429Srpaulo#define IWN5000_SCHEDSZ (IWN5000_NTXQUEUES * IWN5000_SCHED_COUNT * 2) 356178676Ssam 357198429Srpaulostruct iwn_tx_desc { 358198429Srpaulo uint8_t reserved1[3]; 359198429Srpaulo uint8_t nsegs; 360198429Srpaulo struct { 361198429Srpaulo uint32_t addr; 362198429Srpaulo uint16_t len; 363198429Srpaulo } __packed segs[IWN_MAX_SCATTER]; 364198429Srpaulo /* Pad to 128 bytes. */ 365198429Srpaulo uint32_t reserved2; 366198429Srpaulo} __packed; 367178676Ssam 368198429Srpaulostruct iwn_rx_status { 369178676Ssam uint16_t closed_count; 370178676Ssam uint16_t closed_rx_count; 371178676Ssam uint16_t finished_count; 372178676Ssam uint16_t finished_rx_count; 373178676Ssam uint32_t reserved[2]; 374178676Ssam} __packed; 375178676Ssam 376178676Ssamstruct iwn_rx_desc { 377178676Ssam uint32_t len; 378178676Ssam uint8_t type; 379198429Srpaulo#define IWN_UC_READY 1 380198429Srpaulo#define IWN_ADD_NODE_DONE 24 381198429Srpaulo#define IWN_TX_DONE 28 382198429Srpaulo#define IWN5000_CALIBRATION_RESULT 102 383198429Srpaulo#define IWN5000_CALIBRATION_DONE 103 384198429Srpaulo#define IWN_START_SCAN 130 385198429Srpaulo#define IWN_STOP_SCAN 132 386198429Srpaulo#define IWN_RX_STATISTICS 156 387198429Srpaulo#define IWN_BEACON_STATISTICS 157 388198429Srpaulo#define IWN_STATE_CHANGED 161 389198429Srpaulo#define IWN_BEACON_MISSED 162 390198429Srpaulo#define IWN_RX_PHY 192 391198429Srpaulo#define IWN_MPDU_RX_DONE 193 392198429Srpaulo#define IWN_RX_DONE 195 393201209Srpaulo#define IWN_RX_COMPRESSED_BA 197 394178676Ssam 395178676Ssam uint8_t flags; 396178676Ssam uint8_t idx; 397178676Ssam uint8_t qid; 398178676Ssam} __packed; 399178676Ssam 400198429Srpaulo/* Possible RX status flags. */ 401198429Srpaulo#define IWN_RX_NO_CRC_ERR (1 << 0) 402198429Srpaulo#define IWN_RX_NO_OVFL_ERR (1 << 1) 403198429Srpaulo/* Shortcut for the above. */ 404178676Ssam#define IWN_RX_NOERROR (IWN_RX_NO_CRC_ERR | IWN_RX_NO_OVFL_ERR) 405198429Srpaulo#define IWN_RX_MPDU_MIC_OK (1 << 6) 406198429Srpaulo#define IWN_RX_CIPHER_MASK (7 << 8) 407198429Srpaulo#define IWN_RX_CIPHER_CCMP (2 << 8) 408198429Srpaulo#define IWN_RX_MPDU_DEC (1 << 11) 409198429Srpaulo#define IWN_RX_DECRYPT_MASK (3 << 11) 410198429Srpaulo#define IWN_RX_DECRYPT_OK (3 << 11) 411178676Ssam 412178676Ssamstruct iwn_tx_cmd { 413178676Ssam uint8_t code; 414201209Srpaulo#define IWN_CMD_RXON 16 415201209Srpaulo#define IWN_CMD_RXON_ASSOC 17 416198429Srpaulo#define IWN_CMD_EDCA_PARAMS 19 417198429Srpaulo#define IWN_CMD_TIMING 20 418198429Srpaulo#define IWN_CMD_ADD_NODE 24 419198429Srpaulo#define IWN_CMD_TX_DATA 28 420198429Srpaulo#define IWN_CMD_LINK_QUALITY 78 421198429Srpaulo#define IWN_CMD_SET_LED 72 422198429Srpaulo#define IWN5000_CMD_WIMAX_COEX 90 423198429Srpaulo#define IWN5000_CMD_CALIB_CONFIG 101 424202986Srpaulo#define IWN5000_CMD_CALIB_RESULT 102 425202986Srpaulo#define IWN5000_CMD_CALIB_COMPLETE 103 426198429Srpaulo#define IWN_CMD_SET_POWER_MODE 119 427198429Srpaulo#define IWN_CMD_SCAN 128 428202986Srpaulo#define IWN_CMD_SCAN_RESULTS 131 429201209Srpaulo#define IWN_CMD_TXPOWER_DBM 149 430198429Srpaulo#define IWN_CMD_TXPOWER 151 431201209Srpaulo#define IWN5000_CMD_TX_ANT_CONFIG 152 432198429Srpaulo#define IWN_CMD_BT_COEX 155 433198429Srpaulo#define IWN_CMD_GET_STATISTICS 156 434198429Srpaulo#define IWN_CMD_SET_CRITICAL_TEMP 164 435198429Srpaulo#define IWN_CMD_SET_SENSITIVITY 168 436198429Srpaulo#define IWN_CMD_PHY_CALIB 176 437198429Srpaulo 438178676Ssam uint8_t flags; 439178676Ssam uint8_t idx; 440178676Ssam uint8_t qid; 441178676Ssam uint8_t data[136]; 442178676Ssam} __packed; 443178676Ssam 444198429Srpaulo/* Antenna flags, used in various commands. */ 445198429Srpaulo#define IWN_ANT_A (1 << 0) 446198429Srpaulo#define IWN_ANT_B (1 << 1) 447198429Srpaulo#define IWN_ANT_C (1 << 2) 448201209Srpaulo/* Shortcuts. */ 449201209Srpaulo#define IWN_ANT_AB (IWN_ANT_A | IWN_ANT_B) 450201209Srpaulo#define IWN_ANT_BC (IWN_ANT_B | IWN_ANT_C) 451198429Srpaulo#define IWN_ANT_ABC (IWN_ANT_A | IWN_ANT_B | IWN_ANT_C) 452198429Srpaulo 453201209Srpaulo/* Structure for command IWN_CMD_RXON. */ 454198429Srpaulostruct iwn_rxon { 455178676Ssam uint8_t myaddr[IEEE80211_ADDR_LEN]; 456178676Ssam uint16_t reserved1; 457178676Ssam uint8_t bssid[IEEE80211_ADDR_LEN]; 458178676Ssam uint16_t reserved2; 459178676Ssam uint8_t wlap[IEEE80211_ADDR_LEN]; 460178676Ssam uint16_t reserved3; 461178676Ssam uint8_t mode; 462178676Ssam#define IWN_MODE_HOSTAP 1 463178676Ssam#define IWN_MODE_STA 3 464178676Ssam#define IWN_MODE_IBSS 4 465178676Ssam#define IWN_MODE_MONITOR 6 466198429Srpaulo 467198429Srpaulo uint8_t air; 468178676Ssam uint16_t rxchain; 469201209Srpaulo#define IWN_RXCHAIN_DRIVER_FORCE (1 << 0) 470201209Srpaulo#define IWN_RXCHAIN_VALID(x) (((x) & IWN_ANT_ABC) << 1) 471201209Srpaulo#define IWN_RXCHAIN_FORCE_SEL(x) (((x) & IWN_ANT_ABC) << 4) 472201209Srpaulo#define IWN_RXCHAIN_FORCE_MIMO_SEL(x) (((x) & IWN_ANT_ABC) << 7) 473198429Srpaulo#define IWN_RXCHAIN_IDLE_COUNT(x) ((x) << 10) 474198429Srpaulo#define IWN_RXCHAIN_MIMO_COUNT(x) ((x) << 12) 475198429Srpaulo#define IWN_RXCHAIN_MIMO_FORCE (1 << 14) 476198429Srpaulo 477198429Srpaulo uint8_t ofdm_mask; 478198429Srpaulo uint8_t cck_mask; 479178676Ssam uint16_t associd; 480178676Ssam uint32_t flags; 481201209Srpaulo#define IWN_RXON_24GHZ (1 << 0) 482201209Srpaulo#define IWN_RXON_CCK (1 << 1) 483201209Srpaulo#define IWN_RXON_AUTO (1 << 2) 484201209Srpaulo#define IWN_RXON_SHSLOT (1 << 4) 485201209Srpaulo#define IWN_RXON_SHPREAMBLE (1 << 5) 486201209Srpaulo#define IWN_RXON_NODIVERSITY (1 << 7) 487201209Srpaulo#define IWN_RXON_ANTENNA_A (1 << 8) 488201209Srpaulo#define IWN_RXON_ANTENNA_B (1 << 9) 489201209Srpaulo#define IWN_RXON_TSF (1 << 15) 490201209Srpaulo#define IWN_RXON_CTS_TO_SELF (1 << 30) 491198429Srpaulo 492178676Ssam uint32_t filter; 493198429Srpaulo#define IWN_FILTER_PROMISC (1 << 0) 494198429Srpaulo#define IWN_FILTER_CTL (1 << 1) 495198429Srpaulo#define IWN_FILTER_MULTICAST (1 << 2) 496198429Srpaulo#define IWN_FILTER_NODECRYPT (1 << 3) 497198429Srpaulo#define IWN_FILTER_BSS (1 << 5) 498198429Srpaulo#define IWN_FILTER_BEACON (1 << 6) 499198429Srpaulo 500198429Srpaulo uint8_t chan; 501198429Srpaulo uint8_t reserved4; 502198429Srpaulo uint8_t ht_single_mask; 503198429Srpaulo uint8_t ht_dual_mask; 504201209Srpaulo /* The following fields are for >=5000 Series only. */ 505198429Srpaulo uint8_t ht_triple_mask; 506198429Srpaulo uint8_t reserved5; 507198429Srpaulo uint16_t acquisition; 508198429Srpaulo uint16_t reserved6; 509178676Ssam} __packed; 510178676Ssam 511198429Srpaulo#define IWN4965_RXONSZ (sizeof (struct iwn_rxon) - 6) 512198429Srpaulo#define IWN5000_RXONSZ (sizeof (struct iwn_rxon)) 513198429Srpaulo 514198429Srpaulo/* Structure for command IWN_CMD_ASSOCIATE. */ 515178676Ssamstruct iwn_assoc { 516178676Ssam uint32_t flags; 517178676Ssam uint32_t filter; 518178676Ssam uint8_t ofdm_mask; 519178676Ssam uint8_t cck_mask; 520178676Ssam uint16_t reserved; 521178676Ssam} __packed; 522178676Ssam 523198429Srpaulo/* Structure for command IWN_CMD_EDCA_PARAMS. */ 524178676Ssamstruct iwn_edca_params { 525178676Ssam uint32_t flags; 526178676Ssam#define IWN_EDCA_UPDATE (1 << 0) 527178676Ssam#define IWN_EDCA_TXOP (1 << 4) 528178676Ssam 529178676Ssam struct { 530178676Ssam uint16_t cwmin; 531178676Ssam uint16_t cwmax; 532178676Ssam uint8_t aifsn; 533178676Ssam uint8_t reserved; 534178676Ssam uint16_t txoplimit; 535201209Srpaulo } __packed ac[WME_NUM_AC]; 536178676Ssam} __packed; 537178676Ssam 538198429Srpaulo/* Structure for command IWN_CMD_TIMING. */ 539198429Srpaulostruct iwn_cmd_timing { 540178676Ssam uint64_t tstamp; 541178676Ssam uint16_t bintval; 542178676Ssam uint16_t atim; 543178676Ssam uint32_t binitval; 544178676Ssam uint16_t lintval; 545178676Ssam uint16_t reserved; 546178676Ssam} __packed; 547178676Ssam 548198429Srpaulo/* Structure for command IWN_CMD_ADD_NODE. */ 549178676Ssamstruct iwn_node_info { 550178676Ssam uint8_t control; 551178676Ssam#define IWN_NODE_UPDATE (1 << 0) 552198429Srpaulo 553178676Ssam uint8_t reserved1[3]; 554198429Srpaulo 555178676Ssam uint8_t macaddr[IEEE80211_ADDR_LEN]; 556178676Ssam uint16_t reserved2; 557178676Ssam uint8_t id; 558178676Ssam#define IWN_ID_BSS 0 559198429Srpaulo#define IWN5000_ID_BROADCAST 15 560198429Srpaulo#define IWN4965_ID_BROADCAST 31 561198429Srpaulo 562178676Ssam uint8_t flags; 563198429Srpaulo#define IWN_FLAG_SET_KEY (1 << 0) 564198429Srpaulo#define IWN_FLAG_SET_DISABLE_TID (1 << 1) 565198429Srpaulo#define IWN_FLAG_SET_TXRATE (1 << 2) 566198429Srpaulo#define IWN_FLAG_SET_ADDBA (1 << 3) 567198429Srpaulo#define IWN_FLAG_SET_DELBA (1 << 4) 568198429Srpaulo 569178676Ssam uint16_t reserved3; 570198429Srpaulo uint16_t kflags; 571198429Srpaulo#define IWN_KFLAG_CCMP (1 << 1) 572198429Srpaulo#define IWN_KFLAG_MAP (1 << 3) 573198429Srpaulo#define IWN_KFLAG_KID(kid) ((kid) << 8) 574198429Srpaulo#define IWN_KFLAG_INVALID (1 << 11) 575198429Srpaulo#define IWN_KFLAG_GROUP (1 << 14) 576198429Srpaulo 577178676Ssam uint8_t tsc2; /* TKIP TSC2 */ 578178676Ssam uint8_t reserved4; 579178676Ssam uint16_t ttak[5]; 580198429Srpaulo uint8_t kid; 581198429Srpaulo uint8_t reserved5; 582198429Srpaulo uint8_t key[16]; 583198429Srpaulo /* The following 3 fields are for 5000 Series only. */ 584198429Srpaulo uint64_t tsc; 585198429Srpaulo uint8_t rxmic[8]; 586198429Srpaulo uint8_t txmic[8]; 587198429Srpaulo 588178676Ssam uint32_t htflags; 589198429Srpaulo#define IWN_AMDPU_SIZE_FACTOR(x) ((x) << 19) 590198429Srpaulo#define IWN_AMDPU_DENSITY(x) ((x) << 23) 591198429Srpaulo 592178676Ssam uint32_t mask; 593198429Srpaulo uint16_t disable_tid; 594198429Srpaulo uint16_t reserved6; 595198429Srpaulo uint8_t addba_tid; 596198429Srpaulo uint8_t delba_tid; 597198429Srpaulo uint16_t addba_ssn; 598198429Srpaulo uint32_t reserved7; 599198429Srpaulo} __packed; 600198429Srpaulo 601198429Srpaulostruct iwn4965_node_info { 602198429Srpaulo uint8_t control; 603198429Srpaulo uint8_t reserved1[3]; 604198429Srpaulo uint8_t macaddr[IEEE80211_ADDR_LEN]; 605198429Srpaulo uint16_t reserved2; 606198429Srpaulo uint8_t id; 607198429Srpaulo uint8_t flags; 608198429Srpaulo uint16_t reserved3; 609198429Srpaulo uint16_t kflags; 610198429Srpaulo uint8_t tsc2; /* TKIP TSC2 */ 611198429Srpaulo uint8_t reserved4; 612198429Srpaulo uint16_t ttak[5]; 613198429Srpaulo uint8_t kid; 614198429Srpaulo uint8_t reserved5; 615198429Srpaulo uint8_t key[16]; 616198429Srpaulo uint32_t htflags; 617198429Srpaulo uint32_t mask; 618198429Srpaulo uint16_t disable_tid; 619198429Srpaulo uint16_t reserved6; 620198429Srpaulo uint8_t addba_tid; 621198429Srpaulo uint8_t delba_tid; 622198429Srpaulo uint16_t addba_ssn; 623198429Srpaulo uint32_t reserved7; 624198429Srpaulo} __packed; 625198429Srpaulo 626201209Srpaulo#define IWN_RFLAG_CCK (1 << 1) 627198429Srpaulo#define IWN_RFLAG_ANT(x) ((x) << 6) 628178676Ssam 629198429Srpaulo/* Structure for command IWN_CMD_TX_DATA. */ 630178676Ssamstruct iwn_cmd_data { 631178676Ssam uint16_t len; 632178676Ssam uint16_t lnext; 633178676Ssam uint32_t flags; 634198429Srpaulo#define IWN_TX_NEED_PROTECTION (1 << 0) /* 5000 only */ 635178676Ssam#define IWN_TX_NEED_RTS (1 << 1) 636178676Ssam#define IWN_TX_NEED_CTS (1 << 2) 637178676Ssam#define IWN_TX_NEED_ACK (1 << 3) 638198429Srpaulo#define IWN_TX_LINKQ (1 << 4) 639198429Srpaulo#define IWN_TX_IMM_BA (1 << 6) 640178676Ssam#define IWN_TX_FULL_TXOP (1 << 7) 641178676Ssam#define IWN_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */ 642178676Ssam#define IWN_TX_AUTO_SEQ (1 << 13) 643198429Srpaulo#define IWN_TX_MORE_FRAG (1 << 14) 644178676Ssam#define IWN_TX_INSERT_TSTAMP (1 << 16) 645178676Ssam#define IWN_TX_NEED_PADDING (1 << 20) 646178676Ssam 647198429Srpaulo uint32_t scratch; 648198429Srpaulo uint8_t plcp; 649178676Ssam uint8_t rflags; 650178676Ssam uint16_t xrflags; 651198429Srpaulo 652178676Ssam uint8_t id; 653178676Ssam uint8_t security; 654178676Ssam#define IWN_CIPHER_WEP40 1 655178676Ssam#define IWN_CIPHER_CCMP 2 656178676Ssam#define IWN_CIPHER_TKIP 3 657178676Ssam#define IWN_CIPHER_WEP104 9 658178676Ssam 659198429Srpaulo uint8_t linkq; 660178676Ssam uint8_t reserved2; 661198429Srpaulo uint8_t key[16]; 662178676Ssam uint16_t fnext; 663178676Ssam uint16_t reserved3; 664178676Ssam uint32_t lifetime; 665178676Ssam#define IWN_LIFETIME_INFINITE 0xffffffff 666178676Ssam 667178676Ssam uint32_t loaddr; 668178676Ssam uint8_t hiaddr; 669178676Ssam uint8_t rts_ntries; 670178676Ssam uint8_t data_ntries; 671178676Ssam uint8_t tid; 672178676Ssam uint16_t timeout; 673178676Ssam uint16_t txop; 674178676Ssam} __packed; 675178676Ssam 676198429Srpaulo/* Structure for command IWN_CMD_LINK_QUALITY. */ 677178676Ssam#define IWN_MAX_TX_RETRIES 16 678178676Ssamstruct iwn_cmd_link_quality { 679178676Ssam uint8_t id; 680178676Ssam uint8_t reserved1; 681178676Ssam uint16_t ctl; 682178676Ssam uint8_t flags; 683198429Srpaulo uint8_t mimo; 684198429Srpaulo uint8_t antmsk_1stream; 685198429Srpaulo uint8_t antmsk_2stream; 686201209Srpaulo uint8_t ridx[WME_NUM_AC]; 687198429Srpaulo uint16_t ampdu_limit; 688198429Srpaulo uint8_t ampdu_threshold; 689198429Srpaulo uint8_t ampdu_max; 690178676Ssam uint32_t reserved2; 691178676Ssam struct { 692198429Srpaulo uint8_t plcp; 693178676Ssam uint8_t rflags; 694178676Ssam uint16_t xrflags; 695198429Srpaulo } __packed retry[IWN_MAX_TX_RETRIES]; 696178676Ssam uint32_t reserved3; 697178676Ssam} __packed; 698178676Ssam 699198429Srpaulo/* Structure for command IWN_CMD_SET_LED. */ 700178676Ssamstruct iwn_cmd_led { 701178676Ssam uint32_t unit; /* multiplier (in usecs) */ 702178676Ssam uint8_t which; 703178676Ssam#define IWN_LED_ACTIVITY 1 704178676Ssam#define IWN_LED_LINK 2 705178676Ssam 706178676Ssam uint8_t off; 707178676Ssam uint8_t on; 708178676Ssam uint8_t reserved; 709178676Ssam} __packed; 710178676Ssam 711198429Srpaulo/* Structure for command IWN5000_CMD_WIMAX_COEX. */ 712198429Srpaulostruct iwn5000_wimax_coex { 713198429Srpaulo uint32_t flags; 714201209Srpaulo#define IWN_WIMAX_COEX_STA_TABLE_VALID (1 << 0) 715201209Srpaulo#define IWN_WIMAX_COEX_UNASSOC_WA_UNMASK (1 << 2) 716201209Srpaulo#define IWN_WIMAX_COEX_ASSOC_WA_UNMASK (1 << 3) 717201209Srpaulo#define IWN_WIMAX_COEX_ENABLE (1 << 7) 718201209Srpaulo 719201209Srpaulo struct iwn5000_wimax_event { 720198429Srpaulo uint8_t request; 721198429Srpaulo uint8_t window; 722198429Srpaulo uint8_t reserved; 723198429Srpaulo uint8_t flags; 724198429Srpaulo } __packed events[16]; 725198429Srpaulo} __packed; 726198429Srpaulo 727198429Srpaulo/* Structures for command IWN5000_CMD_CALIB_CONFIG. */ 728198429Srpaulostruct iwn5000_calib_elem { 729198429Srpaulo uint32_t enable; 730198429Srpaulo uint32_t start; 731198429Srpaulo uint32_t send; 732198429Srpaulo uint32_t apply; 733198429Srpaulo uint32_t reserved; 734198429Srpaulo} __packed; 735198429Srpaulo 736198429Srpaulostruct iwn5000_calib_status { 737198429Srpaulo struct iwn5000_calib_elem once; 738198429Srpaulo struct iwn5000_calib_elem perd; 739198429Srpaulo uint32_t flags; 740198429Srpaulo} __packed; 741198429Srpaulo 742198429Srpaulostruct iwn5000_calib_config { 743198429Srpaulo struct iwn5000_calib_status ucode; 744198429Srpaulo struct iwn5000_calib_status driver; 745198429Srpaulo uint32_t reserved; 746198429Srpaulo} __packed; 747198429Srpaulo 748198429Srpaulo/* Structure for command IWN_CMD_SET_POWER_MODE. */ 749198429Srpaulostruct iwn_pmgt_cmd { 750178676Ssam uint16_t flags; 751198429Srpaulo#define IWN_PS_ALLOW_SLEEP (1 << 0) 752198429Srpaulo#define IWN_PS_NOTIFY (1 << 1) 753198429Srpaulo#define IWN_PS_SLEEP_OVER_DTIM (1 << 2) 754198429Srpaulo#define IWN_PS_PCI_PMGT (1 << 3) 755198429Srpaulo#define IWN_PS_FAST_PD (1 << 4) 756178676Ssam 757198429Srpaulo uint8_t keepalive; 758178676Ssam uint8_t debug; 759198429Srpaulo uint32_t rxtimeout; 760198429Srpaulo uint32_t txtimeout; 761198429Srpaulo uint32_t intval[5]; 762178676Ssam uint32_t beacons; 763178676Ssam} __packed; 764178676Ssam 765198429Srpaulo/* Structures for command IWN_CMD_SCAN. */ 766178676Ssamstruct iwn_scan_essid { 767178676Ssam uint8_t id; 768178676Ssam uint8_t len; 769178676Ssam uint8_t data[IEEE80211_NWID_LEN]; 770178676Ssam} __packed; 771178676Ssam 772178676Ssamstruct iwn_scan_hdr { 773178676Ssam uint16_t len; 774178676Ssam uint8_t reserved1; 775178676Ssam uint8_t nchan; 776198429Srpaulo uint16_t quiet_time; 777198429Srpaulo uint16_t quiet_threshold; 778178676Ssam uint16_t crc_threshold; 779178676Ssam uint16_t rxchain; 780178676Ssam uint32_t max_svc; /* background scans */ 781178676Ssam uint32_t pause_svc; /* background scans */ 782178676Ssam uint32_t flags; 783178676Ssam uint32_t filter; 784178676Ssam 785198429Srpaulo /* Followed by a struct iwn_cmd_data. */ 786198429Srpaulo /* Followed by an array of 20 structs iwn_scan_essid. */ 787198429Srpaulo /* Followed by probe request body. */ 788198429Srpaulo /* Followed by an array of ``nchan'' structs iwn_scan_chan. */ 789178676Ssam} __packed; 790178676Ssam 791178676Ssamstruct iwn_scan_chan { 792198429Srpaulo uint32_t flags; 793198429Srpaulo#define IWN_CHAN_ACTIVE (1 << 0) 794198429Srpaulo#define IWN_CHAN_NPBREQS(x) (((1 << (x)) - 1) << 1) 795178676Ssam 796198429Srpaulo uint16_t chan; 797178676Ssam uint8_t rf_gain; 798178676Ssam uint8_t dsp_gain; 799178676Ssam uint16_t active; /* msecs */ 800178676Ssam uint16_t passive; /* msecs */ 801178676Ssam} __packed; 802178676Ssam 803198429Srpaulo/* Maximum size of a scan command. */ 804198429Srpaulo#define IWN_SCAN_MAXSZ (MCLBYTES - 4) 805198429Srpaulo 806198429Srpaulo/* Structure for command IWN_CMD_TXPOWER (4965AGN only.) */ 807178676Ssam#define IWN_RIDX_MAX 32 808198429Srpaulostruct iwn4965_cmd_txpower { 809198429Srpaulo uint8_t band; 810198429Srpaulo uint8_t reserved1; 811198429Srpaulo uint8_t chan; 812198429Srpaulo uint8_t reserved2; 813178676Ssam struct { 814198429Srpaulo uint8_t rf_gain[2]; 815198429Srpaulo uint8_t dsp_gain[2]; 816198429Srpaulo } __packed power[IWN_RIDX_MAX + 1]; 817178676Ssam} __packed; 818178676Ssam 819198429Srpaulo/* Structure for command IWN_CMD_TXPOWER_DBM (5000 Series only.) */ 820198429Srpaulostruct iwn5000_cmd_txpower { 821198429Srpaulo int8_t global_limit; /* in half-dBm */ 822198429Srpaulo#define IWN5000_TXPOWER_AUTO 0x7f 823198429Srpaulo#define IWN5000_TXPOWER_MAX_DBM 16 824198429Srpaulo 825198429Srpaulo uint8_t flags; 826198429Srpaulo#define IWN5000_TXPOWER_NO_CLOSED (1 << 6) 827198429Srpaulo 828198429Srpaulo int8_t srv_limit; /* in half-dBm */ 829198429Srpaulo uint8_t reserved; 830198429Srpaulo} __packed; 831198429Srpaulo 832198429Srpaulo/* Structure for command IWN_CMD_BLUETOOTH. */ 833178676Ssamstruct iwn_bluetooth { 834178676Ssam uint8_t flags; 835206444Sbschmidt#define IWN_BT_COEX_CHAN_ANN (1 << 0) 836206444Sbschmidt#define IWN_BT_COEX_BT_PRIO (1 << 1) 837206444Sbschmidt#define IWN_BT_COEX_2_WIRE (1 << 2) 838201209Srpaulo 839201209Srpaulo uint8_t lead_time; 840201209Srpaulo#define IWN_BT_LEAD_TIME_DEF 30 841201209Srpaulo 842201209Srpaulo uint8_t max_kill; 843201209Srpaulo#define IWN_BT_MAX_KILL_DEF 5 844201209Srpaulo 845178676Ssam uint8_t reserved; 846201209Srpaulo uint32_t kill_ack; 847201209Srpaulo uint32_t kill_cts; 848178676Ssam} __packed; 849178676Ssam 850198429Srpaulo/* Structure for command IWN_CMD_SET_CRITICAL_TEMP. */ 851178676Ssamstruct iwn_critical_temp { 852178676Ssam uint32_t reserved; 853178676Ssam uint32_t tempM; 854178676Ssam uint32_t tempR; 855198429Srpaulo/* degK <-> degC conversion macros. */ 856178676Ssam#define IWN_CTOK(c) ((c) + 273) 857178676Ssam#define IWN_KTOC(k) ((k) - 273) 858178676Ssam#define IWN_CTOMUK(c) (((c) * 1000000) + 273150000) 859178676Ssam} __packed; 860178676Ssam 861220729Sbschmidt/* Structures for command IWN_CMD_SET_SENSITIVITY. */ 862178676Ssamstruct iwn_sensitivity_cmd { 863178676Ssam uint16_t which; 864178676Ssam#define IWN_SENSITIVITY_DEFAULTTBL 0 865178676Ssam#define IWN_SENSITIVITY_WORKTBL 1 866178676Ssam 867178676Ssam uint16_t energy_cck; 868178676Ssam uint16_t energy_ofdm; 869178676Ssam uint16_t corr_ofdm_x1; 870178676Ssam uint16_t corr_ofdm_mrc_x1; 871178676Ssam uint16_t corr_cck_mrc_x4; 872178676Ssam uint16_t corr_ofdm_x4; 873178676Ssam uint16_t corr_ofdm_mrc_x4; 874178676Ssam uint16_t corr_barker; 875178676Ssam uint16_t corr_barker_mrc; 876178676Ssam uint16_t corr_cck_x4; 877178676Ssam uint16_t energy_ofdm_th; 878178676Ssam} __packed; 879178676Ssam 880220729Sbschmidtstruct iwn_enhanced_sensitivity_cmd { 881220729Sbschmidt uint16_t which; 882220729Sbschmidt uint16_t energy_cck; 883220729Sbschmidt uint16_t energy_ofdm; 884220729Sbschmidt uint16_t corr_ofdm_x1; 885220729Sbschmidt uint16_t corr_ofdm_mrc_x1; 886220729Sbschmidt uint16_t corr_cck_mrc_x4; 887220729Sbschmidt uint16_t corr_ofdm_x4; 888220729Sbschmidt uint16_t corr_ofdm_mrc_x4; 889220729Sbschmidt uint16_t corr_barker; 890220729Sbschmidt uint16_t corr_barker_mrc; 891220729Sbschmidt uint16_t corr_cck_x4; 892220729Sbschmidt uint16_t energy_ofdm_th; 893220729Sbschmidt /* "Enhanced" part. */ 894220729Sbschmidt uint16_t ina_det_ofdm; 895220729Sbschmidt uint16_t ina_det_cck; 896220729Sbschmidt uint16_t corr_11_9_en; 897220729Sbschmidt uint16_t ofdm_det_slope_mrc; 898220729Sbschmidt uint16_t ofdm_det_icept_mrc; 899220729Sbschmidt uint16_t ofdm_det_slope; 900220729Sbschmidt uint16_t ofdm_det_icept; 901220729Sbschmidt uint16_t cck_det_slope_mrc; 902220729Sbschmidt uint16_t cck_det_icept_mrc; 903220729Sbschmidt uint16_t cck_det_slope; 904220729Sbschmidt uint16_t cck_det_icept; 905220729Sbschmidt uint16_t reserved; 906220729Sbschmidt} __packed; 907220729Sbschmidt 908198429Srpaulo/* Structures for command IWN_CMD_PHY_CALIB. */ 909198429Srpaulostruct iwn_phy_calib { 910198429Srpaulo uint8_t code; 911198429Srpaulo#define IWN4965_PHY_CALIB_DIFF_GAIN 7 912198429Srpaulo#define IWN5000_PHY_CALIB_DC 8 913198429Srpaulo#define IWN5000_PHY_CALIB_LO 9 914198429Srpaulo#define IWN5000_PHY_CALIB_TX_IQ 11 915198429Srpaulo#define IWN5000_PHY_CALIB_CRYSTAL 15 916198429Srpaulo#define IWN5000_PHY_CALIB_BASE_BAND 16 917201209Srpaulo#define IWN5000_PHY_CALIB_TX_IQ_PERIODIC 17 918220676Sbschmidt#define IWN5000_PHY_CALIB_TEMP_OFFSET 18 919220676Sbschmidt 920198429Srpaulo#define IWN5000_PHY_CALIB_RESET_NOISE_GAIN 18 921198429Srpaulo#define IWN5000_PHY_CALIB_NOISE_GAIN 19 922178676Ssam 923198429Srpaulo uint8_t group; 924198429Srpaulo uint8_t ngroups; 925198429Srpaulo uint8_t isvalid; 926198429Srpaulo} __packed; 927178676Ssam 928198429Srpaulostruct iwn5000_phy_calib_crystal { 929198429Srpaulo uint8_t code; 930198429Srpaulo uint8_t group; 931198429Srpaulo uint8_t ngroups; 932198429Srpaulo uint8_t isvalid; 933198429Srpaulo 934198429Srpaulo uint8_t cap_pin[2]; 935198429Srpaulo uint8_t reserved[2]; 936178676Ssam} __packed; 937178676Ssam 938220676Sbschmidtstruct iwn5000_phy_calib_temp_offset { 939220676Sbschmidt uint8_t code; 940220676Sbschmidt uint8_t group; 941220676Sbschmidt uint8_t ngroups; 942220676Sbschmidt uint8_t isvalid; 943220676Sbschmidt int16_t offset; 944220676Sbschmidt#define IWN_DEFAULT_TEMP_OFFSET 2700 945220676Sbschmidt 946220676Sbschmidt uint16_t reserved; 947220676Sbschmidt} __packed; 948220676Sbschmidt 949198429Srpaulostruct iwn_phy_calib_gain { 950198429Srpaulo uint8_t code; 951198429Srpaulo uint8_t group; 952198429Srpaulo uint8_t ngroups; 953198429Srpaulo uint8_t isvalid; 954178676Ssam 955198429Srpaulo int8_t gain[3]; 956198429Srpaulo uint8_t reserved; 957198429Srpaulo} __packed; 958198429Srpaulo 959198429Srpaulo/* Structure for command IWN_CMD_SPECTRUM_MEASUREMENT. */ 960198429Srpaulostruct iwn_spectrum_cmd { 961198429Srpaulo uint16_t len; 962198429Srpaulo uint8_t token; 963198429Srpaulo uint8_t id; 964198429Srpaulo uint8_t origin; 965198429Srpaulo uint8_t periodic; 966198429Srpaulo uint16_t timeout; 967198429Srpaulo uint32_t start; 968198429Srpaulo uint32_t reserved1; 969198429Srpaulo uint32_t flags; 970198429Srpaulo uint32_t filter; 971198429Srpaulo uint16_t nchan; 972198429Srpaulo uint16_t reserved2; 973198429Srpaulo struct { 974198429Srpaulo uint32_t duration; 975198429Srpaulo uint8_t chan; 976198429Srpaulo uint8_t type; 977198429Srpaulo#define IWN_MEASUREMENT_BASIC (1 << 0) 978198429Srpaulo#define IWN_MEASUREMENT_CCA (1 << 1) 979198429Srpaulo#define IWN_MEASUREMENT_RPI_HISTOGRAM (1 << 2) 980198429Srpaulo#define IWN_MEASUREMENT_NOISE_HISTOGRAM (1 << 3) 981198429Srpaulo#define IWN_MEASUREMENT_FRAME (1 << 4) 982198429Srpaulo#define IWN_MEASUREMENT_IDLE (1 << 7) 983198429Srpaulo 984198429Srpaulo uint16_t reserved; 985198429Srpaulo } __packed chan[10]; 986198429Srpaulo} __packed; 987198429Srpaulo 988198429Srpaulo/* Structure for IWN_UC_READY notification. */ 989178676Ssam#define IWN_NATTEN_GROUPS 5 990178676Ssamstruct iwn_ucode_info { 991178676Ssam uint8_t minor; 992178676Ssam uint8_t major; 993178676Ssam uint16_t reserved1; 994178676Ssam uint8_t revision[8]; 995178676Ssam uint8_t type; 996178676Ssam uint8_t subtype; 997178676Ssam#define IWN_UCODE_RUNTIME 0 998178676Ssam#define IWN_UCODE_INIT 9 999178676Ssam 1000178676Ssam uint16_t reserved2; 1001178676Ssam uint32_t logptr; 1002198429Srpaulo uint32_t errptr; 1003178676Ssam uint32_t tstamp; 1004178676Ssam uint32_t valid; 1005178676Ssam 1006198429Srpaulo /* The following fields are for UCODE_INIT only. */ 1007178676Ssam int32_t volt; 1008178676Ssam struct { 1009178676Ssam int32_t chan20MHz; 1010178676Ssam int32_t chan40MHz; 1011178676Ssam } __packed temp[4]; 1012198429Srpaulo int32_t atten[IWN_NATTEN_GROUPS][2]; 1013178676Ssam} __packed; 1014178676Ssam 1015198429Srpaulo/* Structures for IWN_TX_DONE notification. */ 1016198429Srpaulo#define IWN_TX_SUCCESS 0x00 1017198429Srpaulo#define IWN_TX_FAIL 0x80 /* all failures have 0x80 set */ 1018198429Srpaulo#define IWN_TX_FAIL_SHORT_LIMIT 0x82 /* too many RTS retries */ 1019198429Srpaulo#define IWN_TX_FAIL_LONG_LIMIT 0x83 /* too many retries */ 1020198429Srpaulo#define IWN_TX_FAIL_FIFO_UNDERRRUN 0x84 /* tx fifo not kept running */ 1021198429Srpaulo#define IWN_TX_FAIL_DEST_IN_PS 0x88 /* sta found in power save */ 1022198429Srpaulo#define IWN_TX_FAIL_TX_LOCKED 0x90 /* waiting to see traffic */ 1023198429Srpaulo 1024198429Srpaulostruct iwn4965_tx_stat { 1025178676Ssam uint8_t nframes; 1026201209Srpaulo uint8_t btkillcnt; 1027201209Srpaulo uint8_t rtsfailcnt; 1028201209Srpaulo uint8_t ackfailcnt; 1029178676Ssam uint8_t rate; 1030178676Ssam uint8_t rflags; 1031178676Ssam uint16_t xrflags; 1032178676Ssam uint16_t duration; 1033178676Ssam uint16_t reserved; 1034178676Ssam uint32_t power[2]; 1035178676Ssam uint32_t status; 1036178676Ssam} __packed; 1037178676Ssam 1038198429Srpaulostruct iwn5000_tx_stat { 1039198429Srpaulo uint8_t nframes; 1040201209Srpaulo uint8_t btkillcnt; 1041201209Srpaulo uint8_t rtsfailcnt; 1042201209Srpaulo uint8_t ackfailcnt; 1043198429Srpaulo uint8_t rate; 1044198429Srpaulo uint8_t rflags; 1045198429Srpaulo uint16_t xrflags; 1046198429Srpaulo uint16_t duration; 1047198429Srpaulo uint16_t reserved; 1048198429Srpaulo uint32_t power[2]; 1049198429Srpaulo uint32_t info; 1050198429Srpaulo uint16_t seq; 1051198429Srpaulo uint16_t len; 1052201209Srpaulo uint8_t tlc; 1053201209Srpaulo uint8_t ratid; 1054201209Srpaulo uint8_t fc[2]; 1055198429Srpaulo uint16_t status; 1056198429Srpaulo uint16_t sequence; 1057198429Srpaulo} __packed; 1058198429Srpaulo 1059198429Srpaulo/* Structure for IWN_BEACON_MISSED notification. */ 1060178676Ssamstruct iwn_beacon_missed { 1061178676Ssam uint32_t consecutive; 1062178676Ssam uint32_t total; 1063178676Ssam uint32_t expected; 1064178676Ssam uint32_t received; 1065178676Ssam} __packed; 1066178676Ssam 1067198429Srpaulo/* Structure for IWN_MPDU_RX_DONE notification. */ 1068198429Srpaulostruct iwn_rx_mpdu { 1069178676Ssam uint16_t len; 1070178676Ssam uint16_t reserved; 1071178676Ssam} __packed; 1072178676Ssam 1073198429Srpaulo/* Structures for IWN_RX_DONE and IWN_MPDU_RX_DONE notifications. */ 1074198429Srpaulostruct iwn4965_rx_phystat { 1075198429Srpaulo uint16_t antenna; 1076198429Srpaulo uint16_t agc; 1077198429Srpaulo uint8_t rssi[6]; 1078198429Srpaulo} __packed; 1079198429Srpaulo 1080198429Srpaulostruct iwn5000_rx_phystat { 1081198429Srpaulo uint32_t reserved1; 1082198429Srpaulo uint32_t agc; 1083198429Srpaulo uint16_t rssi[3]; 1084198429Srpaulo} __packed; 1085198429Srpaulo 1086178676Ssamstruct iwn_rx_stat { 1087178676Ssam uint8_t phy_len; 1088178676Ssam uint8_t cfg_phy_len; 1089178676Ssam#define IWN_STAT_MAXLEN 20 1090178676Ssam 1091178676Ssam uint8_t id; 1092178676Ssam uint8_t reserved1; 1093178676Ssam uint64_t tstamp; 1094178676Ssam uint32_t beacon; 1095178676Ssam uint16_t flags; 1096198429Srpaulo#define IWN_STAT_FLAG_SHPREAMBLE (1 << 2) 1097198429Srpaulo 1098178676Ssam uint16_t chan; 1099198429Srpaulo uint8_t phybuf[32]; 1100178676Ssam uint8_t rate; 1101178676Ssam uint8_t rflags; 1102178676Ssam uint16_t xrflags; 1103178676Ssam uint16_t len; 1104178676Ssam uint16_t reserve3; 1105178676Ssam} __packed; 1106178676Ssam 1107198429Srpaulo#define IWN_RSSI_TO_DBM 44 1108198429Srpaulo 1109201209Srpaulo/* Structure for IWN_RX_COMPRESSED_BA notification. */ 1110201209Srpaulostruct iwn_compressed_ba { 1111201209Srpaulo uint8_t macaddr[IEEE80211_ADDR_LEN]; 1112201209Srpaulo uint16_t reserved; 1113201209Srpaulo uint8_t id; 1114201209Srpaulo uint8_t tid; 1115201209Srpaulo uint16_t seq; 1116201209Srpaulo uint64_t bitmap; 1117201209Srpaulo uint16_t qid; 1118201209Srpaulo uint16_t ssn; 1119201209Srpaulo} __packed; 1120201209Srpaulo 1121198429Srpaulo/* Structure for IWN_START_SCAN notification. */ 1122178676Ssamstruct iwn_start_scan { 1123178676Ssam uint64_t tstamp; 1124178676Ssam uint32_t tbeacon; 1125178676Ssam uint8_t chan; 1126178676Ssam uint8_t band; 1127178676Ssam uint16_t reserved; 1128178676Ssam uint32_t status; 1129178676Ssam} __packed; 1130178676Ssam 1131198429Srpaulo/* Structure for IWN_STOP_SCAN notification. */ 1132178676Ssamstruct iwn_stop_scan { 1133178676Ssam uint8_t nchan; 1134178676Ssam uint8_t status; 1135178676Ssam uint8_t reserved; 1136178676Ssam uint8_t chan; 1137178676Ssam uint64_t tsf; 1138178676Ssam} __packed; 1139178676Ssam 1140198429Srpaulo/* Structure for IWN_SPECTRUM_MEASUREMENT notification. */ 1141198429Srpaulostruct iwn_spectrum_notif { 1142198429Srpaulo uint8_t id; 1143198429Srpaulo uint8_t token; 1144198429Srpaulo uint8_t idx; 1145198429Srpaulo uint8_t state; 1146198429Srpaulo#define IWN_MEASUREMENT_START 0 1147198429Srpaulo#define IWN_MEASUREMENT_STOP 1 1148198429Srpaulo 1149198429Srpaulo uint32_t start; 1150198429Srpaulo uint8_t band; 1151198429Srpaulo uint8_t chan; 1152198429Srpaulo uint8_t type; 1153198429Srpaulo uint8_t reserved1; 1154198429Srpaulo uint32_t cca_ofdm; 1155198429Srpaulo uint32_t cca_cck; 1156198429Srpaulo uint32_t cca_time; 1157198429Srpaulo uint8_t basic; 1158198429Srpaulo uint8_t reserved2[3]; 1159198429Srpaulo uint32_t ofdm[8]; 1160198429Srpaulo uint32_t cck[8]; 1161198429Srpaulo uint32_t stop; 1162198429Srpaulo uint32_t status; 1163198429Srpaulo#define IWN_MEASUREMENT_OK 0 1164198429Srpaulo#define IWN_MEASUREMENT_CONCURRENT 1 1165198429Srpaulo#define IWN_MEASUREMENT_CSA_CONFLICT 2 1166198429Srpaulo#define IWN_MEASUREMENT_TGH_CONFLICT 3 1167198429Srpaulo#define IWN_MEASUREMENT_STOPPED 6 1168198429Srpaulo#define IWN_MEASUREMENT_TIMEOUT 7 1169198429Srpaulo#define IWN_MEASUREMENT_FAILED 8 1170198429Srpaulo} __packed; 1171198429Srpaulo 1172201209Srpaulo/* Structures for IWN_{RX,BEACON}_STATISTICS notification. */ 1173178676Ssamstruct iwn_rx_phy_stats { 1174178676Ssam uint32_t ina; 1175178676Ssam uint32_t fina; 1176178676Ssam uint32_t bad_plcp; 1177178676Ssam uint32_t bad_crc32; 1178178676Ssam uint32_t overrun; 1179178676Ssam uint32_t eoverrun; 1180178676Ssam uint32_t good_crc32; 1181178676Ssam uint32_t fa; 1182178676Ssam uint32_t bad_fina_sync; 1183178676Ssam uint32_t sfd_timeout; 1184178676Ssam uint32_t fina_timeout; 1185178676Ssam uint32_t no_rts_ack; 1186178676Ssam uint32_t rxe_limit; 1187178676Ssam uint32_t ack; 1188178676Ssam uint32_t cts; 1189178676Ssam uint32_t ba_resp; 1190178676Ssam uint32_t dsp_kill; 1191178676Ssam uint32_t bad_mh; 1192178676Ssam uint32_t rssi_sum; 1193178676Ssam uint32_t reserved; 1194178676Ssam} __packed; 1195178676Ssam 1196178676Ssamstruct iwn_rx_general_stats { 1197178676Ssam uint32_t bad_cts; 1198178676Ssam uint32_t bad_ack; 1199178676Ssam uint32_t not_bss; 1200178676Ssam uint32_t filtered; 1201178676Ssam uint32_t bad_chan; 1202178676Ssam uint32_t beacons; 1203178676Ssam uint32_t missed_beacons; 1204178676Ssam uint32_t adc_saturated; /* time in 0.8us */ 1205178676Ssam uint32_t ina_searched; /* time in 0.8us */ 1206178676Ssam uint32_t noise[3]; 1207178676Ssam uint32_t flags; 1208178676Ssam uint32_t load; 1209178676Ssam uint32_t fa; 1210178676Ssam uint32_t rssi[3]; 1211178676Ssam uint32_t energy[3]; 1212178676Ssam} __packed; 1213178676Ssam 1214178676Ssamstruct iwn_rx_ht_phy_stats { 1215178676Ssam uint32_t bad_plcp; 1216178676Ssam uint32_t overrun; 1217178676Ssam uint32_t eoverrun; 1218178676Ssam uint32_t good_crc32; 1219178676Ssam uint32_t bad_crc32; 1220178676Ssam uint32_t bad_mh; 1221178676Ssam uint32_t good_ampdu_crc32; 1222178676Ssam uint32_t ampdu; 1223178676Ssam uint32_t fragment; 1224178676Ssam uint32_t reserved; 1225178676Ssam} __packed; 1226178676Ssam 1227178676Ssamstruct iwn_rx_stats { 1228178676Ssam struct iwn_rx_phy_stats ofdm; 1229178676Ssam struct iwn_rx_phy_stats cck; 1230178676Ssam struct iwn_rx_general_stats general; 1231178676Ssam struct iwn_rx_ht_phy_stats ht; 1232178676Ssam} __packed; 1233178676Ssam 1234178676Ssamstruct iwn_tx_stats { 1235178676Ssam uint32_t preamble; 1236178676Ssam uint32_t rx_detected; 1237178676Ssam uint32_t bt_defer; 1238178676Ssam uint32_t bt_kill; 1239178676Ssam uint32_t short_len; 1240178676Ssam uint32_t cts_timeout; 1241178676Ssam uint32_t ack_timeout; 1242178676Ssam uint32_t exp_ack; 1243178676Ssam uint32_t ack; 1244178676Ssam uint32_t msdu; 1245178676Ssam uint32_t busrt_err1; 1246178676Ssam uint32_t burst_err2; 1247178676Ssam uint32_t cts_collision; 1248178676Ssam uint32_t ack_collision; 1249178676Ssam uint32_t ba_timeout; 1250178676Ssam uint32_t ba_resched; 1251178676Ssam uint32_t query_ampdu; 1252178676Ssam uint32_t query; 1253178676Ssam uint32_t query_ampdu_frag; 1254178676Ssam uint32_t query_mismatch; 1255178676Ssam uint32_t not_ready; 1256178676Ssam uint32_t underrun; 1257178676Ssam uint32_t bt_ht_kill; 1258178676Ssam uint32_t rx_ba_resp; 1259178676Ssam uint32_t reserved[2]; 1260178676Ssam} __packed; 1261178676Ssam 1262178676Ssamstruct iwn_general_stats { 1263178676Ssam uint32_t temp; 1264178676Ssam uint32_t temp_m; 1265178676Ssam uint32_t burst_check; 1266178676Ssam uint32_t burst; 1267178676Ssam uint32_t reserved1[4]; 1268178676Ssam uint32_t sleep; 1269178676Ssam uint32_t slot_out; 1270178676Ssam uint32_t slot_idle; 1271178676Ssam uint32_t ttl_tstamp; 1272178676Ssam uint32_t tx_ant_a; 1273178676Ssam uint32_t tx_ant_b; 1274178676Ssam uint32_t exec; 1275178676Ssam uint32_t probe; 1276178676Ssam uint32_t reserved2[2]; 1277178676Ssam uint32_t rx_enabled; 1278178676Ssam uint32_t reserved3[3]; 1279178676Ssam} __packed; 1280178676Ssam 1281178676Ssamstruct iwn_stats { 1282178676Ssam uint32_t flags; 1283178676Ssam struct iwn_rx_stats rx; 1284178676Ssam struct iwn_tx_stats tx; 1285178676Ssam struct iwn_general_stats general; 1286178676Ssam} __packed; 1287178676Ssam 1288178676Ssam 1289198429Srpaulo/* Firmware error dump. */ 1290198429Srpaulostruct iwn_fw_dump { 1291198429Srpaulo uint32_t valid; 1292198429Srpaulo uint32_t id; 1293198429Srpaulo uint32_t pc; 1294198429Srpaulo uint32_t branch_link[2]; 1295198429Srpaulo uint32_t interrupt_link[2]; 1296198429Srpaulo uint32_t error_data[2]; 1297198429Srpaulo uint32_t src_line; 1298198429Srpaulo uint32_t tsf; 1299198429Srpaulo uint32_t time[2]; 1300198429Srpaulo} __packed; 1301198429Srpaulo 1302210111Sbschmidt/* TLV firmware header. */ 1303210111Sbschmidtstruct iwn_fw_tlv_hdr { 1304210111Sbschmidt uint32_t zero; /* Always 0, to differentiate from legacy. */ 1305210111Sbschmidt uint32_t signature; 1306210111Sbschmidt#define IWN_FW_SIGNATURE 0x0a4c5749 /* "IWL\n" */ 1307210111Sbschmidt 1308210111Sbschmidt uint8_t descr[64]; 1309210111Sbschmidt uint32_t rev; 1310210111Sbschmidt#define IWN_FW_API(x) (((x) >> 8) & 0xff) 1311210111Sbschmidt 1312210111Sbschmidt uint32_t build; 1313210111Sbschmidt uint64_t altmask; 1314210111Sbschmidt} __packed; 1315210111Sbschmidt 1316210111Sbschmidt/* TLV header. */ 1317210111Sbschmidtstruct iwn_fw_tlv { 1318210111Sbschmidt uint16_t type; 1319210111Sbschmidt#define IWN_FW_TLV_MAIN_TEXT 1 1320210111Sbschmidt#define IWN_FW_TLV_MAIN_DATA 2 1321210111Sbschmidt#define IWN_FW_TLV_INIT_TEXT 3 1322210111Sbschmidt#define IWN_FW_TLV_INIT_DATA 4 1323210111Sbschmidt#define IWN_FW_TLV_BOOT_TEXT 5 1324210111Sbschmidt#define IWN_FW_TLV_PBREQ_MAXLEN 6 1325210111Sbschmidt 1326210111Sbschmidt uint16_t alt; 1327210111Sbschmidt uint32_t len; 1328210111Sbschmidt} __packed; 1329210111Sbschmidt 1330198429Srpaulo#define IWN4965_FW_TEXT_MAXSZ ( 96 * 1024) 1331198429Srpaulo#define IWN4965_FW_DATA_MAXSZ ( 40 * 1024) 1332198429Srpaulo#define IWN5000_FW_TEXT_MAXSZ (256 * 1024) 1333198429Srpaulo#define IWN5000_FW_DATA_MAXSZ ( 80 * 1024) 1334178676Ssam#define IWN_FW_BOOT_TEXT_MAXSZ 1024 1335198429Srpaulo#define IWN4965_FWSZ (IWN4965_FW_TEXT_MAXSZ + IWN4965_FW_DATA_MAXSZ) 1336198429Srpaulo#define IWN5000_FWSZ IWN5000_FW_TEXT_MAXSZ 1337178676Ssam 1338178676Ssam/* 1339178676Ssam * Offsets into EEPROM. 1340178676Ssam */ 1341178676Ssam#define IWN_EEPROM_MAC 0x015 1342220729Sbschmidt#define IWN_EEPROM_SKU_CAP 0x045 1343198429Srpaulo#define IWN_EEPROM_RFCFG 0x048 1344198429Srpaulo#define IWN4965_EEPROM_DOMAIN 0x060 1345198429Srpaulo#define IWN4965_EEPROM_BAND1 0x063 1346198429Srpaulo#define IWN5000_EEPROM_REG 0x066 1347198429Srpaulo#define IWN5000_EEPROM_CAL 0x067 1348198429Srpaulo#define IWN4965_EEPROM_BAND2 0x072 1349198429Srpaulo#define IWN4965_EEPROM_BAND3 0x080 1350198429Srpaulo#define IWN4965_EEPROM_BAND4 0x08d 1351198429Srpaulo#define IWN4965_EEPROM_BAND5 0x099 1352198429Srpaulo#define IWN4965_EEPROM_BAND6 0x0a0 1353198429Srpaulo#define IWN4965_EEPROM_BAND7 0x0a8 1354198429Srpaulo#define IWN4965_EEPROM_MAXPOW 0x0e8 1355198429Srpaulo#define IWN4965_EEPROM_VOLTAGE 0x0e9 1356198429Srpaulo#define IWN4965_EEPROM_BANDS 0x0ea 1357198429Srpaulo/* Indirect offsets. */ 1358198429Srpaulo#define IWN5000_EEPROM_DOMAIN 0x001 1359198429Srpaulo#define IWN5000_EEPROM_BAND1 0x004 1360198429Srpaulo#define IWN5000_EEPROM_BAND2 0x013 1361198429Srpaulo#define IWN5000_EEPROM_BAND3 0x021 1362198429Srpaulo#define IWN5000_EEPROM_BAND4 0x02e 1363198429Srpaulo#define IWN5000_EEPROM_BAND5 0x03a 1364198429Srpaulo#define IWN5000_EEPROM_BAND6 0x041 1365198429Srpaulo#define IWN5000_EEPROM_BAND7 0x049 1366201209Srpaulo#define IWN6000_EEPROM_ENHINFO 0x054 1367198429Srpaulo#define IWN5000_EEPROM_CRYSTAL 0x128 1368198429Srpaulo#define IWN5000_EEPROM_TEMP 0x12a 1369198429Srpaulo#define IWN5000_EEPROM_VOLT 0x12b 1370178676Ssam 1371220729Sbschmidt/* Possible flags for IWN_EEPROM_SKU_CAP. */ 1372220729Sbschmidt#define IWN_EEPROM_SKU_CAP_11N (1 << 6) 1373220729Sbschmidt#define IWN_EEPROM_SKU_CAP_AMT (1 << 7) 1374220729Sbschmidt#define IWN_EEPROM_SKU_CAP_IPAN (1 << 8) 1375220729Sbschmidt 1376198429Srpaulo/* Possible flags for IWN_EEPROM_RFCFG. */ 1377198429Srpaulo#define IWN_RFCFG_TYPE(x) (((x) >> 0) & 0x3) 1378198429Srpaulo#define IWN_RFCFG_STEP(x) (((x) >> 2) & 0x3) 1379198429Srpaulo#define IWN_RFCFG_DASH(x) (((x) >> 4) & 0x3) 1380198429Srpaulo#define IWN_RFCFG_TXANTMSK(x) (((x) >> 8) & 0xf) 1381198429Srpaulo#define IWN_RFCFG_RXANTMSK(x) (((x) >> 12) & 0xf) 1382198429Srpaulo 1383178676Ssamstruct iwn_eeprom_chan { 1384178676Ssam uint8_t flags; 1385178676Ssam#define IWN_EEPROM_CHAN_VALID (1 << 0) 1386198429Srpaulo#define IWN_EEPROM_CHAN_IBSS (1 << 1) 1387198429Srpaulo#define IWN_EEPROM_CHAN_ACTIVE (1 << 3) 1388198429Srpaulo#define IWN_EEPROM_CHAN_RADAR (1 << 4) 1389178676Ssam 1390178676Ssam int8_t maxpwr; 1391178676Ssam} __packed; 1392178676Ssam 1393201209Srpaulostruct iwn_eeprom_enhinfo { 1394201209Srpaulo uint16_t chan; 1395201209Srpaulo int8_t chain[3]; /* max power in half-dBm */ 1396201209Srpaulo uint8_t reserved; 1397201209Srpaulo int8_t mimo2; /* max power in half-dBm */ 1398201209Srpaulo int8_t mimo3; /* max power in half-dBm */ 1399201209Srpaulo} __packed; 1400201209Srpaulo 1401206444Sbschmidtstruct iwn5000_eeprom_calib_hdr { 1402206444Sbschmidt uint8_t version; 1403206444Sbschmidt uint8_t pa_type; 1404206444Sbschmidt uint16_t volt; 1405206444Sbschmidt} __packed; 1406206444Sbschmidt 1407178676Ssam#define IWN_NSAMPLES 3 1408198429Srpaulostruct iwn4965_eeprom_chan_samples { 1409178676Ssam uint8_t num; 1410178676Ssam struct { 1411178676Ssam uint8_t temp; 1412178676Ssam uint8_t gain; 1413178676Ssam uint8_t power; 1414178676Ssam int8_t pa_det; 1415198429Srpaulo } samples[2][IWN_NSAMPLES]; 1416178676Ssam} __packed; 1417178676Ssam 1418178676Ssam#define IWN_NBANDS 8 1419198429Srpaulostruct iwn4965_eeprom_band { 1420178676Ssam uint8_t lo; /* low channel number */ 1421178676Ssam uint8_t hi; /* high channel number */ 1422198429Srpaulo struct iwn4965_eeprom_chan_samples chans[2]; 1423178676Ssam} __packed; 1424178676Ssam 1425198429Srpaulo/* 1426198429Srpaulo * Offsets of channels descriptions in EEPROM. 1427198429Srpaulo */ 1428198429Srpaulostatic const uint32_t iwn4965_regulatory_bands[IWN_NBANDS] = { 1429198429Srpaulo IWN4965_EEPROM_BAND1, 1430198429Srpaulo IWN4965_EEPROM_BAND2, 1431198429Srpaulo IWN4965_EEPROM_BAND3, 1432198429Srpaulo IWN4965_EEPROM_BAND4, 1433198429Srpaulo IWN4965_EEPROM_BAND5, 1434198429Srpaulo IWN4965_EEPROM_BAND6, 1435198429Srpaulo IWN4965_EEPROM_BAND7 1436198429Srpaulo}; 1437178676Ssam 1438198429Srpaulostatic const uint32_t iwn5000_regulatory_bands[IWN_NBANDS] = { 1439198429Srpaulo IWN5000_EEPROM_BAND1, 1440198429Srpaulo IWN5000_EEPROM_BAND2, 1441198429Srpaulo IWN5000_EEPROM_BAND3, 1442198429Srpaulo IWN5000_EEPROM_BAND4, 1443198429Srpaulo IWN5000_EEPROM_BAND5, 1444198429Srpaulo IWN5000_EEPROM_BAND6, 1445198429Srpaulo IWN5000_EEPROM_BAND7 1446198429Srpaulo}; 1447198429Srpaulo 1448198429Srpaulo#define IWN_CHAN_BANDS_COUNT 7 1449198429Srpaulo#define IWN_MAX_CHAN_PER_BAND 14 1450198429Srpaulostatic const struct iwn_chan_band { 1451198429Srpaulo uint8_t nchan; 1452198429Srpaulo uint8_t chan[IWN_MAX_CHAN_PER_BAND]; 1453198429Srpaulo} iwn_bands[] = { 1454198429Srpaulo /* 20MHz channels, 2GHz band. */ 1455198429Srpaulo { 14, { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } }, 1456198429Srpaulo /* 20MHz channels, 5GHz band. */ 1457198429Srpaulo { 13, { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } }, 1458198429Srpaulo { 12, { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } }, 1459198429Srpaulo { 11, { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } }, 1460198429Srpaulo { 6, { 145, 149, 153, 157, 161, 165 } }, 1461198429Srpaulo /* 40MHz channels (primary channels), 2GHz band. */ 1462198429Srpaulo { 7, { 1, 2, 3, 4, 5, 6, 7 } }, 1463198429Srpaulo /* 40MHz channels (primary channels), 5GHz band. */ 1464198429Srpaulo { 11, { 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157 } } 1465198429Srpaulo}; 1466198429Srpaulo 1467220726Sbschmidt#define IWN1000_OTP_NBLOCKS 3 1468220726Sbschmidt#define IWN6000_OTP_NBLOCKS 4 1469201209Srpaulo#define IWN6050_OTP_NBLOCKS 7 1470198429Srpaulo 1471198429Srpaulo/* HW rate indices. */ 1472220715Sbschmidt#define IWN_RIDX_CCK1 0 1473220715Sbschmidt#define IWN_RIDX_OFDM6 4 1474198429Srpaulo 1475198429Srpaulostatic const struct iwn_rate { 1476198429Srpaulo uint8_t rate; 1477198429Srpaulo uint8_t plcp; 1478198429Srpaulo uint8_t flags; 1479198429Srpaulo} iwn_rates[IWN_RIDX_MAX + 1] = { 1480198429Srpaulo { 2, 10, IWN_RFLAG_CCK }, 1481198429Srpaulo { 4, 20, IWN_RFLAG_CCK }, 1482198429Srpaulo { 11, 55, IWN_RFLAG_CCK }, 1483198429Srpaulo { 22, 110, IWN_RFLAG_CCK }, 1484198429Srpaulo { 12, 0xd, 0 }, 1485198429Srpaulo { 18, 0xf, 0 }, 1486198429Srpaulo { 24, 0x5, 0 }, 1487198429Srpaulo { 36, 0x7, 0 }, 1488198429Srpaulo { 48, 0x9, 0 }, 1489198429Srpaulo { 72, 0xb, 0 }, 1490198429Srpaulo { 96, 0x1, 0 }, 1491198429Srpaulo { 108, 0x3, 0 }, 1492198429Srpaulo { 120, 0x3, 0 } 1493198429Srpaulo}; 1494198429Srpaulo 1495198429Srpaulo#define IWN4965_MAX_PWR_INDEX 107 1496198429Srpaulo 1497178676Ssam/* 1498178676Ssam * RF Tx gain values from highest to lowest power (values obtained from 1499178676Ssam * the reference driver.) 1500178676Ssam */ 1501198429Srpaulostatic const uint8_t iwn4965_rf_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1502178676Ssam 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, 1503178676Ssam 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 0x39, 0x38, 1504178676Ssam 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 0x35, 0x35, 1505178676Ssam 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x31, 0x31, 1506178676Ssam 0x31, 0x30, 0x30, 0x30, 0x06, 0x06, 0x06, 0x05, 0x05, 0x05, 0x04, 1507178676Ssam 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01, 1508178676Ssam 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1509178676Ssam 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1510178676Ssam 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1511178676Ssam 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1512178676Ssam}; 1513178676Ssam 1514198429Srpaulostatic const uint8_t iwn4965_rf_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1515178676Ssam 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 1516178676Ssam 0x3c, 0x3c, 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 1517178676Ssam 0x39, 0x38, 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 1518178676Ssam 0x35, 0x35, 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 1519178676Ssam 0x31, 0x31, 0x31, 0x30, 0x30, 0x30, 0x25, 0x25, 0x25, 0x24, 0x24, 1520178676Ssam 0x24, 0x23, 0x23, 0x23, 0x22, 0x18, 0x18, 0x17, 0x17, 0x17, 0x16, 1521178676Ssam 0x16, 0x16, 0x15, 0x15, 0x15, 0x14, 0x14, 0x14, 0x13, 0x13, 0x13, 1522178676Ssam 0x12, 0x08, 0x08, 0x07, 0x07, 0x07, 0x06, 0x06, 0x06, 0x05, 0x05, 1523178676Ssam 0x05, 0x04, 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 1524178676Ssam 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1525178676Ssam}; 1526178676Ssam 1527178676Ssam/* 1528178676Ssam * DSP pre-DAC gain values from highest to lowest power (values obtained 1529178676Ssam * from the reference driver.) 1530178676Ssam */ 1531198429Srpaulostatic const uint8_t iwn4965_dsp_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1532178676Ssam 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1533178676Ssam 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1534178676Ssam 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1535178676Ssam 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1536178676Ssam 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1537178676Ssam 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1538178676Ssam 0x6e, 0x68, 0x62, 0x61, 0x60, 0x5f, 0x5e, 0x5d, 0x5c, 0x5b, 0x5a, 1539178676Ssam 0x59, 0x58, 0x57, 0x56, 0x55, 0x54, 0x53, 0x52, 0x51, 0x50, 0x4f, 1540178676Ssam 0x4e, 0x4d, 0x4c, 0x4b, 0x4a, 0x49, 0x48, 0x47, 0x46, 0x45, 0x44, 1541178676Ssam 0x43, 0x42, 0x41, 0x40, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b 1542178676Ssam}; 1543178676Ssam 1544198429Srpaulostatic const uint8_t iwn4965_dsp_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1545178676Ssam 0x7b, 0x75, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1546178676Ssam 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1547178676Ssam 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1548178676Ssam 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1549178676Ssam 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1550178676Ssam 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1551178676Ssam 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1552178676Ssam 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1553178676Ssam 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1554178676Ssam 0x68, 0x62, 0x6e, 0x68, 0x62, 0x5d, 0x58, 0x53, 0x4e 1555178676Ssam}; 1556178676Ssam 1557198429Srpaulo/* 1558198429Srpaulo * Power saving settings (values obtained from the reference driver.) 1559198429Srpaulo */ 1560198429Srpaulo#define IWN_NDTIMRANGES 3 1561198429Srpaulo#define IWN_NPOWERLEVELS 6 1562198429Srpaulostatic const struct iwn_pmgt { 1563198429Srpaulo uint32_t rxtimeout; 1564198429Srpaulo uint32_t txtimeout; 1565198429Srpaulo uint32_t intval[5]; 1566198429Srpaulo int skip_dtim; 1567198429Srpaulo} iwn_pmgt[IWN_NDTIMRANGES][IWN_NPOWERLEVELS] = { 1568198429Srpaulo /* DTIM <= 2 */ 1569198429Srpaulo { 1570198429Srpaulo { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1571198429Srpaulo { 200, 500, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 1 */ 1572198429Srpaulo { 200, 300, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 2 */ 1573198429Srpaulo { 50, 100, { 2, 2, 2, 2, -1 }, 0 }, /* PS level 3 */ 1574198429Srpaulo { 50, 25, { 2, 2, 4, 4, -1 }, 1 }, /* PS level 4 */ 1575198429Srpaulo { 25, 25, { 2, 2, 4, 6, -1 }, 2 } /* PS level 5 */ 1576198429Srpaulo }, 1577198429Srpaulo /* 3 <= DTIM <= 10 */ 1578198429Srpaulo { 1579198429Srpaulo { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1580198429Srpaulo { 200, 500, { 1, 2, 3, 4, 4 }, 0 }, /* PS level 1 */ 1581198429Srpaulo { 200, 300, { 1, 2, 3, 4, 7 }, 0 }, /* PS level 2 */ 1582198429Srpaulo { 50, 100, { 2, 4, 6, 7, 9 }, 0 }, /* PS level 3 */ 1583198429Srpaulo { 50, 25, { 2, 4, 6, 9, 10 }, 1 }, /* PS level 4 */ 1584198429Srpaulo { 25, 25, { 2, 4, 7, 10, 10 }, 2 } /* PS level 5 */ 1585198429Srpaulo }, 1586198429Srpaulo /* DTIM >= 11 */ 1587198429Srpaulo { 1588198429Srpaulo { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1589198429Srpaulo { 200, 500, { 1, 2, 3, 4, -1 }, 0 }, /* PS level 1 */ 1590198429Srpaulo { 200, 300, { 2, 4, 6, 7, -1 }, 0 }, /* PS level 2 */ 1591198429Srpaulo { 50, 100, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 3 */ 1592198429Srpaulo { 50, 25, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 4 */ 1593198429Srpaulo { 25, 25, { 4, 7, 10, 10, -1 }, 0 } /* PS level 5 */ 1594198429Srpaulo } 1595198429Srpaulo}; 1596198429Srpaulo 1597198429Srpaulostruct iwn_sensitivity_limits { 1598198429Srpaulo uint32_t min_ofdm_x1; 1599198429Srpaulo uint32_t max_ofdm_x1; 1600198429Srpaulo uint32_t min_ofdm_mrc_x1; 1601198429Srpaulo uint32_t max_ofdm_mrc_x1; 1602198429Srpaulo uint32_t min_ofdm_x4; 1603198429Srpaulo uint32_t max_ofdm_x4; 1604198429Srpaulo uint32_t min_ofdm_mrc_x4; 1605198429Srpaulo uint32_t max_ofdm_mrc_x4; 1606198429Srpaulo uint32_t min_cck_x4; 1607198429Srpaulo uint32_t max_cck_x4; 1608198429Srpaulo uint32_t min_cck_mrc_x4; 1609198429Srpaulo uint32_t max_cck_mrc_x4; 1610198429Srpaulo uint32_t min_energy_cck; 1611198429Srpaulo uint32_t energy_cck; 1612198429Srpaulo uint32_t energy_ofdm; 1613198429Srpaulo}; 1614198429Srpaulo 1615198429Srpaulo/* 1616198429Srpaulo * RX sensitivity limits (values obtained from the reference driver.) 1617198429Srpaulo */ 1618198429Srpaulostatic const struct iwn_sensitivity_limits iwn4965_sensitivity_limits = { 1619198429Srpaulo 105, 140, 1620201209Srpaulo 220, 270, 1621198429Srpaulo 85, 120, 1622198429Srpaulo 170, 210, 1623198429Srpaulo 125, 200, 1624198429Srpaulo 200, 400, 1625198429Srpaulo 97, 1626198429Srpaulo 100, 1627198429Srpaulo 100 1628198429Srpaulo}; 1629198429Srpaulo 1630198429Srpaulostatic const struct iwn_sensitivity_limits iwn5000_sensitivity_limits = { 1631206444Sbschmidt 120, 120, /* min = max for performance bug in DSP. */ 1632206444Sbschmidt 240, 240, /* min = max for performance bug in DSP. */ 1633198429Srpaulo 90, 120, 1634198429Srpaulo 170, 210, 1635198429Srpaulo 125, 200, 1636198429Srpaulo 170, 400, 1637198429Srpaulo 95, 1638198429Srpaulo 95, 1639198429Srpaulo 95 1640198429Srpaulo}; 1641198429Srpaulo 1642201209Srpaulostatic const struct iwn_sensitivity_limits iwn5150_sensitivity_limits = { 1643201209Srpaulo 105, 105, /* min = max for performance bug in DSP. */ 1644201209Srpaulo 220, 220, /* min = max for performance bug in DSP. */ 1645201209Srpaulo 90, 120, 1646201209Srpaulo 170, 210, 1647201209Srpaulo 125, 200, 1648201209Srpaulo 170, 400, 1649201209Srpaulo 95, 1650201209Srpaulo 95, 1651201209Srpaulo 95 1652201209Srpaulo}; 1653201209Srpaulo 1654206444Sbschmidtstatic const struct iwn_sensitivity_limits iwn1000_sensitivity_limits = { 1655206444Sbschmidt 120, 155, 1656206444Sbschmidt 240, 290, 1657220726Sbschmidt 90, 120, 1658206444Sbschmidt 170, 210, 1659206444Sbschmidt 125, 200, 1660206444Sbschmidt 170, 400, 1661220726Sbschmidt 95, 1662220726Sbschmidt 95, 1663220726Sbschmidt 95 1664206444Sbschmidt}; 1665206444Sbschmidt 1666201209Srpaulostatic const struct iwn_sensitivity_limits iwn6000_sensitivity_limits = { 1667206444Sbschmidt 105, 110, 1668201209Srpaulo 192, 232, 1669201209Srpaulo 80, 145, 1670201209Srpaulo 128, 232, 1671201209Srpaulo 125, 175, 1672201209Srpaulo 160, 310, 1673201209Srpaulo 97, 1674201209Srpaulo 97, 1675201209Srpaulo 100 1676201209Srpaulo}; 1677201209Srpaulo 1678198429Srpaulo/* Map TID to TX scheduler's FIFO. */ 1679198429Srpaulostatic const uint8_t iwn_tid2fifo[] = { 1680198429Srpaulo 1, 0, 0, 1, 2, 2, 3, 3, 7, 7, 7, 7, 7, 7, 7, 7, 3 1681198429Srpaulo}; 1682198429Srpaulo 1683201209Srpaulo/* WiFi/WiMAX coexist event priority table for 6050. */ 1684201209Srpaulostatic const struct iwn5000_wimax_event iwn6050_wimax_events[] = { 1685201209Srpaulo { 0x04, 0x03, 0x00, 0x00 }, 1686201209Srpaulo { 0x04, 0x03, 0x00, 0x03 }, 1687201209Srpaulo { 0x04, 0x03, 0x00, 0x03 }, 1688201209Srpaulo { 0x04, 0x03, 0x00, 0x03 }, 1689201209Srpaulo { 0x04, 0x03, 0x00, 0x00 }, 1690201209Srpaulo { 0x04, 0x03, 0x00, 0x07 }, 1691201209Srpaulo { 0x04, 0x03, 0x00, 0x00 }, 1692201209Srpaulo { 0x04, 0x03, 0x00, 0x03 }, 1693201209Srpaulo { 0x04, 0x03, 0x00, 0x03 }, 1694201209Srpaulo { 0x04, 0x03, 0x00, 0x00 }, 1695201209Srpaulo { 0x06, 0x03, 0x00, 0x07 }, 1696201209Srpaulo { 0x04, 0x03, 0x00, 0x00 }, 1697201209Srpaulo { 0x06, 0x06, 0x00, 0x03 }, 1698201209Srpaulo { 0x04, 0x03, 0x00, 0x07 }, 1699201209Srpaulo { 0x04, 0x03, 0x00, 0x00 }, 1700201209Srpaulo { 0x04, 0x03, 0x00, 0x00 } 1701201209Srpaulo}; 1702201209Srpaulo 1703198429Srpaulo/* Firmware errors. */ 1704198429Srpaulostatic const char * const iwn_fw_errmsg[] = { 1705198429Srpaulo "OK", 1706198429Srpaulo "FAIL", 1707198429Srpaulo "BAD_PARAM", 1708198429Srpaulo "BAD_CHECKSUM", 1709198429Srpaulo "NMI_INTERRUPT_WDG", 1710198429Srpaulo "SYSASSERT", 1711198429Srpaulo "FATAL_ERROR", 1712198429Srpaulo "BAD_COMMAND", 1713198429Srpaulo "HW_ERROR_TUNE_LOCK", 1714198429Srpaulo "HW_ERROR_TEMPERATURE", 1715198429Srpaulo "ILLEGAL_CHAN_FREQ", 1716198429Srpaulo "VCC_NOT_STABLE", 1717198429Srpaulo "FH_ERROR", 1718198429Srpaulo "NMI_INTERRUPT_HOST", 1719198429Srpaulo "NMI_INTERRUPT_ACTION_PT", 1720198429Srpaulo "NMI_INTERRUPT_UNKNOWN", 1721198429Srpaulo "UCODE_VERSION_MISMATCH", 1722198429Srpaulo "HW_ERROR_ABS_LOCK", 1723198429Srpaulo "HW_ERROR_CAL_LOCK_FAIL", 1724198429Srpaulo "NMI_INTERRUPT_INST_ACTION_PT", 1725198429Srpaulo "NMI_INTERRUPT_DATA_ACTION_PT", 1726198429Srpaulo "NMI_TRM_HW_ER", 1727198429Srpaulo "NMI_INTERRUPT_TRM", 1728198429Srpaulo "NMI_INTERRUPT_BREAKPOINT" 1729198429Srpaulo "DEBUG_0", 1730198429Srpaulo "DEBUG_1", 1731198429Srpaulo "DEBUG_2", 1732198429Srpaulo "DEBUG_3", 1733206444Sbschmidt "ADVANCED_SYSASSERT" 1734198429Srpaulo}; 1735198429Srpaulo 1736198429Srpaulo/* Find least significant bit that is set. */ 1737198429Srpaulo#define IWN_LSB(x) ((((x) - 1) & (x)) ^ (x)) 1738198429Srpaulo 1739178676Ssam#define IWN_READ(sc, reg) \ 1740178676Ssam bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 1741178676Ssam 1742178676Ssam#define IWN_WRITE(sc, reg, val) \ 1743178676Ssam bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 1744178676Ssam 1745201209Srpaulo#define IWN_WRITE_1(sc, reg, val) \ 1746201209Srpaulo bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 1747201209Srpaulo 1748198429Srpaulo#define IWN_SETBITS(sc, reg, mask) \ 1749198429Srpaulo IWN_WRITE(sc, reg, IWN_READ(sc, reg) | (mask)) 1750198429Srpaulo 1751198429Srpaulo#define IWN_CLRBITS(sc, reg, mask) \ 1752198429Srpaulo IWN_WRITE(sc, reg, IWN_READ(sc, reg) & ~(mask)) 1753201209Srpaulo 1754201209Srpaulo#define IWN_BARRIER_WRITE(sc) \ 1755201209Srpaulo bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 1756201209Srpaulo BUS_SPACE_BARRIER_WRITE) 1757201209Srpaulo 1758201209Srpaulo#define IWN_BARRIER_READ_WRITE(sc) \ 1759201209Srpaulo bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 1760201209Srpaulo BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 1761