if_iwnreg.h revision 220659
1/* $FreeBSD: head/sys/dev/iwn/if_iwnreg.h 220659 2011-04-15 16:50:37Z bschmidt $ */ 2/* $OpenBSD: if_iwnreg.h,v 1.40 2010/05/05 19:41:57 damien Exp $ */ 3 4/*- 5 * Copyright (c) 2007, 2008 6 * Damien Bergamini <damien.bergamini@free.fr> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21#define IWN_TX_RING_COUNT 256 22#define IWN_TX_RING_LOMARK 192 23#define IWN_TX_RING_HIMARK 224 24#define IWN_RX_RING_COUNT_LOG 6 25#define IWN_RX_RING_COUNT (1 << IWN_RX_RING_COUNT_LOG) 26 27#define IWN4965_NTXQUEUES 16 28#define IWN5000_NTXQUEUES 20 29 30#define IWN4965_NDMACHNLS 7 31#define IWN5000_NDMACHNLS 8 32 33#define IWN_SRVC_DMACHNL 9 34 35#define IWN_ICT_SIZE 4096 36#define IWN_ICT_COUNT (IWN_ICT_SIZE / sizeof (uint32_t)) 37 38/* Maximum number of DMA segments for TX. */ 39#define IWN_MAX_SCATTER 20 40 41/* RX buffers must be large enough to hold a full 4K A-MPDU. */ 42#define IWN_RBUF_SIZE (4 * 1024) 43 44#if defined(__LP64__) 45/* HW supports 36-bit DMA addresses. */ 46#define IWN_LOADDR(paddr) ((uint32_t)(paddr)) 47#define IWN_HIADDR(paddr) (((paddr) >> 32) & 0xf) 48#else 49#define IWN_LOADDR(paddr) (paddr) 50#define IWN_HIADDR(paddr) (0) 51#endif 52 53/* 54 * Control and status registers. 55 */ 56#define IWN_HW_IF_CONFIG 0x000 57#define IWN_INT_COALESCING 0x004 58#define IWN_INT_PERIODIC 0x005 /* use IWN_WRITE_1 */ 59#define IWN_INT 0x008 60#define IWN_INT_MASK 0x00c 61#define IWN_FH_INT 0x010 62#define IWN_RESET 0x020 63#define IWN_GP_CNTRL 0x024 64#define IWN_HW_REV 0x028 65#define IWN_EEPROM 0x02c 66#define IWN_EEPROM_GP 0x030 67#define IWN_OTP_GP 0x034 68#define IWN_GIO 0x03c 69#define IWN_GP_DRIVER 0x050 70#define IWN_UCODE_GP1_CLR 0x05c 71#define IWN_LED 0x094 72#define IWN_DRAM_INT_TBL 0x0a0 73#define IWN_GIO_CHICKEN 0x100 74#define IWN_ANA_PLL 0x20c 75#define IWN_HW_REV_WA 0x22c 76#define IWN_DBG_HPET_MEM 0x240 77#define IWN_DBG_LINK_PWR_MGMT 0x250 78#define IWN_MEM_RADDR 0x40c 79#define IWN_MEM_WADDR 0x410 80#define IWN_MEM_WDATA 0x418 81#define IWN_MEM_RDATA 0x41c 82#define IWN_PRPH_WADDR 0x444 83#define IWN_PRPH_RADDR 0x448 84#define IWN_PRPH_WDATA 0x44c 85#define IWN_PRPH_RDATA 0x450 86#define IWN_HBUS_TARG_WRPTR 0x460 87 88/* 89 * Flow-Handler registers. 90 */ 91#define IWN_FH_TFBD_CTRL0(qid) (0x1900 + (qid) * 8) 92#define IWN_FH_TFBD_CTRL1(qid) (0x1904 + (qid) * 8) 93#define IWN_FH_KW_ADDR 0x197c 94#define IWN_FH_SRAM_ADDR(qid) (0x19a4 + (qid) * 4) 95#define IWN_FH_CBBC_QUEUE(qid) (0x19d0 + (qid) * 4) 96#define IWN_FH_STATUS_WPTR 0x1bc0 97#define IWN_FH_RX_BASE 0x1bc4 98#define IWN_FH_RX_WPTR 0x1bc8 99#define IWN_FH_RX_CONFIG 0x1c00 100#define IWN_FH_RX_STATUS 0x1c44 101#define IWN_FH_TX_CONFIG(qid) (0x1d00 + (qid) * 32) 102#define IWN_FH_TXBUF_STATUS(qid) (0x1d08 + (qid) * 32) 103#define IWN_FH_TX_CHICKEN 0x1e98 104#define IWN_FH_TX_STATUS 0x1eb0 105 106/* 107 * TX scheduler registers. 108 */ 109#define IWN_SCHED_BASE 0xa02c00 110#define IWN_SCHED_SRAM_ADDR (IWN_SCHED_BASE + 0x000) 111#define IWN5000_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x008) 112#define IWN4965_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x010) 113#define IWN5000_SCHED_TXFACT (IWN_SCHED_BASE + 0x010) 114#define IWN4965_SCHED_TXFACT (IWN_SCHED_BASE + 0x01c) 115#define IWN4965_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x064 + (qid) * 4) 116#define IWN5000_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x068 + (qid) * 4) 117#define IWN4965_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0d0) 118#define IWN4965_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x0e4) 119#define IWN5000_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0e8) 120#define IWN4965_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x104 + (qid) * 4) 121#define IWN5000_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x108) 122#define IWN5000_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x10c + (qid) * 4) 123#define IWN5000_SCHED_AGGR_SEL (IWN_SCHED_BASE + 0x248) 124 125/* 126 * Offsets in TX scheduler's SRAM. 127 */ 128#define IWN4965_SCHED_CTX_OFF 0x380 129#define IWN4965_SCHED_CTX_LEN 416 130#define IWN4965_SCHED_QUEUE_OFFSET(qid) (0x380 + (qid) * 8) 131#define IWN4965_SCHED_TRANS_TBL(qid) (0x500 + (qid) * 2) 132#define IWN5000_SCHED_CTX_OFF 0x600 133#define IWN5000_SCHED_CTX_LEN 520 134#define IWN5000_SCHED_QUEUE_OFFSET(qid) (0x600 + (qid) * 8) 135#define IWN5000_SCHED_TRANS_TBL(qid) (0x7e0 + (qid) * 2) 136 137/* 138 * NIC internal memory offsets. 139 */ 140#define IWN_APMG_CLK_CTRL 0x3000 141#define IWN_APMG_CLK_EN 0x3004 142#define IWN_APMG_CLK_DIS 0x3008 143#define IWN_APMG_PS 0x300c 144#define IWN_APMG_DIGITAL_SVR 0x3058 145#define IWN_APMG_ANALOG_SVR 0x306c 146#define IWN_APMG_PCI_STT 0x3010 147#define IWN_BSM_WR_CTRL 0x3400 148#define IWN_BSM_WR_MEM_SRC 0x3404 149#define IWN_BSM_WR_MEM_DST 0x3408 150#define IWN_BSM_WR_DWCOUNT 0x340c 151#define IWN_BSM_DRAM_TEXT_ADDR 0x3490 152#define IWN_BSM_DRAM_TEXT_SIZE 0x3494 153#define IWN_BSM_DRAM_DATA_ADDR 0x3498 154#define IWN_BSM_DRAM_DATA_SIZE 0x349c 155#define IWN_BSM_SRAM_BASE 0x3800 156 157/* Possible flags for register IWN_HW_IF_CONFIG. */ 158#define IWN_HW_IF_CONFIG_4965_R (1 << 4) 159#define IWN_HW_IF_CONFIG_MAC_SI (1 << 8) 160#define IWN_HW_IF_CONFIG_RADIO_SI (1 << 9) 161#define IWN_HW_IF_CONFIG_EEPROM_LOCKED (1 << 21) 162#define IWN_HW_IF_CONFIG_NIC_READY (1 << 22) 163#define IWN_HW_IF_CONFIG_HAP_WAKE_L1A (1 << 23) 164#define IWN_HW_IF_CONFIG_PREPARE_DONE (1 << 25) 165#define IWN_HW_IF_CONFIG_PREPARE (1 << 27) 166 167/* Possible values for register IWN_INT_PERIODIC. */ 168#define IWN_INT_PERIODIC_DIS 0x00 169#define IWN_INT_PERIODIC_ENA 0xff 170 171/* Possible flags for registers IWN_PRPH_RADDR/IWN_PRPH_WADDR. */ 172#define IWN_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24) 173 174/* Possible values for IWN_BSM_WR_MEM_DST. */ 175#define IWN_FW_TEXT_BASE 0x00000000 176#define IWN_FW_DATA_BASE 0x00800000 177 178/* Possible flags for register IWN_RESET. */ 179#define IWN_RESET_NEVO (1 << 0) 180#define IWN_RESET_SW (1 << 7) 181#define IWN_RESET_MASTER_DISABLED (1 << 8) 182#define IWN_RESET_STOP_MASTER (1 << 9) 183#define IWN_RESET_LINK_PWR_MGMT_DIS (1 << 31) 184 185/* Possible flags for register IWN_GP_CNTRL. */ 186#define IWN_GP_CNTRL_MAC_ACCESS_ENA (1 << 0) 187#define IWN_GP_CNTRL_MAC_CLOCK_READY (1 << 0) 188#define IWN_GP_CNTRL_INIT_DONE (1 << 2) 189#define IWN_GP_CNTRL_MAC_ACCESS_REQ (1 << 3) 190#define IWN_GP_CNTRL_SLEEP (1 << 4) 191#define IWN_GP_CNTRL_RFKILL (1 << 27) 192 193/* Possible flags for register IWN_HW_REV. */ 194#define IWN_HW_REV_TYPE_SHIFT 4 195#define IWN_HW_REV_TYPE_MASK 0x000000f0 196#define IWN_HW_REV_TYPE_4965 0 197#define IWN_HW_REV_TYPE_5300 2 198#define IWN_HW_REV_TYPE_5350 3 199#define IWN_HW_REV_TYPE_5150 4 200#define IWN_HW_REV_TYPE_5100 5 201#define IWN_HW_REV_TYPE_1000 6 202#define IWN_HW_REV_TYPE_6000 7 203#define IWN_HW_REV_TYPE_6050 8 204#define IWN_HW_REV_TYPE_6005 11 205 206/* Possible flags for register IWN_GIO_CHICKEN. */ 207#define IWN_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23) 208#define IWN_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29) 209 210/* Possible flags for register IWN_GIO. */ 211#define IWN_GIO_L0S_ENA (1 << 1) 212 213/* Possible flags for register IWN_GP_DRIVER. */ 214#define IWN_GP_DRIVER_RADIO_3X3_HYB (0 << 0) 215#define IWN_GP_DRIVER_RADIO_2X2_HYB (1 << 0) 216#define IWN_GP_DRIVER_RADIO_2X2_IPA (2 << 0) 217#define IWN_GP_DRIVER_CALIB_VER6 (1 << 2) 218 219/* Possible flags for register IWN_UCODE_GP1_CLR. */ 220#define IWN_UCODE_GP1_RFKILL (1 << 1) 221#define IWN_UCODE_GP1_CMD_BLOCKED (1 << 2) 222#define IWN_UCODE_GP1_CTEMP_STOP_RF (1 << 3) 223 224/* Possible flags/values for register IWN_LED. */ 225#define IWN_LED_BSM_CTRL (1 << 5) 226#define IWN_LED_OFF 0x00000038 227#define IWN_LED_ON 0x00000078 228 229/* Possible flags for register IWN_DRAM_INT_TBL. */ 230#define IWN_DRAM_INT_TBL_WRAP_CHECK (1 << 27) 231#define IWN_DRAM_INT_TBL_ENABLE (1 << 31) 232 233/* Possible values for register IWN_ANA_PLL. */ 234#define IWN_ANA_PLL_INIT 0x00880300 235 236/* Possible flags for register IWN_FH_RX_STATUS. */ 237#define IWN_FH_RX_STATUS_IDLE (1 << 24) 238 239/* Possible flags for register IWN_BSM_WR_CTRL. */ 240#define IWN_BSM_WR_CTRL_START_EN (1 << 30) 241#define IWN_BSM_WR_CTRL_START (1 << 31) 242 243/* Possible flags for register IWN_INT. */ 244#define IWN_INT_ALIVE (1 << 0) 245#define IWN_INT_WAKEUP (1 << 1) 246#define IWN_INT_SW_RX (1 << 3) 247#define IWN_INT_CT_REACHED (1 << 6) 248#define IWN_INT_RF_TOGGLED (1 << 7) 249#define IWN_INT_SW_ERR (1 << 25) 250#define IWN_INT_SCHED (1 << 26) 251#define IWN_INT_FH_TX (1 << 27) 252#define IWN_INT_RX_PERIODIC (1 << 28) 253#define IWN_INT_HW_ERR (1 << 29) 254#define IWN_INT_FH_RX (1 << 31) 255 256/* Shortcut. */ 257#define IWN_INT_MASK_DEF \ 258 (IWN_INT_SW_ERR | IWN_INT_HW_ERR | IWN_INT_FH_TX | \ 259 IWN_INT_FH_RX | IWN_INT_ALIVE | IWN_INT_WAKEUP | \ 260 IWN_INT_SW_RX | IWN_INT_CT_REACHED | IWN_INT_RF_TOGGLED) 261 262/* Possible flags for register IWN_FH_INT. */ 263#define IWN_FH_INT_TX_CHNL(x) (1 << (x)) 264#define IWN_FH_INT_RX_CHNL(x) (1 << ((x) + 16)) 265#define IWN_FH_INT_HI_PRIOR (1 << 30) 266/* Shortcuts for the above. */ 267#define IWN_FH_INT_TX \ 268 (IWN_FH_INT_TX_CHNL(0) | IWN_FH_INT_TX_CHNL(1)) 269#define IWN_FH_INT_RX \ 270 (IWN_FH_INT_RX_CHNL(0) | IWN_FH_INT_RX_CHNL(1) | IWN_FH_INT_HI_PRIOR) 271 272/* Possible flags/values for register IWN_FH_TX_CONFIG. */ 273#define IWN_FH_TX_CONFIG_DMA_PAUSE 0 274#define IWN_FH_TX_CONFIG_DMA_ENA (1 << 31) 275#define IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD (1 << 20) 276 277/* Possible flags/values for register IWN_FH_TXBUF_STATUS. */ 278#define IWN_FH_TXBUF_STATUS_TBNUM(x) ((x) << 20) 279#define IWN_FH_TXBUF_STATUS_TBIDX(x) ((x) << 12) 280#define IWN_FH_TXBUF_STATUS_TFBD_VALID 3 281 282/* Possible flags for register IWN_FH_TX_CHICKEN. */ 283#define IWN_FH_TX_CHICKEN_SCHED_RETRY (1 << 1) 284 285/* Possible flags for register IWN_FH_TX_STATUS. */ 286#define IWN_FH_TX_STATUS_IDLE(chnl) (1 << ((chnl) + 16)) 287 288/* Possible flags for register IWN_FH_RX_CONFIG. */ 289#define IWN_FH_RX_CONFIG_ENA (1 << 31) 290#define IWN_FH_RX_CONFIG_NRBD(x) ((x) << 20) 291#define IWN_FH_RX_CONFIG_RB_SIZE_8K (1 << 16) 292#define IWN_FH_RX_CONFIG_SINGLE_FRAME (1 << 15) 293#define IWN_FH_RX_CONFIG_IRQ_DST_HOST (1 << 12) 294#define IWN_FH_RX_CONFIG_RB_TIMEOUT(x) ((x) << 4) 295#define IWN_FH_RX_CONFIG_IGN_RXF_EMPTY (1 << 2) 296 297/* Possible flags for register IWN_FH_TX_CONFIG. */ 298#define IWN_FH_TX_CONFIG_DMA_ENA (1 << 31) 299#define IWN_FH_TX_CONFIG_DMA_CREDIT_ENA (1 << 3) 300 301/* Possible flags for register IWN_EEPROM. */ 302#define IWN_EEPROM_READ_VALID (1 << 0) 303#define IWN_EEPROM_CMD (1 << 1) 304 305/* Possible flags for register IWN_EEPROM_GP. */ 306#define IWN_EEPROM_GP_IF_OWNER 0x00000180 307 308/* Possible flags for register IWN_OTP_GP. */ 309#define IWN_OTP_GP_DEV_SEL_OTP (1 << 16) 310#define IWN_OTP_GP_RELATIVE_ACCESS (1 << 17) 311#define IWN_OTP_GP_ECC_CORR_STTS (1 << 20) 312#define IWN_OTP_GP_ECC_UNCORR_STTS (1 << 21) 313 314/* Possible flags for register IWN_SCHED_QUEUE_STATUS. */ 315#define IWN4965_TXQ_STATUS_ACTIVE 0x0007fc01 316#define IWN4965_TXQ_STATUS_INACTIVE 0x0007fc00 317#define IWN4965_TXQ_STATUS_AGGR_ENA (1 << 5 | 1 << 8) 318#define IWN4965_TXQ_STATUS_CHGACT (1 << 10) 319#define IWN5000_TXQ_STATUS_ACTIVE 0x00ff0018 320#define IWN5000_TXQ_STATUS_INACTIVE 0x00ff0010 321#define IWN5000_TXQ_STATUS_CHGACT (1 << 19) 322 323/* Possible flags for registers IWN_APMG_CLK_*. */ 324#define IWN_APMG_CLK_CTRL_DMA_CLK_RQT (1 << 9) 325#define IWN_APMG_CLK_CTRL_BSM_CLK_RQT (1 << 11) 326 327/* Possible flags for register IWN_APMG_PS. */ 328#define IWN_APMG_PS_EARLY_PWROFF_DIS (1 << 22) 329#define IWN_APMG_PS_PWR_SRC(x) ((x) << 24) 330#define IWN_APMG_PS_PWR_SRC_VMAIN 0 331#define IWN_APMG_PS_PWR_SRC_VAUX 2 332#define IWN_APMG_PS_PWR_SRC_MASK IWN_APMG_PS_PWR_SRC(3) 333#define IWN_APMG_PS_RESET_REQ (1 << 26) 334 335/* Possible flags for register IWN_APMG_DIGITAL_SVR. */ 336#define IWN_APMG_DIGITAL_SVR_VOLTAGE(x) (((x) & 0xf) << 5) 337#define IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK \ 338 IWN_APMG_DIGITAL_SVR_VOLTAGE(0xf) 339#define IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32 \ 340 IWN_APMG_DIGITAL_SVR_VOLTAGE(3) 341 342/* Possible flags for IWN_APMG_PCI_STT. */ 343#define IWN_APMG_PCI_STT_L1A_DIS (1 << 11) 344 345/* Possible flags for register IWN_BSM_DRAM_TEXT_SIZE. */ 346#define IWN_FW_UPDATED (1 << 31) 347 348#define IWN_SCHED_WINSZ 64 349#define IWN_SCHED_LIMIT 64 350#define IWN4965_SCHED_COUNT 512 351#define IWN5000_SCHED_COUNT (IWN_TX_RING_COUNT + IWN_SCHED_WINSZ) 352#define IWN4965_SCHEDSZ (IWN4965_NTXQUEUES * IWN4965_SCHED_COUNT * 2) 353#define IWN5000_SCHEDSZ (IWN5000_NTXQUEUES * IWN5000_SCHED_COUNT * 2) 354 355struct iwn_tx_desc { 356 uint8_t reserved1[3]; 357 uint8_t nsegs; 358 struct { 359 uint32_t addr; 360 uint16_t len; 361 } __packed segs[IWN_MAX_SCATTER]; 362 /* Pad to 128 bytes. */ 363 uint32_t reserved2; 364} __packed; 365 366struct iwn_rx_status { 367 uint16_t closed_count; 368 uint16_t closed_rx_count; 369 uint16_t finished_count; 370 uint16_t finished_rx_count; 371 uint32_t reserved[2]; 372} __packed; 373 374struct iwn_rx_desc { 375 uint32_t len; 376 uint8_t type; 377#define IWN_UC_READY 1 378#define IWN_ADD_NODE_DONE 24 379#define IWN_TX_DONE 28 380#define IWN5000_CALIBRATION_RESULT 102 381#define IWN5000_CALIBRATION_DONE 103 382#define IWN_START_SCAN 130 383#define IWN_STOP_SCAN 132 384#define IWN_RX_STATISTICS 156 385#define IWN_BEACON_STATISTICS 157 386#define IWN_STATE_CHANGED 161 387#define IWN_BEACON_MISSED 162 388#define IWN_RX_PHY 192 389#define IWN_MPDU_RX_DONE 193 390#define IWN_RX_DONE 195 391#define IWN_RX_COMPRESSED_BA 197 392 393 uint8_t flags; 394 uint8_t idx; 395 uint8_t qid; 396} __packed; 397 398/* Possible RX status flags. */ 399#define IWN_RX_NO_CRC_ERR (1 << 0) 400#define IWN_RX_NO_OVFL_ERR (1 << 1) 401/* Shortcut for the above. */ 402#define IWN_RX_NOERROR (IWN_RX_NO_CRC_ERR | IWN_RX_NO_OVFL_ERR) 403#define IWN_RX_MPDU_MIC_OK (1 << 6) 404#define IWN_RX_CIPHER_MASK (7 << 8) 405#define IWN_RX_CIPHER_CCMP (2 << 8) 406#define IWN_RX_MPDU_DEC (1 << 11) 407#define IWN_RX_DECRYPT_MASK (3 << 11) 408#define IWN_RX_DECRYPT_OK (3 << 11) 409 410struct iwn_tx_cmd { 411 uint8_t code; 412#define IWN_CMD_RXON 16 413#define IWN_CMD_RXON_ASSOC 17 414#define IWN_CMD_EDCA_PARAMS 19 415#define IWN_CMD_TIMING 20 416#define IWN_CMD_ADD_NODE 24 417#define IWN_CMD_TX_DATA 28 418#define IWN_CMD_LINK_QUALITY 78 419#define IWN_CMD_SET_LED 72 420#define IWN5000_CMD_WIMAX_COEX 90 421#define IWN5000_CMD_CALIB_CONFIG 101 422#define IWN5000_CMD_CALIB_RESULT 102 423#define IWN5000_CMD_CALIB_COMPLETE 103 424#define IWN_CMD_SET_POWER_MODE 119 425#define IWN_CMD_SCAN 128 426#define IWN_CMD_SCAN_RESULTS 131 427#define IWN_CMD_TXPOWER_DBM 149 428#define IWN_CMD_TXPOWER 151 429#define IWN5000_CMD_TX_ANT_CONFIG 152 430#define IWN_CMD_BT_COEX 155 431#define IWN_CMD_GET_STATISTICS 156 432#define IWN_CMD_SET_CRITICAL_TEMP 164 433#define IWN_CMD_SET_SENSITIVITY 168 434#define IWN_CMD_PHY_CALIB 176 435 436 uint8_t flags; 437 uint8_t idx; 438 uint8_t qid; 439 uint8_t data[136]; 440} __packed; 441 442/* Antenna flags, used in various commands. */ 443#define IWN_ANT_A (1 << 0) 444#define IWN_ANT_B (1 << 1) 445#define IWN_ANT_C (1 << 2) 446/* Shortcuts. */ 447#define IWN_ANT_AB (IWN_ANT_A | IWN_ANT_B) 448#define IWN_ANT_BC (IWN_ANT_B | IWN_ANT_C) 449#define IWN_ANT_ABC (IWN_ANT_A | IWN_ANT_B | IWN_ANT_C) 450 451/* Structure for command IWN_CMD_RXON. */ 452struct iwn_rxon { 453 uint8_t myaddr[IEEE80211_ADDR_LEN]; 454 uint16_t reserved1; 455 uint8_t bssid[IEEE80211_ADDR_LEN]; 456 uint16_t reserved2; 457 uint8_t wlap[IEEE80211_ADDR_LEN]; 458 uint16_t reserved3; 459 uint8_t mode; 460#define IWN_MODE_HOSTAP 1 461#define IWN_MODE_STA 3 462#define IWN_MODE_IBSS 4 463#define IWN_MODE_MONITOR 6 464 465 uint8_t air; 466 uint16_t rxchain; 467#define IWN_RXCHAIN_DRIVER_FORCE (1 << 0) 468#define IWN_RXCHAIN_VALID(x) (((x) & IWN_ANT_ABC) << 1) 469#define IWN_RXCHAIN_FORCE_SEL(x) (((x) & IWN_ANT_ABC) << 4) 470#define IWN_RXCHAIN_FORCE_MIMO_SEL(x) (((x) & IWN_ANT_ABC) << 7) 471#define IWN_RXCHAIN_IDLE_COUNT(x) ((x) << 10) 472#define IWN_RXCHAIN_MIMO_COUNT(x) ((x) << 12) 473#define IWN_RXCHAIN_MIMO_FORCE (1 << 14) 474 475 uint8_t ofdm_mask; 476 uint8_t cck_mask; 477 uint16_t associd; 478 uint32_t flags; 479#define IWN_RXON_24GHZ (1 << 0) 480#define IWN_RXON_CCK (1 << 1) 481#define IWN_RXON_AUTO (1 << 2) 482#define IWN_RXON_SHSLOT (1 << 4) 483#define IWN_RXON_SHPREAMBLE (1 << 5) 484#define IWN_RXON_NODIVERSITY (1 << 7) 485#define IWN_RXON_ANTENNA_A (1 << 8) 486#define IWN_RXON_ANTENNA_B (1 << 9) 487#define IWN_RXON_TSF (1 << 15) 488#define IWN_RXON_CTS_TO_SELF (1 << 30) 489 490 uint32_t filter; 491#define IWN_FILTER_PROMISC (1 << 0) 492#define IWN_FILTER_CTL (1 << 1) 493#define IWN_FILTER_MULTICAST (1 << 2) 494#define IWN_FILTER_NODECRYPT (1 << 3) 495#define IWN_FILTER_BSS (1 << 5) 496#define IWN_FILTER_BEACON (1 << 6) 497 498 uint8_t chan; 499 uint8_t reserved4; 500 uint8_t ht_single_mask; 501 uint8_t ht_dual_mask; 502 /* The following fields are for >=5000 Series only. */ 503 uint8_t ht_triple_mask; 504 uint8_t reserved5; 505 uint16_t acquisition; 506 uint16_t reserved6; 507} __packed; 508 509#define IWN4965_RXONSZ (sizeof (struct iwn_rxon) - 6) 510#define IWN5000_RXONSZ (sizeof (struct iwn_rxon)) 511 512/* Structure for command IWN_CMD_ASSOCIATE. */ 513struct iwn_assoc { 514 uint32_t flags; 515 uint32_t filter; 516 uint8_t ofdm_mask; 517 uint8_t cck_mask; 518 uint16_t reserved; 519} __packed; 520 521/* Structure for command IWN_CMD_EDCA_PARAMS. */ 522struct iwn_edca_params { 523 uint32_t flags; 524#define IWN_EDCA_UPDATE (1 << 0) 525#define IWN_EDCA_TXOP (1 << 4) 526 527 struct { 528 uint16_t cwmin; 529 uint16_t cwmax; 530 uint8_t aifsn; 531 uint8_t reserved; 532 uint16_t txoplimit; 533 } __packed ac[WME_NUM_AC]; 534} __packed; 535 536/* Structure for command IWN_CMD_TIMING. */ 537struct iwn_cmd_timing { 538 uint64_t tstamp; 539 uint16_t bintval; 540 uint16_t atim; 541 uint32_t binitval; 542 uint16_t lintval; 543 uint16_t reserved; 544} __packed; 545 546/* Structure for command IWN_CMD_ADD_NODE. */ 547struct iwn_node_info { 548 uint8_t control; 549#define IWN_NODE_UPDATE (1 << 0) 550 551 uint8_t reserved1[3]; 552 553 uint8_t macaddr[IEEE80211_ADDR_LEN]; 554 uint16_t reserved2; 555 uint8_t id; 556#define IWN_ID_BSS 0 557#define IWN5000_ID_BROADCAST 15 558#define IWN4965_ID_BROADCAST 31 559 560 uint8_t flags; 561#define IWN_FLAG_SET_KEY (1 << 0) 562#define IWN_FLAG_SET_DISABLE_TID (1 << 1) 563#define IWN_FLAG_SET_TXRATE (1 << 2) 564#define IWN_FLAG_SET_ADDBA (1 << 3) 565#define IWN_FLAG_SET_DELBA (1 << 4) 566 567 uint16_t reserved3; 568 uint16_t kflags; 569#define IWN_KFLAG_CCMP (1 << 1) 570#define IWN_KFLAG_MAP (1 << 3) 571#define IWN_KFLAG_KID(kid) ((kid) << 8) 572#define IWN_KFLAG_INVALID (1 << 11) 573#define IWN_KFLAG_GROUP (1 << 14) 574 575 uint8_t tsc2; /* TKIP TSC2 */ 576 uint8_t reserved4; 577 uint16_t ttak[5]; 578 uint8_t kid; 579 uint8_t reserved5; 580 uint8_t key[16]; 581 /* The following 3 fields are for 5000 Series only. */ 582 uint64_t tsc; 583 uint8_t rxmic[8]; 584 uint8_t txmic[8]; 585 586 uint32_t htflags; 587#define IWN_AMDPU_SIZE_FACTOR(x) ((x) << 19) 588#define IWN_AMDPU_DENSITY(x) ((x) << 23) 589 590 uint32_t mask; 591 uint16_t disable_tid; 592 uint16_t reserved6; 593 uint8_t addba_tid; 594 uint8_t delba_tid; 595 uint16_t addba_ssn; 596 uint32_t reserved7; 597} __packed; 598 599struct iwn4965_node_info { 600 uint8_t control; 601 uint8_t reserved1[3]; 602 uint8_t macaddr[IEEE80211_ADDR_LEN]; 603 uint16_t reserved2; 604 uint8_t id; 605 uint8_t flags; 606 uint16_t reserved3; 607 uint16_t kflags; 608 uint8_t tsc2; /* TKIP TSC2 */ 609 uint8_t reserved4; 610 uint16_t ttak[5]; 611 uint8_t kid; 612 uint8_t reserved5; 613 uint8_t key[16]; 614 uint32_t htflags; 615 uint32_t mask; 616 uint16_t disable_tid; 617 uint16_t reserved6; 618 uint8_t addba_tid; 619 uint8_t delba_tid; 620 uint16_t addba_ssn; 621 uint32_t reserved7; 622} __packed; 623 624#define IWN_RFLAG_CCK (1 << 1) 625#define IWN_RFLAG_ANT(x) ((x) << 6) 626 627/* Structure for command IWN_CMD_TX_DATA. */ 628struct iwn_cmd_data { 629 uint16_t len; 630 uint16_t lnext; 631 uint32_t flags; 632#define IWN_TX_NEED_PROTECTION (1 << 0) /* 5000 only */ 633#define IWN_TX_NEED_RTS (1 << 1) 634#define IWN_TX_NEED_CTS (1 << 2) 635#define IWN_TX_NEED_ACK (1 << 3) 636#define IWN_TX_LINKQ (1 << 4) 637#define IWN_TX_IMM_BA (1 << 6) 638#define IWN_TX_FULL_TXOP (1 << 7) 639#define IWN_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */ 640#define IWN_TX_AUTO_SEQ (1 << 13) 641#define IWN_TX_MORE_FRAG (1 << 14) 642#define IWN_TX_INSERT_TSTAMP (1 << 16) 643#define IWN_TX_NEED_PADDING (1 << 20) 644 645 uint32_t scratch; 646 uint8_t plcp; 647 uint8_t rflags; 648 uint16_t xrflags; 649 650 uint8_t id; 651 uint8_t security; 652#define IWN_CIPHER_WEP40 1 653#define IWN_CIPHER_CCMP 2 654#define IWN_CIPHER_TKIP 3 655#define IWN_CIPHER_WEP104 9 656 657 uint8_t linkq; 658 uint8_t reserved2; 659 uint8_t key[16]; 660 uint16_t fnext; 661 uint16_t reserved3; 662 uint32_t lifetime; 663#define IWN_LIFETIME_INFINITE 0xffffffff 664 665 uint32_t loaddr; 666 uint8_t hiaddr; 667 uint8_t rts_ntries; 668 uint8_t data_ntries; 669 uint8_t tid; 670 uint16_t timeout; 671 uint16_t txop; 672} __packed; 673 674/* Structure for command IWN_CMD_LINK_QUALITY. */ 675#define IWN_MAX_TX_RETRIES 16 676struct iwn_cmd_link_quality { 677 uint8_t id; 678 uint8_t reserved1; 679 uint16_t ctl; 680 uint8_t flags; 681 uint8_t mimo; 682 uint8_t antmsk_1stream; 683 uint8_t antmsk_2stream; 684 uint8_t ridx[WME_NUM_AC]; 685 uint16_t ampdu_limit; 686 uint8_t ampdu_threshold; 687 uint8_t ampdu_max; 688 uint32_t reserved2; 689 struct { 690 uint8_t plcp; 691 uint8_t rflags; 692 uint16_t xrflags; 693 } __packed retry[IWN_MAX_TX_RETRIES]; 694 uint32_t reserved3; 695} __packed; 696 697/* Structure for command IWN_CMD_SET_LED. */ 698struct iwn_cmd_led { 699 uint32_t unit; /* multiplier (in usecs) */ 700 uint8_t which; 701#define IWN_LED_ACTIVITY 1 702#define IWN_LED_LINK 2 703 704 uint8_t off; 705 uint8_t on; 706 uint8_t reserved; 707} __packed; 708 709/* Structure for command IWN5000_CMD_WIMAX_COEX. */ 710struct iwn5000_wimax_coex { 711 uint32_t flags; 712#define IWN_WIMAX_COEX_STA_TABLE_VALID (1 << 0) 713#define IWN_WIMAX_COEX_UNASSOC_WA_UNMASK (1 << 2) 714#define IWN_WIMAX_COEX_ASSOC_WA_UNMASK (1 << 3) 715#define IWN_WIMAX_COEX_ENABLE (1 << 7) 716 717 struct iwn5000_wimax_event { 718 uint8_t request; 719 uint8_t window; 720 uint8_t reserved; 721 uint8_t flags; 722 } __packed events[16]; 723} __packed; 724 725/* Structures for command IWN5000_CMD_CALIB_CONFIG. */ 726struct iwn5000_calib_elem { 727 uint32_t enable; 728 uint32_t start; 729 uint32_t send; 730 uint32_t apply; 731 uint32_t reserved; 732} __packed; 733 734struct iwn5000_calib_status { 735 struct iwn5000_calib_elem once; 736 struct iwn5000_calib_elem perd; 737 uint32_t flags; 738} __packed; 739 740struct iwn5000_calib_config { 741 struct iwn5000_calib_status ucode; 742 struct iwn5000_calib_status driver; 743 uint32_t reserved; 744} __packed; 745 746/* Structure for command IWN_CMD_SET_POWER_MODE. */ 747struct iwn_pmgt_cmd { 748 uint16_t flags; 749#define IWN_PS_ALLOW_SLEEP (1 << 0) 750#define IWN_PS_NOTIFY (1 << 1) 751#define IWN_PS_SLEEP_OVER_DTIM (1 << 2) 752#define IWN_PS_PCI_PMGT (1 << 3) 753#define IWN_PS_FAST_PD (1 << 4) 754 755 uint8_t keepalive; 756 uint8_t debug; 757 uint32_t rxtimeout; 758 uint32_t txtimeout; 759 uint32_t intval[5]; 760 uint32_t beacons; 761} __packed; 762 763/* Structures for command IWN_CMD_SCAN. */ 764struct iwn_scan_essid { 765 uint8_t id; 766 uint8_t len; 767 uint8_t data[IEEE80211_NWID_LEN]; 768} __packed; 769 770struct iwn_scan_hdr { 771 uint16_t len; 772 uint8_t reserved1; 773 uint8_t nchan; 774 uint16_t quiet_time; 775 uint16_t quiet_threshold; 776 uint16_t crc_threshold; 777 uint16_t rxchain; 778 uint32_t max_svc; /* background scans */ 779 uint32_t pause_svc; /* background scans */ 780 uint32_t flags; 781 uint32_t filter; 782 783 /* Followed by a struct iwn_cmd_data. */ 784 /* Followed by an array of 20 structs iwn_scan_essid. */ 785 /* Followed by probe request body. */ 786 /* Followed by an array of ``nchan'' structs iwn_scan_chan. */ 787} __packed; 788 789struct iwn_scan_chan { 790 uint32_t flags; 791#define IWN_CHAN_ACTIVE (1 << 0) 792#define IWN_CHAN_NPBREQS(x) (((1 << (x)) - 1) << 1) 793 794 uint16_t chan; 795 uint8_t rf_gain; 796 uint8_t dsp_gain; 797 uint16_t active; /* msecs */ 798 uint16_t passive; /* msecs */ 799} __packed; 800 801/* Maximum size of a scan command. */ 802#define IWN_SCAN_MAXSZ (MCLBYTES - 4) 803 804/* Structure for command IWN_CMD_TXPOWER (4965AGN only.) */ 805#define IWN_RIDX_MAX 32 806struct iwn4965_cmd_txpower { 807 uint8_t band; 808 uint8_t reserved1; 809 uint8_t chan; 810 uint8_t reserved2; 811 struct { 812 uint8_t rf_gain[2]; 813 uint8_t dsp_gain[2]; 814 } __packed power[IWN_RIDX_MAX + 1]; 815} __packed; 816 817/* Structure for command IWN_CMD_TXPOWER_DBM (5000 Series only.) */ 818struct iwn5000_cmd_txpower { 819 int8_t global_limit; /* in half-dBm */ 820#define IWN5000_TXPOWER_AUTO 0x7f 821#define IWN5000_TXPOWER_MAX_DBM 16 822 823 uint8_t flags; 824#define IWN5000_TXPOWER_NO_CLOSED (1 << 6) 825 826 int8_t srv_limit; /* in half-dBm */ 827 uint8_t reserved; 828} __packed; 829 830/* Structure for command IWN_CMD_BLUETOOTH. */ 831struct iwn_bluetooth { 832 uint8_t flags; 833#define IWN_BT_COEX_CHAN_ANN (1 << 0) 834#define IWN_BT_COEX_BT_PRIO (1 << 1) 835#define IWN_BT_COEX_2_WIRE (1 << 2) 836 837 uint8_t lead_time; 838#define IWN_BT_LEAD_TIME_DEF 30 839 840 uint8_t max_kill; 841#define IWN_BT_MAX_KILL_DEF 5 842 843 uint8_t reserved; 844 uint32_t kill_ack; 845 uint32_t kill_cts; 846} __packed; 847 848/* Structure for command IWN_CMD_SET_CRITICAL_TEMP. */ 849struct iwn_critical_temp { 850 uint32_t reserved; 851 uint32_t tempM; 852 uint32_t tempR; 853/* degK <-> degC conversion macros. */ 854#define IWN_CTOK(c) ((c) + 273) 855#define IWN_KTOC(k) ((k) - 273) 856#define IWN_CTOMUK(c) (((c) * 1000000) + 273150000) 857} __packed; 858 859/* Structure for command IWN_CMD_SET_SENSITIVITY. */ 860struct iwn_sensitivity_cmd { 861 uint16_t which; 862#define IWN_SENSITIVITY_DEFAULTTBL 0 863#define IWN_SENSITIVITY_WORKTBL 1 864 865 uint16_t energy_cck; 866 uint16_t energy_ofdm; 867 uint16_t corr_ofdm_x1; 868 uint16_t corr_ofdm_mrc_x1; 869 uint16_t corr_cck_mrc_x4; 870 uint16_t corr_ofdm_x4; 871 uint16_t corr_ofdm_mrc_x4; 872 uint16_t corr_barker; 873 uint16_t corr_barker_mrc; 874 uint16_t corr_cck_x4; 875 uint16_t energy_ofdm_th; 876} __packed; 877 878/* Structures for command IWN_CMD_PHY_CALIB. */ 879struct iwn_phy_calib { 880 uint8_t code; 881#define IWN4965_PHY_CALIB_DIFF_GAIN 7 882#define IWN5000_PHY_CALIB_DC 8 883#define IWN5000_PHY_CALIB_LO 9 884#define IWN5000_PHY_CALIB_TX_IQ 11 885#define IWN5000_PHY_CALIB_CRYSTAL 15 886#define IWN5000_PHY_CALIB_BASE_BAND 16 887#define IWN5000_PHY_CALIB_TX_IQ_PERIODIC 17 888#define IWN5000_PHY_CALIB_RESET_NOISE_GAIN 18 889#define IWN5000_PHY_CALIB_NOISE_GAIN 19 890 891 uint8_t group; 892 uint8_t ngroups; 893 uint8_t isvalid; 894} __packed; 895 896struct iwn5000_phy_calib_crystal { 897 uint8_t code; 898 uint8_t group; 899 uint8_t ngroups; 900 uint8_t isvalid; 901 902 uint8_t cap_pin[2]; 903 uint8_t reserved[2]; 904} __packed; 905 906struct iwn_phy_calib_gain { 907 uint8_t code; 908 uint8_t group; 909 uint8_t ngroups; 910 uint8_t isvalid; 911 912 int8_t gain[3]; 913 uint8_t reserved; 914} __packed; 915 916/* Structure for command IWN_CMD_SPECTRUM_MEASUREMENT. */ 917struct iwn_spectrum_cmd { 918 uint16_t len; 919 uint8_t token; 920 uint8_t id; 921 uint8_t origin; 922 uint8_t periodic; 923 uint16_t timeout; 924 uint32_t start; 925 uint32_t reserved1; 926 uint32_t flags; 927 uint32_t filter; 928 uint16_t nchan; 929 uint16_t reserved2; 930 struct { 931 uint32_t duration; 932 uint8_t chan; 933 uint8_t type; 934#define IWN_MEASUREMENT_BASIC (1 << 0) 935#define IWN_MEASUREMENT_CCA (1 << 1) 936#define IWN_MEASUREMENT_RPI_HISTOGRAM (1 << 2) 937#define IWN_MEASUREMENT_NOISE_HISTOGRAM (1 << 3) 938#define IWN_MEASUREMENT_FRAME (1 << 4) 939#define IWN_MEASUREMENT_IDLE (1 << 7) 940 941 uint16_t reserved; 942 } __packed chan[10]; 943} __packed; 944 945/* Structure for IWN_UC_READY notification. */ 946#define IWN_NATTEN_GROUPS 5 947struct iwn_ucode_info { 948 uint8_t minor; 949 uint8_t major; 950 uint16_t reserved1; 951 uint8_t revision[8]; 952 uint8_t type; 953 uint8_t subtype; 954#define IWN_UCODE_RUNTIME 0 955#define IWN_UCODE_INIT 9 956 957 uint16_t reserved2; 958 uint32_t logptr; 959 uint32_t errptr; 960 uint32_t tstamp; 961 uint32_t valid; 962 963 /* The following fields are for UCODE_INIT only. */ 964 int32_t volt; 965 struct { 966 int32_t chan20MHz; 967 int32_t chan40MHz; 968 } __packed temp[4]; 969 int32_t atten[IWN_NATTEN_GROUPS][2]; 970} __packed; 971 972/* Structures for IWN_TX_DONE notification. */ 973#define IWN_TX_SUCCESS 0x00 974#define IWN_TX_FAIL 0x80 /* all failures have 0x80 set */ 975#define IWN_TX_FAIL_SHORT_LIMIT 0x82 /* too many RTS retries */ 976#define IWN_TX_FAIL_LONG_LIMIT 0x83 /* too many retries */ 977#define IWN_TX_FAIL_FIFO_UNDERRRUN 0x84 /* tx fifo not kept running */ 978#define IWN_TX_FAIL_DEST_IN_PS 0x88 /* sta found in power save */ 979#define IWN_TX_FAIL_TX_LOCKED 0x90 /* waiting to see traffic */ 980 981struct iwn4965_tx_stat { 982 uint8_t nframes; 983 uint8_t btkillcnt; 984 uint8_t rtsfailcnt; 985 uint8_t ackfailcnt; 986 uint8_t rate; 987 uint8_t rflags; 988 uint16_t xrflags; 989 uint16_t duration; 990 uint16_t reserved; 991 uint32_t power[2]; 992 uint32_t status; 993} __packed; 994 995struct iwn5000_tx_stat { 996 uint8_t nframes; 997 uint8_t btkillcnt; 998 uint8_t rtsfailcnt; 999 uint8_t ackfailcnt; 1000 uint8_t rate; 1001 uint8_t rflags; 1002 uint16_t xrflags; 1003 uint16_t duration; 1004 uint16_t reserved; 1005 uint32_t power[2]; 1006 uint32_t info; 1007 uint16_t seq; 1008 uint16_t len; 1009 uint8_t tlc; 1010 uint8_t ratid; 1011 uint8_t fc[2]; 1012 uint16_t status; 1013 uint16_t sequence; 1014} __packed; 1015 1016/* Structure for IWN_BEACON_MISSED notification. */ 1017struct iwn_beacon_missed { 1018 uint32_t consecutive; 1019 uint32_t total; 1020 uint32_t expected; 1021 uint32_t received; 1022} __packed; 1023 1024/* Structure for IWN_MPDU_RX_DONE notification. */ 1025struct iwn_rx_mpdu { 1026 uint16_t len; 1027 uint16_t reserved; 1028} __packed; 1029 1030/* Structures for IWN_RX_DONE and IWN_MPDU_RX_DONE notifications. */ 1031struct iwn4965_rx_phystat { 1032 uint16_t antenna; 1033 uint16_t agc; 1034 uint8_t rssi[6]; 1035} __packed; 1036 1037struct iwn5000_rx_phystat { 1038 uint32_t reserved1; 1039 uint32_t agc; 1040 uint16_t rssi[3]; 1041} __packed; 1042 1043struct iwn_rx_stat { 1044 uint8_t phy_len; 1045 uint8_t cfg_phy_len; 1046#define IWN_STAT_MAXLEN 20 1047 1048 uint8_t id; 1049 uint8_t reserved1; 1050 uint64_t tstamp; 1051 uint32_t beacon; 1052 uint16_t flags; 1053#define IWN_STAT_FLAG_SHPREAMBLE (1 << 2) 1054 1055 uint16_t chan; 1056 uint8_t phybuf[32]; 1057 uint8_t rate; 1058 uint8_t rflags; 1059 uint16_t xrflags; 1060 uint16_t len; 1061 uint16_t reserve3; 1062} __packed; 1063 1064#define IWN_RSSI_TO_DBM 44 1065 1066/* Structure for IWN_RX_COMPRESSED_BA notification. */ 1067struct iwn_compressed_ba { 1068 uint8_t macaddr[IEEE80211_ADDR_LEN]; 1069 uint16_t reserved; 1070 uint8_t id; 1071 uint8_t tid; 1072 uint16_t seq; 1073 uint64_t bitmap; 1074 uint16_t qid; 1075 uint16_t ssn; 1076} __packed; 1077 1078/* Structure for IWN_START_SCAN notification. */ 1079struct iwn_start_scan { 1080 uint64_t tstamp; 1081 uint32_t tbeacon; 1082 uint8_t chan; 1083 uint8_t band; 1084 uint16_t reserved; 1085 uint32_t status; 1086} __packed; 1087 1088/* Structure for IWN_STOP_SCAN notification. */ 1089struct iwn_stop_scan { 1090 uint8_t nchan; 1091 uint8_t status; 1092 uint8_t reserved; 1093 uint8_t chan; 1094 uint64_t tsf; 1095} __packed; 1096 1097/* Structure for IWN_SPECTRUM_MEASUREMENT notification. */ 1098struct iwn_spectrum_notif { 1099 uint8_t id; 1100 uint8_t token; 1101 uint8_t idx; 1102 uint8_t state; 1103#define IWN_MEASUREMENT_START 0 1104#define IWN_MEASUREMENT_STOP 1 1105 1106 uint32_t start; 1107 uint8_t band; 1108 uint8_t chan; 1109 uint8_t type; 1110 uint8_t reserved1; 1111 uint32_t cca_ofdm; 1112 uint32_t cca_cck; 1113 uint32_t cca_time; 1114 uint8_t basic; 1115 uint8_t reserved2[3]; 1116 uint32_t ofdm[8]; 1117 uint32_t cck[8]; 1118 uint32_t stop; 1119 uint32_t status; 1120#define IWN_MEASUREMENT_OK 0 1121#define IWN_MEASUREMENT_CONCURRENT 1 1122#define IWN_MEASUREMENT_CSA_CONFLICT 2 1123#define IWN_MEASUREMENT_TGH_CONFLICT 3 1124#define IWN_MEASUREMENT_STOPPED 6 1125#define IWN_MEASUREMENT_TIMEOUT 7 1126#define IWN_MEASUREMENT_FAILED 8 1127} __packed; 1128 1129/* Structures for IWN_{RX,BEACON}_STATISTICS notification. */ 1130struct iwn_rx_phy_stats { 1131 uint32_t ina; 1132 uint32_t fina; 1133 uint32_t bad_plcp; 1134 uint32_t bad_crc32; 1135 uint32_t overrun; 1136 uint32_t eoverrun; 1137 uint32_t good_crc32; 1138 uint32_t fa; 1139 uint32_t bad_fina_sync; 1140 uint32_t sfd_timeout; 1141 uint32_t fina_timeout; 1142 uint32_t no_rts_ack; 1143 uint32_t rxe_limit; 1144 uint32_t ack; 1145 uint32_t cts; 1146 uint32_t ba_resp; 1147 uint32_t dsp_kill; 1148 uint32_t bad_mh; 1149 uint32_t rssi_sum; 1150 uint32_t reserved; 1151} __packed; 1152 1153struct iwn_rx_general_stats { 1154 uint32_t bad_cts; 1155 uint32_t bad_ack; 1156 uint32_t not_bss; 1157 uint32_t filtered; 1158 uint32_t bad_chan; 1159 uint32_t beacons; 1160 uint32_t missed_beacons; 1161 uint32_t adc_saturated; /* time in 0.8us */ 1162 uint32_t ina_searched; /* time in 0.8us */ 1163 uint32_t noise[3]; 1164 uint32_t flags; 1165 uint32_t load; 1166 uint32_t fa; 1167 uint32_t rssi[3]; 1168 uint32_t energy[3]; 1169} __packed; 1170 1171struct iwn_rx_ht_phy_stats { 1172 uint32_t bad_plcp; 1173 uint32_t overrun; 1174 uint32_t eoverrun; 1175 uint32_t good_crc32; 1176 uint32_t bad_crc32; 1177 uint32_t bad_mh; 1178 uint32_t good_ampdu_crc32; 1179 uint32_t ampdu; 1180 uint32_t fragment; 1181 uint32_t reserved; 1182} __packed; 1183 1184struct iwn_rx_stats { 1185 struct iwn_rx_phy_stats ofdm; 1186 struct iwn_rx_phy_stats cck; 1187 struct iwn_rx_general_stats general; 1188 struct iwn_rx_ht_phy_stats ht; 1189} __packed; 1190 1191struct iwn_tx_stats { 1192 uint32_t preamble; 1193 uint32_t rx_detected; 1194 uint32_t bt_defer; 1195 uint32_t bt_kill; 1196 uint32_t short_len; 1197 uint32_t cts_timeout; 1198 uint32_t ack_timeout; 1199 uint32_t exp_ack; 1200 uint32_t ack; 1201 uint32_t msdu; 1202 uint32_t busrt_err1; 1203 uint32_t burst_err2; 1204 uint32_t cts_collision; 1205 uint32_t ack_collision; 1206 uint32_t ba_timeout; 1207 uint32_t ba_resched; 1208 uint32_t query_ampdu; 1209 uint32_t query; 1210 uint32_t query_ampdu_frag; 1211 uint32_t query_mismatch; 1212 uint32_t not_ready; 1213 uint32_t underrun; 1214 uint32_t bt_ht_kill; 1215 uint32_t rx_ba_resp; 1216 uint32_t reserved[2]; 1217} __packed; 1218 1219struct iwn_general_stats { 1220 uint32_t temp; 1221 uint32_t temp_m; 1222 uint32_t burst_check; 1223 uint32_t burst; 1224 uint32_t reserved1[4]; 1225 uint32_t sleep; 1226 uint32_t slot_out; 1227 uint32_t slot_idle; 1228 uint32_t ttl_tstamp; 1229 uint32_t tx_ant_a; 1230 uint32_t tx_ant_b; 1231 uint32_t exec; 1232 uint32_t probe; 1233 uint32_t reserved2[2]; 1234 uint32_t rx_enabled; 1235 uint32_t reserved3[3]; 1236} __packed; 1237 1238struct iwn_stats { 1239 uint32_t flags; 1240 struct iwn_rx_stats rx; 1241 struct iwn_tx_stats tx; 1242 struct iwn_general_stats general; 1243} __packed; 1244 1245 1246/* Firmware error dump. */ 1247struct iwn_fw_dump { 1248 uint32_t valid; 1249 uint32_t id; 1250 uint32_t pc; 1251 uint32_t branch_link[2]; 1252 uint32_t interrupt_link[2]; 1253 uint32_t error_data[2]; 1254 uint32_t src_line; 1255 uint32_t tsf; 1256 uint32_t time[2]; 1257} __packed; 1258 1259/* TLV firmware header. */ 1260struct iwn_fw_tlv_hdr { 1261 uint32_t zero; /* Always 0, to differentiate from legacy. */ 1262 uint32_t signature; 1263#define IWN_FW_SIGNATURE 0x0a4c5749 /* "IWL\n" */ 1264 1265 uint8_t descr[64]; 1266 uint32_t rev; 1267#define IWN_FW_API(x) (((x) >> 8) & 0xff) 1268 1269 uint32_t build; 1270 uint64_t altmask; 1271} __packed; 1272 1273/* TLV header. */ 1274struct iwn_fw_tlv { 1275 uint16_t type; 1276#define IWN_FW_TLV_MAIN_TEXT 1 1277#define IWN_FW_TLV_MAIN_DATA 2 1278#define IWN_FW_TLV_INIT_TEXT 3 1279#define IWN_FW_TLV_INIT_DATA 4 1280#define IWN_FW_TLV_BOOT_TEXT 5 1281#define IWN_FW_TLV_PBREQ_MAXLEN 6 1282 1283 uint16_t alt; 1284 uint32_t len; 1285} __packed; 1286 1287#define IWN4965_FW_TEXT_MAXSZ ( 96 * 1024) 1288#define IWN4965_FW_DATA_MAXSZ ( 40 * 1024) 1289#define IWN5000_FW_TEXT_MAXSZ (256 * 1024) 1290#define IWN5000_FW_DATA_MAXSZ ( 80 * 1024) 1291#define IWN_FW_BOOT_TEXT_MAXSZ 1024 1292#define IWN4965_FWSZ (IWN4965_FW_TEXT_MAXSZ + IWN4965_FW_DATA_MAXSZ) 1293#define IWN5000_FWSZ IWN5000_FW_TEXT_MAXSZ 1294 1295/* 1296 * Offsets into EEPROM. 1297 */ 1298#define IWN_EEPROM_MAC 0x015 1299#define IWN_EEPROM_RFCFG 0x048 1300#define IWN4965_EEPROM_DOMAIN 0x060 1301#define IWN4965_EEPROM_BAND1 0x063 1302#define IWN5000_EEPROM_REG 0x066 1303#define IWN5000_EEPROM_CAL 0x067 1304#define IWN4965_EEPROM_BAND2 0x072 1305#define IWN4965_EEPROM_BAND3 0x080 1306#define IWN4965_EEPROM_BAND4 0x08d 1307#define IWN4965_EEPROM_BAND5 0x099 1308#define IWN4965_EEPROM_BAND6 0x0a0 1309#define IWN4965_EEPROM_BAND7 0x0a8 1310#define IWN4965_EEPROM_MAXPOW 0x0e8 1311#define IWN4965_EEPROM_VOLTAGE 0x0e9 1312#define IWN4965_EEPROM_BANDS 0x0ea 1313/* Indirect offsets. */ 1314#define IWN5000_EEPROM_DOMAIN 0x001 1315#define IWN5000_EEPROM_BAND1 0x004 1316#define IWN5000_EEPROM_BAND2 0x013 1317#define IWN5000_EEPROM_BAND3 0x021 1318#define IWN5000_EEPROM_BAND4 0x02e 1319#define IWN5000_EEPROM_BAND5 0x03a 1320#define IWN5000_EEPROM_BAND6 0x041 1321#define IWN5000_EEPROM_BAND7 0x049 1322#define IWN6000_EEPROM_ENHINFO 0x054 1323#define IWN5000_EEPROM_CRYSTAL 0x128 1324#define IWN5000_EEPROM_TEMP 0x12a 1325#define IWN5000_EEPROM_VOLT 0x12b 1326 1327/* Possible flags for IWN_EEPROM_RFCFG. */ 1328#define IWN_RFCFG_TYPE(x) (((x) >> 0) & 0x3) 1329#define IWN_RFCFG_STEP(x) (((x) >> 2) & 0x3) 1330#define IWN_RFCFG_DASH(x) (((x) >> 4) & 0x3) 1331#define IWN_RFCFG_TXANTMSK(x) (((x) >> 8) & 0xf) 1332#define IWN_RFCFG_RXANTMSK(x) (((x) >> 12) & 0xf) 1333 1334struct iwn_eeprom_chan { 1335 uint8_t flags; 1336#define IWN_EEPROM_CHAN_VALID (1 << 0) 1337#define IWN_EEPROM_CHAN_IBSS (1 << 1) 1338#define IWN_EEPROM_CHAN_ACTIVE (1 << 3) 1339#define IWN_EEPROM_CHAN_RADAR (1 << 4) 1340 1341 int8_t maxpwr; 1342} __packed; 1343 1344struct iwn_eeprom_enhinfo { 1345 uint16_t chan; 1346 int8_t chain[3]; /* max power in half-dBm */ 1347 uint8_t reserved; 1348 int8_t mimo2; /* max power in half-dBm */ 1349 int8_t mimo3; /* max power in half-dBm */ 1350} __packed; 1351 1352struct iwn5000_eeprom_calib_hdr { 1353 uint8_t version; 1354 uint8_t pa_type; 1355 uint16_t volt; 1356} __packed; 1357 1358#define IWN_NSAMPLES 3 1359struct iwn4965_eeprom_chan_samples { 1360 uint8_t num; 1361 struct { 1362 uint8_t temp; 1363 uint8_t gain; 1364 uint8_t power; 1365 int8_t pa_det; 1366 } samples[2][IWN_NSAMPLES]; 1367} __packed; 1368 1369#define IWN_NBANDS 8 1370struct iwn4965_eeprom_band { 1371 uint8_t lo; /* low channel number */ 1372 uint8_t hi; /* high channel number */ 1373 struct iwn4965_eeprom_chan_samples chans[2]; 1374} __packed; 1375 1376/* 1377 * Offsets of channels descriptions in EEPROM. 1378 */ 1379static const uint32_t iwn4965_regulatory_bands[IWN_NBANDS] = { 1380 IWN4965_EEPROM_BAND1, 1381 IWN4965_EEPROM_BAND2, 1382 IWN4965_EEPROM_BAND3, 1383 IWN4965_EEPROM_BAND4, 1384 IWN4965_EEPROM_BAND5, 1385 IWN4965_EEPROM_BAND6, 1386 IWN4965_EEPROM_BAND7 1387}; 1388 1389static const uint32_t iwn5000_regulatory_bands[IWN_NBANDS] = { 1390 IWN5000_EEPROM_BAND1, 1391 IWN5000_EEPROM_BAND2, 1392 IWN5000_EEPROM_BAND3, 1393 IWN5000_EEPROM_BAND4, 1394 IWN5000_EEPROM_BAND5, 1395 IWN5000_EEPROM_BAND6, 1396 IWN5000_EEPROM_BAND7 1397}; 1398 1399#define IWN_CHAN_BANDS_COUNT 7 1400#define IWN_MAX_CHAN_PER_BAND 14 1401static const struct iwn_chan_band { 1402 uint8_t nchan; 1403 uint8_t chan[IWN_MAX_CHAN_PER_BAND]; 1404} iwn_bands[] = { 1405 /* 20MHz channels, 2GHz band. */ 1406 { 14, { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } }, 1407 /* 20MHz channels, 5GHz band. */ 1408 { 13, { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } }, 1409 { 12, { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } }, 1410 { 11, { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } }, 1411 { 6, { 145, 149, 153, 157, 161, 165 } }, 1412 /* 40MHz channels (primary channels), 2GHz band. */ 1413 { 7, { 1, 2, 3, 4, 5, 6, 7 } }, 1414 /* 40MHz channels (primary channels), 5GHz band. */ 1415 { 11, { 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157 } } 1416}; 1417 1418#define IWN1000_OTP_NBLOCKS 3 1419#define IWN6000_OTP_NBLOCKS 4 1420#define IWN6050_OTP_NBLOCKS 7 1421 1422/* HW rate indices. */ 1423#define IWN_RIDX_CCK1 0 1424#define IWN_RIDX_CCK11 3 1425#define IWN_RIDX_OFDM6 4 1426#define IWN_RIDX_OFDM54 11 1427 1428static const struct iwn_rate { 1429 uint8_t rate; 1430 uint8_t plcp; 1431 uint8_t flags; 1432} iwn_rates[IWN_RIDX_MAX + 1] = { 1433 { 2, 10, IWN_RFLAG_CCK }, 1434 { 4, 20, IWN_RFLAG_CCK }, 1435 { 11, 55, IWN_RFLAG_CCK }, 1436 { 22, 110, IWN_RFLAG_CCK }, 1437 { 12, 0xd, 0 }, 1438 { 18, 0xf, 0 }, 1439 { 24, 0x5, 0 }, 1440 { 36, 0x7, 0 }, 1441 { 48, 0x9, 0 }, 1442 { 72, 0xb, 0 }, 1443 { 96, 0x1, 0 }, 1444 { 108, 0x3, 0 }, 1445 { 120, 0x3, 0 } 1446}; 1447 1448#define IWN4965_MAX_PWR_INDEX 107 1449 1450/* 1451 * RF Tx gain values from highest to lowest power (values obtained from 1452 * the reference driver.) 1453 */ 1454static const uint8_t iwn4965_rf_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1455 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, 1456 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 0x39, 0x38, 1457 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 0x35, 0x35, 1458 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x31, 0x31, 1459 0x31, 0x30, 0x30, 0x30, 0x06, 0x06, 0x06, 0x05, 0x05, 0x05, 0x04, 1460 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01, 1461 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1462 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1463 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1464 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1465}; 1466 1467static const uint8_t iwn4965_rf_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1468 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 1469 0x3c, 0x3c, 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 1470 0x39, 0x38, 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 1471 0x35, 0x35, 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 1472 0x31, 0x31, 0x31, 0x30, 0x30, 0x30, 0x25, 0x25, 0x25, 0x24, 0x24, 1473 0x24, 0x23, 0x23, 0x23, 0x22, 0x18, 0x18, 0x17, 0x17, 0x17, 0x16, 1474 0x16, 0x16, 0x15, 0x15, 0x15, 0x14, 0x14, 0x14, 0x13, 0x13, 0x13, 1475 0x12, 0x08, 0x08, 0x07, 0x07, 0x07, 0x06, 0x06, 0x06, 0x05, 0x05, 1476 0x05, 0x04, 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 1477 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1478}; 1479 1480/* 1481 * DSP pre-DAC gain values from highest to lowest power (values obtained 1482 * from the reference driver.) 1483 */ 1484static const uint8_t iwn4965_dsp_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1485 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1486 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1487 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1488 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1489 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1490 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1491 0x6e, 0x68, 0x62, 0x61, 0x60, 0x5f, 0x5e, 0x5d, 0x5c, 0x5b, 0x5a, 1492 0x59, 0x58, 0x57, 0x56, 0x55, 0x54, 0x53, 0x52, 0x51, 0x50, 0x4f, 1493 0x4e, 0x4d, 0x4c, 0x4b, 0x4a, 0x49, 0x48, 0x47, 0x46, 0x45, 0x44, 1494 0x43, 0x42, 0x41, 0x40, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b 1495}; 1496 1497static const uint8_t iwn4965_dsp_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1498 0x7b, 0x75, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1499 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1500 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1501 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1502 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1503 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1504 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1505 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1506 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1507 0x68, 0x62, 0x6e, 0x68, 0x62, 0x5d, 0x58, 0x53, 0x4e 1508}; 1509 1510/* 1511 * Power saving settings (values obtained from the reference driver.) 1512 */ 1513#define IWN_NDTIMRANGES 3 1514#define IWN_NPOWERLEVELS 6 1515static const struct iwn_pmgt { 1516 uint32_t rxtimeout; 1517 uint32_t txtimeout; 1518 uint32_t intval[5]; 1519 int skip_dtim; 1520} iwn_pmgt[IWN_NDTIMRANGES][IWN_NPOWERLEVELS] = { 1521 /* DTIM <= 2 */ 1522 { 1523 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1524 { 200, 500, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 1 */ 1525 { 200, 300, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 2 */ 1526 { 50, 100, { 2, 2, 2, 2, -1 }, 0 }, /* PS level 3 */ 1527 { 50, 25, { 2, 2, 4, 4, -1 }, 1 }, /* PS level 4 */ 1528 { 25, 25, { 2, 2, 4, 6, -1 }, 2 } /* PS level 5 */ 1529 }, 1530 /* 3 <= DTIM <= 10 */ 1531 { 1532 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1533 { 200, 500, { 1, 2, 3, 4, 4 }, 0 }, /* PS level 1 */ 1534 { 200, 300, { 1, 2, 3, 4, 7 }, 0 }, /* PS level 2 */ 1535 { 50, 100, { 2, 4, 6, 7, 9 }, 0 }, /* PS level 3 */ 1536 { 50, 25, { 2, 4, 6, 9, 10 }, 1 }, /* PS level 4 */ 1537 { 25, 25, { 2, 4, 7, 10, 10 }, 2 } /* PS level 5 */ 1538 }, 1539 /* DTIM >= 11 */ 1540 { 1541 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1542 { 200, 500, { 1, 2, 3, 4, -1 }, 0 }, /* PS level 1 */ 1543 { 200, 300, { 2, 4, 6, 7, -1 }, 0 }, /* PS level 2 */ 1544 { 50, 100, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 3 */ 1545 { 50, 25, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 4 */ 1546 { 25, 25, { 4, 7, 10, 10, -1 }, 0 } /* PS level 5 */ 1547 } 1548}; 1549 1550struct iwn_sensitivity_limits { 1551 uint32_t min_ofdm_x1; 1552 uint32_t max_ofdm_x1; 1553 uint32_t min_ofdm_mrc_x1; 1554 uint32_t max_ofdm_mrc_x1; 1555 uint32_t min_ofdm_x4; 1556 uint32_t max_ofdm_x4; 1557 uint32_t min_ofdm_mrc_x4; 1558 uint32_t max_ofdm_mrc_x4; 1559 uint32_t min_cck_x4; 1560 uint32_t max_cck_x4; 1561 uint32_t min_cck_mrc_x4; 1562 uint32_t max_cck_mrc_x4; 1563 uint32_t min_energy_cck; 1564 uint32_t energy_cck; 1565 uint32_t energy_ofdm; 1566}; 1567 1568/* 1569 * RX sensitivity limits (values obtained from the reference driver.) 1570 */ 1571static const struct iwn_sensitivity_limits iwn4965_sensitivity_limits = { 1572 105, 140, 1573 220, 270, 1574 85, 120, 1575 170, 210, 1576 125, 200, 1577 200, 400, 1578 97, 1579 100, 1580 100 1581}; 1582 1583static const struct iwn_sensitivity_limits iwn5000_sensitivity_limits = { 1584 120, 120, /* min = max for performance bug in DSP. */ 1585 240, 240, /* min = max for performance bug in DSP. */ 1586 90, 120, 1587 170, 210, 1588 125, 200, 1589 170, 400, 1590 95, 1591 95, 1592 95 1593}; 1594 1595static const struct iwn_sensitivity_limits iwn5150_sensitivity_limits = { 1596 105, 105, /* min = max for performance bug in DSP. */ 1597 220, 220, /* min = max for performance bug in DSP. */ 1598 90, 120, 1599 170, 210, 1600 125, 200, 1601 170, 400, 1602 95, 1603 95, 1604 95 1605}; 1606 1607static const struct iwn_sensitivity_limits iwn1000_sensitivity_limits = { 1608 120, 155, 1609 240, 290, 1610 90, 120, 1611 170, 210, 1612 125, 200, 1613 170, 400, 1614 95, 1615 95, 1616 95 1617}; 1618 1619static const struct iwn_sensitivity_limits iwn6000_sensitivity_limits = { 1620 105, 110, 1621 192, 232, 1622 80, 145, 1623 128, 232, 1624 125, 175, 1625 160, 310, 1626 97, 1627 97, 1628 100 1629}; 1630 1631/* Map TID to TX scheduler's FIFO. */ 1632static const uint8_t iwn_tid2fifo[] = { 1633 1, 0, 0, 1, 2, 2, 3, 3, 7, 7, 7, 7, 7, 7, 7, 7, 3 1634}; 1635 1636/* WiFi/WiMAX coexist event priority table for 6050. */ 1637static const struct iwn5000_wimax_event iwn6050_wimax_events[] = { 1638 { 0x04, 0x03, 0x00, 0x00 }, 1639 { 0x04, 0x03, 0x00, 0x03 }, 1640 { 0x04, 0x03, 0x00, 0x03 }, 1641 { 0x04, 0x03, 0x00, 0x03 }, 1642 { 0x04, 0x03, 0x00, 0x00 }, 1643 { 0x04, 0x03, 0x00, 0x07 }, 1644 { 0x04, 0x03, 0x00, 0x00 }, 1645 { 0x04, 0x03, 0x00, 0x03 }, 1646 { 0x04, 0x03, 0x00, 0x03 }, 1647 { 0x04, 0x03, 0x00, 0x00 }, 1648 { 0x06, 0x03, 0x00, 0x07 }, 1649 { 0x04, 0x03, 0x00, 0x00 }, 1650 { 0x06, 0x06, 0x00, 0x03 }, 1651 { 0x04, 0x03, 0x00, 0x07 }, 1652 { 0x04, 0x03, 0x00, 0x00 }, 1653 { 0x04, 0x03, 0x00, 0x00 } 1654}; 1655 1656/* Firmware errors. */ 1657static const char * const iwn_fw_errmsg[] = { 1658 "OK", 1659 "FAIL", 1660 "BAD_PARAM", 1661 "BAD_CHECKSUM", 1662 "NMI_INTERRUPT_WDG", 1663 "SYSASSERT", 1664 "FATAL_ERROR", 1665 "BAD_COMMAND", 1666 "HW_ERROR_TUNE_LOCK", 1667 "HW_ERROR_TEMPERATURE", 1668 "ILLEGAL_CHAN_FREQ", 1669 "VCC_NOT_STABLE", 1670 "FH_ERROR", 1671 "NMI_INTERRUPT_HOST", 1672 "NMI_INTERRUPT_ACTION_PT", 1673 "NMI_INTERRUPT_UNKNOWN", 1674 "UCODE_VERSION_MISMATCH", 1675 "HW_ERROR_ABS_LOCK", 1676 "HW_ERROR_CAL_LOCK_FAIL", 1677 "NMI_INTERRUPT_INST_ACTION_PT", 1678 "NMI_INTERRUPT_DATA_ACTION_PT", 1679 "NMI_TRM_HW_ER", 1680 "NMI_INTERRUPT_TRM", 1681 "NMI_INTERRUPT_BREAKPOINT" 1682 "DEBUG_0", 1683 "DEBUG_1", 1684 "DEBUG_2", 1685 "DEBUG_3", 1686 "ADVANCED_SYSASSERT" 1687}; 1688 1689/* Find least significant bit that is set. */ 1690#define IWN_LSB(x) ((((x) - 1) & (x)) ^ (x)) 1691 1692#define IWN_READ(sc, reg) \ 1693 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 1694 1695#define IWN_WRITE(sc, reg, val) \ 1696 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 1697 1698#define IWN_WRITE_1(sc, reg, val) \ 1699 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 1700 1701#define IWN_SETBITS(sc, reg, mask) \ 1702 IWN_WRITE(sc, reg, IWN_READ(sc, reg) | (mask)) 1703 1704#define IWN_CLRBITS(sc, reg, mask) \ 1705 IWN_WRITE(sc, reg, IWN_READ(sc, reg) & ~(mask)) 1706 1707#define IWN_BARRIER_WRITE(sc) \ 1708 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 1709 BUS_SPACE_BARRIER_WRITE) 1710 1711#define IWN_BARRIER_READ_WRITE(sc) \ 1712 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 1713 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 1714