1178676Ssam/* $FreeBSD$ */ 2210111Sbschmidt/* $OpenBSD: if_iwnreg.h,v 1.40 2010/05/05 19:41:57 damien Exp $ */ 3178676Ssam 4178676Ssam/*- 5198429Srpaulo * Copyright (c) 2007, 2008 6178676Ssam * Damien Bergamini <damien.bergamini@free.fr> 7178676Ssam * 8178676Ssam * Permission to use, copy, modify, and distribute this software for any 9178676Ssam * purpose with or without fee is hereby granted, provided that the above 10178676Ssam * copyright notice and this permission notice appear in all copies. 11178676Ssam * 12178676Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13178676Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14178676Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15178676Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16178676Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17178676Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18178676Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19178676Ssam */ 20178676Ssam 21253898Sadrian#define IWN_CT_KILL_THRESHOLD 114 /* in Celsius */ 22253898Sadrian#define IWN_CT_KILL_EXIT_THRESHOLD 95 /* in Celsius */ 23253898Sadrian 24178676Ssam#define IWN_TX_RING_COUNT 256 25198429Srpaulo#define IWN_TX_RING_LOMARK 192 26198429Srpaulo#define IWN_TX_RING_HIMARK 224 27198429Srpaulo#define IWN_RX_RING_COUNT_LOG 6 28198429Srpaulo#define IWN_RX_RING_COUNT (1 << IWN_RX_RING_COUNT_LOG) 29178676Ssam 30198429Srpaulo#define IWN4965_NTXQUEUES 16 31198429Srpaulo#define IWN5000_NTXQUEUES 20 32178676Ssam 33221651Sbschmidt#define IWN4965_FIRSTAGGQUEUE 7 34221651Sbschmidt#define IWN5000_FIRSTAGGQUEUE 10 35221651Sbschmidt 36198429Srpaulo#define IWN4965_NDMACHNLS 7 37198429Srpaulo#define IWN5000_NDMACHNLS 8 38178676Ssam 39198429Srpaulo#define IWN_SRVC_DMACHNL 9 40198429Srpaulo 41201209Srpaulo#define IWN_ICT_SIZE 4096 42201209Srpaulo#define IWN_ICT_COUNT (IWN_ICT_SIZE / sizeof (uint32_t)) 43201209Srpaulo 44253898Sadrian/* For cards with PAN command, default is IWN_CMD_QUEUE_NUM */ 45253898Sadrian#define IWN_CMD_QUEUE_NUM 4 46253898Sadrian#define IWN_PAN_CMD_QUEUE 9 47253898Sadrian 48198429Srpaulo/* Maximum number of DMA segments for TX. */ 49178676Ssam#define IWN_MAX_SCATTER 20 50178676Ssam 51198429Srpaulo/* RX buffers must be large enough to hold a full 4K A-MPDU. */ 52178676Ssam#define IWN_RBUF_SIZE (4 * 1024) 53178676Ssam 54198429Srpaulo#if defined(__LP64__) 55198429Srpaulo/* HW supports 36-bit DMA addresses. */ 56198429Srpaulo#define IWN_LOADDR(paddr) ((uint32_t)(paddr)) 57198429Srpaulo#define IWN_HIADDR(paddr) (((paddr) >> 32) & 0xf) 58198429Srpaulo#else 59198429Srpaulo#define IWN_LOADDR(paddr) (paddr) 60198429Srpaulo#define IWN_HIADDR(paddr) (0) 61198429Srpaulo#endif 62198429Srpaulo 63178676Ssam/* 64178676Ssam * Control and status registers. 65178676Ssam */ 66198429Srpaulo#define IWN_HW_IF_CONFIG 0x000 67198429Srpaulo#define IWN_INT_COALESCING 0x004 68201209Srpaulo#define IWN_INT_PERIODIC 0x005 /* use IWN_WRITE_1 */ 69198429Srpaulo#define IWN_INT 0x008 70201209Srpaulo#define IWN_INT_MASK 0x00c 71198429Srpaulo#define IWN_FH_INT 0x010 72253866Sadrian#define IWN_GPIO_IN 0x018 /* read external chip pins */ 73178676Ssam#define IWN_RESET 0x020 74198429Srpaulo#define IWN_GP_CNTRL 0x024 75198429Srpaulo#define IWN_HW_REV 0x028 76198429Srpaulo#define IWN_EEPROM 0x02c 77198429Srpaulo#define IWN_EEPROM_GP 0x030 78198429Srpaulo#define IWN_OTP_GP 0x034 79198429Srpaulo#define IWN_GIO 0x03c 80253866Sadrian#define IWN_GP_UCODE 0x048 81201209Srpaulo#define IWN_GP_DRIVER 0x050 82253866Sadrian#define IWN_UCODE_GP1 0x054 83253866Sadrian#define IWN_UCODE_GP1_SET 0x058 84198429Srpaulo#define IWN_UCODE_GP1_CLR 0x05c 85253866Sadrian#define IWN_UCODE_GP2 0x060 86198429Srpaulo#define IWN_LED 0x094 87201209Srpaulo#define IWN_DRAM_INT_TBL 0x0a0 88220729Sbschmidt#define IWN_SHADOW_REG_CTRL 0x0a8 89198429Srpaulo#define IWN_GIO_CHICKEN 0x100 90198429Srpaulo#define IWN_ANA_PLL 0x20c 91201209Srpaulo#define IWN_HW_REV_WA 0x22c 92198429Srpaulo#define IWN_DBG_HPET_MEM 0x240 93201209Srpaulo#define IWN_DBG_LINK_PWR_MGMT 0x250 94253866Sadrian/* Need nic_lock for use above */ 95198429Srpaulo#define IWN_MEM_RADDR 0x40c 96178676Ssam#define IWN_MEM_WADDR 0x410 97178676Ssam#define IWN_MEM_WDATA 0x418 98198429Srpaulo#define IWN_MEM_RDATA 0x41c 99253898Sadrian#define IWN_TARG_MBX_C 0x430 100220726Sbschmidt#define IWN_PRPH_WADDR 0x444 101220726Sbschmidt#define IWN_PRPH_RADDR 0x448 102220726Sbschmidt#define IWN_PRPH_WDATA 0x44c 103220726Sbschmidt#define IWN_PRPH_RDATA 0x450 104198429Srpaulo#define IWN_HBUS_TARG_WRPTR 0x460 105178676Ssam 106198429Srpaulo/* 107198429Srpaulo * Flow-Handler registers. 108198429Srpaulo */ 109198429Srpaulo#define IWN_FH_TFBD_CTRL0(qid) (0x1900 + (qid) * 8) 110198429Srpaulo#define IWN_FH_TFBD_CTRL1(qid) (0x1904 + (qid) * 8) 111198429Srpaulo#define IWN_FH_KW_ADDR 0x197c 112198429Srpaulo#define IWN_FH_SRAM_ADDR(qid) (0x19a4 + (qid) * 4) 113198429Srpaulo#define IWN_FH_CBBC_QUEUE(qid) (0x19d0 + (qid) * 4) 114198429Srpaulo#define IWN_FH_STATUS_WPTR 0x1bc0 115198429Srpaulo#define IWN_FH_RX_BASE 0x1bc4 116198429Srpaulo#define IWN_FH_RX_WPTR 0x1bc8 117198429Srpaulo#define IWN_FH_RX_CONFIG 0x1c00 118198429Srpaulo#define IWN_FH_RX_STATUS 0x1c44 119198429Srpaulo#define IWN_FH_TX_CONFIG(qid) (0x1d00 + (qid) * 32) 120198429Srpaulo#define IWN_FH_TXBUF_STATUS(qid) (0x1d08 + (qid) * 32) 121198429Srpaulo#define IWN_FH_TX_CHICKEN 0x1e98 122198429Srpaulo#define IWN_FH_TX_STATUS 0x1eb0 123178676Ssam 124198429Srpaulo/* 125198429Srpaulo * TX scheduler registers. 126198429Srpaulo */ 127198429Srpaulo#define IWN_SCHED_BASE 0xa02c00 128198429Srpaulo#define IWN_SCHED_SRAM_ADDR (IWN_SCHED_BASE + 0x000) 129198429Srpaulo#define IWN5000_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x008) 130198429Srpaulo#define IWN4965_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x010) 131198429Srpaulo#define IWN5000_SCHED_TXFACT (IWN_SCHED_BASE + 0x010) 132198429Srpaulo#define IWN4965_SCHED_TXFACT (IWN_SCHED_BASE + 0x01c) 133198429Srpaulo#define IWN4965_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x064 + (qid) * 4) 134198429Srpaulo#define IWN5000_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x068 + (qid) * 4) 135198429Srpaulo#define IWN4965_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0d0) 136198429Srpaulo#define IWN4965_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x0e4) 137198429Srpaulo#define IWN5000_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0e8) 138198429Srpaulo#define IWN4965_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x104 + (qid) * 4) 139198429Srpaulo#define IWN5000_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x108) 140198429Srpaulo#define IWN5000_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x10c + (qid) * 4) 141198429Srpaulo#define IWN5000_SCHED_AGGR_SEL (IWN_SCHED_BASE + 0x248) 142178676Ssam 143178676Ssam/* 144198429Srpaulo * Offsets in TX scheduler's SRAM. 145198429Srpaulo */ 146198429Srpaulo#define IWN4965_SCHED_CTX_OFF 0x380 147198429Srpaulo#define IWN4965_SCHED_CTX_LEN 416 148198429Srpaulo#define IWN4965_SCHED_QUEUE_OFFSET(qid) (0x380 + (qid) * 8) 149198429Srpaulo#define IWN4965_SCHED_TRANS_TBL(qid) (0x500 + (qid) * 2) 150198429Srpaulo#define IWN5000_SCHED_CTX_OFF 0x600 151198429Srpaulo#define IWN5000_SCHED_CTX_LEN 520 152198429Srpaulo#define IWN5000_SCHED_QUEUE_OFFSET(qid) (0x600 + (qid) * 8) 153198429Srpaulo#define IWN5000_SCHED_TRANS_TBL(qid) (0x7e0 + (qid) * 2) 154198429Srpaulo 155198429Srpaulo/* 156178676Ssam * NIC internal memory offsets. 157178676Ssam */ 158201209Srpaulo#define IWN_APMG_CLK_CTRL 0x3000 159201209Srpaulo#define IWN_APMG_CLK_EN 0x3004 160198429Srpaulo#define IWN_APMG_CLK_DIS 0x3008 161198429Srpaulo#define IWN_APMG_PS 0x300c 162201209Srpaulo#define IWN_APMG_DIGITAL_SVR 0x3058 163201209Srpaulo#define IWN_APMG_ANALOG_SVR 0x306c 164198429Srpaulo#define IWN_APMG_PCI_STT 0x3010 165198429Srpaulo#define IWN_BSM_WR_CTRL 0x3400 166198429Srpaulo#define IWN_BSM_WR_MEM_SRC 0x3404 167198429Srpaulo#define IWN_BSM_WR_MEM_DST 0x3408 168198429Srpaulo#define IWN_BSM_WR_DWCOUNT 0x340c 169198429Srpaulo#define IWN_BSM_DRAM_TEXT_ADDR 0x3490 170198429Srpaulo#define IWN_BSM_DRAM_TEXT_SIZE 0x3494 171198429Srpaulo#define IWN_BSM_DRAM_DATA_ADDR 0x3498 172198429Srpaulo#define IWN_BSM_DRAM_DATA_SIZE 0x349c 173198429Srpaulo#define IWN_BSM_SRAM_BASE 0x3800 174178676Ssam 175198429Srpaulo/* Possible flags for register IWN_HW_IF_CONFIG. */ 176198429Srpaulo#define IWN_HW_IF_CONFIG_4965_R (1 << 4) 177198429Srpaulo#define IWN_HW_IF_CONFIG_MAC_SI (1 << 8) 178198429Srpaulo#define IWN_HW_IF_CONFIG_RADIO_SI (1 << 9) 179198429Srpaulo#define IWN_HW_IF_CONFIG_EEPROM_LOCKED (1 << 21) 180198429Srpaulo#define IWN_HW_IF_CONFIG_NIC_READY (1 << 22) 181198429Srpaulo#define IWN_HW_IF_CONFIG_HAP_WAKE_L1A (1 << 23) 182198429Srpaulo#define IWN_HW_IF_CONFIG_PREPARE_DONE (1 << 25) 183198429Srpaulo#define IWN_HW_IF_CONFIG_PREPARE (1 << 27) 184178676Ssam 185201209Srpaulo/* Possible values for register IWN_INT_PERIODIC. */ 186201209Srpaulo#define IWN_INT_PERIODIC_DIS 0x00 187201209Srpaulo#define IWN_INT_PERIODIC_ENA 0xff 188201209Srpaulo 189198429Srpaulo/* Possible flags for registers IWN_PRPH_RADDR/IWN_PRPH_WADDR. */ 190198429Srpaulo#define IWN_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24) 191178676Ssam 192198429Srpaulo/* Possible values for IWN_BSM_WR_MEM_DST. */ 193198429Srpaulo#define IWN_FW_TEXT_BASE 0x00000000 194198429Srpaulo#define IWN_FW_DATA_BASE 0x00800000 195178676Ssam 196198429Srpaulo/* Possible flags for register IWN_RESET. */ 197198429Srpaulo#define IWN_RESET_NEVO (1 << 0) 198198429Srpaulo#define IWN_RESET_SW (1 << 7) 199198429Srpaulo#define IWN_RESET_MASTER_DISABLED (1 << 8) 200198429Srpaulo#define IWN_RESET_STOP_MASTER (1 << 9) 201261455Seadler#define IWN_RESET_LINK_PWR_MGMT_DIS (1U << 31) 202178676Ssam 203198429Srpaulo/* Possible flags for register IWN_GP_CNTRL. */ 204198429Srpaulo#define IWN_GP_CNTRL_MAC_ACCESS_ENA (1 << 0) 205198429Srpaulo#define IWN_GP_CNTRL_MAC_CLOCK_READY (1 << 0) 206198429Srpaulo#define IWN_GP_CNTRL_INIT_DONE (1 << 2) 207198429Srpaulo#define IWN_GP_CNTRL_MAC_ACCESS_REQ (1 << 3) 208198429Srpaulo#define IWN_GP_CNTRL_SLEEP (1 << 4) 209198429Srpaulo#define IWN_GP_CNTRL_RFKILL (1 << 27) 210178676Ssam 211198429Srpaulo/* Possible flags for register IWN_GIO_CHICKEN. */ 212198429Srpaulo#define IWN_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23) 213198429Srpaulo#define IWN_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29) 214178676Ssam 215198429Srpaulo/* Possible flags for register IWN_GIO. */ 216198429Srpaulo#define IWN_GIO_L0S_ENA (1 << 1) 217178676Ssam 218201209Srpaulo/* Possible flags for register IWN_GP_DRIVER. */ 219201209Srpaulo#define IWN_GP_DRIVER_RADIO_3X3_HYB (0 << 0) 220201209Srpaulo#define IWN_GP_DRIVER_RADIO_2X2_HYB (1 << 0) 221201209Srpaulo#define IWN_GP_DRIVER_RADIO_2X2_IPA (2 << 0) 222206444Sbschmidt#define IWN_GP_DRIVER_CALIB_VER6 (1 << 2) 223220729Sbschmidt#define IWN_GP_DRIVER_6050_1X2 (1 << 3) 224253898Sadrian#define IWN_GP_DRIVER_REG_BIT_RADIO_IQ_INVERT (1 << 7) 225201209Srpaulo 226198429Srpaulo/* Possible flags for register IWN_UCODE_GP1_CLR. */ 227198429Srpaulo#define IWN_UCODE_GP1_RFKILL (1 << 1) 228198429Srpaulo#define IWN_UCODE_GP1_CMD_BLOCKED (1 << 2) 229198429Srpaulo#define IWN_UCODE_GP1_CTEMP_STOP_RF (1 << 3) 230253898Sadrian#define IWN_UCODE_GP1_CFG_COMPLETE (1 << 5) 231178676Ssam 232198429Srpaulo/* Possible flags/values for register IWN_LED. */ 233198429Srpaulo#define IWN_LED_BSM_CTRL (1 << 5) 234198429Srpaulo#define IWN_LED_OFF 0x00000038 235198429Srpaulo#define IWN_LED_ON 0x00000078 236178676Ssam 237253898Sadrian#define IWN_MAX_BLINK_TBL 10 238253898Sadrian#define IWN_LED_STATIC_ON 0 239253898Sadrian#define IWN_LED_STATIC_OFF 1 240253898Sadrian#define IWN_LED_SLOW_BLINK 2 241253898Sadrian#define IWN_LED_INT_BLINK 3 242253898Sadrian#define IWN_LED_UNIT 0x1388 /* 5 ms */ 243253898Sadrian 244253898Sadrianstatic const struct { 245253898Sadrian uint16_t tpt; /* Mb/s */ 246253898Sadrian uint8_t on_time; 247253898Sadrian uint8_t off_time; 248253898Sadrian} blink_tbl[] = 249253898Sadrian{ 250253898Sadrian {300, 5, 5}, 251253898Sadrian {200, 8, 8}, 252253898Sadrian {100, 11, 11}, 253253898Sadrian {70, 13, 13}, 254253898Sadrian {50, 15, 15}, 255253898Sadrian {20, 17, 17}, 256253898Sadrian {10, 19, 19}, 257253898Sadrian {5, 22, 22}, 258253898Sadrian {1, 26, 26}, 259253898Sadrian {0, 33, 33}, 260253898Sadrian /* SOLID_ON */ 261253898Sadrian}; 262253898Sadrian 263201209Srpaulo/* Possible flags for register IWN_DRAM_INT_TBL. */ 264201209Srpaulo#define IWN_DRAM_INT_TBL_WRAP_CHECK (1 << 27) 265261455Seadler#define IWN_DRAM_INT_TBL_ENABLE (1U << 31) 266201209Srpaulo 267198429Srpaulo/* Possible values for register IWN_ANA_PLL. */ 268198429Srpaulo#define IWN_ANA_PLL_INIT 0x00880300 269178676Ssam 270198429Srpaulo/* Possible flags for register IWN_FH_RX_STATUS. */ 271198429Srpaulo#define IWN_FH_RX_STATUS_IDLE (1 << 24) 272178676Ssam 273198429Srpaulo/* Possible flags for register IWN_BSM_WR_CTRL. */ 274198429Srpaulo#define IWN_BSM_WR_CTRL_START_EN (1 << 30) 275261455Seadler#define IWN_BSM_WR_CTRL_START (1U << 31) 276178676Ssam 277198429Srpaulo/* Possible flags for register IWN_INT. */ 278198429Srpaulo#define IWN_INT_ALIVE (1 << 0) 279198429Srpaulo#define IWN_INT_WAKEUP (1 << 1) 280198429Srpaulo#define IWN_INT_SW_RX (1 << 3) 281198429Srpaulo#define IWN_INT_CT_REACHED (1 << 6) 282198429Srpaulo#define IWN_INT_RF_TOGGLED (1 << 7) 283198429Srpaulo#define IWN_INT_SW_ERR (1 << 25) 284201209Srpaulo#define IWN_INT_SCHED (1 << 26) 285198429Srpaulo#define IWN_INT_FH_TX (1 << 27) 286201209Srpaulo#define IWN_INT_RX_PERIODIC (1 << 28) 287198429Srpaulo#define IWN_INT_HW_ERR (1 << 29) 288261455Seadler#define IWN_INT_FH_RX (1U << 31) 289178676Ssam 290198429Srpaulo/* Shortcut. */ 291201209Srpaulo#define IWN_INT_MASK_DEF \ 292198429Srpaulo (IWN_INT_SW_ERR | IWN_INT_HW_ERR | IWN_INT_FH_TX | \ 293198429Srpaulo IWN_INT_FH_RX | IWN_INT_ALIVE | IWN_INT_WAKEUP | \ 294198429Srpaulo IWN_INT_SW_RX | IWN_INT_CT_REACHED | IWN_INT_RF_TOGGLED) 295178676Ssam 296198429Srpaulo/* Possible flags for register IWN_FH_INT. */ 297198429Srpaulo#define IWN_FH_INT_TX_CHNL(x) (1 << (x)) 298198429Srpaulo#define IWN_FH_INT_RX_CHNL(x) (1 << ((x) + 16)) 299198429Srpaulo#define IWN_FH_INT_HI_PRIOR (1 << 30) 300198429Srpaulo/* Shortcuts for the above. */ 301198429Srpaulo#define IWN_FH_INT_TX \ 302198429Srpaulo (IWN_FH_INT_TX_CHNL(0) | IWN_FH_INT_TX_CHNL(1)) 303198429Srpaulo#define IWN_FH_INT_RX \ 304198429Srpaulo (IWN_FH_INT_RX_CHNL(0) | IWN_FH_INT_RX_CHNL(1) | IWN_FH_INT_HI_PRIOR) 305178676Ssam 306198429Srpaulo/* Possible flags/values for register IWN_FH_TX_CONFIG. */ 307198429Srpaulo#define IWN_FH_TX_CONFIG_DMA_PAUSE 0 308261455Seadler#define IWN_FH_TX_CONFIG_DMA_ENA (1U << 31) 309198429Srpaulo#define IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD (1 << 20) 310178676Ssam 311198429Srpaulo/* Possible flags/values for register IWN_FH_TXBUF_STATUS. */ 312198429Srpaulo#define IWN_FH_TXBUF_STATUS_TBNUM(x) ((x) << 20) 313198429Srpaulo#define IWN_FH_TXBUF_STATUS_TBIDX(x) ((x) << 12) 314198429Srpaulo#define IWN_FH_TXBUF_STATUS_TFBD_VALID 3 315198429Srpaulo 316198429Srpaulo/* Possible flags for register IWN_FH_TX_CHICKEN. */ 317198429Srpaulo#define IWN_FH_TX_CHICKEN_SCHED_RETRY (1 << 1) 318198429Srpaulo 319198429Srpaulo/* Possible flags for register IWN_FH_TX_STATUS. */ 320220659Sbschmidt#define IWN_FH_TX_STATUS_IDLE(chnl) (1 << ((chnl) + 16)) 321198429Srpaulo 322198429Srpaulo/* Possible flags for register IWN_FH_RX_CONFIG. */ 323261455Seadler#define IWN_FH_RX_CONFIG_ENA (1U << 31) 324198429Srpaulo#define IWN_FH_RX_CONFIG_NRBD(x) ((x) << 20) 325198429Srpaulo#define IWN_FH_RX_CONFIG_RB_SIZE_8K (1 << 16) 326198429Srpaulo#define IWN_FH_RX_CONFIG_SINGLE_FRAME (1 << 15) 327198429Srpaulo#define IWN_FH_RX_CONFIG_IRQ_DST_HOST (1 << 12) 328198429Srpaulo#define IWN_FH_RX_CONFIG_RB_TIMEOUT(x) ((x) << 4) 329198429Srpaulo#define IWN_FH_RX_CONFIG_IGN_RXF_EMPTY (1 << 2) 330198429Srpaulo 331198429Srpaulo/* Possible flags for register IWN_FH_TX_CONFIG. */ 332261455Seadler#define IWN_FH_TX_CONFIG_DMA_ENA (1U << 31) 333198429Srpaulo#define IWN_FH_TX_CONFIG_DMA_CREDIT_ENA (1 << 3) 334198429Srpaulo 335198429Srpaulo/* Possible flags for register IWN_EEPROM. */ 336198429Srpaulo#define IWN_EEPROM_READ_VALID (1 << 0) 337198429Srpaulo#define IWN_EEPROM_CMD (1 << 1) 338198429Srpaulo 339198429Srpaulo/* Possible flags for register IWN_EEPROM_GP. */ 340198429Srpaulo#define IWN_EEPROM_GP_IF_OWNER 0x00000180 341198429Srpaulo 342198429Srpaulo/* Possible flags for register IWN_OTP_GP. */ 343198429Srpaulo#define IWN_OTP_GP_DEV_SEL_OTP (1 << 16) 344198429Srpaulo#define IWN_OTP_GP_RELATIVE_ACCESS (1 << 17) 345198429Srpaulo#define IWN_OTP_GP_ECC_CORR_STTS (1 << 20) 346198429Srpaulo#define IWN_OTP_GP_ECC_UNCORR_STTS (1 << 21) 347198429Srpaulo 348198429Srpaulo/* Possible flags for register IWN_SCHED_QUEUE_STATUS. */ 349198429Srpaulo#define IWN4965_TXQ_STATUS_ACTIVE 0x0007fc01 350198429Srpaulo#define IWN4965_TXQ_STATUS_INACTIVE 0x0007fc00 351198429Srpaulo#define IWN4965_TXQ_STATUS_AGGR_ENA (1 << 5 | 1 << 8) 352198429Srpaulo#define IWN4965_TXQ_STATUS_CHGACT (1 << 10) 353198429Srpaulo#define IWN5000_TXQ_STATUS_ACTIVE 0x00ff0018 354198429Srpaulo#define IWN5000_TXQ_STATUS_INACTIVE 0x00ff0010 355198429Srpaulo#define IWN5000_TXQ_STATUS_CHGACT (1 << 19) 356198429Srpaulo 357201209Srpaulo/* Possible flags for registers IWN_APMG_CLK_*. */ 358198429Srpaulo#define IWN_APMG_CLK_CTRL_DMA_CLK_RQT (1 << 9) 359198429Srpaulo#define IWN_APMG_CLK_CTRL_BSM_CLK_RQT (1 << 11) 360198429Srpaulo 361198429Srpaulo/* Possible flags for register IWN_APMG_PS. */ 362198429Srpaulo#define IWN_APMG_PS_EARLY_PWROFF_DIS (1 << 22) 363198429Srpaulo#define IWN_APMG_PS_PWR_SRC(x) ((x) << 24) 364198429Srpaulo#define IWN_APMG_PS_PWR_SRC_VMAIN 0 365198429Srpaulo#define IWN_APMG_PS_PWR_SRC_VAUX 2 366198429Srpaulo#define IWN_APMG_PS_PWR_SRC_MASK IWN_APMG_PS_PWR_SRC(3) 367198429Srpaulo#define IWN_APMG_PS_RESET_REQ (1 << 26) 368198429Srpaulo 369201209Srpaulo/* Possible flags for register IWN_APMG_DIGITAL_SVR. */ 370201209Srpaulo#define IWN_APMG_DIGITAL_SVR_VOLTAGE(x) (((x) & 0xf) << 5) 371201209Srpaulo#define IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK \ 372201209Srpaulo IWN_APMG_DIGITAL_SVR_VOLTAGE(0xf) 373201209Srpaulo#define IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32 \ 374201209Srpaulo IWN_APMG_DIGITAL_SVR_VOLTAGE(3) 375201209Srpaulo 376198429Srpaulo/* Possible flags for IWN_APMG_PCI_STT. */ 377198429Srpaulo#define IWN_APMG_PCI_STT_L1A_DIS (1 << 11) 378198429Srpaulo 379198429Srpaulo/* Possible flags for register IWN_BSM_DRAM_TEXT_SIZE. */ 380261455Seadler#define IWN_FW_UPDATED (1U << 31) 381178676Ssam 382198429Srpaulo#define IWN_SCHED_WINSZ 64 383198429Srpaulo#define IWN_SCHED_LIMIT 64 384198429Srpaulo#define IWN4965_SCHED_COUNT 512 385198429Srpaulo#define IWN5000_SCHED_COUNT (IWN_TX_RING_COUNT + IWN_SCHED_WINSZ) 386198429Srpaulo#define IWN4965_SCHEDSZ (IWN4965_NTXQUEUES * IWN4965_SCHED_COUNT * 2) 387198429Srpaulo#define IWN5000_SCHEDSZ (IWN5000_NTXQUEUES * IWN5000_SCHED_COUNT * 2) 388178676Ssam 389198429Srpaulostruct iwn_tx_desc { 390198429Srpaulo uint8_t reserved1[3]; 391198429Srpaulo uint8_t nsegs; 392198429Srpaulo struct { 393198429Srpaulo uint32_t addr; 394198429Srpaulo uint16_t len; 395198429Srpaulo } __packed segs[IWN_MAX_SCATTER]; 396198429Srpaulo /* Pad to 128 bytes. */ 397198429Srpaulo uint32_t reserved2; 398198429Srpaulo} __packed; 399178676Ssam 400198429Srpaulostruct iwn_rx_status { 401178676Ssam uint16_t closed_count; 402178676Ssam uint16_t closed_rx_count; 403178676Ssam uint16_t finished_count; 404178676Ssam uint16_t finished_rx_count; 405178676Ssam uint32_t reserved[2]; 406178676Ssam} __packed; 407178676Ssam 408178676Ssamstruct iwn_rx_desc { 409253898Sadrian /* 410253898Sadrian * The first 4 bytes of the RX frame header contain both the RX frame 411253898Sadrian * size and some flags. 412253898Sadrian * Bit fields: 413253898Sadrian * 31: flag flush RB request 414253898Sadrian * 30: flag ignore TC (terminal counter) request 415253898Sadrian * 29: flag fast IRQ request 416253898Sadrian * 28-14: Reserved 417253898Sadrian * 13-00: RX frame size 418253898Sadrian */ 419178676Ssam uint32_t len; 420178676Ssam uint8_t type; 421198429Srpaulo#define IWN_UC_READY 1 422198429Srpaulo#define IWN_ADD_NODE_DONE 24 423198429Srpaulo#define IWN_TX_DONE 28 424253898Sadrian#define IWN_REPLY_LED_CMD 72 425198429Srpaulo#define IWN5000_CALIBRATION_RESULT 102 426198429Srpaulo#define IWN5000_CALIBRATION_DONE 103 427198429Srpaulo#define IWN_START_SCAN 130 428253898Sadrian#define IWN_NOTIF_SCAN_RESULT 131 429198429Srpaulo#define IWN_STOP_SCAN 132 430198429Srpaulo#define IWN_RX_STATISTICS 156 431198429Srpaulo#define IWN_BEACON_STATISTICS 157 432198429Srpaulo#define IWN_STATE_CHANGED 161 433198429Srpaulo#define IWN_BEACON_MISSED 162 434198429Srpaulo#define IWN_RX_PHY 192 435198429Srpaulo#define IWN_MPDU_RX_DONE 193 436198429Srpaulo#define IWN_RX_DONE 195 437201209Srpaulo#define IWN_RX_COMPRESSED_BA 197 438178676Ssam 439253898Sadrian uint8_t flags; /* 0:5 reserved, 6 abort, 7 internal */ 440253898Sadrian uint8_t idx; /* position within TX queue */ 441178676Ssam uint8_t qid; 442253898Sadrian /* 0:4 TX queue id - 5:6 reserved - 7 unsolicited RX 443253898Sadrian * or uCode-originated notification 444253898Sadrian */ 445178676Ssam} __packed; 446178676Ssam 447253898Sadrian#define IWN_RX_DESC_QID_MSK 0x1F 448253898Sadrian#define IWN_UNSOLICITED_RX_NOTIF 0x80 449253898Sadrian 450253898Sadrian/* CARD_STATE_NOTIFICATION */ 451253898Sadrian#define IWN_STATE_CHANGE_HW_CARD_DISABLED 0x01 452253898Sadrian#define IWN_STATE_CHANGE_SW_CARD_DISABLED 0x02 453253898Sadrian#define IWN_STATE_CHANGE_CT_CARD_DISABLED 0x04 454253898Sadrian#define IWN_STATE_CHANGE_RXON_CARD_DISABLED 0x10 455253898Sadrian 456198429Srpaulo/* Possible RX status flags. */ 457198429Srpaulo#define IWN_RX_NO_CRC_ERR (1 << 0) 458198429Srpaulo#define IWN_RX_NO_OVFL_ERR (1 << 1) 459198429Srpaulo/* Shortcut for the above. */ 460178676Ssam#define IWN_RX_NOERROR (IWN_RX_NO_CRC_ERR | IWN_RX_NO_OVFL_ERR) 461198429Srpaulo#define IWN_RX_MPDU_MIC_OK (1 << 6) 462198429Srpaulo#define IWN_RX_CIPHER_MASK (7 << 8) 463198429Srpaulo#define IWN_RX_CIPHER_CCMP (2 << 8) 464198429Srpaulo#define IWN_RX_MPDU_DEC (1 << 11) 465198429Srpaulo#define IWN_RX_DECRYPT_MASK (3 << 11) 466198429Srpaulo#define IWN_RX_DECRYPT_OK (3 << 11) 467178676Ssam 468178676Ssamstruct iwn_tx_cmd { 469178676Ssam uint8_t code; 470201209Srpaulo#define IWN_CMD_RXON 16 471201209Srpaulo#define IWN_CMD_RXON_ASSOC 17 472198429Srpaulo#define IWN_CMD_EDCA_PARAMS 19 473198429Srpaulo#define IWN_CMD_TIMING 20 474198429Srpaulo#define IWN_CMD_ADD_NODE 24 475198429Srpaulo#define IWN_CMD_TX_DATA 28 476198429Srpaulo#define IWN_CMD_LINK_QUALITY 78 477198429Srpaulo#define IWN_CMD_SET_LED 72 478198429Srpaulo#define IWN5000_CMD_WIMAX_COEX 90 479253898Sadrian#define IWN_TEMP_NOTIFICATION 98 480198429Srpaulo#define IWN5000_CMD_CALIB_CONFIG 101 481202986Srpaulo#define IWN5000_CMD_CALIB_RESULT 102 482202986Srpaulo#define IWN5000_CMD_CALIB_COMPLETE 103 483198429Srpaulo#define IWN_CMD_SET_POWER_MODE 119 484198429Srpaulo#define IWN_CMD_SCAN 128 485202986Srpaulo#define IWN_CMD_SCAN_RESULTS 131 486201209Srpaulo#define IWN_CMD_TXPOWER_DBM 149 487198429Srpaulo#define IWN_CMD_TXPOWER 151 488201209Srpaulo#define IWN5000_CMD_TX_ANT_CONFIG 152 489198429Srpaulo#define IWN_CMD_BT_COEX 155 490198429Srpaulo#define IWN_CMD_GET_STATISTICS 156 491198429Srpaulo#define IWN_CMD_SET_CRITICAL_TEMP 164 492198429Srpaulo#define IWN_CMD_SET_SENSITIVITY 168 493198429Srpaulo#define IWN_CMD_PHY_CALIB 176 494220891Sbschmidt#define IWN_CMD_BT_COEX_PRIOTABLE 204 495220891Sbschmidt#define IWN_CMD_BT_COEX_PROT 205 496253898Sadrian#define IWN_CMD_BT_COEX_NOTIF 206 497253898Sadrian/* PAN commands */ 498253898Sadrian#define IWN_CMD_WIPAN_PARAMS 0xb2 499253898Sadrian#define IWN_CMD_WIPAN_RXON 0xb3 500253898Sadrian#define IWN_CMD_WIPAN_RXON_TIMING 0xb4 501253898Sadrian#define IWN_CMD_WIPAN_RXON_ASSOC 0xb6 502253898Sadrian#define IWN_CMD_WIPAN_QOS_PARAM 0xb7 503253898Sadrian#define IWN_CMD_WIPAN_WEPKEY 0xb8 504253898Sadrian#define IWN_CMD_WIPAN_P2P_CHANNEL_SWITCH 0xb9 505253898Sadrian#define IWN_CMD_WIPAN_NOA_NOTIFICATION 0xbc 506253898Sadrian#define IWN_CMD_WIPAN_DEACTIVATION_COMPLETE 0xbd 507198429Srpaulo 508178676Ssam uint8_t flags; 509178676Ssam uint8_t idx; 510178676Ssam uint8_t qid; 511178676Ssam uint8_t data[136]; 512178676Ssam} __packed; 513178676Ssam 514253898Sadrian/* 515253898Sadrian * Structure for IWN_CMD_GET_STATISTICS = (0x9c) 156 516253898Sadrian * all devices identical. 517253898Sadrian * 518253898Sadrian * This command triggers an immediate response containing uCode statistics. 519253898Sadrian * The response is in the same format as IWN_BEACON_STATISTICS (0x9d) 157. 520253898Sadrian * 521253898Sadrian * If the CLEAR_STATS configuration flag is set, uCode will clear its 522253898Sadrian * internal copy of the statistics (counters) after issuing the response. 523253898Sadrian * This flag does not affect IWN_BEACON_STATISTICS after beacons (see below). 524253898Sadrian * 525253898Sadrian * If the DISABLE_NOTIF configuration flag is set, uCode will not issue 526253898Sadrian * IWN_BEACON_STATISTICS after received beacons. This flag 527253898Sadrian * does not affect the response to the IWN_CMD_GET_STATISTICS 0x9c itself. 528253898Sadrian */ 529253898Sadrianstruct iwn_statistics_cmd { 530253898Sadrian uint32_t configuration_flags; 531253898Sadrian#define IWN_STATS_CONF_CLEAR_STATS htole32(0x1) 532253898Sadrian#define IWN_STATS_CONF_DISABLE_NOTIF htole32(0x2) 533253898Sadrian} __packed; 534253898Sadrian 535198429Srpaulo/* Antenna flags, used in various commands. */ 536198429Srpaulo#define IWN_ANT_A (1 << 0) 537198429Srpaulo#define IWN_ANT_B (1 << 1) 538198429Srpaulo#define IWN_ANT_C (1 << 2) 539201209Srpaulo/* Shortcuts. */ 540201209Srpaulo#define IWN_ANT_AB (IWN_ANT_A | IWN_ANT_B) 541201209Srpaulo#define IWN_ANT_BC (IWN_ANT_B | IWN_ANT_C) 542253898Sadrian#define IWN_ANT_AC (IWN_ANT_A | IWN_ANT_C) 543198429Srpaulo#define IWN_ANT_ABC (IWN_ANT_A | IWN_ANT_B | IWN_ANT_C) 544198429Srpaulo 545201209Srpaulo/* Structure for command IWN_CMD_RXON. */ 546198429Srpaulostruct iwn_rxon { 547178676Ssam uint8_t myaddr[IEEE80211_ADDR_LEN]; 548178676Ssam uint16_t reserved1; 549178676Ssam uint8_t bssid[IEEE80211_ADDR_LEN]; 550178676Ssam uint16_t reserved2; 551178676Ssam uint8_t wlap[IEEE80211_ADDR_LEN]; 552178676Ssam uint16_t reserved3; 553178676Ssam uint8_t mode; 554178676Ssam#define IWN_MODE_HOSTAP 1 555178676Ssam#define IWN_MODE_STA 3 556178676Ssam#define IWN_MODE_IBSS 4 557178676Ssam#define IWN_MODE_MONITOR 6 558253898Sadrian#define IWN_MODE_2STA 8 559253898Sadrian#define IWN_MODE_P2P 9 560198429Srpaulo 561198429Srpaulo uint8_t air; 562178676Ssam uint16_t rxchain; 563201209Srpaulo#define IWN_RXCHAIN_DRIVER_FORCE (1 << 0) 564201209Srpaulo#define IWN_RXCHAIN_VALID(x) (((x) & IWN_ANT_ABC) << 1) 565201209Srpaulo#define IWN_RXCHAIN_FORCE_SEL(x) (((x) & IWN_ANT_ABC) << 4) 566201209Srpaulo#define IWN_RXCHAIN_FORCE_MIMO_SEL(x) (((x) & IWN_ANT_ABC) << 7) 567198429Srpaulo#define IWN_RXCHAIN_IDLE_COUNT(x) ((x) << 10) 568198429Srpaulo#define IWN_RXCHAIN_MIMO_COUNT(x) ((x) << 12) 569198429Srpaulo#define IWN_RXCHAIN_MIMO_FORCE (1 << 14) 570198429Srpaulo 571198429Srpaulo uint8_t ofdm_mask; 572198429Srpaulo uint8_t cck_mask; 573178676Ssam uint16_t associd; 574178676Ssam uint32_t flags; 575201209Srpaulo#define IWN_RXON_24GHZ (1 << 0) 576201209Srpaulo#define IWN_RXON_CCK (1 << 1) 577201209Srpaulo#define IWN_RXON_AUTO (1 << 2) 578201209Srpaulo#define IWN_RXON_SHSLOT (1 << 4) 579201209Srpaulo#define IWN_RXON_SHPREAMBLE (1 << 5) 580201209Srpaulo#define IWN_RXON_NODIVERSITY (1 << 7) 581201209Srpaulo#define IWN_RXON_ANTENNA_A (1 << 8) 582201209Srpaulo#define IWN_RXON_ANTENNA_B (1 << 9) 583201209Srpaulo#define IWN_RXON_TSF (1 << 15) 584221653Sbschmidt#define IWN_RXON_HT_HT40MINUS (1 << 22) 585221653Sbschmidt#define IWN_RXON_HT_PROTMODE(x) (x << 23) 586221653Sbschmidt#define IWN_RXON_HT_MODEPURE40 (1 << 25) 587221653Sbschmidt#define IWN_RXON_HT_MODEMIXED (2 << 25) 588201209Srpaulo#define IWN_RXON_CTS_TO_SELF (1 << 30) 589198429Srpaulo 590178676Ssam uint32_t filter; 591198429Srpaulo#define IWN_FILTER_PROMISC (1 << 0) 592198429Srpaulo#define IWN_FILTER_CTL (1 << 1) 593198429Srpaulo#define IWN_FILTER_MULTICAST (1 << 2) 594198429Srpaulo#define IWN_FILTER_NODECRYPT (1 << 3) 595198429Srpaulo#define IWN_FILTER_BSS (1 << 5) 596198429Srpaulo#define IWN_FILTER_BEACON (1 << 6) 597198429Srpaulo 598198429Srpaulo uint8_t chan; 599198429Srpaulo uint8_t reserved4; 600198429Srpaulo uint8_t ht_single_mask; 601198429Srpaulo uint8_t ht_dual_mask; 602201209Srpaulo /* The following fields are for >=5000 Series only. */ 603198429Srpaulo uint8_t ht_triple_mask; 604198429Srpaulo uint8_t reserved5; 605198429Srpaulo uint16_t acquisition; 606198429Srpaulo uint16_t reserved6; 607178676Ssam} __packed; 608178676Ssam 609198429Srpaulo#define IWN4965_RXONSZ (sizeof (struct iwn_rxon) - 6) 610198429Srpaulo#define IWN5000_RXONSZ (sizeof (struct iwn_rxon)) 611198429Srpaulo 612198429Srpaulo/* Structure for command IWN_CMD_ASSOCIATE. */ 613178676Ssamstruct iwn_assoc { 614178676Ssam uint32_t flags; 615178676Ssam uint32_t filter; 616178676Ssam uint8_t ofdm_mask; 617178676Ssam uint8_t cck_mask; 618178676Ssam uint16_t reserved; 619178676Ssam} __packed; 620178676Ssam 621198429Srpaulo/* Structure for command IWN_CMD_EDCA_PARAMS. */ 622178676Ssamstruct iwn_edca_params { 623178676Ssam uint32_t flags; 624178676Ssam#define IWN_EDCA_UPDATE (1 << 0) 625178676Ssam#define IWN_EDCA_TXOP (1 << 4) 626178676Ssam 627178676Ssam struct { 628178676Ssam uint16_t cwmin; 629178676Ssam uint16_t cwmax; 630178676Ssam uint8_t aifsn; 631178676Ssam uint8_t reserved; 632178676Ssam uint16_t txoplimit; 633201209Srpaulo } __packed ac[WME_NUM_AC]; 634178676Ssam} __packed; 635178676Ssam 636198429Srpaulo/* Structure for command IWN_CMD_TIMING. */ 637198429Srpaulostruct iwn_cmd_timing { 638178676Ssam uint64_t tstamp; 639178676Ssam uint16_t bintval; 640178676Ssam uint16_t atim; 641178676Ssam uint32_t binitval; 642178676Ssam uint16_t lintval; 643253898Sadrian uint8_t dtim_period; 644253898Sadrian uint8_t delta_cp_bss_tbtts; 645178676Ssam} __packed; 646178676Ssam 647198429Srpaulo/* Structure for command IWN_CMD_ADD_NODE. */ 648178676Ssamstruct iwn_node_info { 649178676Ssam uint8_t control; 650178676Ssam#define IWN_NODE_UPDATE (1 << 0) 651198429Srpaulo 652178676Ssam uint8_t reserved1[3]; 653198429Srpaulo 654178676Ssam uint8_t macaddr[IEEE80211_ADDR_LEN]; 655178676Ssam uint16_t reserved2; 656178676Ssam uint8_t id; 657178676Ssam#define IWN_ID_BSS 0 658253898Sadrian#define IWN_STA_ID 1 659253898Sadrian 660253898Sadrian#define IWN_PAN_ID_BCAST 14 661198429Srpaulo#define IWN5000_ID_BROADCAST 15 662198429Srpaulo#define IWN4965_ID_BROADCAST 31 663198429Srpaulo 664178676Ssam uint8_t flags; 665198429Srpaulo#define IWN_FLAG_SET_KEY (1 << 0) 666198429Srpaulo#define IWN_FLAG_SET_DISABLE_TID (1 << 1) 667198429Srpaulo#define IWN_FLAG_SET_TXRATE (1 << 2) 668198429Srpaulo#define IWN_FLAG_SET_ADDBA (1 << 3) 669198429Srpaulo#define IWN_FLAG_SET_DELBA (1 << 4) 670198429Srpaulo 671178676Ssam uint16_t reserved3; 672198429Srpaulo uint16_t kflags; 673198429Srpaulo#define IWN_KFLAG_CCMP (1 << 1) 674198429Srpaulo#define IWN_KFLAG_MAP (1 << 3) 675198429Srpaulo#define IWN_KFLAG_KID(kid) ((kid) << 8) 676198429Srpaulo#define IWN_KFLAG_INVALID (1 << 11) 677198429Srpaulo#define IWN_KFLAG_GROUP (1 << 14) 678198429Srpaulo 679178676Ssam uint8_t tsc2; /* TKIP TSC2 */ 680178676Ssam uint8_t reserved4; 681178676Ssam uint16_t ttak[5]; 682198429Srpaulo uint8_t kid; 683198429Srpaulo uint8_t reserved5; 684198429Srpaulo uint8_t key[16]; 685198429Srpaulo /* The following 3 fields are for 5000 Series only. */ 686198429Srpaulo uint64_t tsc; 687198429Srpaulo uint8_t rxmic[8]; 688198429Srpaulo uint8_t txmic[8]; 689198429Srpaulo 690178676Ssam uint32_t htflags; 691221653Sbschmidt#define IWN_SMPS_MIMO_PROT (1 << 17) 692198429Srpaulo#define IWN_AMDPU_SIZE_FACTOR(x) ((x) << 19) 693221653Sbschmidt#define IWN_NODE_HT40 (1 << 21) 694221653Sbschmidt#define IWN_SMPS_MIMO_DIS (1 << 22) 695198429Srpaulo#define IWN_AMDPU_DENSITY(x) ((x) << 23) 696198429Srpaulo 697178676Ssam uint32_t mask; 698198429Srpaulo uint16_t disable_tid; 699198429Srpaulo uint16_t reserved6; 700198429Srpaulo uint8_t addba_tid; 701198429Srpaulo uint8_t delba_tid; 702198429Srpaulo uint16_t addba_ssn; 703198429Srpaulo uint32_t reserved7; 704198429Srpaulo} __packed; 705198429Srpaulo 706198429Srpaulostruct iwn4965_node_info { 707198429Srpaulo uint8_t control; 708198429Srpaulo uint8_t reserved1[3]; 709198429Srpaulo uint8_t macaddr[IEEE80211_ADDR_LEN]; 710198429Srpaulo uint16_t reserved2; 711198429Srpaulo uint8_t id; 712198429Srpaulo uint8_t flags; 713198429Srpaulo uint16_t reserved3; 714198429Srpaulo uint16_t kflags; 715198429Srpaulo uint8_t tsc2; /* TKIP TSC2 */ 716198429Srpaulo uint8_t reserved4; 717198429Srpaulo uint16_t ttak[5]; 718198429Srpaulo uint8_t kid; 719198429Srpaulo uint8_t reserved5; 720198429Srpaulo uint8_t key[16]; 721198429Srpaulo uint32_t htflags; 722198429Srpaulo uint32_t mask; 723198429Srpaulo uint16_t disable_tid; 724198429Srpaulo uint16_t reserved6; 725198429Srpaulo uint8_t addba_tid; 726198429Srpaulo uint8_t delba_tid; 727198429Srpaulo uint16_t addba_ssn; 728198429Srpaulo uint32_t reserved7; 729198429Srpaulo} __packed; 730198429Srpaulo 731221649Sbschmidt#define IWN_RFLAG_MCS (1 << 8) 732221648Sbschmidt#define IWN_RFLAG_CCK (1 << 9) 733221649Sbschmidt#define IWN_RFLAG_GREENFIELD (1 << 10) 734221649Sbschmidt#define IWN_RFLAG_HT40 (1 << 11) 735221649Sbschmidt#define IWN_RFLAG_DUPLICATE (1 << 12) 736221649Sbschmidt#define IWN_RFLAG_SGI (1 << 13) 737221648Sbschmidt#define IWN_RFLAG_ANT(x) ((x) << 14) 738178676Ssam 739198429Srpaulo/* Structure for command IWN_CMD_TX_DATA. */ 740178676Ssamstruct iwn_cmd_data { 741178676Ssam uint16_t len; 742178676Ssam uint16_t lnext; 743178676Ssam uint32_t flags; 744198429Srpaulo#define IWN_TX_NEED_PROTECTION (1 << 0) /* 5000 only */ 745178676Ssam#define IWN_TX_NEED_RTS (1 << 1) 746178676Ssam#define IWN_TX_NEED_CTS (1 << 2) 747178676Ssam#define IWN_TX_NEED_ACK (1 << 3) 748198429Srpaulo#define IWN_TX_LINKQ (1 << 4) 749198429Srpaulo#define IWN_TX_IMM_BA (1 << 6) 750178676Ssam#define IWN_TX_FULL_TXOP (1 << 7) 751178676Ssam#define IWN_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */ 752178676Ssam#define IWN_TX_AUTO_SEQ (1 << 13) 753198429Srpaulo#define IWN_TX_MORE_FRAG (1 << 14) 754178676Ssam#define IWN_TX_INSERT_TSTAMP (1 << 16) 755178676Ssam#define IWN_TX_NEED_PADDING (1 << 20) 756178676Ssam 757198429Srpaulo uint32_t scratch; 758221648Sbschmidt uint32_t rate; 759198429Srpaulo 760178676Ssam uint8_t id; 761178676Ssam uint8_t security; 762178676Ssam#define IWN_CIPHER_WEP40 1 763178676Ssam#define IWN_CIPHER_CCMP 2 764178676Ssam#define IWN_CIPHER_TKIP 3 765178676Ssam#define IWN_CIPHER_WEP104 9 766178676Ssam 767198429Srpaulo uint8_t linkq; 768178676Ssam uint8_t reserved2; 769198429Srpaulo uint8_t key[16]; 770178676Ssam uint16_t fnext; 771178676Ssam uint16_t reserved3; 772178676Ssam uint32_t lifetime; 773178676Ssam#define IWN_LIFETIME_INFINITE 0xffffffff 774178676Ssam 775178676Ssam uint32_t loaddr; 776178676Ssam uint8_t hiaddr; 777178676Ssam uint8_t rts_ntries; 778178676Ssam uint8_t data_ntries; 779178676Ssam uint8_t tid; 780178676Ssam uint16_t timeout; 781178676Ssam uint16_t txop; 782178676Ssam} __packed; 783178676Ssam 784198429Srpaulo/* Structure for command IWN_CMD_LINK_QUALITY. */ 785178676Ssam#define IWN_MAX_TX_RETRIES 16 786178676Ssamstruct iwn_cmd_link_quality { 787178676Ssam uint8_t id; 788178676Ssam uint8_t reserved1; 789178676Ssam uint16_t ctl; 790178676Ssam uint8_t flags; 791198429Srpaulo uint8_t mimo; 792198429Srpaulo uint8_t antmsk_1stream; 793198429Srpaulo uint8_t antmsk_2stream; 794201209Srpaulo uint8_t ridx[WME_NUM_AC]; 795198429Srpaulo uint16_t ampdu_limit; 796198429Srpaulo uint8_t ampdu_threshold; 797198429Srpaulo uint8_t ampdu_max; 798178676Ssam uint32_t reserved2; 799221648Sbschmidt uint32_t retry[IWN_MAX_TX_RETRIES]; 800178676Ssam uint32_t reserved3; 801178676Ssam} __packed; 802178676Ssam 803198429Srpaulo/* Structure for command IWN_CMD_SET_LED. */ 804178676Ssamstruct iwn_cmd_led { 805178676Ssam uint32_t unit; /* multiplier (in usecs) */ 806178676Ssam uint8_t which; 807178676Ssam#define IWN_LED_ACTIVITY 1 808178676Ssam#define IWN_LED_LINK 2 809178676Ssam 810178676Ssam uint8_t off; 811178676Ssam uint8_t on; 812178676Ssam uint8_t reserved; 813178676Ssam} __packed; 814178676Ssam 815198429Srpaulo/* Structure for command IWN5000_CMD_WIMAX_COEX. */ 816198429Srpaulostruct iwn5000_wimax_coex { 817198429Srpaulo uint32_t flags; 818201209Srpaulo#define IWN_WIMAX_COEX_STA_TABLE_VALID (1 << 0) 819201209Srpaulo#define IWN_WIMAX_COEX_UNASSOC_WA_UNMASK (1 << 2) 820201209Srpaulo#define IWN_WIMAX_COEX_ASSOC_WA_UNMASK (1 << 3) 821201209Srpaulo#define IWN_WIMAX_COEX_ENABLE (1 << 7) 822201209Srpaulo 823201209Srpaulo struct iwn5000_wimax_event { 824198429Srpaulo uint8_t request; 825198429Srpaulo uint8_t window; 826198429Srpaulo uint8_t reserved; 827198429Srpaulo uint8_t flags; 828198429Srpaulo } __packed events[16]; 829198429Srpaulo} __packed; 830198429Srpaulo 831198429Srpaulo/* Structures for command IWN5000_CMD_CALIB_CONFIG. */ 832198429Srpaulostruct iwn5000_calib_elem { 833198429Srpaulo uint32_t enable; 834198429Srpaulo uint32_t start; 835227805Sbschmidt#define IWN5000_CALIB_DC (1 << 1) 836227805Sbschmidt 837198429Srpaulo uint32_t send; 838198429Srpaulo uint32_t apply; 839198429Srpaulo uint32_t reserved; 840198429Srpaulo} __packed; 841198429Srpaulo 842198429Srpaulostruct iwn5000_calib_status { 843198429Srpaulo struct iwn5000_calib_elem once; 844198429Srpaulo struct iwn5000_calib_elem perd; 845198429Srpaulo uint32_t flags; 846198429Srpaulo} __packed; 847198429Srpaulo 848198429Srpaulostruct iwn5000_calib_config { 849198429Srpaulo struct iwn5000_calib_status ucode; 850198429Srpaulo struct iwn5000_calib_status driver; 851198429Srpaulo uint32_t reserved; 852198429Srpaulo} __packed; 853198429Srpaulo 854198429Srpaulo/* Structure for command IWN_CMD_SET_POWER_MODE. */ 855198429Srpaulostruct iwn_pmgt_cmd { 856178676Ssam uint16_t flags; 857198429Srpaulo#define IWN_PS_ALLOW_SLEEP (1 << 0) 858198429Srpaulo#define IWN_PS_NOTIFY (1 << 1) 859198429Srpaulo#define IWN_PS_SLEEP_OVER_DTIM (1 << 2) 860198429Srpaulo#define IWN_PS_PCI_PMGT (1 << 3) 861198429Srpaulo#define IWN_PS_FAST_PD (1 << 4) 862253898Sadrian#define IWN_PS_BEACON_FILTERING (1 << 5) 863253898Sadrian#define IWN_PS_SHADOW_REG (1 << 6) 864253898Sadrian#define IWN_PS_CT_KILL (1 << 7) 865253898Sadrian#define IWN_PS_BT_SCD (1 << 8) 866253898Sadrian#define IWN_PS_ADVANCED_PM (1 << 9) 867178676Ssam 868198429Srpaulo uint8_t keepalive; 869178676Ssam uint8_t debug; 870198429Srpaulo uint32_t rxtimeout; 871198429Srpaulo uint32_t txtimeout; 872198429Srpaulo uint32_t intval[5]; 873178676Ssam uint32_t beacons; 874178676Ssam} __packed; 875178676Ssam 876198429Srpaulo/* Structures for command IWN_CMD_SCAN. */ 877178676Ssamstruct iwn_scan_essid { 878178676Ssam uint8_t id; 879178676Ssam uint8_t len; 880178676Ssam uint8_t data[IEEE80211_NWID_LEN]; 881178676Ssam} __packed; 882178676Ssam 883178676Ssamstruct iwn_scan_hdr { 884178676Ssam uint16_t len; 885178676Ssam uint8_t reserved1; 886178676Ssam uint8_t nchan; 887198429Srpaulo uint16_t quiet_time; 888198429Srpaulo uint16_t quiet_threshold; 889178676Ssam uint16_t crc_threshold; 890178676Ssam uint16_t rxchain; 891178676Ssam uint32_t max_svc; /* background scans */ 892178676Ssam uint32_t pause_svc; /* background scans */ 893178676Ssam uint32_t flags; 894178676Ssam uint32_t filter; 895178676Ssam 896198429Srpaulo /* Followed by a struct iwn_cmd_data. */ 897198429Srpaulo /* Followed by an array of 20 structs iwn_scan_essid. */ 898198429Srpaulo /* Followed by probe request body. */ 899198429Srpaulo /* Followed by an array of ``nchan'' structs iwn_scan_chan. */ 900178676Ssam} __packed; 901178676Ssam 902178676Ssamstruct iwn_scan_chan { 903198429Srpaulo uint32_t flags; 904253898Sadrian#define IWN_CHAN_PASSIVE (0 << 0) 905198429Srpaulo#define IWN_CHAN_ACTIVE (1 << 0) 906198429Srpaulo#define IWN_CHAN_NPBREQS(x) (((1 << (x)) - 1) << 1) 907178676Ssam 908198429Srpaulo uint16_t chan; 909178676Ssam uint8_t rf_gain; 910178676Ssam uint8_t dsp_gain; 911178676Ssam uint16_t active; /* msecs */ 912178676Ssam uint16_t passive; /* msecs */ 913178676Ssam} __packed; 914178676Ssam 915253898Sadrian#define IWN_SCAN_CRC_TH_DISABLED 0 916253898Sadrian#define IWN_SCAN_CRC_TH_DEFAULT htole16(1) 917253898Sadrian#define IWN_SCAN_CRC_TH_NEVER htole16(0xffff) 918253898Sadrian 919198429Srpaulo/* Maximum size of a scan command. */ 920198429Srpaulo#define IWN_SCAN_MAXSZ (MCLBYTES - 4) 921198429Srpaulo 922253898Sadrian#define IWN_ACTIVE_DWELL_TIME_24 (30) /* all times in msec */ 923253898Sadrian#define IWN_ACTIVE_DWELL_TIME_52 (20) 924253898Sadrian#define IWN_ACTIVE_DWELL_FACTOR_24 (3) 925253898Sadrian#define IWN_ACTIVE_DWELL_FACTOR_52 (2) 926253898Sadrian 927253898Sadrian#define IWN_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */ 928253898Sadrian#define IWN_PASSIVE_DWELL_TIME_52 (10) 929253898Sadrian#define IWN_PASSIVE_DWELL_BASE (100) 930253898Sadrian#define IWN_CHANNEL_TUNE_TIME (5) 931253898Sadrian 932253898Sadrian#define IWN_SCAN_CHAN_TIMEOUT 2 933253898Sadrian 934198429Srpaulo/* Structure for command IWN_CMD_TXPOWER (4965AGN only.) */ 935178676Ssam#define IWN_RIDX_MAX 32 936198429Srpaulostruct iwn4965_cmd_txpower { 937198429Srpaulo uint8_t band; 938198429Srpaulo uint8_t reserved1; 939198429Srpaulo uint8_t chan; 940198429Srpaulo uint8_t reserved2; 941178676Ssam struct { 942198429Srpaulo uint8_t rf_gain[2]; 943198429Srpaulo uint8_t dsp_gain[2]; 944198429Srpaulo } __packed power[IWN_RIDX_MAX + 1]; 945178676Ssam} __packed; 946178676Ssam 947198429Srpaulo/* Structure for command IWN_CMD_TXPOWER_DBM (5000 Series only.) */ 948198429Srpaulostruct iwn5000_cmd_txpower { 949198429Srpaulo int8_t global_limit; /* in half-dBm */ 950198429Srpaulo#define IWN5000_TXPOWER_AUTO 0x7f 951198429Srpaulo#define IWN5000_TXPOWER_MAX_DBM 16 952198429Srpaulo 953198429Srpaulo uint8_t flags; 954198429Srpaulo#define IWN5000_TXPOWER_NO_CLOSED (1 << 6) 955198429Srpaulo 956198429Srpaulo int8_t srv_limit; /* in half-dBm */ 957198429Srpaulo uint8_t reserved; 958198429Srpaulo} __packed; 959198429Srpaulo 960220891Sbschmidt/* Structures for command IWN_CMD_BLUETOOTH. */ 961178676Ssamstruct iwn_bluetooth { 962178676Ssam uint8_t flags; 963206444Sbschmidt#define IWN_BT_COEX_CHAN_ANN (1 << 0) 964206444Sbschmidt#define IWN_BT_COEX_BT_PRIO (1 << 1) 965206444Sbschmidt#define IWN_BT_COEX_2_WIRE (1 << 2) 966201209Srpaulo 967201209Srpaulo uint8_t lead_time; 968201209Srpaulo#define IWN_BT_LEAD_TIME_DEF 30 969201209Srpaulo 970201209Srpaulo uint8_t max_kill; 971201209Srpaulo#define IWN_BT_MAX_KILL_DEF 5 972201209Srpaulo 973178676Ssam uint8_t reserved; 974201209Srpaulo uint32_t kill_ack; 975201209Srpaulo uint32_t kill_cts; 976178676Ssam} __packed; 977178676Ssam 978220891Sbschmidtstruct iwn6000_btcoex_config { 979220891Sbschmidt uint8_t flags; 980253898Sadrian#define IWN_BT_FLAG_COEX6000_CHAN_INHIBITION 1 981253898Sadrian#define IWN_BT_FLAG_COEX6000_MODE_MASK ((1 << 3) | (1 << 4) | (1 << 5 )) 982253898Sadrian#define IWN_BT_FLAG_COEX6000_MODE_SHIFT 3 983253898Sadrian#define IWN_BT_FLAG_COEX6000_MODE_DISABLED 0 984253898Sadrian#define IWN_BT_FLAG_COEX6000_MODE_LEGACY_2W 1 985253898Sadrian#define IWN_BT_FLAG_COEX6000_MODE_3W 2 986253898Sadrian#define IWN_BT_FLAG_COEX6000_MODE_4W 3 987253898Sadrian 988253898Sadrian#define IWN_BT_FLAG_UCODE_DEFAULT (1 << 6) 989253898Sadrian#define IWN_BT_FLAG_SYNC_2_BT_DISABLE (1 << 7) 990220891Sbschmidt uint8_t lead_time; 991220891Sbschmidt uint8_t max_kill; 992220891Sbschmidt uint8_t bt3_t7_timer; 993220891Sbschmidt uint32_t kill_ack; 994220891Sbschmidt uint32_t kill_cts; 995220891Sbschmidt uint8_t sample_time; 996220891Sbschmidt uint8_t bt3_t2_timer; 997220891Sbschmidt uint16_t bt4_reaction; 998220891Sbschmidt uint32_t lookup_table[12]; 999220891Sbschmidt uint16_t bt4_decision; 1000220891Sbschmidt uint16_t valid; 1001220891Sbschmidt uint8_t prio_boost; 1002220891Sbschmidt uint8_t tx_prio_boost; 1003220891Sbschmidt uint16_t rx_prio_boost; 1004220891Sbschmidt} __packed; 1005220891Sbschmidt 1006253898Sadrian/* Structure for enhanced command IWN_CMD_BLUETOOTH for 2000 Series. */ 1007253898Sadrianstruct iwn2000_btcoex_config { 1008253898Sadrian uint8_t flags; /* Cf Flags in iwn6000_btcoex_config */ 1009253898Sadrian uint8_t lead_time; 1010253898Sadrian uint8_t max_kill; 1011253898Sadrian uint8_t bt3_t7_timer; 1012253898Sadrian uint32_t kill_ack; 1013253898Sadrian uint32_t kill_cts; 1014253898Sadrian uint8_t sample_time; 1015253898Sadrian uint8_t bt3_t2_timer; 1016253898Sadrian uint16_t bt4_reaction; 1017253898Sadrian uint32_t lookup_table[12]; 1018253898Sadrian uint16_t bt4_decision; 1019253898Sadrian uint16_t valid; 1020253898Sadrian 1021253898Sadrian uint32_t prio_boost; /* size change prior to iwn6000_btcoex_config */ 1022253898Sadrian uint8_t reserved; /* added prior to iwn6000_btcoex_config */ 1023253898Sadrian 1024253898Sadrian uint8_t tx_prio_boost; 1025253898Sadrian uint16_t rx_prio_boost; 1026253898Sadrian} __packed; 1027253898Sadrian 1028220891Sbschmidtstruct iwn_btcoex_priotable { 1029220891Sbschmidt uint8_t calib_init1; 1030220891Sbschmidt uint8_t calib_init2; 1031220891Sbschmidt uint8_t calib_periodic_low1; 1032220891Sbschmidt uint8_t calib_periodic_low2; 1033220891Sbschmidt uint8_t calib_periodic_high1; 1034220891Sbschmidt uint8_t calib_periodic_high2; 1035220891Sbschmidt uint8_t dtim; 1036220891Sbschmidt uint8_t scan52; 1037220891Sbschmidt uint8_t scan24; 1038220891Sbschmidt uint8_t reserved[7]; 1039220891Sbschmidt} __packed; 1040220891Sbschmidt 1041220891Sbschmidtstruct iwn_btcoex_prot { 1042220891Sbschmidt uint8_t open; 1043220891Sbschmidt uint8_t type; 1044220891Sbschmidt uint8_t reserved[2]; 1045220891Sbschmidt} __packed; 1046220891Sbschmidt 1047198429Srpaulo/* Structure for command IWN_CMD_SET_CRITICAL_TEMP. */ 1048178676Ssamstruct iwn_critical_temp { 1049178676Ssam uint32_t reserved; 1050178676Ssam uint32_t tempM; 1051178676Ssam uint32_t tempR; 1052198429Srpaulo/* degK <-> degC conversion macros. */ 1053178676Ssam#define IWN_CTOK(c) ((c) + 273) 1054178676Ssam#define IWN_KTOC(k) ((k) - 273) 1055178676Ssam#define IWN_CTOMUK(c) (((c) * 1000000) + 273150000) 1056178676Ssam} __packed; 1057178676Ssam 1058220729Sbschmidt/* Structures for command IWN_CMD_SET_SENSITIVITY. */ 1059178676Ssamstruct iwn_sensitivity_cmd { 1060178676Ssam uint16_t which; 1061178676Ssam#define IWN_SENSITIVITY_DEFAULTTBL 0 1062178676Ssam#define IWN_SENSITIVITY_WORKTBL 1 1063178676Ssam 1064178676Ssam uint16_t energy_cck; 1065178676Ssam uint16_t energy_ofdm; 1066178676Ssam uint16_t corr_ofdm_x1; 1067178676Ssam uint16_t corr_ofdm_mrc_x1; 1068178676Ssam uint16_t corr_cck_mrc_x4; 1069178676Ssam uint16_t corr_ofdm_x4; 1070178676Ssam uint16_t corr_ofdm_mrc_x4; 1071178676Ssam uint16_t corr_barker; 1072178676Ssam uint16_t corr_barker_mrc; 1073178676Ssam uint16_t corr_cck_x4; 1074178676Ssam uint16_t energy_ofdm_th; 1075178676Ssam} __packed; 1076178676Ssam 1077220729Sbschmidtstruct iwn_enhanced_sensitivity_cmd { 1078220729Sbschmidt uint16_t which; 1079220729Sbschmidt uint16_t energy_cck; 1080220729Sbschmidt uint16_t energy_ofdm; 1081220729Sbschmidt uint16_t corr_ofdm_x1; 1082220729Sbschmidt uint16_t corr_ofdm_mrc_x1; 1083220729Sbschmidt uint16_t corr_cck_mrc_x4; 1084220729Sbschmidt uint16_t corr_ofdm_x4; 1085220729Sbschmidt uint16_t corr_ofdm_mrc_x4; 1086220729Sbschmidt uint16_t corr_barker; 1087220729Sbschmidt uint16_t corr_barker_mrc; 1088220729Sbschmidt uint16_t corr_cck_x4; 1089220729Sbschmidt uint16_t energy_ofdm_th; 1090220729Sbschmidt /* "Enhanced" part. */ 1091220729Sbschmidt uint16_t ina_det_ofdm; 1092220729Sbschmidt uint16_t ina_det_cck; 1093220729Sbschmidt uint16_t corr_11_9_en; 1094220729Sbschmidt uint16_t ofdm_det_slope_mrc; 1095220729Sbschmidt uint16_t ofdm_det_icept_mrc; 1096220729Sbschmidt uint16_t ofdm_det_slope; 1097220729Sbschmidt uint16_t ofdm_det_icept; 1098220729Sbschmidt uint16_t cck_det_slope_mrc; 1099220729Sbschmidt uint16_t cck_det_icept_mrc; 1100220729Sbschmidt uint16_t cck_det_slope; 1101220729Sbschmidt uint16_t cck_det_icept; 1102220729Sbschmidt uint16_t reserved; 1103220729Sbschmidt} __packed; 1104220729Sbschmidt 1105198429Srpaulo/* Structures for command IWN_CMD_PHY_CALIB. */ 1106198429Srpaulostruct iwn_phy_calib { 1107198429Srpaulo uint8_t code; 1108198429Srpaulo#define IWN4965_PHY_CALIB_DIFF_GAIN 7 1109198429Srpaulo#define IWN5000_PHY_CALIB_DC 8 1110198429Srpaulo#define IWN5000_PHY_CALIB_LO 9 1111198429Srpaulo#define IWN5000_PHY_CALIB_TX_IQ 11 1112198429Srpaulo#define IWN5000_PHY_CALIB_CRYSTAL 15 1113198429Srpaulo#define IWN5000_PHY_CALIB_BASE_BAND 16 1114201209Srpaulo#define IWN5000_PHY_CALIB_TX_IQ_PERIODIC 17 1115220676Sbschmidt#define IWN5000_PHY_CALIB_TEMP_OFFSET 18 1116220676Sbschmidt 1117198429Srpaulo#define IWN5000_PHY_CALIB_RESET_NOISE_GAIN 18 1118198429Srpaulo#define IWN5000_PHY_CALIB_NOISE_GAIN 19 1119178676Ssam 1120198429Srpaulo uint8_t group; 1121198429Srpaulo uint8_t ngroups; 1122198429Srpaulo uint8_t isvalid; 1123198429Srpaulo} __packed; 1124178676Ssam 1125198429Srpaulostruct iwn5000_phy_calib_crystal { 1126198429Srpaulo uint8_t code; 1127198429Srpaulo uint8_t group; 1128198429Srpaulo uint8_t ngroups; 1129198429Srpaulo uint8_t isvalid; 1130198429Srpaulo 1131198429Srpaulo uint8_t cap_pin[2]; 1132198429Srpaulo uint8_t reserved[2]; 1133178676Ssam} __packed; 1134178676Ssam 1135220676Sbschmidtstruct iwn5000_phy_calib_temp_offset { 1136220676Sbschmidt uint8_t code; 1137220676Sbschmidt uint8_t group; 1138220676Sbschmidt uint8_t ngroups; 1139220676Sbschmidt uint8_t isvalid; 1140220676Sbschmidt int16_t offset; 1141220676Sbschmidt#define IWN_DEFAULT_TEMP_OFFSET 2700 1142220676Sbschmidt 1143220676Sbschmidt uint16_t reserved; 1144220676Sbschmidt} __packed; 1145220676Sbschmidt 1146253898Sadrianstruct iwn5000_phy_calib_temp_offsetv2 { 1147253898Sadrian uint8_t code; 1148253898Sadrian uint8_t group; 1149253898Sadrian uint8_t ngroups; 1150253898Sadrian uint8_t isvalid; 1151253898Sadrian int16_t offset_high; 1152253898Sadrian int16_t offset_low; 1153253898Sadrian int16_t burnt_voltage_ref; 1154253898Sadrian int16_t reserved; 1155253898Sadrian} __packed; 1156253898Sadrian 1157198429Srpaulostruct iwn_phy_calib_gain { 1158198429Srpaulo uint8_t code; 1159198429Srpaulo uint8_t group; 1160198429Srpaulo uint8_t ngroups; 1161198429Srpaulo uint8_t isvalid; 1162178676Ssam 1163198429Srpaulo int8_t gain[3]; 1164198429Srpaulo uint8_t reserved; 1165198429Srpaulo} __packed; 1166198429Srpaulo 1167198429Srpaulo/* Structure for command IWN_CMD_SPECTRUM_MEASUREMENT. */ 1168198429Srpaulostruct iwn_spectrum_cmd { 1169198429Srpaulo uint16_t len; 1170198429Srpaulo uint8_t token; 1171198429Srpaulo uint8_t id; 1172198429Srpaulo uint8_t origin; 1173198429Srpaulo uint8_t periodic; 1174198429Srpaulo uint16_t timeout; 1175198429Srpaulo uint32_t start; 1176198429Srpaulo uint32_t reserved1; 1177198429Srpaulo uint32_t flags; 1178198429Srpaulo uint32_t filter; 1179198429Srpaulo uint16_t nchan; 1180198429Srpaulo uint16_t reserved2; 1181198429Srpaulo struct { 1182198429Srpaulo uint32_t duration; 1183198429Srpaulo uint8_t chan; 1184198429Srpaulo uint8_t type; 1185198429Srpaulo#define IWN_MEASUREMENT_BASIC (1 << 0) 1186198429Srpaulo#define IWN_MEASUREMENT_CCA (1 << 1) 1187198429Srpaulo#define IWN_MEASUREMENT_RPI_HISTOGRAM (1 << 2) 1188198429Srpaulo#define IWN_MEASUREMENT_NOISE_HISTOGRAM (1 << 3) 1189198429Srpaulo#define IWN_MEASUREMENT_FRAME (1 << 4) 1190198429Srpaulo#define IWN_MEASUREMENT_IDLE (1 << 7) 1191198429Srpaulo 1192198429Srpaulo uint16_t reserved; 1193198429Srpaulo } __packed chan[10]; 1194198429Srpaulo} __packed; 1195198429Srpaulo 1196198429Srpaulo/* Structure for IWN_UC_READY notification. */ 1197178676Ssam#define IWN_NATTEN_GROUPS 5 1198178676Ssamstruct iwn_ucode_info { 1199178676Ssam uint8_t minor; 1200178676Ssam uint8_t major; 1201178676Ssam uint16_t reserved1; 1202178676Ssam uint8_t revision[8]; 1203178676Ssam uint8_t type; 1204178676Ssam uint8_t subtype; 1205178676Ssam#define IWN_UCODE_RUNTIME 0 1206178676Ssam#define IWN_UCODE_INIT 9 1207178676Ssam 1208178676Ssam uint16_t reserved2; 1209178676Ssam uint32_t logptr; 1210198429Srpaulo uint32_t errptr; 1211178676Ssam uint32_t tstamp; 1212178676Ssam uint32_t valid; 1213178676Ssam 1214198429Srpaulo /* The following fields are for UCODE_INIT only. */ 1215178676Ssam int32_t volt; 1216178676Ssam struct { 1217178676Ssam int32_t chan20MHz; 1218178676Ssam int32_t chan40MHz; 1219178676Ssam } __packed temp[4]; 1220198429Srpaulo int32_t atten[IWN_NATTEN_GROUPS][2]; 1221178676Ssam} __packed; 1222178676Ssam 1223198429Srpaulo/* Structures for IWN_TX_DONE notification. */ 1224253898Sadrian#define IWN_TX_STATUS_MSK 0xff 1225253898Sadrian#define TX_STATUS_SUCCESS 0x01 1226253898Sadrian#define TX_STATUS_DIRECT_DONE 0x02 1227253898Sadrian 1228198429Srpaulo#define IWN_TX_SUCCESS 0x00 1229198429Srpaulo#define IWN_TX_FAIL 0x80 /* all failures have 0x80 set */ 1230198429Srpaulo#define IWN_TX_FAIL_SHORT_LIMIT 0x82 /* too many RTS retries */ 1231198429Srpaulo#define IWN_TX_FAIL_LONG_LIMIT 0x83 /* too many retries */ 1232198429Srpaulo#define IWN_TX_FAIL_FIFO_UNDERRRUN 0x84 /* tx fifo not kept running */ 1233198429Srpaulo#define IWN_TX_FAIL_DEST_IN_PS 0x88 /* sta found in power save */ 1234198429Srpaulo#define IWN_TX_FAIL_TX_LOCKED 0x90 /* waiting to see traffic */ 1235198429Srpaulo 1236198429Srpaulostruct iwn4965_tx_stat { 1237178676Ssam uint8_t nframes; 1238201209Srpaulo uint8_t btkillcnt; 1239201209Srpaulo uint8_t rtsfailcnt; 1240201209Srpaulo uint8_t ackfailcnt; 1241221648Sbschmidt uint32_t rate; 1242178676Ssam uint16_t duration; 1243178676Ssam uint16_t reserved; 1244178676Ssam uint32_t power[2]; 1245178676Ssam uint32_t status; 1246178676Ssam} __packed; 1247178676Ssam 1248198429Srpaulostruct iwn5000_tx_stat { 1249253898Sadrian uint8_t nframes; /* 1 no aggregation, >1 aggregation */ 1250201209Srpaulo uint8_t btkillcnt; 1251201209Srpaulo uint8_t rtsfailcnt; 1252201209Srpaulo uint8_t ackfailcnt; 1253221648Sbschmidt uint32_t rate; 1254198429Srpaulo uint16_t duration; 1255198429Srpaulo uint16_t reserved; 1256198429Srpaulo uint32_t power[2]; 1257198429Srpaulo uint32_t info; 1258198429Srpaulo uint16_t seq; 1259198429Srpaulo uint16_t len; 1260201209Srpaulo uint8_t tlc; 1261253898Sadrian uint8_t ratid; /* tid (0:3), sta_id (4:7) */ 1262201209Srpaulo uint8_t fc[2]; 1263198429Srpaulo uint16_t status; 1264198429Srpaulo uint16_t sequence; 1265198429Srpaulo} __packed; 1266198429Srpaulo 1267198429Srpaulo/* Structure for IWN_BEACON_MISSED notification. */ 1268178676Ssamstruct iwn_beacon_missed { 1269178676Ssam uint32_t consecutive; 1270178676Ssam uint32_t total; 1271178676Ssam uint32_t expected; 1272178676Ssam uint32_t received; 1273178676Ssam} __packed; 1274178676Ssam 1275198429Srpaulo/* Structure for IWN_MPDU_RX_DONE notification. */ 1276198429Srpaulostruct iwn_rx_mpdu { 1277178676Ssam uint16_t len; 1278178676Ssam uint16_t reserved; 1279178676Ssam} __packed; 1280178676Ssam 1281198429Srpaulo/* Structures for IWN_RX_DONE and IWN_MPDU_RX_DONE notifications. */ 1282198429Srpaulostruct iwn4965_rx_phystat { 1283198429Srpaulo uint16_t antenna; 1284198429Srpaulo uint16_t agc; 1285198429Srpaulo uint8_t rssi[6]; 1286198429Srpaulo} __packed; 1287198429Srpaulo 1288198429Srpaulostruct iwn5000_rx_phystat { 1289198429Srpaulo uint32_t reserved1; 1290198429Srpaulo uint32_t agc; 1291198429Srpaulo uint16_t rssi[3]; 1292198429Srpaulo} __packed; 1293198429Srpaulo 1294178676Ssamstruct iwn_rx_stat { 1295178676Ssam uint8_t phy_len; 1296178676Ssam uint8_t cfg_phy_len; 1297178676Ssam#define IWN_STAT_MAXLEN 20 1298178676Ssam 1299178676Ssam uint8_t id; 1300178676Ssam uint8_t reserved1; 1301178676Ssam uint64_t tstamp; 1302178676Ssam uint32_t beacon; 1303178676Ssam uint16_t flags; 1304198429Srpaulo#define IWN_STAT_FLAG_SHPREAMBLE (1 << 2) 1305198429Srpaulo 1306178676Ssam uint16_t chan; 1307198429Srpaulo uint8_t phybuf[32]; 1308221648Sbschmidt uint32_t rate; 1309253898Sadrian/* 1310253898Sadrian * rate bit fields 1311253898Sadrian * 1312253898Sadrian * High-throughput (HT) rate format for bits 7:0 (bit 8 must be "1"): 1313253898Sadrian * 2-0: 0) 6 Mbps 1314253898Sadrian * 1) 12 Mbps 1315253898Sadrian * 2) 18 Mbps 1316253898Sadrian * 3) 24 Mbps 1317253898Sadrian * 4) 36 Mbps 1318253898Sadrian * 5) 48 Mbps 1319253898Sadrian * 6) 54 Mbps 1320253898Sadrian * 7) 60 Mbps 1321253898Sadrian * 1322253898Sadrian * 4-3: 0) Single stream (SISO) 1323253898Sadrian * 1) Dual stream (MIMO) 1324253898Sadrian * 2) Triple stream (MIMO) 1325253898Sadrian * 1326253898Sadrian * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data 1327253898Sadrian * 1328253898Sadrian * Legacy OFDM rate format for bits 7:0 (bit 8 must be "0", bit 9 "0"): 1329253898Sadrian * 3-0: 0xD) 6 Mbps 1330253898Sadrian * 0xF) 9 Mbps 1331253898Sadrian * 0x5) 12 Mbps 1332253898Sadrian * 0x7) 18 Mbps 1333253898Sadrian * 0x9) 24 Mbps 1334253898Sadrian * 0xB) 36 Mbps 1335253898Sadrian * 0x1) 48 Mbps 1336253898Sadrian * 0x3) 54 Mbps 1337253898Sadrian * 1338253898Sadrian * Legacy CCK rate format for bits 7:0 (bit 8 must be "0", bit 9 "1"): 1339253898Sadrian * 6-0: 10) 1 Mbps 1340253898Sadrian * 20) 2 Mbps 1341253898Sadrian * 55) 5.5 Mbps 1342253898Sadrian * 110) 11 Mbps 1343253898Sadrian * 1344253898Sadrian */ 1345178676Ssam uint16_t len; 1346178676Ssam uint16_t reserve3; 1347178676Ssam} __packed; 1348178676Ssam 1349198429Srpaulo#define IWN_RSSI_TO_DBM 44 1350198429Srpaulo 1351201209Srpaulo/* Structure for IWN_RX_COMPRESSED_BA notification. */ 1352201209Srpaulostruct iwn_compressed_ba { 1353201209Srpaulo uint8_t macaddr[IEEE80211_ADDR_LEN]; 1354201209Srpaulo uint16_t reserved; 1355201209Srpaulo uint8_t id; 1356201209Srpaulo uint8_t tid; 1357201209Srpaulo uint16_t seq; 1358201209Srpaulo uint64_t bitmap; 1359201209Srpaulo uint16_t qid; 1360201209Srpaulo uint16_t ssn; 1361201209Srpaulo} __packed; 1362201209Srpaulo 1363198429Srpaulo/* Structure for IWN_START_SCAN notification. */ 1364178676Ssamstruct iwn_start_scan { 1365178676Ssam uint64_t tstamp; 1366178676Ssam uint32_t tbeacon; 1367178676Ssam uint8_t chan; 1368178676Ssam uint8_t band; 1369178676Ssam uint16_t reserved; 1370178676Ssam uint32_t status; 1371178676Ssam} __packed; 1372178676Ssam 1373198429Srpaulo/* Structure for IWN_STOP_SCAN notification. */ 1374178676Ssamstruct iwn_stop_scan { 1375178676Ssam uint8_t nchan; 1376178676Ssam uint8_t status; 1377178676Ssam uint8_t reserved; 1378178676Ssam uint8_t chan; 1379178676Ssam uint64_t tsf; 1380178676Ssam} __packed; 1381178676Ssam 1382198429Srpaulo/* Structure for IWN_SPECTRUM_MEASUREMENT notification. */ 1383198429Srpaulostruct iwn_spectrum_notif { 1384198429Srpaulo uint8_t id; 1385198429Srpaulo uint8_t token; 1386198429Srpaulo uint8_t idx; 1387198429Srpaulo uint8_t state; 1388198429Srpaulo#define IWN_MEASUREMENT_START 0 1389198429Srpaulo#define IWN_MEASUREMENT_STOP 1 1390198429Srpaulo 1391198429Srpaulo uint32_t start; 1392198429Srpaulo uint8_t band; 1393198429Srpaulo uint8_t chan; 1394198429Srpaulo uint8_t type; 1395198429Srpaulo uint8_t reserved1; 1396198429Srpaulo uint32_t cca_ofdm; 1397198429Srpaulo uint32_t cca_cck; 1398198429Srpaulo uint32_t cca_time; 1399198429Srpaulo uint8_t basic; 1400198429Srpaulo uint8_t reserved2[3]; 1401198429Srpaulo uint32_t ofdm[8]; 1402198429Srpaulo uint32_t cck[8]; 1403198429Srpaulo uint32_t stop; 1404198429Srpaulo uint32_t status; 1405198429Srpaulo#define IWN_MEASUREMENT_OK 0 1406198429Srpaulo#define IWN_MEASUREMENT_CONCURRENT 1 1407198429Srpaulo#define IWN_MEASUREMENT_CSA_CONFLICT 2 1408198429Srpaulo#define IWN_MEASUREMENT_TGH_CONFLICT 3 1409198429Srpaulo#define IWN_MEASUREMENT_STOPPED 6 1410198429Srpaulo#define IWN_MEASUREMENT_TIMEOUT 7 1411198429Srpaulo#define IWN_MEASUREMENT_FAILED 8 1412198429Srpaulo} __packed; 1413198429Srpaulo 1414201209Srpaulo/* Structures for IWN_{RX,BEACON}_STATISTICS notification. */ 1415178676Ssamstruct iwn_rx_phy_stats { 1416178676Ssam uint32_t ina; 1417178676Ssam uint32_t fina; 1418178676Ssam uint32_t bad_plcp; 1419178676Ssam uint32_t bad_crc32; 1420178676Ssam uint32_t overrun; 1421178676Ssam uint32_t eoverrun; 1422178676Ssam uint32_t good_crc32; 1423178676Ssam uint32_t fa; 1424178676Ssam uint32_t bad_fina_sync; 1425178676Ssam uint32_t sfd_timeout; 1426178676Ssam uint32_t fina_timeout; 1427178676Ssam uint32_t no_rts_ack; 1428178676Ssam uint32_t rxe_limit; 1429178676Ssam uint32_t ack; 1430178676Ssam uint32_t cts; 1431178676Ssam uint32_t ba_resp; 1432178676Ssam uint32_t dsp_kill; 1433178676Ssam uint32_t bad_mh; 1434178676Ssam uint32_t rssi_sum; 1435178676Ssam uint32_t reserved; 1436178676Ssam} __packed; 1437178676Ssam 1438178676Ssamstruct iwn_rx_general_stats { 1439178676Ssam uint32_t bad_cts; 1440178676Ssam uint32_t bad_ack; 1441178676Ssam uint32_t not_bss; 1442178676Ssam uint32_t filtered; 1443178676Ssam uint32_t bad_chan; 1444178676Ssam uint32_t beacons; 1445178676Ssam uint32_t missed_beacons; 1446178676Ssam uint32_t adc_saturated; /* time in 0.8us */ 1447178676Ssam uint32_t ina_searched; /* time in 0.8us */ 1448178676Ssam uint32_t noise[3]; 1449178676Ssam uint32_t flags; 1450178676Ssam uint32_t load; 1451178676Ssam uint32_t fa; 1452178676Ssam uint32_t rssi[3]; 1453178676Ssam uint32_t energy[3]; 1454178676Ssam} __packed; 1455178676Ssam 1456178676Ssamstruct iwn_rx_ht_phy_stats { 1457178676Ssam uint32_t bad_plcp; 1458178676Ssam uint32_t overrun; 1459178676Ssam uint32_t eoverrun; 1460178676Ssam uint32_t good_crc32; 1461178676Ssam uint32_t bad_crc32; 1462178676Ssam uint32_t bad_mh; 1463178676Ssam uint32_t good_ampdu_crc32; 1464178676Ssam uint32_t ampdu; 1465178676Ssam uint32_t fragment; 1466178676Ssam uint32_t reserved; 1467178676Ssam} __packed; 1468178676Ssam 1469178676Ssamstruct iwn_rx_stats { 1470178676Ssam struct iwn_rx_phy_stats ofdm; 1471178676Ssam struct iwn_rx_phy_stats cck; 1472178676Ssam struct iwn_rx_general_stats general; 1473178676Ssam struct iwn_rx_ht_phy_stats ht; 1474178676Ssam} __packed; 1475178676Ssam 1476178676Ssamstruct iwn_tx_stats { 1477178676Ssam uint32_t preamble; 1478178676Ssam uint32_t rx_detected; 1479178676Ssam uint32_t bt_defer; 1480178676Ssam uint32_t bt_kill; 1481178676Ssam uint32_t short_len; 1482178676Ssam uint32_t cts_timeout; 1483178676Ssam uint32_t ack_timeout; 1484178676Ssam uint32_t exp_ack; 1485178676Ssam uint32_t ack; 1486178676Ssam uint32_t msdu; 1487178676Ssam uint32_t busrt_err1; 1488178676Ssam uint32_t burst_err2; 1489178676Ssam uint32_t cts_collision; 1490178676Ssam uint32_t ack_collision; 1491178676Ssam uint32_t ba_timeout; 1492178676Ssam uint32_t ba_resched; 1493178676Ssam uint32_t query_ampdu; 1494178676Ssam uint32_t query; 1495178676Ssam uint32_t query_ampdu_frag; 1496178676Ssam uint32_t query_mismatch; 1497178676Ssam uint32_t not_ready; 1498178676Ssam uint32_t underrun; 1499178676Ssam uint32_t bt_ht_kill; 1500178676Ssam uint32_t rx_ba_resp; 1501178676Ssam uint32_t reserved[2]; 1502178676Ssam} __packed; 1503178676Ssam 1504178676Ssamstruct iwn_general_stats { 1505178676Ssam uint32_t temp; 1506178676Ssam uint32_t temp_m; 1507178676Ssam uint32_t burst_check; 1508178676Ssam uint32_t burst; 1509178676Ssam uint32_t reserved1[4]; 1510178676Ssam uint32_t sleep; 1511178676Ssam uint32_t slot_out; 1512178676Ssam uint32_t slot_idle; 1513178676Ssam uint32_t ttl_tstamp; 1514178676Ssam uint32_t tx_ant_a; 1515178676Ssam uint32_t tx_ant_b; 1516178676Ssam uint32_t exec; 1517178676Ssam uint32_t probe; 1518178676Ssam uint32_t reserved2[2]; 1519178676Ssam uint32_t rx_enabled; 1520178676Ssam uint32_t reserved3[3]; 1521178676Ssam} __packed; 1522178676Ssam 1523178676Ssamstruct iwn_stats { 1524178676Ssam uint32_t flags; 1525178676Ssam struct iwn_rx_stats rx; 1526178676Ssam struct iwn_tx_stats tx; 1527178676Ssam struct iwn_general_stats general; 1528178676Ssam} __packed; 1529178676Ssam 1530178676Ssam 1531198429Srpaulo/* Firmware error dump. */ 1532198429Srpaulostruct iwn_fw_dump { 1533198429Srpaulo uint32_t valid; 1534198429Srpaulo uint32_t id; 1535198429Srpaulo uint32_t pc; 1536198429Srpaulo uint32_t branch_link[2]; 1537198429Srpaulo uint32_t interrupt_link[2]; 1538198429Srpaulo uint32_t error_data[2]; 1539198429Srpaulo uint32_t src_line; 1540198429Srpaulo uint32_t tsf; 1541198429Srpaulo uint32_t time[2]; 1542198429Srpaulo} __packed; 1543198429Srpaulo 1544210111Sbschmidt/* TLV firmware header. */ 1545210111Sbschmidtstruct iwn_fw_tlv_hdr { 1546210111Sbschmidt uint32_t zero; /* Always 0, to differentiate from legacy. */ 1547210111Sbschmidt uint32_t signature; 1548210111Sbschmidt#define IWN_FW_SIGNATURE 0x0a4c5749 /* "IWL\n" */ 1549210111Sbschmidt 1550210111Sbschmidt uint8_t descr[64]; 1551210111Sbschmidt uint32_t rev; 1552210111Sbschmidt#define IWN_FW_API(x) (((x) >> 8) & 0xff) 1553210111Sbschmidt 1554210111Sbschmidt uint32_t build; 1555210111Sbschmidt uint64_t altmask; 1556210111Sbschmidt} __packed; 1557210111Sbschmidt 1558210111Sbschmidt/* TLV header. */ 1559210111Sbschmidtstruct iwn_fw_tlv { 1560210111Sbschmidt uint16_t type; 1561210111Sbschmidt#define IWN_FW_TLV_MAIN_TEXT 1 1562210111Sbschmidt#define IWN_FW_TLV_MAIN_DATA 2 1563210111Sbschmidt#define IWN_FW_TLV_INIT_TEXT 3 1564210111Sbschmidt#define IWN_FW_TLV_INIT_DATA 4 1565210111Sbschmidt#define IWN_FW_TLV_BOOT_TEXT 5 1566210111Sbschmidt#define IWN_FW_TLV_PBREQ_MAXLEN 6 1567253898Sadrian#define IWN_FW_TLV_PAN 7 1568253898Sadrian#define IWN_FW_TLV_RUNT_EVTLOG_PTR 8 1569253898Sadrian#define IWN_FW_TLV_RUNT_EVTLOG_SIZE 9 1570253898Sadrian#define IWN_FW_TLV_RUNT_ERRLOG_PTR 10 1571253898Sadrian#define IWN_FW_TLV_INIT_EVTLOG_PTR 11 1572253898Sadrian#define IWN_FW_TLV_INIT_EVTLOG_SIZE 12 1573253898Sadrian#define IWN_FW_TLV_INIT_ERRLOG_PTR 13 1574220866Sbschmidt#define IWN_FW_TLV_ENH_SENS 14 1575220866Sbschmidt#define IWN_FW_TLV_PHY_CALIB 15 1576253898Sadrian#define IWN_FW_TLV_WOWLAN_INST 16 1577253898Sadrian#define IWN_FW_TLV_WOWLAN_DATA 17 1578253898Sadrian#define IWN_FW_TLV_FLAGS 18 1579210111Sbschmidt 1580210111Sbschmidt uint16_t alt; 1581210111Sbschmidt uint32_t len; 1582210111Sbschmidt} __packed; 1583210111Sbschmidt 1584198429Srpaulo#define IWN4965_FW_TEXT_MAXSZ ( 96 * 1024) 1585198429Srpaulo#define IWN4965_FW_DATA_MAXSZ ( 40 * 1024) 1586198429Srpaulo#define IWN5000_FW_TEXT_MAXSZ (256 * 1024) 1587198429Srpaulo#define IWN5000_FW_DATA_MAXSZ ( 80 * 1024) 1588178676Ssam#define IWN_FW_BOOT_TEXT_MAXSZ 1024 1589198429Srpaulo#define IWN4965_FWSZ (IWN4965_FW_TEXT_MAXSZ + IWN4965_FW_DATA_MAXSZ) 1590198429Srpaulo#define IWN5000_FWSZ IWN5000_FW_TEXT_MAXSZ 1591178676Ssam 1592178676Ssam/* 1593178676Ssam * Offsets into EEPROM. 1594178676Ssam */ 1595178676Ssam#define IWN_EEPROM_MAC 0x015 1596220729Sbschmidt#define IWN_EEPROM_SKU_CAP 0x045 1597198429Srpaulo#define IWN_EEPROM_RFCFG 0x048 1598198429Srpaulo#define IWN4965_EEPROM_DOMAIN 0x060 1599198429Srpaulo#define IWN4965_EEPROM_BAND1 0x063 1600198429Srpaulo#define IWN5000_EEPROM_REG 0x066 1601198429Srpaulo#define IWN5000_EEPROM_CAL 0x067 1602198429Srpaulo#define IWN4965_EEPROM_BAND2 0x072 1603198429Srpaulo#define IWN4965_EEPROM_BAND3 0x080 1604198429Srpaulo#define IWN4965_EEPROM_BAND4 0x08d 1605198429Srpaulo#define IWN4965_EEPROM_BAND5 0x099 1606198429Srpaulo#define IWN4965_EEPROM_BAND6 0x0a0 1607198429Srpaulo#define IWN4965_EEPROM_BAND7 0x0a8 1608198429Srpaulo#define IWN4965_EEPROM_MAXPOW 0x0e8 1609198429Srpaulo#define IWN4965_EEPROM_VOLTAGE 0x0e9 1610198429Srpaulo#define IWN4965_EEPROM_BANDS 0x0ea 1611198429Srpaulo/* Indirect offsets. */ 1612253898Sadrian#define IWN5000_EEPROM_NO_HT40 0x000 1613198429Srpaulo#define IWN5000_EEPROM_DOMAIN 0x001 1614198429Srpaulo#define IWN5000_EEPROM_BAND1 0x004 1615198429Srpaulo#define IWN5000_EEPROM_BAND2 0x013 1616198429Srpaulo#define IWN5000_EEPROM_BAND3 0x021 1617198429Srpaulo#define IWN5000_EEPROM_BAND4 0x02e 1618198429Srpaulo#define IWN5000_EEPROM_BAND5 0x03a 1619198429Srpaulo#define IWN5000_EEPROM_BAND6 0x041 1620221635Sbschmidt#define IWN6000_EEPROM_BAND6 0x040 1621198429Srpaulo#define IWN5000_EEPROM_BAND7 0x049 1622201209Srpaulo#define IWN6000_EEPROM_ENHINFO 0x054 1623198429Srpaulo#define IWN5000_EEPROM_CRYSTAL 0x128 1624198429Srpaulo#define IWN5000_EEPROM_TEMP 0x12a 1625198429Srpaulo#define IWN5000_EEPROM_VOLT 0x12b 1626178676Ssam 1627220729Sbschmidt/* Possible flags for IWN_EEPROM_SKU_CAP. */ 1628220729Sbschmidt#define IWN_EEPROM_SKU_CAP_11N (1 << 6) 1629220729Sbschmidt#define IWN_EEPROM_SKU_CAP_AMT (1 << 7) 1630220729Sbschmidt#define IWN_EEPROM_SKU_CAP_IPAN (1 << 8) 1631220729Sbschmidt 1632198429Srpaulo/* Possible flags for IWN_EEPROM_RFCFG. */ 1633198429Srpaulo#define IWN_RFCFG_TYPE(x) (((x) >> 0) & 0x3) 1634198429Srpaulo#define IWN_RFCFG_STEP(x) (((x) >> 2) & 0x3) 1635198429Srpaulo#define IWN_RFCFG_DASH(x) (((x) >> 4) & 0x3) 1636198429Srpaulo#define IWN_RFCFG_TXANTMSK(x) (((x) >> 8) & 0xf) 1637198429Srpaulo#define IWN_RFCFG_RXANTMSK(x) (((x) >> 12) & 0xf) 1638198429Srpaulo 1639178676Ssamstruct iwn_eeprom_chan { 1640178676Ssam uint8_t flags; 1641178676Ssam#define IWN_EEPROM_CHAN_VALID (1 << 0) 1642198429Srpaulo#define IWN_EEPROM_CHAN_IBSS (1 << 1) 1643198429Srpaulo#define IWN_EEPROM_CHAN_ACTIVE (1 << 3) 1644198429Srpaulo#define IWN_EEPROM_CHAN_RADAR (1 << 4) 1645178676Ssam 1646178676Ssam int8_t maxpwr; 1647178676Ssam} __packed; 1648178676Ssam 1649201209Srpaulostruct iwn_eeprom_enhinfo { 1650221637Sbschmidt uint8_t flags; 1651221637Sbschmidt#define IWN_ENHINFO_VALID 0x01 1652221637Sbschmidt#define IWN_ENHINFO_5GHZ 0x02 1653221637Sbschmidt#define IWN_ENHINFO_OFDM 0x04 1654221637Sbschmidt#define IWN_ENHINFO_HT40 0x08 1655221637Sbschmidt#define IWN_ENHINFO_HTAP 0x10 1656221637Sbschmidt#define IWN_ENHINFO_RES1 0x20 1657221637Sbschmidt#define IWN_ENHINFO_RES2 0x40 1658221637Sbschmidt#define IWN_ENHINFO_COMMON 0x80 1659221637Sbschmidt 1660221637Sbschmidt uint8_t chan; 1661201209Srpaulo int8_t chain[3]; /* max power in half-dBm */ 1662201209Srpaulo uint8_t reserved; 1663201209Srpaulo int8_t mimo2; /* max power in half-dBm */ 1664201209Srpaulo int8_t mimo3; /* max power in half-dBm */ 1665201209Srpaulo} __packed; 1666201209Srpaulo 1667206444Sbschmidtstruct iwn5000_eeprom_calib_hdr { 1668206444Sbschmidt uint8_t version; 1669206444Sbschmidt uint8_t pa_type; 1670206444Sbschmidt uint16_t volt; 1671206444Sbschmidt} __packed; 1672206444Sbschmidt 1673178676Ssam#define IWN_NSAMPLES 3 1674198429Srpaulostruct iwn4965_eeprom_chan_samples { 1675178676Ssam uint8_t num; 1676178676Ssam struct { 1677178676Ssam uint8_t temp; 1678178676Ssam uint8_t gain; 1679178676Ssam uint8_t power; 1680178676Ssam int8_t pa_det; 1681198429Srpaulo } samples[2][IWN_NSAMPLES]; 1682178676Ssam} __packed; 1683178676Ssam 1684178676Ssam#define IWN_NBANDS 8 1685198429Srpaulostruct iwn4965_eeprom_band { 1686178676Ssam uint8_t lo; /* low channel number */ 1687178676Ssam uint8_t hi; /* high channel number */ 1688198429Srpaulo struct iwn4965_eeprom_chan_samples chans[2]; 1689178676Ssam} __packed; 1690178676Ssam 1691198429Srpaulo/* 1692198429Srpaulo * Offsets of channels descriptions in EEPROM. 1693198429Srpaulo */ 1694198429Srpaulostatic const uint32_t iwn4965_regulatory_bands[IWN_NBANDS] = { 1695198429Srpaulo IWN4965_EEPROM_BAND1, 1696198429Srpaulo IWN4965_EEPROM_BAND2, 1697198429Srpaulo IWN4965_EEPROM_BAND3, 1698198429Srpaulo IWN4965_EEPROM_BAND4, 1699198429Srpaulo IWN4965_EEPROM_BAND5, 1700198429Srpaulo IWN4965_EEPROM_BAND6, 1701198429Srpaulo IWN4965_EEPROM_BAND7 1702198429Srpaulo}; 1703178676Ssam 1704198429Srpaulostatic const uint32_t iwn5000_regulatory_bands[IWN_NBANDS] = { 1705198429Srpaulo IWN5000_EEPROM_BAND1, 1706198429Srpaulo IWN5000_EEPROM_BAND2, 1707198429Srpaulo IWN5000_EEPROM_BAND3, 1708198429Srpaulo IWN5000_EEPROM_BAND4, 1709198429Srpaulo IWN5000_EEPROM_BAND5, 1710198429Srpaulo IWN5000_EEPROM_BAND6, 1711198429Srpaulo IWN5000_EEPROM_BAND7 1712198429Srpaulo}; 1713198429Srpaulo 1714221635Sbschmidtstatic const uint32_t iwn6000_regulatory_bands[IWN_NBANDS] = { 1715221635Sbschmidt IWN5000_EEPROM_BAND1, 1716221635Sbschmidt IWN5000_EEPROM_BAND2, 1717221635Sbschmidt IWN5000_EEPROM_BAND3, 1718221635Sbschmidt IWN5000_EEPROM_BAND4, 1719221635Sbschmidt IWN5000_EEPROM_BAND5, 1720221635Sbschmidt IWN6000_EEPROM_BAND6, 1721221635Sbschmidt IWN5000_EEPROM_BAND7 1722221635Sbschmidt}; 1723221635Sbschmidt 1724253898Sadrianstatic const uint32_t iwn1000_regulatory_bands[IWN_NBANDS] = { 1725253898Sadrian IWN5000_EEPROM_BAND1, 1726253898Sadrian IWN5000_EEPROM_BAND2, 1727253898Sadrian IWN5000_EEPROM_BAND3, 1728253898Sadrian IWN5000_EEPROM_BAND4, 1729253898Sadrian IWN5000_EEPROM_BAND5, 1730253898Sadrian IWN5000_EEPROM_BAND6, 1731253898Sadrian IWN5000_EEPROM_NO_HT40, 1732253898Sadrian}; 1733253898Sadrian 1734198429Srpaulo#define IWN_CHAN_BANDS_COUNT 7 1735198429Srpaulo#define IWN_MAX_CHAN_PER_BAND 14 1736198429Srpaulostatic const struct iwn_chan_band { 1737198429Srpaulo uint8_t nchan; 1738198429Srpaulo uint8_t chan[IWN_MAX_CHAN_PER_BAND]; 1739198429Srpaulo} iwn_bands[] = { 1740198429Srpaulo /* 20MHz channels, 2GHz band. */ 1741198429Srpaulo { 14, { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } }, 1742198429Srpaulo /* 20MHz channels, 5GHz band. */ 1743198429Srpaulo { 13, { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } }, 1744198429Srpaulo { 12, { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } }, 1745198429Srpaulo { 11, { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } }, 1746198429Srpaulo { 6, { 145, 149, 153, 157, 161, 165 } }, 1747198429Srpaulo /* 40MHz channels (primary channels), 2GHz band. */ 1748198429Srpaulo { 7, { 1, 2, 3, 4, 5, 6, 7 } }, 1749198429Srpaulo /* 40MHz channels (primary channels), 5GHz band. */ 1750198429Srpaulo { 11, { 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157 } } 1751198429Srpaulo}; 1752198429Srpaulo 1753253898Sadrianstatic const uint8_t iwn_bss_ac_to_queue[] = { 1754253898Sadrian 2, 3, 1, 0, 1755253898Sadrian}; 1756253898Sadrian 1757253898Sadrianstatic const uint8_t iwn_pan_ac_to_queue[] = { 1758253898Sadrian 5, 4, 6, 7, 1759253898Sadrian}; 1760220726Sbschmidt#define IWN1000_OTP_NBLOCKS 3 1761220726Sbschmidt#define IWN6000_OTP_NBLOCKS 4 1762201209Srpaulo#define IWN6050_OTP_NBLOCKS 7 1763198429Srpaulo 1764198429Srpaulo/* HW rate indices. */ 1765220715Sbschmidt#define IWN_RIDX_CCK1 0 1766220715Sbschmidt#define IWN_RIDX_OFDM6 4 1767198429Srpaulo 1768198429Srpaulo#define IWN4965_MAX_PWR_INDEX 107 1769253898Sadrian#define IWN_POWERSAVE_LVL_NONE 0 1770253898Sadrian#define IWN_POWERSAVE_LVL_VOIP_COMPATIBLE 1 1771253898Sadrian#define IWN_POWERSAVE_LVL_MAX 5 1772198429Srpaulo 1773253898Sadrian#define IWN_POWERSAVE_LVL_DEFAULT IWN_POWERSAVE_LVL_NONE 1774253898Sadrian 1775253898Sadrian/* DTIM value to pass in for IWN_POWERSAVE_LVL_VOIP_COMPATIBLE */ 1776253898Sadrian#define IWN_POWERSAVE_DTIM_VOIP_COMPATIBLE 2 1777253898Sadrian 1778178676Ssam/* 1779178676Ssam * RF Tx gain values from highest to lowest power (values obtained from 1780178676Ssam * the reference driver.) 1781178676Ssam */ 1782198429Srpaulostatic const uint8_t iwn4965_rf_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1783178676Ssam 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, 1784178676Ssam 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 0x39, 0x38, 1785178676Ssam 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 0x35, 0x35, 1786178676Ssam 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x31, 0x31, 1787178676Ssam 0x31, 0x30, 0x30, 0x30, 0x06, 0x06, 0x06, 0x05, 0x05, 0x05, 0x04, 1788178676Ssam 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01, 1789178676Ssam 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1790178676Ssam 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1791178676Ssam 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1792178676Ssam 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1793178676Ssam}; 1794178676Ssam 1795198429Srpaulostatic const uint8_t iwn4965_rf_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1796178676Ssam 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 1797178676Ssam 0x3c, 0x3c, 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 1798178676Ssam 0x39, 0x38, 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 1799178676Ssam 0x35, 0x35, 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 1800178676Ssam 0x31, 0x31, 0x31, 0x30, 0x30, 0x30, 0x25, 0x25, 0x25, 0x24, 0x24, 1801178676Ssam 0x24, 0x23, 0x23, 0x23, 0x22, 0x18, 0x18, 0x17, 0x17, 0x17, 0x16, 1802178676Ssam 0x16, 0x16, 0x15, 0x15, 0x15, 0x14, 0x14, 0x14, 0x13, 0x13, 0x13, 1803178676Ssam 0x12, 0x08, 0x08, 0x07, 0x07, 0x07, 0x06, 0x06, 0x06, 0x05, 0x05, 1804178676Ssam 0x05, 0x04, 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 1805178676Ssam 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1806178676Ssam}; 1807178676Ssam 1808178676Ssam/* 1809178676Ssam * DSP pre-DAC gain values from highest to lowest power (values obtained 1810178676Ssam * from the reference driver.) 1811178676Ssam */ 1812198429Srpaulostatic const uint8_t iwn4965_dsp_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1813178676Ssam 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1814178676Ssam 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1815178676Ssam 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1816178676Ssam 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1817178676Ssam 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1818178676Ssam 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1819178676Ssam 0x6e, 0x68, 0x62, 0x61, 0x60, 0x5f, 0x5e, 0x5d, 0x5c, 0x5b, 0x5a, 1820178676Ssam 0x59, 0x58, 0x57, 0x56, 0x55, 0x54, 0x53, 0x52, 0x51, 0x50, 0x4f, 1821178676Ssam 0x4e, 0x4d, 0x4c, 0x4b, 0x4a, 0x49, 0x48, 0x47, 0x46, 0x45, 0x44, 1822178676Ssam 0x43, 0x42, 0x41, 0x40, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b 1823178676Ssam}; 1824178676Ssam 1825198429Srpaulostatic const uint8_t iwn4965_dsp_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1826178676Ssam 0x7b, 0x75, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1827178676Ssam 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1828178676Ssam 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1829178676Ssam 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1830178676Ssam 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1831178676Ssam 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1832178676Ssam 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1833178676Ssam 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1834178676Ssam 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1835178676Ssam 0x68, 0x62, 0x6e, 0x68, 0x62, 0x5d, 0x58, 0x53, 0x4e 1836178676Ssam}; 1837178676Ssam 1838198429Srpaulo/* 1839198429Srpaulo * Power saving settings (values obtained from the reference driver.) 1840198429Srpaulo */ 1841198429Srpaulo#define IWN_NDTIMRANGES 3 1842198429Srpaulo#define IWN_NPOWERLEVELS 6 1843198429Srpaulostatic const struct iwn_pmgt { 1844198429Srpaulo uint32_t rxtimeout; 1845198429Srpaulo uint32_t txtimeout; 1846198429Srpaulo uint32_t intval[5]; 1847198429Srpaulo int skip_dtim; 1848198429Srpaulo} iwn_pmgt[IWN_NDTIMRANGES][IWN_NPOWERLEVELS] = { 1849198429Srpaulo /* DTIM <= 2 */ 1850198429Srpaulo { 1851198429Srpaulo { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1852198429Srpaulo { 200, 500, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 1 */ 1853198429Srpaulo { 200, 300, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 2 */ 1854198429Srpaulo { 50, 100, { 2, 2, 2, 2, -1 }, 0 }, /* PS level 3 */ 1855198429Srpaulo { 50, 25, { 2, 2, 4, 4, -1 }, 1 }, /* PS level 4 */ 1856198429Srpaulo { 25, 25, { 2, 2, 4, 6, -1 }, 2 } /* PS level 5 */ 1857198429Srpaulo }, 1858198429Srpaulo /* 3 <= DTIM <= 10 */ 1859198429Srpaulo { 1860198429Srpaulo { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1861198429Srpaulo { 200, 500, { 1, 2, 3, 4, 4 }, 0 }, /* PS level 1 */ 1862198429Srpaulo { 200, 300, { 1, 2, 3, 4, 7 }, 0 }, /* PS level 2 */ 1863198429Srpaulo { 50, 100, { 2, 4, 6, 7, 9 }, 0 }, /* PS level 3 */ 1864198429Srpaulo { 50, 25, { 2, 4, 6, 9, 10 }, 1 }, /* PS level 4 */ 1865198429Srpaulo { 25, 25, { 2, 4, 7, 10, 10 }, 2 } /* PS level 5 */ 1866198429Srpaulo }, 1867198429Srpaulo /* DTIM >= 11 */ 1868198429Srpaulo { 1869198429Srpaulo { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1870198429Srpaulo { 200, 500, { 1, 2, 3, 4, -1 }, 0 }, /* PS level 1 */ 1871198429Srpaulo { 200, 300, { 2, 4, 6, 7, -1 }, 0 }, /* PS level 2 */ 1872198429Srpaulo { 50, 100, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 3 */ 1873198429Srpaulo { 50, 25, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 4 */ 1874198429Srpaulo { 25, 25, { 4, 7, 10, 10, -1 }, 0 } /* PS level 5 */ 1875198429Srpaulo } 1876198429Srpaulo}; 1877198429Srpaulo 1878198429Srpaulostruct iwn_sensitivity_limits { 1879198429Srpaulo uint32_t min_ofdm_x1; 1880198429Srpaulo uint32_t max_ofdm_x1; 1881198429Srpaulo uint32_t min_ofdm_mrc_x1; 1882198429Srpaulo uint32_t max_ofdm_mrc_x1; 1883198429Srpaulo uint32_t min_ofdm_x4; 1884198429Srpaulo uint32_t max_ofdm_x4; 1885198429Srpaulo uint32_t min_ofdm_mrc_x4; 1886198429Srpaulo uint32_t max_ofdm_mrc_x4; 1887198429Srpaulo uint32_t min_cck_x4; 1888198429Srpaulo uint32_t max_cck_x4; 1889198429Srpaulo uint32_t min_cck_mrc_x4; 1890198429Srpaulo uint32_t max_cck_mrc_x4; 1891198429Srpaulo uint32_t min_energy_cck; 1892198429Srpaulo uint32_t energy_cck; 1893198429Srpaulo uint32_t energy_ofdm; 1894198429Srpaulo}; 1895198429Srpaulo 1896198429Srpaulo/* 1897198429Srpaulo * RX sensitivity limits (values obtained from the reference driver.) 1898198429Srpaulo */ 1899198429Srpaulostatic const struct iwn_sensitivity_limits iwn4965_sensitivity_limits = { 1900198429Srpaulo 105, 140, 1901201209Srpaulo 220, 270, 1902198429Srpaulo 85, 120, 1903198429Srpaulo 170, 210, 1904198429Srpaulo 125, 200, 1905198429Srpaulo 200, 400, 1906198429Srpaulo 97, 1907198429Srpaulo 100, 1908198429Srpaulo 100 1909198429Srpaulo}; 1910198429Srpaulo 1911198429Srpaulostatic const struct iwn_sensitivity_limits iwn5000_sensitivity_limits = { 1912206444Sbschmidt 120, 120, /* min = max for performance bug in DSP. */ 1913206444Sbschmidt 240, 240, /* min = max for performance bug in DSP. */ 1914198429Srpaulo 90, 120, 1915198429Srpaulo 170, 210, 1916198429Srpaulo 125, 200, 1917198429Srpaulo 170, 400, 1918198429Srpaulo 95, 1919198429Srpaulo 95, 1920198429Srpaulo 95 1921198429Srpaulo}; 1922198429Srpaulo 1923201209Srpaulostatic const struct iwn_sensitivity_limits iwn5150_sensitivity_limits = { 1924201209Srpaulo 105, 105, /* min = max for performance bug in DSP. */ 1925201209Srpaulo 220, 220, /* min = max for performance bug in DSP. */ 1926201209Srpaulo 90, 120, 1927201209Srpaulo 170, 210, 1928201209Srpaulo 125, 200, 1929201209Srpaulo 170, 400, 1930201209Srpaulo 95, 1931201209Srpaulo 95, 1932201209Srpaulo 95 1933201209Srpaulo}; 1934201209Srpaulo 1935206444Sbschmidtstatic const struct iwn_sensitivity_limits iwn1000_sensitivity_limits = { 1936206444Sbschmidt 120, 155, 1937206444Sbschmidt 240, 290, 1938220726Sbschmidt 90, 120, 1939206444Sbschmidt 170, 210, 1940206444Sbschmidt 125, 200, 1941206444Sbschmidt 170, 400, 1942220726Sbschmidt 95, 1943220726Sbschmidt 95, 1944220726Sbschmidt 95 1945206444Sbschmidt}; 1946206444Sbschmidt 1947201209Srpaulostatic const struct iwn_sensitivity_limits iwn6000_sensitivity_limits = { 1948206444Sbschmidt 105, 110, 1949201209Srpaulo 192, 232, 1950201209Srpaulo 80, 145, 1951201209Srpaulo 128, 232, 1952201209Srpaulo 125, 175, 1953201209Srpaulo 160, 310, 1954201209Srpaulo 97, 1955201209Srpaulo 97, 1956201209Srpaulo 100 1957201209Srpaulo}; 1958201209Srpaulo 1959253898Sadrian/* Get value from linux kernel 3.2.+ in Drivers/net/wireless/iwlwifi/iwl-2000.c*/ 1960253898Sadrianstatic const struct iwn_sensitivity_limits iwn2030_sensitivity_limits = { 1961253898Sadrian 105,110, 1962253898Sadrian 128,232, 1963253898Sadrian 80,145, 1964253898Sadrian 128,232, 1965253898Sadrian 125,175, 1966253898Sadrian 160,310, 1967253898Sadrian 97, 1968253898Sadrian 97, 1969253898Sadrian 110 1970253898Sadrian}; 1971253898Sadrian 1972198429Srpaulo/* Map TID to TX scheduler's FIFO. */ 1973198429Srpaulostatic const uint8_t iwn_tid2fifo[] = { 1974198429Srpaulo 1, 0, 0, 1, 2, 2, 3, 3, 7, 7, 7, 7, 7, 7, 7, 7, 3 1975198429Srpaulo}; 1976198429Srpaulo 1977201209Srpaulo/* WiFi/WiMAX coexist event priority table for 6050. */ 1978201209Srpaulostatic const struct iwn5000_wimax_event iwn6050_wimax_events[] = { 1979201209Srpaulo { 0x04, 0x03, 0x00, 0x00 }, 1980201209Srpaulo { 0x04, 0x03, 0x00, 0x03 }, 1981201209Srpaulo { 0x04, 0x03, 0x00, 0x03 }, 1982201209Srpaulo { 0x04, 0x03, 0x00, 0x03 }, 1983201209Srpaulo { 0x04, 0x03, 0x00, 0x00 }, 1984201209Srpaulo { 0x04, 0x03, 0x00, 0x07 }, 1985201209Srpaulo { 0x04, 0x03, 0x00, 0x00 }, 1986201209Srpaulo { 0x04, 0x03, 0x00, 0x03 }, 1987201209Srpaulo { 0x04, 0x03, 0x00, 0x03 }, 1988201209Srpaulo { 0x04, 0x03, 0x00, 0x00 }, 1989201209Srpaulo { 0x06, 0x03, 0x00, 0x07 }, 1990201209Srpaulo { 0x04, 0x03, 0x00, 0x00 }, 1991201209Srpaulo { 0x06, 0x06, 0x00, 0x03 }, 1992201209Srpaulo { 0x04, 0x03, 0x00, 0x07 }, 1993201209Srpaulo { 0x04, 0x03, 0x00, 0x00 }, 1994201209Srpaulo { 0x04, 0x03, 0x00, 0x00 } 1995201209Srpaulo}; 1996201209Srpaulo 1997198429Srpaulo/* Firmware errors. */ 1998198429Srpaulostatic const char * const iwn_fw_errmsg[] = { 1999198429Srpaulo "OK", 2000198429Srpaulo "FAIL", 2001198429Srpaulo "BAD_PARAM", 2002198429Srpaulo "BAD_CHECKSUM", 2003198429Srpaulo "NMI_INTERRUPT_WDG", 2004198429Srpaulo "SYSASSERT", 2005198429Srpaulo "FATAL_ERROR", 2006198429Srpaulo "BAD_COMMAND", 2007198429Srpaulo "HW_ERROR_TUNE_LOCK", 2008198429Srpaulo "HW_ERROR_TEMPERATURE", 2009198429Srpaulo "ILLEGAL_CHAN_FREQ", 2010198429Srpaulo "VCC_NOT_STABLE", 2011198429Srpaulo "FH_ERROR", 2012198429Srpaulo "NMI_INTERRUPT_HOST", 2013198429Srpaulo "NMI_INTERRUPT_ACTION_PT", 2014198429Srpaulo "NMI_INTERRUPT_UNKNOWN", 2015198429Srpaulo "UCODE_VERSION_MISMATCH", 2016198429Srpaulo "HW_ERROR_ABS_LOCK", 2017198429Srpaulo "HW_ERROR_CAL_LOCK_FAIL", 2018198429Srpaulo "NMI_INTERRUPT_INST_ACTION_PT", 2019198429Srpaulo "NMI_INTERRUPT_DATA_ACTION_PT", 2020198429Srpaulo "NMI_TRM_HW_ER", 2021198429Srpaulo "NMI_INTERRUPT_TRM", 2022264779Sbrueffer "NMI_INTERRUPT_BREAKPOINT", 2023198429Srpaulo "DEBUG_0", 2024198429Srpaulo "DEBUG_1", 2025198429Srpaulo "DEBUG_2", 2026198429Srpaulo "DEBUG_3", 2027206444Sbschmidt "ADVANCED_SYSASSERT" 2028198429Srpaulo}; 2029198429Srpaulo 2030198429Srpaulo/* Find least significant bit that is set. */ 2031198429Srpaulo#define IWN_LSB(x) ((((x) - 1) & (x)) ^ (x)) 2032198429Srpaulo 2033178676Ssam#define IWN_READ(sc, reg) \ 2034178676Ssam bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 2035178676Ssam 2036178676Ssam#define IWN_WRITE(sc, reg, val) \ 2037178676Ssam bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 2038178676Ssam 2039201209Srpaulo#define IWN_WRITE_1(sc, reg, val) \ 2040201209Srpaulo bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 2041201209Srpaulo 2042198429Srpaulo#define IWN_SETBITS(sc, reg, mask) \ 2043198429Srpaulo IWN_WRITE(sc, reg, IWN_READ(sc, reg) | (mask)) 2044198429Srpaulo 2045198429Srpaulo#define IWN_CLRBITS(sc, reg, mask) \ 2046198429Srpaulo IWN_WRITE(sc, reg, IWN_READ(sc, reg) & ~(mask)) 2047201209Srpaulo 2048201209Srpaulo#define IWN_BARRIER_WRITE(sc) \ 2049201209Srpaulo bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 2050201209Srpaulo BUS_SPACE_BARRIER_WRITE) 2051201209Srpaulo 2052201209Srpaulo#define IWN_BARRIER_READ_WRITE(sc) \ 2053201209Srpaulo bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 2054201209Srpaulo BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 2055