1/*- 2 * Copyright (c) 2012 Chelsio Communications, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD$"); 29 30#include "opt_inet.h" 31 32#include "common.h" 33#include "t4_regs.h" 34#include "t4_regs_values.h" 35#include "firmware/t4fw_interface.h" 36 37#undef msleep 38#define msleep(x) do { \ 39 if (cold) \ 40 DELAY((x) * 1000); \ 41 else \ 42 pause("t4hw", (x) * hz / 1000); \ 43} while (0) 44 45/** 46 * t4_wait_op_done_val - wait until an operation is completed 47 * @adapter: the adapter performing the operation 48 * @reg: the register to check for completion 49 * @mask: a single-bit field within @reg that indicates completion 50 * @polarity: the value of the field when the operation is completed 51 * @attempts: number of check iterations 52 * @delay: delay in usecs between iterations 53 * @valp: where to store the value of the register at completion time 54 * 55 * Wait until an operation is completed by checking a bit in a register 56 * up to @attempts times. If @valp is not NULL the value of the register 57 * at the time it indicated completion is stored there. Returns 0 if the 58 * operation completes and -EAGAIN otherwise. 59 */ 60int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, 61 int polarity, int attempts, int delay, u32 *valp) 62{ 63 while (1) { 64 u32 val = t4_read_reg(adapter, reg); 65 66 if (!!(val & mask) == polarity) { 67 if (valp) 68 *valp = val; 69 return 0; 70 } 71 if (--attempts == 0) 72 return -EAGAIN; 73 if (delay) 74 udelay(delay); 75 } 76} 77 78/** 79 * t4_set_reg_field - set a register field to a value 80 * @adapter: the adapter to program 81 * @addr: the register address 82 * @mask: specifies the portion of the register to modify 83 * @val: the new value for the register field 84 * 85 * Sets a register field specified by the supplied mask to the 86 * given value. 87 */ 88void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask, 89 u32 val) 90{ 91 u32 v = t4_read_reg(adapter, addr) & ~mask; 92 93 t4_write_reg(adapter, addr, v | val); 94 (void) t4_read_reg(adapter, addr); /* flush */ 95} 96 97/** 98 * t4_read_indirect - read indirectly addressed registers 99 * @adap: the adapter 100 * @addr_reg: register holding the indirect address 101 * @data_reg: register holding the value of the indirect register 102 * @vals: where the read register values are stored 103 * @nregs: how many indirect registers to read 104 * @start_idx: index of first indirect register to read 105 * 106 * Reads registers that are accessed indirectly through an address/data 107 * register pair. 108 */ 109void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 110 unsigned int data_reg, u32 *vals, unsigned int nregs, 111 unsigned int start_idx) 112{ 113 while (nregs--) { 114 t4_write_reg(adap, addr_reg, start_idx); 115 *vals++ = t4_read_reg(adap, data_reg); 116 start_idx++; 117 } 118} 119 120/** 121 * t4_write_indirect - write indirectly addressed registers 122 * @adap: the adapter 123 * @addr_reg: register holding the indirect addresses 124 * @data_reg: register holding the value for the indirect registers 125 * @vals: values to write 126 * @nregs: how many indirect registers to write 127 * @start_idx: address of first indirect register to write 128 * 129 * Writes a sequential block of registers that are accessed indirectly 130 * through an address/data register pair. 131 */ 132void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 133 unsigned int data_reg, const u32 *vals, 134 unsigned int nregs, unsigned int start_idx) 135{ 136 while (nregs--) { 137 t4_write_reg(adap, addr_reg, start_idx++); 138 t4_write_reg(adap, data_reg, *vals++); 139 } 140} 141 142/* 143 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor 144 * mechanism. This guarantees that we get the real value even if we're 145 * operating within a Virtual Machine and the Hypervisor is trapping our 146 * Configuration Space accesses. 147 */ 148u32 t4_hw_pci_read_cfg4(adapter_t *adap, int reg) 149{ 150 t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, 151 F_ENABLE | F_LOCALCFG | V_FUNCTION(adap->pf) | 152 V_REGISTER(reg)); 153 return t4_read_reg(adap, A_PCIE_CFG_SPACE_DATA); 154} 155 156/* 157 * t4_report_fw_error - report firmware error 158 * @adap: the adapter 159 * 160 * The adapter firmware can indicate error conditions to the host. 161 * This routine prints out the reason for the firmware error (as 162 * reported by the firmware). 163 */ 164static void t4_report_fw_error(struct adapter *adap) 165{ 166 static const char *reason[] = { 167 "Crash", /* PCIE_FW_EVAL_CRASH */ 168 "During Device Preparation", /* PCIE_FW_EVAL_PREP */ 169 "During Device Configuration", /* PCIE_FW_EVAL_CONF */ 170 "During Device Initialization", /* PCIE_FW_EVAL_INIT */ 171 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */ 172 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */ 173 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */ 174 "Reserved", /* reserved */ 175 }; 176 u32 pcie_fw; 177 178 pcie_fw = t4_read_reg(adap, A_PCIE_FW); 179 if (pcie_fw & F_PCIE_FW_ERR) 180 CH_ERR(adap, "Firmware reports adapter error: %s\n", 181 reason[G_PCIE_FW_EVAL(pcie_fw)]); 182} 183 184/* 185 * Get the reply to a mailbox command and store it in @rpl in big-endian order. 186 */ 187static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit, 188 u32 mbox_addr) 189{ 190 for ( ; nflit; nflit--, mbox_addr += 8) 191 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr)); 192} 193 194/* 195 * Handle a FW assertion reported in a mailbox. 196 */ 197static void fw_asrt(struct adapter *adap, u32 mbox_addr) 198{ 199 struct fw_debug_cmd asrt; 200 201 get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr); 202 CH_ALERT(adap, "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n", 203 asrt.u.assert.filename_0_7, ntohl(asrt.u.assert.line), 204 ntohl(asrt.u.assert.x), ntohl(asrt.u.assert.y)); 205} 206 207#define X_CIM_PF_NOACCESS 0xeeeeeeee 208/** 209 * t4_wr_mbox_meat - send a command to FW through the given mailbox 210 * @adap: the adapter 211 * @mbox: index of the mailbox to use 212 * @cmd: the command to write 213 * @size: command length in bytes 214 * @rpl: where to optionally store the reply 215 * @sleep_ok: if true we may sleep while awaiting command completion 216 * 217 * Sends the given command to FW through the selected mailbox and waits 218 * for the FW to execute the command. If @rpl is not %NULL it is used to 219 * store the FW's reply to the command. The command and its optional 220 * reply are of the same length. Some FW commands like RESET and 221 * INITIALIZE can take a considerable amount of time to execute. 222 * @sleep_ok determines whether we may sleep while awaiting the response. 223 * If sleeping is allowed we use progressive backoff otherwise we spin. 224 * 225 * The return value is 0 on success or a negative errno on failure. A 226 * failure can happen either because we are not able to execute the 227 * command or FW executes it but signals an error. In the latter case 228 * the return value is the error code indicated by FW (negated). 229 */ 230int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 231 void *rpl, bool sleep_ok) 232{ 233 /* 234 * We delay in small increments at first in an effort to maintain 235 * responsiveness for simple, fast executing commands but then back 236 * off to larger delays to a maximum retry delay. 237 */ 238 static const int delay[] = { 239 1, 1, 3, 5, 10, 10, 20, 50, 100 240 }; 241 242 u32 v; 243 u64 res; 244 int i, ms, delay_idx; 245 const __be64 *p = cmd; 246 u32 data_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_DATA); 247 u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL); 248 249 if ((size & 15) || size > MBOX_LEN) 250 return -EINVAL; 251 252 v = G_MBOWNER(t4_read_reg(adap, ctl_reg)); 253 for (i = 0; v == X_MBOWNER_NONE && i < 3; i++) 254 v = G_MBOWNER(t4_read_reg(adap, ctl_reg)); 255 256 if (v != X_MBOWNER_PL) 257 return v ? -EBUSY : -ETIMEDOUT; 258 259 for (i = 0; i < size; i += 8, p++) 260 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p)); 261 262 t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW)); 263 t4_read_reg(adap, ctl_reg); /* flush write */ 264 265 delay_idx = 0; 266 ms = delay[0]; 267 268 for (i = 0; i < FW_CMD_MAX_TIMEOUT; i += ms) { 269 if (sleep_ok) { 270 ms = delay[delay_idx]; /* last element may repeat */ 271 if (delay_idx < ARRAY_SIZE(delay) - 1) 272 delay_idx++; 273 msleep(ms); 274 } else 275 mdelay(ms); 276 277 v = t4_read_reg(adap, ctl_reg); 278 if (v == X_CIM_PF_NOACCESS) 279 continue; 280 if (G_MBOWNER(v) == X_MBOWNER_PL) { 281 if (!(v & F_MBMSGVALID)) { 282 t4_write_reg(adap, ctl_reg, 283 V_MBOWNER(X_MBOWNER_NONE)); 284 continue; 285 } 286 287 res = t4_read_reg64(adap, data_reg); 288 if (G_FW_CMD_OP(res >> 32) == FW_DEBUG_CMD) { 289 fw_asrt(adap, data_reg); 290 res = V_FW_CMD_RETVAL(EIO); 291 } else if (rpl) 292 get_mbox_rpl(adap, rpl, size / 8, data_reg); 293 t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE)); 294 return -G_FW_CMD_RETVAL((int)res); 295 } 296 } 297 298 /* 299 * We timed out waiting for a reply to our mailbox command. Report 300 * the error and also check to see if the firmware reported any 301 * errors ... 302 */ 303 CH_ERR(adap, "command %#x in mailbox %d timed out\n", 304 *(const u8 *)cmd, mbox); 305 if (t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_ERR) 306 t4_report_fw_error(adap); 307 return -ETIMEDOUT; 308} 309 310/** 311 * t4_mc_read - read from MC through backdoor accesses 312 * @adap: the adapter 313 * @idx: which MC to access 314 * @addr: address of first byte requested 315 * @data: 64 bytes of data containing the requested address 316 * @ecc: where to store the corresponding 64-bit ECC word 317 * 318 * Read 64 bytes of data from MC starting at a 64-byte-aligned address 319 * that covers the requested address @addr. If @parity is not %NULL it 320 * is assigned the 64-bit ECC word for the read data. 321 */ 322int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc) 323{ 324 int i; 325 u32 mc_bist_cmd_reg, mc_bist_cmd_addr_reg, mc_bist_cmd_len_reg; 326 u32 mc_bist_status_rdata_reg, mc_bist_data_pattern_reg; 327 328 if (is_t4(adap)) { 329 mc_bist_cmd_reg = A_MC_BIST_CMD; 330 mc_bist_cmd_addr_reg = A_MC_BIST_CMD_ADDR; 331 mc_bist_cmd_len_reg = A_MC_BIST_CMD_LEN; 332 mc_bist_status_rdata_reg = A_MC_BIST_STATUS_RDATA; 333 mc_bist_data_pattern_reg = A_MC_BIST_DATA_PATTERN; 334 } else { 335 mc_bist_cmd_reg = MC_REG(A_MC_P_BIST_CMD, idx); 336 mc_bist_cmd_addr_reg = MC_REG(A_MC_P_BIST_CMD_ADDR, idx); 337 mc_bist_cmd_len_reg = MC_REG(A_MC_P_BIST_CMD_LEN, idx); 338 mc_bist_status_rdata_reg = MC_REG(A_MC_P_BIST_STATUS_RDATA, 339 idx); 340 mc_bist_data_pattern_reg = MC_REG(A_MC_P_BIST_DATA_PATTERN, 341 idx); 342 } 343 344 if (t4_read_reg(adap, mc_bist_cmd_reg) & F_START_BIST) 345 return -EBUSY; 346 t4_write_reg(adap, mc_bist_cmd_addr_reg, addr & ~0x3fU); 347 t4_write_reg(adap, mc_bist_cmd_len_reg, 64); 348 t4_write_reg(adap, mc_bist_data_pattern_reg, 0xc); 349 t4_write_reg(adap, mc_bist_cmd_reg, V_BIST_OPCODE(1) | 350 F_START_BIST | V_BIST_CMD_GAP(1)); 351 i = t4_wait_op_done(adap, mc_bist_cmd_reg, F_START_BIST, 0, 10, 1); 352 if (i) 353 return i; 354 355#define MC_DATA(i) MC_BIST_STATUS_REG(mc_bist_status_rdata_reg, i) 356 357 for (i = 15; i >= 0; i--) 358 *data++ = ntohl(t4_read_reg(adap, MC_DATA(i))); 359 if (ecc) 360 *ecc = t4_read_reg64(adap, MC_DATA(16)); 361#undef MC_DATA 362 return 0; 363} 364 365/** 366 * t4_edc_read - read from EDC through backdoor accesses 367 * @adap: the adapter 368 * @idx: which EDC to access 369 * @addr: address of first byte requested 370 * @data: 64 bytes of data containing the requested address 371 * @ecc: where to store the corresponding 64-bit ECC word 372 * 373 * Read 64 bytes of data from EDC starting at a 64-byte-aligned address 374 * that covers the requested address @addr. If @parity is not %NULL it 375 * is assigned the 64-bit ECC word for the read data. 376 */ 377int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc) 378{ 379 int i; 380 u32 edc_bist_cmd_reg, edc_bist_cmd_addr_reg, edc_bist_cmd_len_reg; 381 u32 edc_bist_cmd_data_pattern, edc_bist_status_rdata_reg; 382 383 if (is_t4(adap)) { 384 edc_bist_cmd_reg = EDC_REG(A_EDC_BIST_CMD, idx); 385 edc_bist_cmd_addr_reg = EDC_REG(A_EDC_BIST_CMD_ADDR, idx); 386 edc_bist_cmd_len_reg = EDC_REG(A_EDC_BIST_CMD_LEN, idx); 387 edc_bist_cmd_data_pattern = EDC_REG(A_EDC_BIST_DATA_PATTERN, 388 idx); 389 edc_bist_status_rdata_reg = EDC_REG(A_EDC_BIST_STATUS_RDATA, 390 idx); 391 } else { 392/* 393 * These macro are missing in t4_regs.h file. 394 * Added temporarily for testing. 395 */ 396#define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR) 397#define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx) 398 edc_bist_cmd_reg = EDC_REG_T5(A_EDC_H_BIST_CMD, idx); 399 edc_bist_cmd_addr_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_ADDR, idx); 400 edc_bist_cmd_len_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_LEN, idx); 401 edc_bist_cmd_data_pattern = EDC_REG_T5(A_EDC_H_BIST_DATA_PATTERN, 402 idx); 403 edc_bist_status_rdata_reg = EDC_REG_T5(A_EDC_H_BIST_STATUS_RDATA, 404 idx); 405#undef EDC_REG_T5 406#undef EDC_STRIDE_T5 407 } 408 409 if (t4_read_reg(adap, edc_bist_cmd_reg) & F_START_BIST) 410 return -EBUSY; 411 t4_write_reg(adap, edc_bist_cmd_addr_reg, addr & ~0x3fU); 412 t4_write_reg(adap, edc_bist_cmd_len_reg, 64); 413 t4_write_reg(adap, edc_bist_cmd_data_pattern, 0xc); 414 t4_write_reg(adap, edc_bist_cmd_reg, 415 V_BIST_OPCODE(1) | V_BIST_CMD_GAP(1) | F_START_BIST); 416 i = t4_wait_op_done(adap, edc_bist_cmd_reg, F_START_BIST, 0, 10, 1); 417 if (i) 418 return i; 419 420#define EDC_DATA(i) EDC_BIST_STATUS_REG(edc_bist_status_rdata_reg, i) 421 422 for (i = 15; i >= 0; i--) 423 *data++ = ntohl(t4_read_reg(adap, EDC_DATA(i))); 424 if (ecc) 425 *ecc = t4_read_reg64(adap, EDC_DATA(16)); 426#undef EDC_DATA 427 return 0; 428} 429 430/** 431 * t4_mem_read - read EDC 0, EDC 1 or MC into buffer 432 * @adap: the adapter 433 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC 434 * @addr: address within indicated memory type 435 * @len: amount of memory to read 436 * @buf: host memory buffer 437 * 438 * Reads an [almost] arbitrary memory region in the firmware: the 439 * firmware memory address, length and host buffer must be aligned on 440 * 32-bit boudaries. The memory is returned as a raw byte sequence from 441 * the firmware's memory. If this memory contains data structures which 442 * contain multi-byte integers, it's the callers responsibility to 443 * perform appropriate byte order conversions. 444 */ 445int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 len, 446 __be32 *buf) 447{ 448 u32 pos, start, end, offset; 449 int ret; 450 451 /* 452 * Argument sanity checks ... 453 */ 454 if ((addr & 0x3) || (len & 0x3)) 455 return -EINVAL; 456 457 /* 458 * The underlaying EDC/MC read routines read 64 bytes at a time so we 459 * need to round down the start and round up the end. We'll start 460 * copying out of the first line at (addr - start) a word at a time. 461 */ 462 start = addr & ~(64-1); 463 end = (addr + len + 64-1) & ~(64-1); 464 offset = (addr - start)/sizeof(__be32); 465 466 for (pos = start; pos < end; pos += 64, offset = 0) { 467 __be32 data[16]; 468 469 /* 470 * Read the chip's memory block and bail if there's an error. 471 */ 472 if ((mtype == MEM_MC) || (mtype == MEM_MC1)) 473 ret = t4_mc_read(adap, mtype - MEM_MC, pos, data, NULL); 474 else 475 ret = t4_edc_read(adap, mtype, pos, data, NULL); 476 if (ret) 477 return ret; 478 479 /* 480 * Copy the data into the caller's memory buffer. 481 */ 482 while (offset < 16 && len > 0) { 483 *buf++ = data[offset++]; 484 len -= sizeof(__be32); 485 } 486 } 487 488 return 0; 489} 490 491/* 492 * Partial EEPROM Vital Product Data structure. Includes only the ID and 493 * VPD-R header. 494 */ 495struct t4_vpd_hdr { 496 u8 id_tag; 497 u8 id_len[2]; 498 u8 id_data[ID_LEN]; 499 u8 vpdr_tag; 500 u8 vpdr_len[2]; 501}; 502 503/* 504 * EEPROM reads take a few tens of us while writes can take a bit over 5 ms. 505 */ 506#define EEPROM_MAX_RD_POLL 40 507#define EEPROM_MAX_WR_POLL 6 508#define EEPROM_STAT_ADDR 0x7bfc 509#define VPD_BASE 0x400 510#define VPD_BASE_OLD 0 511#define VPD_LEN 1024 512#define VPD_INFO_FLD_HDR_SIZE 3 513#define CHELSIO_VPD_UNIQUE_ID 0x82 514 515/** 516 * t4_seeprom_read - read a serial EEPROM location 517 * @adapter: adapter to read 518 * @addr: EEPROM virtual address 519 * @data: where to store the read data 520 * 521 * Read a 32-bit word from a location in serial EEPROM using the card's PCI 522 * VPD capability. Note that this function must be called with a virtual 523 * address. 524 */ 525int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data) 526{ 527 u16 val; 528 int attempts = EEPROM_MAX_RD_POLL; 529 unsigned int base = adapter->params.pci.vpd_cap_addr; 530 531 if (addr >= EEPROMVSIZE || (addr & 3)) 532 return -EINVAL; 533 534 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, (u16)addr); 535 do { 536 udelay(10); 537 t4_os_pci_read_cfg2(adapter, base + PCI_VPD_ADDR, &val); 538 } while (!(val & PCI_VPD_ADDR_F) && --attempts); 539 540 if (!(val & PCI_VPD_ADDR_F)) { 541 CH_ERR(adapter, "reading EEPROM address 0x%x failed\n", addr); 542 return -EIO; 543 } 544 t4_os_pci_read_cfg4(adapter, base + PCI_VPD_DATA, data); 545 *data = le32_to_cpu(*data); 546 return 0; 547} 548 549/** 550 * t4_seeprom_write - write a serial EEPROM location 551 * @adapter: adapter to write 552 * @addr: virtual EEPROM address 553 * @data: value to write 554 * 555 * Write a 32-bit word to a location in serial EEPROM using the card's PCI 556 * VPD capability. Note that this function must be called with a virtual 557 * address. 558 */ 559int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data) 560{ 561 u16 val; 562 int attempts = EEPROM_MAX_WR_POLL; 563 unsigned int base = adapter->params.pci.vpd_cap_addr; 564 565 if (addr >= EEPROMVSIZE || (addr & 3)) 566 return -EINVAL; 567 568 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 569 cpu_to_le32(data)); 570 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, 571 (u16)addr | PCI_VPD_ADDR_F); 572 do { 573 msleep(1); 574 t4_os_pci_read_cfg2(adapter, base + PCI_VPD_ADDR, &val); 575 } while ((val & PCI_VPD_ADDR_F) && --attempts); 576 577 if (val & PCI_VPD_ADDR_F) { 578 CH_ERR(adapter, "write to EEPROM address 0x%x failed\n", addr); 579 return -EIO; 580 } 581 return 0; 582} 583 584/** 585 * t4_eeprom_ptov - translate a physical EEPROM address to virtual 586 * @phys_addr: the physical EEPROM address 587 * @fn: the PCI function number 588 * @sz: size of function-specific area 589 * 590 * Translate a physical EEPROM address to virtual. The first 1K is 591 * accessed through virtual addresses starting at 31K, the rest is 592 * accessed through virtual addresses starting at 0. 593 * 594 * The mapping is as follows: 595 * [0..1K) -> [31K..32K) 596 * [1K..1K+A) -> [ES-A..ES) 597 * [1K+A..ES) -> [0..ES-A-1K) 598 * 599 * where A = @fn * @sz, and ES = EEPROM size. 600 */ 601int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz) 602{ 603 fn *= sz; 604 if (phys_addr < 1024) 605 return phys_addr + (31 << 10); 606 if (phys_addr < 1024 + fn) 607 return EEPROMSIZE - fn + phys_addr - 1024; 608 if (phys_addr < EEPROMSIZE) 609 return phys_addr - 1024 - fn; 610 return -EINVAL; 611} 612 613/** 614 * t4_seeprom_wp - enable/disable EEPROM write protection 615 * @adapter: the adapter 616 * @enable: whether to enable or disable write protection 617 * 618 * Enables or disables write protection on the serial EEPROM. 619 */ 620int t4_seeprom_wp(struct adapter *adapter, int enable) 621{ 622 return t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0); 623} 624 625/** 626 * get_vpd_keyword_val - Locates an information field keyword in the VPD 627 * @v: Pointer to buffered vpd data structure 628 * @kw: The keyword to search for 629 * 630 * Returns the value of the information field keyword or 631 * -ENOENT otherwise. 632 */ 633static int get_vpd_keyword_val(const struct t4_vpd_hdr *v, const char *kw) 634{ 635 int i; 636 unsigned int offset , len; 637 const u8 *buf = &v->id_tag; 638 const u8 *vpdr_len = &v->vpdr_tag; 639 offset = sizeof(struct t4_vpd_hdr); 640 len = (u16)vpdr_len[1] + ((u16)vpdr_len[2] << 8); 641 642 if (len + sizeof(struct t4_vpd_hdr) > VPD_LEN) { 643 return -ENOENT; 644 } 645 646 for (i = offset; i + VPD_INFO_FLD_HDR_SIZE <= offset + len;) { 647 if(memcmp(buf + i , kw , 2) == 0){ 648 i += VPD_INFO_FLD_HDR_SIZE; 649 return i; 650 } 651 652 i += VPD_INFO_FLD_HDR_SIZE + buf[i+2]; 653 } 654 655 return -ENOENT; 656} 657 658 659/** 660 * get_vpd_params - read VPD parameters from VPD EEPROM 661 * @adapter: adapter to read 662 * @p: where to store the parameters 663 * 664 * Reads card parameters stored in VPD EEPROM. 665 */ 666static int get_vpd_params(struct adapter *adapter, struct vpd_params *p) 667{ 668 int i, ret, addr; 669 int ec, sn, pn, na; 670 u8 vpd[VPD_LEN], csum; 671 const struct t4_vpd_hdr *v; 672 673 /* 674 * Card information normally starts at VPD_BASE but early cards had 675 * it at 0. 676 */ 677 ret = t4_seeprom_read(adapter, VPD_BASE, (u32 *)(vpd)); 678 addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD; 679 680 for (i = 0; i < sizeof(vpd); i += 4) { 681 ret = t4_seeprom_read(adapter, addr + i, (u32 *)(vpd + i)); 682 if (ret) 683 return ret; 684 } 685 v = (const struct t4_vpd_hdr *)vpd; 686 687#define FIND_VPD_KW(var,name) do { \ 688 var = get_vpd_keyword_val(v , name); \ 689 if (var < 0) { \ 690 CH_ERR(adapter, "missing VPD keyword " name "\n"); \ 691 return -EINVAL; \ 692 } \ 693} while (0) 694 695 FIND_VPD_KW(i, "RV"); 696 for (csum = 0; i >= 0; i--) 697 csum += vpd[i]; 698 699 if (csum) { 700 CH_ERR(adapter, "corrupted VPD EEPROM, actual csum %u\n", csum); 701 return -EINVAL; 702 } 703 FIND_VPD_KW(ec, "EC"); 704 FIND_VPD_KW(sn, "SN"); 705 FIND_VPD_KW(pn, "PN"); 706 FIND_VPD_KW(na, "NA"); 707#undef FIND_VPD_KW 708 709 memcpy(p->id, v->id_data, ID_LEN); 710 strstrip(p->id); 711 memcpy(p->ec, vpd + ec, EC_LEN); 712 strstrip(p->ec); 713 i = vpd[sn - VPD_INFO_FLD_HDR_SIZE + 2]; 714 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN)); 715 strstrip(p->sn); 716 i = vpd[pn - VPD_INFO_FLD_HDR_SIZE + 2]; 717 memcpy(p->pn, vpd + pn, min(i, PN_LEN)); 718 strstrip((char *)p->pn); 719 i = vpd[na - VPD_INFO_FLD_HDR_SIZE + 2]; 720 memcpy(p->na, vpd + na, min(i, MACADDR_LEN)); 721 strstrip((char *)p->na); 722 723 return 0; 724} 725 726/* serial flash and firmware constants and flash config file constants */ 727enum { 728 SF_ATTEMPTS = 10, /* max retries for SF operations */ 729 730 /* flash command opcodes */ 731 SF_PROG_PAGE = 2, /* program page */ 732 SF_WR_DISABLE = 4, /* disable writes */ 733 SF_RD_STATUS = 5, /* read status register */ 734 SF_WR_ENABLE = 6, /* enable writes */ 735 SF_RD_DATA_FAST = 0xb, /* read flash */ 736 SF_RD_ID = 0x9f, /* read ID */ 737 SF_ERASE_SECTOR = 0xd8, /* erase sector */ 738}; 739 740/** 741 * sf1_read - read data from the serial flash 742 * @adapter: the adapter 743 * @byte_cnt: number of bytes to read 744 * @cont: whether another operation will be chained 745 * @lock: whether to lock SF for PL access only 746 * @valp: where to store the read data 747 * 748 * Reads up to 4 bytes of data from the serial flash. The location of 749 * the read needs to be specified prior to calling this by issuing the 750 * appropriate commands to the serial flash. 751 */ 752static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont, 753 int lock, u32 *valp) 754{ 755 int ret; 756 757 if (!byte_cnt || byte_cnt > 4) 758 return -EINVAL; 759 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY) 760 return -EBUSY; 761 t4_write_reg(adapter, A_SF_OP, 762 V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1)); 763 ret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5); 764 if (!ret) 765 *valp = t4_read_reg(adapter, A_SF_DATA); 766 return ret; 767} 768 769/** 770 * sf1_write - write data to the serial flash 771 * @adapter: the adapter 772 * @byte_cnt: number of bytes to write 773 * @cont: whether another operation will be chained 774 * @lock: whether to lock SF for PL access only 775 * @val: value to write 776 * 777 * Writes up to 4 bytes of data to the serial flash. The location of 778 * the write needs to be specified prior to calling this by issuing the 779 * appropriate commands to the serial flash. 780 */ 781static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont, 782 int lock, u32 val) 783{ 784 if (!byte_cnt || byte_cnt > 4) 785 return -EINVAL; 786 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY) 787 return -EBUSY; 788 t4_write_reg(adapter, A_SF_DATA, val); 789 t4_write_reg(adapter, A_SF_OP, V_SF_LOCK(lock) | 790 V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1)); 791 return t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5); 792} 793 794/** 795 * flash_wait_op - wait for a flash operation to complete 796 * @adapter: the adapter 797 * @attempts: max number of polls of the status register 798 * @delay: delay between polls in ms 799 * 800 * Wait for a flash operation to complete by polling the status register. 801 */ 802static int flash_wait_op(struct adapter *adapter, int attempts, int delay) 803{ 804 int ret; 805 u32 status; 806 807 while (1) { 808 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 || 809 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0) 810 return ret; 811 if (!(status & 1)) 812 return 0; 813 if (--attempts == 0) 814 return -EAGAIN; 815 if (delay) 816 msleep(delay); 817 } 818} 819 820/** 821 * t4_read_flash - read words from serial flash 822 * @adapter: the adapter 823 * @addr: the start address for the read 824 * @nwords: how many 32-bit words to read 825 * @data: where to store the read data 826 * @byte_oriented: whether to store data as bytes or as words 827 * 828 * Read the specified number of 32-bit words from the serial flash. 829 * If @byte_oriented is set the read data is stored as a byte array 830 * (i.e., big-endian), otherwise as 32-bit words in the platform's 831 * natural endianess. 832 */ 833int t4_read_flash(struct adapter *adapter, unsigned int addr, 834 unsigned int nwords, u32 *data, int byte_oriented) 835{ 836 int ret; 837 838 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3)) 839 return -EINVAL; 840 841 addr = swab32(addr) | SF_RD_DATA_FAST; 842 843 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 || 844 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0) 845 return ret; 846 847 for ( ; nwords; nwords--, data++) { 848 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data); 849 if (nwords == 1) 850 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 851 if (ret) 852 return ret; 853 if (byte_oriented) 854 *data = htonl(*data); 855 } 856 return 0; 857} 858 859/** 860 * t4_write_flash - write up to a page of data to the serial flash 861 * @adapter: the adapter 862 * @addr: the start address to write 863 * @n: length of data to write in bytes 864 * @data: the data to write 865 * @byte_oriented: whether to store data as bytes or as words 866 * 867 * Writes up to a page of data (256 bytes) to the serial flash starting 868 * at the given address. All the data must be written to the same page. 869 * If @byte_oriented is set the write data is stored as byte stream 870 * (i.e. matches what on disk), otherwise in big-endian. 871 */ 872static int t4_write_flash(struct adapter *adapter, unsigned int addr, 873 unsigned int n, const u8 *data, int byte_oriented) 874{ 875 int ret; 876 u32 buf[SF_PAGE_SIZE / 4]; 877 unsigned int i, c, left, val, offset = addr & 0xff; 878 879 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE) 880 return -EINVAL; 881 882 val = swab32(addr) | SF_PROG_PAGE; 883 884 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 || 885 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0) 886 goto unlock; 887 888 for (left = n; left; left -= c) { 889 c = min(left, 4U); 890 for (val = 0, i = 0; i < c; ++i) 891 val = (val << 8) + *data++; 892 893 if (!byte_oriented) 894 val = htonl(val); 895 896 ret = sf1_write(adapter, c, c != left, 1, val); 897 if (ret) 898 goto unlock; 899 } 900 ret = flash_wait_op(adapter, 8, 1); 901 if (ret) 902 goto unlock; 903 904 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 905 906 /* Read the page to verify the write succeeded */ 907 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 908 byte_oriented); 909 if (ret) 910 return ret; 911 912 if (memcmp(data - n, (u8 *)buf + offset, n)) { 913 CH_ERR(adapter, "failed to correctly write the flash page " 914 "at %#x\n", addr); 915 return -EIO; 916 } 917 return 0; 918 919unlock: 920 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 921 return ret; 922} 923 924/** 925 * t4_get_fw_version - read the firmware version 926 * @adapter: the adapter 927 * @vers: where to place the version 928 * 929 * Reads the FW version from flash. 930 */ 931int t4_get_fw_version(struct adapter *adapter, u32 *vers) 932{ 933 return t4_read_flash(adapter, 934 FLASH_FW_START + offsetof(struct fw_hdr, fw_ver), 1, 935 vers, 0); 936} 937 938/** 939 * t4_get_tp_version - read the TP microcode version 940 * @adapter: the adapter 941 * @vers: where to place the version 942 * 943 * Reads the TP microcode version from flash. 944 */ 945int t4_get_tp_version(struct adapter *adapter, u32 *vers) 946{ 947 return t4_read_flash(adapter, FLASH_FW_START + offsetof(struct fw_hdr, 948 tp_microcode_ver), 949 1, vers, 0); 950} 951 952/** 953 * t4_check_fw_version - check if the FW is compatible with this driver 954 * @adapter: the adapter 955 * 956 * Checks if an adapter's FW is compatible with the driver. Returns 0 957 * if there's exact match, a negative error if the version could not be 958 * read or there's a major version mismatch, and a positive value if the 959 * expected major version is found but there's a minor version mismatch. 960 */ 961int t4_check_fw_version(struct adapter *adapter) 962{ 963 int ret, major, minor, micro; 964 int exp_major, exp_minor, exp_micro; 965 966 ret = t4_get_fw_version(adapter, &adapter->params.fw_vers); 967 if (!ret) 968 ret = t4_get_tp_version(adapter, &adapter->params.tp_vers); 969 if (ret) 970 return ret; 971 972 major = G_FW_HDR_FW_VER_MAJOR(adapter->params.fw_vers); 973 minor = G_FW_HDR_FW_VER_MINOR(adapter->params.fw_vers); 974 micro = G_FW_HDR_FW_VER_MICRO(adapter->params.fw_vers); 975 976 switch (chip_id(adapter)) { 977 case CHELSIO_T4: 978 exp_major = T4FW_VERSION_MAJOR; 979 exp_minor = T4FW_VERSION_MINOR; 980 exp_micro = T4FW_VERSION_MICRO; 981 break; 982 case CHELSIO_T5: 983 exp_major = T5FW_VERSION_MAJOR; 984 exp_minor = T5FW_VERSION_MINOR; 985 exp_micro = T5FW_VERSION_MICRO; 986 break; 987 default: 988 CH_ERR(adapter, "Unsupported chip type, %x\n", 989 chip_id(adapter)); 990 return -EINVAL; 991 } 992 993 if (major != exp_major) { /* major mismatch - fail */ 994 CH_ERR(adapter, "card FW has major version %u, driver wants " 995 "%u\n", major, exp_major); 996 return -EINVAL; 997 } 998 999 if (minor == exp_minor && micro == exp_micro) 1000 return 0; /* perfect match */ 1001 1002 /* Minor/micro version mismatch. Report it but often it's OK. */ 1003 return 1; 1004} 1005 1006/** 1007 * t4_flash_erase_sectors - erase a range of flash sectors 1008 * @adapter: the adapter 1009 * @start: the first sector to erase 1010 * @end: the last sector to erase 1011 * 1012 * Erases the sectors in the given inclusive range. 1013 */ 1014static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end) 1015{ 1016 int ret = 0; 1017 1018 while (start <= end) { 1019 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 || 1020 (ret = sf1_write(adapter, 4, 0, 1, 1021 SF_ERASE_SECTOR | (start << 8))) != 0 || 1022 (ret = flash_wait_op(adapter, 14, 500)) != 0) { 1023 CH_ERR(adapter, "erase of flash sector %d failed, " 1024 "error %d\n", start, ret); 1025 break; 1026 } 1027 start++; 1028 } 1029 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 1030 return ret; 1031} 1032 1033/** 1034 * t4_flash_cfg_addr - return the address of the flash configuration file 1035 * @adapter: the adapter 1036 * 1037 * Return the address within the flash where the Firmware Configuration 1038 * File is stored, or an error if the device FLASH is too small to contain 1039 * a Firmware Configuration File. 1040 */ 1041int t4_flash_cfg_addr(struct adapter *adapter) 1042{ 1043 /* 1044 * If the device FLASH isn't large enough to hold a Firmware 1045 * Configuration File, return an error. 1046 */ 1047 if (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE) 1048 return -ENOSPC; 1049 1050 return FLASH_CFG_START; 1051} 1052 1053/** 1054 * t4_load_cfg - download config file 1055 * @adap: the adapter 1056 * @cfg_data: the cfg text file to write 1057 * @size: text file size 1058 * 1059 * Write the supplied config text file to the card's serial flash. 1060 */ 1061int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size) 1062{ 1063 int ret, i, n, cfg_addr; 1064 unsigned int addr; 1065 unsigned int flash_cfg_start_sec; 1066 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 1067 1068 cfg_addr = t4_flash_cfg_addr(adap); 1069 if (cfg_addr < 0) 1070 return cfg_addr; 1071 1072 addr = cfg_addr; 1073 flash_cfg_start_sec = addr / SF_SEC_SIZE; 1074 1075 if (size > FLASH_CFG_MAX_SIZE) { 1076 CH_ERR(adap, "cfg file too large, max is %u bytes\n", 1077 FLASH_CFG_MAX_SIZE); 1078 return -EFBIG; 1079 } 1080 1081 i = DIV_ROUND_UP(FLASH_CFG_MAX_SIZE, /* # of sectors spanned */ 1082 sf_sec_size); 1083 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec, 1084 flash_cfg_start_sec + i - 1); 1085 /* 1086 * If size == 0 then we're simply erasing the FLASH sectors associated 1087 * with the on-adapter Firmware Configuration File. 1088 */ 1089 if (ret || size == 0) 1090 goto out; 1091 1092 /* this will write to the flash up to SF_PAGE_SIZE at a time */ 1093 for (i = 0; i< size; i+= SF_PAGE_SIZE) { 1094 if ( (size - i) < SF_PAGE_SIZE) 1095 n = size - i; 1096 else 1097 n = SF_PAGE_SIZE; 1098 ret = t4_write_flash(adap, addr, n, cfg_data, 1); 1099 if (ret) 1100 goto out; 1101 1102 addr += SF_PAGE_SIZE; 1103 cfg_data += SF_PAGE_SIZE; 1104 } 1105 1106out: 1107 if (ret) 1108 CH_ERR(adap, "config file %s failed %d\n", 1109 (size == 0 ? "clear" : "download"), ret); 1110 return ret; 1111} 1112 1113 1114/** 1115 * t4_load_fw - download firmware 1116 * @adap: the adapter 1117 * @fw_data: the firmware image to write 1118 * @size: image size 1119 * 1120 * Write the supplied firmware image to the card's serial flash. 1121 */ 1122int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size) 1123{ 1124 u32 csum; 1125 int ret, addr; 1126 unsigned int i; 1127 u8 first_page[SF_PAGE_SIZE]; 1128 const u32 *p = (const u32 *)fw_data; 1129 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data; 1130 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 1131 unsigned int fw_start_sec; 1132 unsigned int fw_start; 1133 unsigned int fw_size; 1134 1135 if (ntohl(hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP) { 1136 fw_start_sec = FLASH_FWBOOTSTRAP_START_SEC; 1137 fw_start = FLASH_FWBOOTSTRAP_START; 1138 fw_size = FLASH_FWBOOTSTRAP_MAX_SIZE; 1139 } else { 1140 fw_start_sec = FLASH_FW_START_SEC; 1141 fw_start = FLASH_FW_START; 1142 fw_size = FLASH_FW_MAX_SIZE; 1143 } 1144 if (!size) { 1145 CH_ERR(adap, "FW image has no data\n"); 1146 return -EINVAL; 1147 } 1148 if (size & 511) { 1149 CH_ERR(adap, "FW image size not multiple of 512 bytes\n"); 1150 return -EINVAL; 1151 } 1152 if (ntohs(hdr->len512) * 512 != size) { 1153 CH_ERR(adap, "FW image size differs from size in FW header\n"); 1154 return -EINVAL; 1155 } 1156 if (size > fw_size) { 1157 CH_ERR(adap, "FW image too large, max is %u bytes\n", fw_size); 1158 return -EFBIG; 1159 } 1160 if ((is_t4(adap) && hdr->chip != FW_HDR_CHIP_T4) || 1161 (is_t5(adap) && hdr->chip != FW_HDR_CHIP_T5)) { 1162 CH_ERR(adap, 1163 "FW image (%d) is not suitable for this adapter (%d)\n", 1164 hdr->chip, chip_id(adap)); 1165 return -EINVAL; 1166 } 1167 1168 for (csum = 0, i = 0; i < size / sizeof(csum); i++) 1169 csum += ntohl(p[i]); 1170 1171 if (csum != 0xffffffff) { 1172 CH_ERR(adap, "corrupted firmware image, checksum %#x\n", 1173 csum); 1174 return -EINVAL; 1175 } 1176 1177 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */ 1178 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1); 1179 if (ret) 1180 goto out; 1181 1182 /* 1183 * We write the correct version at the end so the driver can see a bad 1184 * version if the FW write fails. Start by writing a copy of the 1185 * first page with a bad version. 1186 */ 1187 memcpy(first_page, fw_data, SF_PAGE_SIZE); 1188 ((struct fw_hdr *)first_page)->fw_ver = htonl(0xffffffff); 1189 ret = t4_write_flash(adap, fw_start, SF_PAGE_SIZE, first_page, 1); 1190 if (ret) 1191 goto out; 1192 1193 addr = fw_start; 1194 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) { 1195 addr += SF_PAGE_SIZE; 1196 fw_data += SF_PAGE_SIZE; 1197 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data, 1); 1198 if (ret) 1199 goto out; 1200 } 1201 1202 ret = t4_write_flash(adap, 1203 fw_start + offsetof(struct fw_hdr, fw_ver), 1204 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver, 1); 1205out: 1206 if (ret) 1207 CH_ERR(adap, "firmware download failed, error %d\n", ret); 1208 return ret; 1209} 1210 1211/* BIOS boot headers */ 1212typedef struct pci_expansion_rom_header { 1213 u8 signature[2]; /* ROM Signature. Should be 0xaa55 */ 1214 u8 reserved[22]; /* Reserved per processor Architecture data */ 1215 u8 pcir_offset[2]; /* Offset to PCI Data Structure */ 1216} pci_exp_rom_header_t; /* PCI_EXPANSION_ROM_HEADER */ 1217 1218/* Legacy PCI Expansion ROM Header */ 1219typedef struct legacy_pci_expansion_rom_header { 1220 u8 signature[2]; /* ROM Signature. Should be 0xaa55 */ 1221 u8 size512; /* Current Image Size in units of 512 bytes */ 1222 u8 initentry_point[4]; 1223 u8 cksum; /* Checksum computed on the entire Image */ 1224 u8 reserved[16]; /* Reserved */ 1225 u8 pcir_offset[2]; /* Offset to PCI Data Struture */ 1226} legacy_pci_exp_rom_header_t; /* LEGACY_PCI_EXPANSION_ROM_HEADER */ 1227 1228/* EFI PCI Expansion ROM Header */ 1229typedef struct efi_pci_expansion_rom_header { 1230 u8 signature[2]; // ROM signature. The value 0xaa55 1231 u8 initialization_size[2]; /* Units 512. Includes this header */ 1232 u8 efi_signature[4]; /* Signature from EFI image header. 0x0EF1 */ 1233 u8 efi_subsystem[2]; /* Subsystem value for EFI image header */ 1234 u8 efi_machine_type[2]; /* Machine type from EFI image header */ 1235 u8 compression_type[2]; /* Compression type. */ 1236 /* 1237 * Compression type definition 1238 * 0x0: uncompressed 1239 * 0x1: Compressed 1240 * 0x2-0xFFFF: Reserved 1241 */ 1242 u8 reserved[8]; /* Reserved */ 1243 u8 efi_image_header_offset[2]; /* Offset to EFI Image */ 1244 u8 pcir_offset[2]; /* Offset to PCI Data Structure */ 1245} efi_pci_exp_rom_header_t; /* EFI PCI Expansion ROM Header */ 1246 1247/* PCI Data Structure Format */ 1248typedef struct pcir_data_structure { /* PCI Data Structure */ 1249 u8 signature[4]; /* Signature. The string "PCIR" */ 1250 u8 vendor_id[2]; /* Vendor Identification */ 1251 u8 device_id[2]; /* Device Identification */ 1252 u8 vital_product[2]; /* Pointer to Vital Product Data */ 1253 u8 length[2]; /* PCIR Data Structure Length */ 1254 u8 revision; /* PCIR Data Structure Revision */ 1255 u8 class_code[3]; /* Class Code */ 1256 u8 image_length[2]; /* Image Length. Multiple of 512B */ 1257 u8 code_revision[2]; /* Revision Level of Code/Data */ 1258 u8 code_type; /* Code Type. */ 1259 /* 1260 * PCI Expansion ROM Code Types 1261 * 0x00: Intel IA-32, PC-AT compatible. Legacy 1262 * 0x01: Open Firmware standard for PCI. FCODE 1263 * 0x02: Hewlett-Packard PA RISC. HP reserved 1264 * 0x03: EFI Image. EFI 1265 * 0x04-0xFF: Reserved. 1266 */ 1267 u8 indicator; /* Indicator. Identifies the last image in the ROM */ 1268 u8 reserved[2]; /* Reserved */ 1269} pcir_data_t; /* PCI__DATA_STRUCTURE */ 1270 1271/* BOOT constants */ 1272enum { 1273 BOOT_FLASH_BOOT_ADDR = 0x0,/* start address of boot image in flash */ 1274 BOOT_SIGNATURE = 0xaa55, /* signature of BIOS boot ROM */ 1275 BOOT_SIZE_INC = 512, /* image size measured in 512B chunks */ 1276 BOOT_MIN_SIZE = sizeof(pci_exp_rom_header_t), /* basic header */ 1277 BOOT_MAX_SIZE = 1024*BOOT_SIZE_INC, /* 1 byte * length increment */ 1278 VENDOR_ID = 0x1425, /* Vendor ID */ 1279 PCIR_SIGNATURE = 0x52494350 /* PCIR signature */ 1280}; 1281 1282/* 1283 * modify_device_id - Modifies the device ID of the Boot BIOS image 1284 * @adatper: the device ID to write. 1285 * @boot_data: the boot image to modify. 1286 * 1287 * Write the supplied device ID to the boot BIOS image. 1288 */ 1289static void modify_device_id(int device_id, u8 *boot_data) 1290{ 1291 legacy_pci_exp_rom_header_t *header; 1292 pcir_data_t *pcir_header; 1293 u32 cur_header = 0; 1294 1295 /* 1296 * Loop through all chained images and change the device ID's 1297 */ 1298 while (1) { 1299 header = (legacy_pci_exp_rom_header_t *) &boot_data[cur_header]; 1300 pcir_header = (pcir_data_t *) &boot_data[cur_header + 1301 le16_to_cpu(*(u16*)header->pcir_offset)]; 1302 1303 /* 1304 * Only modify the Device ID if code type is Legacy or HP. 1305 * 0x00: Okay to modify 1306 * 0x01: FCODE. Do not be modify 1307 * 0x03: Okay to modify 1308 * 0x04-0xFF: Do not modify 1309 */ 1310 if (pcir_header->code_type == 0x00) { 1311 u8 csum = 0; 1312 int i; 1313 1314 /* 1315 * Modify Device ID to match current adatper 1316 */ 1317 *(u16*) pcir_header->device_id = device_id; 1318 1319 /* 1320 * Set checksum temporarily to 0. 1321 * We will recalculate it later. 1322 */ 1323 header->cksum = 0x0; 1324 1325 /* 1326 * Calculate and update checksum 1327 */ 1328 for (i = 0; i < (header->size512 * 512); i++) 1329 csum += (u8)boot_data[cur_header + i]; 1330 1331 /* 1332 * Invert summed value to create the checksum 1333 * Writing new checksum value directly to the boot data 1334 */ 1335 boot_data[cur_header + 7] = -csum; 1336 1337 } else if (pcir_header->code_type == 0x03) { 1338 1339 /* 1340 * Modify Device ID to match current adatper 1341 */ 1342 *(u16*) pcir_header->device_id = device_id; 1343 1344 } 1345 1346 1347 /* 1348 * Check indicator element to identify if this is the last 1349 * image in the ROM. 1350 */ 1351 if (pcir_header->indicator & 0x80) 1352 break; 1353 1354 /* 1355 * Move header pointer up to the next image in the ROM. 1356 */ 1357 cur_header += header->size512 * 512; 1358 } 1359} 1360 1361/* 1362 * t4_load_boot - download boot flash 1363 * @adapter: the adapter 1364 * @boot_data: the boot image to write 1365 * @boot_addr: offset in flash to write boot_data 1366 * @size: image size 1367 * 1368 * Write the supplied boot image to the card's serial flash. 1369 * The boot image has the following sections: a 28-byte header and the 1370 * boot image. 1371 */ 1372int t4_load_boot(struct adapter *adap, u8 *boot_data, 1373 unsigned int boot_addr, unsigned int size) 1374{ 1375 pci_exp_rom_header_t *header; 1376 int pcir_offset ; 1377 pcir_data_t *pcir_header; 1378 int ret, addr; 1379 uint16_t device_id; 1380 unsigned int i; 1381 unsigned int boot_sector = boot_addr * 1024; 1382 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 1383 1384 /* 1385 * Make sure the boot image does not encroach on the firmware region 1386 */ 1387 if ((boot_sector + size) >> 16 > FLASH_FW_START_SEC) { 1388 CH_ERR(adap, "boot image encroaching on firmware region\n"); 1389 return -EFBIG; 1390 } 1391 1392 /* 1393 * Number of sectors spanned 1394 */ 1395 i = DIV_ROUND_UP(size ? size : FLASH_BOOTCFG_MAX_SIZE, 1396 sf_sec_size); 1397 ret = t4_flash_erase_sectors(adap, boot_sector >> 16, 1398 (boot_sector >> 16) + i - 1); 1399 1400 /* 1401 * If size == 0 then we're simply erasing the FLASH sectors associated 1402 * with the on-adapter option ROM file 1403 */ 1404 if (ret || (size == 0)) 1405 goto out; 1406 1407 /* Get boot header */ 1408 header = (pci_exp_rom_header_t *)boot_data; 1409 pcir_offset = le16_to_cpu(*(u16 *)header->pcir_offset); 1410 /* PCIR Data Structure */ 1411 pcir_header = (pcir_data_t *) &boot_data[pcir_offset]; 1412 1413 /* 1414 * Perform some primitive sanity testing to avoid accidentally 1415 * writing garbage over the boot sectors. We ought to check for 1416 * more but it's not worth it for now ... 1417 */ 1418 if (size < BOOT_MIN_SIZE || size > BOOT_MAX_SIZE) { 1419 CH_ERR(adap, "boot image too small/large\n"); 1420 return -EFBIG; 1421 } 1422 1423 /* 1424 * Check BOOT ROM header signature 1425 */ 1426 if (le16_to_cpu(*(u16*)header->signature) != BOOT_SIGNATURE ) { 1427 CH_ERR(adap, "Boot image missing signature\n"); 1428 return -EINVAL; 1429 } 1430 1431 /* 1432 * Check PCI header signature 1433 */ 1434 if (le32_to_cpu(*(u32*)pcir_header->signature) != PCIR_SIGNATURE) { 1435 CH_ERR(adap, "PCI header missing signature\n"); 1436 return -EINVAL; 1437 } 1438 1439 /* 1440 * Check Vendor ID matches Chelsio ID 1441 */ 1442 if (le16_to_cpu(*(u16*)pcir_header->vendor_id) != VENDOR_ID) { 1443 CH_ERR(adap, "Vendor ID missing signature\n"); 1444 return -EINVAL; 1445 } 1446 1447 /* 1448 * Retrieve adapter's device ID 1449 */ 1450 t4_os_pci_read_cfg2(adap, PCI_DEVICE_ID, &device_id); 1451 /* Want to deal with PF 0 so I strip off PF 4 indicator */ 1452 device_id = (device_id & 0xff) | 0x4000; 1453 1454 /* 1455 * Check PCIE Device ID 1456 */ 1457 if (le16_to_cpu(*(u16*)pcir_header->device_id) != device_id) { 1458 /* 1459 * Change the device ID in the Boot BIOS image to match 1460 * the Device ID of the current adapter. 1461 */ 1462 modify_device_id(device_id, boot_data); 1463 } 1464 1465 /* 1466 * Skip over the first SF_PAGE_SIZE worth of data and write it after 1467 * we finish copying the rest of the boot image. This will ensure 1468 * that the BIOS boot header will only be written if the boot image 1469 * was written in full. 1470 */ 1471 addr = boot_sector; 1472 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) { 1473 addr += SF_PAGE_SIZE; 1474 boot_data += SF_PAGE_SIZE; 1475 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, boot_data, 0); 1476 if (ret) 1477 goto out; 1478 } 1479 1480 ret = t4_write_flash(adap, boot_sector, SF_PAGE_SIZE, boot_data, 0); 1481 1482out: 1483 if (ret) 1484 CH_ERR(adap, "boot image download failed, error %d\n", ret); 1485 return ret; 1486} 1487 1488/** 1489 * t4_read_cimq_cfg - read CIM queue configuration 1490 * @adap: the adapter 1491 * @base: holds the queue base addresses in bytes 1492 * @size: holds the queue sizes in bytes 1493 * @thres: holds the queue full thresholds in bytes 1494 * 1495 * Returns the current configuration of the CIM queues, starting with 1496 * the IBQs, then the OBQs. 1497 */ 1498void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres) 1499{ 1500 unsigned int i, v; 1501 int cim_num_obq = is_t4(adap) ? CIM_NUM_OBQ : CIM_NUM_OBQ_T5; 1502 1503 for (i = 0; i < CIM_NUM_IBQ; i++) { 1504 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_IBQSELECT | 1505 V_QUENUMSELECT(i)); 1506 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL); 1507 *base++ = G_CIMQBASE(v) * 256; /* value is in 256-byte units */ 1508 *size++ = G_CIMQSIZE(v) * 256; /* value is in 256-byte units */ 1509 *thres++ = G_QUEFULLTHRSH(v) * 8; /* 8-byte unit */ 1510 } 1511 for (i = 0; i < cim_num_obq; i++) { 1512 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT | 1513 V_QUENUMSELECT(i)); 1514 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL); 1515 *base++ = G_CIMQBASE(v) * 256; /* value is in 256-byte units */ 1516 *size++ = G_CIMQSIZE(v) * 256; /* value is in 256-byte units */ 1517 } 1518} 1519 1520/** 1521 * t4_read_cim_ibq - read the contents of a CIM inbound queue 1522 * @adap: the adapter 1523 * @qid: the queue index 1524 * @data: where to store the queue contents 1525 * @n: capacity of @data in 32-bit words 1526 * 1527 * Reads the contents of the selected CIM queue starting at address 0 up 1528 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on 1529 * error and the number of 32-bit words actually read on success. 1530 */ 1531int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n) 1532{ 1533 int i, err; 1534 unsigned int addr; 1535 const unsigned int nwords = CIM_IBQ_SIZE * 4; 1536 1537 if (qid > 5 || (n & 3)) 1538 return -EINVAL; 1539 1540 addr = qid * nwords; 1541 if (n > nwords) 1542 n = nwords; 1543 1544 for (i = 0; i < n; i++, addr++) { 1545 t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, V_IBQDBGADDR(addr) | 1546 F_IBQDBGEN); 1547 /* 1548 * It might take 3-10ms before the IBQ debug read access is 1549 * allowed. Wait for 1 Sec with a delay of 1 usec. 1550 */ 1551 err = t4_wait_op_done(adap, A_CIM_IBQ_DBG_CFG, F_IBQDBGBUSY, 0, 1552 1000000, 1); 1553 if (err) 1554 return err; 1555 *data++ = t4_read_reg(adap, A_CIM_IBQ_DBG_DATA); 1556 } 1557 t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, 0); 1558 return i; 1559} 1560 1561/** 1562 * t4_read_cim_obq - read the contents of a CIM outbound queue 1563 * @adap: the adapter 1564 * @qid: the queue index 1565 * @data: where to store the queue contents 1566 * @n: capacity of @data in 32-bit words 1567 * 1568 * Reads the contents of the selected CIM queue starting at address 0 up 1569 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on 1570 * error and the number of 32-bit words actually read on success. 1571 */ 1572int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n) 1573{ 1574 int i, err; 1575 unsigned int addr, v, nwords; 1576 int cim_num_obq = is_t4(adap) ? CIM_NUM_OBQ : CIM_NUM_OBQ_T5; 1577 1578 if (qid >= cim_num_obq || (n & 3)) 1579 return -EINVAL; 1580 1581 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT | 1582 V_QUENUMSELECT(qid)); 1583 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL); 1584 1585 addr = G_CIMQBASE(v) * 64; /* muliple of 256 -> muliple of 4 */ 1586 nwords = G_CIMQSIZE(v) * 64; /* same */ 1587 if (n > nwords) 1588 n = nwords; 1589 1590 for (i = 0; i < n; i++, addr++) { 1591 t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, V_OBQDBGADDR(addr) | 1592 F_OBQDBGEN); 1593 err = t4_wait_op_done(adap, A_CIM_OBQ_DBG_CFG, F_OBQDBGBUSY, 0, 1594 2, 1); 1595 if (err) 1596 return err; 1597 *data++ = t4_read_reg(adap, A_CIM_OBQ_DBG_DATA); 1598 } 1599 t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, 0); 1600 return i; 1601} 1602 1603enum { 1604 CIM_QCTL_BASE = 0, 1605 CIM_CTL_BASE = 0x2000, 1606 CIM_PBT_ADDR_BASE = 0x2800, 1607 CIM_PBT_LRF_BASE = 0x3000, 1608 CIM_PBT_DATA_BASE = 0x3800 1609}; 1610 1611/** 1612 * t4_cim_read - read a block from CIM internal address space 1613 * @adap: the adapter 1614 * @addr: the start address within the CIM address space 1615 * @n: number of words to read 1616 * @valp: where to store the result 1617 * 1618 * Reads a block of 4-byte words from the CIM intenal address space. 1619 */ 1620int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 1621 unsigned int *valp) 1622{ 1623 int ret = 0; 1624 1625 if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY) 1626 return -EBUSY; 1627 1628 for ( ; !ret && n--; addr += 4) { 1629 t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr); 1630 ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY, 1631 0, 5, 2); 1632 if (!ret) 1633 *valp++ = t4_read_reg(adap, A_CIM_HOST_ACC_DATA); 1634 } 1635 return ret; 1636} 1637 1638/** 1639 * t4_cim_write - write a block into CIM internal address space 1640 * @adap: the adapter 1641 * @addr: the start address within the CIM address space 1642 * @n: number of words to write 1643 * @valp: set of values to write 1644 * 1645 * Writes a block of 4-byte words into the CIM intenal address space. 1646 */ 1647int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 1648 const unsigned int *valp) 1649{ 1650 int ret = 0; 1651 1652 if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY) 1653 return -EBUSY; 1654 1655 for ( ; !ret && n--; addr += 4) { 1656 t4_write_reg(adap, A_CIM_HOST_ACC_DATA, *valp++); 1657 t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr | F_HOSTWRITE); 1658 ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY, 1659 0, 5, 2); 1660 } 1661 return ret; 1662} 1663 1664static int t4_cim_write1(struct adapter *adap, unsigned int addr, unsigned int val) 1665{ 1666 return t4_cim_write(adap, addr, 1, &val); 1667} 1668 1669/** 1670 * t4_cim_ctl_read - read a block from CIM control region 1671 * @adap: the adapter 1672 * @addr: the start address within the CIM control region 1673 * @n: number of words to read 1674 * @valp: where to store the result 1675 * 1676 * Reads a block of 4-byte words from the CIM control region. 1677 */ 1678int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n, 1679 unsigned int *valp) 1680{ 1681 return t4_cim_read(adap, addr + CIM_CTL_BASE, n, valp); 1682} 1683 1684/** 1685 * t4_cim_read_la - read CIM LA capture buffer 1686 * @adap: the adapter 1687 * @la_buf: where to store the LA data 1688 * @wrptr: the HW write pointer within the capture buffer 1689 * 1690 * Reads the contents of the CIM LA buffer with the most recent entry at 1691 * the end of the returned data and with the entry at @wrptr first. 1692 * We try to leave the LA in the running state we find it in. 1693 */ 1694int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr) 1695{ 1696 int i, ret; 1697 unsigned int cfg, val, idx; 1698 1699 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &cfg); 1700 if (ret) 1701 return ret; 1702 1703 if (cfg & F_UPDBGLAEN) { /* LA is running, freeze it */ 1704 ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 0); 1705 if (ret) 1706 return ret; 1707 } 1708 1709 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val); 1710 if (ret) 1711 goto restart; 1712 1713 idx = G_UPDBGLAWRPTR(val); 1714 if (wrptr) 1715 *wrptr = idx; 1716 1717 for (i = 0; i < adap->params.cim_la_size; i++) { 1718 ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 1719 V_UPDBGLARDPTR(idx) | F_UPDBGLARDEN); 1720 if (ret) 1721 break; 1722 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val); 1723 if (ret) 1724 break; 1725 if (val & F_UPDBGLARDEN) { 1726 ret = -ETIMEDOUT; 1727 break; 1728 } 1729 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_DATA, 1, &la_buf[i]); 1730 if (ret) 1731 break; 1732 idx = (idx + 1) & M_UPDBGLARDPTR; 1733 } 1734restart: 1735 if (cfg & F_UPDBGLAEN) { 1736 int r = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 1737 cfg & ~F_UPDBGLARDEN); 1738 if (!ret) 1739 ret = r; 1740 } 1741 return ret; 1742} 1743 1744void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 1745 unsigned int *pif_req_wrptr, 1746 unsigned int *pif_rsp_wrptr) 1747{ 1748 int i, j; 1749 u32 cfg, val, req, rsp; 1750 1751 cfg = t4_read_reg(adap, A_CIM_DEBUGCFG); 1752 if (cfg & F_LADBGEN) 1753 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN); 1754 1755 val = t4_read_reg(adap, A_CIM_DEBUGSTS); 1756 req = G_POLADBGWRPTR(val); 1757 rsp = G_PILADBGWRPTR(val); 1758 if (pif_req_wrptr) 1759 *pif_req_wrptr = req; 1760 if (pif_rsp_wrptr) 1761 *pif_rsp_wrptr = rsp; 1762 1763 for (i = 0; i < CIM_PIFLA_SIZE; i++) { 1764 for (j = 0; j < 6; j++) { 1765 t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(req) | 1766 V_PILADBGRDPTR(rsp)); 1767 *pif_req++ = t4_read_reg(adap, A_CIM_PO_LA_DEBUGDATA); 1768 *pif_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_DEBUGDATA); 1769 req++; 1770 rsp++; 1771 } 1772 req = (req + 2) & M_POLADBGRDPTR; 1773 rsp = (rsp + 2) & M_PILADBGRDPTR; 1774 } 1775 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg); 1776} 1777 1778void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp) 1779{ 1780 u32 cfg; 1781 int i, j, idx; 1782 1783 cfg = t4_read_reg(adap, A_CIM_DEBUGCFG); 1784 if (cfg & F_LADBGEN) 1785 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN); 1786 1787 for (i = 0; i < CIM_MALA_SIZE; i++) { 1788 for (j = 0; j < 5; j++) { 1789 idx = 8 * i + j; 1790 t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(idx) | 1791 V_PILADBGRDPTR(idx)); 1792 *ma_req++ = t4_read_reg(adap, A_CIM_PO_LA_MADEBUGDATA); 1793 *ma_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_MADEBUGDATA); 1794 } 1795 } 1796 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg); 1797} 1798 1799/** 1800 * t4_tp_read_la - read TP LA capture buffer 1801 * @adap: the adapter 1802 * @la_buf: where to store the LA data 1803 * @wrptr: the HW write pointer within the capture buffer 1804 * 1805 * Reads the contents of the TP LA buffer with the most recent entry at 1806 * the end of the returned data and with the entry at @wrptr first. 1807 * We leave the LA in the running state we find it in. 1808 */ 1809void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr) 1810{ 1811 bool last_incomplete; 1812 unsigned int i, cfg, val, idx; 1813 1814 cfg = t4_read_reg(adap, A_TP_DBG_LA_CONFIG) & 0xffff; 1815 if (cfg & F_DBGLAENABLE) /* freeze LA */ 1816 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, 1817 adap->params.tp.la_mask | (cfg ^ F_DBGLAENABLE)); 1818 1819 val = t4_read_reg(adap, A_TP_DBG_LA_CONFIG); 1820 idx = G_DBGLAWPTR(val); 1821 last_incomplete = G_DBGLAMODE(val) >= 2 && (val & F_DBGLAWHLF) == 0; 1822 if (last_incomplete) 1823 idx = (idx + 1) & M_DBGLARPTR; 1824 if (wrptr) 1825 *wrptr = idx; 1826 1827 val &= 0xffff; 1828 val &= ~V_DBGLARPTR(M_DBGLARPTR); 1829 val |= adap->params.tp.la_mask; 1830 1831 for (i = 0; i < TPLA_SIZE; i++) { 1832 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, V_DBGLARPTR(idx) | val); 1833 la_buf[i] = t4_read_reg64(adap, A_TP_DBG_LA_DATAL); 1834 idx = (idx + 1) & M_DBGLARPTR; 1835 } 1836 1837 /* Wipe out last entry if it isn't valid */ 1838 if (last_incomplete) 1839 la_buf[TPLA_SIZE - 1] = ~0ULL; 1840 1841 if (cfg & F_DBGLAENABLE) /* restore running state */ 1842 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, 1843 cfg | adap->params.tp.la_mask); 1844} 1845 1846void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf) 1847{ 1848 unsigned int i, j; 1849 1850 for (i = 0; i < 8; i++) { 1851 u32 *p = la_buf + i; 1852 1853 t4_write_reg(adap, A_ULP_RX_LA_CTL, i); 1854 j = t4_read_reg(adap, A_ULP_RX_LA_WRPTR); 1855 t4_write_reg(adap, A_ULP_RX_LA_RDPTR, j); 1856 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8) 1857 *p = t4_read_reg(adap, A_ULP_RX_LA_RDDATA); 1858 } 1859} 1860 1861#define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\ 1862 FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_SPEED_40G | \ 1863 FW_PORT_CAP_SPEED_100G | FW_PORT_CAP_ANEG) 1864 1865/** 1866 * t4_link_start - apply link configuration to MAC/PHY 1867 * @phy: the PHY to setup 1868 * @mac: the MAC to setup 1869 * @lc: the requested link configuration 1870 * 1871 * Set up a port's MAC and PHY according to a desired link configuration. 1872 * - If the PHY can auto-negotiate first decide what to advertise, then 1873 * enable/disable auto-negotiation as desired, and reset. 1874 * - If the PHY does not auto-negotiate just reset it. 1875 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC, 1876 * otherwise do it later based on the outcome of auto-negotiation. 1877 */ 1878int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port, 1879 struct link_config *lc) 1880{ 1881 struct fw_port_cmd c; 1882 unsigned int fc = 0, mdi = V_FW_PORT_CAP_MDI(FW_PORT_CAP_MDI_AUTO); 1883 1884 lc->link_ok = 0; 1885 if (lc->requested_fc & PAUSE_RX) 1886 fc |= FW_PORT_CAP_FC_RX; 1887 if (lc->requested_fc & PAUSE_TX) 1888 fc |= FW_PORT_CAP_FC_TX; 1889 1890 memset(&c, 0, sizeof(c)); 1891 c.op_to_portid = htonl(V_FW_CMD_OP(FW_PORT_CMD) | F_FW_CMD_REQUEST | 1892 F_FW_CMD_EXEC | V_FW_PORT_CMD_PORTID(port)); 1893 c.action_to_len16 = htonl(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) | 1894 FW_LEN16(c)); 1895 1896 if (!(lc->supported & FW_PORT_CAP_ANEG)) { 1897 c.u.l1cfg.rcap = htonl((lc->supported & ADVERT_MASK) | fc); 1898 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX); 1899 } else if (lc->autoneg == AUTONEG_DISABLE) { 1900 c.u.l1cfg.rcap = htonl(lc->requested_speed | fc | mdi); 1901 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX); 1902 } else 1903 c.u.l1cfg.rcap = htonl(lc->advertising | fc | mdi); 1904 1905 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 1906} 1907 1908/** 1909 * t4_restart_aneg - restart autonegotiation 1910 * @adap: the adapter 1911 * @mbox: mbox to use for the FW command 1912 * @port: the port id 1913 * 1914 * Restarts autonegotiation for the selected port. 1915 */ 1916int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port) 1917{ 1918 struct fw_port_cmd c; 1919 1920 memset(&c, 0, sizeof(c)); 1921 c.op_to_portid = htonl(V_FW_CMD_OP(FW_PORT_CMD) | F_FW_CMD_REQUEST | 1922 F_FW_CMD_EXEC | V_FW_PORT_CMD_PORTID(port)); 1923 c.action_to_len16 = htonl(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) | 1924 FW_LEN16(c)); 1925 c.u.l1cfg.rcap = htonl(FW_PORT_CAP_ANEG); 1926 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 1927} 1928 1929struct intr_info { 1930 unsigned int mask; /* bits to check in interrupt status */ 1931 const char *msg; /* message to print or NULL */ 1932 short stat_idx; /* stat counter to increment or -1 */ 1933 unsigned short fatal; /* whether the condition reported is fatal */ 1934}; 1935 1936/** 1937 * t4_handle_intr_status - table driven interrupt handler 1938 * @adapter: the adapter that generated the interrupt 1939 * @reg: the interrupt status register to process 1940 * @acts: table of interrupt actions 1941 * 1942 * A table driven interrupt handler that applies a set of masks to an 1943 * interrupt status word and performs the corresponding actions if the 1944 * interrupts described by the mask have occured. The actions include 1945 * optionally emitting a warning or alert message. The table is terminated 1946 * by an entry specifying mask 0. Returns the number of fatal interrupt 1947 * conditions. 1948 */ 1949static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg, 1950 const struct intr_info *acts) 1951{ 1952 int fatal = 0; 1953 unsigned int mask = 0; 1954 unsigned int status = t4_read_reg(adapter, reg); 1955 1956 for ( ; acts->mask; ++acts) { 1957 if (!(status & acts->mask)) 1958 continue; 1959 if (acts->fatal) { 1960 fatal++; 1961 CH_ALERT(adapter, "%s (0x%x)\n", 1962 acts->msg, status & acts->mask); 1963 } else if (acts->msg) 1964 CH_WARN_RATELIMIT(adapter, "%s (0x%x)\n", 1965 acts->msg, status & acts->mask); 1966 mask |= acts->mask; 1967 } 1968 status &= mask; 1969 if (status) /* clear processed interrupts */ 1970 t4_write_reg(adapter, reg, status); 1971 return fatal; 1972} 1973 1974/* 1975 * Interrupt handler for the PCIE module. 1976 */ 1977static void pcie_intr_handler(struct adapter *adapter) 1978{ 1979 static struct intr_info sysbus_intr_info[] = { 1980 { F_RNPP, "RXNP array parity error", -1, 1 }, 1981 { F_RPCP, "RXPC array parity error", -1, 1 }, 1982 { F_RCIP, "RXCIF array parity error", -1, 1 }, 1983 { F_RCCP, "Rx completions control array parity error", -1, 1 }, 1984 { F_RFTP, "RXFT array parity error", -1, 1 }, 1985 { 0 } 1986 }; 1987 static struct intr_info pcie_port_intr_info[] = { 1988 { F_TPCP, "TXPC array parity error", -1, 1 }, 1989 { F_TNPP, "TXNP array parity error", -1, 1 }, 1990 { F_TFTP, "TXFT array parity error", -1, 1 }, 1991 { F_TCAP, "TXCA array parity error", -1, 1 }, 1992 { F_TCIP, "TXCIF array parity error", -1, 1 }, 1993 { F_RCAP, "RXCA array parity error", -1, 1 }, 1994 { F_OTDD, "outbound request TLP discarded", -1, 1 }, 1995 { F_RDPE, "Rx data parity error", -1, 1 }, 1996 { F_TDUE, "Tx uncorrectable data error", -1, 1 }, 1997 { 0 } 1998 }; 1999 static struct intr_info pcie_intr_info[] = { 2000 { F_MSIADDRLPERR, "MSI AddrL parity error", -1, 1 }, 2001 { F_MSIADDRHPERR, "MSI AddrH parity error", -1, 1 }, 2002 { F_MSIDATAPERR, "MSI data parity error", -1, 1 }, 2003 { F_MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 }, 2004 { F_MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 }, 2005 { F_MSIXDATAPERR, "MSI-X data parity error", -1, 1 }, 2006 { F_MSIXDIPERR, "MSI-X DI parity error", -1, 1 }, 2007 { F_PIOCPLPERR, "PCI PIO completion FIFO parity error", -1, 1 }, 2008 { F_PIOREQPERR, "PCI PIO request FIFO parity error", -1, 1 }, 2009 { F_TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 }, 2010 { F_CCNTPERR, "PCI CMD channel count parity error", -1, 1 }, 2011 { F_CREQPERR, "PCI CMD channel request parity error", -1, 1 }, 2012 { F_CRSPPERR, "PCI CMD channel response parity error", -1, 1 }, 2013 { F_DCNTPERR, "PCI DMA channel count parity error", -1, 1 }, 2014 { F_DREQPERR, "PCI DMA channel request parity error", -1, 1 }, 2015 { F_DRSPPERR, "PCI DMA channel response parity error", -1, 1 }, 2016 { F_HCNTPERR, "PCI HMA channel count parity error", -1, 1 }, 2017 { F_HREQPERR, "PCI HMA channel request parity error", -1, 1 }, 2018 { F_HRSPPERR, "PCI HMA channel response parity error", -1, 1 }, 2019 { F_CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 }, 2020 { F_FIDPERR, "PCI FID parity error", -1, 1 }, 2021 { F_INTXCLRPERR, "PCI INTx clear parity error", -1, 1 }, 2022 { F_MATAGPERR, "PCI MA tag parity error", -1, 1 }, 2023 { F_PIOTAGPERR, "PCI PIO tag parity error", -1, 1 }, 2024 { F_RXCPLPERR, "PCI Rx completion parity error", -1, 1 }, 2025 { F_RXWRPERR, "PCI Rx write parity error", -1, 1 }, 2026 { F_RPLPERR, "PCI replay buffer parity error", -1, 1 }, 2027 { F_PCIESINT, "PCI core secondary fault", -1, 1 }, 2028 { F_PCIEPINT, "PCI core primary fault", -1, 1 }, 2029 { F_UNXSPLCPLERR, "PCI unexpected split completion error", -1, 2030 0 }, 2031 { 0 } 2032 }; 2033 2034 static struct intr_info t5_pcie_intr_info[] = { 2035 { F_MSTGRPPERR, "Master Response Read Queue parity error", 2036 -1, 1 }, 2037 { F_MSTTIMEOUTPERR, "Master Timeout FIFO parity error", -1, 1 }, 2038 { F_MSIXSTIPERR, "MSI-X STI SRAM parity error", -1, 1 }, 2039 { F_MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 }, 2040 { F_MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 }, 2041 { F_MSIXDATAPERR, "MSI-X data parity error", -1, 1 }, 2042 { F_MSIXDIPERR, "MSI-X DI parity error", -1, 1 }, 2043 { F_PIOCPLGRPPERR, "PCI PIO completion Group FIFO parity error", 2044 -1, 1 }, 2045 { F_PIOREQGRPPERR, "PCI PIO request Group FIFO parity error", 2046 -1, 1 }, 2047 { F_TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 }, 2048 { F_MSTTAGQPERR, "PCI master tag queue parity error", -1, 1 }, 2049 { F_CREQPERR, "PCI CMD channel request parity error", -1, 1 }, 2050 { F_CRSPPERR, "PCI CMD channel response parity error", -1, 1 }, 2051 { F_DREQWRPERR, "PCI DMA channel write request parity error", 2052 -1, 1 }, 2053 { F_DREQPERR, "PCI DMA channel request parity error", -1, 1 }, 2054 { F_DRSPPERR, "PCI DMA channel response parity error", -1, 1 }, 2055 { F_HREQWRPERR, "PCI HMA channel count parity error", -1, 1 }, 2056 { F_HREQPERR, "PCI HMA channel request parity error", -1, 1 }, 2057 { F_HRSPPERR, "PCI HMA channel response parity error", -1, 1 }, 2058 { F_CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 }, 2059 { F_FIDPERR, "PCI FID parity error", -1, 1 }, 2060 { F_VFIDPERR, "PCI INTx clear parity error", -1, 1 }, 2061 { F_MAGRPPERR, "PCI MA group FIFO parity error", -1, 1 }, 2062 { F_PIOTAGPERR, "PCI PIO tag parity error", -1, 1 }, 2063 { F_IPRXHDRGRPPERR, "PCI IP Rx header group parity error", 2064 -1, 1 }, 2065 { F_IPRXDATAGRPPERR, "PCI IP Rx data group parity error", 2066 -1, 1 }, 2067 { F_RPLPERR, "PCI IP replay buffer parity error", -1, 1 }, 2068 { F_IPSOTPERR, "PCI IP SOT buffer parity error", -1, 1 }, 2069 { F_TRGT1GRPPERR, "PCI TRGT1 group FIFOs parity error", -1, 1 }, 2070 { F_READRSPERR, "Outbound read error", -1, 2071 0 }, 2072 { 0 } 2073 }; 2074 2075 int fat; 2076 2077 if (is_t4(adapter)) 2078 fat = t4_handle_intr_status(adapter, 2079 A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS, 2080 sysbus_intr_info) + 2081 t4_handle_intr_status(adapter, 2082 A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, 2083 pcie_port_intr_info) + 2084 t4_handle_intr_status(adapter, A_PCIE_INT_CAUSE, 2085 pcie_intr_info); 2086 else 2087 fat = t4_handle_intr_status(adapter, A_PCIE_INT_CAUSE, 2088 t5_pcie_intr_info); 2089 if (fat) 2090 t4_fatal_err(adapter); 2091} 2092 2093/* 2094 * TP interrupt handler. 2095 */ 2096static void tp_intr_handler(struct adapter *adapter) 2097{ 2098 static struct intr_info tp_intr_info[] = { 2099 { 0x3fffffff, "TP parity error", -1, 1 }, 2100 { F_FLMTXFLSTEMPTY, "TP out of Tx pages", -1, 1 }, 2101 { 0 } 2102 }; 2103 2104 if (t4_handle_intr_status(adapter, A_TP_INT_CAUSE, tp_intr_info)) 2105 t4_fatal_err(adapter); 2106} 2107 2108/* 2109 * SGE interrupt handler. 2110 */ 2111static void sge_intr_handler(struct adapter *adapter) 2112{ 2113 u64 v; 2114 u32 err; 2115 2116 static struct intr_info sge_intr_info[] = { 2117 { F_ERR_CPL_EXCEED_IQE_SIZE, 2118 "SGE received CPL exceeding IQE size", -1, 1 }, 2119 { F_ERR_INVALID_CIDX_INC, 2120 "SGE GTS CIDX increment too large", -1, 0 }, 2121 { F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL", -1, 0 }, 2122 { F_ERR_DROPPED_DB, "SGE doorbell dropped", -1, 0 }, 2123 { F_ERR_DATA_CPL_ON_HIGH_QID1 | F_ERR_DATA_CPL_ON_HIGH_QID0, 2124 "SGE IQID > 1023 received CPL for FL", -1, 0 }, 2125 { F_ERR_BAD_DB_PIDX3, "SGE DBP 3 pidx increment too large", -1, 2126 0 }, 2127 { F_ERR_BAD_DB_PIDX2, "SGE DBP 2 pidx increment too large", -1, 2128 0 }, 2129 { F_ERR_BAD_DB_PIDX1, "SGE DBP 1 pidx increment too large", -1, 2130 0 }, 2131 { F_ERR_BAD_DB_PIDX0, "SGE DBP 0 pidx increment too large", -1, 2132 0 }, 2133 { F_ERR_ING_CTXT_PRIO, 2134 "SGE too many priority ingress contexts", -1, 0 }, 2135 { F_ERR_EGR_CTXT_PRIO, 2136 "SGE too many priority egress contexts", -1, 0 }, 2137 { F_INGRESS_SIZE_ERR, "SGE illegal ingress QID", -1, 0 }, 2138 { F_EGRESS_SIZE_ERR, "SGE illegal egress QID", -1, 0 }, 2139 { 0 } 2140 }; 2141 2142 v = (u64)t4_read_reg(adapter, A_SGE_INT_CAUSE1) | 2143 ((u64)t4_read_reg(adapter, A_SGE_INT_CAUSE2) << 32); 2144 if (v) { 2145 CH_ALERT(adapter, "SGE parity error (%#llx)\n", 2146 (unsigned long long)v); 2147 t4_write_reg(adapter, A_SGE_INT_CAUSE1, v); 2148 t4_write_reg(adapter, A_SGE_INT_CAUSE2, v >> 32); 2149 } 2150 2151 v |= t4_handle_intr_status(adapter, A_SGE_INT_CAUSE3, sge_intr_info); 2152 2153 err = t4_read_reg(adapter, A_SGE_ERROR_STATS); 2154 if (err & F_ERROR_QID_VALID) { 2155 CH_ERR(adapter, "SGE error for queue %u\n", G_ERROR_QID(err)); 2156 if (err & F_UNCAPTURED_ERROR) 2157 CH_ERR(adapter, "SGE UNCAPTURED_ERROR set (clearing)\n"); 2158 t4_write_reg(adapter, A_SGE_ERROR_STATS, F_ERROR_QID_VALID | 2159 F_UNCAPTURED_ERROR); 2160 } 2161 2162 if (v != 0) 2163 t4_fatal_err(adapter); 2164} 2165 2166#define CIM_OBQ_INTR (F_OBQULP0PARERR | F_OBQULP1PARERR | F_OBQULP2PARERR |\ 2167 F_OBQULP3PARERR | F_OBQSGEPARERR | F_OBQNCSIPARERR) 2168#define CIM_IBQ_INTR (F_IBQTP0PARERR | F_IBQTP1PARERR | F_IBQULPPARERR |\ 2169 F_IBQSGEHIPARERR | F_IBQSGELOPARERR | F_IBQNCSIPARERR) 2170 2171/* 2172 * CIM interrupt handler. 2173 */ 2174static void cim_intr_handler(struct adapter *adapter) 2175{ 2176 static struct intr_info cim_intr_info[] = { 2177 { F_PREFDROPINT, "CIM control register prefetch drop", -1, 1 }, 2178 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 }, 2179 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 }, 2180 { F_MBUPPARERR, "CIM mailbox uP parity error", -1, 1 }, 2181 { F_MBHOSTPARERR, "CIM mailbox host parity error", -1, 1 }, 2182 { F_TIEQINPARERRINT, "CIM TIEQ outgoing parity error", -1, 1 }, 2183 { F_TIEQOUTPARERRINT, "CIM TIEQ incoming parity error", -1, 1 }, 2184 { 0 } 2185 }; 2186 static struct intr_info cim_upintr_info[] = { 2187 { F_RSVDSPACEINT, "CIM reserved space access", -1, 1 }, 2188 { F_ILLTRANSINT, "CIM illegal transaction", -1, 1 }, 2189 { F_ILLWRINT, "CIM illegal write", -1, 1 }, 2190 { F_ILLRDINT, "CIM illegal read", -1, 1 }, 2191 { F_ILLRDBEINT, "CIM illegal read BE", -1, 1 }, 2192 { F_ILLWRBEINT, "CIM illegal write BE", -1, 1 }, 2193 { F_SGLRDBOOTINT, "CIM single read from boot space", -1, 1 }, 2194 { F_SGLWRBOOTINT, "CIM single write to boot space", -1, 1 }, 2195 { F_BLKWRBOOTINT, "CIM block write to boot space", -1, 1 }, 2196 { F_SGLRDFLASHINT, "CIM single read from flash space", -1, 1 }, 2197 { F_SGLWRFLASHINT, "CIM single write to flash space", -1, 1 }, 2198 { F_BLKWRFLASHINT, "CIM block write to flash space", -1, 1 }, 2199 { F_SGLRDEEPROMINT, "CIM single EEPROM read", -1, 1 }, 2200 { F_SGLWREEPROMINT, "CIM single EEPROM write", -1, 1 }, 2201 { F_BLKRDEEPROMINT, "CIM block EEPROM read", -1, 1 }, 2202 { F_BLKWREEPROMINT, "CIM block EEPROM write", -1, 1 }, 2203 { F_SGLRDCTLINT , "CIM single read from CTL space", -1, 1 }, 2204 { F_SGLWRCTLINT , "CIM single write to CTL space", -1, 1 }, 2205 { F_BLKRDCTLINT , "CIM block read from CTL space", -1, 1 }, 2206 { F_BLKWRCTLINT , "CIM block write to CTL space", -1, 1 }, 2207 { F_SGLRDPLINT , "CIM single read from PL space", -1, 1 }, 2208 { F_SGLWRPLINT , "CIM single write to PL space", -1, 1 }, 2209 { F_BLKRDPLINT , "CIM block read from PL space", -1, 1 }, 2210 { F_BLKWRPLINT , "CIM block write to PL space", -1, 1 }, 2211 { F_REQOVRLOOKUPINT , "CIM request FIFO overwrite", -1, 1 }, 2212 { F_RSPOVRLOOKUPINT , "CIM response FIFO overwrite", -1, 1 }, 2213 { F_TIMEOUTINT , "CIM PIF timeout", -1, 1 }, 2214 { F_TIMEOUTMAINT , "CIM PIF MA timeout", -1, 1 }, 2215 { 0 } 2216 }; 2217 int fat; 2218 2219 if (t4_read_reg(adapter, A_PCIE_FW) & F_PCIE_FW_ERR) 2220 t4_report_fw_error(adapter); 2221 2222 fat = t4_handle_intr_status(adapter, A_CIM_HOST_INT_CAUSE, 2223 cim_intr_info) + 2224 t4_handle_intr_status(adapter, A_CIM_HOST_UPACC_INT_CAUSE, 2225 cim_upintr_info); 2226 if (fat) 2227 t4_fatal_err(adapter); 2228} 2229 2230/* 2231 * ULP RX interrupt handler. 2232 */ 2233static void ulprx_intr_handler(struct adapter *adapter) 2234{ 2235 static struct intr_info ulprx_intr_info[] = { 2236 { F_CAUSE_CTX_1, "ULPRX channel 1 context error", -1, 1 }, 2237 { F_CAUSE_CTX_0, "ULPRX channel 0 context error", -1, 1 }, 2238 { 0x7fffff, "ULPRX parity error", -1, 1 }, 2239 { 0 } 2240 }; 2241 2242 if (t4_handle_intr_status(adapter, A_ULP_RX_INT_CAUSE, ulprx_intr_info)) 2243 t4_fatal_err(adapter); 2244} 2245 2246/* 2247 * ULP TX interrupt handler. 2248 */ 2249static void ulptx_intr_handler(struct adapter *adapter) 2250{ 2251 static struct intr_info ulptx_intr_info[] = { 2252 { F_PBL_BOUND_ERR_CH3, "ULPTX channel 3 PBL out of bounds", -1, 2253 0 }, 2254 { F_PBL_BOUND_ERR_CH2, "ULPTX channel 2 PBL out of bounds", -1, 2255 0 }, 2256 { F_PBL_BOUND_ERR_CH1, "ULPTX channel 1 PBL out of bounds", -1, 2257 0 }, 2258 { F_PBL_BOUND_ERR_CH0, "ULPTX channel 0 PBL out of bounds", -1, 2259 0 }, 2260 { 0xfffffff, "ULPTX parity error", -1, 1 }, 2261 { 0 } 2262 }; 2263 2264 if (t4_handle_intr_status(adapter, A_ULP_TX_INT_CAUSE, ulptx_intr_info)) 2265 t4_fatal_err(adapter); 2266} 2267 2268/* 2269 * PM TX interrupt handler. 2270 */ 2271static void pmtx_intr_handler(struct adapter *adapter) 2272{ 2273 static struct intr_info pmtx_intr_info[] = { 2274 { F_PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large", -1, 1 }, 2275 { F_PCMD_LEN_OVFL1, "PMTX channel 1 pcmd too large", -1, 1 }, 2276 { F_PCMD_LEN_OVFL2, "PMTX channel 2 pcmd too large", -1, 1 }, 2277 { F_ZERO_C_CMD_ERROR, "PMTX 0-length pcmd", -1, 1 }, 2278 { 0xffffff0, "PMTX framing error", -1, 1 }, 2279 { F_OESPI_PAR_ERROR, "PMTX oespi parity error", -1, 1 }, 2280 { F_DB_OPTIONS_PAR_ERROR, "PMTX db_options parity error", -1, 2281 1 }, 2282 { F_ICSPI_PAR_ERROR, "PMTX icspi parity error", -1, 1 }, 2283 { F_C_PCMD_PAR_ERROR, "PMTX c_pcmd parity error", -1, 1}, 2284 { 0 } 2285 }; 2286 2287 if (t4_handle_intr_status(adapter, A_PM_TX_INT_CAUSE, pmtx_intr_info)) 2288 t4_fatal_err(adapter); 2289} 2290 2291/* 2292 * PM RX interrupt handler. 2293 */ 2294static void pmrx_intr_handler(struct adapter *adapter) 2295{ 2296 static struct intr_info pmrx_intr_info[] = { 2297 { F_ZERO_E_CMD_ERROR, "PMRX 0-length pcmd", -1, 1 }, 2298 { 0x3ffff0, "PMRX framing error", -1, 1 }, 2299 { F_OCSPI_PAR_ERROR, "PMRX ocspi parity error", -1, 1 }, 2300 { F_DB_OPTIONS_PAR_ERROR, "PMRX db_options parity error", -1, 2301 1 }, 2302 { F_IESPI_PAR_ERROR, "PMRX iespi parity error", -1, 1 }, 2303 { F_E_PCMD_PAR_ERROR, "PMRX e_pcmd parity error", -1, 1}, 2304 { 0 } 2305 }; 2306 2307 if (t4_handle_intr_status(adapter, A_PM_RX_INT_CAUSE, pmrx_intr_info)) 2308 t4_fatal_err(adapter); 2309} 2310 2311/* 2312 * CPL switch interrupt handler. 2313 */ 2314static void cplsw_intr_handler(struct adapter *adapter) 2315{ 2316 static struct intr_info cplsw_intr_info[] = { 2317 { F_CIM_OP_MAP_PERR, "CPLSW CIM op_map parity error", -1, 1 }, 2318 { F_CIM_OVFL_ERROR, "CPLSW CIM overflow", -1, 1 }, 2319 { F_TP_FRAMING_ERROR, "CPLSW TP framing error", -1, 1 }, 2320 { F_SGE_FRAMING_ERROR, "CPLSW SGE framing error", -1, 1 }, 2321 { F_CIM_FRAMING_ERROR, "CPLSW CIM framing error", -1, 1 }, 2322 { F_ZERO_SWITCH_ERROR, "CPLSW no-switch error", -1, 1 }, 2323 { 0 } 2324 }; 2325 2326 if (t4_handle_intr_status(adapter, A_CPL_INTR_CAUSE, cplsw_intr_info)) 2327 t4_fatal_err(adapter); 2328} 2329 2330/* 2331 * LE interrupt handler. 2332 */ 2333static void le_intr_handler(struct adapter *adap) 2334{ 2335 static struct intr_info le_intr_info[] = { 2336 { F_LIPMISS, "LE LIP miss", -1, 0 }, 2337 { F_LIP0, "LE 0 LIP error", -1, 0 }, 2338 { F_PARITYERR, "LE parity error", -1, 1 }, 2339 { F_UNKNOWNCMD, "LE unknown command", -1, 1 }, 2340 { F_REQQPARERR, "LE request queue parity error", -1, 1 }, 2341 { 0 } 2342 }; 2343 2344 if (t4_handle_intr_status(adap, A_LE_DB_INT_CAUSE, le_intr_info)) 2345 t4_fatal_err(adap); 2346} 2347 2348/* 2349 * MPS interrupt handler. 2350 */ 2351static void mps_intr_handler(struct adapter *adapter) 2352{ 2353 static struct intr_info mps_rx_intr_info[] = { 2354 { 0xffffff, "MPS Rx parity error", -1, 1 }, 2355 { 0 } 2356 }; 2357 static struct intr_info mps_tx_intr_info[] = { 2358 { V_TPFIFO(M_TPFIFO), "MPS Tx TP FIFO parity error", -1, 1 }, 2359 { F_NCSIFIFO, "MPS Tx NC-SI FIFO parity error", -1, 1 }, 2360 { V_TXDATAFIFO(M_TXDATAFIFO), "MPS Tx data FIFO parity error", 2361 -1, 1 }, 2362 { V_TXDESCFIFO(M_TXDESCFIFO), "MPS Tx desc FIFO parity error", 2363 -1, 1 }, 2364 { F_BUBBLE, "MPS Tx underflow", -1, 1 }, 2365 { F_SECNTERR, "MPS Tx SOP/EOP error", -1, 1 }, 2366 { F_FRMERR, "MPS Tx framing error", -1, 1 }, 2367 { 0 } 2368 }; 2369 static struct intr_info mps_trc_intr_info[] = { 2370 { V_FILTMEM(M_FILTMEM), "MPS TRC filter parity error", -1, 1 }, 2371 { V_PKTFIFO(M_PKTFIFO), "MPS TRC packet FIFO parity error", -1, 2372 1 }, 2373 { F_MISCPERR, "MPS TRC misc parity error", -1, 1 }, 2374 { 0 } 2375 }; 2376 static struct intr_info mps_stat_sram_intr_info[] = { 2377 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 }, 2378 { 0 } 2379 }; 2380 static struct intr_info mps_stat_tx_intr_info[] = { 2381 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 }, 2382 { 0 } 2383 }; 2384 static struct intr_info mps_stat_rx_intr_info[] = { 2385 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 }, 2386 { 0 } 2387 }; 2388 static struct intr_info mps_cls_intr_info[] = { 2389 { F_MATCHSRAM, "MPS match SRAM parity error", -1, 1 }, 2390 { F_MATCHTCAM, "MPS match TCAM parity error", -1, 1 }, 2391 { F_HASHSRAM, "MPS hash SRAM parity error", -1, 1 }, 2392 { 0 } 2393 }; 2394 2395 int fat; 2396 2397 fat = t4_handle_intr_status(adapter, A_MPS_RX_PERR_INT_CAUSE, 2398 mps_rx_intr_info) + 2399 t4_handle_intr_status(adapter, A_MPS_TX_INT_CAUSE, 2400 mps_tx_intr_info) + 2401 t4_handle_intr_status(adapter, A_MPS_TRC_INT_CAUSE, 2402 mps_trc_intr_info) + 2403 t4_handle_intr_status(adapter, A_MPS_STAT_PERR_INT_CAUSE_SRAM, 2404 mps_stat_sram_intr_info) + 2405 t4_handle_intr_status(adapter, A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO, 2406 mps_stat_tx_intr_info) + 2407 t4_handle_intr_status(adapter, A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO, 2408 mps_stat_rx_intr_info) + 2409 t4_handle_intr_status(adapter, A_MPS_CLS_INT_CAUSE, 2410 mps_cls_intr_info); 2411 2412 t4_write_reg(adapter, A_MPS_INT_CAUSE, 0); 2413 t4_read_reg(adapter, A_MPS_INT_CAUSE); /* flush */ 2414 if (fat) 2415 t4_fatal_err(adapter); 2416} 2417 2418#define MEM_INT_MASK (F_PERR_INT_CAUSE | F_ECC_CE_INT_CAUSE | F_ECC_UE_INT_CAUSE) 2419 2420/* 2421 * EDC/MC interrupt handler. 2422 */ 2423static void mem_intr_handler(struct adapter *adapter, int idx) 2424{ 2425 static const char name[3][5] = { "EDC0", "EDC1", "MC" }; 2426 2427 unsigned int addr, cnt_addr, v; 2428 2429 if (idx <= MEM_EDC1) { 2430 addr = EDC_REG(A_EDC_INT_CAUSE, idx); 2431 cnt_addr = EDC_REG(A_EDC_ECC_STATUS, idx); 2432 } else { 2433 if (is_t4(adapter)) { 2434 addr = A_MC_INT_CAUSE; 2435 cnt_addr = A_MC_ECC_STATUS; 2436 } else { 2437 addr = A_MC_P_INT_CAUSE; 2438 cnt_addr = A_MC_P_ECC_STATUS; 2439 } 2440 } 2441 2442 v = t4_read_reg(adapter, addr) & MEM_INT_MASK; 2443 if (v & F_PERR_INT_CAUSE) 2444 CH_ALERT(adapter, "%s FIFO parity error\n", name[idx]); 2445 if (v & F_ECC_CE_INT_CAUSE) { 2446 u32 cnt = G_ECC_CECNT(t4_read_reg(adapter, cnt_addr)); 2447 2448 t4_write_reg(adapter, cnt_addr, V_ECC_CECNT(M_ECC_CECNT)); 2449 CH_WARN_RATELIMIT(adapter, 2450 "%u %s correctable ECC data error%s\n", 2451 cnt, name[idx], cnt > 1 ? "s" : ""); 2452 } 2453 if (v & F_ECC_UE_INT_CAUSE) 2454 CH_ALERT(adapter, "%s uncorrectable ECC data error\n", 2455 name[idx]); 2456 2457 t4_write_reg(adapter, addr, v); 2458 if (v & (F_PERR_INT_CAUSE | F_ECC_UE_INT_CAUSE)) 2459 t4_fatal_err(adapter); 2460} 2461 2462/* 2463 * MA interrupt handler. 2464 */ 2465static void ma_intr_handler(struct adapter *adapter) 2466{ 2467 u32 v, status = t4_read_reg(adapter, A_MA_INT_CAUSE); 2468 2469 if (status & F_MEM_PERR_INT_CAUSE) { 2470 CH_ALERT(adapter, "MA parity error, parity status %#x\n", 2471 t4_read_reg(adapter, A_MA_PARITY_ERROR_STATUS1)); 2472 if (is_t5(adapter)) 2473 CH_ALERT(adapter, 2474 "MA parity error, parity status %#x\n", 2475 t4_read_reg(adapter, 2476 A_MA_PARITY_ERROR_STATUS2)); 2477 } 2478 if (status & F_MEM_WRAP_INT_CAUSE) { 2479 v = t4_read_reg(adapter, A_MA_INT_WRAP_STATUS); 2480 CH_ALERT(adapter, "MA address wrap-around error by client %u to" 2481 " address %#x\n", G_MEM_WRAP_CLIENT_NUM(v), 2482 G_MEM_WRAP_ADDRESS(v) << 4); 2483 } 2484 t4_write_reg(adapter, A_MA_INT_CAUSE, status); 2485 t4_fatal_err(adapter); 2486} 2487 2488/* 2489 * SMB interrupt handler. 2490 */ 2491static void smb_intr_handler(struct adapter *adap) 2492{ 2493 static struct intr_info smb_intr_info[] = { 2494 { F_MSTTXFIFOPARINT, "SMB master Tx FIFO parity error", -1, 1 }, 2495 { F_MSTRXFIFOPARINT, "SMB master Rx FIFO parity error", -1, 1 }, 2496 { F_SLVFIFOPARINT, "SMB slave FIFO parity error", -1, 1 }, 2497 { 0 } 2498 }; 2499 2500 if (t4_handle_intr_status(adap, A_SMB_INT_CAUSE, smb_intr_info)) 2501 t4_fatal_err(adap); 2502} 2503 2504/* 2505 * NC-SI interrupt handler. 2506 */ 2507static void ncsi_intr_handler(struct adapter *adap) 2508{ 2509 static struct intr_info ncsi_intr_info[] = { 2510 { F_CIM_DM_PRTY_ERR, "NC-SI CIM parity error", -1, 1 }, 2511 { F_MPS_DM_PRTY_ERR, "NC-SI MPS parity error", -1, 1 }, 2512 { F_TXFIFO_PRTY_ERR, "NC-SI Tx FIFO parity error", -1, 1 }, 2513 { F_RXFIFO_PRTY_ERR, "NC-SI Rx FIFO parity error", -1, 1 }, 2514 { 0 } 2515 }; 2516 2517 if (t4_handle_intr_status(adap, A_NCSI_INT_CAUSE, ncsi_intr_info)) 2518 t4_fatal_err(adap); 2519} 2520 2521/* 2522 * XGMAC interrupt handler. 2523 */ 2524static void xgmac_intr_handler(struct adapter *adap, int port) 2525{ 2526 u32 v, int_cause_reg; 2527 2528 if (is_t4(adap)) 2529 int_cause_reg = PORT_REG(port, A_XGMAC_PORT_INT_CAUSE); 2530 else 2531 int_cause_reg = T5_PORT_REG(port, A_MAC_PORT_INT_CAUSE); 2532 2533 v = t4_read_reg(adap, int_cause_reg); 2534 v &= (F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR); 2535 if (!v) 2536 return; 2537 2538 if (v & F_TXFIFO_PRTY_ERR) 2539 CH_ALERT(adap, "XGMAC %d Tx FIFO parity error\n", port); 2540 if (v & F_RXFIFO_PRTY_ERR) 2541 CH_ALERT(adap, "XGMAC %d Rx FIFO parity error\n", port); 2542 t4_write_reg(adap, int_cause_reg, v); 2543 t4_fatal_err(adap); 2544} 2545 2546/* 2547 * PL interrupt handler. 2548 */ 2549static void pl_intr_handler(struct adapter *adap) 2550{ 2551 static struct intr_info pl_intr_info[] = { 2552 { F_FATALPERR, "Fatal parity error", -1, 1 }, 2553 { F_PERRVFID, "PL VFID_MAP parity error", -1, 1 }, 2554 { 0 } 2555 }; 2556 2557 static struct intr_info t5_pl_intr_info[] = { 2558 { F_PL_BUSPERR, "PL bus parity error", -1, 1 }, 2559 { F_FATALPERR, "Fatal parity error", -1, 1 }, 2560 { 0 } 2561 }; 2562 2563 if (t4_handle_intr_status(adap, A_PL_PL_INT_CAUSE, 2564 is_t4(adap) ? pl_intr_info : t5_pl_intr_info)) 2565 t4_fatal_err(adap); 2566} 2567 2568#define PF_INTR_MASK (F_PFSW | F_PFCIM) 2569#define GLBL_INTR_MASK (F_CIM | F_MPS | F_PL | F_PCIE | F_MC | F_EDC0 | \ 2570 F_EDC1 | F_LE | F_TP | F_MA | F_PM_TX | F_PM_RX | F_ULP_RX | \ 2571 F_CPL_SWITCH | F_SGE | F_ULP_TX) 2572 2573/** 2574 * t4_slow_intr_handler - control path interrupt handler 2575 * @adapter: the adapter 2576 * 2577 * T4 interrupt handler for non-data global interrupt events, e.g., errors. 2578 * The designation 'slow' is because it involves register reads, while 2579 * data interrupts typically don't involve any MMIOs. 2580 */ 2581int t4_slow_intr_handler(struct adapter *adapter) 2582{ 2583 u32 cause = t4_read_reg(adapter, A_PL_INT_CAUSE); 2584 2585 if (!(cause & GLBL_INTR_MASK)) 2586 return 0; 2587 if (cause & F_CIM) 2588 cim_intr_handler(adapter); 2589 if (cause & F_MPS) 2590 mps_intr_handler(adapter); 2591 if (cause & F_NCSI) 2592 ncsi_intr_handler(adapter); 2593 if (cause & F_PL) 2594 pl_intr_handler(adapter); 2595 if (cause & F_SMB) 2596 smb_intr_handler(adapter); 2597 if (cause & F_XGMAC0) 2598 xgmac_intr_handler(adapter, 0); 2599 if (cause & F_XGMAC1) 2600 xgmac_intr_handler(adapter, 1); 2601 if (cause & F_XGMAC_KR0) 2602 xgmac_intr_handler(adapter, 2); 2603 if (cause & F_XGMAC_KR1) 2604 xgmac_intr_handler(adapter, 3); 2605 if (cause & F_PCIE) 2606 pcie_intr_handler(adapter); 2607 if (cause & F_MC) 2608 mem_intr_handler(adapter, MEM_MC); 2609 if (cause & F_EDC0) 2610 mem_intr_handler(adapter, MEM_EDC0); 2611 if (cause & F_EDC1) 2612 mem_intr_handler(adapter, MEM_EDC1); 2613 if (cause & F_LE) 2614 le_intr_handler(adapter); 2615 if (cause & F_TP) 2616 tp_intr_handler(adapter); 2617 if (cause & F_MA) 2618 ma_intr_handler(adapter); 2619 if (cause & F_PM_TX) 2620 pmtx_intr_handler(adapter); 2621 if (cause & F_PM_RX) 2622 pmrx_intr_handler(adapter); 2623 if (cause & F_ULP_RX) 2624 ulprx_intr_handler(adapter); 2625 if (cause & F_CPL_SWITCH) 2626 cplsw_intr_handler(adapter); 2627 if (cause & F_SGE) 2628 sge_intr_handler(adapter); 2629 if (cause & F_ULP_TX) 2630 ulptx_intr_handler(adapter); 2631 2632 /* Clear the interrupts just processed for which we are the master. */ 2633 t4_write_reg(adapter, A_PL_INT_CAUSE, cause & GLBL_INTR_MASK); 2634 (void) t4_read_reg(adapter, A_PL_INT_CAUSE); /* flush */ 2635 return 1; 2636} 2637 2638/** 2639 * t4_intr_enable - enable interrupts 2640 * @adapter: the adapter whose interrupts should be enabled 2641 * 2642 * Enable PF-specific interrupts for the calling function and the top-level 2643 * interrupt concentrator for global interrupts. Interrupts are already 2644 * enabled at each module, here we just enable the roots of the interrupt 2645 * hierarchies. 2646 * 2647 * Note: this function should be called only when the driver manages 2648 * non PF-specific interrupts from the various HW modules. Only one PCI 2649 * function at a time should be doing this. 2650 */ 2651void t4_intr_enable(struct adapter *adapter) 2652{ 2653 u32 pf = G_SOURCEPF(t4_read_reg(adapter, A_PL_WHOAMI)); 2654 2655 t4_write_reg(adapter, A_SGE_INT_ENABLE3, F_ERR_CPL_EXCEED_IQE_SIZE | 2656 F_ERR_INVALID_CIDX_INC | F_ERR_CPL_OPCODE_0 | 2657 F_ERR_DROPPED_DB | F_ERR_DATA_CPL_ON_HIGH_QID1 | 2658 F_ERR_DATA_CPL_ON_HIGH_QID0 | F_ERR_BAD_DB_PIDX3 | 2659 F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 | 2660 F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO | 2661 F_ERR_EGR_CTXT_PRIO | F_INGRESS_SIZE_ERR | 2662 F_EGRESS_SIZE_ERR); 2663 t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), PF_INTR_MASK); 2664 t4_set_reg_field(adapter, A_PL_INT_MAP0, 0, 1 << pf); 2665} 2666 2667/** 2668 * t4_intr_disable - disable interrupts 2669 * @adapter: the adapter whose interrupts should be disabled 2670 * 2671 * Disable interrupts. We only disable the top-level interrupt 2672 * concentrators. The caller must be a PCI function managing global 2673 * interrupts. 2674 */ 2675void t4_intr_disable(struct adapter *adapter) 2676{ 2677 u32 pf = G_SOURCEPF(t4_read_reg(adapter, A_PL_WHOAMI)); 2678 2679 t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), 0); 2680 t4_set_reg_field(adapter, A_PL_INT_MAP0, 1 << pf, 0); 2681} 2682 2683/** 2684 * t4_intr_clear - clear all interrupts 2685 * @adapter: the adapter whose interrupts should be cleared 2686 * 2687 * Clears all interrupts. The caller must be a PCI function managing 2688 * global interrupts. 2689 */ 2690void t4_intr_clear(struct adapter *adapter) 2691{ 2692 static const unsigned int cause_reg[] = { 2693 A_SGE_INT_CAUSE1, A_SGE_INT_CAUSE2, A_SGE_INT_CAUSE3, 2694 A_PCIE_NONFAT_ERR, A_PCIE_INT_CAUSE, 2695 A_MA_INT_WRAP_STATUS, A_MA_PARITY_ERROR_STATUS1, A_MA_INT_CAUSE, 2696 A_EDC_INT_CAUSE, EDC_REG(A_EDC_INT_CAUSE, 1), 2697 A_CIM_HOST_INT_CAUSE, A_CIM_HOST_UPACC_INT_CAUSE, 2698 MYPF_REG(A_CIM_PF_HOST_INT_CAUSE), 2699 A_TP_INT_CAUSE, 2700 A_ULP_RX_INT_CAUSE, A_ULP_TX_INT_CAUSE, 2701 A_PM_RX_INT_CAUSE, A_PM_TX_INT_CAUSE, 2702 A_MPS_RX_PERR_INT_CAUSE, 2703 A_CPL_INTR_CAUSE, 2704 MYPF_REG(A_PL_PF_INT_CAUSE), 2705 A_PL_PL_INT_CAUSE, 2706 A_LE_DB_INT_CAUSE, 2707 }; 2708 2709 unsigned int i; 2710 2711 for (i = 0; i < ARRAY_SIZE(cause_reg); ++i) 2712 t4_write_reg(adapter, cause_reg[i], 0xffffffff); 2713 2714 t4_write_reg(adapter, is_t4(adapter) ? A_MC_INT_CAUSE : 2715 A_MC_P_INT_CAUSE, 0xffffffff); 2716 2717 if (is_t4(adapter)) { 2718 t4_write_reg(adapter, A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS, 2719 0xffffffff); 2720 t4_write_reg(adapter, A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, 2721 0xffffffff); 2722 } else 2723 t4_write_reg(adapter, A_MA_PARITY_ERROR_STATUS2, 0xffffffff); 2724 2725 t4_write_reg(adapter, A_PL_INT_CAUSE, GLBL_INTR_MASK); 2726 (void) t4_read_reg(adapter, A_PL_INT_CAUSE); /* flush */ 2727} 2728 2729/** 2730 * hash_mac_addr - return the hash value of a MAC address 2731 * @addr: the 48-bit Ethernet MAC address 2732 * 2733 * Hashes a MAC address according to the hash function used by HW inexact 2734 * (hash) address matching. 2735 */ 2736static int hash_mac_addr(const u8 *addr) 2737{ 2738 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 2739 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 2740 a ^= b; 2741 a ^= (a >> 12); 2742 a ^= (a >> 6); 2743 return a & 0x3f; 2744} 2745 2746/** 2747 * t4_config_rss_range - configure a portion of the RSS mapping table 2748 * @adapter: the adapter 2749 * @mbox: mbox to use for the FW command 2750 * @viid: virtual interface whose RSS subtable is to be written 2751 * @start: start entry in the table to write 2752 * @n: how many table entries to write 2753 * @rspq: values for the "response queue" (Ingress Queue) lookup table 2754 * @nrspq: number of values in @rspq 2755 * 2756 * Programs the selected part of the VI's RSS mapping table with the 2757 * provided values. If @nrspq < @n the supplied values are used repeatedly 2758 * until the full table range is populated. 2759 * 2760 * The caller must ensure the values in @rspq are in the range allowed for 2761 * @viid. 2762 */ 2763int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 2764 int start, int n, const u16 *rspq, unsigned int nrspq) 2765{ 2766 int ret; 2767 const u16 *rsp = rspq; 2768 const u16 *rsp_end = rspq + nrspq; 2769 struct fw_rss_ind_tbl_cmd cmd; 2770 2771 memset(&cmd, 0, sizeof(cmd)); 2772 cmd.op_to_viid = htonl(V_FW_CMD_OP(FW_RSS_IND_TBL_CMD) | 2773 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 2774 V_FW_RSS_IND_TBL_CMD_VIID(viid)); 2775 cmd.retval_len16 = htonl(FW_LEN16(cmd)); 2776 2777 2778 /* 2779 * Each firmware RSS command can accommodate up to 32 RSS Ingress 2780 * Queue Identifiers. These Ingress Queue IDs are packed three to 2781 * a 32-bit word as 10-bit values with the upper remaining 2 bits 2782 * reserved. 2783 */ 2784 while (n > 0) { 2785 int nq = min(n, 32); 2786 int nq_packed = 0; 2787 __be32 *qp = &cmd.iq0_to_iq2; 2788 2789 /* 2790 * Set up the firmware RSS command header to send the next 2791 * "nq" Ingress Queue IDs to the firmware. 2792 */ 2793 cmd.niqid = htons(nq); 2794 cmd.startidx = htons(start); 2795 2796 /* 2797 * "nq" more done for the start of the next loop. 2798 */ 2799 start += nq; 2800 n -= nq; 2801 2802 /* 2803 * While there are still Ingress Queue IDs to stuff into the 2804 * current firmware RSS command, retrieve them from the 2805 * Ingress Queue ID array and insert them into the command. 2806 */ 2807 while (nq > 0) { 2808 /* 2809 * Grab up to the next 3 Ingress Queue IDs (wrapping 2810 * around the Ingress Queue ID array if necessary) and 2811 * insert them into the firmware RSS command at the 2812 * current 3-tuple position within the commad. 2813 */ 2814 u16 qbuf[3]; 2815 u16 *qbp = qbuf; 2816 int nqbuf = min(3, nq); 2817 2818 nq -= nqbuf; 2819 qbuf[0] = qbuf[1] = qbuf[2] = 0; 2820 while (nqbuf && nq_packed < 32) { 2821 nqbuf--; 2822 nq_packed++; 2823 *qbp++ = *rsp++; 2824 if (rsp >= rsp_end) 2825 rsp = rspq; 2826 } 2827 *qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) | 2828 V_FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) | 2829 V_FW_RSS_IND_TBL_CMD_IQ2(qbuf[2])); 2830 } 2831 2832 /* 2833 * Send this portion of the RRS table update to the firmware; 2834 * bail out on any errors. 2835 */ 2836 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL); 2837 if (ret) 2838 return ret; 2839 } 2840 2841 return 0; 2842} 2843 2844/** 2845 * t4_config_glbl_rss - configure the global RSS mode 2846 * @adapter: the adapter 2847 * @mbox: mbox to use for the FW command 2848 * @mode: global RSS mode 2849 * @flags: mode-specific flags 2850 * 2851 * Sets the global RSS mode. 2852 */ 2853int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 2854 unsigned int flags) 2855{ 2856 struct fw_rss_glb_config_cmd c; 2857 2858 memset(&c, 0, sizeof(c)); 2859 c.op_to_write = htonl(V_FW_CMD_OP(FW_RSS_GLB_CONFIG_CMD) | 2860 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 2861 c.retval_len16 = htonl(FW_LEN16(c)); 2862 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) { 2863 c.u.manual.mode_pkd = htonl(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode)); 2864 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) { 2865 c.u.basicvirtual.mode_pkd = 2866 htonl(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode)); 2867 c.u.basicvirtual.synmapen_to_hashtoeplitz = htonl(flags); 2868 } else 2869 return -EINVAL; 2870 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL); 2871} 2872 2873/** 2874 * t4_config_vi_rss - configure per VI RSS settings 2875 * @adapter: the adapter 2876 * @mbox: mbox to use for the FW command 2877 * @viid: the VI id 2878 * @flags: RSS flags 2879 * @defq: id of the default RSS queue for the VI. 2880 * 2881 * Configures VI-specific RSS properties. 2882 */ 2883int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 2884 unsigned int flags, unsigned int defq) 2885{ 2886 struct fw_rss_vi_config_cmd c; 2887 2888 memset(&c, 0, sizeof(c)); 2889 c.op_to_viid = htonl(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) | 2890 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 2891 V_FW_RSS_VI_CONFIG_CMD_VIID(viid)); 2892 c.retval_len16 = htonl(FW_LEN16(c)); 2893 c.u.basicvirtual.defaultq_to_udpen = htonl(flags | 2894 V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(defq)); 2895 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL); 2896} 2897 2898/* Read an RSS table row */ 2899static int rd_rss_row(struct adapter *adap, int row, u32 *val) 2900{ 2901 t4_write_reg(adap, A_TP_RSS_LKP_TABLE, 0xfff00000 | row); 2902 return t4_wait_op_done_val(adap, A_TP_RSS_LKP_TABLE, F_LKPTBLROWVLD, 1, 2903 5, 0, val); 2904} 2905 2906/** 2907 * t4_read_rss - read the contents of the RSS mapping table 2908 * @adapter: the adapter 2909 * @map: holds the contents of the RSS mapping table 2910 * 2911 * Reads the contents of the RSS hash->queue mapping table. 2912 */ 2913int t4_read_rss(struct adapter *adapter, u16 *map) 2914{ 2915 u32 val; 2916 int i, ret; 2917 2918 for (i = 0; i < RSS_NENTRIES / 2; ++i) { 2919 ret = rd_rss_row(adapter, i, &val); 2920 if (ret) 2921 return ret; 2922 *map++ = G_LKPTBLQUEUE0(val); 2923 *map++ = G_LKPTBLQUEUE1(val); 2924 } 2925 return 0; 2926} 2927 2928/** 2929 * t4_read_rss_key - read the global RSS key 2930 * @adap: the adapter 2931 * @key: 10-entry array holding the 320-bit RSS key 2932 * 2933 * Reads the global 320-bit RSS key. 2934 */ 2935void t4_read_rss_key(struct adapter *adap, u32 *key) 2936{ 2937 t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, key, 10, 2938 A_TP_RSS_SECRET_KEY0); 2939} 2940 2941/** 2942 * t4_write_rss_key - program one of the RSS keys 2943 * @adap: the adapter 2944 * @key: 10-entry array holding the 320-bit RSS key 2945 * @idx: which RSS key to write 2946 * 2947 * Writes one of the RSS keys with the given 320-bit value. If @idx is 2948 * 0..15 the corresponding entry in the RSS key table is written, 2949 * otherwise the global RSS key is written. 2950 */ 2951void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx) 2952{ 2953 t4_write_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, key, 10, 2954 A_TP_RSS_SECRET_KEY0); 2955 if (idx >= 0 && idx < 16) 2956 t4_write_reg(adap, A_TP_RSS_CONFIG_VRT, 2957 V_KEYWRADDR(idx) | F_KEYWREN); 2958} 2959 2960/** 2961 * t4_read_rss_pf_config - read PF RSS Configuration Table 2962 * @adapter: the adapter 2963 * @index: the entry in the PF RSS table to read 2964 * @valp: where to store the returned value 2965 * 2966 * Reads the PF RSS Configuration Table at the specified index and returns 2967 * the value found there. 2968 */ 2969void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, u32 *valp) 2970{ 2971 t4_read_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA, 2972 valp, 1, A_TP_RSS_PF0_CONFIG + index); 2973} 2974 2975/** 2976 * t4_write_rss_pf_config - write PF RSS Configuration Table 2977 * @adapter: the adapter 2978 * @index: the entry in the VF RSS table to read 2979 * @val: the value to store 2980 * 2981 * Writes the PF RSS Configuration Table at the specified index with the 2982 * specified value. 2983 */ 2984void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index, u32 val) 2985{ 2986 t4_write_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA, 2987 &val, 1, A_TP_RSS_PF0_CONFIG + index); 2988} 2989 2990/** 2991 * t4_read_rss_vf_config - read VF RSS Configuration Table 2992 * @adapter: the adapter 2993 * @index: the entry in the VF RSS table to read 2994 * @vfl: where to store the returned VFL 2995 * @vfh: where to store the returned VFH 2996 * 2997 * Reads the VF RSS Configuration Table at the specified index and returns 2998 * the (VFL, VFH) values found there. 2999 */ 3000void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 3001 u32 *vfl, u32 *vfh) 3002{ 3003 u32 vrt; 3004 3005 /* 3006 * Request that the index'th VF Table values be read into VFL/VFH. 3007 */ 3008 vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT); 3009 vrt &= ~(F_VFRDRG | V_VFWRADDR(M_VFWRADDR) | F_VFWREN | F_KEYWREN); 3010 vrt |= V_VFWRADDR(index) | F_VFRDEN; 3011 t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt); 3012 3013 /* 3014 * Grab the VFL/VFH values ... 3015 */ 3016 t4_read_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA, 3017 vfl, 1, A_TP_RSS_VFL_CONFIG); 3018 t4_read_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA, 3019 vfh, 1, A_TP_RSS_VFH_CONFIG); 3020} 3021 3022/** 3023 * t4_write_rss_vf_config - write VF RSS Configuration Table 3024 * 3025 * @adapter: the adapter 3026 * @index: the entry in the VF RSS table to write 3027 * @vfl: the VFL to store 3028 * @vfh: the VFH to store 3029 * 3030 * Writes the VF RSS Configuration Table at the specified index with the 3031 * specified (VFL, VFH) values. 3032 */ 3033void t4_write_rss_vf_config(struct adapter *adapter, unsigned int index, 3034 u32 vfl, u32 vfh) 3035{ 3036 u32 vrt; 3037 3038 /* 3039 * Load up VFL/VFH with the values to be written ... 3040 */ 3041 t4_write_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA, 3042 &vfl, 1, A_TP_RSS_VFL_CONFIG); 3043 t4_write_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA, 3044 &vfh, 1, A_TP_RSS_VFH_CONFIG); 3045 3046 /* 3047 * Write the VFL/VFH into the VF Table at index'th location. 3048 */ 3049 vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT); 3050 vrt &= ~(F_VFRDRG | F_VFRDEN | V_VFWRADDR(M_VFWRADDR) | F_KEYWREN); 3051 vrt |= V_VFWRADDR(index) | F_VFWREN; 3052 t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt); 3053} 3054 3055/** 3056 * t4_read_rss_pf_map - read PF RSS Map 3057 * @adapter: the adapter 3058 * 3059 * Reads the PF RSS Map register and returns its value. 3060 */ 3061u32 t4_read_rss_pf_map(struct adapter *adapter) 3062{ 3063 u32 pfmap; 3064 3065 t4_read_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA, 3066 &pfmap, 1, A_TP_RSS_PF_MAP); 3067 return pfmap; 3068} 3069 3070/** 3071 * t4_write_rss_pf_map - write PF RSS Map 3072 * @adapter: the adapter 3073 * @pfmap: PF RSS Map value 3074 * 3075 * Writes the specified value to the PF RSS Map register. 3076 */ 3077void t4_write_rss_pf_map(struct adapter *adapter, u32 pfmap) 3078{ 3079 t4_write_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA, 3080 &pfmap, 1, A_TP_RSS_PF_MAP); 3081} 3082 3083/** 3084 * t4_read_rss_pf_mask - read PF RSS Mask 3085 * @adapter: the adapter 3086 * 3087 * Reads the PF RSS Mask register and returns its value. 3088 */ 3089u32 t4_read_rss_pf_mask(struct adapter *adapter) 3090{ 3091 u32 pfmask; 3092 3093 t4_read_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA, 3094 &pfmask, 1, A_TP_RSS_PF_MSK); 3095 return pfmask; 3096} 3097 3098/** 3099 * t4_write_rss_pf_mask - write PF RSS Mask 3100 * @adapter: the adapter 3101 * @pfmask: PF RSS Mask value 3102 * 3103 * Writes the specified value to the PF RSS Mask register. 3104 */ 3105void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask) 3106{ 3107 t4_write_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA, 3108 &pfmask, 1, A_TP_RSS_PF_MSK); 3109} 3110 3111/** 3112 * t4_set_filter_mode - configure the optional components of filter tuples 3113 * @adap: the adapter 3114 * @mode_map: a bitmap selcting which optional filter components to enable 3115 * 3116 * Sets the filter mode by selecting the optional components to enable 3117 * in filter tuples. Returns 0 on success and a negative error if the 3118 * requested mode needs more bits than are available for optional 3119 * components. 3120 */ 3121int t4_set_filter_mode(struct adapter *adap, unsigned int mode_map) 3122{ 3123 static u8 width[] = { 1, 3, 17, 17, 8, 8, 16, 9, 3, 1 }; 3124 3125 int i, nbits = 0; 3126 3127 for (i = S_FCOE; i <= S_FRAGMENTATION; i++) 3128 if (mode_map & (1 << i)) 3129 nbits += width[i]; 3130 if (nbits > FILTER_OPT_LEN) 3131 return -EINVAL; 3132 t4_write_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, &mode_map, 1, 3133 A_TP_VLAN_PRI_MAP); 3134 return 0; 3135} 3136 3137/** 3138 * t4_tp_get_tcp_stats - read TP's TCP MIB counters 3139 * @adap: the adapter 3140 * @v4: holds the TCP/IP counter values 3141 * @v6: holds the TCP/IPv6 counter values 3142 * 3143 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters. 3144 * Either @v4 or @v6 may be %NULL to skip the corresponding stats. 3145 */ 3146void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 3147 struct tp_tcp_stats *v6) 3148{ 3149 u32 val[A_TP_MIB_TCP_RXT_SEG_LO - A_TP_MIB_TCP_OUT_RST + 1]; 3150 3151#define STAT_IDX(x) ((A_TP_MIB_TCP_##x) - A_TP_MIB_TCP_OUT_RST) 3152#define STAT(x) val[STAT_IDX(x)] 3153#define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO)) 3154 3155 if (v4) { 3156 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, val, 3157 ARRAY_SIZE(val), A_TP_MIB_TCP_OUT_RST); 3158 v4->tcpOutRsts = STAT(OUT_RST); 3159 v4->tcpInSegs = STAT64(IN_SEG); 3160 v4->tcpOutSegs = STAT64(OUT_SEG); 3161 v4->tcpRetransSegs = STAT64(RXT_SEG); 3162 } 3163 if (v6) { 3164 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, val, 3165 ARRAY_SIZE(val), A_TP_MIB_TCP_V6OUT_RST); 3166 v6->tcpOutRsts = STAT(OUT_RST); 3167 v6->tcpInSegs = STAT64(IN_SEG); 3168 v6->tcpOutSegs = STAT64(OUT_SEG); 3169 v6->tcpRetransSegs = STAT64(RXT_SEG); 3170 } 3171#undef STAT64 3172#undef STAT 3173#undef STAT_IDX 3174} 3175 3176/** 3177 * t4_tp_get_err_stats - read TP's error MIB counters 3178 * @adap: the adapter 3179 * @st: holds the counter values 3180 * 3181 * Returns the values of TP's error counters. 3182 */ 3183void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st) 3184{ 3185 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, st->macInErrs, 3186 12, A_TP_MIB_MAC_IN_ERR_0); 3187 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, st->tnlCongDrops, 3188 8, A_TP_MIB_TNL_CNG_DROP_0); 3189 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, st->tnlTxDrops, 3190 4, A_TP_MIB_TNL_DROP_0); 3191 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, st->ofldVlanDrops, 3192 4, A_TP_MIB_OFD_VLN_DROP_0); 3193 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, st->tcp6InErrs, 3194 4, A_TP_MIB_TCP_V6IN_ERR_0); 3195 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, &st->ofldNoNeigh, 3196 2, A_TP_MIB_OFD_ARP_DROP); 3197} 3198 3199/** 3200 * t4_tp_get_proxy_stats - read TP's proxy MIB counters 3201 * @adap: the adapter 3202 * @st: holds the counter values 3203 * 3204 * Returns the values of TP's proxy counters. 3205 */ 3206void t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st) 3207{ 3208 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, st->proxy, 3209 4, A_TP_MIB_TNL_LPBK_0); 3210} 3211 3212/** 3213 * t4_tp_get_cpl_stats - read TP's CPL MIB counters 3214 * @adap: the adapter 3215 * @st: holds the counter values 3216 * 3217 * Returns the values of TP's CPL counters. 3218 */ 3219void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st) 3220{ 3221 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, st->req, 3222 8, A_TP_MIB_CPL_IN_REQ_0); 3223} 3224 3225/** 3226 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters 3227 * @adap: the adapter 3228 * @st: holds the counter values 3229 * 3230 * Returns the values of TP's RDMA counters. 3231 */ 3232void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st) 3233{ 3234 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, &st->rqe_dfr_mod, 3235 2, A_TP_MIB_RQE_DFR_MOD); 3236} 3237 3238/** 3239 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port 3240 * @adap: the adapter 3241 * @idx: the port index 3242 * @st: holds the counter values 3243 * 3244 * Returns the values of TP's FCoE counters for the selected port. 3245 */ 3246void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 3247 struct tp_fcoe_stats *st) 3248{ 3249 u32 val[2]; 3250 3251 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, &st->framesDDP, 3252 1, A_TP_MIB_FCOE_DDP_0 + idx); 3253 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, &st->framesDrop, 3254 1, A_TP_MIB_FCOE_DROP_0 + idx); 3255 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, val, 3256 2, A_TP_MIB_FCOE_BYTE_0_HI + 2 * idx); 3257 st->octetsDDP = ((u64)val[0] << 32) | val[1]; 3258} 3259 3260/** 3261 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters 3262 * @adap: the adapter 3263 * @st: holds the counter values 3264 * 3265 * Returns the values of TP's counters for non-TCP directly-placed packets. 3266 */ 3267void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st) 3268{ 3269 u32 val[4]; 3270 3271 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, val, 4, 3272 A_TP_MIB_USM_PKTS); 3273 st->frames = val[0]; 3274 st->drops = val[1]; 3275 st->octets = ((u64)val[2] << 32) | val[3]; 3276} 3277 3278/** 3279 * t4_read_mtu_tbl - returns the values in the HW path MTU table 3280 * @adap: the adapter 3281 * @mtus: where to store the MTU values 3282 * @mtu_log: where to store the MTU base-2 log (may be %NULL) 3283 * 3284 * Reads the HW path MTU table. 3285 */ 3286void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log) 3287{ 3288 u32 v; 3289 int i; 3290 3291 for (i = 0; i < NMTUS; ++i) { 3292 t4_write_reg(adap, A_TP_MTU_TABLE, 3293 V_MTUINDEX(0xff) | V_MTUVALUE(i)); 3294 v = t4_read_reg(adap, A_TP_MTU_TABLE); 3295 mtus[i] = G_MTUVALUE(v); 3296 if (mtu_log) 3297 mtu_log[i] = G_MTUWIDTH(v); 3298 } 3299} 3300 3301/** 3302 * t4_read_cong_tbl - reads the congestion control table 3303 * @adap: the adapter 3304 * @incr: where to store the alpha values 3305 * 3306 * Reads the additive increments programmed into the HW congestion 3307 * control table. 3308 */ 3309void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]) 3310{ 3311 unsigned int mtu, w; 3312 3313 for (mtu = 0; mtu < NMTUS; ++mtu) 3314 for (w = 0; w < NCCTRL_WIN; ++w) { 3315 t4_write_reg(adap, A_TP_CCTRL_TABLE, 3316 V_ROWINDEX(0xffff) | (mtu << 5) | w); 3317 incr[mtu][w] = (u16)t4_read_reg(adap, 3318 A_TP_CCTRL_TABLE) & 0x1fff; 3319 } 3320} 3321 3322/** 3323 * t4_read_pace_tbl - read the pace table 3324 * @adap: the adapter 3325 * @pace_vals: holds the returned values 3326 * 3327 * Returns the values of TP's pace table in microseconds. 3328 */ 3329void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]) 3330{ 3331 unsigned int i, v; 3332 3333 for (i = 0; i < NTX_SCHED; i++) { 3334 t4_write_reg(adap, A_TP_PACE_TABLE, 0xffff0000 + i); 3335 v = t4_read_reg(adap, A_TP_PACE_TABLE); 3336 pace_vals[i] = dack_ticks_to_usec(adap, v); 3337 } 3338} 3339 3340/** 3341 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register 3342 * @adap: the adapter 3343 * @addr: the indirect TP register address 3344 * @mask: specifies the field within the register to modify 3345 * @val: new value for the field 3346 * 3347 * Sets a field of an indirect TP register to the given value. 3348 */ 3349void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 3350 unsigned int mask, unsigned int val) 3351{ 3352 t4_write_reg(adap, A_TP_PIO_ADDR, addr); 3353 val |= t4_read_reg(adap, A_TP_PIO_DATA) & ~mask; 3354 t4_write_reg(adap, A_TP_PIO_DATA, val); 3355} 3356 3357/** 3358 * init_cong_ctrl - initialize congestion control parameters 3359 * @a: the alpha values for congestion control 3360 * @b: the beta values for congestion control 3361 * 3362 * Initialize the congestion control parameters. 3363 */ 3364static void __devinit init_cong_ctrl(unsigned short *a, unsigned short *b) 3365{ 3366 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1; 3367 a[9] = 2; 3368 a[10] = 3; 3369 a[11] = 4; 3370 a[12] = 5; 3371 a[13] = 6; 3372 a[14] = 7; 3373 a[15] = 8; 3374 a[16] = 9; 3375 a[17] = 10; 3376 a[18] = 14; 3377 a[19] = 17; 3378 a[20] = 21; 3379 a[21] = 25; 3380 a[22] = 30; 3381 a[23] = 35; 3382 a[24] = 45; 3383 a[25] = 60; 3384 a[26] = 80; 3385 a[27] = 100; 3386 a[28] = 200; 3387 a[29] = 300; 3388 a[30] = 400; 3389 a[31] = 500; 3390 3391 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0; 3392 b[9] = b[10] = 1; 3393 b[11] = b[12] = 2; 3394 b[13] = b[14] = b[15] = b[16] = 3; 3395 b[17] = b[18] = b[19] = b[20] = b[21] = 4; 3396 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5; 3397 b[28] = b[29] = 6; 3398 b[30] = b[31] = 7; 3399} 3400 3401/* The minimum additive increment value for the congestion control table */ 3402#define CC_MIN_INCR 2U 3403 3404/** 3405 * t4_load_mtus - write the MTU and congestion control HW tables 3406 * @adap: the adapter 3407 * @mtus: the values for the MTU table 3408 * @alpha: the values for the congestion control alpha parameter 3409 * @beta: the values for the congestion control beta parameter 3410 * 3411 * Write the HW MTU table with the supplied MTUs and the high-speed 3412 * congestion control table with the supplied alpha, beta, and MTUs. 3413 * We write the two tables together because the additive increments 3414 * depend on the MTUs. 3415 */ 3416void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 3417 const unsigned short *alpha, const unsigned short *beta) 3418{ 3419 static const unsigned int avg_pkts[NCCTRL_WIN] = { 3420 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640, 3421 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480, 3422 28672, 40960, 57344, 81920, 114688, 163840, 229376 3423 }; 3424 3425 unsigned int i, w; 3426 3427 for (i = 0; i < NMTUS; ++i) { 3428 unsigned int mtu = mtus[i]; 3429 unsigned int log2 = fls(mtu); 3430 3431 if (!(mtu & ((1 << log2) >> 2))) /* round */ 3432 log2--; 3433 t4_write_reg(adap, A_TP_MTU_TABLE, V_MTUINDEX(i) | 3434 V_MTUWIDTH(log2) | V_MTUVALUE(mtu)); 3435 3436 for (w = 0; w < NCCTRL_WIN; ++w) { 3437 unsigned int inc; 3438 3439 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w], 3440 CC_MIN_INCR); 3441 3442 t4_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) | 3443 (w << 16) | (beta[w] << 13) | inc); 3444 } 3445 } 3446} 3447 3448/** 3449 * t4_set_pace_tbl - set the pace table 3450 * @adap: the adapter 3451 * @pace_vals: the pace values in microseconds 3452 * @start: index of the first entry in the HW pace table to set 3453 * @n: how many entries to set 3454 * 3455 * Sets (a subset of the) HW pace table. 3456 */ 3457int t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals, 3458 unsigned int start, unsigned int n) 3459{ 3460 unsigned int vals[NTX_SCHED], i; 3461 unsigned int tick_ns = dack_ticks_to_usec(adap, 1000); 3462 3463 if (n > NTX_SCHED) 3464 return -ERANGE; 3465 3466 /* convert values from us to dack ticks, rounding to closest value */ 3467 for (i = 0; i < n; i++, pace_vals++) { 3468 vals[i] = (1000 * *pace_vals + tick_ns / 2) / tick_ns; 3469 if (vals[i] > 0x7ff) 3470 return -ERANGE; 3471 if (*pace_vals && vals[i] == 0) 3472 return -ERANGE; 3473 } 3474 for (i = 0; i < n; i++, start++) 3475 t4_write_reg(adap, A_TP_PACE_TABLE, (start << 16) | vals[i]); 3476 return 0; 3477} 3478 3479/** 3480 * t4_set_sched_bps - set the bit rate for a HW traffic scheduler 3481 * @adap: the adapter 3482 * @kbps: target rate in Kbps 3483 * @sched: the scheduler index 3484 * 3485 * Configure a Tx HW scheduler for the target rate. 3486 */ 3487int t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps) 3488{ 3489 unsigned int v, tps, cpt, bpt, delta, mindelta = ~0; 3490 unsigned int clk = adap->params.vpd.cclk * 1000; 3491 unsigned int selected_cpt = 0, selected_bpt = 0; 3492 3493 if (kbps > 0) { 3494 kbps *= 125; /* -> bytes */ 3495 for (cpt = 1; cpt <= 255; cpt++) { 3496 tps = clk / cpt; 3497 bpt = (kbps + tps / 2) / tps; 3498 if (bpt > 0 && bpt <= 255) { 3499 v = bpt * tps; 3500 delta = v >= kbps ? v - kbps : kbps - v; 3501 if (delta < mindelta) { 3502 mindelta = delta; 3503 selected_cpt = cpt; 3504 selected_bpt = bpt; 3505 } 3506 } else if (selected_cpt) 3507 break; 3508 } 3509 if (!selected_cpt) 3510 return -EINVAL; 3511 } 3512 t4_write_reg(adap, A_TP_TM_PIO_ADDR, 3513 A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2); 3514 v = t4_read_reg(adap, A_TP_TM_PIO_DATA); 3515 if (sched & 1) 3516 v = (v & 0xffff) | (selected_cpt << 16) | (selected_bpt << 24); 3517 else 3518 v = (v & 0xffff0000) | selected_cpt | (selected_bpt << 8); 3519 t4_write_reg(adap, A_TP_TM_PIO_DATA, v); 3520 return 0; 3521} 3522 3523/** 3524 * t4_set_sched_ipg - set the IPG for a Tx HW packet rate scheduler 3525 * @adap: the adapter 3526 * @sched: the scheduler index 3527 * @ipg: the interpacket delay in tenths of nanoseconds 3528 * 3529 * Set the interpacket delay for a HW packet rate scheduler. 3530 */ 3531int t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg) 3532{ 3533 unsigned int v, addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2; 3534 3535 /* convert ipg to nearest number of core clocks */ 3536 ipg *= core_ticks_per_usec(adap); 3537 ipg = (ipg + 5000) / 10000; 3538 if (ipg > M_TXTIMERSEPQ0) 3539 return -EINVAL; 3540 3541 t4_write_reg(adap, A_TP_TM_PIO_ADDR, addr); 3542 v = t4_read_reg(adap, A_TP_TM_PIO_DATA); 3543 if (sched & 1) 3544 v = (v & V_TXTIMERSEPQ0(M_TXTIMERSEPQ0)) | V_TXTIMERSEPQ1(ipg); 3545 else 3546 v = (v & V_TXTIMERSEPQ1(M_TXTIMERSEPQ1)) | V_TXTIMERSEPQ0(ipg); 3547 t4_write_reg(adap, A_TP_TM_PIO_DATA, v); 3548 t4_read_reg(adap, A_TP_TM_PIO_DATA); 3549 return 0; 3550} 3551 3552/** 3553 * t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler 3554 * @adap: the adapter 3555 * @sched: the scheduler index 3556 * @kbps: the byte rate in Kbps 3557 * @ipg: the interpacket delay in tenths of nanoseconds 3558 * 3559 * Return the current configuration of a HW Tx scheduler. 3560 */ 3561void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps, 3562 unsigned int *ipg) 3563{ 3564 unsigned int v, addr, bpt, cpt; 3565 3566 if (kbps) { 3567 addr = A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2; 3568 t4_write_reg(adap, A_TP_TM_PIO_ADDR, addr); 3569 v = t4_read_reg(adap, A_TP_TM_PIO_DATA); 3570 if (sched & 1) 3571 v >>= 16; 3572 bpt = (v >> 8) & 0xff; 3573 cpt = v & 0xff; 3574 if (!cpt) 3575 *kbps = 0; /* scheduler disabled */ 3576 else { 3577 v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */ 3578 *kbps = (v * bpt) / 125; 3579 } 3580 } 3581 if (ipg) { 3582 addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2; 3583 t4_write_reg(adap, A_TP_TM_PIO_ADDR, addr); 3584 v = t4_read_reg(adap, A_TP_TM_PIO_DATA); 3585 if (sched & 1) 3586 v >>= 16; 3587 v &= 0xffff; 3588 *ipg = (10000 * v) / core_ticks_per_usec(adap); 3589 } 3590} 3591 3592/* 3593 * Calculates a rate in bytes/s given the number of 256-byte units per 4K core 3594 * clocks. The formula is 3595 * 3596 * bytes/s = bytes256 * 256 * ClkFreq / 4096 3597 * 3598 * which is equivalent to 3599 * 3600 * bytes/s = 62.5 * bytes256 * ClkFreq_ms 3601 */ 3602static u64 chan_rate(struct adapter *adap, unsigned int bytes256) 3603{ 3604 u64 v = bytes256 * adap->params.vpd.cclk; 3605 3606 return v * 62 + v / 2; 3607} 3608 3609/** 3610 * t4_get_chan_txrate - get the current per channel Tx rates 3611 * @adap: the adapter 3612 * @nic_rate: rates for NIC traffic 3613 * @ofld_rate: rates for offloaded traffic 3614 * 3615 * Return the current Tx rates in bytes/s for NIC and offloaded traffic 3616 * for each channel. 3617 */ 3618void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate) 3619{ 3620 u32 v; 3621 3622 v = t4_read_reg(adap, A_TP_TX_TRATE); 3623 nic_rate[0] = chan_rate(adap, G_TNLRATE0(v)); 3624 nic_rate[1] = chan_rate(adap, G_TNLRATE1(v)); 3625 nic_rate[2] = chan_rate(adap, G_TNLRATE2(v)); 3626 nic_rate[3] = chan_rate(adap, G_TNLRATE3(v)); 3627 3628 v = t4_read_reg(adap, A_TP_TX_ORATE); 3629 ofld_rate[0] = chan_rate(adap, G_OFDRATE0(v)); 3630 ofld_rate[1] = chan_rate(adap, G_OFDRATE1(v)); 3631 ofld_rate[2] = chan_rate(adap, G_OFDRATE2(v)); 3632 ofld_rate[3] = chan_rate(adap, G_OFDRATE3(v)); 3633} 3634 3635/** 3636 * t4_set_trace_filter - configure one of the tracing filters 3637 * @adap: the adapter 3638 * @tp: the desired trace filter parameters 3639 * @idx: which filter to configure 3640 * @enable: whether to enable or disable the filter 3641 * 3642 * Configures one of the tracing filters available in HW. If @tp is %NULL 3643 * it indicates that the filter is already written in the register and it 3644 * just needs to be enabled or disabled. 3645 */ 3646int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp, 3647 int idx, int enable) 3648{ 3649 int i, ofst = idx * 4; 3650 u32 data_reg, mask_reg, cfg; 3651 u32 multitrc = F_TRCMULTIFILTER; 3652 u32 en = is_t4(adap) ? F_TFEN : F_T5_TFEN; 3653 3654 if (idx < 0 || idx >= NTRACE) 3655 return -EINVAL; 3656 3657 if (tp == NULL || !enable) { 3658 t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en, 3659 enable ? en : 0); 3660 return 0; 3661 } 3662 3663 /* 3664 * TODO - After T4 data book is updated, specify the exact 3665 * section below. 3666 * 3667 * See T4 data book - MPS section for a complete description 3668 * of the below if..else handling of A_MPS_TRC_CFG register 3669 * value. 3670 */ 3671 cfg = t4_read_reg(adap, A_MPS_TRC_CFG); 3672 if (cfg & F_TRCMULTIFILTER) { 3673 /* 3674 * If multiple tracers are enabled, then maximum 3675 * capture size is 2.5KB (FIFO size of a single channel) 3676 * minus 2 flits for CPL_TRACE_PKT header. 3677 */ 3678 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8))) 3679 return -EINVAL; 3680 } else { 3681 /* 3682 * If multiple tracers are disabled, to avoid deadlocks 3683 * maximum packet capture size of 9600 bytes is recommended. 3684 * Also in this mode, only trace0 can be enabled and running. 3685 */ 3686 multitrc = 0; 3687 if (tp->snap_len > 9600 || idx) 3688 return -EINVAL; 3689 } 3690 3691 if (tp->port > (is_t4(adap) ? 11 : 19) || tp->invert > 1 || 3692 tp->skip_len > M_TFLENGTH || tp->skip_ofst > M_TFOFFSET || 3693 tp->min_len > M_TFMINPKTSIZE) 3694 return -EINVAL; 3695 3696 /* stop the tracer we'll be changing */ 3697 t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en, 0); 3698 3699 idx *= (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH); 3700 data_reg = A_MPS_TRC_FILTER0_MATCH + idx; 3701 mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + idx; 3702 3703 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) { 3704 t4_write_reg(adap, data_reg, tp->data[i]); 3705 t4_write_reg(adap, mask_reg, ~tp->mask[i]); 3706 } 3707 t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst, 3708 V_TFCAPTUREMAX(tp->snap_len) | 3709 V_TFMINPKTSIZE(tp->min_len)); 3710 t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, 3711 V_TFOFFSET(tp->skip_ofst) | V_TFLENGTH(tp->skip_len) | en | 3712 (is_t4(adap) ? 3713 V_TFPORT(tp->port) | V_TFINVERTMATCH(tp->invert) : 3714 V_T5_TFPORT(tp->port) | V_T5_TFINVERTMATCH(tp->invert))); 3715 3716 return 0; 3717} 3718 3719/** 3720 * t4_get_trace_filter - query one of the tracing filters 3721 * @adap: the adapter 3722 * @tp: the current trace filter parameters 3723 * @idx: which trace filter to query 3724 * @enabled: non-zero if the filter is enabled 3725 * 3726 * Returns the current settings of one of the HW tracing filters. 3727 */ 3728void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx, 3729 int *enabled) 3730{ 3731 u32 ctla, ctlb; 3732 int i, ofst = idx * 4; 3733 u32 data_reg, mask_reg; 3734 3735 ctla = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst); 3736 ctlb = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst); 3737 3738 if (is_t4(adap)) { 3739 *enabled = !!(ctla & F_TFEN); 3740 tp->port = G_TFPORT(ctla); 3741 tp->invert = !!(ctla & F_TFINVERTMATCH); 3742 } else { 3743 *enabled = !!(ctla & F_T5_TFEN); 3744 tp->port = G_T5_TFPORT(ctla); 3745 tp->invert = !!(ctla & F_T5_TFINVERTMATCH); 3746 } 3747 tp->snap_len = G_TFCAPTUREMAX(ctlb); 3748 tp->min_len = G_TFMINPKTSIZE(ctlb); 3749 tp->skip_ofst = G_TFOFFSET(ctla); 3750 tp->skip_len = G_TFLENGTH(ctla); 3751 3752 ofst = (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH) * idx; 3753 data_reg = A_MPS_TRC_FILTER0_MATCH + ofst; 3754 mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + ofst; 3755 3756 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) { 3757 tp->mask[i] = ~t4_read_reg(adap, mask_reg); 3758 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i]; 3759 } 3760} 3761 3762/** 3763 * t4_pmtx_get_stats - returns the HW stats from PMTX 3764 * @adap: the adapter 3765 * @cnt: where to store the count statistics 3766 * @cycles: where to store the cycle statistics 3767 * 3768 * Returns performance statistics from PMTX. 3769 */ 3770void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) 3771{ 3772 int i; 3773 u32 data[2]; 3774 3775 for (i = 0; i < PM_NSTATS; i++) { 3776 t4_write_reg(adap, A_PM_TX_STAT_CONFIG, i + 1); 3777 cnt[i] = t4_read_reg(adap, A_PM_TX_STAT_COUNT); 3778 if (is_t4(adap)) 3779 cycles[i] = t4_read_reg64(adap, A_PM_TX_STAT_LSB); 3780 else { 3781 t4_read_indirect(adap, A_PM_TX_DBG_CTRL, 3782 A_PM_TX_DBG_DATA, data, 2, 3783 A_PM_TX_DBG_STAT_MSB); 3784 cycles[i] = (((u64)data[0] << 32) | data[1]); 3785 } 3786 } 3787} 3788 3789/** 3790 * t4_pmrx_get_stats - returns the HW stats from PMRX 3791 * @adap: the adapter 3792 * @cnt: where to store the count statistics 3793 * @cycles: where to store the cycle statistics 3794 * 3795 * Returns performance statistics from PMRX. 3796 */ 3797void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) 3798{ 3799 int i; 3800 u32 data[2]; 3801 3802 for (i = 0; i < PM_NSTATS; i++) { 3803 t4_write_reg(adap, A_PM_RX_STAT_CONFIG, i + 1); 3804 cnt[i] = t4_read_reg(adap, A_PM_RX_STAT_COUNT); 3805 if (is_t4(adap)) 3806 cycles[i] = t4_read_reg64(adap, A_PM_RX_STAT_LSB); 3807 else { 3808 t4_read_indirect(adap, A_PM_RX_DBG_CTRL, 3809 A_PM_RX_DBG_DATA, data, 2, 3810 A_PM_RX_DBG_STAT_MSB); 3811 cycles[i] = (((u64)data[0] << 32) | data[1]); 3812 } 3813 } 3814} 3815 3816/** 3817 * get_mps_bg_map - return the buffer groups associated with a port 3818 * @adap: the adapter 3819 * @idx: the port index 3820 * 3821 * Returns a bitmap indicating which MPS buffer groups are associated 3822 * with the given port. Bit i is set if buffer group i is used by the 3823 * port. 3824 */ 3825static unsigned int get_mps_bg_map(struct adapter *adap, int idx) 3826{ 3827 u32 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL)); 3828 3829 if (n == 0) 3830 return idx == 0 ? 0xf : 0; 3831 if (n == 1) 3832 return idx < 2 ? (3 << (2 * idx)) : 0; 3833 return 1 << idx; 3834} 3835 3836/** 3837 * t4_get_port_stats_offset - collect port stats relative to a previous 3838 * snapshot 3839 * @adap: The adapter 3840 * @idx: The port 3841 * @stats: Current stats to fill 3842 * @offset: Previous stats snapshot 3843 */ 3844void t4_get_port_stats_offset(struct adapter *adap, int idx, 3845 struct port_stats *stats, 3846 struct port_stats *offset) 3847{ 3848 u64 *s, *o; 3849 int i; 3850 3851 t4_get_port_stats(adap, idx, stats); 3852 for (i = 0, s = (u64 *)stats, o = (u64 *)offset ; 3853 i < (sizeof(struct port_stats)/sizeof(u64)) ; 3854 i++, s++, o++) 3855 *s -= *o; 3856} 3857 3858/** 3859 * t4_get_port_stats - collect port statistics 3860 * @adap: the adapter 3861 * @idx: the port index 3862 * @p: the stats structure to fill 3863 * 3864 * Collect statistics related to the given port from HW. 3865 */ 3866void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p) 3867{ 3868 u32 bgmap = get_mps_bg_map(adap, idx); 3869 3870#define GET_STAT(name) \ 3871 t4_read_reg64(adap, \ 3872 (is_t4(adap) ? PORT_REG(idx, A_MPS_PORT_STAT_##name##_L) : \ 3873 T5_PORT_REG(idx, A_MPS_PORT_STAT_##name##_L))) 3874#define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L) 3875 3876 p->tx_pause = GET_STAT(TX_PORT_PAUSE); 3877 p->tx_octets = GET_STAT(TX_PORT_BYTES); 3878 p->tx_frames = GET_STAT(TX_PORT_FRAMES); 3879 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST); 3880 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST); 3881 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST); 3882 p->tx_error_frames = GET_STAT(TX_PORT_ERROR); 3883 p->tx_frames_64 = GET_STAT(TX_PORT_64B); 3884 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B); 3885 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B); 3886 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B); 3887 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B); 3888 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B); 3889 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX); 3890 p->tx_drop = GET_STAT(TX_PORT_DROP); 3891 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0); 3892 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1); 3893 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2); 3894 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3); 3895 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4); 3896 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5); 3897 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6); 3898 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7); 3899 3900 p->rx_pause = GET_STAT(RX_PORT_PAUSE); 3901 p->rx_octets = GET_STAT(RX_PORT_BYTES); 3902 p->rx_frames = GET_STAT(RX_PORT_FRAMES); 3903 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST); 3904 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST); 3905 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST); 3906 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR); 3907 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR); 3908 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR); 3909 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR); 3910 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR); 3911 p->rx_runt = GET_STAT(RX_PORT_LESS_64B); 3912 p->rx_frames_64 = GET_STAT(RX_PORT_64B); 3913 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B); 3914 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B); 3915 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B); 3916 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B); 3917 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B); 3918 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX); 3919 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0); 3920 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1); 3921 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2); 3922 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3); 3923 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4); 3924 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5); 3925 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6); 3926 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7); 3927 3928 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0; 3929 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0; 3930 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0; 3931 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0; 3932 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0; 3933 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0; 3934 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0; 3935 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0; 3936 3937#undef GET_STAT 3938#undef GET_STAT_COM 3939} 3940 3941/** 3942 * t4_clr_port_stats - clear port statistics 3943 * @adap: the adapter 3944 * @idx: the port index 3945 * 3946 * Clear HW statistics for the given port. 3947 */ 3948void t4_clr_port_stats(struct adapter *adap, int idx) 3949{ 3950 unsigned int i; 3951 u32 bgmap = get_mps_bg_map(adap, idx); 3952 u32 port_base_addr; 3953 3954 if (is_t4(adap)) 3955 port_base_addr = PORT_BASE(idx); 3956 else 3957 port_base_addr = T5_PORT_BASE(idx); 3958 3959 for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L; 3960 i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8) 3961 t4_write_reg(adap, port_base_addr + i, 0); 3962 for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L; 3963 i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8) 3964 t4_write_reg(adap, port_base_addr + i, 0); 3965 for (i = 0; i < 4; i++) 3966 if (bgmap & (1 << i)) { 3967 t4_write_reg(adap, 3968 A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L + i * 8, 0); 3969 t4_write_reg(adap, 3970 A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L + i * 8, 0); 3971 } 3972} 3973 3974/** 3975 * t4_get_lb_stats - collect loopback port statistics 3976 * @adap: the adapter 3977 * @idx: the loopback port index 3978 * @p: the stats structure to fill 3979 * 3980 * Return HW statistics for the given loopback port. 3981 */ 3982void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p) 3983{ 3984 u32 bgmap = get_mps_bg_map(adap, idx); 3985 3986#define GET_STAT(name) \ 3987 t4_read_reg64(adap, \ 3988 (is_t4(adap) ? \ 3989 PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L) : \ 3990 T5_PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L))) 3991#define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L) 3992 3993 p->octets = GET_STAT(BYTES); 3994 p->frames = GET_STAT(FRAMES); 3995 p->bcast_frames = GET_STAT(BCAST); 3996 p->mcast_frames = GET_STAT(MCAST); 3997 p->ucast_frames = GET_STAT(UCAST); 3998 p->error_frames = GET_STAT(ERROR); 3999 4000 p->frames_64 = GET_STAT(64B); 4001 p->frames_65_127 = GET_STAT(65B_127B); 4002 p->frames_128_255 = GET_STAT(128B_255B); 4003 p->frames_256_511 = GET_STAT(256B_511B); 4004 p->frames_512_1023 = GET_STAT(512B_1023B); 4005 p->frames_1024_1518 = GET_STAT(1024B_1518B); 4006 p->frames_1519_max = GET_STAT(1519B_MAX); 4007 p->drop = GET_STAT(DROP_FRAMES); 4008 4009 p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0; 4010 p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0; 4011 p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0; 4012 p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0; 4013 p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0; 4014 p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0; 4015 p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0; 4016 p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0; 4017 4018#undef GET_STAT 4019#undef GET_STAT_COM 4020} 4021 4022/** 4023 * t4_wol_magic_enable - enable/disable magic packet WoL 4024 * @adap: the adapter 4025 * @port: the physical port index 4026 * @addr: MAC address expected in magic packets, %NULL to disable 4027 * 4028 * Enables/disables magic packet wake-on-LAN for the selected port. 4029 */ 4030void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 4031 const u8 *addr) 4032{ 4033 u32 mag_id_reg_l, mag_id_reg_h, port_cfg_reg; 4034 4035 if (is_t4(adap)) { 4036 mag_id_reg_l = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_LO); 4037 mag_id_reg_h = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_HI); 4038 port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2); 4039 } else { 4040 mag_id_reg_l = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_LO); 4041 mag_id_reg_h = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_HI); 4042 port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2); 4043 } 4044 4045 if (addr) { 4046 t4_write_reg(adap, mag_id_reg_l, 4047 (addr[2] << 24) | (addr[3] << 16) | 4048 (addr[4] << 8) | addr[5]); 4049 t4_write_reg(adap, mag_id_reg_h, 4050 (addr[0] << 8) | addr[1]); 4051 } 4052 t4_set_reg_field(adap, port_cfg_reg, F_MAGICEN, 4053 V_MAGICEN(addr != NULL)); 4054} 4055 4056/** 4057 * t4_wol_pat_enable - enable/disable pattern-based WoL 4058 * @adap: the adapter 4059 * @port: the physical port index 4060 * @map: bitmap of which HW pattern filters to set 4061 * @mask0: byte mask for bytes 0-63 of a packet 4062 * @mask1: byte mask for bytes 64-127 of a packet 4063 * @crc: Ethernet CRC for selected bytes 4064 * @enable: enable/disable switch 4065 * 4066 * Sets the pattern filters indicated in @map to mask out the bytes 4067 * specified in @mask0/@mask1 in received packets and compare the CRC of 4068 * the resulting packet against @crc. If @enable is %true pattern-based 4069 * WoL is enabled, otherwise disabled. 4070 */ 4071int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 4072 u64 mask0, u64 mask1, unsigned int crc, bool enable) 4073{ 4074 int i; 4075 u32 port_cfg_reg; 4076 4077 if (is_t4(adap)) 4078 port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2); 4079 else 4080 port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2); 4081 4082 if (!enable) { 4083 t4_set_reg_field(adap, port_cfg_reg, F_PATEN, 0); 4084 return 0; 4085 } 4086 if (map > 0xff) 4087 return -EINVAL; 4088 4089#define EPIO_REG(name) \ 4090 (is_t4(adap) ? PORT_REG(port, A_XGMAC_PORT_EPIO_##name) : \ 4091 T5_PORT_REG(port, A_MAC_PORT_EPIO_##name)) 4092 4093 t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32); 4094 t4_write_reg(adap, EPIO_REG(DATA2), mask1); 4095 t4_write_reg(adap, EPIO_REG(DATA3), mask1 >> 32); 4096 4097 for (i = 0; i < NWOL_PAT; i++, map >>= 1) { 4098 if (!(map & 1)) 4099 continue; 4100 4101 /* write byte masks */ 4102 t4_write_reg(adap, EPIO_REG(DATA0), mask0); 4103 t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i) | F_EPIOWR); 4104 t4_read_reg(adap, EPIO_REG(OP)); /* flush */ 4105 if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY) 4106 return -ETIMEDOUT; 4107 4108 /* write CRC */ 4109 t4_write_reg(adap, EPIO_REG(DATA0), crc); 4110 t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i + 32) | F_EPIOWR); 4111 t4_read_reg(adap, EPIO_REG(OP)); /* flush */ 4112 if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY) 4113 return -ETIMEDOUT; 4114 } 4115#undef EPIO_REG 4116 4117 t4_set_reg_field(adap, port_cfg_reg, 0, F_PATEN); 4118 return 0; 4119} 4120 4121/** 4122 * t4_mk_filtdelwr - create a delete filter WR 4123 * @ftid: the filter ID 4124 * @wr: the filter work request to populate 4125 * @qid: ingress queue to receive the delete notification 4126 * 4127 * Creates a filter work request to delete the supplied filter. If @qid is 4128 * negative the delete notification is suppressed. 4129 */ 4130void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid) 4131{ 4132 memset(wr, 0, sizeof(*wr)); 4133 wr->op_pkd = htonl(V_FW_WR_OP(FW_FILTER_WR)); 4134 wr->len16_pkd = htonl(V_FW_WR_LEN16(sizeof(*wr) / 16)); 4135 wr->tid_to_iq = htonl(V_FW_FILTER_WR_TID(ftid) | 4136 V_FW_FILTER_WR_NOREPLY(qid < 0)); 4137 wr->del_filter_to_l2tix = htonl(F_FW_FILTER_WR_DEL_FILTER); 4138 if (qid >= 0) 4139 wr->rx_chan_rx_rpl_iq = htons(V_FW_FILTER_WR_RX_RPL_IQ(qid)); 4140} 4141 4142#define INIT_CMD(var, cmd, rd_wr) do { \ 4143 (var).op_to_write = htonl(V_FW_CMD_OP(FW_##cmd##_CMD) | \ 4144 F_FW_CMD_REQUEST | F_FW_CMD_##rd_wr); \ 4145 (var).retval_len16 = htonl(FW_LEN16(var)); \ 4146} while (0) 4147 4148int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, u32 addr, u32 val) 4149{ 4150 struct fw_ldst_cmd c; 4151 4152 memset(&c, 0, sizeof(c)); 4153 c.op_to_addrspace = htonl(V_FW_CMD_OP(FW_LDST_CMD) | F_FW_CMD_REQUEST | 4154 F_FW_CMD_WRITE | V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FIRMWARE)); 4155 c.cycles_to_len16 = htonl(FW_LEN16(c)); 4156 c.u.addrval.addr = htonl(addr); 4157 c.u.addrval.val = htonl(val); 4158 4159 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 4160} 4161 4162/** 4163 * t4_mdio_rd - read a PHY register through MDIO 4164 * @adap: the adapter 4165 * @mbox: mailbox to use for the FW command 4166 * @phy_addr: the PHY address 4167 * @mmd: the PHY MMD to access (0 for clause 22 PHYs) 4168 * @reg: the register to read 4169 * @valp: where to store the value 4170 * 4171 * Issues a FW command through the given mailbox to read a PHY register. 4172 */ 4173int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 4174 unsigned int mmd, unsigned int reg, unsigned int *valp) 4175{ 4176 int ret; 4177 struct fw_ldst_cmd c; 4178 4179 memset(&c, 0, sizeof(c)); 4180 c.op_to_addrspace = htonl(V_FW_CMD_OP(FW_LDST_CMD) | F_FW_CMD_REQUEST | 4181 F_FW_CMD_READ | V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO)); 4182 c.cycles_to_len16 = htonl(FW_LEN16(c)); 4183 c.u.mdio.paddr_mmd = htons(V_FW_LDST_CMD_PADDR(phy_addr) | 4184 V_FW_LDST_CMD_MMD(mmd)); 4185 c.u.mdio.raddr = htons(reg); 4186 4187 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 4188 if (ret == 0) 4189 *valp = ntohs(c.u.mdio.rval); 4190 return ret; 4191} 4192 4193/** 4194 * t4_mdio_wr - write a PHY register through MDIO 4195 * @adap: the adapter 4196 * @mbox: mailbox to use for the FW command 4197 * @phy_addr: the PHY address 4198 * @mmd: the PHY MMD to access (0 for clause 22 PHYs) 4199 * @reg: the register to write 4200 * @valp: value to write 4201 * 4202 * Issues a FW command through the given mailbox to write a PHY register. 4203 */ 4204int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 4205 unsigned int mmd, unsigned int reg, unsigned int val) 4206{ 4207 struct fw_ldst_cmd c; 4208 4209 memset(&c, 0, sizeof(c)); 4210 c.op_to_addrspace = htonl(V_FW_CMD_OP(FW_LDST_CMD) | F_FW_CMD_REQUEST | 4211 F_FW_CMD_WRITE | V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO)); 4212 c.cycles_to_len16 = htonl(FW_LEN16(c)); 4213 c.u.mdio.paddr_mmd = htons(V_FW_LDST_CMD_PADDR(phy_addr) | 4214 V_FW_LDST_CMD_MMD(mmd)); 4215 c.u.mdio.raddr = htons(reg); 4216 c.u.mdio.rval = htons(val); 4217 4218 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 4219} 4220 4221/** 4222 * t4_i2c_rd - read I2C data from adapter 4223 * @adap: the adapter 4224 * @port: Port number if per-port device; <0 if not 4225 * @devid: per-port device ID or absolute device ID 4226 * @offset: byte offset into device I2C space 4227 * @len: byte length of I2C space data 4228 * @buf: buffer in which to return I2C data 4229 * 4230 * Reads the I2C data from the indicated device and location. 4231 */ 4232int t4_i2c_rd(struct adapter *adap, unsigned int mbox, 4233 int port, unsigned int devid, 4234 unsigned int offset, unsigned int len, 4235 u8 *buf) 4236{ 4237 struct fw_ldst_cmd ldst; 4238 int ret; 4239 4240 if (port >= 4 || 4241 devid >= 256 || 4242 offset >= 256 || 4243 len > sizeof ldst.u.i2c.data) 4244 return -EINVAL; 4245 4246 memset(&ldst, 0, sizeof ldst); 4247 ldst.op_to_addrspace = 4248 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 4249 F_FW_CMD_REQUEST | 4250 F_FW_CMD_READ | 4251 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_I2C)); 4252 ldst.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst)); 4253 ldst.u.i2c.pid = (port < 0 ? 0xff : port); 4254 ldst.u.i2c.did = devid; 4255 ldst.u.i2c.boffset = offset; 4256 ldst.u.i2c.blen = len; 4257 ret = t4_wr_mbox(adap, mbox, &ldst, sizeof ldst, &ldst); 4258 if (!ret) 4259 memcpy(buf, ldst.u.i2c.data, len); 4260 return ret; 4261} 4262 4263/** 4264 * t4_i2c_wr - write I2C data to adapter 4265 * @adap: the adapter 4266 * @port: Port number if per-port device; <0 if not 4267 * @devid: per-port device ID or absolute device ID 4268 * @offset: byte offset into device I2C space 4269 * @len: byte length of I2C space data 4270 * @buf: buffer containing new I2C data 4271 * 4272 * Write the I2C data to the indicated device and location. 4273 */ 4274int t4_i2c_wr(struct adapter *adap, unsigned int mbox, 4275 int port, unsigned int devid, 4276 unsigned int offset, unsigned int len, 4277 u8 *buf) 4278{ 4279 struct fw_ldst_cmd ldst; 4280 4281 if (port >= 4 || 4282 devid >= 256 || 4283 offset >= 256 || 4284 len > sizeof ldst.u.i2c.data) 4285 return -EINVAL; 4286 4287 memset(&ldst, 0, sizeof ldst); 4288 ldst.op_to_addrspace = 4289 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 4290 F_FW_CMD_REQUEST | 4291 F_FW_CMD_WRITE | 4292 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_I2C)); 4293 ldst.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst)); 4294 ldst.u.i2c.pid = (port < 0 ? 0xff : port); 4295 ldst.u.i2c.did = devid; 4296 ldst.u.i2c.boffset = offset; 4297 ldst.u.i2c.blen = len; 4298 memcpy(ldst.u.i2c.data, buf, len); 4299 return t4_wr_mbox(adap, mbox, &ldst, sizeof ldst, &ldst); 4300} 4301 4302/** 4303 * t4_sge_ctxt_flush - flush the SGE context cache 4304 * @adap: the adapter 4305 * @mbox: mailbox to use for the FW command 4306 * 4307 * Issues a FW command through the given mailbox to flush the 4308 * SGE context cache. 4309 */ 4310int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox) 4311{ 4312 int ret; 4313 struct fw_ldst_cmd c; 4314 4315 memset(&c, 0, sizeof(c)); 4316 c.op_to_addrspace = htonl(V_FW_CMD_OP(FW_LDST_CMD) | F_FW_CMD_REQUEST | 4317 F_FW_CMD_READ | 4318 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_SGE_EGRC)); 4319 c.cycles_to_len16 = htonl(FW_LEN16(c)); 4320 c.u.idctxt.msg_ctxtflush = htonl(F_FW_LDST_CMD_CTXTFLUSH); 4321 4322 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 4323 return ret; 4324} 4325 4326/** 4327 * t4_sge_ctxt_rd - read an SGE context through FW 4328 * @adap: the adapter 4329 * @mbox: mailbox to use for the FW command 4330 * @cid: the context id 4331 * @ctype: the context type 4332 * @data: where to store the context data 4333 * 4334 * Issues a FW command through the given mailbox to read an SGE context. 4335 */ 4336int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 4337 enum ctxt_type ctype, u32 *data) 4338{ 4339 int ret; 4340 struct fw_ldst_cmd c; 4341 4342 if (ctype == CTXT_EGRESS) 4343 ret = FW_LDST_ADDRSPC_SGE_EGRC; 4344 else if (ctype == CTXT_INGRESS) 4345 ret = FW_LDST_ADDRSPC_SGE_INGC; 4346 else if (ctype == CTXT_FLM) 4347 ret = FW_LDST_ADDRSPC_SGE_FLMC; 4348 else 4349 ret = FW_LDST_ADDRSPC_SGE_CONMC; 4350 4351 memset(&c, 0, sizeof(c)); 4352 c.op_to_addrspace = htonl(V_FW_CMD_OP(FW_LDST_CMD) | F_FW_CMD_REQUEST | 4353 F_FW_CMD_READ | V_FW_LDST_CMD_ADDRSPACE(ret)); 4354 c.cycles_to_len16 = htonl(FW_LEN16(c)); 4355 c.u.idctxt.physid = htonl(cid); 4356 4357 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 4358 if (ret == 0) { 4359 data[0] = ntohl(c.u.idctxt.ctxt_data0); 4360 data[1] = ntohl(c.u.idctxt.ctxt_data1); 4361 data[2] = ntohl(c.u.idctxt.ctxt_data2); 4362 data[3] = ntohl(c.u.idctxt.ctxt_data3); 4363 data[4] = ntohl(c.u.idctxt.ctxt_data4); 4364 data[5] = ntohl(c.u.idctxt.ctxt_data5); 4365 } 4366 return ret; 4367} 4368 4369/** 4370 * t4_sge_ctxt_rd_bd - read an SGE context bypassing FW 4371 * @adap: the adapter 4372 * @cid: the context id 4373 * @ctype: the context type 4374 * @data: where to store the context data 4375 * 4376 * Reads an SGE context directly, bypassing FW. This is only for 4377 * debugging when FW is unavailable. 4378 */ 4379int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype, 4380 u32 *data) 4381{ 4382 int i, ret; 4383 4384 t4_write_reg(adap, A_SGE_CTXT_CMD, V_CTXTQID(cid) | V_CTXTTYPE(ctype)); 4385 ret = t4_wait_op_done(adap, A_SGE_CTXT_CMD, F_BUSY, 0, 3, 1); 4386 if (!ret) 4387 for (i = A_SGE_CTXT_DATA0; i <= A_SGE_CTXT_DATA5; i += 4) 4388 *data++ = t4_read_reg(adap, i); 4389 return ret; 4390} 4391 4392/** 4393 * t4_fw_hello - establish communication with FW 4394 * @adap: the adapter 4395 * @mbox: mailbox to use for the FW command 4396 * @evt_mbox: mailbox to receive async FW events 4397 * @master: specifies the caller's willingness to be the device master 4398 * @state: returns the current device state (if non-NULL) 4399 * 4400 * Issues a command to establish communication with FW. Returns either 4401 * an error (negative integer) or the mailbox of the Master PF. 4402 */ 4403int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 4404 enum dev_master master, enum dev_state *state) 4405{ 4406 int ret; 4407 struct fw_hello_cmd c; 4408 u32 v; 4409 unsigned int master_mbox; 4410 int retries = FW_CMD_HELLO_RETRIES; 4411 4412retry: 4413 memset(&c, 0, sizeof(c)); 4414 INIT_CMD(c, HELLO, WRITE); 4415 c.err_to_clearinit = htonl( 4416 V_FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) | 4417 V_FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) | 4418 V_FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ? mbox : 4419 M_FW_HELLO_CMD_MBMASTER) | 4420 V_FW_HELLO_CMD_MBASYNCNOT(evt_mbox) | 4421 V_FW_HELLO_CMD_STAGE(FW_HELLO_CMD_STAGE_OS) | 4422 F_FW_HELLO_CMD_CLEARINIT); 4423 4424 /* 4425 * Issue the HELLO command to the firmware. If it's not successful 4426 * but indicates that we got a "busy" or "timeout" condition, retry 4427 * the HELLO until we exhaust our retry limit. If we do exceed our 4428 * retry limit, check to see if the firmware left us any error 4429 * information and report that if so ... 4430 */ 4431 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 4432 if (ret != FW_SUCCESS) { 4433 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0) 4434 goto retry; 4435 if (t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_ERR) 4436 t4_report_fw_error(adap); 4437 return ret; 4438 } 4439 4440 v = ntohl(c.err_to_clearinit); 4441 master_mbox = G_FW_HELLO_CMD_MBMASTER(v); 4442 if (state) { 4443 if (v & F_FW_HELLO_CMD_ERR) 4444 *state = DEV_STATE_ERR; 4445 else if (v & F_FW_HELLO_CMD_INIT) 4446 *state = DEV_STATE_INIT; 4447 else 4448 *state = DEV_STATE_UNINIT; 4449 } 4450 4451 /* 4452 * If we're not the Master PF then we need to wait around for the 4453 * Master PF Driver to finish setting up the adapter. 4454 * 4455 * Note that we also do this wait if we're a non-Master-capable PF and 4456 * there is no current Master PF; a Master PF may show up momentarily 4457 * and we wouldn't want to fail pointlessly. (This can happen when an 4458 * OS loads lots of different drivers rapidly at the same time). In 4459 * this case, the Master PF returned by the firmware will be 4460 * M_PCIE_FW_MASTER so the test below will work ... 4461 */ 4462 if ((v & (F_FW_HELLO_CMD_ERR|F_FW_HELLO_CMD_INIT)) == 0 && 4463 master_mbox != mbox) { 4464 int waiting = FW_CMD_HELLO_TIMEOUT; 4465 4466 /* 4467 * Wait for the firmware to either indicate an error or 4468 * initialized state. If we see either of these we bail out 4469 * and report the issue to the caller. If we exhaust the 4470 * "hello timeout" and we haven't exhausted our retries, try 4471 * again. Otherwise bail with a timeout error. 4472 */ 4473 for (;;) { 4474 u32 pcie_fw; 4475 4476 msleep(50); 4477 waiting -= 50; 4478 4479 /* 4480 * If neither Error nor Initialialized are indicated 4481 * by the firmware keep waiting till we exhaust our 4482 * timeout ... and then retry if we haven't exhausted 4483 * our retries ... 4484 */ 4485 pcie_fw = t4_read_reg(adap, A_PCIE_FW); 4486 if (!(pcie_fw & (F_PCIE_FW_ERR|F_PCIE_FW_INIT))) { 4487 if (waiting <= 0) { 4488 if (retries-- > 0) 4489 goto retry; 4490 4491 return -ETIMEDOUT; 4492 } 4493 continue; 4494 } 4495 4496 /* 4497 * We either have an Error or Initialized condition 4498 * report errors preferentially. 4499 */ 4500 if (state) { 4501 if (pcie_fw & F_PCIE_FW_ERR) 4502 *state = DEV_STATE_ERR; 4503 else if (pcie_fw & F_PCIE_FW_INIT) 4504 *state = DEV_STATE_INIT; 4505 } 4506 4507 /* 4508 * If we arrived before a Master PF was selected and 4509 * there's not a valid Master PF, grab its identity 4510 * for our caller. 4511 */ 4512 if (master_mbox == M_PCIE_FW_MASTER && 4513 (pcie_fw & F_PCIE_FW_MASTER_VLD)) 4514 master_mbox = G_PCIE_FW_MASTER(pcie_fw); 4515 break; 4516 } 4517 } 4518 4519 return master_mbox; 4520} 4521 4522/** 4523 * t4_fw_bye - end communication with FW 4524 * @adap: the adapter 4525 * @mbox: mailbox to use for the FW command 4526 * 4527 * Issues a command to terminate communication with FW. 4528 */ 4529int t4_fw_bye(struct adapter *adap, unsigned int mbox) 4530{ 4531 struct fw_bye_cmd c; 4532 4533 memset(&c, 0, sizeof(c)); 4534 INIT_CMD(c, BYE, WRITE); 4535 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 4536} 4537 4538/** 4539 * t4_fw_reset - issue a reset to FW 4540 * @adap: the adapter 4541 * @mbox: mailbox to use for the FW command 4542 * @reset: specifies the type of reset to perform 4543 * 4544 * Issues a reset command of the specified type to FW. 4545 */ 4546int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset) 4547{ 4548 struct fw_reset_cmd c; 4549 4550 memset(&c, 0, sizeof(c)); 4551 INIT_CMD(c, RESET, WRITE); 4552 c.val = htonl(reset); 4553 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 4554} 4555 4556/** 4557 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET 4558 * @adap: the adapter 4559 * @mbox: mailbox to use for the FW RESET command (if desired) 4560 * @force: force uP into RESET even if FW RESET command fails 4561 * 4562 * Issues a RESET command to firmware (if desired) with a HALT indication 4563 * and then puts the microprocessor into RESET state. The RESET command 4564 * will only be issued if a legitimate mailbox is provided (mbox <= 4565 * M_PCIE_FW_MASTER). 4566 * 4567 * This is generally used in order for the host to safely manipulate the 4568 * adapter without fear of conflicting with whatever the firmware might 4569 * be doing. The only way out of this state is to RESTART the firmware 4570 * ... 4571 */ 4572int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force) 4573{ 4574 int ret = 0; 4575 4576 /* 4577 * If a legitimate mailbox is provided, issue a RESET command 4578 * with a HALT indication. 4579 */ 4580 if (mbox <= M_PCIE_FW_MASTER) { 4581 struct fw_reset_cmd c; 4582 4583 memset(&c, 0, sizeof(c)); 4584 INIT_CMD(c, RESET, WRITE); 4585 c.val = htonl(F_PIORST | F_PIORSTMODE); 4586 c.halt_pkd = htonl(F_FW_RESET_CMD_HALT); 4587 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 4588 } 4589 4590 /* 4591 * Normally we won't complete the operation if the firmware RESET 4592 * command fails but if our caller insists we'll go ahead and put the 4593 * uP into RESET. This can be useful if the firmware is hung or even 4594 * missing ... We'll have to take the risk of putting the uP into 4595 * RESET without the cooperation of firmware in that case. 4596 * 4597 * We also force the firmware's HALT flag to be on in case we bypassed 4598 * the firmware RESET command above or we're dealing with old firmware 4599 * which doesn't have the HALT capability. This will serve as a flag 4600 * for the incoming firmware to know that it's coming out of a HALT 4601 * rather than a RESET ... if it's new enough to understand that ... 4602 */ 4603 if (ret == 0 || force) { 4604 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST); 4605 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT, F_PCIE_FW_HALT); 4606 } 4607 4608 /* 4609 * And we always return the result of the firmware RESET command 4610 * even when we force the uP into RESET ... 4611 */ 4612 return ret; 4613} 4614 4615/** 4616 * t4_fw_restart - restart the firmware by taking the uP out of RESET 4617 * @adap: the adapter 4618 * @reset: if we want to do a RESET to restart things 4619 * 4620 * Restart firmware previously halted by t4_fw_halt(). On successful 4621 * return the previous PF Master remains as the new PF Master and there 4622 * is no need to issue a new HELLO command, etc. 4623 * 4624 * We do this in two ways: 4625 * 4626 * 1. If we're dealing with newer firmware we'll simply want to take 4627 * the chip's microprocessor out of RESET. This will cause the 4628 * firmware to start up from its start vector. And then we'll loop 4629 * until the firmware indicates it's started again (PCIE_FW.HALT 4630 * reset to 0) or we timeout. 4631 * 4632 * 2. If we're dealing with older firmware then we'll need to RESET 4633 * the chip since older firmware won't recognize the PCIE_FW.HALT 4634 * flag and automatically RESET itself on startup. 4635 */ 4636int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset) 4637{ 4638 if (reset) { 4639 /* 4640 * Since we're directing the RESET instead of the firmware 4641 * doing it automatically, we need to clear the PCIE_FW.HALT 4642 * bit. 4643 */ 4644 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT, 0); 4645 4646 /* 4647 * If we've been given a valid mailbox, first try to get the 4648 * firmware to do the RESET. If that works, great and we can 4649 * return success. Otherwise, if we haven't been given a 4650 * valid mailbox or the RESET command failed, fall back to 4651 * hitting the chip with a hammer. 4652 */ 4653 if (mbox <= M_PCIE_FW_MASTER) { 4654 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0); 4655 msleep(100); 4656 if (t4_fw_reset(adap, mbox, 4657 F_PIORST | F_PIORSTMODE) == 0) 4658 return 0; 4659 } 4660 4661 t4_write_reg(adap, A_PL_RST, F_PIORST | F_PIORSTMODE); 4662 msleep(2000); 4663 } else { 4664 int ms; 4665 4666 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0); 4667 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) { 4668 if (!(t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_HALT)) 4669 return FW_SUCCESS; 4670 msleep(100); 4671 ms += 100; 4672 } 4673 return -ETIMEDOUT; 4674 } 4675 return 0; 4676} 4677 4678/** 4679 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW 4680 * @adap: the adapter 4681 * @mbox: mailbox to use for the FW RESET command (if desired) 4682 * @fw_data: the firmware image to write 4683 * @size: image size 4684 * @force: force upgrade even if firmware doesn't cooperate 4685 * 4686 * Perform all of the steps necessary for upgrading an adapter's 4687 * firmware image. Normally this requires the cooperation of the 4688 * existing firmware in order to halt all existing activities 4689 * but if an invalid mailbox token is passed in we skip that step 4690 * (though we'll still put the adapter microprocessor into RESET in 4691 * that case). 4692 * 4693 * On successful return the new firmware will have been loaded and 4694 * the adapter will have been fully RESET losing all previous setup 4695 * state. On unsuccessful return the adapter may be completely hosed ... 4696 * positive errno indicates that the adapter is ~probably~ intact, a 4697 * negative errno indicates that things are looking bad ... 4698 */ 4699int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 4700 const u8 *fw_data, unsigned int size, int force) 4701{ 4702 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data; 4703 unsigned int bootstrap = ntohl(fw_hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP; 4704 int reset, ret; 4705 4706 if (!bootstrap) { 4707 ret = t4_fw_halt(adap, mbox, force); 4708 if (ret < 0 && !force) 4709 return ret; 4710 } 4711 4712 ret = t4_load_fw(adap, fw_data, size); 4713 if (ret < 0 || bootstrap) 4714 return ret; 4715 4716 /* 4717 * Older versions of the firmware don't understand the new 4718 * PCIE_FW.HALT flag and so won't know to perform a RESET when they 4719 * restart. So for newly loaded older firmware we'll have to do the 4720 * RESET for it so it starts up on a clean slate. We can tell if 4721 * the newly loaded firmware will handle this right by checking 4722 * its header flags to see if it advertises the capability. 4723 */ 4724 reset = ((ntohl(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0); 4725 return t4_fw_restart(adap, mbox, reset); 4726} 4727 4728/** 4729 * t4_fw_initialize - ask FW to initialize the device 4730 * @adap: the adapter 4731 * @mbox: mailbox to use for the FW command 4732 * 4733 * Issues a command to FW to partially initialize the device. This 4734 * performs initialization that generally doesn't depend on user input. 4735 */ 4736int t4_fw_initialize(struct adapter *adap, unsigned int mbox) 4737{ 4738 struct fw_initialize_cmd c; 4739 4740 memset(&c, 0, sizeof(c)); 4741 INIT_CMD(c, INITIALIZE, WRITE); 4742 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 4743} 4744 4745/** 4746 * t4_query_params - query FW or device parameters 4747 * @adap: the adapter 4748 * @mbox: mailbox to use for the FW command 4749 * @pf: the PF 4750 * @vf: the VF 4751 * @nparams: the number of parameters 4752 * @params: the parameter names 4753 * @val: the parameter values 4754 * 4755 * Reads the value of FW or device parameters. Up to 7 parameters can be 4756 * queried at once. 4757 */ 4758int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 4759 unsigned int vf, unsigned int nparams, const u32 *params, 4760 u32 *val) 4761{ 4762 int i, ret; 4763 struct fw_params_cmd c; 4764 __be32 *p = &c.param[0].mnem; 4765 4766 if (nparams > 7) 4767 return -EINVAL; 4768 4769 memset(&c, 0, sizeof(c)); 4770 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_PARAMS_CMD) | F_FW_CMD_REQUEST | 4771 F_FW_CMD_READ | V_FW_PARAMS_CMD_PFN(pf) | 4772 V_FW_PARAMS_CMD_VFN(vf)); 4773 c.retval_len16 = htonl(FW_LEN16(c)); 4774 4775 for (i = 0; i < nparams; i++, p += 2, params++) 4776 *p = htonl(*params); 4777 4778 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 4779 if (ret == 0) 4780 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2) 4781 *val++ = ntohl(*p); 4782 return ret; 4783} 4784 4785/** 4786 * t4_set_params - sets FW or device parameters 4787 * @adap: the adapter 4788 * @mbox: mailbox to use for the FW command 4789 * @pf: the PF 4790 * @vf: the VF 4791 * @nparams: the number of parameters 4792 * @params: the parameter names 4793 * @val: the parameter values 4794 * 4795 * Sets the value of FW or device parameters. Up to 7 parameters can be 4796 * specified at once. 4797 */ 4798int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 4799 unsigned int vf, unsigned int nparams, const u32 *params, 4800 const u32 *val) 4801{ 4802 struct fw_params_cmd c; 4803 __be32 *p = &c.param[0].mnem; 4804 4805 if (nparams > 7) 4806 return -EINVAL; 4807 4808 memset(&c, 0, sizeof(c)); 4809 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_PARAMS_CMD) | F_FW_CMD_REQUEST | 4810 F_FW_CMD_WRITE | V_FW_PARAMS_CMD_PFN(pf) | 4811 V_FW_PARAMS_CMD_VFN(vf)); 4812 c.retval_len16 = htonl(FW_LEN16(c)); 4813 4814 while (nparams--) { 4815 *p++ = htonl(*params); 4816 params++; 4817 *p++ = htonl(*val); 4818 val++; 4819 } 4820 4821 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 4822} 4823 4824/** 4825 * t4_cfg_pfvf - configure PF/VF resource limits 4826 * @adap: the adapter 4827 * @mbox: mailbox to use for the FW command 4828 * @pf: the PF being configured 4829 * @vf: the VF being configured 4830 * @txq: the max number of egress queues 4831 * @txq_eth_ctrl: the max number of egress Ethernet or control queues 4832 * @rxqi: the max number of interrupt-capable ingress queues 4833 * @rxq: the max number of interruptless ingress queues 4834 * @tc: the PCI traffic class 4835 * @vi: the max number of virtual interfaces 4836 * @cmask: the channel access rights mask for the PF/VF 4837 * @pmask: the port access rights mask for the PF/VF 4838 * @nexact: the maximum number of exact MPS filters 4839 * @rcaps: read capabilities 4840 * @wxcaps: write/execute capabilities 4841 * 4842 * Configures resource limits and capabilities for a physical or virtual 4843 * function. 4844 */ 4845int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 4846 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 4847 unsigned int rxqi, unsigned int rxq, unsigned int tc, 4848 unsigned int vi, unsigned int cmask, unsigned int pmask, 4849 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps) 4850{ 4851 struct fw_pfvf_cmd c; 4852 4853 memset(&c, 0, sizeof(c)); 4854 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_PFVF_CMD) | F_FW_CMD_REQUEST | 4855 F_FW_CMD_WRITE | V_FW_PFVF_CMD_PFN(pf) | 4856 V_FW_PFVF_CMD_VFN(vf)); 4857 c.retval_len16 = htonl(FW_LEN16(c)); 4858 c.niqflint_niq = htonl(V_FW_PFVF_CMD_NIQFLINT(rxqi) | 4859 V_FW_PFVF_CMD_NIQ(rxq)); 4860 c.type_to_neq = htonl(V_FW_PFVF_CMD_CMASK(cmask) | 4861 V_FW_PFVF_CMD_PMASK(pmask) | 4862 V_FW_PFVF_CMD_NEQ(txq)); 4863 c.tc_to_nexactf = htonl(V_FW_PFVF_CMD_TC(tc) | V_FW_PFVF_CMD_NVI(vi) | 4864 V_FW_PFVF_CMD_NEXACTF(nexact)); 4865 c.r_caps_to_nethctrl = htonl(V_FW_PFVF_CMD_R_CAPS(rcaps) | 4866 V_FW_PFVF_CMD_WX_CAPS(wxcaps) | 4867 V_FW_PFVF_CMD_NETHCTRL(txq_eth_ctrl)); 4868 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 4869} 4870 4871/** 4872 * t4_alloc_vi_func - allocate a virtual interface 4873 * @adap: the adapter 4874 * @mbox: mailbox to use for the FW command 4875 * @port: physical port associated with the VI 4876 * @pf: the PF owning the VI 4877 * @vf: the VF owning the VI 4878 * @nmac: number of MAC addresses needed (1 to 5) 4879 * @mac: the MAC addresses of the VI 4880 * @rss_size: size of RSS table slice associated with this VI 4881 * @portfunc: which Port Application Function MAC Address is desired 4882 * @idstype: Intrusion Detection Type 4883 * 4884 * Allocates a virtual interface for the given physical port. If @mac is 4885 * not %NULL it contains the MAC addresses of the VI as assigned by FW. 4886 * @mac should be large enough to hold @nmac Ethernet addresses, they are 4887 * stored consecutively so the space needed is @nmac * 6 bytes. 4888 * Returns a negative error number or the non-negative VI id. 4889 */ 4890int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox, 4891 unsigned int port, unsigned int pf, unsigned int vf, 4892 unsigned int nmac, u8 *mac, u16 *rss_size, 4893 unsigned int portfunc, unsigned int idstype) 4894{ 4895 int ret; 4896 struct fw_vi_cmd c; 4897 4898 memset(&c, 0, sizeof(c)); 4899 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST | 4900 F_FW_CMD_WRITE | F_FW_CMD_EXEC | 4901 V_FW_VI_CMD_PFN(pf) | V_FW_VI_CMD_VFN(vf)); 4902 c.alloc_to_len16 = htonl(F_FW_VI_CMD_ALLOC | FW_LEN16(c)); 4903 c.type_to_viid = htons(V_FW_VI_CMD_TYPE(idstype) | 4904 V_FW_VI_CMD_FUNC(portfunc)); 4905 c.portid_pkd = V_FW_VI_CMD_PORTID(port); 4906 c.nmac = nmac - 1; 4907 4908 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 4909 if (ret) 4910 return ret; 4911 4912 if (mac) { 4913 memcpy(mac, c.mac, sizeof(c.mac)); 4914 switch (nmac) { 4915 case 5: 4916 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3)); 4917 case 4: 4918 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2)); 4919 case 3: 4920 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1)); 4921 case 2: 4922 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0)); 4923 } 4924 } 4925 if (rss_size) 4926 *rss_size = G_FW_VI_CMD_RSSSIZE(ntohs(c.norss_rsssize)); 4927 return G_FW_VI_CMD_VIID(htons(c.type_to_viid)); 4928} 4929 4930/** 4931 * t4_alloc_vi - allocate an [Ethernet Function] virtual interface 4932 * @adap: the adapter 4933 * @mbox: mailbox to use for the FW command 4934 * @port: physical port associated with the VI 4935 * @pf: the PF owning the VI 4936 * @vf: the VF owning the VI 4937 * @nmac: number of MAC addresses needed (1 to 5) 4938 * @mac: the MAC addresses of the VI 4939 * @rss_size: size of RSS table slice associated with this VI 4940 * 4941 * backwards compatible and convieniance routine to allocate a Virtual 4942 * Interface with a Ethernet Port Application Function and Intrustion 4943 * Detection System disabled. 4944 */ 4945int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 4946 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 4947 u16 *rss_size) 4948{ 4949 return t4_alloc_vi_func(adap, mbox, port, pf, vf, nmac, mac, rss_size, 4950 FW_VI_FUNC_ETH, 0); 4951} 4952 4953/** 4954 * t4_free_vi - free a virtual interface 4955 * @adap: the adapter 4956 * @mbox: mailbox to use for the FW command 4957 * @pf: the PF owning the VI 4958 * @vf: the VF owning the VI 4959 * @viid: virtual interface identifiler 4960 * 4961 * Free a previously allocated virtual interface. 4962 */ 4963int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf, 4964 unsigned int vf, unsigned int viid) 4965{ 4966 struct fw_vi_cmd c; 4967 4968 memset(&c, 0, sizeof(c)); 4969 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_VI_CMD) | 4970 F_FW_CMD_REQUEST | 4971 F_FW_CMD_EXEC | 4972 V_FW_VI_CMD_PFN(pf) | 4973 V_FW_VI_CMD_VFN(vf)); 4974 c.alloc_to_len16 = htonl(F_FW_VI_CMD_FREE | FW_LEN16(c)); 4975 c.type_to_viid = htons(V_FW_VI_CMD_VIID(viid)); 4976 4977 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 4978} 4979 4980/** 4981 * t4_set_rxmode - set Rx properties of a virtual interface 4982 * @adap: the adapter 4983 * @mbox: mailbox to use for the FW command 4984 * @viid: the VI id 4985 * @mtu: the new MTU or -1 4986 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change 4987 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change 4988 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change 4989 * @vlanex: 1 to enable HVLAN extraction, 0 to disable it, -1 no change 4990 * @sleep_ok: if true we may sleep while awaiting command completion 4991 * 4992 * Sets Rx properties of a virtual interface. 4993 */ 4994int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 4995 int mtu, int promisc, int all_multi, int bcast, int vlanex, 4996 bool sleep_ok) 4997{ 4998 struct fw_vi_rxmode_cmd c; 4999 5000 /* convert to FW values */ 5001 if (mtu < 0) 5002 mtu = M_FW_VI_RXMODE_CMD_MTU; 5003 if (promisc < 0) 5004 promisc = M_FW_VI_RXMODE_CMD_PROMISCEN; 5005 if (all_multi < 0) 5006 all_multi = M_FW_VI_RXMODE_CMD_ALLMULTIEN; 5007 if (bcast < 0) 5008 bcast = M_FW_VI_RXMODE_CMD_BROADCASTEN; 5009 if (vlanex < 0) 5010 vlanex = M_FW_VI_RXMODE_CMD_VLANEXEN; 5011 5012 memset(&c, 0, sizeof(c)); 5013 c.op_to_viid = htonl(V_FW_CMD_OP(FW_VI_RXMODE_CMD) | F_FW_CMD_REQUEST | 5014 F_FW_CMD_WRITE | V_FW_VI_RXMODE_CMD_VIID(viid)); 5015 c.retval_len16 = htonl(FW_LEN16(c)); 5016 c.mtu_to_vlanexen = htonl(V_FW_VI_RXMODE_CMD_MTU(mtu) | 5017 V_FW_VI_RXMODE_CMD_PROMISCEN(promisc) | 5018 V_FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) | 5019 V_FW_VI_RXMODE_CMD_BROADCASTEN(bcast) | 5020 V_FW_VI_RXMODE_CMD_VLANEXEN(vlanex)); 5021 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok); 5022} 5023 5024/** 5025 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses 5026 * @adap: the adapter 5027 * @mbox: mailbox to use for the FW command 5028 * @viid: the VI id 5029 * @free: if true any existing filters for this VI id are first removed 5030 * @naddr: the number of MAC addresses to allocate filters for (up to 7) 5031 * @addr: the MAC address(es) 5032 * @idx: where to store the index of each allocated filter 5033 * @hash: pointer to hash address filter bitmap 5034 * @sleep_ok: call is allowed to sleep 5035 * 5036 * Allocates an exact-match filter for each of the supplied addresses and 5037 * sets it to the corresponding address. If @idx is not %NULL it should 5038 * have at least @naddr entries, each of which will be set to the index of 5039 * the filter allocated for the corresponding MAC address. If a filter 5040 * could not be allocated for an address its index is set to 0xffff. 5041 * If @hash is not %NULL addresses that fail to allocate an exact filter 5042 * are hashed and update the hash filter bitmap pointed at by @hash. 5043 * 5044 * Returns a negative error number or the number of filters allocated. 5045 */ 5046int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 5047 unsigned int viid, bool free, unsigned int naddr, 5048 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok) 5049{ 5050 int offset, ret = 0; 5051 struct fw_vi_mac_cmd c; 5052 unsigned int nfilters = 0; 5053 unsigned int max_naddr = is_t4(adap) ? 5054 NUM_MPS_CLS_SRAM_L_INSTANCES : 5055 NUM_MPS_T5_CLS_SRAM_L_INSTANCES; 5056 unsigned int rem = naddr; 5057 5058 if (naddr > max_naddr) 5059 return -EINVAL; 5060 5061 for (offset = 0; offset < naddr ; /**/) { 5062 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) 5063 ? rem 5064 : ARRAY_SIZE(c.u.exact)); 5065 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd, 5066 u.exact[fw_naddr]), 16); 5067 struct fw_vi_mac_exact *p; 5068 int i; 5069 5070 memset(&c, 0, sizeof(c)); 5071 c.op_to_viid = htonl(V_FW_CMD_OP(FW_VI_MAC_CMD) | 5072 F_FW_CMD_REQUEST | 5073 F_FW_CMD_WRITE | 5074 V_FW_CMD_EXEC(free) | 5075 V_FW_VI_MAC_CMD_VIID(viid)); 5076 c.freemacs_to_len16 = htonl(V_FW_VI_MAC_CMD_FREEMACS(free) | 5077 V_FW_CMD_LEN16(len16)); 5078 5079 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) { 5080 p->valid_to_idx = htons( 5081 F_FW_VI_MAC_CMD_VALID | 5082 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC)); 5083 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr)); 5084 } 5085 5086 /* 5087 * It's okay if we run out of space in our MAC address arena. 5088 * Some of the addresses we submit may get stored so we need 5089 * to run through the reply to see what the results were ... 5090 */ 5091 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok); 5092 if (ret && ret != -FW_ENOMEM) 5093 break; 5094 5095 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) { 5096 u16 index = G_FW_VI_MAC_CMD_IDX(ntohs(p->valid_to_idx)); 5097 5098 if (idx) 5099 idx[offset+i] = (index >= max_naddr 5100 ? 0xffff 5101 : index); 5102 if (index < max_naddr) 5103 nfilters++; 5104 else if (hash) 5105 *hash |= (1ULL << hash_mac_addr(addr[offset+i])); 5106 } 5107 5108 free = false; 5109 offset += fw_naddr; 5110 rem -= fw_naddr; 5111 } 5112 5113 if (ret == 0 || ret == -FW_ENOMEM) 5114 ret = nfilters; 5115 return ret; 5116} 5117 5118/** 5119 * t4_change_mac - modifies the exact-match filter for a MAC address 5120 * @adap: the adapter 5121 * @mbox: mailbox to use for the FW command 5122 * @viid: the VI id 5123 * @idx: index of existing filter for old value of MAC address, or -1 5124 * @addr: the new MAC address value 5125 * @persist: whether a new MAC allocation should be persistent 5126 * @add_smt: if true also add the address to the HW SMT 5127 * 5128 * Modifies an exact-match filter and sets it to the new MAC address if 5129 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the 5130 * latter case the address is added persistently if @persist is %true. 5131 * 5132 * Note that in general it is not possible to modify the value of a given 5133 * filter so the generic way to modify an address filter is to free the one 5134 * being used by the old address value and allocate a new filter for the 5135 * new address value. 5136 * 5137 * Returns a negative error number or the index of the filter with the new 5138 * MAC value. Note that this index may differ from @idx. 5139 */ 5140int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 5141 int idx, const u8 *addr, bool persist, bool add_smt) 5142{ 5143 int ret, mode; 5144 struct fw_vi_mac_cmd c; 5145 struct fw_vi_mac_exact *p = c.u.exact; 5146 unsigned int max_mac_addr = is_t4(adap) ? 5147 NUM_MPS_CLS_SRAM_L_INSTANCES : 5148 NUM_MPS_T5_CLS_SRAM_L_INSTANCES; 5149 5150 if (idx < 0) /* new allocation */ 5151 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC; 5152 mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY; 5153 5154 memset(&c, 0, sizeof(c)); 5155 c.op_to_viid = htonl(V_FW_CMD_OP(FW_VI_MAC_CMD) | F_FW_CMD_REQUEST | 5156 F_FW_CMD_WRITE | V_FW_VI_MAC_CMD_VIID(viid)); 5157 c.freemacs_to_len16 = htonl(V_FW_CMD_LEN16(1)); 5158 p->valid_to_idx = htons(F_FW_VI_MAC_CMD_VALID | 5159 V_FW_VI_MAC_CMD_SMAC_RESULT(mode) | 5160 V_FW_VI_MAC_CMD_IDX(idx)); 5161 memcpy(p->macaddr, addr, sizeof(p->macaddr)); 5162 5163 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 5164 if (ret == 0) { 5165 ret = G_FW_VI_MAC_CMD_IDX(ntohs(p->valid_to_idx)); 5166 if (ret >= max_mac_addr) 5167 ret = -ENOMEM; 5168 } 5169 return ret; 5170} 5171 5172/** 5173 * t4_set_addr_hash - program the MAC inexact-match hash filter 5174 * @adap: the adapter 5175 * @mbox: mailbox to use for the FW command 5176 * @viid: the VI id 5177 * @ucast: whether the hash filter should also match unicast addresses 5178 * @vec: the value to be written to the hash filter 5179 * @sleep_ok: call is allowed to sleep 5180 * 5181 * Sets the 64-bit inexact-match hash filter for a virtual interface. 5182 */ 5183int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 5184 bool ucast, u64 vec, bool sleep_ok) 5185{ 5186 struct fw_vi_mac_cmd c; 5187 5188 memset(&c, 0, sizeof(c)); 5189 c.op_to_viid = htonl(V_FW_CMD_OP(FW_VI_MAC_CMD) | F_FW_CMD_REQUEST | 5190 F_FW_CMD_WRITE | V_FW_VI_ENABLE_CMD_VIID(viid)); 5191 c.freemacs_to_len16 = htonl(F_FW_VI_MAC_CMD_HASHVECEN | 5192 V_FW_VI_MAC_CMD_HASHUNIEN(ucast) | 5193 V_FW_CMD_LEN16(1)); 5194 c.u.hash.hashvec = cpu_to_be64(vec); 5195 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok); 5196} 5197 5198/** 5199 * t4_enable_vi - enable/disable a virtual interface 5200 * @adap: the adapter 5201 * @mbox: mailbox to use for the FW command 5202 * @viid: the VI id 5203 * @rx_en: 1=enable Rx, 0=disable Rx 5204 * @tx_en: 1=enable Tx, 0=disable Tx 5205 * 5206 * Enables/disables a virtual interface. 5207 */ 5208int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 5209 bool rx_en, bool tx_en) 5210{ 5211 struct fw_vi_enable_cmd c; 5212 5213 memset(&c, 0, sizeof(c)); 5214 c.op_to_viid = htonl(V_FW_CMD_OP(FW_VI_ENABLE_CMD) | F_FW_CMD_REQUEST | 5215 F_FW_CMD_EXEC | V_FW_VI_ENABLE_CMD_VIID(viid)); 5216 c.ien_to_len16 = htonl(V_FW_VI_ENABLE_CMD_IEN(rx_en) | 5217 V_FW_VI_ENABLE_CMD_EEN(tx_en) | FW_LEN16(c)); 5218 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 5219} 5220 5221/** 5222 * t4_identify_port - identify a VI's port by blinking its LED 5223 * @adap: the adapter 5224 * @mbox: mailbox to use for the FW command 5225 * @viid: the VI id 5226 * @nblinks: how many times to blink LED at 2.5 Hz 5227 * 5228 * Identifies a VI's port by blinking its LED. 5229 */ 5230int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 5231 unsigned int nblinks) 5232{ 5233 struct fw_vi_enable_cmd c; 5234 5235 memset(&c, 0, sizeof(c)); 5236 c.op_to_viid = htonl(V_FW_CMD_OP(FW_VI_ENABLE_CMD) | F_FW_CMD_REQUEST | 5237 F_FW_CMD_EXEC | V_FW_VI_ENABLE_CMD_VIID(viid)); 5238 c.ien_to_len16 = htonl(F_FW_VI_ENABLE_CMD_LED | FW_LEN16(c)); 5239 c.blinkdur = htons(nblinks); 5240 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 5241} 5242 5243/** 5244 * t4_iq_start_stop - enable/disable an ingress queue and its FLs 5245 * @adap: the adapter 5246 * @mbox: mailbox to use for the FW command 5247 * @start: %true to enable the queues, %false to disable them 5248 * @pf: the PF owning the queues 5249 * @vf: the VF owning the queues 5250 * @iqid: ingress queue id 5251 * @fl0id: FL0 queue id or 0xffff if no attached FL0 5252 * @fl1id: FL1 queue id or 0xffff if no attached FL1 5253 * 5254 * Starts or stops an ingress queue and its associated FLs, if any. 5255 */ 5256int t4_iq_start_stop(struct adapter *adap, unsigned int mbox, bool start, 5257 unsigned int pf, unsigned int vf, unsigned int iqid, 5258 unsigned int fl0id, unsigned int fl1id) 5259{ 5260 struct fw_iq_cmd c; 5261 5262 memset(&c, 0, sizeof(c)); 5263 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 5264 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) | 5265 V_FW_IQ_CMD_VFN(vf)); 5266 c.alloc_to_len16 = htonl(V_FW_IQ_CMD_IQSTART(start) | 5267 V_FW_IQ_CMD_IQSTOP(!start) | FW_LEN16(c)); 5268 c.iqid = htons(iqid); 5269 c.fl0id = htons(fl0id); 5270 c.fl1id = htons(fl1id); 5271 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 5272} 5273 5274/** 5275 * t4_iq_free - free an ingress queue and its FLs 5276 * @adap: the adapter 5277 * @mbox: mailbox to use for the FW command 5278 * @pf: the PF owning the queues 5279 * @vf: the VF owning the queues 5280 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.) 5281 * @iqid: ingress queue id 5282 * @fl0id: FL0 queue id or 0xffff if no attached FL0 5283 * @fl1id: FL1 queue id or 0xffff if no attached FL1 5284 * 5285 * Frees an ingress queue and its associated FLs, if any. 5286 */ 5287int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 5288 unsigned int vf, unsigned int iqtype, unsigned int iqid, 5289 unsigned int fl0id, unsigned int fl1id) 5290{ 5291 struct fw_iq_cmd c; 5292 5293 memset(&c, 0, sizeof(c)); 5294 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 5295 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) | 5296 V_FW_IQ_CMD_VFN(vf)); 5297 c.alloc_to_len16 = htonl(F_FW_IQ_CMD_FREE | FW_LEN16(c)); 5298 c.type_to_iqandstindex = htonl(V_FW_IQ_CMD_TYPE(iqtype)); 5299 c.iqid = htons(iqid); 5300 c.fl0id = htons(fl0id); 5301 c.fl1id = htons(fl1id); 5302 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 5303} 5304 5305/** 5306 * t4_eth_eq_free - free an Ethernet egress queue 5307 * @adap: the adapter 5308 * @mbox: mailbox to use for the FW command 5309 * @pf: the PF owning the queue 5310 * @vf: the VF owning the queue 5311 * @eqid: egress queue id 5312 * 5313 * Frees an Ethernet egress queue. 5314 */ 5315int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 5316 unsigned int vf, unsigned int eqid) 5317{ 5318 struct fw_eq_eth_cmd c; 5319 5320 memset(&c, 0, sizeof(c)); 5321 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST | 5322 F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(pf) | 5323 V_FW_EQ_ETH_CMD_VFN(vf)); 5324 c.alloc_to_len16 = htonl(F_FW_EQ_ETH_CMD_FREE | FW_LEN16(c)); 5325 c.eqid_pkd = htonl(V_FW_EQ_ETH_CMD_EQID(eqid)); 5326 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 5327} 5328 5329/** 5330 * t4_ctrl_eq_free - free a control egress queue 5331 * @adap: the adapter 5332 * @mbox: mailbox to use for the FW command 5333 * @pf: the PF owning the queue 5334 * @vf: the VF owning the queue 5335 * @eqid: egress queue id 5336 * 5337 * Frees a control egress queue. 5338 */ 5339int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 5340 unsigned int vf, unsigned int eqid) 5341{ 5342 struct fw_eq_ctrl_cmd c; 5343 5344 memset(&c, 0, sizeof(c)); 5345 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST | 5346 F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(pf) | 5347 V_FW_EQ_CTRL_CMD_VFN(vf)); 5348 c.alloc_to_len16 = htonl(F_FW_EQ_CTRL_CMD_FREE | FW_LEN16(c)); 5349 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_EQID(eqid)); 5350 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 5351} 5352 5353/** 5354 * t4_ofld_eq_free - free an offload egress queue 5355 * @adap: the adapter 5356 * @mbox: mailbox to use for the FW command 5357 * @pf: the PF owning the queue 5358 * @vf: the VF owning the queue 5359 * @eqid: egress queue id 5360 * 5361 * Frees a control egress queue. 5362 */ 5363int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 5364 unsigned int vf, unsigned int eqid) 5365{ 5366 struct fw_eq_ofld_cmd c; 5367 5368 memset(&c, 0, sizeof(c)); 5369 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST | 5370 F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(pf) | 5371 V_FW_EQ_OFLD_CMD_VFN(vf)); 5372 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_FREE | FW_LEN16(c)); 5373 c.eqid_pkd = htonl(V_FW_EQ_OFLD_CMD_EQID(eqid)); 5374 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 5375} 5376 5377/** 5378 * t4_handle_fw_rpl - process a FW reply message 5379 * @adap: the adapter 5380 * @rpl: start of the FW message 5381 * 5382 * Processes a FW message, such as link state change messages. 5383 */ 5384int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl) 5385{ 5386 u8 opcode = *(const u8 *)rpl; 5387 const struct fw_port_cmd *p = (const void *)rpl; 5388 unsigned int action = G_FW_PORT_CMD_ACTION(ntohl(p->action_to_len16)); 5389 5390 if (opcode == FW_PORT_CMD && action == FW_PORT_ACTION_GET_PORT_INFO) { 5391 /* link/module state change message */ 5392 int speed = 0, fc = 0, i; 5393 int chan = G_FW_PORT_CMD_PORTID(ntohl(p->op_to_portid)); 5394 struct port_info *pi = NULL; 5395 struct link_config *lc; 5396 u32 stat = ntohl(p->u.info.lstatus_to_modtype); 5397 int link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0; 5398 u32 mod = G_FW_PORT_CMD_MODTYPE(stat); 5399 5400 if (stat & F_FW_PORT_CMD_RXPAUSE) 5401 fc |= PAUSE_RX; 5402 if (stat & F_FW_PORT_CMD_TXPAUSE) 5403 fc |= PAUSE_TX; 5404 if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M)) 5405 speed = SPEED_100; 5406 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G)) 5407 speed = SPEED_1000; 5408 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G)) 5409 speed = SPEED_10000; 5410 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G)) 5411 speed = SPEED_40000; 5412 5413 for_each_port(adap, i) { 5414 pi = adap2pinfo(adap, i); 5415 if (pi->tx_chan == chan) 5416 break; 5417 } 5418 lc = &pi->link_cfg; 5419 5420 if (link_ok != lc->link_ok || speed != lc->speed || 5421 fc != lc->fc) { /* something changed */ 5422 int reason; 5423 5424 if (!link_ok && lc->link_ok) 5425 reason = G_FW_PORT_CMD_LINKDNRC(stat); 5426 else 5427 reason = -1; 5428 5429 lc->link_ok = link_ok; 5430 lc->speed = speed; 5431 lc->fc = fc; 5432 lc->supported = ntohs(p->u.info.pcap); 5433 t4_os_link_changed(adap, i, link_ok, reason); 5434 } 5435 if (mod != pi->mod_type) { 5436 pi->mod_type = mod; 5437 t4_os_portmod_changed(adap, i); 5438 } 5439 } else { 5440 CH_WARN_RATELIMIT(adap, 5441 "Unknown firmware reply 0x%x (0x%x)\n", opcode, action); 5442 return -EINVAL; 5443 } 5444 return 0; 5445} 5446 5447/** 5448 * get_pci_mode - determine a card's PCI mode 5449 * @adapter: the adapter 5450 * @p: where to store the PCI settings 5451 * 5452 * Determines a card's PCI mode and associated parameters, such as speed 5453 * and width. 5454 */ 5455static void __devinit get_pci_mode(struct adapter *adapter, 5456 struct pci_params *p) 5457{ 5458 u16 val; 5459 u32 pcie_cap; 5460 5461 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP); 5462 if (pcie_cap) { 5463 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_LNKSTA, &val); 5464 p->speed = val & PCI_EXP_LNKSTA_CLS; 5465 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4; 5466 } 5467} 5468 5469/** 5470 * init_link_config - initialize a link's SW state 5471 * @lc: structure holding the link state 5472 * @caps: link capabilities 5473 * 5474 * Initializes the SW state maintained for each link, including the link's 5475 * capabilities and default speed/flow-control/autonegotiation settings. 5476 */ 5477static void __devinit init_link_config(struct link_config *lc, 5478 unsigned int caps) 5479{ 5480 lc->supported = caps; 5481 lc->requested_speed = 0; 5482 lc->speed = 0; 5483 lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX; 5484 if (lc->supported & FW_PORT_CAP_ANEG) { 5485 lc->advertising = lc->supported & ADVERT_MASK; 5486 lc->autoneg = AUTONEG_ENABLE; 5487 lc->requested_fc |= PAUSE_AUTONEG; 5488 } else { 5489 lc->advertising = 0; 5490 lc->autoneg = AUTONEG_DISABLE; 5491 } 5492} 5493 5494static int __devinit get_flash_params(struct adapter *adapter) 5495{ 5496 int ret; 5497 u32 info = 0; 5498 5499 ret = sf1_write(adapter, 1, 1, 0, SF_RD_ID); 5500 if (!ret) 5501 ret = sf1_read(adapter, 3, 0, 1, &info); 5502 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 5503 if (ret < 0) 5504 return ret; 5505 5506 if ((info & 0xff) != 0x20) /* not a Numonix flash */ 5507 return -EINVAL; 5508 info >>= 16; /* log2 of size */ 5509 if (info >= 0x14 && info < 0x18) 5510 adapter->params.sf_nsec = 1 << (info - 16); 5511 else if (info == 0x18) 5512 adapter->params.sf_nsec = 64; 5513 else 5514 return -EINVAL; 5515 adapter->params.sf_size = 1 << info; 5516 return 0; 5517} 5518 5519static void __devinit set_pcie_completion_timeout(struct adapter *adapter, 5520 u8 range) 5521{ 5522 u16 val; 5523 u32 pcie_cap; 5524 5525 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP); 5526 if (pcie_cap) { 5527 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val); 5528 val &= 0xfff0; 5529 val |= range ; 5530 t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val); 5531 } 5532} 5533 5534/** 5535 * t4_prep_adapter - prepare SW and HW for operation 5536 * @adapter: the adapter 5537 * @reset: if true perform a HW reset 5538 * 5539 * Initialize adapter SW state for the various HW modules, set initial 5540 * values for some adapter tunables, take PHYs out of reset, and 5541 * initialize the MDIO interface. 5542 */ 5543int __devinit t4_prep_adapter(struct adapter *adapter) 5544{ 5545 int ret; 5546 uint16_t device_id; 5547 uint32_t pl_rev; 5548 5549 get_pci_mode(adapter, &adapter->params.pci); 5550 5551 pl_rev = t4_read_reg(adapter, A_PL_REV); 5552 adapter->params.chipid = G_CHIPID(pl_rev); 5553 adapter->params.rev = G_REV(pl_rev); 5554 if (adapter->params.chipid == 0) { 5555 /* T4 did not have chipid in PL_REV (T5 onwards do) */ 5556 adapter->params.chipid = CHELSIO_T4; 5557 5558 /* T4A1 chip is not supported */ 5559 if (adapter->params.rev == 1) { 5560 CH_ALERT(adapter, "T4 rev 1 chip is not supported.\n"); 5561 return -EINVAL; 5562 } 5563 } 5564 adapter->params.pci.vpd_cap_addr = 5565 t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD); 5566 5567 ret = get_flash_params(adapter); 5568 if (ret < 0) 5569 return ret; 5570 5571 ret = get_vpd_params(adapter, &adapter->params.vpd); 5572 if (ret < 0) 5573 return ret; 5574 5575 /* Cards with real ASICs have the chipid in the PCIe device id */ 5576 t4_os_pci_read_cfg2(adapter, PCI_DEVICE_ID, &device_id); 5577 if (device_id >> 12 == adapter->params.chipid) 5578 adapter->params.cim_la_size = CIMLA_SIZE; 5579 else { 5580 /* FPGA */ 5581 adapter->params.fpga = 1; 5582 adapter->params.cim_la_size = 2 * CIMLA_SIZE; 5583 } 5584 5585 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd); 5586 5587 /* 5588 * Default port and clock for debugging in case we can't reach FW. 5589 */ 5590 adapter->params.nports = 1; 5591 adapter->params.portvec = 1; 5592 adapter->params.vpd.cclk = 50000; 5593 5594 /* Set pci completion timeout value to 4 seconds. */ 5595 set_pcie_completion_timeout(adapter, 0xd); 5596 return 0; 5597} 5598 5599/** 5600 * t4_init_tp_params - initialize adap->params.tp 5601 * @adap: the adapter 5602 * 5603 * Initialize various fields of the adapter's TP Parameters structure. 5604 */ 5605int __devinit t4_init_tp_params(struct adapter *adap) 5606{ 5607 int chan; 5608 u32 v; 5609 5610 v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION); 5611 adap->params.tp.tre = G_TIMERRESOLUTION(v); 5612 adap->params.tp.dack_re = G_DELAYEDACKRESOLUTION(v); 5613 5614 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */ 5615 for (chan = 0; chan < NCHAN; chan++) 5616 adap->params.tp.tx_modq[chan] = chan; 5617 5618 /* 5619 * Cache the adapter's Compressed Filter Mode and global Incress 5620 * Configuration. 5621 */ 5622 t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, 5623 &adap->params.tp.vlan_pri_map, 1, 5624 A_TP_VLAN_PRI_MAP); 5625 t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, 5626 &adap->params.tp.ingress_config, 1, 5627 A_TP_INGRESS_CONFIG); 5628 5629 /* 5630 * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field 5631 * shift positions of several elements of the Compressed Filter Tuple 5632 * for this adapter which we need frequently ... 5633 */ 5634 adap->params.tp.vlan_shift = t4_filter_field_shift(adap, F_VLAN); 5635 adap->params.tp.vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID); 5636 adap->params.tp.port_shift = t4_filter_field_shift(adap, F_PORT); 5637 adap->params.tp.protocol_shift = t4_filter_field_shift(adap, F_PROTOCOL); 5638 5639 /* 5640 * If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID 5641 * represents the presense of an Outer VLAN instead of a VNIC ID. 5642 */ 5643 if ((adap->params.tp.ingress_config & F_VNIC) == 0) 5644 adap->params.tp.vnic_shift = -1; 5645 5646 return 0; 5647} 5648 5649/** 5650 * t4_filter_field_shift - calculate filter field shift 5651 * @adap: the adapter 5652 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits) 5653 * 5654 * Return the shift position of a filter field within the Compressed 5655 * Filter Tuple. The filter field is specified via its selection bit 5656 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN. 5657 */ 5658int t4_filter_field_shift(const struct adapter *adap, int filter_sel) 5659{ 5660 unsigned int filter_mode = adap->params.tp.vlan_pri_map; 5661 unsigned int sel; 5662 int field_shift; 5663 5664 if ((filter_mode & filter_sel) == 0) 5665 return -1; 5666 5667 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) { 5668 switch (filter_mode & sel) { 5669 case F_FCOE: field_shift += W_FT_FCOE; break; 5670 case F_PORT: field_shift += W_FT_PORT; break; 5671 case F_VNIC_ID: field_shift += W_FT_VNIC_ID; break; 5672 case F_VLAN: field_shift += W_FT_VLAN; break; 5673 case F_TOS: field_shift += W_FT_TOS; break; 5674 case F_PROTOCOL: field_shift += W_FT_PROTOCOL; break; 5675 case F_ETHERTYPE: field_shift += W_FT_ETHERTYPE; break; 5676 case F_MACMATCH: field_shift += W_FT_MACMATCH; break; 5677 case F_MPSHITTYPE: field_shift += W_FT_MPSHITTYPE; break; 5678 case F_FRAGMENTATION: field_shift += W_FT_FRAGMENTATION; break; 5679 } 5680 } 5681 return field_shift; 5682} 5683 5684int __devinit t4_port_init(struct port_info *p, int mbox, int pf, int vf) 5685{ 5686 u8 addr[6]; 5687 int ret, i, j; 5688 struct fw_port_cmd c; 5689 u16 rss_size; 5690 adapter_t *adap = p->adapter; 5691 5692 memset(&c, 0, sizeof(c)); 5693 5694 for (i = 0, j = -1; i <= p->port_id; i++) { 5695 do { 5696 j++; 5697 } while ((adap->params.portvec & (1 << j)) == 0); 5698 } 5699 5700 c.op_to_portid = htonl(V_FW_CMD_OP(FW_PORT_CMD) | 5701 F_FW_CMD_REQUEST | F_FW_CMD_READ | 5702 V_FW_PORT_CMD_PORTID(j)); 5703 c.action_to_len16 = htonl( 5704 V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_GET_PORT_INFO) | 5705 FW_LEN16(c)); 5706 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 5707 if (ret) 5708 return ret; 5709 5710 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size); 5711 if (ret < 0) 5712 return ret; 5713 5714 p->viid = ret; 5715 p->tx_chan = j; 5716 p->rx_chan_map = get_mps_bg_map(adap, j); 5717 p->lport = j; 5718 p->rss_size = rss_size; 5719 t4_os_set_hw_addr(adap, p->port_id, addr); 5720 5721 ret = ntohl(c.u.info.lstatus_to_modtype); 5722 p->mdio_addr = (ret & F_FW_PORT_CMD_MDIOCAP) ? 5723 G_FW_PORT_CMD_MDIOADDR(ret) : -1; 5724 p->port_type = G_FW_PORT_CMD_PTYPE(ret); 5725 p->mod_type = G_FW_PORT_CMD_MODTYPE(ret); 5726 5727 init_link_config(&p->link_cfg, ntohs(c.u.info.pcap)); 5728 5729 return 0; 5730} 5731 5732int t4_sched_config(struct adapter *adapter, int type, int minmaxen, 5733 int sleep_ok) 5734{ 5735 struct fw_sched_cmd cmd; 5736 5737 memset(&cmd, 0, sizeof(cmd)); 5738 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 5739 F_FW_CMD_REQUEST | 5740 F_FW_CMD_WRITE); 5741 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 5742 5743 cmd.u.config.sc = FW_SCHED_SC_CONFIG; 5744 cmd.u.config.type = type; 5745 cmd.u.config.minmaxen = minmaxen; 5746 5747 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 5748 NULL, sleep_ok); 5749} 5750 5751int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 5752 int rateunit, int ratemode, int channel, int cl, 5753 int minrate, int maxrate, int weight, int pktsize, 5754 int sleep_ok) 5755{ 5756 struct fw_sched_cmd cmd; 5757 5758 memset(&cmd, 0, sizeof(cmd)); 5759 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 5760 F_FW_CMD_REQUEST | 5761 F_FW_CMD_WRITE); 5762 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 5763 5764 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 5765 cmd.u.params.type = type; 5766 cmd.u.params.level = level; 5767 cmd.u.params.mode = mode; 5768 cmd.u.params.ch = channel; 5769 cmd.u.params.cl = cl; 5770 cmd.u.params.unit = rateunit; 5771 cmd.u.params.rate = ratemode; 5772 cmd.u.params.min = cpu_to_be32(minrate); 5773 cmd.u.params.max = cpu_to_be32(maxrate); 5774 cmd.u.params.weight = cpu_to_be16(weight); 5775 cmd.u.params.pktsize = cpu_to_be16(pktsize); 5776 5777 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 5778 NULL, sleep_ok); 5779} 5780