ar5212_attach.c revision 235972
1185377Ssam/* 2187831Ssam * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2002-2008 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17187831Ssam * $FreeBSD: head/sys/dev/ath/ath_hal/ar5212/ar5212_attach.c 235972 2012-05-25 05:01:27Z adrian $ 18185377Ssam */ 19185377Ssam#include "opt_ah.h" 20185377Ssam 21185377Ssam#include "ah.h" 22185377Ssam#include "ah_internal.h" 23185377Ssam#include "ah_devid.h" 24185377Ssam 25185377Ssam#include "ar5212/ar5212.h" 26185377Ssam#include "ar5212/ar5212reg.h" 27185377Ssam#include "ar5212/ar5212phy.h" 28185377Ssam 29185377Ssam#define AH_5212_COMMON 30185377Ssam#include "ar5212/ar5212.ini" 31185377Ssam 32235972Sadrianstatic void ar5212ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, 33235972Sadrian HAL_BOOL power_off); 34188979Ssamstatic void ar5212DisablePCIE(struct ath_hal *ah); 35188979Ssam 36185377Ssamstatic const struct ath_hal_private ar5212hal = {{ 37185377Ssam .ah_magic = AR5212_MAGIC, 38185377Ssam 39185377Ssam .ah_getRateTable = ar5212GetRateTable, 40185377Ssam .ah_detach = ar5212Detach, 41185377Ssam 42185377Ssam /* Reset Functions */ 43185377Ssam .ah_reset = ar5212Reset, 44185377Ssam .ah_phyDisable = ar5212PhyDisable, 45185377Ssam .ah_disable = ar5212Disable, 46188979Ssam .ah_configPCIE = ar5212ConfigPCIE, 47188979Ssam .ah_disablePCIE = ar5212DisablePCIE, 48185377Ssam .ah_setPCUConfig = ar5212SetPCUConfig, 49185377Ssam .ah_perCalibration = ar5212PerCalibration, 50185380Ssam .ah_perCalibrationN = ar5212PerCalibrationN, 51185380Ssam .ah_resetCalValid = ar5212ResetCalValid, 52185377Ssam .ah_setTxPowerLimit = ar5212SetTxPowerLimit, 53185377Ssam .ah_getChanNoise = ath_hal_getChanNoise, 54185377Ssam 55185377Ssam /* Transmit functions */ 56185377Ssam .ah_updateTxTrigLevel = ar5212UpdateTxTrigLevel, 57185377Ssam .ah_setupTxQueue = ar5212SetupTxQueue, 58185377Ssam .ah_setTxQueueProps = ar5212SetTxQueueProps, 59185377Ssam .ah_getTxQueueProps = ar5212GetTxQueueProps, 60185377Ssam .ah_releaseTxQueue = ar5212ReleaseTxQueue, 61185377Ssam .ah_resetTxQueue = ar5212ResetTxQueue, 62185377Ssam .ah_getTxDP = ar5212GetTxDP, 63185377Ssam .ah_setTxDP = ar5212SetTxDP, 64185377Ssam .ah_numTxPending = ar5212NumTxPending, 65185377Ssam .ah_startTxDma = ar5212StartTxDma, 66185377Ssam .ah_stopTxDma = ar5212StopTxDma, 67185377Ssam .ah_setupTxDesc = ar5212SetupTxDesc, 68185377Ssam .ah_setupXTxDesc = ar5212SetupXTxDesc, 69185377Ssam .ah_fillTxDesc = ar5212FillTxDesc, 70185377Ssam .ah_procTxDesc = ar5212ProcTxDesc, 71185377Ssam .ah_getTxIntrQueue = ar5212GetTxIntrQueue, 72185377Ssam .ah_reqTxIntrDesc = ar5212IntrReqTxDesc, 73217621Sadrian .ah_getTxCompletionRates = ar5212GetTxCompletionRates, 74185377Ssam 75185377Ssam /* RX Functions */ 76185377Ssam .ah_getRxDP = ar5212GetRxDP, 77185377Ssam .ah_setRxDP = ar5212SetRxDP, 78185377Ssam .ah_enableReceive = ar5212EnableReceive, 79185377Ssam .ah_stopDmaReceive = ar5212StopDmaReceive, 80185377Ssam .ah_startPcuReceive = ar5212StartPcuReceive, 81185377Ssam .ah_stopPcuReceive = ar5212StopPcuReceive, 82185377Ssam .ah_setMulticastFilter = ar5212SetMulticastFilter, 83185377Ssam .ah_setMulticastFilterIndex = ar5212SetMulticastFilterIndex, 84185377Ssam .ah_clrMulticastFilterIndex = ar5212ClrMulticastFilterIndex, 85185377Ssam .ah_getRxFilter = ar5212GetRxFilter, 86185377Ssam .ah_setRxFilter = ar5212SetRxFilter, 87185377Ssam .ah_setupRxDesc = ar5212SetupRxDesc, 88185377Ssam .ah_procRxDesc = ar5212ProcRxDesc, 89217684Sadrian .ah_rxMonitor = ar5212RxMonitor, 90217684Sadrian .ah_aniPoll = ar5212AniPoll, 91185377Ssam .ah_procMibEvent = ar5212ProcessMibIntr, 92185377Ssam 93185377Ssam /* Misc Functions */ 94185377Ssam .ah_getCapability = ar5212GetCapability, 95185377Ssam .ah_setCapability = ar5212SetCapability, 96185377Ssam .ah_getDiagState = ar5212GetDiagState, 97185377Ssam .ah_getMacAddress = ar5212GetMacAddress, 98185377Ssam .ah_setMacAddress = ar5212SetMacAddress, 99185377Ssam .ah_getBssIdMask = ar5212GetBssIdMask, 100185377Ssam .ah_setBssIdMask = ar5212SetBssIdMask, 101185380Ssam .ah_setRegulatoryDomain = ar5212SetRegulatoryDomain, 102185377Ssam .ah_setLedState = ar5212SetLedState, 103185377Ssam .ah_writeAssocid = ar5212WriteAssocid, 104185377Ssam .ah_gpioCfgInput = ar5212GpioCfgInput, 105185377Ssam .ah_gpioCfgOutput = ar5212GpioCfgOutput, 106185377Ssam .ah_gpioGet = ar5212GpioGet, 107185377Ssam .ah_gpioSet = ar5212GpioSet, 108185377Ssam .ah_gpioSetIntr = ar5212GpioSetIntr, 109185377Ssam .ah_getTsf32 = ar5212GetTsf32, 110185377Ssam .ah_getTsf64 = ar5212GetTsf64, 111185377Ssam .ah_resetTsf = ar5212ResetTsf, 112185377Ssam .ah_detectCardPresent = ar5212DetectCardPresent, 113185377Ssam .ah_updateMibCounters = ar5212UpdateMibCounters, 114185377Ssam .ah_getRfGain = ar5212GetRfgain, 115185377Ssam .ah_getDefAntenna = ar5212GetDefAntenna, 116185377Ssam .ah_setDefAntenna = ar5212SetDefAntenna, 117185377Ssam .ah_getAntennaSwitch = ar5212GetAntennaSwitch, 118185377Ssam .ah_setAntennaSwitch = ar5212SetAntennaSwitch, 119185377Ssam .ah_setSifsTime = ar5212SetSifsTime, 120185377Ssam .ah_getSifsTime = ar5212GetSifsTime, 121185377Ssam .ah_setSlotTime = ar5212SetSlotTime, 122185377Ssam .ah_getSlotTime = ar5212GetSlotTime, 123185377Ssam .ah_setAckTimeout = ar5212SetAckTimeout, 124185377Ssam .ah_getAckTimeout = ar5212GetAckTimeout, 125185377Ssam .ah_setAckCTSRate = ar5212SetAckCTSRate, 126185377Ssam .ah_getAckCTSRate = ar5212GetAckCTSRate, 127185377Ssam .ah_setCTSTimeout = ar5212SetCTSTimeout, 128185377Ssam .ah_getCTSTimeout = ar5212GetCTSTimeout, 129234873Sadrian .ah_setDecompMask = ar5212SetDecompMask, 130234873Sadrian .ah_setCoverageClass = ar5212SetCoverageClass, 131222644Sadrian .ah_setQuiet = ar5212SetQuiet, 132234873Sadrian .ah_getMibCycleCounts = ar5212GetMibCycleCounts, 133185377Ssam 134222584Sadrian /* DFS Functions */ 135222584Sadrian .ah_enableDfs = ar5212EnableDfs, 136222584Sadrian .ah_getDfsThresh = ar5212GetDfsThresh, 137222815Sadrian .ah_procRadarEvent = ar5212ProcessRadarEvent, 138224709Sadrian .ah_isFastClockEnabled = ar5212IsFastClockEnabled, 139230791Sadrian .ah_get11nExtBusy = ar5212Get11nExtBusy, 140222584Sadrian 141185377Ssam /* Key Cache Functions */ 142185377Ssam .ah_getKeyCacheSize = ar5212GetKeyCacheSize, 143185377Ssam .ah_resetKeyCacheEntry = ar5212ResetKeyCacheEntry, 144185377Ssam .ah_isKeyCacheEntryValid = ar5212IsKeyCacheEntryValid, 145185377Ssam .ah_setKeyCacheEntry = ar5212SetKeyCacheEntry, 146185377Ssam .ah_setKeyCacheEntryMac = ar5212SetKeyCacheEntryMac, 147185377Ssam 148185377Ssam /* Power Management Functions */ 149185377Ssam .ah_setPowerMode = ar5212SetPowerMode, 150185377Ssam .ah_getPowerMode = ar5212GetPowerMode, 151185377Ssam 152185377Ssam /* Beacon Functions */ 153185377Ssam .ah_setBeaconTimers = ar5212SetBeaconTimers, 154185377Ssam .ah_beaconInit = ar5212BeaconInit, 155185377Ssam .ah_setStationBeaconTimers = ar5212SetStaBeaconTimers, 156185377Ssam .ah_resetStationBeaconTimers = ar5212ResetStaBeaconTimers, 157225444Sadrian .ah_getNextTBTT = ar5212GetNextTBTT, 158185377Ssam 159185377Ssam /* Interrupt Functions */ 160185377Ssam .ah_isInterruptPending = ar5212IsInterruptPending, 161185377Ssam .ah_getPendingInterrupts = ar5212GetPendingInterrupts, 162185377Ssam .ah_getInterrupts = ar5212GetInterrupts, 163185377Ssam .ah_setInterrupts = ar5212SetInterrupts }, 164185377Ssam 165185377Ssam .ah_getChannelEdges = ar5212GetChannelEdges, 166185377Ssam .ah_getWirelessModes = ar5212GetWirelessModes, 167185377Ssam .ah_eepromRead = ar5212EepromRead, 168185377Ssam#ifdef AH_SUPPORT_WRITE_EEPROM 169185377Ssam .ah_eepromWrite = ar5212EepromWrite, 170185377Ssam#endif 171185377Ssam .ah_getChipPowerLimits = ar5212GetChipPowerLimits, 172185377Ssam}; 173185377Ssam 174185377Ssamuint32_t 175185377Ssamar5212GetRadioRev(struct ath_hal *ah) 176185377Ssam{ 177185377Ssam uint32_t val; 178185377Ssam int i; 179185377Ssam 180185377Ssam /* Read Radio Chip Rev Extract */ 181185377Ssam OS_REG_WRITE(ah, AR_PHY(0x34), 0x00001c16); 182185377Ssam for (i = 0; i < 8; i++) 183185377Ssam OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000); 184185377Ssam val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; 185185377Ssam val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 186185377Ssam return ath_hal_reverseBits(val, 8); 187185377Ssam} 188185377Ssam 189185377Ssamstatic void 190185377Ssamar5212AniSetup(struct ath_hal *ah) 191185377Ssam{ 192185377Ssam static const struct ar5212AniParams aniparams = { 193185377Ssam .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 194185377Ssam .totalSizeDesired = { -55, -55, -55, -55, -62 }, 195185377Ssam .coarseHigh = { -14, -14, -14, -14, -12 }, 196185377Ssam .coarseLow = { -64, -64, -64, -64, -70 }, 197185377Ssam .firpwr = { -78, -78, -78, -78, -80 }, 198185377Ssam .maxSpurImmunityLevel = 2, /* NB: depends on chip rev */ 199185377Ssam .cycPwrThr1 = { 2, 4, 6, 8, 10, 12, 14, 16 }, 200185377Ssam .maxFirstepLevel = 2, /* levels 0..2 */ 201185377Ssam .firstep = { 0, 4, 8 }, 202185377Ssam .ofdmTrigHigh = 500, 203185377Ssam .ofdmTrigLow = 200, 204185377Ssam .cckTrigHigh = 200, 205185377Ssam .cckTrigLow = 100, 206185377Ssam .rssiThrHigh = 40, 207185377Ssam .rssiThrLow = 7, 208185377Ssam .period = 100, 209185377Ssam }; 210185377Ssam if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN) { 211185377Ssam struct ar5212AniParams tmp; 212185377Ssam OS_MEMCPY(&tmp, &aniparams, sizeof(struct ar5212AniParams)); 213185377Ssam tmp.maxSpurImmunityLevel = 7; /* Venice and earlier */ 214185377Ssam ar5212AniAttach(ah, &tmp, &tmp, AH_TRUE); 215185377Ssam } else 216185377Ssam ar5212AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 217222265Sadrian 218222265Sadrian /* Set overridable ANI methods */ 219222265Sadrian AH5212(ah)->ah_aniControl = ar5212AniControl; 220185377Ssam} 221185377Ssam 222185377Ssam/* 223185377Ssam * Attach for an AR5212 part. 224185377Ssam */ 225185377Ssamvoid 226185377Ssamar5212InitState(struct ath_hal_5212 *ahp, uint16_t devid, HAL_SOFTC sc, 227185377Ssam HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) 228185377Ssam{ 229185377Ssam#define N(a) (sizeof(a)/sizeof(a[0])) 230185377Ssam static const uint8_t defbssidmask[IEEE80211_ADDR_LEN] = 231185377Ssam { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 232185377Ssam struct ath_hal *ah; 233185377Ssam 234185377Ssam ah = &ahp->ah_priv.h; 235185377Ssam /* set initial values */ 236185377Ssam OS_MEMCPY(&ahp->ah_priv, &ar5212hal, sizeof(struct ath_hal_private)); 237185377Ssam ah->ah_sc = sc; 238185377Ssam ah->ah_st = st; 239185377Ssam ah->ah_sh = sh; 240185377Ssam 241185377Ssam ah->ah_devid = devid; /* NB: for alq */ 242185377Ssam AH_PRIVATE(ah)->ah_devid = devid; 243185377Ssam AH_PRIVATE(ah)->ah_subvendorid = 0; /* XXX */ 244185377Ssam 245185377Ssam AH_PRIVATE(ah)->ah_powerLimit = MAX_RATE_POWER; 246185377Ssam AH_PRIVATE(ah)->ah_tpScale = HAL_TP_SCALE_MAX; /* no scaling */ 247185377Ssam 248185380Ssam ahp->ah_antControl = HAL_ANT_VARIABLE; 249185380Ssam ahp->ah_diversity = AH_TRUE; 250185377Ssam ahp->ah_bIQCalibration = AH_FALSE; 251185377Ssam /* 252185377Ssam * Enable MIC handling. 253185377Ssam */ 254185377Ssam ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE; 255185377Ssam ahp->ah_rssiThr = INIT_RSSI_THR; 256185377Ssam ahp->ah_tpcEnabled = AH_FALSE; /* disabled by default */ 257185380Ssam ahp->ah_phyPowerOn = AH_FALSE; 258185377Ssam ahp->ah_macTPC = SM(MAX_RATE_POWER, AR_TPC_ACK) 259185377Ssam | SM(MAX_RATE_POWER, AR_TPC_CTS) 260185377Ssam | SM(MAX_RATE_POWER, AR_TPC_CHIRP); 261185377Ssam ahp->ah_beaconInterval = 100; /* XXX [20..1000] */ 262185377Ssam ahp->ah_enable32kHzClock = DONT_USE_32KHZ;/* XXX */ 263185377Ssam ahp->ah_slottime = (u_int) -1; 264185377Ssam ahp->ah_acktimeout = (u_int) -1; 265185377Ssam ahp->ah_ctstimeout = (u_int) -1; 266185377Ssam ahp->ah_sifstime = (u_int) -1; 267204579Srpaulo ahp->ah_txTrigLev = INIT_TX_FIFO_THRESHOLD, 268204579Srpaulo ahp->ah_maxTxTrigLev = MAX_TX_FIFO_THRESHOLD, 269204579Srpaulo 270185377Ssam OS_MEMCPY(&ahp->ah_bssidmask, defbssidmask, IEEE80211_ADDR_LEN); 271185377Ssam#undef N 272185377Ssam} 273185377Ssam 274185377Ssam/* 275185377Ssam * Validate MAC version and revision. 276185377Ssam */ 277185377Ssamstatic HAL_BOOL 278185377Ssamar5212IsMacSupported(uint8_t macVersion, uint8_t macRev) 279185377Ssam{ 280185377Ssam#define N(a) (sizeof(a)/sizeof(a[0])) 281185377Ssam static const struct { 282185377Ssam uint8_t version; 283185377Ssam uint8_t revMin, revMax; 284185377Ssam } macs[] = { 285185377Ssam { AR_SREV_VERSION_VENICE, 286185377Ssam AR_SREV_D2PLUS, AR_SREV_REVISION_MAX }, 287185377Ssam { AR_SREV_VERSION_GRIFFIN, 288185377Ssam AR_SREV_D2PLUS, AR_SREV_REVISION_MAX }, 289185377Ssam { AR_SREV_5413, 290185377Ssam AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 291185377Ssam { AR_SREV_5424, 292185377Ssam AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 293185377Ssam { AR_SREV_2425, 294185377Ssam AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 295185377Ssam { AR_SREV_2417, 296185377Ssam AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 297185377Ssam }; 298185377Ssam int i; 299185377Ssam 300185377Ssam for (i = 0; i < N(macs); i++) 301185377Ssam if (macs[i].version == macVersion && 302185377Ssam macs[i].revMin <= macRev && macRev <= macs[i].revMax) 303185377Ssam return AH_TRUE; 304185377Ssam return AH_FALSE; 305185377Ssam#undef N 306185377Ssam} 307185377Ssam 308185377Ssam/* 309185377Ssam * Attach for an AR5212 part. 310185377Ssam */ 311185406Ssamstatic struct ath_hal * 312185377Ssamar5212Attach(uint16_t devid, HAL_SOFTC sc, 313217624Sadrian HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 314217624Sadrian HAL_STATUS *status) 315185377Ssam{ 316185377Ssam#define AH_EEPROM_PROTECT(ah) \ 317188979Ssam (AH_PRIVATE(ah)->ah_ispcie)? AR_EEPROM_PROTECT_PCIE : AR_EEPROM_PROTECT) 318185377Ssam struct ath_hal_5212 *ahp; 319185377Ssam struct ath_hal *ah; 320185406Ssam struct ath_hal_rf *rf; 321185377Ssam uint32_t val; 322185377Ssam uint16_t eeval; 323185377Ssam HAL_STATUS ecode; 324185377Ssam 325225883Sadrian HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 326185377Ssam __func__, sc, (void*) st, (void*) sh); 327185377Ssam 328185377Ssam /* NB: memory is returned zero'd */ 329185377Ssam ahp = ath_hal_malloc(sizeof (struct ath_hal_5212)); 330185377Ssam if (ahp == AH_NULL) { 331225883Sadrian HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 332185377Ssam "%s: cannot allocate memory for state block\n", __func__); 333185377Ssam *status = HAL_ENOMEM; 334185377Ssam return AH_NULL; 335185377Ssam } 336185377Ssam ar5212InitState(ahp, devid, sc, st, sh, status); 337185377Ssam ah = &ahp->ah_priv.h; 338185377Ssam 339185377Ssam if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 340185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", 341185377Ssam __func__); 342185377Ssam ecode = HAL_EIO; 343185377Ssam goto bad; 344185377Ssam } 345185377Ssam /* Read Revisions from Chips before taking out of reset */ 346185377Ssam val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID; 347185377Ssam AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S; 348185377Ssam AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION; 349188979Ssam AH_PRIVATE(ah)->ah_ispcie = IS_5424(ah) || IS_2425(ah); 350185377Ssam 351185377Ssam if (!ar5212IsMacSupported(AH_PRIVATE(ah)->ah_macVersion, AH_PRIVATE(ah)->ah_macRev)) { 352185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 353185377Ssam "%s: Mac Chip Rev 0x%02x.%x not supported\n" , 354185377Ssam __func__, AH_PRIVATE(ah)->ah_macVersion, 355185377Ssam AH_PRIVATE(ah)->ah_macRev); 356185377Ssam ecode = HAL_ENOTSUPP; 357185377Ssam goto bad; 358185377Ssam } 359185377Ssam 360185377Ssam /* setup common ini data; rf backends handle remainder */ 361185377Ssam HAL_INI_INIT(&ahp->ah_ini_modes, ar5212Modes, 6); 362185377Ssam HAL_INI_INIT(&ahp->ah_ini_common, ar5212Common, 2); 363185377Ssam 364185377Ssam if (!ar5212ChipReset(ah, AH_NULL)) { /* reset chip */ 365185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 366185377Ssam ecode = HAL_EIO; 367185377Ssam goto bad; 368185377Ssam } 369185377Ssam 370185377Ssam AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 371185377Ssam 372188979Ssam if (AH_PRIVATE(ah)->ah_ispcie) { 373185377Ssam /* XXX: build flag to disable this? */ 374235972Sadrian ath_hal_configPCIE(ah, AH_FALSE, AH_FALSE); 375185377Ssam } 376185377Ssam 377185377Ssam if (!ar5212ChipTest(ah)) { 378185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 379185377Ssam __func__); 380185377Ssam ecode = HAL_ESELFTEST; 381185377Ssam goto bad; 382185377Ssam } 383185377Ssam 384185377Ssam /* Enable PCI core retry fix in software for Hainan and up */ 385185377Ssam if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_VENICE) 386185377Ssam OS_REG_SET_BIT(ah, AR_PCICFG, AR_PCICFG_RETRYFIXEN); 387185377Ssam 388185377Ssam /* 389185377Ssam * Set correct Baseband to analog shift 390185377Ssam * setting to access analog chips. 391185377Ssam */ 392185377Ssam OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 393185377Ssam 394185377Ssam /* Read Radio Chip Rev Extract */ 395185377Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah); 396185406Ssam 397185406Ssam rf = ath_hal_rfprobe(ah, &ecode); 398185406Ssam if (rf == AH_NULL) 399185406Ssam goto bad; 400185406Ssam 401185377Ssam /* NB: silently accept anything in release code per Atheros */ 402185377Ssam switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 403185377Ssam case AR_RAD5111_SREV_MAJOR: 404185377Ssam case AR_RAD5112_SREV_MAJOR: 405185377Ssam case AR_RAD2112_SREV_MAJOR: 406185377Ssam case AR_RAD2111_SREV_MAJOR: 407185377Ssam case AR_RAD2413_SREV_MAJOR: 408185377Ssam case AR_RAD5413_SREV_MAJOR: 409185377Ssam case AR_RAD5424_SREV_MAJOR: 410185377Ssam break; 411185377Ssam default: 412185377Ssam if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 413185377Ssam /* 414185377Ssam * When RF_Silent is used, the 415185377Ssam * analog chip is reset. So when the system boots 416185377Ssam * up with the radio switch off we cannot determine 417185377Ssam * the RF chip rev. To workaround this check the 418185377Ssam * mac+phy revs and if Hainan, set the radio rev 419185377Ssam * to Derby. 420185377Ssam */ 421185377Ssam if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE && 422185377Ssam AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN && 423185377Ssam AH_PRIVATE(ah)->ah_phyRev == AR_PHYREV_HAINAN) { 424185377Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = AR_ANALOG5REV_HAINAN; 425185377Ssam break; 426185377Ssam } 427185377Ssam if (IS_2413(ah)) { /* Griffin */ 428185380Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = 429185380Ssam AR_RAD2413_SREV_MAJOR | 0x1; 430185377Ssam break; 431185377Ssam } 432185377Ssam if (IS_5413(ah)) { /* Eagle */ 433185380Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = 434185380Ssam AR_RAD5413_SREV_MAJOR | 0x2; 435185377Ssam break; 436185377Ssam } 437185377Ssam if (IS_2425(ah) || IS_2417(ah)) {/* Swan or Nala */ 438185380Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = 439185380Ssam AR_RAD5424_SREV_MAJOR | 0x2; 440185377Ssam break; 441185377Ssam } 442185377Ssam } 443185377Ssam#ifdef AH_DEBUG 444185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 445185377Ssam "%s: 5G Radio Chip Rev 0x%02X is not supported by " 446185377Ssam "this driver\n", 447185377Ssam __func__, AH_PRIVATE(ah)->ah_analog5GhzRev); 448185377Ssam ecode = HAL_ENOTSUPP; 449185377Ssam goto bad; 450185377Ssam#endif 451185377Ssam } 452185380Ssam if (IS_RAD5112_REV1(ah)) { 453185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 454185377Ssam "%s: 5112 Rev 1 is not supported by this " 455185377Ssam "driver (analog5GhzRev 0x%x)\n", __func__, 456185377Ssam AH_PRIVATE(ah)->ah_analog5GhzRev); 457185377Ssam ecode = HAL_ENOTSUPP; 458185377Ssam goto bad; 459185377Ssam } 460185377Ssam 461185377Ssam val = OS_REG_READ(ah, AR_PCICFG); 462185377Ssam val = MS(val, AR_PCICFG_EEPROM_SIZE); 463185377Ssam if (val == 0) { 464188979Ssam if (!AH_PRIVATE(ah)->ah_ispcie) { 465185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 466185377Ssam "%s: unsupported EEPROM size %u (0x%x) found\n", 467185377Ssam __func__, val, val); 468185377Ssam ecode = HAL_EESIZE; 469185377Ssam goto bad; 470185377Ssam } 471185377Ssam /* XXX AH_PRIVATE(ah)->ah_isPciExpress = AH_TRUE; */ 472185377Ssam } else if (val != AR_PCICFG_EEPROM_SIZE_16K) { 473185377Ssam if (AR_PCICFG_EEPROM_SIZE_FAILED == val) { 474185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 475185377Ssam "%s: unsupported EEPROM size %u (0x%x) found\n", 476185377Ssam __func__, val, val); 477185377Ssam ecode = HAL_EESIZE; 478185377Ssam goto bad; 479185377Ssam } 480185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 481185377Ssam "%s: EEPROM size = %d. Must be %d (16k).\n", 482185377Ssam __func__, val, AR_PCICFG_EEPROM_SIZE_16K); 483185377Ssam ecode = HAL_EESIZE; 484185377Ssam goto bad; 485185377Ssam } 486185377Ssam ecode = ath_hal_legacyEepromAttach(ah); 487185377Ssam if (ecode != HAL_OK) { 488185377Ssam goto bad; 489185377Ssam } 490185377Ssam ahp->ah_isHb63 = IS_2425(ah) && ath_hal_eepromGetFlag(ah, AR_EEP_ISTALON); 491185377Ssam 492185377Ssam /* 493185377Ssam * If Bmode and AR5212, verify 2.4 analog exists 494185377Ssam */ 495185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) && 496185377Ssam (AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD5111_SREV_MAJOR) { 497185377Ssam /* 498185377Ssam * Set correct Baseband to analog shift 499185377Ssam * setting to access analog chips. 500185377Ssam */ 501185377Ssam OS_REG_WRITE(ah, AR_PHY(0), 0x00004007); 502185377Ssam OS_DELAY(2000); 503185377Ssam AH_PRIVATE(ah)->ah_analog2GhzRev = ar5212GetRadioRev(ah); 504185377Ssam 505185377Ssam /* Set baseband for 5GHz chip */ 506185377Ssam OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 507185377Ssam OS_DELAY(2000); 508185377Ssam if ((AH_PRIVATE(ah)->ah_analog2GhzRev & 0xF0) != AR_RAD2111_SREV_MAJOR) { 509185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 510185377Ssam "%s: 2G Radio Chip Rev 0x%02X is not " 511185377Ssam "supported by this driver\n", __func__, 512185377Ssam AH_PRIVATE(ah)->ah_analog2GhzRev); 513185377Ssam ecode = HAL_ENOTSUPP; 514185377Ssam goto bad; 515185377Ssam } 516185377Ssam } 517185377Ssam 518185377Ssam ecode = ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, &eeval); 519185377Ssam if (ecode != HAL_OK) { 520185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 521185377Ssam "%s: cannot read regulatory domain from EEPROM\n", 522185377Ssam __func__); 523185377Ssam goto bad; 524185377Ssam } 525185377Ssam AH_PRIVATE(ah)->ah_currentRD = eeval; 526185377Ssam /* XXX record serial number */ 527185377Ssam 528185377Ssam /* 529185377Ssam * Got everything we need now to setup the capabilities. 530185377Ssam */ 531185377Ssam if (!ar5212FillCapabilityInfo(ah)) { 532185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 533185377Ssam "%s: failed ar5212FillCapabilityInfo\n", __func__); 534185377Ssam ecode = HAL_EEREAD; 535185377Ssam goto bad; 536185377Ssam } 537185377Ssam 538185406Ssam if (!rf->attach(ah, &ecode)) { 539185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 540185377Ssam __func__, ecode); 541185377Ssam goto bad; 542185377Ssam } 543185377Ssam /* 544185377Ssam * Set noise floor adjust method; we arrange a 545185377Ssam * direct call instead of thunking. 546185377Ssam */ 547185377Ssam AH_PRIVATE(ah)->ah_getNfAdjust = ahp->ah_rfHal->getNfAdjust; 548185377Ssam 549185377Ssam /* Initialize gain ladder thermal calibration structure */ 550185377Ssam ar5212InitializeGainValues(ah); 551185377Ssam 552185377Ssam ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 553185377Ssam if (ecode != HAL_OK) { 554185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 555185377Ssam "%s: error getting mac address from EEPROM\n", __func__); 556185377Ssam goto bad; 557185377Ssam } 558185377Ssam 559185377Ssam ar5212AniSetup(ah); 560185377Ssam /* Setup of Radar/AR structures happens in ath_hal_initchannels*/ 561185377Ssam ar5212InitNfCalHistBuffer(ah); 562185377Ssam 563185377Ssam /* XXX EAR stuff goes here */ 564185377Ssam 565185377Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 566185377Ssam 567185377Ssam return ah; 568185377Ssam 569185377Ssambad: 570185377Ssam if (ahp) 571185377Ssam ar5212Detach((struct ath_hal *) ahp); 572185377Ssam if (status) 573185377Ssam *status = ecode; 574185377Ssam return AH_NULL; 575185377Ssam#undef AH_EEPROM_PROTECT 576185377Ssam} 577185377Ssam 578185377Ssamvoid 579185377Ssamar5212Detach(struct ath_hal *ah) 580185377Ssam{ 581185377Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__); 582185377Ssam 583185377Ssam HALASSERT(ah != AH_NULL); 584185377Ssam HALASSERT(ah->ah_magic == AR5212_MAGIC); 585185377Ssam 586185377Ssam ar5212AniDetach(ah); 587185377Ssam ar5212RfDetach(ah); 588185377Ssam ar5212Disable(ah); 589185377Ssam ar5212SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); 590185377Ssam 591185377Ssam ath_hal_eepromDetach(ah); 592185377Ssam ath_hal_free(ah); 593185377Ssam} 594185377Ssam 595185377SsamHAL_BOOL 596185377Ssamar5212ChipTest(struct ath_hal *ah) 597185377Ssam{ 598185377Ssam uint32_t regAddr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) }; 599185377Ssam uint32_t regHold[2]; 600185377Ssam uint32_t patternData[4] = 601185377Ssam { 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 }; 602185377Ssam int i, j; 603185377Ssam 604185377Ssam /* Test PHY & MAC registers */ 605185377Ssam for (i = 0; i < 2; i++) { 606185377Ssam uint32_t addr = regAddr[i]; 607185377Ssam uint32_t wrData, rdData; 608185377Ssam 609185377Ssam regHold[i] = OS_REG_READ(ah, addr); 610185377Ssam for (j = 0; j < 0x100; j++) { 611185377Ssam wrData = (j << 16) | j; 612185377Ssam OS_REG_WRITE(ah, addr, wrData); 613185377Ssam rdData = OS_REG_READ(ah, addr); 614185377Ssam if (rdData != wrData) { 615185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 616185377Ssam"%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 617185377Ssam __func__, addr, wrData, rdData); 618185377Ssam return AH_FALSE; 619185377Ssam } 620185377Ssam } 621185377Ssam for (j = 0; j < 4; j++) { 622185377Ssam wrData = patternData[j]; 623185377Ssam OS_REG_WRITE(ah, addr, wrData); 624185377Ssam rdData = OS_REG_READ(ah, addr); 625185377Ssam if (wrData != rdData) { 626185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 627185377Ssam"%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 628185377Ssam __func__, addr, wrData, rdData); 629185377Ssam return AH_FALSE; 630185377Ssam } 631185377Ssam } 632185377Ssam OS_REG_WRITE(ah, regAddr[i], regHold[i]); 633185377Ssam } 634185377Ssam OS_DELAY(100); 635185377Ssam return AH_TRUE; 636185377Ssam} 637185377Ssam 638185377Ssam/* 639185377Ssam * Store the channel edges for the requested operational mode 640185377Ssam */ 641185377SsamHAL_BOOL 642185377Ssamar5212GetChannelEdges(struct ath_hal *ah, 643185377Ssam uint16_t flags, uint16_t *low, uint16_t *high) 644185377Ssam{ 645187831Ssam if (flags & IEEE80211_CHAN_5GHZ) { 646185377Ssam *low = 4915; 647185377Ssam *high = 6100; 648185377Ssam return AH_TRUE; 649185377Ssam } 650187831Ssam if ((flags & IEEE80211_CHAN_2GHZ) && 651185377Ssam (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) || 652185377Ssam ath_hal_eepromGetFlag(ah, AR_EEP_GMODE))) { 653185377Ssam *low = 2312; 654185377Ssam *high = 2732; 655185377Ssam return AH_TRUE; 656185377Ssam } 657185377Ssam return AH_FALSE; 658185377Ssam} 659185377Ssam 660185377Ssam/* 661188979Ssam * Disable PLL when in L0s as well as receiver clock when in L1. 662188979Ssam * This power saving option must be enabled through the Serdes. 663188979Ssam * 664188979Ssam * Programming the Serdes must go through the same 288 bit serial shift 665188979Ssam * register as the other analog registers. Hence the 9 writes. 666188979Ssam * 667188979Ssam * XXX Clean up the magic numbers. 668188979Ssam */ 669188979Ssamstatic void 670235972Sadrianar5212ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off) 671188979Ssam{ 672188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 673188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 674188979Ssam 675188979Ssam /* RX shut off when elecidle is asserted */ 676188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039); 677188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824); 678188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579); 679188979Ssam 680188979Ssam /* Shut off PLL and CLKREQ active in L1 */ 681188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff); 682188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 683188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 684188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007); 685188979Ssam 686188979Ssam /* Load the new settings */ 687188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 688188979Ssam} 689188979Ssam 690188979Ssamstatic void 691188979Ssamar5212DisablePCIE(struct ath_hal *ah) 692188979Ssam{ 693188979Ssam /* NB: fill in for 9100 */ 694188979Ssam} 695188979Ssam 696188979Ssam/* 697185377Ssam * Fill all software cached or static hardware state information. 698185377Ssam * Return failure if capabilities are to come from EEPROM and 699185377Ssam * cannot be read. 700185377Ssam */ 701185377SsamHAL_BOOL 702185377Ssamar5212FillCapabilityInfo(struct ath_hal *ah) 703185377Ssam{ 704185377Ssam#define AR_KEYTABLE_SIZE 128 705185377Ssam#define IS_GRIFFIN_LITE(ah) \ 706185377Ssam (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_GRIFFIN && \ 707185377Ssam AH_PRIVATE(ah)->ah_macRev == AR_SREV_GRIFFIN_LITE) 708185377Ssam#define IS_COBRA(ah) \ 709185377Ssam (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_COBRA) 710185377Ssam#define IS_2112(ah) \ 711185377Ssam ((AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD2112_SREV_MAJOR) 712185377Ssam 713185377Ssam struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 714185377Ssam HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 715185377Ssam uint16_t capField, val; 716185377Ssam 717185377Ssam /* Read the capability EEPROM location */ 718185377Ssam if (ath_hal_eepromGet(ah, AR_EEP_OPCAP, &capField) != HAL_OK) { 719185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 720185377Ssam "%s: unable to read caps from eeprom\n", __func__); 721185377Ssam return AH_FALSE; 722185377Ssam } 723185377Ssam if (IS_2112(ah)) 724185377Ssam ath_hal_eepromSet(ah, AR_EEP_AMODE, AH_FALSE); 725185377Ssam if (capField == 0 && IS_GRIFFIN_LITE(ah)) { 726185377Ssam /* 727185377Ssam * For griffin-lite cards with unprogrammed capabilities. 728185377Ssam */ 729185377Ssam ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE); 730185377Ssam ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE); 731185377Ssam ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE); 732185377Ssam ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE); 733185377Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, 734185377Ssam "%s: override caps for griffin-lite, now 0x%x (+!turbo)\n", 735185377Ssam __func__, capField); 736185377Ssam } 737185377Ssam 738185377Ssam /* Modify reg domain on newer cards that need to work with older sw */ 739185377Ssam if (ahpriv->ah_opmode != HAL_M_HOSTAP && 740185377Ssam ahpriv->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) { 741185377Ssam if (ahpriv->ah_currentRD == 0x64 || 742185377Ssam ahpriv->ah_currentRD == 0x65) 743185377Ssam ahpriv->ah_currentRD += 5; 744185377Ssam else if (ahpriv->ah_currentRD == 0x41) 745185377Ssam ahpriv->ah_currentRD = 0x43; 746185377Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: regdomain mapped to 0x%x\n", 747185377Ssam __func__, ahpriv->ah_currentRD); 748185377Ssam } 749185377Ssam 750185377Ssam if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2417 || 751185377Ssam AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2425) { 752185377Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, 753185377Ssam "%s: enable Bmode and disable turbo for Swan/Nala\n", 754185377Ssam __func__); 755185377Ssam ath_hal_eepromSet(ah, AR_EEP_BMODE, AH_TRUE); 756185377Ssam ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE); 757185377Ssam ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE); 758185377Ssam ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE); 759185377Ssam ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE); 760185377Ssam } 761185377Ssam 762185377Ssam /* Construct wireless mode from EEPROM */ 763185377Ssam pCap->halWirelessModes = 0; 764185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) { 765185377Ssam pCap->halWirelessModes |= HAL_MODE_11A; 766185377Ssam if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO5DISABLE)) 767185377Ssam pCap->halWirelessModes |= HAL_MODE_TURBO; 768185377Ssam } 769185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE)) 770185377Ssam pCap->halWirelessModes |= HAL_MODE_11B; 771185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE) && 772185377Ssam ahpriv->ah_subvendorid != AR_SUBVENDOR_ID_NOG) { 773185377Ssam pCap->halWirelessModes |= HAL_MODE_11G; 774185377Ssam if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO2DISABLE)) 775185377Ssam pCap->halWirelessModes |= HAL_MODE_108G; 776185377Ssam } 777185377Ssam 778185377Ssam pCap->halLow2GhzChan = 2312; 779185380Ssam /* XXX 2417 too? */ 780185380Ssam if (IS_RAD5112_ANY(ah) || IS_5413(ah) || IS_2425(ah) || IS_2417(ah)) 781185377Ssam pCap->halHigh2GhzChan = 2500; 782185377Ssam else 783185377Ssam pCap->halHigh2GhzChan = 2732; 784185377Ssam 785185377Ssam pCap->halLow5GhzChan = 4915; 786185377Ssam pCap->halHigh5GhzChan = 6100; 787185377Ssam 788185377Ssam pCap->halCipherCkipSupport = AH_FALSE; 789185377Ssam pCap->halCipherTkipSupport = AH_TRUE; 790185377Ssam pCap->halCipherAesCcmSupport = 791185377Ssam (ath_hal_eepromGetFlag(ah, AR_EEP_AES) && 792185377Ssam ((AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE) || 793185377Ssam ((AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE) && 794185377Ssam (AH_PRIVATE(ah)->ah_macRev >= AR_SREV_VERSION_OAHU)))); 795185377Ssam 796185377Ssam pCap->halMicCkipSupport = AH_FALSE; 797185377Ssam pCap->halMicTkipSupport = AH_TRUE; 798185377Ssam pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 799185377Ssam /* 800185377Ssam * Starting with Griffin TX+RX mic keys can be combined 801185377Ssam * in one key cache slot. 802185377Ssam */ 803185377Ssam if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_GRIFFIN) 804185377Ssam pCap->halTkipMicTxRxKeySupport = AH_TRUE; 805185377Ssam else 806185377Ssam pCap->halTkipMicTxRxKeySupport = AH_FALSE; 807185377Ssam pCap->halChanSpreadSupport = AH_TRUE; 808185377Ssam pCap->halSleepAfterBeaconBroken = AH_TRUE; 809185377Ssam 810185377Ssam if (ahpriv->ah_macRev > 1 || IS_COBRA(ah)) { 811185377Ssam pCap->halCompressSupport = 812185377Ssam ath_hal_eepromGetFlag(ah, AR_EEP_COMPRESS) && 813185377Ssam (pCap->halWirelessModes & (HAL_MODE_11A|HAL_MODE_11G)) != 0; 814185377Ssam pCap->halBurstSupport = ath_hal_eepromGetFlag(ah, AR_EEP_BURST); 815185377Ssam pCap->halFastFramesSupport = 816185377Ssam ath_hal_eepromGetFlag(ah, AR_EEP_FASTFRAME) && 817185377Ssam (pCap->halWirelessModes & (HAL_MODE_11A|HAL_MODE_11G)) != 0; 818185377Ssam pCap->halChapTuningSupport = AH_TRUE; 819185377Ssam pCap->halTurboPrimeSupport = AH_TRUE; 820185377Ssam } 821185377Ssam pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G; 822185377Ssam 823185377Ssam pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */ 824185377Ssam pCap->halVEOLSupport = AH_TRUE; 825185377Ssam pCap->halBssIdMaskSupport = AH_TRUE; 826185377Ssam pCap->halMcastKeySrchSupport = AH_TRUE; 827185377Ssam if ((ahpriv->ah_macVersion == AR_SREV_VERSION_VENICE && 828185377Ssam ahpriv->ah_macRev == 8) || 829185377Ssam ahpriv->ah_macVersion > AR_SREV_VERSION_VENICE) 830185377Ssam pCap->halTsfAddSupport = AH_TRUE; 831185377Ssam 832185377Ssam if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK) 833185377Ssam pCap->halTotalQueues = val; 834185377Ssam else 835185377Ssam pCap->halTotalQueues = HAL_NUM_TX_QUEUES; 836185377Ssam 837185377Ssam if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK) 838185377Ssam pCap->halKeyCacheSize = val; 839185377Ssam else 840185377Ssam pCap->halKeyCacheSize = AR_KEYTABLE_SIZE; 841185377Ssam 842185380Ssam pCap->halChanHalfRate = AH_TRUE; 843185380Ssam pCap->halChanQuarterRate = AH_TRUE; 844185377Ssam 845230791Sadrian /* 846230791Sadrian * RSSI uses the combined field; some 11n NICs may use 847230791Sadrian * the control chain RSSI. 848230791Sadrian */ 849230791Sadrian pCap->halUseCombinedRadarRssi = AH_TRUE; 850230791Sadrian 851185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) && 852185377Ssam ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) { 853185377Ssam /* NB: enabled by default */ 854185377Ssam ahpriv->ah_rfkillEnabled = AH_TRUE; 855185377Ssam pCap->halRfSilentSupport = AH_TRUE; 856185377Ssam } 857185377Ssam 858185377Ssam /* NB: this is a guess, noone seems to know the answer */ 859185377Ssam ahpriv->ah_rxornIsFatal = 860185377Ssam (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_VENICE); 861185377Ssam 862195114Ssam /* enable features that first appeared in Hainan */ 863195114Ssam if ((AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE && 864185377Ssam AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN) || 865195114Ssam AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE) { 866195114Ssam /* h/w phy counters */ 867195114Ssam pCap->halHwPhyCounterSupport = AH_TRUE; 868195114Ssam /* bssid match disable */ 869195114Ssam pCap->halBssidMatchSupport = AH_TRUE; 870195114Ssam } 871185377Ssam 872185377Ssam pCap->halTstampPrecision = 15; 873192396Ssam pCap->halIntrMask = HAL_INT_COMMON 874192396Ssam | HAL_INT_RX 875192396Ssam | HAL_INT_TX 876192396Ssam | HAL_INT_FATAL 877192396Ssam | HAL_INT_BNR 878192396Ssam | HAL_INT_BMISC 879192396Ssam ; 880192400Ssam if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN) 881192400Ssam pCap->halIntrMask &= ~HAL_INT_TBTT; 882185377Ssam 883218436Sadrian pCap->hal4kbSplitTransSupport = AH_TRUE; 884220324Sadrian pCap->halHasRxSelfLinkedTail = AH_TRUE; 885218436Sadrian 886185377Ssam return AH_TRUE; 887185377Ssam#undef IS_COBRA 888185377Ssam#undef IS_GRIFFIN_LITE 889185377Ssam#undef AR_KEYTABLE_SIZE 890185377Ssam} 891185406Ssam 892185406Ssamstatic const char* 893185406Ssamar5212Probe(uint16_t vendorid, uint16_t devid) 894185406Ssam{ 895185406Ssam if (vendorid == ATHEROS_VENDOR_ID || 896185406Ssam vendorid == ATHEROS_3COM_VENDOR_ID || 897185406Ssam vendorid == ATHEROS_3COM2_VENDOR_ID) { 898185406Ssam switch (devid) { 899185406Ssam case AR5212_FPGA: 900185406Ssam return "Atheros 5212 (FPGA)"; 901185406Ssam case AR5212_DEVID: 902185406Ssam case AR5212_DEVID_IBM: 903185406Ssam case AR5212_DEFAULT: 904185406Ssam return "Atheros 5212"; 905185406Ssam case AR5212_AR2413: 906185406Ssam return "Atheros 2413"; 907185406Ssam case AR5212_AR2417: 908185406Ssam return "Atheros 2417"; 909185406Ssam case AR5212_AR5413: 910185406Ssam return "Atheros 5413"; 911185406Ssam case AR5212_AR5424: 912185406Ssam return "Atheros 5424/2424"; 913185406Ssam } 914185406Ssam } 915185406Ssam return AH_NULL; 916185406Ssam} 917185418SsamAH_CHIP(AR5212, ar5212Probe, ar5212Attach); 918