1185377Ssam/* 2187831Ssam * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2002-2008 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17187831Ssam * $FreeBSD$ 18185377Ssam */ 19185377Ssam#include "opt_ah.h" 20185377Ssam 21185377Ssam#include "ah.h" 22185377Ssam#include "ah_internal.h" 23185377Ssam#include "ah_devid.h" 24185377Ssam 25185377Ssam#include "ar5212/ar5212.h" 26185377Ssam#include "ar5212/ar5212reg.h" 27185377Ssam#include "ar5212/ar5212phy.h" 28185377Ssam 29185377Ssam#define AH_5212_COMMON 30185377Ssam#include "ar5212/ar5212.ini" 31185377Ssam 32235972Sadrianstatic void ar5212ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, 33235972Sadrian HAL_BOOL power_off); 34188979Ssamstatic void ar5212DisablePCIE(struct ath_hal *ah); 35188979Ssam 36185377Ssamstatic const struct ath_hal_private ar5212hal = {{ 37185377Ssam .ah_magic = AR5212_MAGIC, 38185377Ssam 39185377Ssam .ah_getRateTable = ar5212GetRateTable, 40185377Ssam .ah_detach = ar5212Detach, 41185377Ssam 42185377Ssam /* Reset Functions */ 43185377Ssam .ah_reset = ar5212Reset, 44185377Ssam .ah_phyDisable = ar5212PhyDisable, 45185377Ssam .ah_disable = ar5212Disable, 46188979Ssam .ah_configPCIE = ar5212ConfigPCIE, 47188979Ssam .ah_disablePCIE = ar5212DisablePCIE, 48185377Ssam .ah_setPCUConfig = ar5212SetPCUConfig, 49185377Ssam .ah_perCalibration = ar5212PerCalibration, 50185380Ssam .ah_perCalibrationN = ar5212PerCalibrationN, 51185380Ssam .ah_resetCalValid = ar5212ResetCalValid, 52185377Ssam .ah_setTxPowerLimit = ar5212SetTxPowerLimit, 53185377Ssam .ah_getChanNoise = ath_hal_getChanNoise, 54185377Ssam 55185377Ssam /* Transmit functions */ 56185377Ssam .ah_updateTxTrigLevel = ar5212UpdateTxTrigLevel, 57185377Ssam .ah_setupTxQueue = ar5212SetupTxQueue, 58185377Ssam .ah_setTxQueueProps = ar5212SetTxQueueProps, 59185377Ssam .ah_getTxQueueProps = ar5212GetTxQueueProps, 60185377Ssam .ah_releaseTxQueue = ar5212ReleaseTxQueue, 61185377Ssam .ah_resetTxQueue = ar5212ResetTxQueue, 62185377Ssam .ah_getTxDP = ar5212GetTxDP, 63185377Ssam .ah_setTxDP = ar5212SetTxDP, 64185377Ssam .ah_numTxPending = ar5212NumTxPending, 65185377Ssam .ah_startTxDma = ar5212StartTxDma, 66185377Ssam .ah_stopTxDma = ar5212StopTxDma, 67185377Ssam .ah_setupTxDesc = ar5212SetupTxDesc, 68185377Ssam .ah_setupXTxDesc = ar5212SetupXTxDesc, 69185377Ssam .ah_fillTxDesc = ar5212FillTxDesc, 70185377Ssam .ah_procTxDesc = ar5212ProcTxDesc, 71185377Ssam .ah_getTxIntrQueue = ar5212GetTxIntrQueue, 72185377Ssam .ah_reqTxIntrDesc = ar5212IntrReqTxDesc, 73217621Sadrian .ah_getTxCompletionRates = ar5212GetTxCompletionRates, 74238607Sadrian .ah_setTxDescLink = ar5212SetTxDescLink, 75238607Sadrian .ah_getTxDescLink = ar5212GetTxDescLink, 76238607Sadrian .ah_getTxDescLinkPtr = ar5212GetTxDescLinkPtr, 77185377Ssam 78185377Ssam /* RX Functions */ 79185377Ssam .ah_getRxDP = ar5212GetRxDP, 80185377Ssam .ah_setRxDP = ar5212SetRxDP, 81185377Ssam .ah_enableReceive = ar5212EnableReceive, 82185377Ssam .ah_stopDmaReceive = ar5212StopDmaReceive, 83185377Ssam .ah_startPcuReceive = ar5212StartPcuReceive, 84185377Ssam .ah_stopPcuReceive = ar5212StopPcuReceive, 85185377Ssam .ah_setMulticastFilter = ar5212SetMulticastFilter, 86185377Ssam .ah_setMulticastFilterIndex = ar5212SetMulticastFilterIndex, 87185377Ssam .ah_clrMulticastFilterIndex = ar5212ClrMulticastFilterIndex, 88185377Ssam .ah_getRxFilter = ar5212GetRxFilter, 89185377Ssam .ah_setRxFilter = ar5212SetRxFilter, 90185377Ssam .ah_setupRxDesc = ar5212SetupRxDesc, 91185377Ssam .ah_procRxDesc = ar5212ProcRxDesc, 92217684Sadrian .ah_rxMonitor = ar5212RxMonitor, 93217684Sadrian .ah_aniPoll = ar5212AniPoll, 94185377Ssam .ah_procMibEvent = ar5212ProcessMibIntr, 95185377Ssam 96185377Ssam /* Misc Functions */ 97185377Ssam .ah_getCapability = ar5212GetCapability, 98185377Ssam .ah_setCapability = ar5212SetCapability, 99185377Ssam .ah_getDiagState = ar5212GetDiagState, 100185377Ssam .ah_getMacAddress = ar5212GetMacAddress, 101185377Ssam .ah_setMacAddress = ar5212SetMacAddress, 102185377Ssam .ah_getBssIdMask = ar5212GetBssIdMask, 103185377Ssam .ah_setBssIdMask = ar5212SetBssIdMask, 104185380Ssam .ah_setRegulatoryDomain = ar5212SetRegulatoryDomain, 105185377Ssam .ah_setLedState = ar5212SetLedState, 106185377Ssam .ah_writeAssocid = ar5212WriteAssocid, 107185377Ssam .ah_gpioCfgInput = ar5212GpioCfgInput, 108185377Ssam .ah_gpioCfgOutput = ar5212GpioCfgOutput, 109185377Ssam .ah_gpioGet = ar5212GpioGet, 110185377Ssam .ah_gpioSet = ar5212GpioSet, 111185377Ssam .ah_gpioSetIntr = ar5212GpioSetIntr, 112185377Ssam .ah_getTsf32 = ar5212GetTsf32, 113185377Ssam .ah_getTsf64 = ar5212GetTsf64, 114243424Sadrian .ah_setTsf64 = ar5212SetTsf64, 115185377Ssam .ah_resetTsf = ar5212ResetTsf, 116185377Ssam .ah_detectCardPresent = ar5212DetectCardPresent, 117185377Ssam .ah_updateMibCounters = ar5212UpdateMibCounters, 118185377Ssam .ah_getRfGain = ar5212GetRfgain, 119185377Ssam .ah_getDefAntenna = ar5212GetDefAntenna, 120185377Ssam .ah_setDefAntenna = ar5212SetDefAntenna, 121185377Ssam .ah_getAntennaSwitch = ar5212GetAntennaSwitch, 122185377Ssam .ah_setAntennaSwitch = ar5212SetAntennaSwitch, 123185377Ssam .ah_setSifsTime = ar5212SetSifsTime, 124185377Ssam .ah_getSifsTime = ar5212GetSifsTime, 125185377Ssam .ah_setSlotTime = ar5212SetSlotTime, 126185377Ssam .ah_getSlotTime = ar5212GetSlotTime, 127185377Ssam .ah_setAckTimeout = ar5212SetAckTimeout, 128185377Ssam .ah_getAckTimeout = ar5212GetAckTimeout, 129185377Ssam .ah_setAckCTSRate = ar5212SetAckCTSRate, 130185377Ssam .ah_getAckCTSRate = ar5212GetAckCTSRate, 131185377Ssam .ah_setCTSTimeout = ar5212SetCTSTimeout, 132185377Ssam .ah_getCTSTimeout = ar5212GetCTSTimeout, 133234873Sadrian .ah_setDecompMask = ar5212SetDecompMask, 134234873Sadrian .ah_setCoverageClass = ar5212SetCoverageClass, 135222644Sadrian .ah_setQuiet = ar5212SetQuiet, 136234873Sadrian .ah_getMibCycleCounts = ar5212GetMibCycleCounts, 137247286Sadrian .ah_setChainMasks = ar5212SetChainMasks, 138185377Ssam 139222584Sadrian /* DFS Functions */ 140222584Sadrian .ah_enableDfs = ar5212EnableDfs, 141222584Sadrian .ah_getDfsThresh = ar5212GetDfsThresh, 142239642Sadrian .ah_getDfsDefaultThresh = ar5212GetDfsDefaultThresh, 143222815Sadrian .ah_procRadarEvent = ar5212ProcessRadarEvent, 144224709Sadrian .ah_isFastClockEnabled = ar5212IsFastClockEnabled, 145230791Sadrian .ah_get11nExtBusy = ar5212Get11nExtBusy, 146222584Sadrian 147185377Ssam /* Key Cache Functions */ 148185377Ssam .ah_getKeyCacheSize = ar5212GetKeyCacheSize, 149185377Ssam .ah_resetKeyCacheEntry = ar5212ResetKeyCacheEntry, 150185377Ssam .ah_isKeyCacheEntryValid = ar5212IsKeyCacheEntryValid, 151185377Ssam .ah_setKeyCacheEntry = ar5212SetKeyCacheEntry, 152185377Ssam .ah_setKeyCacheEntryMac = ar5212SetKeyCacheEntryMac, 153185377Ssam 154185377Ssam /* Power Management Functions */ 155185377Ssam .ah_setPowerMode = ar5212SetPowerMode, 156185377Ssam .ah_getPowerMode = ar5212GetPowerMode, 157185377Ssam 158185377Ssam /* Beacon Functions */ 159185377Ssam .ah_setBeaconTimers = ar5212SetBeaconTimers, 160185377Ssam .ah_beaconInit = ar5212BeaconInit, 161185377Ssam .ah_setStationBeaconTimers = ar5212SetStaBeaconTimers, 162185377Ssam .ah_resetStationBeaconTimers = ar5212ResetStaBeaconTimers, 163225444Sadrian .ah_getNextTBTT = ar5212GetNextTBTT, 164185377Ssam 165185377Ssam /* Interrupt Functions */ 166185377Ssam .ah_isInterruptPending = ar5212IsInterruptPending, 167185377Ssam .ah_getPendingInterrupts = ar5212GetPendingInterrupts, 168185377Ssam .ah_getInterrupts = ar5212GetInterrupts, 169185377Ssam .ah_setInterrupts = ar5212SetInterrupts }, 170185377Ssam 171185377Ssam .ah_getChannelEdges = ar5212GetChannelEdges, 172185377Ssam .ah_getWirelessModes = ar5212GetWirelessModes, 173185377Ssam .ah_eepromRead = ar5212EepromRead, 174185377Ssam#ifdef AH_SUPPORT_WRITE_EEPROM 175185377Ssam .ah_eepromWrite = ar5212EepromWrite, 176185377Ssam#endif 177185377Ssam .ah_getChipPowerLimits = ar5212GetChipPowerLimits, 178185377Ssam}; 179185377Ssam 180185377Ssamuint32_t 181185377Ssamar5212GetRadioRev(struct ath_hal *ah) 182185377Ssam{ 183185377Ssam uint32_t val; 184185377Ssam int i; 185185377Ssam 186185377Ssam /* Read Radio Chip Rev Extract */ 187185377Ssam OS_REG_WRITE(ah, AR_PHY(0x34), 0x00001c16); 188185377Ssam for (i = 0; i < 8; i++) 189185377Ssam OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000); 190185377Ssam val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; 191185377Ssam val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 192185377Ssam return ath_hal_reverseBits(val, 8); 193185377Ssam} 194185377Ssam 195185377Ssamstatic void 196185377Ssamar5212AniSetup(struct ath_hal *ah) 197185377Ssam{ 198185377Ssam static const struct ar5212AniParams aniparams = { 199185377Ssam .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 200185377Ssam .totalSizeDesired = { -55, -55, -55, -55, -62 }, 201185377Ssam .coarseHigh = { -14, -14, -14, -14, -12 }, 202185377Ssam .coarseLow = { -64, -64, -64, -64, -70 }, 203185377Ssam .firpwr = { -78, -78, -78, -78, -80 }, 204185377Ssam .maxSpurImmunityLevel = 2, /* NB: depends on chip rev */ 205185377Ssam .cycPwrThr1 = { 2, 4, 6, 8, 10, 12, 14, 16 }, 206185377Ssam .maxFirstepLevel = 2, /* levels 0..2 */ 207185377Ssam .firstep = { 0, 4, 8 }, 208185377Ssam .ofdmTrigHigh = 500, 209185377Ssam .ofdmTrigLow = 200, 210185377Ssam .cckTrigHigh = 200, 211185377Ssam .cckTrigLow = 100, 212185377Ssam .rssiThrHigh = 40, 213185377Ssam .rssiThrLow = 7, 214185377Ssam .period = 100, 215185377Ssam }; 216185377Ssam if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN) { 217185377Ssam struct ar5212AniParams tmp; 218185377Ssam OS_MEMCPY(&tmp, &aniparams, sizeof(struct ar5212AniParams)); 219185377Ssam tmp.maxSpurImmunityLevel = 7; /* Venice and earlier */ 220185377Ssam ar5212AniAttach(ah, &tmp, &tmp, AH_TRUE); 221185377Ssam } else 222185377Ssam ar5212AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 223222265Sadrian 224222265Sadrian /* Set overridable ANI methods */ 225222265Sadrian AH5212(ah)->ah_aniControl = ar5212AniControl; 226185377Ssam} 227185377Ssam 228185377Ssam/* 229185377Ssam * Attach for an AR5212 part. 230185377Ssam */ 231185377Ssamvoid 232185377Ssamar5212InitState(struct ath_hal_5212 *ahp, uint16_t devid, HAL_SOFTC sc, 233185377Ssam HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) 234185377Ssam{ 235185377Ssam#define N(a) (sizeof(a)/sizeof(a[0])) 236185377Ssam static const uint8_t defbssidmask[IEEE80211_ADDR_LEN] = 237185377Ssam { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 238185377Ssam struct ath_hal *ah; 239185377Ssam 240185377Ssam ah = &ahp->ah_priv.h; 241185377Ssam /* set initial values */ 242185377Ssam OS_MEMCPY(&ahp->ah_priv, &ar5212hal, sizeof(struct ath_hal_private)); 243185377Ssam ah->ah_sc = sc; 244185377Ssam ah->ah_st = st; 245185377Ssam ah->ah_sh = sh; 246185377Ssam 247185377Ssam ah->ah_devid = devid; /* NB: for alq */ 248185377Ssam AH_PRIVATE(ah)->ah_devid = devid; 249185377Ssam AH_PRIVATE(ah)->ah_subvendorid = 0; /* XXX */ 250185377Ssam 251185377Ssam AH_PRIVATE(ah)->ah_powerLimit = MAX_RATE_POWER; 252185377Ssam AH_PRIVATE(ah)->ah_tpScale = HAL_TP_SCALE_MAX; /* no scaling */ 253185377Ssam 254185380Ssam ahp->ah_antControl = HAL_ANT_VARIABLE; 255185380Ssam ahp->ah_diversity = AH_TRUE; 256185377Ssam ahp->ah_bIQCalibration = AH_FALSE; 257185377Ssam /* 258185377Ssam * Enable MIC handling. 259185377Ssam */ 260185377Ssam ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE; 261185377Ssam ahp->ah_rssiThr = INIT_RSSI_THR; 262185377Ssam ahp->ah_tpcEnabled = AH_FALSE; /* disabled by default */ 263185380Ssam ahp->ah_phyPowerOn = AH_FALSE; 264185377Ssam ahp->ah_macTPC = SM(MAX_RATE_POWER, AR_TPC_ACK) 265185377Ssam | SM(MAX_RATE_POWER, AR_TPC_CTS) 266185377Ssam | SM(MAX_RATE_POWER, AR_TPC_CHIRP); 267185377Ssam ahp->ah_beaconInterval = 100; /* XXX [20..1000] */ 268185377Ssam ahp->ah_enable32kHzClock = DONT_USE_32KHZ;/* XXX */ 269185377Ssam ahp->ah_slottime = (u_int) -1; 270185377Ssam ahp->ah_acktimeout = (u_int) -1; 271185377Ssam ahp->ah_ctstimeout = (u_int) -1; 272185377Ssam ahp->ah_sifstime = (u_int) -1; 273204579Srpaulo ahp->ah_txTrigLev = INIT_TX_FIFO_THRESHOLD, 274204579Srpaulo ahp->ah_maxTxTrigLev = MAX_TX_FIFO_THRESHOLD, 275204579Srpaulo 276185377Ssam OS_MEMCPY(&ahp->ah_bssidmask, defbssidmask, IEEE80211_ADDR_LEN); 277185377Ssam#undef N 278185377Ssam} 279185377Ssam 280185377Ssam/* 281185377Ssam * Validate MAC version and revision. 282185377Ssam */ 283185377Ssamstatic HAL_BOOL 284185377Ssamar5212IsMacSupported(uint8_t macVersion, uint8_t macRev) 285185377Ssam{ 286185377Ssam#define N(a) (sizeof(a)/sizeof(a[0])) 287185377Ssam static const struct { 288185377Ssam uint8_t version; 289185377Ssam uint8_t revMin, revMax; 290185377Ssam } macs[] = { 291185377Ssam { AR_SREV_VERSION_VENICE, 292185377Ssam AR_SREV_D2PLUS, AR_SREV_REVISION_MAX }, 293185377Ssam { AR_SREV_VERSION_GRIFFIN, 294185377Ssam AR_SREV_D2PLUS, AR_SREV_REVISION_MAX }, 295185377Ssam { AR_SREV_5413, 296185377Ssam AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 297185377Ssam { AR_SREV_5424, 298185377Ssam AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 299185377Ssam { AR_SREV_2425, 300185377Ssam AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 301185377Ssam { AR_SREV_2417, 302185377Ssam AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 303185377Ssam }; 304185377Ssam int i; 305185377Ssam 306185377Ssam for (i = 0; i < N(macs); i++) 307185377Ssam if (macs[i].version == macVersion && 308185377Ssam macs[i].revMin <= macRev && macRev <= macs[i].revMax) 309185377Ssam return AH_TRUE; 310185377Ssam return AH_FALSE; 311185377Ssam#undef N 312185377Ssam} 313185377Ssam 314185377Ssam/* 315185377Ssam * Attach for an AR5212 part. 316185377Ssam */ 317185406Ssamstatic struct ath_hal * 318185377Ssamar5212Attach(uint16_t devid, HAL_SOFTC sc, 319217624Sadrian HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 320217624Sadrian HAL_STATUS *status) 321185377Ssam{ 322185377Ssam#define AH_EEPROM_PROTECT(ah) \ 323188979Ssam (AH_PRIVATE(ah)->ah_ispcie)? AR_EEPROM_PROTECT_PCIE : AR_EEPROM_PROTECT) 324185377Ssam struct ath_hal_5212 *ahp; 325185377Ssam struct ath_hal *ah; 326185406Ssam struct ath_hal_rf *rf; 327185377Ssam uint32_t val; 328185377Ssam uint16_t eeval; 329185377Ssam HAL_STATUS ecode; 330185377Ssam 331225883Sadrian HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 332185377Ssam __func__, sc, (void*) st, (void*) sh); 333185377Ssam 334185377Ssam /* NB: memory is returned zero'd */ 335185377Ssam ahp = ath_hal_malloc(sizeof (struct ath_hal_5212)); 336185377Ssam if (ahp == AH_NULL) { 337225883Sadrian HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 338185377Ssam "%s: cannot allocate memory for state block\n", __func__); 339185377Ssam *status = HAL_ENOMEM; 340185377Ssam return AH_NULL; 341185377Ssam } 342185377Ssam ar5212InitState(ahp, devid, sc, st, sh, status); 343185377Ssam ah = &ahp->ah_priv.h; 344185377Ssam 345185377Ssam if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 346185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", 347185377Ssam __func__); 348185377Ssam ecode = HAL_EIO; 349185377Ssam goto bad; 350185377Ssam } 351185377Ssam /* Read Revisions from Chips before taking out of reset */ 352185377Ssam val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID; 353185377Ssam AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S; 354185377Ssam AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION; 355188979Ssam AH_PRIVATE(ah)->ah_ispcie = IS_5424(ah) || IS_2425(ah); 356185377Ssam 357185377Ssam if (!ar5212IsMacSupported(AH_PRIVATE(ah)->ah_macVersion, AH_PRIVATE(ah)->ah_macRev)) { 358185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 359185377Ssam "%s: Mac Chip Rev 0x%02x.%x not supported\n" , 360185377Ssam __func__, AH_PRIVATE(ah)->ah_macVersion, 361185377Ssam AH_PRIVATE(ah)->ah_macRev); 362185377Ssam ecode = HAL_ENOTSUPP; 363185377Ssam goto bad; 364185377Ssam } 365185377Ssam 366185377Ssam /* setup common ini data; rf backends handle remainder */ 367185377Ssam HAL_INI_INIT(&ahp->ah_ini_modes, ar5212Modes, 6); 368185377Ssam HAL_INI_INIT(&ahp->ah_ini_common, ar5212Common, 2); 369185377Ssam 370185377Ssam if (!ar5212ChipReset(ah, AH_NULL)) { /* reset chip */ 371185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 372185377Ssam ecode = HAL_EIO; 373185377Ssam goto bad; 374185377Ssam } 375185377Ssam 376185377Ssam AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 377185377Ssam 378188979Ssam if (AH_PRIVATE(ah)->ah_ispcie) { 379185377Ssam /* XXX: build flag to disable this? */ 380235972Sadrian ath_hal_configPCIE(ah, AH_FALSE, AH_FALSE); 381185377Ssam } 382185377Ssam 383185377Ssam if (!ar5212ChipTest(ah)) { 384185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 385185377Ssam __func__); 386185377Ssam ecode = HAL_ESELFTEST; 387185377Ssam goto bad; 388185377Ssam } 389185377Ssam 390185377Ssam /* Enable PCI core retry fix in software for Hainan and up */ 391185377Ssam if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_VENICE) 392185377Ssam OS_REG_SET_BIT(ah, AR_PCICFG, AR_PCICFG_RETRYFIXEN); 393185377Ssam 394185377Ssam /* 395185377Ssam * Set correct Baseband to analog shift 396185377Ssam * setting to access analog chips. 397185377Ssam */ 398185377Ssam OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 399185377Ssam 400185377Ssam /* Read Radio Chip Rev Extract */ 401185377Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah); 402185406Ssam 403185406Ssam rf = ath_hal_rfprobe(ah, &ecode); 404185406Ssam if (rf == AH_NULL) 405185406Ssam goto bad; 406185406Ssam 407185377Ssam /* NB: silently accept anything in release code per Atheros */ 408185377Ssam switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 409185377Ssam case AR_RAD5111_SREV_MAJOR: 410185377Ssam case AR_RAD5112_SREV_MAJOR: 411185377Ssam case AR_RAD2112_SREV_MAJOR: 412185377Ssam case AR_RAD2111_SREV_MAJOR: 413185377Ssam case AR_RAD2413_SREV_MAJOR: 414185377Ssam case AR_RAD5413_SREV_MAJOR: 415185377Ssam case AR_RAD5424_SREV_MAJOR: 416185377Ssam break; 417185377Ssam default: 418185377Ssam if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 419185377Ssam /* 420185377Ssam * When RF_Silent is used, the 421185377Ssam * analog chip is reset. So when the system boots 422185377Ssam * up with the radio switch off we cannot determine 423185377Ssam * the RF chip rev. To workaround this check the 424185377Ssam * mac+phy revs and if Hainan, set the radio rev 425185377Ssam * to Derby. 426185377Ssam */ 427185377Ssam if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE && 428185377Ssam AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN && 429185377Ssam AH_PRIVATE(ah)->ah_phyRev == AR_PHYREV_HAINAN) { 430185377Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = AR_ANALOG5REV_HAINAN; 431185377Ssam break; 432185377Ssam } 433185377Ssam if (IS_2413(ah)) { /* Griffin */ 434185380Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = 435185380Ssam AR_RAD2413_SREV_MAJOR | 0x1; 436185377Ssam break; 437185377Ssam } 438185377Ssam if (IS_5413(ah)) { /* Eagle */ 439185380Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = 440185380Ssam AR_RAD5413_SREV_MAJOR | 0x2; 441185377Ssam break; 442185377Ssam } 443185377Ssam if (IS_2425(ah) || IS_2417(ah)) {/* Swan or Nala */ 444185380Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = 445185380Ssam AR_RAD5424_SREV_MAJOR | 0x2; 446185377Ssam break; 447185377Ssam } 448185377Ssam } 449185377Ssam#ifdef AH_DEBUG 450185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 451185377Ssam "%s: 5G Radio Chip Rev 0x%02X is not supported by " 452185377Ssam "this driver\n", 453185377Ssam __func__, AH_PRIVATE(ah)->ah_analog5GhzRev); 454185377Ssam ecode = HAL_ENOTSUPP; 455185377Ssam goto bad; 456185377Ssam#endif 457185377Ssam } 458185380Ssam if (IS_RAD5112_REV1(ah)) { 459185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 460185377Ssam "%s: 5112 Rev 1 is not supported by this " 461185377Ssam "driver (analog5GhzRev 0x%x)\n", __func__, 462185377Ssam AH_PRIVATE(ah)->ah_analog5GhzRev); 463185377Ssam ecode = HAL_ENOTSUPP; 464185377Ssam goto bad; 465185377Ssam } 466185377Ssam 467185377Ssam val = OS_REG_READ(ah, AR_PCICFG); 468185377Ssam val = MS(val, AR_PCICFG_EEPROM_SIZE); 469185377Ssam if (val == 0) { 470188979Ssam if (!AH_PRIVATE(ah)->ah_ispcie) { 471185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 472185377Ssam "%s: unsupported EEPROM size %u (0x%x) found\n", 473185377Ssam __func__, val, val); 474185377Ssam ecode = HAL_EESIZE; 475185377Ssam goto bad; 476185377Ssam } 477185377Ssam /* XXX AH_PRIVATE(ah)->ah_isPciExpress = AH_TRUE; */ 478185377Ssam } else if (val != AR_PCICFG_EEPROM_SIZE_16K) { 479185377Ssam if (AR_PCICFG_EEPROM_SIZE_FAILED == val) { 480185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 481185377Ssam "%s: unsupported EEPROM size %u (0x%x) found\n", 482185377Ssam __func__, val, val); 483185377Ssam ecode = HAL_EESIZE; 484185377Ssam goto bad; 485185377Ssam } 486185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 487185377Ssam "%s: EEPROM size = %d. Must be %d (16k).\n", 488185377Ssam __func__, val, AR_PCICFG_EEPROM_SIZE_16K); 489185377Ssam ecode = HAL_EESIZE; 490185377Ssam goto bad; 491185377Ssam } 492185377Ssam ecode = ath_hal_legacyEepromAttach(ah); 493185377Ssam if (ecode != HAL_OK) { 494185377Ssam goto bad; 495185377Ssam } 496185377Ssam ahp->ah_isHb63 = IS_2425(ah) && ath_hal_eepromGetFlag(ah, AR_EEP_ISTALON); 497185377Ssam 498185377Ssam /* 499185377Ssam * If Bmode and AR5212, verify 2.4 analog exists 500185377Ssam */ 501185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) && 502185377Ssam (AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD5111_SREV_MAJOR) { 503185377Ssam /* 504185377Ssam * Set correct Baseband to analog shift 505185377Ssam * setting to access analog chips. 506185377Ssam */ 507185377Ssam OS_REG_WRITE(ah, AR_PHY(0), 0x00004007); 508185377Ssam OS_DELAY(2000); 509185377Ssam AH_PRIVATE(ah)->ah_analog2GhzRev = ar5212GetRadioRev(ah); 510185377Ssam 511185377Ssam /* Set baseband for 5GHz chip */ 512185377Ssam OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 513185377Ssam OS_DELAY(2000); 514185377Ssam if ((AH_PRIVATE(ah)->ah_analog2GhzRev & 0xF0) != AR_RAD2111_SREV_MAJOR) { 515185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 516185377Ssam "%s: 2G Radio Chip Rev 0x%02X is not " 517185377Ssam "supported by this driver\n", __func__, 518185377Ssam AH_PRIVATE(ah)->ah_analog2GhzRev); 519185377Ssam ecode = HAL_ENOTSUPP; 520185377Ssam goto bad; 521185377Ssam } 522185377Ssam } 523185377Ssam 524185377Ssam ecode = ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, &eeval); 525185377Ssam if (ecode != HAL_OK) { 526185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 527185377Ssam "%s: cannot read regulatory domain from EEPROM\n", 528185377Ssam __func__); 529185377Ssam goto bad; 530185377Ssam } 531185377Ssam AH_PRIVATE(ah)->ah_currentRD = eeval; 532185377Ssam /* XXX record serial number */ 533185377Ssam 534185377Ssam /* 535185377Ssam * Got everything we need now to setup the capabilities. 536185377Ssam */ 537185377Ssam if (!ar5212FillCapabilityInfo(ah)) { 538185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 539185377Ssam "%s: failed ar5212FillCapabilityInfo\n", __func__); 540185377Ssam ecode = HAL_EEREAD; 541185377Ssam goto bad; 542185377Ssam } 543185377Ssam 544185406Ssam if (!rf->attach(ah, &ecode)) { 545185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 546185377Ssam __func__, ecode); 547185377Ssam goto bad; 548185377Ssam } 549185377Ssam /* 550185377Ssam * Set noise floor adjust method; we arrange a 551185377Ssam * direct call instead of thunking. 552185377Ssam */ 553185377Ssam AH_PRIVATE(ah)->ah_getNfAdjust = ahp->ah_rfHal->getNfAdjust; 554185377Ssam 555185377Ssam /* Initialize gain ladder thermal calibration structure */ 556185377Ssam ar5212InitializeGainValues(ah); 557185377Ssam 558185377Ssam ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 559185377Ssam if (ecode != HAL_OK) { 560185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 561185377Ssam "%s: error getting mac address from EEPROM\n", __func__); 562185377Ssam goto bad; 563185377Ssam } 564185377Ssam 565185377Ssam ar5212AniSetup(ah); 566185377Ssam /* Setup of Radar/AR structures happens in ath_hal_initchannels*/ 567185377Ssam ar5212InitNfCalHistBuffer(ah); 568185377Ssam 569185377Ssam /* XXX EAR stuff goes here */ 570185377Ssam 571185377Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 572185377Ssam 573185377Ssam return ah; 574185377Ssam 575185377Ssambad: 576185377Ssam if (ahp) 577185377Ssam ar5212Detach((struct ath_hal *) ahp); 578185377Ssam if (status) 579185377Ssam *status = ecode; 580185377Ssam return AH_NULL; 581185377Ssam#undef AH_EEPROM_PROTECT 582185377Ssam} 583185377Ssam 584185377Ssamvoid 585185377Ssamar5212Detach(struct ath_hal *ah) 586185377Ssam{ 587185377Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__); 588185377Ssam 589185377Ssam HALASSERT(ah != AH_NULL); 590185377Ssam HALASSERT(ah->ah_magic == AR5212_MAGIC); 591185377Ssam 592185377Ssam ar5212AniDetach(ah); 593185377Ssam ar5212RfDetach(ah); 594185377Ssam ar5212Disable(ah); 595185377Ssam ar5212SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); 596185377Ssam 597185377Ssam ath_hal_eepromDetach(ah); 598185377Ssam ath_hal_free(ah); 599185377Ssam} 600185377Ssam 601185377SsamHAL_BOOL 602185377Ssamar5212ChipTest(struct ath_hal *ah) 603185377Ssam{ 604185377Ssam uint32_t regAddr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) }; 605185377Ssam uint32_t regHold[2]; 606185377Ssam uint32_t patternData[4] = 607185377Ssam { 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 }; 608185377Ssam int i, j; 609185377Ssam 610185377Ssam /* Test PHY & MAC registers */ 611185377Ssam for (i = 0; i < 2; i++) { 612185377Ssam uint32_t addr = regAddr[i]; 613185377Ssam uint32_t wrData, rdData; 614185377Ssam 615185377Ssam regHold[i] = OS_REG_READ(ah, addr); 616185377Ssam for (j = 0; j < 0x100; j++) { 617185377Ssam wrData = (j << 16) | j; 618185377Ssam OS_REG_WRITE(ah, addr, wrData); 619185377Ssam rdData = OS_REG_READ(ah, addr); 620185377Ssam if (rdData != wrData) { 621185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 622185377Ssam"%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 623185377Ssam __func__, addr, wrData, rdData); 624185377Ssam return AH_FALSE; 625185377Ssam } 626185377Ssam } 627185377Ssam for (j = 0; j < 4; j++) { 628185377Ssam wrData = patternData[j]; 629185377Ssam OS_REG_WRITE(ah, addr, wrData); 630185377Ssam rdData = OS_REG_READ(ah, addr); 631185377Ssam if (wrData != rdData) { 632185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 633185377Ssam"%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 634185377Ssam __func__, addr, wrData, rdData); 635185377Ssam return AH_FALSE; 636185377Ssam } 637185377Ssam } 638185377Ssam OS_REG_WRITE(ah, regAddr[i], regHold[i]); 639185377Ssam } 640185377Ssam OS_DELAY(100); 641185377Ssam return AH_TRUE; 642185377Ssam} 643185377Ssam 644185377Ssam/* 645185377Ssam * Store the channel edges for the requested operational mode 646185377Ssam */ 647185377SsamHAL_BOOL 648185377Ssamar5212GetChannelEdges(struct ath_hal *ah, 649185377Ssam uint16_t flags, uint16_t *low, uint16_t *high) 650185377Ssam{ 651187831Ssam if (flags & IEEE80211_CHAN_5GHZ) { 652185377Ssam *low = 4915; 653185377Ssam *high = 6100; 654185377Ssam return AH_TRUE; 655185377Ssam } 656187831Ssam if ((flags & IEEE80211_CHAN_2GHZ) && 657185377Ssam (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) || 658185377Ssam ath_hal_eepromGetFlag(ah, AR_EEP_GMODE))) { 659185377Ssam *low = 2312; 660185377Ssam *high = 2732; 661185377Ssam return AH_TRUE; 662185377Ssam } 663185377Ssam return AH_FALSE; 664185377Ssam} 665185377Ssam 666185377Ssam/* 667188979Ssam * Disable PLL when in L0s as well as receiver clock when in L1. 668188979Ssam * This power saving option must be enabled through the Serdes. 669188979Ssam * 670188979Ssam * Programming the Serdes must go through the same 288 bit serial shift 671188979Ssam * register as the other analog registers. Hence the 9 writes. 672188979Ssam * 673188979Ssam * XXX Clean up the magic numbers. 674188979Ssam */ 675188979Ssamstatic void 676235972Sadrianar5212ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off) 677188979Ssam{ 678188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 679188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 680188979Ssam 681188979Ssam /* RX shut off when elecidle is asserted */ 682188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039); 683188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824); 684188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579); 685188979Ssam 686188979Ssam /* Shut off PLL and CLKREQ active in L1 */ 687188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff); 688188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 689188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 690188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007); 691188979Ssam 692188979Ssam /* Load the new settings */ 693188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 694188979Ssam} 695188979Ssam 696188979Ssamstatic void 697188979Ssamar5212DisablePCIE(struct ath_hal *ah) 698188979Ssam{ 699188979Ssam /* NB: fill in for 9100 */ 700188979Ssam} 701188979Ssam 702188979Ssam/* 703185377Ssam * Fill all software cached or static hardware state information. 704185377Ssam * Return failure if capabilities are to come from EEPROM and 705185377Ssam * cannot be read. 706185377Ssam */ 707185377SsamHAL_BOOL 708185377Ssamar5212FillCapabilityInfo(struct ath_hal *ah) 709185377Ssam{ 710185377Ssam#define AR_KEYTABLE_SIZE 128 711185377Ssam#define IS_GRIFFIN_LITE(ah) \ 712185377Ssam (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_GRIFFIN && \ 713185377Ssam AH_PRIVATE(ah)->ah_macRev == AR_SREV_GRIFFIN_LITE) 714185377Ssam#define IS_COBRA(ah) \ 715185377Ssam (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_COBRA) 716185377Ssam#define IS_2112(ah) \ 717185377Ssam ((AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD2112_SREV_MAJOR) 718185377Ssam 719185377Ssam struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 720185377Ssam HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 721185377Ssam uint16_t capField, val; 722185377Ssam 723185377Ssam /* Read the capability EEPROM location */ 724185377Ssam if (ath_hal_eepromGet(ah, AR_EEP_OPCAP, &capField) != HAL_OK) { 725185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 726185377Ssam "%s: unable to read caps from eeprom\n", __func__); 727185377Ssam return AH_FALSE; 728185377Ssam } 729185377Ssam if (IS_2112(ah)) 730185377Ssam ath_hal_eepromSet(ah, AR_EEP_AMODE, AH_FALSE); 731185377Ssam if (capField == 0 && IS_GRIFFIN_LITE(ah)) { 732185377Ssam /* 733185377Ssam * For griffin-lite cards with unprogrammed capabilities. 734185377Ssam */ 735185377Ssam ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE); 736185377Ssam ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE); 737185377Ssam ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE); 738185377Ssam ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE); 739185377Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, 740185377Ssam "%s: override caps for griffin-lite, now 0x%x (+!turbo)\n", 741185377Ssam __func__, capField); 742185377Ssam } 743185377Ssam 744185377Ssam /* Modify reg domain on newer cards that need to work with older sw */ 745185377Ssam if (ahpriv->ah_opmode != HAL_M_HOSTAP && 746185377Ssam ahpriv->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) { 747185377Ssam if (ahpriv->ah_currentRD == 0x64 || 748185377Ssam ahpriv->ah_currentRD == 0x65) 749185377Ssam ahpriv->ah_currentRD += 5; 750185377Ssam else if (ahpriv->ah_currentRD == 0x41) 751185377Ssam ahpriv->ah_currentRD = 0x43; 752185377Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: regdomain mapped to 0x%x\n", 753185377Ssam __func__, ahpriv->ah_currentRD); 754185377Ssam } 755185377Ssam 756185377Ssam if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2417 || 757185377Ssam AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2425) { 758185377Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, 759185377Ssam "%s: enable Bmode and disable turbo for Swan/Nala\n", 760185377Ssam __func__); 761185377Ssam ath_hal_eepromSet(ah, AR_EEP_BMODE, AH_TRUE); 762185377Ssam ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE); 763185377Ssam ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE); 764185377Ssam ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE); 765185377Ssam ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE); 766185377Ssam } 767185377Ssam 768185377Ssam /* Construct wireless mode from EEPROM */ 769185377Ssam pCap->halWirelessModes = 0; 770185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) { 771185377Ssam pCap->halWirelessModes |= HAL_MODE_11A; 772185377Ssam if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO5DISABLE)) 773185377Ssam pCap->halWirelessModes |= HAL_MODE_TURBO; 774185377Ssam } 775185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE)) 776185377Ssam pCap->halWirelessModes |= HAL_MODE_11B; 777185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE) && 778185377Ssam ahpriv->ah_subvendorid != AR_SUBVENDOR_ID_NOG) { 779185377Ssam pCap->halWirelessModes |= HAL_MODE_11G; 780185377Ssam if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO2DISABLE)) 781185377Ssam pCap->halWirelessModes |= HAL_MODE_108G; 782185377Ssam } 783185377Ssam 784185377Ssam pCap->halLow2GhzChan = 2312; 785185380Ssam /* XXX 2417 too? */ 786185380Ssam if (IS_RAD5112_ANY(ah) || IS_5413(ah) || IS_2425(ah) || IS_2417(ah)) 787185377Ssam pCap->halHigh2GhzChan = 2500; 788185377Ssam else 789185377Ssam pCap->halHigh2GhzChan = 2732; 790185377Ssam 791242408Sadrian /* 792242408Sadrian * For AR5111 version < 4, the lowest centre frequency supported is 793242408Sadrian * 5130MHz. For AR5111 version 4, the 4.9GHz channels are supported 794242408Sadrian * but only in 10MHz increments. 795242408Sadrian * 796242408Sadrian * In addition, the programming method is wrong - it uses the IEEE 797242408Sadrian * channel number to calculate the frequency, rather than the 798242408Sadrian * channel centre. Since half/quarter rates re-use some of the 799242408Sadrian * 5GHz channel IEEE numbers, this will result in a badly programmed 800242408Sadrian * synth. 801242408Sadrian * 802242408Sadrian * Until the relevant support is written, just limit lower frequency 803242408Sadrian * support for AR5111 so things aren't incorrectly programmed. 804242408Sadrian * 805242408Sadrian * XXX It's also possible this code doesn't correctly limit the 806242408Sadrian * centre frequencies of potential channels; this is very important 807242408Sadrian * for half/quarter rate! 808242408Sadrian */ 809242408Sadrian if (AH_RADIO_MAJOR(ah) == AR_RAD5111_SREV_MAJOR) { 810242408Sadrian pCap->halLow5GhzChan = 5120; /* XXX lowest centre = 5130MHz */ 811242408Sadrian } else { 812242408Sadrian pCap->halLow5GhzChan = 4915; 813242408Sadrian } 814185377Ssam pCap->halHigh5GhzChan = 6100; 815185377Ssam 816185377Ssam pCap->halCipherCkipSupport = AH_FALSE; 817185377Ssam pCap->halCipherTkipSupport = AH_TRUE; 818185377Ssam pCap->halCipherAesCcmSupport = 819185377Ssam (ath_hal_eepromGetFlag(ah, AR_EEP_AES) && 820185377Ssam ((AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE) || 821185377Ssam ((AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE) && 822185377Ssam (AH_PRIVATE(ah)->ah_macRev >= AR_SREV_VERSION_OAHU)))); 823185377Ssam 824185377Ssam pCap->halMicCkipSupport = AH_FALSE; 825185377Ssam pCap->halMicTkipSupport = AH_TRUE; 826185377Ssam pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 827185377Ssam /* 828185377Ssam * Starting with Griffin TX+RX mic keys can be combined 829185377Ssam * in one key cache slot. 830185377Ssam */ 831185377Ssam if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_GRIFFIN) 832185377Ssam pCap->halTkipMicTxRxKeySupport = AH_TRUE; 833185377Ssam else 834185377Ssam pCap->halTkipMicTxRxKeySupport = AH_FALSE; 835185377Ssam pCap->halChanSpreadSupport = AH_TRUE; 836185377Ssam pCap->halSleepAfterBeaconBroken = AH_TRUE; 837185377Ssam 838185377Ssam if (ahpriv->ah_macRev > 1 || IS_COBRA(ah)) { 839185377Ssam pCap->halCompressSupport = 840185377Ssam ath_hal_eepromGetFlag(ah, AR_EEP_COMPRESS) && 841185377Ssam (pCap->halWirelessModes & (HAL_MODE_11A|HAL_MODE_11G)) != 0; 842185377Ssam pCap->halBurstSupport = ath_hal_eepromGetFlag(ah, AR_EEP_BURST); 843185377Ssam pCap->halFastFramesSupport = 844185377Ssam ath_hal_eepromGetFlag(ah, AR_EEP_FASTFRAME) && 845185377Ssam (pCap->halWirelessModes & (HAL_MODE_11A|HAL_MODE_11G)) != 0; 846185377Ssam pCap->halChapTuningSupport = AH_TRUE; 847185377Ssam pCap->halTurboPrimeSupport = AH_TRUE; 848185377Ssam } 849185377Ssam pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G; 850185377Ssam 851185377Ssam pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */ 852238858Sadrian pCap->halNumMRRetries = 4; /* Hardware supports 4 MRR */ 853239643Sadrian pCap->halNumTxMaps = 1; /* Single TX ptr per descr */ 854185377Ssam pCap->halVEOLSupport = AH_TRUE; 855185377Ssam pCap->halBssIdMaskSupport = AH_TRUE; 856185377Ssam pCap->halMcastKeySrchSupport = AH_TRUE; 857185377Ssam if ((ahpriv->ah_macVersion == AR_SREV_VERSION_VENICE && 858185377Ssam ahpriv->ah_macRev == 8) || 859185377Ssam ahpriv->ah_macVersion > AR_SREV_VERSION_VENICE) 860185377Ssam pCap->halTsfAddSupport = AH_TRUE; 861185377Ssam 862185377Ssam if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK) 863185377Ssam pCap->halTotalQueues = val; 864185377Ssam else 865185377Ssam pCap->halTotalQueues = HAL_NUM_TX_QUEUES; 866185377Ssam 867185377Ssam if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK) 868185377Ssam pCap->halKeyCacheSize = val; 869185377Ssam else 870185377Ssam pCap->halKeyCacheSize = AR_KEYTABLE_SIZE; 871185377Ssam 872185380Ssam pCap->halChanHalfRate = AH_TRUE; 873185380Ssam pCap->halChanQuarterRate = AH_TRUE; 874185377Ssam 875230791Sadrian /* 876230791Sadrian * RSSI uses the combined field; some 11n NICs may use 877230791Sadrian * the control chain RSSI. 878230791Sadrian */ 879230791Sadrian pCap->halUseCombinedRadarRssi = AH_TRUE; 880230791Sadrian 881185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) && 882185377Ssam ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) { 883185377Ssam /* NB: enabled by default */ 884185377Ssam ahpriv->ah_rfkillEnabled = AH_TRUE; 885185377Ssam pCap->halRfSilentSupport = AH_TRUE; 886185377Ssam } 887185377Ssam 888185377Ssam /* NB: this is a guess, noone seems to know the answer */ 889185377Ssam ahpriv->ah_rxornIsFatal = 890185377Ssam (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_VENICE); 891185377Ssam 892195114Ssam /* enable features that first appeared in Hainan */ 893195114Ssam if ((AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE && 894185377Ssam AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN) || 895195114Ssam AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE) { 896195114Ssam /* h/w phy counters */ 897195114Ssam pCap->halHwPhyCounterSupport = AH_TRUE; 898195114Ssam /* bssid match disable */ 899195114Ssam pCap->halBssidMatchSupport = AH_TRUE; 900195114Ssam } 901185377Ssam 902185377Ssam pCap->halTstampPrecision = 15; 903192396Ssam pCap->halIntrMask = HAL_INT_COMMON 904192396Ssam | HAL_INT_RX 905192396Ssam | HAL_INT_TX 906192396Ssam | HAL_INT_FATAL 907192396Ssam | HAL_INT_BNR 908192396Ssam | HAL_INT_BMISC 909192396Ssam ; 910192400Ssam if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN) 911192400Ssam pCap->halIntrMask &= ~HAL_INT_TBTT; 912185377Ssam 913218436Sadrian pCap->hal4kbSplitTransSupport = AH_TRUE; 914220324Sadrian pCap->halHasRxSelfLinkedTail = AH_TRUE; 915218436Sadrian 916185377Ssam return AH_TRUE; 917185377Ssam#undef IS_COBRA 918185377Ssam#undef IS_GRIFFIN_LITE 919185377Ssam#undef AR_KEYTABLE_SIZE 920185377Ssam} 921185406Ssam 922185406Ssamstatic const char* 923185406Ssamar5212Probe(uint16_t vendorid, uint16_t devid) 924185406Ssam{ 925185406Ssam if (vendorid == ATHEROS_VENDOR_ID || 926185406Ssam vendorid == ATHEROS_3COM_VENDOR_ID || 927185406Ssam vendorid == ATHEROS_3COM2_VENDOR_ID) { 928185406Ssam switch (devid) { 929185406Ssam case AR5212_FPGA: 930185406Ssam return "Atheros 5212 (FPGA)"; 931185406Ssam case AR5212_DEVID: 932185406Ssam case AR5212_DEVID_IBM: 933185406Ssam case AR5212_DEFAULT: 934185406Ssam return "Atheros 5212"; 935185406Ssam case AR5212_AR2413: 936185406Ssam return "Atheros 2413"; 937185406Ssam case AR5212_AR2417: 938185406Ssam return "Atheros 2417"; 939185406Ssam case AR5212_AR5413: 940185406Ssam return "Atheros 5413"; 941185406Ssam case AR5212_AR5424: 942185406Ssam return "Atheros 5424/2424"; 943185406Ssam } 944185406Ssam } 945185406Ssam return AH_NULL; 946185406Ssam} 947185418SsamAH_CHIP(AR5212, ar5212Probe, ar5212Attach); 948