1/*- 2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD$"); 29 30#include <sys/param.h> 31#include <sys/module.h> 32#include <sys/systm.h> 33#include <sys/kernel.h> 34#include <sys/ata.h> 35#include <sys/bus.h> 36#include <sys/endian.h> 37#include <sys/malloc.h> 38#include <sys/lock.h> 39#include <sys/mutex.h> 40#include <sys/sema.h> 41#include <sys/taskqueue.h> 42#include <vm/uma.h> 43#include <machine/stdarg.h> 44#include <machine/resource.h> 45#include <machine/bus.h> 46#include <sys/rman.h> 47#include <dev/pci/pcivar.h> 48#include <dev/pci/pcireg.h> 49#include <dev/ata/ata-all.h> 50#include <dev/ata/ata-pci.h> 51#include <ata_if.h> 52 53/* local prototypes */ 54static int ata_marvell_chipinit(device_t dev); 55static int ata_marvell_ch_attach(device_t dev); 56static int ata_marvell_setmode(device_t dev, int target, int mode); 57static int ata_marvell_dummy_chipinit(device_t dev); 58static int ata_marvell_edma_ch_attach(device_t dev); 59static int ata_marvell_edma_ch_detach(device_t dev); 60static int ata_marvell_edma_status(device_t dev); 61static int ata_marvell_edma_begin_transaction(struct ata_request *request); 62static int ata_marvell_edma_end_transaction(struct ata_request *request); 63static void ata_marvell_edma_reset(device_t dev); 64static void ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 65static void ata_marvell_edma_dmainit(device_t dev); 66 67/* misc defines */ 68#define MV_50XX 50 69#define MV_60XX 60 70#define MV_6042 62 71#define MV_7042 72 72#define MV_61XX 61 73#define MV_91XX 91 74 75/* 76 * Marvell chipset support functions 77 */ 78#define ATA_MV_HOST_BASE(ch) \ 79 ((ch->unit & 3) * 0x0100) + (ch->unit > 3 ? 0x30000 : 0x20000) 80#define ATA_MV_EDMA_BASE(ch) \ 81 ((ch->unit & 3) * 0x2000) + (ch->unit > 3 ? 0x30000 : 0x20000) 82 83struct ata_marvell_response { 84 u_int16_t tag; 85 u_int8_t edma_status; 86 u_int8_t dev_status; 87 u_int32_t timestamp; 88}; 89 90struct ata_marvell_dma_prdentry { 91 u_int32_t addrlo; 92 u_int32_t count; 93 u_int32_t addrhi; 94 u_int32_t reserved; 95}; 96 97static int 98ata_marvell_probe(device_t dev) 99{ 100 struct ata_pci_controller *ctlr = device_get_softc(dev); 101 static const struct ata_chip_id ids[] = 102 {{ ATA_M88SX5040, 0, 4, MV_50XX, ATA_SA150, "88SX5040" }, 103 { ATA_M88SX5041, 0, 4, MV_50XX, ATA_SA150, "88SX5041" }, 104 { ATA_M88SX5080, 0, 8, MV_50XX, ATA_SA150, "88SX5080" }, 105 { ATA_M88SX5081, 0, 8, MV_50XX, ATA_SA150, "88SX5081" }, 106 { ATA_M88SX6041, 0, 4, MV_60XX, ATA_SA300, "88SX6041" }, 107 { ATA_M88SX6042, 0, 4, MV_6042, ATA_SA300, "88SX6042" }, 108 { ATA_M88SX6081, 0, 8, MV_60XX, ATA_SA300, "88SX6081" }, 109 { ATA_M88SX7042, 0, 4, MV_7042, ATA_SA300, "88SX7042" }, 110 { ATA_M88SE6101, 0, 0, MV_61XX, ATA_UDMA6, "88SE6101" }, 111 { ATA_M88SE6102, 0, 0, MV_61XX, ATA_UDMA6, "88SE6102" }, 112 { ATA_M88SE6111, 0, 1, MV_61XX, ATA_UDMA6, "88SE6111" }, 113 { ATA_M88SE6121, 0, 2, MV_61XX, ATA_UDMA6, "88SE6121" }, 114 { ATA_M88SE6141, 0, 4, MV_61XX, ATA_UDMA6, "88SE6141" }, 115 { ATA_M88SE6145, 0, 4, MV_61XX, ATA_UDMA6, "88SE6145" }, 116 { 0x91a41b4b, 0, 0, MV_91XX, ATA_UDMA6, "88SE912x" }, 117 { 0, 0, 0, 0, 0, 0}}; 118 119 if (pci_get_vendor(dev) != ATA_MARVELL_ID && 120 pci_get_vendor(dev) != ATA_MARVELL2_ID) 121 return ENXIO; 122 123 if (!(ctlr->chip = ata_match_chip(dev, ids))) 124 return ENXIO; 125 126 ata_set_desc(dev); 127 128 switch (ctlr->chip->cfg2) { 129 case MV_50XX: 130 case MV_60XX: 131 case MV_6042: 132 case MV_7042: 133 ctlr->chipinit = ata_marvell_edma_chipinit; 134 break; 135 case MV_61XX: 136 ctlr->chipinit = ata_marvell_chipinit; 137 break; 138 case MV_91XX: 139 ctlr->chipinit = ata_marvell_dummy_chipinit; 140 break; 141 } 142 return (BUS_PROBE_DEFAULT); 143} 144 145static int 146ata_marvell_chipinit(device_t dev) 147{ 148 struct ata_pci_controller *ctlr = device_get_softc(dev); 149 device_t child; 150 151 if (ata_setup_interrupt(dev, ata_generic_intr)) 152 return ENXIO; 153 /* Create AHCI subdevice if AHCI part present. */ 154 if (ctlr->chip->cfg1) { 155 child = device_add_child(dev, NULL, -1); 156 if (child != NULL) { 157 device_set_ivars(child, (void *)(intptr_t)-1); 158 bus_generic_attach(dev); 159 } 160 } 161 ctlr->ch_attach = ata_marvell_ch_attach; 162 ctlr->ch_detach = ata_pci_ch_detach; 163 ctlr->reset = ata_generic_reset; 164 ctlr->setmode = ata_marvell_setmode; 165 ctlr->channels = 1; 166 return (0); 167} 168 169static int 170ata_marvell_ch_attach(device_t dev) 171{ 172 struct ata_channel *ch = device_get_softc(dev); 173 int error; 174 175 error = ata_pci_ch_attach(dev); 176 /* dont use 32 bit PIO transfers */ 177 ch->flags |= ATA_USE_16BIT; 178 ch->flags |= ATA_CHECKS_CABLE; 179 return (error); 180} 181 182static int 183ata_marvell_setmode(device_t dev, int target, int mode) 184{ 185 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 186 struct ata_channel *ch = device_get_softc(dev); 187 188 mode = min(mode, ctlr->chip->max_dma); 189 /* Check for 80pin cable present. */ 190 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 191 ATA_IDX_INB(ch, ATA_BMDEVSPEC_0) & 0x01) { 192 ata_print_cable(dev, "controller"); 193 mode = ATA_UDMA2; 194 } 195 /* Nothing to do to setup mode, the controller snoop SET_FEATURE cmd. */ 196 return (mode); 197} 198 199static int 200ata_marvell_dummy_chipinit(device_t dev) 201{ 202 struct ata_pci_controller *ctlr = device_get_softc(dev); 203 204 ctlr->channels = 0; 205 return (0); 206} 207 208int 209ata_marvell_edma_chipinit(device_t dev) 210{ 211 struct ata_pci_controller *ctlr = device_get_softc(dev); 212 213 if (ata_setup_interrupt(dev, ata_generic_intr)) 214 return ENXIO; 215 216 ctlr->r_type1 = SYS_RES_MEMORY; 217 ctlr->r_rid1 = PCIR_BAR(0); 218 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 219 &ctlr->r_rid1, RF_ACTIVE))) 220 return ENXIO; 221 222 /* mask all host controller interrupts */ 223 ATA_OUTL(ctlr->r_res1, 0x01d64, 0x00000000); 224 225 /* mask all PCI interrupts */ 226 ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x00000000); 227 228 ctlr->ch_attach = ata_marvell_edma_ch_attach; 229 ctlr->ch_detach = ata_marvell_edma_ch_detach; 230 ctlr->reset = ata_marvell_edma_reset; 231 ctlr->setmode = ata_sata_setmode; 232 ctlr->getrev = ata_sata_getrev; 233 ctlr->channels = ctlr->chip->cfg1; 234 235 /* clear host controller interrupts */ 236 ATA_OUTL(ctlr->r_res1, 0x20014, 0x00000000); 237 if (ctlr->chip->cfg1 > 4) 238 ATA_OUTL(ctlr->r_res1, 0x30014, 0x00000000); 239 240 /* clear PCI interrupts */ 241 ATA_OUTL(ctlr->r_res1, 0x01d58, 0x00000000); 242 243 /* unmask PCI interrupts we want */ 244 ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x007fffff); 245 246 /* unmask host controller interrupts we want */ 247 ATA_OUTL(ctlr->r_res1, 0x01d64, 0x000000ff/*HC0*/ | 0x0001fe00/*HC1*/ | 248 /*(1<<19) | (1<<20) | (1<<21) |*/(1<<22) | (1<<24) | (0x7f << 25)); 249 250 return 0; 251} 252 253static int 254ata_marvell_edma_ch_attach(device_t dev) 255{ 256 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 257 struct ata_channel *ch = device_get_softc(dev); 258 u_int64_t work; 259 int i; 260 261 ata_marvell_edma_dmainit(dev); 262 work = ch->dma.work_bus; 263 /* clear work area */ 264 bzero(ch->dma.work, 1024+256); 265 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 266 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 267 268 /* set legacy ATA resources */ 269 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 270 ch->r_io[i].res = ctlr->r_res1; 271 ch->r_io[i].offset = 0x02100 + (i << 2) + ATA_MV_EDMA_BASE(ch); 272 } 273 ch->r_io[ATA_CONTROL].res = ctlr->r_res1; 274 ch->r_io[ATA_CONTROL].offset = 0x02120 + ATA_MV_EDMA_BASE(ch); 275 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res1; 276 ata_default_registers(dev); 277 278 /* set SATA resources */ 279 switch (ctlr->chip->cfg2) { 280 case MV_50XX: 281 ch->r_io[ATA_SSTATUS].res = ctlr->r_res1; 282 ch->r_io[ATA_SSTATUS].offset = 0x00100 + ATA_MV_HOST_BASE(ch); 283 ch->r_io[ATA_SERROR].res = ctlr->r_res1; 284 ch->r_io[ATA_SERROR].offset = 0x00104 + ATA_MV_HOST_BASE(ch); 285 ch->r_io[ATA_SCONTROL].res = ctlr->r_res1; 286 ch->r_io[ATA_SCONTROL].offset = 0x00108 + ATA_MV_HOST_BASE(ch); 287 break; 288 case MV_60XX: 289 case MV_6042: 290 case MV_7042: 291 ch->r_io[ATA_SSTATUS].res = ctlr->r_res1; 292 ch->r_io[ATA_SSTATUS].offset = 0x02300 + ATA_MV_EDMA_BASE(ch); 293 ch->r_io[ATA_SERROR].res = ctlr->r_res1; 294 ch->r_io[ATA_SERROR].offset = 0x02304 + ATA_MV_EDMA_BASE(ch); 295 ch->r_io[ATA_SCONTROL].res = ctlr->r_res1; 296 ch->r_io[ATA_SCONTROL].offset = 0x02308 + ATA_MV_EDMA_BASE(ch); 297 ch->r_io[ATA_SACTIVE].res = ctlr->r_res1; 298 ch->r_io[ATA_SACTIVE].offset = 0x02350 + ATA_MV_EDMA_BASE(ch); 299 break; 300 } 301 302 ch->flags |= ATA_NO_SLAVE; 303 ch->flags |= ATA_USE_16BIT; /* XXX SOS needed ? */ 304 ch->flags |= ATA_SATA; 305 ata_generic_hw(dev); 306 ch->hw.begin_transaction = ata_marvell_edma_begin_transaction; 307 ch->hw.end_transaction = ata_marvell_edma_end_transaction; 308 ch->hw.status = ata_marvell_edma_status; 309 310 /* disable the EDMA machinery */ 311 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002); 312 DELAY(100000); /* SOS should poll for disabled */ 313 314 /* set configuration to non-queued 128b read transfers stop on error */ 315 ATA_OUTL(ctlr->r_res1, 0x02000 + ATA_MV_EDMA_BASE(ch), (1<<11) | (1<<13)); 316 317 /* request queue base high */ 318 ATA_OUTL(ctlr->r_res1, 0x02010 + ATA_MV_EDMA_BASE(ch), work >> 32); 319 320 /* request queue in ptr */ 321 ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff); 322 323 /* request queue out ptr */ 324 ATA_OUTL(ctlr->r_res1, 0x02018 + ATA_MV_EDMA_BASE(ch), 0x0); 325 326 /* response queue base high */ 327 work += 1024; 328 ATA_OUTL(ctlr->r_res1, 0x0201c + ATA_MV_EDMA_BASE(ch), work >> 32); 329 330 /* response queue in ptr */ 331 ATA_OUTL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch), 0x0); 332 333 /* response queue out ptr */ 334 ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff); 335 336 /* clear SATA error register */ 337 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR)); 338 339 /* clear any outstanding error interrupts */ 340 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0); 341 342 /* unmask all error interrupts */ 343 ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0); 344 345 /* enable EDMA machinery */ 346 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001); 347 return 0; 348} 349 350static int 351ata_marvell_edma_ch_detach(device_t dev) 352{ 353 struct ata_channel *ch = device_get_softc(dev); 354 355 if (ch->dma.work_tag && ch->dma.work_map) 356 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 357 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 358 ata_dmafini(dev); 359 return (0); 360} 361 362static int 363ata_marvell_edma_status(device_t dev) 364{ 365 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 366 struct ata_channel *ch = device_get_softc(dev); 367 u_int32_t cause = ATA_INL(ctlr->r_res1, 0x01d60); 368 int shift = (ch->unit << 1) + (ch->unit > 3); 369 370 if (cause & (1 << shift)) { 371 372 /* clear interrupt(s) */ 373 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0); 374 375 /* do we have any PHY events ? */ 376 ata_sata_phy_check_events(dev, -1); 377 } 378 379 /* do we have any device action ? */ 380 return (cause & (2 << shift)); 381} 382 383/* must be called with ATA channel locked and state_mtx held */ 384static int 385ata_marvell_edma_begin_transaction(struct ata_request *request) 386{ 387 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 388 struct ata_channel *ch = device_get_softc(request->parent); 389 u_int32_t req_in; 390 u_int8_t *bytep; 391 int i; 392 int error, slot; 393 394 /* only DMA R/W goes through the EMDA machine */ 395 if (request->u.ata.command != ATA_READ_DMA && 396 request->u.ata.command != ATA_WRITE_DMA && 397 request->u.ata.command != ATA_READ_DMA48 && 398 request->u.ata.command != ATA_WRITE_DMA48) { 399 400 /* disable the EDMA machinery */ 401 if (ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001) 402 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002); 403 return ata_begin_transaction(request); 404 } 405 406 /* check sanity, setup SG list and DMA engine */ 407 if ((error = ch->dma.load(request, NULL, NULL))) { 408 device_printf(request->parent, "setting up DMA failed\n"); 409 request->result = error; 410 return ATA_OP_FINISHED; 411 } 412 413 /* get next free request queue slot */ 414 req_in = ATA_INL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch)); 415 slot = (((req_in & ~0xfffffc00) >> 5) + 0) & 0x1f; 416 bytep = (u_int8_t *)(ch->dma.work); 417 bytep += (slot << 5); 418 419 /* fill in this request */ 420 le32enc(bytep + 0 * sizeof(u_int32_t), 421 request->dma->sg_bus & 0xffffffff); 422 le32enc(bytep + 1 * sizeof(u_int32_t), 423 (u_int64_t)request->dma->sg_bus >> 32); 424 if (ctlr->chip->cfg2 != MV_6042 && ctlr->chip->cfg2 != MV_7042) { 425 le16enc(bytep + 4 * sizeof(u_int16_t), 426 (request->flags & ATA_R_READ ? 0x01 : 0x00) | (request->tag << 1)); 427 428 i = 10; 429 bytep[i++] = (request->u.ata.count >> 8) & 0xff; 430 bytep[i++] = 0x10 | ATA_COUNT; 431 bytep[i++] = request->u.ata.count & 0xff; 432 bytep[i++] = 0x10 | ATA_COUNT; 433 434 bytep[i++] = (request->u.ata.lba >> 24) & 0xff; 435 bytep[i++] = 0x10 | ATA_SECTOR; 436 bytep[i++] = request->u.ata.lba & 0xff; 437 bytep[i++] = 0x10 | ATA_SECTOR; 438 439 bytep[i++] = (request->u.ata.lba >> 32) & 0xff; 440 bytep[i++] = 0x10 | ATA_CYL_LSB; 441 bytep[i++] = (request->u.ata.lba >> 8) & 0xff; 442 bytep[i++] = 0x10 | ATA_CYL_LSB; 443 444 bytep[i++] = (request->u.ata.lba >> 40) & 0xff; 445 bytep[i++] = 0x10 | ATA_CYL_MSB; 446 bytep[i++] = (request->u.ata.lba >> 16) & 0xff; 447 bytep[i++] = 0x10 | ATA_CYL_MSB; 448 449 bytep[i++] = ATA_D_LBA | ATA_D_IBM | ((request->u.ata.lba >> 24) & 0xf); 450 bytep[i++] = 0x10 | ATA_DRIVE; 451 452 bytep[i++] = request->u.ata.command; 453 bytep[i++] = 0x90 | ATA_COMMAND; 454 } else { 455 le32enc(bytep + 2 * sizeof(u_int32_t), 456 (request->flags & ATA_R_READ ? 0x01 : 0x00) | (request->tag << 1)); 457 458 i = 16; 459 bytep[i++] = 0; 460 bytep[i++] = 0; 461 bytep[i++] = request->u.ata.command; 462 bytep[i++] = request->u.ata.feature & 0xff; 463 464 bytep[i++] = request->u.ata.lba & 0xff; 465 bytep[i++] = (request->u.ata.lba >> 8) & 0xff; 466 bytep[i++] = (request->u.ata.lba >> 16) & 0xff; 467 bytep[i++] = ATA_D_LBA | ATA_D_IBM | ((request->u.ata.lba >> 24) & 0x0f); 468 469 bytep[i++] = (request->u.ata.lba >> 24) & 0xff; 470 bytep[i++] = (request->u.ata.lba >> 32) & 0xff; 471 bytep[i++] = (request->u.ata.lba >> 40) & 0xff; 472 bytep[i++] = (request->u.ata.feature >> 8) & 0xff; 473 474 bytep[i++] = request->u.ata.count & 0xff; 475 bytep[i++] = (request->u.ata.count >> 8) & 0xff; 476 bytep[i++] = 0; 477 bytep[i++] = 0; 478 } 479 480 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 481 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 482 483 /* enable EDMA machinery if needed */ 484 if (!(ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) { 485 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001); 486 while (!(ATA_INL(ctlr->r_res1, 487 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) 488 DELAY(10); 489 } 490 491 /* tell EDMA it has a new request */ 492 slot = (((req_in & ~0xfffffc00) >> 5) + 1) & 0x1f; 493 req_in &= 0xfffffc00; 494 req_in += (slot << 5); 495 ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), req_in); 496 497 return ATA_OP_CONTINUES; 498} 499 500/* must be called with ATA channel locked and state_mtx held */ 501static int 502ata_marvell_edma_end_transaction(struct ata_request *request) 503{ 504 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 505 struct ata_channel *ch = device_get_softc(request->parent); 506 int offset = (ch->unit > 3 ? 0x30014 : 0x20014); 507 u_int32_t icr = ATA_INL(ctlr->r_res1, offset); 508 int res; 509 510 /* EDMA interrupt */ 511 if ((icr & (0x0001 << (ch->unit & 3)))) { 512 struct ata_marvell_response *response; 513 u_int32_t rsp_in, rsp_out; 514 int slot; 515 516 /* stop timeout */ 517 callout_stop(&request->callout); 518 519 /* get response ptr's */ 520 rsp_in = ATA_INL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch)); 521 rsp_out = ATA_INL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch)); 522 slot = (((rsp_in & ~0xffffff00) >> 3)) & 0x1f; 523 rsp_out &= 0xffffff00; 524 rsp_out += (slot << 3); 525 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 526 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 527 response = (struct ata_marvell_response *) 528 (ch->dma.work + 1024 + (slot << 3)); 529 530 /* record status for this request */ 531 request->status = response->dev_status; 532 request->error = 0; 533 534 /* ack response */ 535 ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), rsp_out); 536 537 /* update progress */ 538 if (!(request->status & ATA_S_ERROR) && 539 !(request->flags & ATA_R_TIMEOUT)) 540 request->donecount = request->bytecount; 541 542 /* unload SG list */ 543 ch->dma.unload(request); 544 545 res = ATA_OP_FINISHED; 546 } 547 548 /* legacy ATA interrupt */ 549 else { 550 res = ata_end_transaction(request); 551 } 552 553 /* ack interrupt */ 554 ATA_OUTL(ctlr->r_res1, offset, ~(icr & (0x0101 << (ch->unit & 3)))); 555 return res; 556} 557 558static void 559ata_marvell_edma_reset(device_t dev) 560{ 561 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 562 struct ata_channel *ch = device_get_softc(dev); 563 564 /* disable the EDMA machinery */ 565 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002); 566 while ((ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) 567 DELAY(10); 568 569 /* clear SATA error register */ 570 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR)); 571 572 /* clear any outstanding error interrupts */ 573 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0); 574 575 /* unmask all error interrupts */ 576 ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0); 577 578 /* enable channel and test for devices */ 579 if (ata_sata_phy_reset(dev, -1, 1)) 580 ata_generic_reset(dev); 581 else 582 ch->devices = 0; 583 584 /* enable EDMA machinery */ 585 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001); 586} 587 588static void 589ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, 590 int error) 591{ 592 struct ata_dmasetprd_args *args = xsc; 593 struct ata_marvell_dma_prdentry *prd = args->dmatab; 594 int i; 595 596 if ((args->error = error)) 597 return; 598 599 for (i = 0; i < nsegs; i++) { 600 prd[i].addrlo = htole32(segs[i].ds_addr); 601 prd[i].count = htole32(segs[i].ds_len); 602 prd[i].addrhi = htole32((u_int64_t)segs[i].ds_addr >> 32); 603 prd[i].reserved = 0; 604 } 605 prd[i - 1].count |= htole32(ATA_DMA_EOT); 606 KASSERT(nsegs <= ATA_DMA_ENTRIES, ("too many DMA segment entries\n")); 607 args->nsegs = nsegs; 608} 609 610static void 611ata_marvell_edma_dmainit(device_t dev) 612{ 613 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 614 struct ata_channel *ch = device_get_softc(dev); 615 616 /* note start and stop are not used here */ 617 ch->dma.setprd = ata_marvell_edma_dmasetprd; 618 619 /* if 64bit support present adjust max address used */ 620 if (ATA_INL(ctlr->r_res1, 0x00d00) & 0x00000004) 621 ch->dma.max_address = BUS_SPACE_MAXADDR; 622 623 /* chip does not reliably do 64K DMA transfers */ 624 if (ctlr->chip->cfg2 == MV_50XX || ctlr->chip->cfg2 == MV_60XX) 625 ch->dma.max_iosize = 64 * DEV_BSIZE; 626 ata_dmainit(dev); 627} 628 629ATA_DECLARE_DRIVER(ata_marvell); 630