1/*- 2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD$"); 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/kernel.h> 33#include <sys/endian.h> 34#include <sys/ata.h> 35#include <sys/conf.h> 36#include <sys/ctype.h> 37#include <sys/bus.h> 38#include <sys/sema.h> 39#include <sys/taskqueue.h> 40#include <vm/uma.h> 41#include <machine/bus.h> 42#include <sys/rman.h> 43#include <dev/ata/ata-all.h> 44#include <dev/ata/ata-pci.h> 45#include <ata_if.h> 46 47/* prototypes */ 48static int ata_generic_status(device_t dev); 49static int ata_wait(struct ata_channel *ch, int unit, u_int8_t); 50static void ata_pio_read(struct ata_request *, int); 51static void ata_pio_write(struct ata_request *, int); 52static void ata_tf_read(struct ata_request *); 53static void ata_tf_write(struct ata_request *); 54 55/* 56 * low level ATA functions 57 */ 58void 59ata_generic_hw(device_t dev) 60{ 61 struct ata_channel *ch = device_get_softc(dev); 62 63 ch->hw.begin_transaction = ata_begin_transaction; 64 ch->hw.end_transaction = ata_end_transaction; 65 ch->hw.status = ata_generic_status; 66 ch->hw.softreset = NULL; 67 ch->hw.command = ata_generic_command; 68 ch->hw.tf_read = ata_tf_read; 69 ch->hw.tf_write = ata_tf_write; 70 ch->hw.pm_read = NULL; 71 ch->hw.pm_write = NULL; 72} 73 74/* must be called with ATA channel locked and state_mtx held */ 75int 76ata_begin_transaction(struct ata_request *request) 77{ 78 struct ata_channel *ch = device_get_softc(request->parent); 79 int dummy, error; 80 81 ATA_DEBUG_RQ(request, "begin transaction"); 82 83 /* disable ATAPI DMA writes if HW doesn't support it */ 84 if ((ch->flags & ATA_NO_ATAPI_DMA) && 85 (request->flags & ATA_R_ATAPI) == ATA_R_ATAPI) 86 request->flags &= ~ATA_R_DMA; 87 if ((ch->flags & ATA_ATAPI_DMA_RO) && 88 ((request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)) == 89 (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE))) 90 request->flags &= ~ATA_R_DMA; 91 92 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA)) { 93 94 /* ATA PIO data transfer and control commands */ 95 default: 96 { 97 /* record command direction here as our request might be gone later */ 98 int write = (request->flags & ATA_R_WRITE); 99 100 /* issue command */ 101 if (ch->hw.command(request)) { 102 device_printf(request->parent, "error issuing %s command\n", 103 ata_cmd2str(request)); 104 request->result = EIO; 105 goto begin_finished; 106 } 107 108 /* device reset doesn't interrupt */ 109 if (request->u.ata.command == ATA_DEVICE_RESET) { 110 111 int timeout = 1000000; 112 do { 113 DELAY(10); 114 request->status = ATA_IDX_INB(ch, ATA_STATUS); 115 } while (request->status & ATA_S_BUSY && timeout--); 116 if (request->status & ATA_S_ERROR) 117 request->error = ATA_IDX_INB(ch, ATA_ERROR); 118 ch->hw.tf_read(request); 119 goto begin_finished; 120 } 121 122 /* if write command output the data */ 123 if (write) { 124 if (ata_wait(ch, request->unit, (ATA_S_READY | ATA_S_DRQ)) < 0) { 125 device_printf(request->parent, 126 "timeout waiting for write DRQ\n"); 127 request->result = EIO; 128 goto begin_finished; 129 } 130 ata_pio_write(request, request->transfersize); 131 } 132 } 133 goto begin_continue; 134 135 /* ATA DMA data transfer commands */ 136 case ATA_R_DMA: 137 /* check sanity, setup SG list and DMA engine */ 138 if ((error = ch->dma.load(request, NULL, &dummy))) { 139 device_printf(request->parent, "setting up DMA failed\n"); 140 request->result = error; 141 goto begin_finished; 142 } 143 144 /* start DMA engine if necessary */ 145 if ((ch->flags & ATA_DMA_BEFORE_CMD) && 146 ch->dma.start && ch->dma.start(request)) { 147 device_printf(request->parent, "error starting DMA\n"); 148 request->result = EIO; 149 goto begin_finished; 150 } 151 152 /* issue command */ 153 if (ch->hw.command(request)) { 154 device_printf(request->parent, "error issuing %s command\n", 155 ata_cmd2str(request)); 156 request->result = EIO; 157 goto begin_finished; 158 } 159 160 /* start DMA engine */ 161 if (!(ch->flags & ATA_DMA_BEFORE_CMD) && 162 ch->dma.start && ch->dma.start(request)) { 163 device_printf(request->parent, "error starting DMA\n"); 164 request->result = EIO; 165 goto begin_finished; 166 } 167 goto begin_continue; 168 169 /* ATAPI PIO commands */ 170 case ATA_R_ATAPI: 171 /* is this just a POLL DSC command ? */ 172 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { 173 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit)); 174 DELAY(10); 175 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC)) 176 request->result = EBUSY; 177 goto begin_finished; 178 } 179 180 /* start ATAPI operation */ 181 if (ch->hw.command(request)) { 182 device_printf(request->parent, "error issuing ATA PACKET command\n"); 183 request->result = EIO; 184 goto begin_finished; 185 } 186 goto begin_continue; 187 188 /* ATAPI DMA commands */ 189 case ATA_R_ATAPI|ATA_R_DMA: 190 /* is this just a POLL DSC command ? */ 191 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { 192 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit)); 193 DELAY(10); 194 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC)) 195 request->result = EBUSY; 196 goto begin_finished; 197 } 198 199 /* check sanity, setup SG list and DMA engine */ 200 if ((error = ch->dma.load(request, NULL, &dummy))) { 201 device_printf(request->parent, "setting up DMA failed\n"); 202 request->result = error; 203 goto begin_finished; 204 } 205 206 /* start ATAPI operation */ 207 if (ch->hw.command(request)) { 208 device_printf(request->parent, "error issuing ATA PACKET command\n"); 209 request->result = EIO; 210 goto begin_finished; 211 } 212 213 /* start DMA engine */ 214 if (ch->dma.start && ch->dma.start(request)) { 215 request->result = EIO; 216 goto begin_finished; 217 } 218 goto begin_continue; 219 } 220 /* NOT REACHED */ 221 printf("ata_begin_transaction OOPS!!!\n"); 222 223begin_finished: 224 if (ch->dma.unload) { 225 ch->dma.unload(request); 226 } 227 return ATA_OP_FINISHED; 228 229begin_continue: 230 callout_reset(&request->callout, request->timeout * hz, 231 (timeout_t*)ata_timeout, request); 232 return ATA_OP_CONTINUES; 233} 234 235/* must be called with ATA channel locked and state_mtx held */ 236int 237ata_end_transaction(struct ata_request *request) 238{ 239 struct ata_channel *ch = device_get_softc(request->parent); 240 int length; 241 242 ATA_DEBUG_RQ(request, "end transaction"); 243 244 /* clear interrupt and get status */ 245 request->status = ATA_IDX_INB(ch, ATA_STATUS); 246 247 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_CONTROL)) { 248 249 /* ATA PIO data transfer and control commands */ 250 default: 251 252 /* on timeouts we have no data or anything so just return */ 253 if (request->flags & ATA_R_TIMEOUT) 254 goto end_finished; 255 256 /* Read back registers to the request struct. */ 257 if ((request->status & ATA_S_ERROR) || 258 (request->flags & (ATA_R_CONTROL | ATA_R_NEEDRESULT))) { 259 ch->hw.tf_read(request); 260 } 261 262 /* if we got an error we are done with the HW */ 263 if (request->status & ATA_S_ERROR) { 264 request->error = ATA_IDX_INB(ch, ATA_ERROR); 265 goto end_finished; 266 } 267 268 /* are we moving data ? */ 269 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 270 271 /* if read data get it */ 272 if (request->flags & ATA_R_READ) { 273 int flags = ATA_S_DRQ; 274 275 if (request->u.ata.command != ATA_ATAPI_IDENTIFY) 276 flags |= ATA_S_READY; 277 if (ata_wait(ch, request->unit, flags) < 0) { 278 device_printf(request->parent, 279 "timeout waiting for read DRQ\n"); 280 request->result = EIO; 281 goto end_finished; 282 } 283 ata_pio_read(request, request->transfersize); 284 } 285 286 /* update how far we've gotten */ 287 request->donecount += request->transfersize; 288 289 /* do we need a scoop more ? */ 290 if (request->bytecount > request->donecount) { 291 292 /* set this transfer size according to HW capabilities */ 293 request->transfersize = 294 min((request->bytecount - request->donecount), 295 request->transfersize); 296 297 /* if data write command, output the data */ 298 if (request->flags & ATA_R_WRITE) { 299 300 /* if we get an error here we are done with the HW */ 301 if (ata_wait(ch, request->unit, (ATA_S_READY | ATA_S_DRQ)) < 0) { 302 device_printf(request->parent, 303 "timeout waiting for write DRQ\n"); 304 request->status = ATA_IDX_INB(ch, ATA_STATUS); 305 goto end_finished; 306 } 307 308 /* output data and return waiting for new interrupt */ 309 ata_pio_write(request, request->transfersize); 310 goto end_continue; 311 } 312 313 /* if data read command, return & wait for interrupt */ 314 if (request->flags & ATA_R_READ) 315 goto end_continue; 316 } 317 } 318 /* done with HW */ 319 goto end_finished; 320 321 /* ATA DMA data transfer commands */ 322 case ATA_R_DMA: 323 324 /* stop DMA engine and get status */ 325 if (ch->dma.stop) 326 request->dma->status = ch->dma.stop(request); 327 328 /* did we get error or data */ 329 if (request->status & ATA_S_ERROR) 330 request->error = ATA_IDX_INB(ch, ATA_ERROR); 331 else if (request->dma->status & ATA_BMSTAT_ERROR) 332 request->status |= ATA_S_ERROR; 333 else if (!(request->flags & ATA_R_TIMEOUT)) 334 request->donecount = request->bytecount; 335 336 /* Read back registers to the request struct. */ 337 if ((request->status & ATA_S_ERROR) || 338 (request->flags & (ATA_R_CONTROL | ATA_R_NEEDRESULT))) { 339 ch->hw.tf_read(request); 340 } 341 342 /* release SG list etc */ 343 ch->dma.unload(request); 344 345 /* done with HW */ 346 goto end_finished; 347 348 /* ATAPI PIO commands */ 349 case ATA_R_ATAPI: 350 length = ATA_IDX_INB(ch, ATA_CYL_LSB)|(ATA_IDX_INB(ch, ATA_CYL_MSB)<<8); 351 352 /* on timeouts we have no data or anything so just return */ 353 if (request->flags & ATA_R_TIMEOUT) 354 goto end_finished; 355 356 switch ((ATA_IDX_INB(ch, ATA_IREASON) & (ATA_I_CMD | ATA_I_IN)) | 357 (request->status & ATA_S_DRQ)) { 358 359 case ATAPI_P_CMDOUT: 360 /* this seems to be needed for some (slow) devices */ 361 DELAY(10); 362 363 if (!(request->status & ATA_S_DRQ)) { 364 device_printf(request->parent, "command interrupt without DRQ\n"); 365 request->status = ATA_S_ERROR; 366 goto end_finished; 367 } 368 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb, 369 (request->flags & ATA_R_ATAPI16) ? 8 : 6); 370 /* return wait for interrupt */ 371 goto end_continue; 372 373 case ATAPI_P_WRITE: 374 if (request->flags & ATA_R_READ) { 375 request->status = ATA_S_ERROR; 376 device_printf(request->parent, 377 "%s trying to write on read buffer\n", 378 ata_cmd2str(request)); 379 goto end_finished; 380 } 381 ata_pio_write(request, length); 382 request->donecount += length; 383 384 /* set next transfer size according to HW capabilities */ 385 request->transfersize = min((request->bytecount-request->donecount), 386 request->transfersize); 387 /* return wait for interrupt */ 388 goto end_continue; 389 390 case ATAPI_P_READ: 391 if (request->flags & ATA_R_WRITE) { 392 request->status = ATA_S_ERROR; 393 device_printf(request->parent, 394 "%s trying to read on write buffer\n", 395 ata_cmd2str(request)); 396 goto end_finished; 397 } 398 ata_pio_read(request, length); 399 request->donecount += length; 400 401 /* set next transfer size according to HW capabilities */ 402 request->transfersize = min((request->bytecount-request->donecount), 403 request->transfersize); 404 /* return wait for interrupt */ 405 goto end_continue; 406 407 case ATAPI_P_DONEDRQ: 408 device_printf(request->parent, 409 "WARNING - %s DONEDRQ non conformant device\n", 410 ata_cmd2str(request)); 411 if (request->flags & ATA_R_READ) { 412 ata_pio_read(request, length); 413 request->donecount += length; 414 } 415 else if (request->flags & ATA_R_WRITE) { 416 ata_pio_write(request, length); 417 request->donecount += length; 418 } 419 else 420 request->status = ATA_S_ERROR; 421 /* FALLTHROUGH */ 422 423 case ATAPI_P_ABORT: 424 case ATAPI_P_DONE: 425 if (request->status & (ATA_S_ERROR | ATA_S_DWF)) 426 request->error = ATA_IDX_INB(ch, ATA_ERROR); 427 goto end_finished; 428 429 default: 430 device_printf(request->parent, "unknown transfer phase\n"); 431 request->status = ATA_S_ERROR; 432 } 433 434 /* done with HW */ 435 goto end_finished; 436 437 /* ATAPI DMA commands */ 438 case ATA_R_ATAPI|ATA_R_DMA: 439 440 /* stop DMA engine and get status */ 441 if (ch->dma.stop) 442 request->dma->status = ch->dma.stop(request); 443 444 /* did we get error or data */ 445 if (request->status & (ATA_S_ERROR | ATA_S_DWF)) 446 request->error = ATA_IDX_INB(ch, ATA_ERROR); 447 else if (request->dma->status & ATA_BMSTAT_ERROR) 448 request->status |= ATA_S_ERROR; 449 else if (!(request->flags & ATA_R_TIMEOUT)) 450 request->donecount = request->bytecount; 451 452 /* release SG list etc */ 453 ch->dma.unload(request); 454 455 /* done with HW */ 456 goto end_finished; 457 } 458 /* NOT REACHED */ 459 printf("ata_end_transaction OOPS!!\n"); 460 461end_finished: 462 callout_stop(&request->callout); 463 return ATA_OP_FINISHED; 464 465end_continue: 466 return ATA_OP_CONTINUES; 467} 468 469/* must be called with ATA channel locked and state_mtx held */ 470void 471ata_generic_reset(device_t dev) 472{ 473 struct ata_channel *ch = device_get_softc(dev); 474 475 u_int8_t ostat0 = 0, stat0 = 0, ostat1 = 0, stat1 = 0; 476 u_int8_t err = 0, lsb = 0, msb = 0; 477 int mask = 0, timeout; 478 479 /* do we have any signs of ATA/ATAPI HW being present ? */ 480 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_MASTER)); 481 DELAY(10); 482 ostat0 = ATA_IDX_INB(ch, ATA_STATUS); 483 if (((ostat0 & 0xf8) != 0xf8 || (ch->flags & ATA_KNOWN_PRESENCE)) && 484 ostat0 != 0xa5) { 485 stat0 = ATA_S_BUSY; 486 mask |= 0x01; 487 } 488 489 /* in some setups we dont want to test for a slave */ 490 if (!(ch->flags & ATA_NO_SLAVE)) { 491 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_SLAVE)); 492 DELAY(10); 493 ostat1 = ATA_IDX_INB(ch, ATA_STATUS); 494 if (((ostat1 & 0xf8) != 0xf8 || (ch->flags & ATA_KNOWN_PRESENCE)) && 495 ostat1 != 0xa5) { 496 stat1 = ATA_S_BUSY; 497 mask |= 0x02; 498 } 499 } 500 501 if (bootverbose) 502 device_printf(dev, "reset tp1 mask=%02x ostat0=%02x ostat1=%02x\n", 503 mask, ostat0, ostat1); 504 505 /* if nothing showed up there is no need to get any further */ 506 /* XXX SOS is that too strong?, we just might lose devices here */ 507 ch->devices = 0; 508 if (!mask) 509 return; 510 511 /* reset (both) devices on this channel */ 512 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_MASTER)); 513 DELAY(10); 514 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS | ATA_A_RESET); 515 ata_udelay(10000); 516 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS); 517 ata_udelay(100000); 518 ATA_IDX_INB(ch, ATA_ERROR); 519 520 /* wait for BUSY to go inactive */ 521 for (timeout = 0; timeout < 310; timeout++) { 522 if ((mask & 0x01) && (stat0 & ATA_S_BUSY)) { 523 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(ATA_MASTER)); 524 DELAY(10); 525 if (ch->flags & ATA_STATUS_IS_LONG) 526 stat0 = ATA_IDX_INL(ch, ATA_STATUS) & 0xff; 527 else 528 stat0 = ATA_IDX_INB(ch, ATA_STATUS); 529 err = ATA_IDX_INB(ch, ATA_ERROR); 530 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); 531 msb = ATA_IDX_INB(ch, ATA_CYL_MSB); 532 if (bootverbose) 533 device_printf(dev, 534 "stat0=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n", 535 stat0, err, lsb, msb); 536 if (stat0 == err && lsb == err && msb == err && 537 timeout > (stat0 & ATA_S_BUSY ? 100 : 10)) 538 mask &= ~0x01; 539 if (!(stat0 & ATA_S_BUSY)) { 540 if ((err & 0x7f) == ATA_E_ILI) { 541 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) { 542 ch->devices |= ATA_ATAPI_MASTER; 543 } 544 else if (lsb == 0 && msb == 0 && (stat0 & ATA_S_READY)) { 545 ch->devices |= ATA_ATA_MASTER; 546 } 547 } 548 else if ((stat0 & 0x0f) && err == lsb && err == msb) { 549 stat0 |= ATA_S_BUSY; 550 } 551 } 552 } 553 554 if ((mask & 0x02) && (stat1 & ATA_S_BUSY) && 555 !((mask & 0x01) && (stat0 & ATA_S_BUSY))) { 556 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(ATA_SLAVE)); 557 DELAY(10); 558 if (ch->flags & ATA_STATUS_IS_LONG) 559 stat1 = ATA_IDX_INL(ch, ATA_STATUS) & 0xff; 560 else 561 stat1 = ATA_IDX_INB(ch, ATA_STATUS); 562 err = ATA_IDX_INB(ch, ATA_ERROR); 563 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); 564 msb = ATA_IDX_INB(ch, ATA_CYL_MSB); 565 if (bootverbose) 566 device_printf(dev, 567 "stat1=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n", 568 stat1, err, lsb, msb); 569 if (stat1 == err && lsb == err && msb == err && 570 timeout > (stat1 & ATA_S_BUSY ? 100 : 10)) 571 mask &= ~0x02; 572 if (!(stat1 & ATA_S_BUSY)) { 573 if ((err & 0x7f) == ATA_E_ILI) { 574 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) { 575 ch->devices |= ATA_ATAPI_SLAVE; 576 } 577 else if (lsb == 0 && msb == 0 && (stat1 & ATA_S_READY)) { 578 ch->devices |= ATA_ATA_SLAVE; 579 } 580 } 581 else if ((stat1 & 0x0f) && err == lsb && err == msb) { 582 stat1 |= ATA_S_BUSY; 583 } 584 } 585 } 586 587 if ((ch->flags & ATA_KNOWN_PRESENCE) == 0 && 588 timeout > ((mask == 0x03) ? 20 : 10)) { 589 if ((mask & 0x01) && stat0 == 0xff) 590 mask &= ~0x01; 591 if ((mask & 0x02) && stat1 == 0xff) 592 mask &= ~0x02; 593 } 594 if (((mask & 0x01) == 0 || !(stat0 & ATA_S_BUSY)) && 595 ((mask & 0x02) == 0 || !(stat1 & ATA_S_BUSY))) 596 break; 597 ata_udelay(100000); 598 } 599 600 if (bootverbose) 601 device_printf(dev, "reset tp2 stat0=%02x stat1=%02x devices=0x%x\n", 602 stat0, stat1, ch->devices); 603} 604 605/* must be called with ATA channel locked and state_mtx held */ 606static int 607ata_generic_status(device_t dev) 608{ 609 struct ata_channel *ch = device_get_softc(dev); 610 611 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) { 612 DELAY(100); 613 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) 614 return 0; 615 } 616 return 1; 617} 618 619static int 620ata_wait(struct ata_channel *ch, int unit, u_int8_t mask) 621{ 622 u_int8_t status; 623 int timeout = 0; 624 625 DELAY(1); 626 627 /* wait at max 1 second for device to get !BUSY */ 628 while (timeout < 1000000) { 629 status = ATA_IDX_INB(ch, ATA_ALTSTAT); 630 631 /* if drive fails status, reselect the drive and try again */ 632 if (status == 0xff) { 633 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(unit)); 634 timeout += 1000; 635 DELAY(1000); 636 continue; 637 } 638 639 /* are we done ? */ 640 if (!(status & ATA_S_BUSY)) 641 break; 642 643 if (timeout > 1000) { 644 timeout += 1000; 645 DELAY(1000); 646 } 647 else { 648 timeout += 10; 649 DELAY(10); 650 } 651 } 652 if (timeout >= 1000000) 653 return -2; 654 if (!mask) 655 return (status & ATA_S_ERROR); 656 657 DELAY(1); 658 659 /* wait 50 msec for bits wanted */ 660 timeout = 5000; 661 while (timeout--) { 662 status = ATA_IDX_INB(ch, ATA_ALTSTAT); 663 if ((status & mask) == mask) 664 return (status & ATA_S_ERROR); 665 DELAY(10); 666 } 667 return -3; 668} 669 670int 671ata_generic_command(struct ata_request *request) 672{ 673 struct ata_channel *ch = device_get_softc(request->parent); 674 675 /* select device */ 676 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit)); 677 678 /* ready to issue command ? */ 679 if (ata_wait(ch, request->unit, 0) < 0) { 680 device_printf(request->parent, "timeout waiting to issue command\n"); 681 request->flags |= ATA_R_TIMEOUT; 682 return (-1); 683 } 684 685 /* enable interrupt */ 686 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT); 687 688 if (request->flags & ATA_R_ATAPI) { 689 int timeout = 5000; 690 int res; 691 692 /* issue packet command to controller */ 693 if (request->flags & ATA_R_DMA) { 694 ATA_IDX_OUTB(ch, ATA_FEATURE, ATA_F_DMA); 695 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 0); 696 ATA_IDX_OUTB(ch, ATA_CYL_MSB, 0); 697 } 698 else { 699 ATA_IDX_OUTB(ch, ATA_FEATURE, 0); 700 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->transfersize); 701 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->transfersize >> 8); 702 } 703 ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_PACKET_CMD); 704 705 /* command interrupt device ? just return and wait for interrupt */ 706 if (request->flags & ATA_R_ATAPI_INTR) 707 return (0); 708 709 /* command processed ? */ 710 res = ata_wait(ch, request->unit, 0); 711 if (res != 0) { 712 if (res < 0) { 713 device_printf(request->parent, 714 "timeout waiting for PACKET command\n"); 715 request->flags |= ATA_R_TIMEOUT; 716 } 717 return (-1); 718 } 719 /* wait for ready to write ATAPI command block */ 720 while (timeout--) { 721 int reason = ATA_IDX_INB(ch, ATA_IREASON); 722 int status = ATA_IDX_INB(ch, ATA_STATUS); 723 724 if (((reason & (ATA_I_CMD | ATA_I_IN)) | 725 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT) 726 break; 727 DELAY(20); 728 } 729 if (timeout <= 0) { 730 device_printf(request->parent, 731 "timeout waiting for ATAPI ready\n"); 732 request->flags |= ATA_R_TIMEOUT; 733 return (-1); 734 } 735 736 /* this seems to be needed for some (slow) devices */ 737 DELAY(10); 738 739 /* output command block */ 740 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb, 741 (request->flags & ATA_R_ATAPI16) ? 8 : 6); 742 } 743 else { 744 ch->hw.tf_write(request); 745 746 /* issue command to controller */ 747 ATA_IDX_OUTB(ch, ATA_COMMAND, request->u.ata.command); 748 } 749 return (0); 750} 751 752static void 753ata_tf_read(struct ata_request *request) 754{ 755 struct ata_channel *ch = device_get_softc(request->parent); 756 757 if (request->flags & ATA_R_48BIT) { 758 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT | ATA_A_HOB); 759 request->u.ata.count = (ATA_IDX_INB(ch, ATA_COUNT) << 8); 760 request->u.ata.lba = 761 ((u_int64_t)(ATA_IDX_INB(ch, ATA_SECTOR)) << 24) | 762 ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_LSB)) << 32) | 763 ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_MSB)) << 40); 764 765 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT); 766 request->u.ata.count |= ATA_IDX_INB(ch, ATA_COUNT); 767 request->u.ata.lba |= 768 (ATA_IDX_INB(ch, ATA_SECTOR) | 769 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) | 770 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16)); 771 } 772 else { 773 request->u.ata.count = ATA_IDX_INB(ch, ATA_COUNT); 774 request->u.ata.lba = ATA_IDX_INB(ch, ATA_SECTOR) | 775 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) | 776 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16) | 777 ((ATA_IDX_INB(ch, ATA_DRIVE) & 0xf) << 24); 778 } 779} 780 781static void 782ata_tf_write(struct ata_request *request) 783{ 784 struct ata_channel *ch = device_get_softc(request->parent); 785 786 if (request->flags & ATA_R_48BIT) { 787 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature >> 8); 788 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature); 789 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count >> 8); 790 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count); 791 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba >> 24); 792 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba); 793 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 32); 794 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 795 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 40); 796 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 797 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(request->unit)); 798 } 799 else { 800 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature); 801 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count); 802 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba); 803 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 804 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 805 ATA_IDX_OUTB(ch, ATA_DRIVE, 806 ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) | 807 ((request->u.ata.lba >> 24) & 0x0f)); 808 } 809} 810 811static void 812ata_pio_read(struct ata_request *request, int length) 813{ 814 struct ata_channel *ch = device_get_softc(request->parent); 815 uint8_t *addr; 816 int size = min(request->transfersize, length); 817 int resid; 818 uint8_t buf[2] __aligned(sizeof(int16_t)); 819#ifndef __NO_STRICT_ALIGNMENT 820 int i; 821#endif 822 823 addr = (uint8_t *)request->data + request->donecount; 824 if (__predict_false(ch->flags & ATA_USE_16BIT || 825 (size % sizeof(int32_t)) || ((uintptr_t)addr % sizeof(int32_t)))) { 826#ifndef __NO_STRICT_ALIGNMENT 827 if (__predict_false((uintptr_t)addr % sizeof(int16_t))) { 828 for (i = 0, resid = size & ~1; resid > 0; resid -= 829 sizeof(int16_t)) { 830 *(uint16_t *)&buf = ATA_IDX_INW_STRM(ch, ATA_DATA); 831 addr[i++] = buf[0]; 832 addr[i++] = buf[1]; 833 } 834 } else 835#endif 836 ATA_IDX_INSW_STRM(ch, ATA_DATA, (void*)addr, size / 837 sizeof(int16_t)); 838 if (size & 1) { 839 *(uint16_t *)&buf = ATA_IDX_INW_STRM(ch, ATA_DATA); 840 (addr + (size & ~1))[0] = buf[0]; 841 } 842 } else 843 ATA_IDX_INSL_STRM(ch, ATA_DATA, (void*)addr, size / sizeof(int32_t)); 844 845 if (request->transfersize < length) { 846 device_printf(request->parent, "WARNING - %s read data overrun %d>%d\n", 847 ata_cmd2str(request), length, request->transfersize); 848 for (resid = request->transfersize + (size & 1); resid < length; 849 resid += sizeof(int16_t)) 850 ATA_IDX_INW(ch, ATA_DATA); 851 } 852} 853 854static void 855ata_pio_write(struct ata_request *request, int length) 856{ 857 struct ata_channel *ch = device_get_softc(request->parent); 858 uint8_t *addr; 859 int size = min(request->transfersize, length); 860 int resid; 861 uint8_t buf[2] __aligned(sizeof(int16_t)); 862#ifndef __NO_STRICT_ALIGNMENT 863 int i; 864#endif 865 866 size = min(request->transfersize, length); 867 addr = (uint8_t *)request->data + request->donecount; 868 if (__predict_false(ch->flags & ATA_USE_16BIT || 869 (size % sizeof(int32_t)) || ((uintptr_t)addr % sizeof(int32_t)))) { 870#ifndef __NO_STRICT_ALIGNMENT 871 if (__predict_false((uintptr_t)addr % sizeof(int16_t))) { 872 for (i = 0, resid = size & ~1; resid > 0; resid -= 873 sizeof(int16_t)) { 874 buf[0] = addr[i++]; 875 buf[1] = addr[i++]; 876 ATA_IDX_OUTW_STRM(ch, ATA_DATA, *(uint16_t *)&buf); 877 } 878 } else 879#endif 880 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (void*)addr, size / 881 sizeof(int16_t)); 882 if (size & 1) { 883 buf[0] = (addr + (size & ~1))[0]; 884 ATA_IDX_OUTW_STRM(ch, ATA_DATA, *(uint16_t *)&buf); 885 } 886 } else 887 ATA_IDX_OUTSL_STRM(ch, ATA_DATA, (void*)addr, size / sizeof(int32_t)); 888 889 if (request->transfersize < length) { 890 device_printf(request->parent, "WARNING - %s write data underrun %d>%d\n", 891 ata_cmd2str(request), length, request->transfersize); 892 for (resid = request->transfersize + (size & 1); resid < length; 893 resid += sizeof(int16_t)) 894 ATA_IDX_OUTW(ch, ATA_DATA, 0); 895 } 896} 897