1/* 2 * DO NOT EDIT - This file is automatically generated 3 * from the following source files: 4 * 5 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.seq#58 $ 6 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.reg#40 $ 7 * 8 * $FreeBSD$ 9 */ 10typedef int (ahc_reg_print_t)(u_int, u_int *, u_int); 11typedef struct ahc_reg_parse_entry { 12 char *name; 13 uint8_t value; 14 uint8_t mask; 15} ahc_reg_parse_entry_t; 16 17#if AIC_DEBUG_REGISTERS 18ahc_reg_print_t ahc_scsiseq_print; 19#else 20#define ahc_scsiseq_print(regvalue, cur_col, wrap) \ 21 ahc_print_register(NULL, 0, "SCSISEQ", 0x00, regvalue, cur_col, wrap) 22#endif 23 24#if AIC_DEBUG_REGISTERS 25ahc_reg_print_t ahc_sxfrctl0_print; 26#else 27#define ahc_sxfrctl0_print(regvalue, cur_col, wrap) \ 28 ahc_print_register(NULL, 0, "SXFRCTL0", 0x01, regvalue, cur_col, wrap) 29#endif 30 31#if AIC_DEBUG_REGISTERS 32ahc_reg_print_t ahc_sxfrctl1_print; 33#else 34#define ahc_sxfrctl1_print(regvalue, cur_col, wrap) \ 35 ahc_print_register(NULL, 0, "SXFRCTL1", 0x02, regvalue, cur_col, wrap) 36#endif 37 38#if AIC_DEBUG_REGISTERS 39ahc_reg_print_t ahc_scsisigi_print; 40#else 41#define ahc_scsisigi_print(regvalue, cur_col, wrap) \ 42 ahc_print_register(NULL, 0, "SCSISIGI", 0x03, regvalue, cur_col, wrap) 43#endif 44 45#if AIC_DEBUG_REGISTERS 46ahc_reg_print_t ahc_scsisigo_print; 47#else 48#define ahc_scsisigo_print(regvalue, cur_col, wrap) \ 49 ahc_print_register(NULL, 0, "SCSISIGO", 0x03, regvalue, cur_col, wrap) 50#endif 51 52#if AIC_DEBUG_REGISTERS 53ahc_reg_print_t ahc_scsirate_print; 54#else 55#define ahc_scsirate_print(regvalue, cur_col, wrap) \ 56 ahc_print_register(NULL, 0, "SCSIRATE", 0x04, regvalue, cur_col, wrap) 57#endif 58 59#if AIC_DEBUG_REGISTERS 60ahc_reg_print_t ahc_scsiid_print; 61#else 62#define ahc_scsiid_print(regvalue, cur_col, wrap) \ 63 ahc_print_register(NULL, 0, "SCSIID", 0x05, regvalue, cur_col, wrap) 64#endif 65 66#if AIC_DEBUG_REGISTERS 67ahc_reg_print_t ahc_scsidatl_print; 68#else 69#define ahc_scsidatl_print(regvalue, cur_col, wrap) \ 70 ahc_print_register(NULL, 0, "SCSIDATL", 0x06, regvalue, cur_col, wrap) 71#endif 72 73#if AIC_DEBUG_REGISTERS 74ahc_reg_print_t ahc_scsidath_print; 75#else 76#define ahc_scsidath_print(regvalue, cur_col, wrap) \ 77 ahc_print_register(NULL, 0, "SCSIDATH", 0x07, regvalue, cur_col, wrap) 78#endif 79 80#if AIC_DEBUG_REGISTERS 81ahc_reg_print_t ahc_optionmode_print; 82#else 83#define ahc_optionmode_print(regvalue, cur_col, wrap) \ 84 ahc_print_register(NULL, 0, "OPTIONMODE", 0x08, regvalue, cur_col, wrap) 85#endif 86 87#if AIC_DEBUG_REGISTERS 88ahc_reg_print_t ahc_stcnt_print; 89#else 90#define ahc_stcnt_print(regvalue, cur_col, wrap) \ 91 ahc_print_register(NULL, 0, "STCNT", 0x08, regvalue, cur_col, wrap) 92#endif 93 94#if AIC_DEBUG_REGISTERS 95ahc_reg_print_t ahc_targcrccnt_print; 96#else 97#define ahc_targcrccnt_print(regvalue, cur_col, wrap) \ 98 ahc_print_register(NULL, 0, "TARGCRCCNT", 0x0a, regvalue, cur_col, wrap) 99#endif 100 101#if AIC_DEBUG_REGISTERS 102ahc_reg_print_t ahc_clrsint0_print; 103#else 104#define ahc_clrsint0_print(regvalue, cur_col, wrap) \ 105 ahc_print_register(NULL, 0, "CLRSINT0", 0x0b, regvalue, cur_col, wrap) 106#endif 107 108#if AIC_DEBUG_REGISTERS 109ahc_reg_print_t ahc_sstat0_print; 110#else 111#define ahc_sstat0_print(regvalue, cur_col, wrap) \ 112 ahc_print_register(NULL, 0, "SSTAT0", 0x0b, regvalue, cur_col, wrap) 113#endif 114 115#if AIC_DEBUG_REGISTERS 116ahc_reg_print_t ahc_clrsint1_print; 117#else 118#define ahc_clrsint1_print(regvalue, cur_col, wrap) \ 119 ahc_print_register(NULL, 0, "CLRSINT1", 0x0c, regvalue, cur_col, wrap) 120#endif 121 122#if AIC_DEBUG_REGISTERS 123ahc_reg_print_t ahc_sstat1_print; 124#else 125#define ahc_sstat1_print(regvalue, cur_col, wrap) \ 126 ahc_print_register(NULL, 0, "SSTAT1", 0x0c, regvalue, cur_col, wrap) 127#endif 128 129#if AIC_DEBUG_REGISTERS 130ahc_reg_print_t ahc_sstat2_print; 131#else 132#define ahc_sstat2_print(regvalue, cur_col, wrap) \ 133 ahc_print_register(NULL, 0, "SSTAT2", 0x0d, regvalue, cur_col, wrap) 134#endif 135 136#if AIC_DEBUG_REGISTERS 137ahc_reg_print_t ahc_sstat3_print; 138#else 139#define ahc_sstat3_print(regvalue, cur_col, wrap) \ 140 ahc_print_register(NULL, 0, "SSTAT3", 0x0e, regvalue, cur_col, wrap) 141#endif 142 143#if AIC_DEBUG_REGISTERS 144ahc_reg_print_t ahc_scsiid_ultra2_print; 145#else 146#define ahc_scsiid_ultra2_print(regvalue, cur_col, wrap) \ 147 ahc_print_register(NULL, 0, "SCSIID_ULTRA2", 0x0f, regvalue, cur_col, wrap) 148#endif 149 150#if AIC_DEBUG_REGISTERS 151ahc_reg_print_t ahc_simode0_print; 152#else 153#define ahc_simode0_print(regvalue, cur_col, wrap) \ 154 ahc_print_register(NULL, 0, "SIMODE0", 0x10, regvalue, cur_col, wrap) 155#endif 156 157#if AIC_DEBUG_REGISTERS 158ahc_reg_print_t ahc_simode1_print; 159#else 160#define ahc_simode1_print(regvalue, cur_col, wrap) \ 161 ahc_print_register(NULL, 0, "SIMODE1", 0x11, regvalue, cur_col, wrap) 162#endif 163 164#if AIC_DEBUG_REGISTERS 165ahc_reg_print_t ahc_scsibusl_print; 166#else 167#define ahc_scsibusl_print(regvalue, cur_col, wrap) \ 168 ahc_print_register(NULL, 0, "SCSIBUSL", 0x12, regvalue, cur_col, wrap) 169#endif 170 171#if AIC_DEBUG_REGISTERS 172ahc_reg_print_t ahc_sxfrctl2_print; 173#else 174#define ahc_sxfrctl2_print(regvalue, cur_col, wrap) \ 175 ahc_print_register(NULL, 0, "SXFRCTL2", 0x13, regvalue, cur_col, wrap) 176#endif 177 178#if AIC_DEBUG_REGISTERS 179ahc_reg_print_t ahc_scsibush_print; 180#else 181#define ahc_scsibush_print(regvalue, cur_col, wrap) \ 182 ahc_print_register(NULL, 0, "SCSIBUSH", 0x13, regvalue, cur_col, wrap) 183#endif 184 185#if AIC_DEBUG_REGISTERS 186ahc_reg_print_t ahc_shaddr_print; 187#else 188#define ahc_shaddr_print(regvalue, cur_col, wrap) \ 189 ahc_print_register(NULL, 0, "SHADDR", 0x14, regvalue, cur_col, wrap) 190#endif 191 192#if AIC_DEBUG_REGISTERS 193ahc_reg_print_t ahc_seltimer_print; 194#else 195#define ahc_seltimer_print(regvalue, cur_col, wrap) \ 196 ahc_print_register(NULL, 0, "SELTIMER", 0x18, regvalue, cur_col, wrap) 197#endif 198 199#if AIC_DEBUG_REGISTERS 200ahc_reg_print_t ahc_selid_print; 201#else 202#define ahc_selid_print(regvalue, cur_col, wrap) \ 203 ahc_print_register(NULL, 0, "SELID", 0x19, regvalue, cur_col, wrap) 204#endif 205 206#if AIC_DEBUG_REGISTERS 207ahc_reg_print_t ahc_scamctl_print; 208#else 209#define ahc_scamctl_print(regvalue, cur_col, wrap) \ 210 ahc_print_register(NULL, 0, "SCAMCTL", 0x1a, regvalue, cur_col, wrap) 211#endif 212 213#if AIC_DEBUG_REGISTERS 214ahc_reg_print_t ahc_targid_print; 215#else 216#define ahc_targid_print(regvalue, cur_col, wrap) \ 217 ahc_print_register(NULL, 0, "TARGID", 0x1b, regvalue, cur_col, wrap) 218#endif 219 220#if AIC_DEBUG_REGISTERS 221ahc_reg_print_t ahc_spiocap_print; 222#else 223#define ahc_spiocap_print(regvalue, cur_col, wrap) \ 224 ahc_print_register(NULL, 0, "SPIOCAP", 0x1b, regvalue, cur_col, wrap) 225#endif 226 227#if AIC_DEBUG_REGISTERS 228ahc_reg_print_t ahc_brdctl_print; 229#else 230#define ahc_brdctl_print(regvalue, cur_col, wrap) \ 231 ahc_print_register(NULL, 0, "BRDCTL", 0x1d, regvalue, cur_col, wrap) 232#endif 233 234#if AIC_DEBUG_REGISTERS 235ahc_reg_print_t ahc_seectl_print; 236#else 237#define ahc_seectl_print(regvalue, cur_col, wrap) \ 238 ahc_print_register(NULL, 0, "SEECTL", 0x1e, regvalue, cur_col, wrap) 239#endif 240 241#if AIC_DEBUG_REGISTERS 242ahc_reg_print_t ahc_sblkctl_print; 243#else 244#define ahc_sblkctl_print(regvalue, cur_col, wrap) \ 245 ahc_print_register(NULL, 0, "SBLKCTL", 0x1f, regvalue, cur_col, wrap) 246#endif 247 248#if AIC_DEBUG_REGISTERS 249ahc_reg_print_t ahc_busy_targets_print; 250#else 251#define ahc_busy_targets_print(regvalue, cur_col, wrap) \ 252 ahc_print_register(NULL, 0, "BUSY_TARGETS", 0x20, regvalue, cur_col, wrap) 253#endif 254 255#if AIC_DEBUG_REGISTERS 256ahc_reg_print_t ahc_ultra_enb_print; 257#else 258#define ahc_ultra_enb_print(regvalue, cur_col, wrap) \ 259 ahc_print_register(NULL, 0, "ULTRA_ENB", 0x30, regvalue, cur_col, wrap) 260#endif 261 262#if AIC_DEBUG_REGISTERS 263ahc_reg_print_t ahc_disc_dsb_print; 264#else 265#define ahc_disc_dsb_print(regvalue, cur_col, wrap) \ 266 ahc_print_register(NULL, 0, "DISC_DSB", 0x32, regvalue, cur_col, wrap) 267#endif 268 269#if AIC_DEBUG_REGISTERS 270ahc_reg_print_t ahc_cmdsize_table_tail_print; 271#else 272#define ahc_cmdsize_table_tail_print(regvalue, cur_col, wrap) \ 273 ahc_print_register(NULL, 0, "CMDSIZE_TABLE_TAIL", 0x34, regvalue, cur_col, wrap) 274#endif 275 276#if AIC_DEBUG_REGISTERS 277ahc_reg_print_t ahc_mwi_residual_print; 278#else 279#define ahc_mwi_residual_print(regvalue, cur_col, wrap) \ 280 ahc_print_register(NULL, 0, "MWI_RESIDUAL", 0x38, regvalue, cur_col, wrap) 281#endif 282 283#if AIC_DEBUG_REGISTERS 284ahc_reg_print_t ahc_next_queued_scb_print; 285#else 286#define ahc_next_queued_scb_print(regvalue, cur_col, wrap) \ 287 ahc_print_register(NULL, 0, "NEXT_QUEUED_SCB", 0x39, regvalue, cur_col, wrap) 288#endif 289 290#if AIC_DEBUG_REGISTERS 291ahc_reg_print_t ahc_msg_out_print; 292#else 293#define ahc_msg_out_print(regvalue, cur_col, wrap) \ 294 ahc_print_register(NULL, 0, "MSG_OUT", 0x3a, regvalue, cur_col, wrap) 295#endif 296 297#if AIC_DEBUG_REGISTERS 298ahc_reg_print_t ahc_dmaparams_print; 299#else 300#define ahc_dmaparams_print(regvalue, cur_col, wrap) \ 301 ahc_print_register(NULL, 0, "DMAPARAMS", 0x3b, regvalue, cur_col, wrap) 302#endif 303 304#if AIC_DEBUG_REGISTERS 305ahc_reg_print_t ahc_seq_flags_print; 306#else 307#define ahc_seq_flags_print(regvalue, cur_col, wrap) \ 308 ahc_print_register(NULL, 0, "SEQ_FLAGS", 0x3c, regvalue, cur_col, wrap) 309#endif 310 311#if AIC_DEBUG_REGISTERS 312ahc_reg_print_t ahc_saved_scsiid_print; 313#else 314#define ahc_saved_scsiid_print(regvalue, cur_col, wrap) \ 315 ahc_print_register(NULL, 0, "SAVED_SCSIID", 0x3d, regvalue, cur_col, wrap) 316#endif 317 318#if AIC_DEBUG_REGISTERS 319ahc_reg_print_t ahc_saved_lun_print; 320#else 321#define ahc_saved_lun_print(regvalue, cur_col, wrap) \ 322 ahc_print_register(NULL, 0, "SAVED_LUN", 0x3e, regvalue, cur_col, wrap) 323#endif 324 325#if AIC_DEBUG_REGISTERS 326ahc_reg_print_t ahc_lastphase_print; 327#else 328#define ahc_lastphase_print(regvalue, cur_col, wrap) \ 329 ahc_print_register(NULL, 0, "LASTPHASE", 0x3f, regvalue, cur_col, wrap) 330#endif 331 332#if AIC_DEBUG_REGISTERS 333ahc_reg_print_t ahc_waiting_scbh_print; 334#else 335#define ahc_waiting_scbh_print(regvalue, cur_col, wrap) \ 336 ahc_print_register(NULL, 0, "WAITING_SCBH", 0x40, regvalue, cur_col, wrap) 337#endif 338 339#if AIC_DEBUG_REGISTERS 340ahc_reg_print_t ahc_disconnected_scbh_print; 341#else 342#define ahc_disconnected_scbh_print(regvalue, cur_col, wrap) \ 343 ahc_print_register(NULL, 0, "DISCONNECTED_SCBH", 0x41, regvalue, cur_col, wrap) 344#endif 345 346#if AIC_DEBUG_REGISTERS 347ahc_reg_print_t ahc_free_scbh_print; 348#else 349#define ahc_free_scbh_print(regvalue, cur_col, wrap) \ 350 ahc_print_register(NULL, 0, "FREE_SCBH", 0x42, regvalue, cur_col, wrap) 351#endif 352 353#if AIC_DEBUG_REGISTERS 354ahc_reg_print_t ahc_complete_scbh_print; 355#else 356#define ahc_complete_scbh_print(regvalue, cur_col, wrap) \ 357 ahc_print_register(NULL, 0, "COMPLETE_SCBH", 0x43, regvalue, cur_col, wrap) 358#endif 359 360#if AIC_DEBUG_REGISTERS 361ahc_reg_print_t ahc_hscb_addr_print; 362#else 363#define ahc_hscb_addr_print(regvalue, cur_col, wrap) \ 364 ahc_print_register(NULL, 0, "HSCB_ADDR", 0x44, regvalue, cur_col, wrap) 365#endif 366 367#if AIC_DEBUG_REGISTERS 368ahc_reg_print_t ahc_shared_data_addr_print; 369#else 370#define ahc_shared_data_addr_print(regvalue, cur_col, wrap) \ 371 ahc_print_register(NULL, 0, "SHARED_DATA_ADDR", 0x48, regvalue, cur_col, wrap) 372#endif 373 374#if AIC_DEBUG_REGISTERS 375ahc_reg_print_t ahc_kernel_qinpos_print; 376#else 377#define ahc_kernel_qinpos_print(regvalue, cur_col, wrap) \ 378 ahc_print_register(NULL, 0, "KERNEL_QINPOS", 0x4c, regvalue, cur_col, wrap) 379#endif 380 381#if AIC_DEBUG_REGISTERS 382ahc_reg_print_t ahc_qinpos_print; 383#else 384#define ahc_qinpos_print(regvalue, cur_col, wrap) \ 385 ahc_print_register(NULL, 0, "QINPOS", 0x4d, regvalue, cur_col, wrap) 386#endif 387 388#if AIC_DEBUG_REGISTERS 389ahc_reg_print_t ahc_qoutpos_print; 390#else 391#define ahc_qoutpos_print(regvalue, cur_col, wrap) \ 392 ahc_print_register(NULL, 0, "QOUTPOS", 0x4e, regvalue, cur_col, wrap) 393#endif 394 395#if AIC_DEBUG_REGISTERS 396ahc_reg_print_t ahc_kernel_tqinpos_print; 397#else 398#define ahc_kernel_tqinpos_print(regvalue, cur_col, wrap) \ 399 ahc_print_register(NULL, 0, "KERNEL_TQINPOS", 0x4f, regvalue, cur_col, wrap) 400#endif 401 402#if AIC_DEBUG_REGISTERS 403ahc_reg_print_t ahc_tqinpos_print; 404#else 405#define ahc_tqinpos_print(regvalue, cur_col, wrap) \ 406 ahc_print_register(NULL, 0, "TQINPOS", 0x50, regvalue, cur_col, wrap) 407#endif 408 409#if AIC_DEBUG_REGISTERS 410ahc_reg_print_t ahc_arg_1_print; 411#else 412#define ahc_arg_1_print(regvalue, cur_col, wrap) \ 413 ahc_print_register(NULL, 0, "ARG_1", 0x51, regvalue, cur_col, wrap) 414#endif 415 416#if AIC_DEBUG_REGISTERS 417ahc_reg_print_t ahc_arg_2_print; 418#else 419#define ahc_arg_2_print(regvalue, cur_col, wrap) \ 420 ahc_print_register(NULL, 0, "ARG_2", 0x52, regvalue, cur_col, wrap) 421#endif 422 423#if AIC_DEBUG_REGISTERS 424ahc_reg_print_t ahc_last_msg_print; 425#else 426#define ahc_last_msg_print(regvalue, cur_col, wrap) \ 427 ahc_print_register(NULL, 0, "LAST_MSG", 0x53, regvalue, cur_col, wrap) 428#endif 429 430#if AIC_DEBUG_REGISTERS 431ahc_reg_print_t ahc_scsiseq_template_print; 432#else 433#define ahc_scsiseq_template_print(regvalue, cur_col, wrap) \ 434 ahc_print_register(NULL, 0, "SCSISEQ_TEMPLATE", 0x54, regvalue, cur_col, wrap) 435#endif 436 437#if AIC_DEBUG_REGISTERS 438ahc_reg_print_t ahc_ha_274_biosglobal_print; 439#else 440#define ahc_ha_274_biosglobal_print(regvalue, cur_col, wrap) \ 441 ahc_print_register(NULL, 0, "HA_274_BIOSGLOBAL", 0x56, regvalue, cur_col, wrap) 442#endif 443 444#if AIC_DEBUG_REGISTERS 445ahc_reg_print_t ahc_seq_flags2_print; 446#else 447#define ahc_seq_flags2_print(regvalue, cur_col, wrap) \ 448 ahc_print_register(NULL, 0, "SEQ_FLAGS2", 0x57, regvalue, cur_col, wrap) 449#endif 450 451#if AIC_DEBUG_REGISTERS 452ahc_reg_print_t ahc_scsiconf_print; 453#else 454#define ahc_scsiconf_print(regvalue, cur_col, wrap) \ 455 ahc_print_register(NULL, 0, "SCSICONF", 0x5a, regvalue, cur_col, wrap) 456#endif 457 458#if AIC_DEBUG_REGISTERS 459ahc_reg_print_t ahc_intdef_print; 460#else 461#define ahc_intdef_print(regvalue, cur_col, wrap) \ 462 ahc_print_register(NULL, 0, "INTDEF", 0x5c, regvalue, cur_col, wrap) 463#endif 464 465#if AIC_DEBUG_REGISTERS 466ahc_reg_print_t ahc_hostconf_print; 467#else 468#define ahc_hostconf_print(regvalue, cur_col, wrap) \ 469 ahc_print_register(NULL, 0, "HOSTCONF", 0x5d, regvalue, cur_col, wrap) 470#endif 471 472#if AIC_DEBUG_REGISTERS 473ahc_reg_print_t ahc_ha_274_biosctrl_print; 474#else 475#define ahc_ha_274_biosctrl_print(regvalue, cur_col, wrap) \ 476 ahc_print_register(NULL, 0, "HA_274_BIOSCTRL", 0x5f, regvalue, cur_col, wrap) 477#endif 478 479#if AIC_DEBUG_REGISTERS 480ahc_reg_print_t ahc_seqctl_print; 481#else 482#define ahc_seqctl_print(regvalue, cur_col, wrap) \ 483 ahc_print_register(NULL, 0, "SEQCTL", 0x60, regvalue, cur_col, wrap) 484#endif 485 486#if AIC_DEBUG_REGISTERS 487ahc_reg_print_t ahc_seqram_print; 488#else 489#define ahc_seqram_print(regvalue, cur_col, wrap) \ 490 ahc_print_register(NULL, 0, "SEQRAM", 0x61, regvalue, cur_col, wrap) 491#endif 492 493#if AIC_DEBUG_REGISTERS 494ahc_reg_print_t ahc_seqaddr0_print; 495#else 496#define ahc_seqaddr0_print(regvalue, cur_col, wrap) \ 497 ahc_print_register(NULL, 0, "SEQADDR0", 0x62, regvalue, cur_col, wrap) 498#endif 499 500#if AIC_DEBUG_REGISTERS 501ahc_reg_print_t ahc_seqaddr1_print; 502#else 503#define ahc_seqaddr1_print(regvalue, cur_col, wrap) \ 504 ahc_print_register(NULL, 0, "SEQADDR1", 0x63, regvalue, cur_col, wrap) 505#endif 506 507#if AIC_DEBUG_REGISTERS 508ahc_reg_print_t ahc_accum_print; 509#else 510#define ahc_accum_print(regvalue, cur_col, wrap) \ 511 ahc_print_register(NULL, 0, "ACCUM", 0x64, regvalue, cur_col, wrap) 512#endif 513 514#if AIC_DEBUG_REGISTERS 515ahc_reg_print_t ahc_sindex_print; 516#else 517#define ahc_sindex_print(regvalue, cur_col, wrap) \ 518 ahc_print_register(NULL, 0, "SINDEX", 0x65, regvalue, cur_col, wrap) 519#endif 520 521#if AIC_DEBUG_REGISTERS 522ahc_reg_print_t ahc_dindex_print; 523#else 524#define ahc_dindex_print(regvalue, cur_col, wrap) \ 525 ahc_print_register(NULL, 0, "DINDEX", 0x66, regvalue, cur_col, wrap) 526#endif 527 528#if AIC_DEBUG_REGISTERS 529ahc_reg_print_t ahc_allones_print; 530#else 531#define ahc_allones_print(regvalue, cur_col, wrap) \ 532 ahc_print_register(NULL, 0, "ALLONES", 0x69, regvalue, cur_col, wrap) 533#endif 534 535#if AIC_DEBUG_REGISTERS 536ahc_reg_print_t ahc_none_print; 537#else 538#define ahc_none_print(regvalue, cur_col, wrap) \ 539 ahc_print_register(NULL, 0, "NONE", 0x6a, regvalue, cur_col, wrap) 540#endif 541 542#if AIC_DEBUG_REGISTERS 543ahc_reg_print_t ahc_allzeros_print; 544#else 545#define ahc_allzeros_print(regvalue, cur_col, wrap) \ 546 ahc_print_register(NULL, 0, "ALLZEROS", 0x6a, regvalue, cur_col, wrap) 547#endif 548 549#if AIC_DEBUG_REGISTERS 550ahc_reg_print_t ahc_flags_print; 551#else 552#define ahc_flags_print(regvalue, cur_col, wrap) \ 553 ahc_print_register(NULL, 0, "FLAGS", 0x6b, regvalue, cur_col, wrap) 554#endif 555 556#if AIC_DEBUG_REGISTERS 557ahc_reg_print_t ahc_sindir_print; 558#else 559#define ahc_sindir_print(regvalue, cur_col, wrap) \ 560 ahc_print_register(NULL, 0, "SINDIR", 0x6c, regvalue, cur_col, wrap) 561#endif 562 563#if AIC_DEBUG_REGISTERS 564ahc_reg_print_t ahc_dindir_print; 565#else 566#define ahc_dindir_print(regvalue, cur_col, wrap) \ 567 ahc_print_register(NULL, 0, "DINDIR", 0x6d, regvalue, cur_col, wrap) 568#endif 569 570#if AIC_DEBUG_REGISTERS 571ahc_reg_print_t ahc_function1_print; 572#else 573#define ahc_function1_print(regvalue, cur_col, wrap) \ 574 ahc_print_register(NULL, 0, "FUNCTION1", 0x6e, regvalue, cur_col, wrap) 575#endif 576 577#if AIC_DEBUG_REGISTERS 578ahc_reg_print_t ahc_stack_print; 579#else 580#define ahc_stack_print(regvalue, cur_col, wrap) \ 581 ahc_print_register(NULL, 0, "STACK", 0x6f, regvalue, cur_col, wrap) 582#endif 583 584#if AIC_DEBUG_REGISTERS 585ahc_reg_print_t ahc_targ_offset_print; 586#else 587#define ahc_targ_offset_print(regvalue, cur_col, wrap) \ 588 ahc_print_register(NULL, 0, "TARG_OFFSET", 0x70, regvalue, cur_col, wrap) 589#endif 590 591#if AIC_DEBUG_REGISTERS 592ahc_reg_print_t ahc_sram_base_print; 593#else 594#define ahc_sram_base_print(regvalue, cur_col, wrap) \ 595 ahc_print_register(NULL, 0, "SRAM_BASE", 0x70, regvalue, cur_col, wrap) 596#endif 597 598#if AIC_DEBUG_REGISTERS 599ahc_reg_print_t ahc_dscommand0_print; 600#else 601#define ahc_dscommand0_print(regvalue, cur_col, wrap) \ 602 ahc_print_register(NULL, 0, "DSCOMMAND0", 0x84, regvalue, cur_col, wrap) 603#endif 604 605#if AIC_DEBUG_REGISTERS 606ahc_reg_print_t ahc_bctl_print; 607#else 608#define ahc_bctl_print(regvalue, cur_col, wrap) \ 609 ahc_print_register(NULL, 0, "BCTL", 0x84, regvalue, cur_col, wrap) 610#endif 611 612#if AIC_DEBUG_REGISTERS 613ahc_reg_print_t ahc_bustime_print; 614#else 615#define ahc_bustime_print(regvalue, cur_col, wrap) \ 616 ahc_print_register(NULL, 0, "BUSTIME", 0x85, regvalue, cur_col, wrap) 617#endif 618 619#if AIC_DEBUG_REGISTERS 620ahc_reg_print_t ahc_dscommand1_print; 621#else 622#define ahc_dscommand1_print(regvalue, cur_col, wrap) \ 623 ahc_print_register(NULL, 0, "DSCOMMAND1", 0x85, regvalue, cur_col, wrap) 624#endif 625 626#if AIC_DEBUG_REGISTERS 627ahc_reg_print_t ahc_busspd_print; 628#else 629#define ahc_busspd_print(regvalue, cur_col, wrap) \ 630 ahc_print_register(NULL, 0, "BUSSPD", 0x86, regvalue, cur_col, wrap) 631#endif 632 633#if AIC_DEBUG_REGISTERS 634ahc_reg_print_t ahc_hs_mailbox_print; 635#else 636#define ahc_hs_mailbox_print(regvalue, cur_col, wrap) \ 637 ahc_print_register(NULL, 0, "HS_MAILBOX", 0x86, regvalue, cur_col, wrap) 638#endif 639 640#if AIC_DEBUG_REGISTERS 641ahc_reg_print_t ahc_dspcistatus_print; 642#else 643#define ahc_dspcistatus_print(regvalue, cur_col, wrap) \ 644 ahc_print_register(NULL, 0, "DSPCISTATUS", 0x86, regvalue, cur_col, wrap) 645#endif 646 647#if AIC_DEBUG_REGISTERS 648ahc_reg_print_t ahc_hcntrl_print; 649#else 650#define ahc_hcntrl_print(regvalue, cur_col, wrap) \ 651 ahc_print_register(NULL, 0, "HCNTRL", 0x87, regvalue, cur_col, wrap) 652#endif 653 654#if AIC_DEBUG_REGISTERS 655ahc_reg_print_t ahc_haddr_print; 656#else 657#define ahc_haddr_print(regvalue, cur_col, wrap) \ 658 ahc_print_register(NULL, 0, "HADDR", 0x88, regvalue, cur_col, wrap) 659#endif 660 661#if AIC_DEBUG_REGISTERS 662ahc_reg_print_t ahc_hcnt_print; 663#else 664#define ahc_hcnt_print(regvalue, cur_col, wrap) \ 665 ahc_print_register(NULL, 0, "HCNT", 0x8c, regvalue, cur_col, wrap) 666#endif 667 668#if AIC_DEBUG_REGISTERS 669ahc_reg_print_t ahc_scbptr_print; 670#else 671#define ahc_scbptr_print(regvalue, cur_col, wrap) \ 672 ahc_print_register(NULL, 0, "SCBPTR", 0x90, regvalue, cur_col, wrap) 673#endif 674 675#if AIC_DEBUG_REGISTERS 676ahc_reg_print_t ahc_intstat_print; 677#else 678#define ahc_intstat_print(regvalue, cur_col, wrap) \ 679 ahc_print_register(NULL, 0, "INTSTAT", 0x91, regvalue, cur_col, wrap) 680#endif 681 682#if AIC_DEBUG_REGISTERS 683ahc_reg_print_t ahc_error_print; 684#else 685#define ahc_error_print(regvalue, cur_col, wrap) \ 686 ahc_print_register(NULL, 0, "ERROR", 0x92, regvalue, cur_col, wrap) 687#endif 688 689#if AIC_DEBUG_REGISTERS 690ahc_reg_print_t ahc_clrint_print; 691#else 692#define ahc_clrint_print(regvalue, cur_col, wrap) \ 693 ahc_print_register(NULL, 0, "CLRINT", 0x92, regvalue, cur_col, wrap) 694#endif 695 696#if AIC_DEBUG_REGISTERS 697ahc_reg_print_t ahc_dfcntrl_print; 698#else 699#define ahc_dfcntrl_print(regvalue, cur_col, wrap) \ 700 ahc_print_register(NULL, 0, "DFCNTRL", 0x93, regvalue, cur_col, wrap) 701#endif 702 703#if AIC_DEBUG_REGISTERS 704ahc_reg_print_t ahc_dfstatus_print; 705#else 706#define ahc_dfstatus_print(regvalue, cur_col, wrap) \ 707 ahc_print_register(NULL, 0, "DFSTATUS", 0x94, regvalue, cur_col, wrap) 708#endif 709 710#if AIC_DEBUG_REGISTERS 711ahc_reg_print_t ahc_dfwaddr_print; 712#else 713#define ahc_dfwaddr_print(regvalue, cur_col, wrap) \ 714 ahc_print_register(NULL, 0, "DFWADDR", 0x95, regvalue, cur_col, wrap) 715#endif 716 717#if AIC_DEBUG_REGISTERS 718ahc_reg_print_t ahc_dfraddr_print; 719#else 720#define ahc_dfraddr_print(regvalue, cur_col, wrap) \ 721 ahc_print_register(NULL, 0, "DFRADDR", 0x97, regvalue, cur_col, wrap) 722#endif 723 724#if AIC_DEBUG_REGISTERS 725ahc_reg_print_t ahc_dfdat_print; 726#else 727#define ahc_dfdat_print(regvalue, cur_col, wrap) \ 728 ahc_print_register(NULL, 0, "DFDAT", 0x99, regvalue, cur_col, wrap) 729#endif 730 731#if AIC_DEBUG_REGISTERS 732ahc_reg_print_t ahc_scbcnt_print; 733#else 734#define ahc_scbcnt_print(regvalue, cur_col, wrap) \ 735 ahc_print_register(NULL, 0, "SCBCNT", 0x9a, regvalue, cur_col, wrap) 736#endif 737 738#if AIC_DEBUG_REGISTERS 739ahc_reg_print_t ahc_qinfifo_print; 740#else 741#define ahc_qinfifo_print(regvalue, cur_col, wrap) \ 742 ahc_print_register(NULL, 0, "QINFIFO", 0x9b, regvalue, cur_col, wrap) 743#endif 744 745#if AIC_DEBUG_REGISTERS 746ahc_reg_print_t ahc_qincnt_print; 747#else 748#define ahc_qincnt_print(regvalue, cur_col, wrap) \ 749 ahc_print_register(NULL, 0, "QINCNT", 0x9c, regvalue, cur_col, wrap) 750#endif 751 752#if AIC_DEBUG_REGISTERS 753ahc_reg_print_t ahc_crccontrol1_print; 754#else 755#define ahc_crccontrol1_print(regvalue, cur_col, wrap) \ 756 ahc_print_register(NULL, 0, "CRCCONTROL1", 0x9d, regvalue, cur_col, wrap) 757#endif 758 759#if AIC_DEBUG_REGISTERS 760ahc_reg_print_t ahc_qoutfifo_print; 761#else 762#define ahc_qoutfifo_print(regvalue, cur_col, wrap) \ 763 ahc_print_register(NULL, 0, "QOUTFIFO", 0x9d, regvalue, cur_col, wrap) 764#endif 765 766#if AIC_DEBUG_REGISTERS 767ahc_reg_print_t ahc_qoutcnt_print; 768#else 769#define ahc_qoutcnt_print(regvalue, cur_col, wrap) \ 770 ahc_print_register(NULL, 0, "QOUTCNT", 0x9e, regvalue, cur_col, wrap) 771#endif 772 773#if AIC_DEBUG_REGISTERS 774ahc_reg_print_t ahc_scsiphase_print; 775#else 776#define ahc_scsiphase_print(regvalue, cur_col, wrap) \ 777 ahc_print_register(NULL, 0, "SCSIPHASE", 0x9e, regvalue, cur_col, wrap) 778#endif 779 780#if AIC_DEBUG_REGISTERS 781ahc_reg_print_t ahc_sfunct_print; 782#else 783#define ahc_sfunct_print(regvalue, cur_col, wrap) \ 784 ahc_print_register(NULL, 0, "SFUNCT", 0x9f, regvalue, cur_col, wrap) 785#endif 786 787#if AIC_DEBUG_REGISTERS 788ahc_reg_print_t ahc_scb_base_print; 789#else 790#define ahc_scb_base_print(regvalue, cur_col, wrap) \ 791 ahc_print_register(NULL, 0, "SCB_BASE", 0xa0, regvalue, cur_col, wrap) 792#endif 793 794#if AIC_DEBUG_REGISTERS 795ahc_reg_print_t ahc_scb_cdb_ptr_print; 796#else 797#define ahc_scb_cdb_ptr_print(regvalue, cur_col, wrap) \ 798 ahc_print_register(NULL, 0, "SCB_CDB_PTR", 0xa0, regvalue, cur_col, wrap) 799#endif 800 801#if AIC_DEBUG_REGISTERS 802ahc_reg_print_t ahc_scb_residual_sgptr_print; 803#else 804#define ahc_scb_residual_sgptr_print(regvalue, cur_col, wrap) \ 805 ahc_print_register(NULL, 0, "SCB_RESIDUAL_SGPTR", 0xa4, regvalue, cur_col, wrap) 806#endif 807 808#if AIC_DEBUG_REGISTERS 809ahc_reg_print_t ahc_scb_scsi_status_print; 810#else 811#define ahc_scb_scsi_status_print(regvalue, cur_col, wrap) \ 812 ahc_print_register(NULL, 0, "SCB_SCSI_STATUS", 0xa8, regvalue, cur_col, wrap) 813#endif 814 815#if AIC_DEBUG_REGISTERS 816ahc_reg_print_t ahc_scb_target_phases_print; 817#else 818#define ahc_scb_target_phases_print(regvalue, cur_col, wrap) \ 819 ahc_print_register(NULL, 0, "SCB_TARGET_PHASES", 0xa9, regvalue, cur_col, wrap) 820#endif 821 822#if AIC_DEBUG_REGISTERS 823ahc_reg_print_t ahc_scb_target_data_dir_print; 824#else 825#define ahc_scb_target_data_dir_print(regvalue, cur_col, wrap) \ 826 ahc_print_register(NULL, 0, "SCB_TARGET_DATA_DIR", 0xaa, regvalue, cur_col, wrap) 827#endif 828 829#if AIC_DEBUG_REGISTERS 830ahc_reg_print_t ahc_scb_target_itag_print; 831#else 832#define ahc_scb_target_itag_print(regvalue, cur_col, wrap) \ 833 ahc_print_register(NULL, 0, "SCB_TARGET_ITAG", 0xab, regvalue, cur_col, wrap) 834#endif 835 836#if AIC_DEBUG_REGISTERS 837ahc_reg_print_t ahc_scb_dataptr_print; 838#else 839#define ahc_scb_dataptr_print(regvalue, cur_col, wrap) \ 840 ahc_print_register(NULL, 0, "SCB_DATAPTR", 0xac, regvalue, cur_col, wrap) 841#endif 842 843#if AIC_DEBUG_REGISTERS 844ahc_reg_print_t ahc_scb_datacnt_print; 845#else 846#define ahc_scb_datacnt_print(regvalue, cur_col, wrap) \ 847 ahc_print_register(NULL, 0, "SCB_DATACNT", 0xb0, regvalue, cur_col, wrap) 848#endif 849 850#if AIC_DEBUG_REGISTERS 851ahc_reg_print_t ahc_scb_sgptr_print; 852#else 853#define ahc_scb_sgptr_print(regvalue, cur_col, wrap) \ 854 ahc_print_register(NULL, 0, "SCB_SGPTR", 0xb4, regvalue, cur_col, wrap) 855#endif 856 857#if AIC_DEBUG_REGISTERS 858ahc_reg_print_t ahc_scb_control_print; 859#else 860#define ahc_scb_control_print(regvalue, cur_col, wrap) \ 861 ahc_print_register(NULL, 0, "SCB_CONTROL", 0xb8, regvalue, cur_col, wrap) 862#endif 863 864#if AIC_DEBUG_REGISTERS 865ahc_reg_print_t ahc_scb_scsiid_print; 866#else 867#define ahc_scb_scsiid_print(regvalue, cur_col, wrap) \ 868 ahc_print_register(NULL, 0, "SCB_SCSIID", 0xb9, regvalue, cur_col, wrap) 869#endif 870 871#if AIC_DEBUG_REGISTERS 872ahc_reg_print_t ahc_scb_lun_print; 873#else 874#define ahc_scb_lun_print(regvalue, cur_col, wrap) \ 875 ahc_print_register(NULL, 0, "SCB_LUN", 0xba, regvalue, cur_col, wrap) 876#endif 877 878#if AIC_DEBUG_REGISTERS 879ahc_reg_print_t ahc_scb_tag_print; 880#else 881#define ahc_scb_tag_print(regvalue, cur_col, wrap) \ 882 ahc_print_register(NULL, 0, "SCB_TAG", 0xbb, regvalue, cur_col, wrap) 883#endif 884 885#if AIC_DEBUG_REGISTERS 886ahc_reg_print_t ahc_scb_cdb_len_print; 887#else 888#define ahc_scb_cdb_len_print(regvalue, cur_col, wrap) \ 889 ahc_print_register(NULL, 0, "SCB_CDB_LEN", 0xbc, regvalue, cur_col, wrap) 890#endif 891 892#if AIC_DEBUG_REGISTERS 893ahc_reg_print_t ahc_scb_scsirate_print; 894#else 895#define ahc_scb_scsirate_print(regvalue, cur_col, wrap) \ 896 ahc_print_register(NULL, 0, "SCB_SCSIRATE", 0xbd, regvalue, cur_col, wrap) 897#endif 898 899#if AIC_DEBUG_REGISTERS 900ahc_reg_print_t ahc_scb_scsioffset_print; 901#else 902#define ahc_scb_scsioffset_print(regvalue, cur_col, wrap) \ 903 ahc_print_register(NULL, 0, "SCB_SCSIOFFSET", 0xbe, regvalue, cur_col, wrap) 904#endif 905 906#if AIC_DEBUG_REGISTERS 907ahc_reg_print_t ahc_scb_next_print; 908#else 909#define ahc_scb_next_print(regvalue, cur_col, wrap) \ 910 ahc_print_register(NULL, 0, "SCB_NEXT", 0xbf, regvalue, cur_col, wrap) 911#endif 912 913#if AIC_DEBUG_REGISTERS 914ahc_reg_print_t ahc_scb_64_spare_print; 915#else 916#define ahc_scb_64_spare_print(regvalue, cur_col, wrap) \ 917 ahc_print_register(NULL, 0, "SCB_64_SPARE", 0xc0, regvalue, cur_col, wrap) 918#endif 919 920#if AIC_DEBUG_REGISTERS 921ahc_reg_print_t ahc_seectl_2840_print; 922#else 923#define ahc_seectl_2840_print(regvalue, cur_col, wrap) \ 924 ahc_print_register(NULL, 0, "SEECTL_2840", 0xc0, regvalue, cur_col, wrap) 925#endif 926 927#if AIC_DEBUG_REGISTERS 928ahc_reg_print_t ahc_status_2840_print; 929#else 930#define ahc_status_2840_print(regvalue, cur_col, wrap) \ 931 ahc_print_register(NULL, 0, "STATUS_2840", 0xc1, regvalue, cur_col, wrap) 932#endif 933 934#if AIC_DEBUG_REGISTERS 935ahc_reg_print_t ahc_scb_64_btt_print; 936#else 937#define ahc_scb_64_btt_print(regvalue, cur_col, wrap) \ 938 ahc_print_register(NULL, 0, "SCB_64_BTT", 0xd0, regvalue, cur_col, wrap) 939#endif 940 941#if AIC_DEBUG_REGISTERS 942ahc_reg_print_t ahc_cchaddr_print; 943#else 944#define ahc_cchaddr_print(regvalue, cur_col, wrap) \ 945 ahc_print_register(NULL, 0, "CCHADDR", 0xe0, regvalue, cur_col, wrap) 946#endif 947 948#if AIC_DEBUG_REGISTERS 949ahc_reg_print_t ahc_cchcnt_print; 950#else 951#define ahc_cchcnt_print(regvalue, cur_col, wrap) \ 952 ahc_print_register(NULL, 0, "CCHCNT", 0xe8, regvalue, cur_col, wrap) 953#endif 954 955#if AIC_DEBUG_REGISTERS 956ahc_reg_print_t ahc_ccsgram_print; 957#else 958#define ahc_ccsgram_print(regvalue, cur_col, wrap) \ 959 ahc_print_register(NULL, 0, "CCSGRAM", 0xe9, regvalue, cur_col, wrap) 960#endif 961 962#if AIC_DEBUG_REGISTERS 963ahc_reg_print_t ahc_ccsgaddr_print; 964#else 965#define ahc_ccsgaddr_print(regvalue, cur_col, wrap) \ 966 ahc_print_register(NULL, 0, "CCSGADDR", 0xea, regvalue, cur_col, wrap) 967#endif 968 969#if AIC_DEBUG_REGISTERS 970ahc_reg_print_t ahc_ccsgctl_print; 971#else 972#define ahc_ccsgctl_print(regvalue, cur_col, wrap) \ 973 ahc_print_register(NULL, 0, "CCSGCTL", 0xeb, regvalue, cur_col, wrap) 974#endif 975 976#if AIC_DEBUG_REGISTERS 977ahc_reg_print_t ahc_ccscbram_print; 978#else 979#define ahc_ccscbram_print(regvalue, cur_col, wrap) \ 980 ahc_print_register(NULL, 0, "CCSCBRAM", 0xec, regvalue, cur_col, wrap) 981#endif 982 983#if AIC_DEBUG_REGISTERS 984ahc_reg_print_t ahc_ccscbaddr_print; 985#else 986#define ahc_ccscbaddr_print(regvalue, cur_col, wrap) \ 987 ahc_print_register(NULL, 0, "CCSCBADDR", 0xed, regvalue, cur_col, wrap) 988#endif 989 990#if AIC_DEBUG_REGISTERS 991ahc_reg_print_t ahc_ccscbctl_print; 992#else 993#define ahc_ccscbctl_print(regvalue, cur_col, wrap) \ 994 ahc_print_register(NULL, 0, "CCSCBCTL", 0xee, regvalue, cur_col, wrap) 995#endif 996 997#if AIC_DEBUG_REGISTERS 998ahc_reg_print_t ahc_ccscbcnt_print; 999#else 1000#define ahc_ccscbcnt_print(regvalue, cur_col, wrap) \ 1001 ahc_print_register(NULL, 0, "CCSCBCNT", 0xef, regvalue, cur_col, wrap) 1002#endif 1003 1004#if AIC_DEBUG_REGISTERS 1005ahc_reg_print_t ahc_scbbaddr_print; 1006#else 1007#define ahc_scbbaddr_print(regvalue, cur_col, wrap) \ 1008 ahc_print_register(NULL, 0, "SCBBADDR", 0xf0, regvalue, cur_col, wrap) 1009#endif 1010 1011#if AIC_DEBUG_REGISTERS 1012ahc_reg_print_t ahc_ccscbptr_print; 1013#else 1014#define ahc_ccscbptr_print(regvalue, cur_col, wrap) \ 1015 ahc_print_register(NULL, 0, "CCSCBPTR", 0xf1, regvalue, cur_col, wrap) 1016#endif 1017 1018#if AIC_DEBUG_REGISTERS 1019ahc_reg_print_t ahc_hnscb_qoff_print; 1020#else 1021#define ahc_hnscb_qoff_print(regvalue, cur_col, wrap) \ 1022 ahc_print_register(NULL, 0, "HNSCB_QOFF", 0xf4, regvalue, cur_col, wrap) 1023#endif 1024 1025#if AIC_DEBUG_REGISTERS 1026ahc_reg_print_t ahc_snscb_qoff_print; 1027#else 1028#define ahc_snscb_qoff_print(regvalue, cur_col, wrap) \ 1029 ahc_print_register(NULL, 0, "SNSCB_QOFF", 0xf6, regvalue, cur_col, wrap) 1030#endif 1031 1032#if AIC_DEBUG_REGISTERS 1033ahc_reg_print_t ahc_sdscb_qoff_print; 1034#else 1035#define ahc_sdscb_qoff_print(regvalue, cur_col, wrap) \ 1036 ahc_print_register(NULL, 0, "SDSCB_QOFF", 0xf8, regvalue, cur_col, wrap) 1037#endif 1038 1039#if AIC_DEBUG_REGISTERS 1040ahc_reg_print_t ahc_qoff_ctlsta_print; 1041#else 1042#define ahc_qoff_ctlsta_print(regvalue, cur_col, wrap) \ 1043 ahc_print_register(NULL, 0, "QOFF_CTLSTA", 0xfa, regvalue, cur_col, wrap) 1044#endif 1045 1046#if AIC_DEBUG_REGISTERS 1047ahc_reg_print_t ahc_dff_thrsh_print; 1048#else 1049#define ahc_dff_thrsh_print(regvalue, cur_col, wrap) \ 1050 ahc_print_register(NULL, 0, "DFF_THRSH", 0xfb, regvalue, cur_col, wrap) 1051#endif 1052 1053#if AIC_DEBUG_REGISTERS 1054ahc_reg_print_t ahc_sg_cache_shadow_print; 1055#else 1056#define ahc_sg_cache_shadow_print(regvalue, cur_col, wrap) \ 1057 ahc_print_register(NULL, 0, "SG_CACHE_SHADOW", 0xfc, regvalue, cur_col, wrap) 1058#endif 1059 1060#if AIC_DEBUG_REGISTERS 1061ahc_reg_print_t ahc_sg_cache_pre_print; 1062#else 1063#define ahc_sg_cache_pre_print(regvalue, cur_col, wrap) \ 1064 ahc_print_register(NULL, 0, "SG_CACHE_PRE", 0xfc, regvalue, cur_col, wrap) 1065#endif 1066 1067 1068#define SCSISEQ 0x00 1069#define TEMODE 0x80 1070#define SCSIRSTO 0x01 1071 1072#define SXFRCTL0 0x01 1073#define DFON 0x80 1074#define DFPEXP 0x40 1075#define FAST20 0x20 1076#define CLRSTCNT 0x10 1077#define SPIOEN 0x08 1078#define SCAMEN 0x04 1079#define CLRCHN 0x02 1080 1081#define SXFRCTL1 0x02 1082#define STIMESEL 0x18 1083#define BITBUCKET 0x80 1084#define SWRAPEN 0x40 1085#define ENSTIMER 0x04 1086#define ACTNEGEN 0x02 1087#define STPWEN 0x01 1088 1089#define SCSISIGI 0x03 1090#define P_DATAIN_DT 0x60 1091#define P_DATAOUT_DT 0x20 1092#define ATNI 0x10 1093#define SELI 0x08 1094#define BSYI 0x04 1095#define REQI 0x02 1096#define ACKI 0x01 1097 1098#define SCSISIGO 0x03 1099#define CDO 0x80 1100#define IOO 0x40 1101#define MSGO 0x20 1102#define ATNO 0x10 1103#define SELO 0x08 1104#define BSYO 0x04 1105#define REQO 0x02 1106#define ACKO 0x01 1107 1108#define SCSIRATE 0x04 1109#define SXFR 0x70 1110#define SXFR_ULTRA2 0x0f 1111#define SOFS 0x0f 1112#define WIDEXFER 0x80 1113#define ENABLE_CRC 0x40 1114#define SINGLE_EDGE 0x10 1115 1116#define SCSIID 0x05 1117#define SCSIOFFSET 0x05 1118#define SOFS_ULTRA2 0x7f 1119 1120#define SCSIDATL 0x06 1121 1122#define SCSIDATH 0x07 1123 1124#define OPTIONMODE 0x08 1125#define OPTIONMODE_DEFAULTS 0x03 1126#define AUTORATEEN 0x80 1127#define AUTOACKEN 0x40 1128#define ATNMGMNTEN 0x20 1129#define BUSFREEREV 0x10 1130#define EXPPHASEDIS 0x08 1131#define SCSIDATL_IMGEN 0x04 1132#define AUTO_MSGOUT_DE 0x02 1133#define DIS_MSGIN_DUALEDGE 0x01 1134 1135#define STCNT 0x08 1136 1137#define TARGCRCCNT 0x0a 1138 1139#define CLRSINT0 0x0b 1140#define CLRSELDO 0x40 1141#define CLRSELDI 0x20 1142#define CLRSELINGO 0x10 1143#define CLRIOERR 0x08 1144#define CLRSWRAP 0x08 1145#define CLRSPIORDY 0x02 1146 1147#define SSTAT0 0x0b 1148#define TARGET 0x80 1149#define SELDO 0x40 1150#define SELDI 0x20 1151#define SELINGO 0x10 1152#define SWRAP 0x08 1153#define IOERR 0x08 1154#define SDONE 0x04 1155#define SPIORDY 0x02 1156#define DMADONE 0x01 1157 1158#define CLRSINT1 0x0c 1159#define CLRSELTIMEO 0x80 1160#define CLRATNO 0x40 1161#define CLRSCSIRSTI 0x20 1162#define CLRBUSFREE 0x08 1163#define CLRSCSIPERR 0x04 1164#define CLRPHASECHG 0x02 1165#define CLRREQINIT 0x01 1166 1167#define SSTAT1 0x0c 1168#define SELTO 0x80 1169#define ATNTARG 0x40 1170#define SCSIRSTI 0x20 1171#define PHASEMIS 0x10 1172#define BUSFREE 0x08 1173#define SCSIPERR 0x04 1174#define PHASECHG 0x02 1175#define REQINIT 0x01 1176 1177#define SSTAT2 0x0d 1178#define SFCNT 0x1f 1179#define OVERRUN 0x80 1180#define SHVALID 0x40 1181#define EXP_ACTIVE 0x10 1182#define CRCVALERR 0x08 1183#define CRCENDERR 0x04 1184#define CRCREQERR 0x02 1185#define DUAL_EDGE_ERR 0x01 1186 1187#define SSTAT3 0x0e 1188#define SCSICNT 0xf0 1189#define U2OFFCNT 0x7f 1190#define OFFCNT 0x0f 1191 1192#define SCSIID_ULTRA2 0x0f 1193 1194#define SIMODE0 0x10 1195#define ENSELDO 0x40 1196#define ENSELDI 0x20 1197#define ENSELINGO 0x10 1198#define ENIOERR 0x08 1199#define ENSWRAP 0x08 1200#define ENSDONE 0x04 1201#define ENSPIORDY 0x02 1202#define ENDMADONE 0x01 1203 1204#define SIMODE1 0x11 1205#define ENSELTIMO 0x80 1206#define ENATNTARG 0x40 1207#define ENSCSIRST 0x20 1208#define ENPHASEMIS 0x10 1209#define ENBUSFREE 0x08 1210#define ENSCSIPERR 0x04 1211#define ENPHASECHG 0x02 1212#define ENREQINIT 0x01 1213 1214#define SCSIBUSL 0x12 1215 1216#define SXFRCTL2 0x13 1217#define ASYNC_SETUP 0x07 1218#define AUTORSTDIS 0x10 1219#define CMDDMAEN 0x08 1220 1221#define SCSIBUSH 0x13 1222 1223#define SHADDR 0x14 1224 1225#define SELTIMER 0x18 1226#define TARGIDIN 0x18 1227#define STAGE6 0x20 1228#define STAGE5 0x10 1229#define STAGE4 0x08 1230#define STAGE3 0x04 1231#define STAGE2 0x02 1232#define STAGE1 0x01 1233 1234#define SELID 0x19 1235#define SELID_MASK 0xf0 1236#define ONEBIT 0x08 1237 1238#define SCAMCTL 0x1a 1239#define SCAMLVL 0x03 1240#define ENSCAMSELO 0x80 1241#define CLRSCAMSELID 0x40 1242#define ALTSTIM 0x20 1243#define DFLTTID 0x10 1244 1245#define TARGID 0x1b 1246 1247#define SPIOCAP 0x1b 1248#define SOFT1 0x80 1249#define SOFT0 0x40 1250#define SOFTCMDEN 0x20 1251#define EXT_BRDCTL 0x10 1252#define SEEPROM 0x08 1253#define EEPROM 0x04 1254#define ROM 0x02 1255#define SSPIOCPS 0x01 1256 1257#define BRDCTL 0x1d 1258#define BRDDAT7 0x80 1259#define BRDDAT6 0x40 1260#define BRDDAT5 0x20 1261#define BRDDAT4 0x10 1262#define BRDSTB 0x10 1263#define BRDDAT3 0x08 1264#define BRDCS 0x08 1265#define BRDDAT2 0x04 1266#define BRDRW 0x04 1267#define BRDCTL1 0x02 1268#define BRDRW_ULTRA2 0x02 1269#define BRDCTL0 0x01 1270#define BRDSTB_ULTRA2 0x01 1271 1272#define SEECTL 0x1e 1273#define EXTARBACK 0x80 1274#define EXTARBREQ 0x40 1275#define SEEMS 0x20 1276#define SEERDY 0x10 1277#define SEECS 0x08 1278#define SEECK 0x04 1279#define SEEDO 0x02 1280#define SEEDI 0x01 1281 1282#define SBLKCTL 0x1f 1283#define DIAGLEDEN 0x80 1284#define DIAGLEDON 0x40 1285#define AUTOFLUSHDIS 0x20 1286#define ENAB40 0x08 1287#define SELBUSB 0x08 1288#define ENAB20 0x04 1289#define SELWIDE 0x02 1290#define XCVR 0x01 1291 1292#define BUSY_TARGETS 0x20 1293#define TARG_SCSIRATE 0x20 1294 1295#define ULTRA_ENB 0x30 1296#define CMDSIZE_TABLE 0x30 1297 1298#define DISC_DSB 0x32 1299 1300#define CMDSIZE_TABLE_TAIL 0x34 1301 1302#define MWI_RESIDUAL 0x38 1303 1304#define NEXT_QUEUED_SCB 0x39 1305 1306#define MSG_OUT 0x3a 1307 1308#define DMAPARAMS 0x3b 1309#define PRELOADEN 0x80 1310#define WIDEODD 0x40 1311#define SCSIEN 0x20 1312#define SDMAENACK 0x10 1313#define SDMAEN 0x10 1314#define HDMAEN 0x08 1315#define HDMAENACK 0x08 1316#define DIRECTION 0x04 1317#define FIFOFLUSH 0x02 1318#define FIFORESET 0x01 1319 1320#define SEQ_FLAGS 0x3c 1321#define NOT_IDENTIFIED 0x80 1322#define NO_CDB_SENT 0x40 1323#define TARGET_CMD_IS_TAGGED 0x40 1324#define DPHASE 0x20 1325#define TARG_CMD_PENDING 0x10 1326#define CMDPHASE_PENDING 0x08 1327#define DPHASE_PENDING 0x04 1328#define SPHASE_PENDING 0x02 1329#define NO_DISCONNECT 0x01 1330 1331#define SAVED_SCSIID 0x3d 1332 1333#define SAVED_LUN 0x3e 1334 1335#define LASTPHASE 0x3f 1336#define PHASE_MASK 0xe0 1337#define P_MESGIN 0xe0 1338#define P_STATUS 0xc0 1339#define P_MESGOUT 0xa0 1340#define P_COMMAND 0x80 1341#define P_DATAIN 0x40 1342#define P_BUSFREE 0x01 1343#define P_DATAOUT 0x00 1344#define CDI 0x80 1345#define IOI 0x40 1346#define MSGI 0x20 1347 1348#define WAITING_SCBH 0x40 1349 1350#define DISCONNECTED_SCBH 0x41 1351 1352#define FREE_SCBH 0x42 1353 1354#define COMPLETE_SCBH 0x43 1355 1356#define HSCB_ADDR 0x44 1357 1358#define SHARED_DATA_ADDR 0x48 1359 1360#define KERNEL_QINPOS 0x4c 1361 1362#define QINPOS 0x4d 1363 1364#define QOUTPOS 0x4e 1365 1366#define KERNEL_TQINPOS 0x4f 1367 1368#define TQINPOS 0x50 1369 1370#define ARG_1 0x51 1371#define RETURN_1 0x51 1372#define SEND_MSG 0x80 1373#define SEND_SENSE 0x40 1374#define SEND_REJ 0x20 1375#define MSGOUT_PHASEMIS 0x10 1376#define EXIT_MSG_LOOP 0x08 1377#define CONT_MSG_LOOP 0x04 1378#define CONT_TARG_SESSION 0x02 1379#define SPARE 0x01 1380 1381#define ARG_2 0x52 1382#define RETURN_2 0x52 1383 1384#define LAST_MSG 0x53 1385#define TARG_IMMEDIATE_SCB 0x53 1386 1387#define SCSISEQ_TEMPLATE 0x54 1388#define ENSELO 0x40 1389#define ENSELI 0x20 1390#define ENRSELI 0x10 1391#define ENAUTOATNO 0x08 1392#define ENAUTOATNI 0x04 1393#define ENAUTOATNP 0x02 1394 1395#define HA_274_BIOSGLOBAL 0x56 1396#define INITIATOR_TAG 0x56 1397#define HA_274_EXTENDED_TRANS 0x01 1398 1399#define SEQ_FLAGS2 0x57 1400#define TARGET_MSG_PENDING 0x02 1401#define SCB_DMA 0x01 1402 1403#define SCSICONF 0x5a 1404#define HWSCSIID 0x0f 1405#define HSCSIID 0x07 1406#define TERM_ENB 0x80 1407#define RESET_SCSI 0x40 1408#define ENSPCHK 0x20 1409 1410#define INTDEF 0x5c 1411#define VECTOR 0x0f 1412#define EDGE_TRIG 0x80 1413 1414#define HOSTCONF 0x5d 1415 1416#define HA_274_BIOSCTRL 0x5f 1417#define BIOSDISABLED 0x30 1418#define BIOSMODE 0x30 1419#define CHANNEL_B_PRIMARY 0x08 1420 1421#define SEQCTL 0x60 1422#define PERRORDIS 0x80 1423#define PAUSEDIS 0x40 1424#define FAILDIS 0x20 1425#define FASTMODE 0x10 1426#define BRKADRINTEN 0x08 1427#define STEP 0x04 1428#define SEQRESET 0x02 1429#define LOADRAM 0x01 1430 1431#define SEQRAM 0x61 1432 1433#define SEQADDR0 0x62 1434 1435#define SEQADDR1 0x63 1436#define SEQADDR1_MASK 0x01 1437 1438#define ACCUM 0x64 1439 1440#define SINDEX 0x65 1441 1442#define DINDEX 0x66 1443 1444#define ALLONES 0x69 1445 1446#define NONE 0x6a 1447 1448#define ALLZEROS 0x6a 1449 1450#define FLAGS 0x6b 1451#define ZERO 0x02 1452#define CARRY 0x01 1453 1454#define SINDIR 0x6c 1455 1456#define DINDIR 0x6d 1457 1458#define FUNCTION1 0x6e 1459 1460#define STACK 0x6f 1461 1462#define TARG_OFFSET 0x70 1463 1464#define SRAM_BASE 0x70 1465 1466#define DSCOMMAND0 0x84 1467#define CACHETHEN 0x80 1468#define DPARCKEN 0x40 1469#define MPARCKEN 0x20 1470#define EXTREQLCK 0x10 1471#define INTSCBRAMSEL 0x08 1472#define RAMPS 0x04 1473#define USCBSIZE32 0x02 1474#define CIOPARCKEN 0x01 1475 1476#define BCTL 0x84 1477#define ACE 0x08 1478#define ENABLE 0x01 1479 1480#define BUSTIME 0x85 1481#define BOFF 0xf0 1482#define BON 0x0f 1483 1484#define DSCOMMAND1 0x85 1485#define DSLATT 0xfc 1486#define HADDLDSEL1 0x02 1487#define HADDLDSEL0 0x01 1488 1489#define BUSSPD 0x86 1490#define DFTHRSH 0xc0 1491#define DFTHRSH_75 0x80 1492#define STBOFF 0x38 1493#define STBON 0x07 1494 1495#define HS_MAILBOX 0x86 1496#define HOST_MAILBOX 0xf0 1497#define HOST_TQINPOS 0x80 1498#define SEQ_MAILBOX 0x0f 1499 1500#define DSPCISTATUS 0x86 1501#define DFTHRSH_100 0xc0 1502 1503#define HCNTRL 0x87 1504#define POWRDN 0x40 1505#define SWINT 0x10 1506#define IRQMS 0x08 1507#define PAUSE 0x04 1508#define INTEN 0x02 1509#define CHIPRST 0x01 1510#define CHIPRSTACK 0x01 1511 1512#define HADDR 0x88 1513 1514#define HCNT 0x8c 1515 1516#define SCBPTR 0x90 1517 1518#define INTSTAT 0x91 1519#define SEQINT_MASK 0xf1 1520#define OUT_OF_RANGE 0xe1 1521#define NO_FREE_SCB 0xd1 1522#define SCB_MISMATCH 0xc1 1523#define MISSED_BUSFREE 0xb1 1524#define MKMSG_FAILED 0xa1 1525#define DATA_OVERRUN 0x91 1526#define PERR_DETECTED 0x81 1527#define BAD_STATUS 0x71 1528#define HOST_MSG_LOOP 0x61 1529#define PDATA_REINIT 0x51 1530#define IGN_WIDE_RES 0x41 1531#define NO_MATCH 0x31 1532#define PROTO_VIOLATION 0x21 1533#define SEND_REJECT 0x11 1534#define INT_PEND 0x0f 1535#define BAD_PHASE 0x01 1536#define BRKADRINT 0x08 1537#define SCSIINT 0x04 1538#define CMDCMPLT 0x02 1539#define SEQINT 0x01 1540 1541#define ERROR 0x92 1542#define CIOPARERR 0x80 1543#define PCIERRSTAT 0x40 1544#define MPARERR 0x20 1545#define DPARERR 0x10 1546#define SQPARERR 0x08 1547#define ILLOPCODE 0x04 1548#define ILLSADDR 0x02 1549#define ILLHADDR 0x01 1550 1551#define CLRINT 0x92 1552#define CLRPARERR 0x10 1553#define CLRBRKADRINT 0x08 1554#define CLRSCSIINT 0x04 1555#define CLRCMDINT 0x02 1556#define CLRSEQINT 0x01 1557 1558#define DFCNTRL 0x93 1559 1560#define DFSTATUS 0x94 1561#define PRELOAD_AVAIL 0x80 1562#define DFCACHETH 0x40 1563#define FIFOQWDEMP 0x20 1564#define MREQPEND 0x10 1565#define HDONE 0x08 1566#define DFTHRESH 0x04 1567#define FIFOFULL 0x02 1568#define FIFOEMP 0x01 1569 1570#define DFWADDR 0x95 1571 1572#define DFRADDR 0x97 1573 1574#define DFDAT 0x99 1575 1576#define SCBCNT 0x9a 1577#define SCBCNT_MASK 0x1f 1578#define SCBAUTO 0x80 1579 1580#define QINFIFO 0x9b 1581 1582#define QINCNT 0x9c 1583 1584#define CRCCONTROL1 0x9d 1585#define CRCONSEEN 0x80 1586#define CRCVALCHKEN 0x40 1587#define CRCENDCHKEN 0x20 1588#define CRCREQCHKEN 0x10 1589#define TARGCRCENDEN 0x08 1590#define TARGCRCCNTEN 0x04 1591 1592#define QOUTFIFO 0x9d 1593 1594#define QOUTCNT 0x9e 1595 1596#define SCSIPHASE 0x9e 1597#define DATA_PHASE_MASK 0x03 1598#define STATUS_PHASE 0x20 1599#define COMMAND_PHASE 0x10 1600#define MSG_IN_PHASE 0x08 1601#define MSG_OUT_PHASE 0x04 1602#define DATA_IN_PHASE 0x02 1603#define DATA_OUT_PHASE 0x01 1604 1605#define SFUNCT 0x9f 1606#define ALT_MODE 0x80 1607 1608#define SCB_BASE 0xa0 1609 1610#define SCB_CDB_PTR 0xa0 1611#define SCB_RESIDUAL_DATACNT 0xa0 1612#define SCB_CDB_STORE 0xa0 1613 1614#define SCB_RESIDUAL_SGPTR 0xa4 1615 1616#define SCB_SCSI_STATUS 0xa8 1617 1618#define SCB_TARGET_PHASES 0xa9 1619 1620#define SCB_TARGET_DATA_DIR 0xaa 1621 1622#define SCB_TARGET_ITAG 0xab 1623 1624#define SCB_DATAPTR 0xac 1625 1626#define SCB_DATACNT 0xb0 1627#define SG_HIGH_ADDR_BITS 0x7f 1628#define SG_LAST_SEG 0x80 1629 1630#define SCB_SGPTR 0xb4 1631#define SG_RESID_VALID 0x04 1632#define SG_FULL_RESID 0x02 1633#define SG_LIST_NULL 0x01 1634 1635#define SCB_CONTROL 0xb8 1636#define SCB_TAG_TYPE 0x03 1637#define STATUS_RCVD 0x80 1638#define TARGET_SCB 0x80 1639#define DISCENB 0x40 1640#define TAG_ENB 0x20 1641#define MK_MESSAGE 0x10 1642#define ULTRAENB 0x08 1643#define DISCONNECTED 0x04 1644 1645#define SCB_SCSIID 0xb9 1646#define TID 0xf0 1647#define TWIN_TID 0x70 1648#define OID 0x0f 1649#define TWIN_CHNLB 0x80 1650 1651#define SCB_LUN 0xba 1652#define LID 0x3f 1653#define SCB_XFERLEN_ODD 0x80 1654 1655#define SCB_TAG 0xbb 1656 1657#define SCB_CDB_LEN 0xbc 1658 1659#define SCB_SCSIRATE 0xbd 1660 1661#define SCB_SCSIOFFSET 0xbe 1662 1663#define SCB_NEXT 0xbf 1664 1665#define SCB_64_SPARE 0xc0 1666 1667#define SEECTL_2840 0xc0 1668#define CS_2840 0x04 1669#define CK_2840 0x02 1670#define DO_2840 0x01 1671 1672#define STATUS_2840 0xc1 1673#define BIOS_SEL 0x60 1674#define ADSEL 0x1e 1675#define EEPROM_TF 0x80 1676#define DI_2840 0x01 1677 1678#define SCB_64_BTT 0xd0 1679 1680#define CCHADDR 0xe0 1681 1682#define CCHCNT 0xe8 1683 1684#define CCSGRAM 0xe9 1685 1686#define CCSGADDR 0xea 1687 1688#define CCSGCTL 0xeb 1689#define CCSGDONE 0x80 1690#define CCSGEN 0x08 1691#define SG_FETCH_NEEDED 0x02 1692#define CCSGRESET 0x01 1693 1694#define CCSCBRAM 0xec 1695 1696#define CCSCBADDR 0xed 1697 1698#define CCSCBCTL 0xee 1699#define CCSCBDONE 0x80 1700#define ARRDONE 0x40 1701#define CCARREN 0x10 1702#define CCSCBEN 0x08 1703#define CCSCBDIR 0x04 1704#define CCSCBRESET 0x01 1705 1706#define CCSCBCNT 0xef 1707 1708#define SCBBADDR 0xf0 1709 1710#define CCSCBPTR 0xf1 1711 1712#define HNSCB_QOFF 0xf4 1713 1714#define SNSCB_QOFF 0xf6 1715 1716#define SDSCB_QOFF 0xf8 1717 1718#define QOFF_CTLSTA 0xfa 1719#define SCB_QSIZE 0x07 1720#define SCB_QSIZE_256 0x06 1721#define SCB_AVAIL 0x40 1722#define SNSCB_ROLLOVER 0x20 1723#define SDSCB_ROLLOVER 0x10 1724 1725#define DFF_THRSH 0xfb 1726#define WR_DFTHRSH 0x70 1727#define WR_DFTHRSH_MAX 0x70 1728#define WR_DFTHRSH_90 0x60 1729#define WR_DFTHRSH_85 0x50 1730#define WR_DFTHRSH_75 0x40 1731#define WR_DFTHRSH_63 0x30 1732#define WR_DFTHRSH_50 0x20 1733#define WR_DFTHRSH_25 0x10 1734#define RD_DFTHRSH_MAX 0x07 1735#define RD_DFTHRSH 0x07 1736#define RD_DFTHRSH_90 0x06 1737#define RD_DFTHRSH_85 0x05 1738#define RD_DFTHRSH_75 0x04 1739#define RD_DFTHRSH_63 0x03 1740#define RD_DFTHRSH_50 0x02 1741#define RD_DFTHRSH_25 0x01 1742#define RD_DFTHRSH_MIN 0x00 1743#define WR_DFTHRSH_MIN 0x00 1744 1745#define SG_CACHE_SHADOW 0xfc 1746#define SG_ADDR_MASK 0xf8 1747#define LAST_SEG 0x02 1748#define LAST_SEG_DONE 0x01 1749 1750#define SG_CACHE_PRE 0xfc 1751 1752 1753#define MAX_OFFSET_ULTRA2 0x7f 1754#define SCB_LIST_NULL 0xff 1755#define HOST_MSG 0xff 1756#define MAX_OFFSET 0x7f 1757#define BUS_32_BIT 0x02 1758#define CMD_GROUP_CODE_SHIFT 0x05 1759#define BUS_8_BIT 0x00 1760#define CCSGRAM_MAXSEGS 0x10 1761#define TARGET_DATA_IN 0x01 1762#define STATUS_QUEUE_FULL 0x28 1763#define STATUS_BUSY 0x08 1764#define MAX_OFFSET_8BIT 0x0f 1765#define BUS_16_BIT 0x01 1766#define TID_SHIFT 0x04 1767#define SCB_DOWNLOAD_SIZE_64 0x30 1768#define SCB_UPLOAD_SIZE 0x20 1769#define HOST_MAILBOX_SHIFT 0x04 1770#define MAX_OFFSET_16BIT 0x08 1771#define TARGET_CMD_CMPLT 0xfe 1772#define SG_SIZEOF 0x08 1773#define SCB_DOWNLOAD_SIZE 0x20 1774#define SEQ_MAILBOX_SHIFT 0x00 1775#define CCSGADDR_MAX 0x80 1776#define STACK_SIZE 0x04 1777 1778 1779/* Downloaded Constant Definitions */ 1780#define SG_PREFETCH_ADDR_MASK 0x06 1781#define SG_PREFETCH_ALIGN_MASK 0x05 1782#define QOUTFIFO_OFFSET 0x00 1783#define SG_PREFETCH_CNT 0x04 1784#define INVERTED_CACHESIZE_MASK 0x03 1785#define CACHESIZE_MASK 0x02 1786#define QINFIFO_OFFSET 0x01 1787#define DOWNLOAD_CONST_COUNT 0x07 1788 1789 1790/* Exported Labels */ 1791