1/*- 2 * Copyright (c) 2009-2012 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD$"); 29 30#include <sys/param.h> 31#include <sys/module.h> 32#include <sys/systm.h> 33#include <sys/kernel.h> 34#include <sys/bus.h> 35#include <sys/conf.h> 36#include <sys/endian.h> 37#include <sys/malloc.h> 38#include <sys/lock.h> 39#include <sys/mutex.h> 40#include <machine/stdarg.h> 41#include <machine/resource.h> 42#include <machine/bus.h> 43#include <sys/rman.h> 44#include <dev/pci/pcivar.h> 45#include <dev/pci/pcireg.h> 46#include "ahci.h" 47 48#include <cam/cam.h> 49#include <cam/cam_ccb.h> 50#include <cam/cam_sim.h> 51#include <cam/cam_xpt_sim.h> 52#include <cam/cam_debug.h> 53 54/* local prototypes */ 55static int ahci_setup_interrupt(device_t dev); 56static void ahci_intr(void *data); 57static void ahci_intr_one(void *data); 58static void ahci_intr_one_edge(void *data); 59static int ahci_suspend(device_t dev); 60static int ahci_resume(device_t dev); 61static int ahci_ch_init(device_t dev); 62static int ahci_ch_deinit(device_t dev); 63static int ahci_ch_suspend(device_t dev); 64static int ahci_ch_resume(device_t dev); 65static void ahci_ch_pm(void *arg); 66static void ahci_ch_intr(void *arg); 67static void ahci_ch_intr_direct(void *arg); 68static void ahci_ch_intr_main(struct ahci_channel *ch, uint32_t istatus); 69static int ahci_ctlr_reset(device_t dev); 70static int ahci_ctlr_setup(device_t dev); 71static void ahci_begin_transaction(device_t dev, union ccb *ccb); 72static void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 73static void ahci_execute_transaction(struct ahci_slot *slot); 74static void ahci_timeout(struct ahci_slot *slot); 75static void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et); 76static int ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag); 77static void ahci_dmainit(device_t dev); 78static void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 79static void ahci_dmafini(device_t dev); 80static void ahci_slotsalloc(device_t dev); 81static void ahci_slotsfree(device_t dev); 82static void ahci_reset(device_t dev); 83static void ahci_start(device_t dev, int fbs); 84static void ahci_stop(device_t dev); 85static void ahci_clo(device_t dev); 86static void ahci_start_fr(device_t dev); 87static void ahci_stop_fr(device_t dev); 88 89static int ahci_sata_connect(struct ahci_channel *ch); 90static int ahci_sata_phy_reset(device_t dev); 91static int ahci_wait_ready(device_t dev, int t, int t0); 92 93static void ahci_issue_recovery(device_t dev); 94static void ahci_process_read_log(device_t dev, union ccb *ccb); 95static void ahci_process_request_sense(device_t dev, union ccb *ccb); 96 97static void ahciaction(struct cam_sim *sim, union ccb *ccb); 98static void ahcipoll(struct cam_sim *sim); 99 100static MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers"); 101 102static struct { 103 uint32_t id; 104 uint8_t rev; 105 const char *name; 106 int quirks; 107#define AHCI_Q_NOFORCE 1 108#define AHCI_Q_NOPMP 2 109#define AHCI_Q_NONCQ 4 110#define AHCI_Q_1CH 8 111#define AHCI_Q_2CH 16 112#define AHCI_Q_4CH 32 113#define AHCI_Q_EDGEIS 64 114#define AHCI_Q_SATA2 128 115#define AHCI_Q_NOBSYRES 256 116#define AHCI_Q_NOAA 512 117#define AHCI_Q_NOCOUNT 1024 118#define AHCI_Q_ALTSIG 2048 119#define AHCI_Q_NOMSI 4096 120 121#define AHCI_Q_BIT_STRING \ 122 "\020" \ 123 "\001NOFORCE" \ 124 "\002NOPMP" \ 125 "\003NONCQ" \ 126 "\0041CH" \ 127 "\0052CH" \ 128 "\0064CH" \ 129 "\007EDGEIS" \ 130 "\010SATA2" \ 131 "\011NOBSYRES" \ 132 "\012NOAA" \ 133 "\013NOCOUNT" \ 134 "\014ALTSIG" \ 135 "\015NOMSI" 136} ahci_ids[] = { 137 {0x43801002, 0x00, "AMD SB600", AHCI_Q_NOMSI}, 138 {0x43901002, 0x00, "AMD SB7x0/SB8x0/SB9x0", 0}, 139 {0x43911002, 0x00, "AMD SB7x0/SB8x0/SB9x0", 0}, 140 {0x43921002, 0x00, "AMD SB7x0/SB8x0/SB9x0", 0}, 141 {0x43931002, 0x00, "AMD SB7x0/SB8x0/SB9x0", 0}, 142 {0x43941002, 0x00, "AMD SB7x0/SB8x0/SB9x0", 0}, 143 {0x43951002, 0x00, "AMD SB8x0/SB9x0", 0}, 144 {0x78001022, 0x00, "AMD Hudson-2", 0}, 145 {0x78011022, 0x00, "AMD Hudson-2", 0}, 146 {0x78021022, 0x00, "AMD Hudson-2", 0}, 147 {0x78031022, 0x00, "AMD Hudson-2", 0}, 148 {0x78041022, 0x00, "AMD Hudson-2", 0}, 149 {0x06111b21, 0x00, "ASMedia ASM2106", 0}, 150 {0x06121b21, 0x00, "ASMedia ASM1061", 0}, 151 {0x26528086, 0x00, "Intel ICH6", AHCI_Q_NOFORCE}, 152 {0x26538086, 0x00, "Intel ICH6M", AHCI_Q_NOFORCE}, 153 {0x26818086, 0x00, "Intel ESB2", 0}, 154 {0x26828086, 0x00, "Intel ESB2", 0}, 155 {0x26838086, 0x00, "Intel ESB2", 0}, 156 {0x27c18086, 0x00, "Intel ICH7", 0}, 157 {0x27c38086, 0x00, "Intel ICH7", 0}, 158 {0x27c58086, 0x00, "Intel ICH7M", 0}, 159 {0x27c68086, 0x00, "Intel ICH7M", 0}, 160 {0x28218086, 0x00, "Intel ICH8", 0}, 161 {0x28228086, 0x00, "Intel ICH8", 0}, 162 {0x28248086, 0x00, "Intel ICH8", 0}, 163 {0x28298086, 0x00, "Intel ICH8M", 0}, 164 {0x282a8086, 0x00, "Intel ICH8M", 0}, 165 {0x29228086, 0x00, "Intel ICH9", 0}, 166 {0x29238086, 0x00, "Intel ICH9", 0}, 167 {0x29248086, 0x00, "Intel ICH9", 0}, 168 {0x29258086, 0x00, "Intel ICH9", 0}, 169 {0x29278086, 0x00, "Intel ICH9", 0}, 170 {0x29298086, 0x00, "Intel ICH9M", 0}, 171 {0x292a8086, 0x00, "Intel ICH9M", 0}, 172 {0x292b8086, 0x00, "Intel ICH9M", 0}, 173 {0x292c8086, 0x00, "Intel ICH9M", 0}, 174 {0x292f8086, 0x00, "Intel ICH9M", 0}, 175 {0x294d8086, 0x00, "Intel ICH9", 0}, 176 {0x294e8086, 0x00, "Intel ICH9M", 0}, 177 {0x3a058086, 0x00, "Intel ICH10", 0}, 178 {0x3a228086, 0x00, "Intel ICH10", 0}, 179 {0x3a258086, 0x00, "Intel ICH10", 0}, 180 {0x3b228086, 0x00, "Intel 5 Series/3400 Series", 0}, 181 {0x3b238086, 0x00, "Intel 5 Series/3400 Series", 0}, 182 {0x3b258086, 0x00, "Intel 5 Series/3400 Series", 0}, 183 {0x3b298086, 0x00, "Intel 5 Series/3400 Series", 0}, 184 {0x3b2c8086, 0x00, "Intel 5 Series/3400 Series", 0}, 185 {0x3b2f8086, 0x00, "Intel 5 Series/3400 Series", 0}, 186 {0x1c028086, 0x00, "Intel Cougar Point", 0}, 187 {0x1c038086, 0x00, "Intel Cougar Point", 0}, 188 {0x1c048086, 0x00, "Intel Cougar Point", 0}, 189 {0x1c058086, 0x00, "Intel Cougar Point", 0}, 190 {0x1d028086, 0x00, "Intel Patsburg", 0}, 191 {0x1d048086, 0x00, "Intel Patsburg", 0}, 192 {0x1d068086, 0x00, "Intel Patsburg", 0}, 193 {0x28268086, 0x00, "Intel Patsburg (RAID)", 0}, 194 {0x1e028086, 0x00, "Intel Panther Point", 0}, 195 {0x1e038086, 0x00, "Intel Panther Point", 0}, 196 {0x1e048086, 0x00, "Intel Panther Point (RAID)", 0}, 197 {0x1e058086, 0x00, "Intel Panther Point (RAID)", 0}, 198 {0x1e068086, 0x00, "Intel Panther Point (RAID)", 0}, 199 {0x1e078086, 0x00, "Intel Panther Point (RAID)", 0}, 200 {0x1e0e8086, 0x00, "Intel Panther Point (RAID)", 0}, 201 {0x1e0f8086, 0x00, "Intel Panther Point (RAID)", 0}, 202 {0x1f228086, 0x00, "Intel Avoton", 0}, 203 {0x1f238086, 0x00, "Intel Avoton", 0}, 204 {0x1f248086, 0x00, "Intel Avoton (RAID)", 0}, 205 {0x1f258086, 0x00, "Intel Avoton (RAID)", 0}, 206 {0x1f268086, 0x00, "Intel Avoton (RAID)", 0}, 207 {0x1f278086, 0x00, "Intel Avoton (RAID)", 0}, 208 {0x1f2e8086, 0x00, "Intel Avoton (RAID)", 0}, 209 {0x1f2f8086, 0x00, "Intel Avoton (RAID)", 0}, 210 {0x1f328086, 0x00, "Intel Avoton", 0}, 211 {0x1f338086, 0x00, "Intel Avoton", 0}, 212 {0x1f348086, 0x00, "Intel Avoton (RAID)", 0}, 213 {0x1f358086, 0x00, "Intel Avoton (RAID)", 0}, 214 {0x1f368086, 0x00, "Intel Avoton (RAID)", 0}, 215 {0x1f378086, 0x00, "Intel Avoton (RAID)", 0}, 216 {0x1f3e8086, 0x00, "Intel Avoton (RAID)", 0}, 217 {0x1f3f8086, 0x00, "Intel Avoton (RAID)", 0}, 218 {0x23a38086, 0x00, "Intel Coleto Creek", 0}, 219 {0x28238086, 0x00, "Intel Wellsburg (RAID)", 0}, 220 {0x28278086, 0x00, "Intel Wellsburg (RAID)", 0}, 221 {0x8c028086, 0x00, "Intel Lynx Point", 0}, 222 {0x8c038086, 0x00, "Intel Lynx Point", 0}, 223 {0x8c048086, 0x00, "Intel Lynx Point (RAID)", 0}, 224 {0x8c058086, 0x00, "Intel Lynx Point (RAID)", 0}, 225 {0x8c068086, 0x00, "Intel Lynx Point (RAID)", 0}, 226 {0x8c078086, 0x00, "Intel Lynx Point (RAID)", 0}, 227 {0x8c0e8086, 0x00, "Intel Lynx Point (RAID)", 0}, 228 {0x8c0f8086, 0x00, "Intel Lynx Point (RAID)", 0}, 229 {0x8d028086, 0x00, "Intel Wellsburg", 0}, 230 {0x8d048086, 0x00, "Intel Wellsburg (RAID)", 0}, 231 {0x8d068086, 0x00, "Intel Wellsburg (RAID)", 0}, 232 {0x8d628086, 0x00, "Intel Wellsburg", 0}, 233 {0x8d648086, 0x00, "Intel Wellsburg (RAID)", 0}, 234 {0x8d668086, 0x00, "Intel Wellsburg (RAID)", 0}, 235 {0x8d6e8086, 0x00, "Intel Wellsburg (RAID)", 0}, 236 {0x9c028086, 0x00, "Intel Lynx Point-LP", 0}, 237 {0x9c038086, 0x00, "Intel Lynx Point-LP", 0}, 238 {0x9c048086, 0x00, "Intel Lynx Point-LP (RAID)", 0}, 239 {0x9c058086, 0x00, "Intel Lynx Point-LP (RAID)", 0}, 240 {0x9c068086, 0x00, "Intel Lynx Point-LP (RAID)", 0}, 241 {0x9c078086, 0x00, "Intel Lynx Point-LP (RAID)", 0}, 242 {0x9c0e8086, 0x00, "Intel Lynx Point-LP (RAID)", 0}, 243 {0x9c0f8086, 0x00, "Intel Lynx Point-LP (RAID)", 0}, 244 {0x23238086, 0x00, "Intel DH89xxCC", 0}, 245 {0x2360197b, 0x00, "JMicron JMB360", 0}, 246 {0x2361197b, 0x00, "JMicron JMB361", AHCI_Q_NOFORCE}, 247 {0x2362197b, 0x00, "JMicron JMB362", 0}, 248 {0x2363197b, 0x00, "JMicron JMB363", AHCI_Q_NOFORCE}, 249 {0x2365197b, 0x00, "JMicron JMB365", AHCI_Q_NOFORCE}, 250 {0x2366197b, 0x00, "JMicron JMB366", AHCI_Q_NOFORCE}, 251 {0x2368197b, 0x00, "JMicron JMB368", AHCI_Q_NOFORCE}, 252 {0x611111ab, 0x00, "Marvell 88SE6111", AHCI_Q_NOFORCE | AHCI_Q_1CH | 253 AHCI_Q_EDGEIS}, 254 {0x612111ab, 0x00, "Marvell 88SE6121", AHCI_Q_NOFORCE | AHCI_Q_2CH | 255 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, 256 {0x614111ab, 0x00, "Marvell 88SE6141", AHCI_Q_NOFORCE | AHCI_Q_4CH | 257 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, 258 {0x614511ab, 0x00, "Marvell 88SE6145", AHCI_Q_NOFORCE | AHCI_Q_4CH | 259 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, 260 {0x91201b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS}, 261 {0x91231b4b, 0x11, "Marvell 88SE912x", AHCI_Q_ALTSIG}, 262 {0x91231b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_SATA2}, 263 {0x91251b4b, 0x00, "Marvell 88SE9125", 0}, 264 {0x91281b4b, 0x00, "Marvell 88SE9128", AHCI_Q_ALTSIG}, 265 {0x91301b4b, 0x00, "Marvell 88SE9130", AHCI_Q_ALTSIG}, 266 {0x91721b4b, 0x00, "Marvell 88SE9172", 0}, 267 {0x91821b4b, 0x00, "Marvell 88SE9182", 0}, 268 {0x91831b4b, 0x00, "Marvell 88SS9183", 0}, 269 {0x91a01b4b, 0x00, "Marvell 88SE91Ax", 0}, 270 {0x92151b4b, 0x00, "Marvell 88SE9215", 0}, 271 {0x92201b4b, 0x00, "Marvell 88SE9220", AHCI_Q_ALTSIG}, 272 {0x92301b4b, 0x00, "Marvell 88SE9230", AHCI_Q_ALTSIG}, 273 {0x92351b4b, 0x00, "Marvell 88SE9235", 0}, 274 {0x06201103, 0x00, "HighPoint RocketRAID 620", 0}, 275 {0x06201b4b, 0x00, "HighPoint RocketRAID 620", 0}, 276 {0x06221103, 0x00, "HighPoint RocketRAID 622", 0}, 277 {0x06221b4b, 0x00, "HighPoint RocketRAID 622", 0}, 278 {0x06401103, 0x00, "HighPoint RocketRAID 640", 0}, 279 {0x06401b4b, 0x00, "HighPoint RocketRAID 640", 0}, 280 {0x06441103, 0x00, "HighPoint RocketRAID 644", 0}, 281 {0x06441b4b, 0x00, "HighPoint RocketRAID 644", 0}, 282 {0x06411103, 0x00, "HighPoint RocketRAID 640L", 0}, 283 {0x06421103, 0x00, "HighPoint RocketRAID 642L", 0}, 284 {0x06451103, 0x00, "HighPoint RocketRAID 644L", 0}, 285 {0x044c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 286 {0x044d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 287 {0x044e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 288 {0x044f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 289 {0x045c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 290 {0x045d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 291 {0x045e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 292 {0x045f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 293 {0x055010de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 294 {0x055110de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 295 {0x055210de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 296 {0x055310de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 297 {0x055410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 298 {0x055510de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 299 {0x055610de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 300 {0x055710de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 301 {0x055810de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 302 {0x055910de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 303 {0x055A10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 304 {0x055B10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 305 {0x058410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 306 {0x07f010de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 307 {0x07f110de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 308 {0x07f210de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 309 {0x07f310de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 310 {0x07f410de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 311 {0x07f510de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 312 {0x07f610de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 313 {0x07f710de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 314 {0x07f810de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 315 {0x07f910de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 316 {0x07fa10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 317 {0x07fb10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 318 {0x0ad010de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 319 {0x0ad110de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 320 {0x0ad210de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 321 {0x0ad310de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 322 {0x0ad410de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 323 {0x0ad510de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 324 {0x0ad610de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 325 {0x0ad710de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 326 {0x0ad810de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 327 {0x0ad910de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 328 {0x0ada10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 329 {0x0adb10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 330 {0x0ab410de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 331 {0x0ab510de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 332 {0x0ab610de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 333 {0x0ab710de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 334 {0x0ab810de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 335 {0x0ab910de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 336 {0x0aba10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 337 {0x0abb10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 338 {0x0abc10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 339 {0x0abd10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 340 {0x0abe10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 341 {0x0abf10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 342 {0x0d8410de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 343 {0x0d8510de, 0x00, "NVIDIA MCP89", AHCI_Q_NOFORCE|AHCI_Q_NOAA}, 344 {0x0d8610de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 345 {0x0d8710de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 346 {0x0d8810de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 347 {0x0d8910de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 348 {0x0d8a10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 349 {0x0d8b10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 350 {0x0d8c10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 351 {0x0d8d10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 352 {0x0d8e10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 353 {0x0d8f10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 354 {0x3781105a, 0x00, "Promise TX8660", 0}, 355 {0x33491106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ}, 356 {0x62871106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ}, 357 {0x11841039, 0x00, "SiS 966", 0}, 358 {0x11851039, 0x00, "SiS 968", 0}, 359 {0x01861039, 0x00, "SiS 968", 0}, 360 {0x00000000, 0x00, NULL, 0} 361}; 362 363#define recovery_type spriv_field0 364#define RECOVERY_NONE 0 365#define RECOVERY_READ_LOG 1 366#define RECOVERY_REQUEST_SENSE 2 367#define recovery_slot spriv_field1 368 369static int force_ahci = 1; 370TUNABLE_INT("hw.ahci.force", &force_ahci); 371 372static int 373ahci_probe(device_t dev) 374{ 375 char buf[64]; 376 int i, valid = 0; 377 uint32_t devid = pci_get_devid(dev); 378 uint8_t revid = pci_get_revid(dev); 379 380 /* 381 * Ensure it is not a PCI bridge (some vendors use 382 * the same PID and VID in PCI bridge and AHCI cards). 383 */ 384 if (pci_get_class(dev) == PCIC_BRIDGE) 385 return (ENXIO); 386 387 /* Is this a possible AHCI candidate? */ 388 if (pci_get_class(dev) == PCIC_STORAGE && 389 pci_get_subclass(dev) == PCIS_STORAGE_SATA && 390 pci_get_progif(dev) == PCIP_STORAGE_SATA_AHCI_1_0) 391 valid = 1; 392 /* Is this a known AHCI chip? */ 393 for (i = 0; ahci_ids[i].id != 0; i++) { 394 if (ahci_ids[i].id == devid && 395 ahci_ids[i].rev <= revid && 396 (valid || (force_ahci == 1 && 397 !(ahci_ids[i].quirks & AHCI_Q_NOFORCE)))) { 398 /* Do not attach JMicrons with single PCI function. */ 399 if (pci_get_vendor(dev) == 0x197b && 400 (pci_read_config(dev, 0xdf, 1) & 0x40) == 0) 401 return (ENXIO); 402 snprintf(buf, sizeof(buf), "%s AHCI SATA controller", 403 ahci_ids[i].name); 404 device_set_desc_copy(dev, buf); 405 return (BUS_PROBE_VENDOR); 406 } 407 } 408 if (!valid) 409 return (ENXIO); 410 device_set_desc_copy(dev, "AHCI SATA controller"); 411 return (BUS_PROBE_VENDOR); 412} 413 414static int 415ahci_ata_probe(device_t dev) 416{ 417 char buf[64]; 418 int i; 419 uint32_t devid = pci_get_devid(dev); 420 uint8_t revid = pci_get_revid(dev); 421 422 if ((intptr_t)device_get_ivars(dev) >= 0) 423 return (ENXIO); 424 /* Is this a known AHCI chip? */ 425 for (i = 0; ahci_ids[i].id != 0; i++) { 426 if (ahci_ids[i].id == devid && 427 ahci_ids[i].rev <= revid) { 428 snprintf(buf, sizeof(buf), "%s AHCI SATA controller", 429 ahci_ids[i].name); 430 device_set_desc_copy(dev, buf); 431 return (BUS_PROBE_VENDOR); 432 } 433 } 434 device_set_desc_copy(dev, "AHCI SATA controller"); 435 return (BUS_PROBE_VENDOR); 436} 437 438static int 439ahci_attach(device_t dev) 440{ 441 struct ahci_controller *ctlr = device_get_softc(dev); 442 device_t child; 443 int error, unit, speed, i; 444 u_int u; 445 uint32_t devid = pci_get_devid(dev); 446 uint8_t revid = pci_get_revid(dev); 447 u_int32_t version; 448 449 ctlr->dev = dev; 450 i = 0; 451 while (ahci_ids[i].id != 0 && 452 (ahci_ids[i].id != devid || 453 ahci_ids[i].rev > revid)) 454 i++; 455 ctlr->quirks = ahci_ids[i].quirks; 456 resource_int_value(device_get_name(dev), 457 device_get_unit(dev), "ccc", &ctlr->ccc); 458 /* if we have a memory BAR(5) we are likely on an AHCI part */ 459 ctlr->r_rid = PCIR_BAR(5); 460 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 461 &ctlr->r_rid, RF_ACTIVE))) 462 return ENXIO; 463 /* Setup our own memory management for channels. */ 464 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem); 465 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem); 466 ctlr->sc_iomem.rm_type = RMAN_ARRAY; 467 ctlr->sc_iomem.rm_descr = "I/O memory addresses"; 468 if ((error = rman_init(&ctlr->sc_iomem)) != 0) { 469 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 470 return (error); 471 } 472 if ((error = rman_manage_region(&ctlr->sc_iomem, 473 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) { 474 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 475 rman_fini(&ctlr->sc_iomem); 476 return (error); 477 } 478 pci_enable_busmaster(dev); 479 /* Reset controller */ 480 if ((error = ahci_ctlr_reset(dev)) != 0) { 481 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 482 rman_fini(&ctlr->sc_iomem); 483 return (error); 484 }; 485 /* Get the HW capabilities */ 486 version = ATA_INL(ctlr->r_mem, AHCI_VS); 487 ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP); 488 if (version >= 0x00010200) 489 ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2); 490 if (ctlr->caps & AHCI_CAP_EMS) 491 ctlr->capsem = ATA_INL(ctlr->r_mem, AHCI_EM_CTL); 492 ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI); 493 494 /* Identify and set separate quirks for HBA and RAID f/w Marvells. */ 495 if ((ctlr->quirks & AHCI_Q_ALTSIG) && 496 (ctlr->caps & AHCI_CAP_SPM) == 0) 497 ctlr->quirks |= AHCI_Q_NOBSYRES; 498 499 if (ctlr->quirks & AHCI_Q_1CH) { 500 ctlr->caps &= ~AHCI_CAP_NPMASK; 501 ctlr->ichannels &= 0x01; 502 } 503 if (ctlr->quirks & AHCI_Q_2CH) { 504 ctlr->caps &= ~AHCI_CAP_NPMASK; 505 ctlr->caps |= 1; 506 ctlr->ichannels &= 0x03; 507 } 508 if (ctlr->quirks & AHCI_Q_4CH) { 509 ctlr->caps &= ~AHCI_CAP_NPMASK; 510 ctlr->caps |= 3; 511 ctlr->ichannels &= 0x0f; 512 } 513 ctlr->channels = MAX(flsl(ctlr->ichannels), 514 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 515 if (ctlr->quirks & AHCI_Q_NOPMP) 516 ctlr->caps &= ~AHCI_CAP_SPM; 517 if (ctlr->quirks & AHCI_Q_NONCQ) 518 ctlr->caps &= ~AHCI_CAP_SNCQ; 519 if ((ctlr->caps & AHCI_CAP_CCCS) == 0) 520 ctlr->ccc = 0; 521 ctlr->emloc = ATA_INL(ctlr->r_mem, AHCI_EM_LOC); 522 523 /* Create controller-wide DMA tag. */ 524 if (bus_dma_tag_create(bus_get_dma_tag(dev), 0, 0, 525 (ctlr->caps & AHCI_CAP_64BIT) ? BUS_SPACE_MAXADDR : 526 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 527 BUS_SPACE_MAXSIZE, BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, 528 0, NULL, NULL, &ctlr->dma_tag)) { 529 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, 530 ctlr->r_mem); 531 rman_fini(&ctlr->sc_iomem); 532 return ENXIO; 533 } 534 535 ahci_ctlr_setup(dev); 536 /* Setup interrupts. */ 537 if (ahci_setup_interrupt(dev)) { 538 bus_dma_tag_destroy(ctlr->dma_tag); 539 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 540 rman_fini(&ctlr->sc_iomem); 541 return ENXIO; 542 } 543 i = 0; 544 for (u = ctlr->ichannels; u != 0; u >>= 1) 545 i += (u & 1); 546 ctlr->direct = (ctlr->msi && (ctlr->numirqs > 1 || i <= 3)); 547 resource_int_value(device_get_name(dev), device_get_unit(dev), 548 "direct", &ctlr->direct); 549 /* Announce HW capabilities. */ 550 speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT; 551 device_printf(dev, 552 "AHCI v%x.%02x with %d %sGbps ports, Port Multiplier %s%s\n", 553 ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f), 554 ((version >> 4) & 0xf0) + (version & 0x0f), 555 (ctlr->caps & AHCI_CAP_NPMASK) + 1, 556 ((speed == 1) ? "1.5":((speed == 2) ? "3": 557 ((speed == 3) ? "6":"?"))), 558 (ctlr->caps & AHCI_CAP_SPM) ? 559 "supported" : "not supported", 560 (ctlr->caps & AHCI_CAP_FBSS) ? 561 " with FBS" : ""); 562 if (ctlr->quirks != 0) { 563 device_printf(dev, "quirks=0x%b\n", ctlr->quirks, 564 AHCI_Q_BIT_STRING); 565 } 566 if (bootverbose) { 567 device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps", 568 (ctlr->caps & AHCI_CAP_64BIT) ? " 64bit":"", 569 (ctlr->caps & AHCI_CAP_SNCQ) ? " NCQ":"", 570 (ctlr->caps & AHCI_CAP_SSNTF) ? " SNTF":"", 571 (ctlr->caps & AHCI_CAP_SMPS) ? " MPS":"", 572 (ctlr->caps & AHCI_CAP_SSS) ? " SS":"", 573 (ctlr->caps & AHCI_CAP_SALP) ? " ALP":"", 574 (ctlr->caps & AHCI_CAP_SAL) ? " AL":"", 575 (ctlr->caps & AHCI_CAP_SCLO) ? " CLO":"", 576 ((speed == 1) ? "1.5":((speed == 2) ? "3": 577 ((speed == 3) ? "6":"?")))); 578 printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n", 579 (ctlr->caps & AHCI_CAP_SAM) ? " AM":"", 580 (ctlr->caps & AHCI_CAP_SPM) ? " PM":"", 581 (ctlr->caps & AHCI_CAP_FBSS) ? " FBS":"", 582 (ctlr->caps & AHCI_CAP_PMD) ? " PMD":"", 583 (ctlr->caps & AHCI_CAP_SSC) ? " SSC":"", 584 (ctlr->caps & AHCI_CAP_PSC) ? " PSC":"", 585 ((ctlr->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1, 586 (ctlr->caps & AHCI_CAP_CCCS) ? " CCC":"", 587 (ctlr->caps & AHCI_CAP_EMS) ? " EM":"", 588 (ctlr->caps & AHCI_CAP_SXS) ? " eSATA":"", 589 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 590 } 591 if (bootverbose && version >= 0x00010200) { 592 device_printf(dev, "Caps2:%s%s%s%s%s%s\n", 593 (ctlr->caps2 & AHCI_CAP2_DESO) ? " DESO":"", 594 (ctlr->caps2 & AHCI_CAP2_SADM) ? " SADM":"", 595 (ctlr->caps2 & AHCI_CAP2_SDS) ? " SDS":"", 596 (ctlr->caps2 & AHCI_CAP2_APST) ? " APST":"", 597 (ctlr->caps2 & AHCI_CAP2_NVMP) ? " NVMP":"", 598 (ctlr->caps2 & AHCI_CAP2_BOH) ? " BOH":""); 599 } 600 /* Attach all channels on this controller */ 601 for (unit = 0; unit < ctlr->channels; unit++) { 602 child = device_add_child(dev, "ahcich", -1); 603 if (child == NULL) { 604 device_printf(dev, "failed to add channel device\n"); 605 continue; 606 } 607 device_set_ivars(child, (void *)(intptr_t)unit); 608 if ((ctlr->ichannels & (1 << unit)) == 0) 609 device_disable(child); 610 } 611 if (ctlr->caps & AHCI_CAP_EMS) { 612 child = device_add_child(dev, "ahciem", -1); 613 if (child == NULL) 614 device_printf(dev, "failed to add enclosure device\n"); 615 else 616 device_set_ivars(child, (void *)(intptr_t)-1); 617 } 618 bus_generic_attach(dev); 619 return 0; 620} 621 622static int 623ahci_detach(device_t dev) 624{ 625 struct ahci_controller *ctlr = device_get_softc(dev); 626 int i; 627 628 /* Detach & delete all children */ 629 device_delete_children(dev); 630 631 /* Free interrupts. */ 632 for (i = 0; i < ctlr->numirqs; i++) { 633 if (ctlr->irqs[i].r_irq) { 634 bus_teardown_intr(dev, ctlr->irqs[i].r_irq, 635 ctlr->irqs[i].handle); 636 bus_release_resource(dev, SYS_RES_IRQ, 637 ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq); 638 } 639 } 640 pci_release_msi(dev); 641 bus_dma_tag_destroy(ctlr->dma_tag); 642 /* Free memory. */ 643 rman_fini(&ctlr->sc_iomem); 644 if (ctlr->r_mem) 645 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 646 return (0); 647} 648 649static int 650ahci_ctlr_reset(device_t dev) 651{ 652 struct ahci_controller *ctlr = device_get_softc(dev); 653 int timeout; 654 655 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == 0x28298086 && 656 (pci_read_config(dev, 0x92, 1) & 0xfe) == 0x04) 657 pci_write_config(dev, 0x92, 0x01, 1); 658 /* Enable AHCI mode */ 659 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 660 /* Reset AHCI controller */ 661 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR); 662 for (timeout = 1000; timeout > 0; timeout--) { 663 DELAY(1000); 664 if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0) 665 break; 666 } 667 if (timeout == 0) { 668 device_printf(dev, "AHCI controller reset failure\n"); 669 return ENXIO; 670 } 671 /* Reenable AHCI mode */ 672 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 673 return (0); 674} 675 676static int 677ahci_ctlr_setup(device_t dev) 678{ 679 struct ahci_controller *ctlr = device_get_softc(dev); 680 /* Clear interrupts */ 681 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS)); 682 /* Configure CCC */ 683 if (ctlr->ccc) { 684 ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI)); 685 ATA_OUTL(ctlr->r_mem, AHCI_CCCC, 686 (ctlr->ccc << AHCI_CCCC_TV_SHIFT) | 687 (4 << AHCI_CCCC_CC_SHIFT) | 688 AHCI_CCCC_EN); 689 ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) & 690 AHCI_CCCC_INT_MASK) >> AHCI_CCCC_INT_SHIFT; 691 if (bootverbose) { 692 device_printf(dev, 693 "CCC with %dms/4cmd enabled on vector %d\n", 694 ctlr->ccc, ctlr->cccv); 695 } 696 } 697 /* Enable AHCI interrupts */ 698 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 699 ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE); 700 return (0); 701} 702 703static int 704ahci_suspend(device_t dev) 705{ 706 struct ahci_controller *ctlr = device_get_softc(dev); 707 708 bus_generic_suspend(dev); 709 /* Disable interupts, so the state change(s) doesn't trigger */ 710 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 711 ATA_INL(ctlr->r_mem, AHCI_GHC) & (~AHCI_GHC_IE)); 712 return 0; 713} 714 715static int 716ahci_resume(device_t dev) 717{ 718 int res; 719 720 if ((res = ahci_ctlr_reset(dev)) != 0) 721 return (res); 722 ahci_ctlr_setup(dev); 723 return (bus_generic_resume(dev)); 724} 725 726static int 727ahci_setup_interrupt(device_t dev) 728{ 729 struct ahci_controller *ctlr = device_get_softc(dev); 730 int i; 731 732 ctlr->msi = 2; 733 /* Process hints. */ 734 if (ctlr->quirks & AHCI_Q_NOMSI) 735 ctlr->msi = 0; 736 resource_int_value(device_get_name(dev), 737 device_get_unit(dev), "msi", &ctlr->msi); 738 ctlr->numirqs = 1; 739 if (ctlr->msi < 0) 740 ctlr->msi = 0; 741 else if (ctlr->msi == 1) 742 ctlr->msi = min(1, pci_msi_count(dev)); 743 else if (ctlr->msi > 1) { 744 ctlr->msi = 2; 745 ctlr->numirqs = pci_msi_count(dev); 746 } 747 /* Allocate MSI if needed/present. */ 748 if (ctlr->msi && pci_alloc_msi(dev, &ctlr->numirqs) != 0) { 749 ctlr->msi = 0; 750 ctlr->numirqs = 1; 751 } 752 /* Check for single MSI vector fallback. */ 753 if (ctlr->numirqs > 1 && 754 (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) { 755 device_printf(dev, "Falling back to one MSI\n"); 756 ctlr->numirqs = 1; 757 } 758 /* Allocate all IRQs. */ 759 for (i = 0; i < ctlr->numirqs; i++) { 760 ctlr->irqs[i].ctlr = ctlr; 761 ctlr->irqs[i].r_irq_rid = i + (ctlr->msi ? 1 : 0); 762 if (ctlr->numirqs == 1 || i >= ctlr->channels || 763 (ctlr->ccc && i == ctlr->cccv)) 764 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL; 765 else if (i == ctlr->numirqs - 1) 766 ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER; 767 else 768 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE; 769 if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 770 &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) { 771 device_printf(dev, "unable to map interrupt\n"); 772 return ENXIO; 773 } 774 if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL, 775 (ctlr->irqs[i].mode != AHCI_IRQ_MODE_ONE) ? ahci_intr : 776 ((ctlr->quirks & AHCI_Q_EDGEIS) ? ahci_intr_one_edge : 777 ahci_intr_one), 778 &ctlr->irqs[i], &ctlr->irqs[i].handle))) { 779 /* SOS XXX release r_irq */ 780 device_printf(dev, "unable to setup interrupt\n"); 781 return ENXIO; 782 } 783 if (ctlr->numirqs > 1) { 784 bus_describe_intr(dev, ctlr->irqs[i].r_irq, 785 ctlr->irqs[i].handle, 786 ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE ? 787 "ch%d" : "%d", i); 788 } 789 } 790 return (0); 791} 792 793/* 794 * Common case interrupt handler. 795 */ 796static void 797ahci_intr(void *data) 798{ 799 struct ahci_controller_irq *irq = data; 800 struct ahci_controller *ctlr = irq->ctlr; 801 u_int32_t is, ise = 0; 802 void *arg; 803 int unit; 804 805 if (irq->mode == AHCI_IRQ_MODE_ALL) { 806 unit = 0; 807 if (ctlr->ccc) 808 is = ctlr->ichannels; 809 else 810 is = ATA_INL(ctlr->r_mem, AHCI_IS); 811 } else { /* AHCI_IRQ_MODE_AFTER */ 812 unit = irq->r_irq_rid - 1; 813 is = ATA_INL(ctlr->r_mem, AHCI_IS); 814 } 815 /* CCC interrupt is edge triggered. */ 816 if (ctlr->ccc) 817 ise = 1 << ctlr->cccv; 818 /* Some controllers have edge triggered IS. */ 819 if (ctlr->quirks & AHCI_Q_EDGEIS) 820 ise |= is; 821 if (ise != 0) 822 ATA_OUTL(ctlr->r_mem, AHCI_IS, ise); 823 for (; unit < ctlr->channels; unit++) { 824 if ((is & (1 << unit)) != 0 && 825 (arg = ctlr->interrupt[unit].argument)) { 826 ctlr->interrupt[unit].function(arg); 827 } 828 } 829 /* AHCI declares level triggered IS. */ 830 if (!(ctlr->quirks & AHCI_Q_EDGEIS)) 831 ATA_OUTL(ctlr->r_mem, AHCI_IS, is); 832} 833 834/* 835 * Simplified interrupt handler for multivector MSI mode. 836 */ 837static void 838ahci_intr_one(void *data) 839{ 840 struct ahci_controller_irq *irq = data; 841 struct ahci_controller *ctlr = irq->ctlr; 842 void *arg; 843 int unit; 844 845 unit = irq->r_irq_rid - 1; 846 if ((arg = ctlr->interrupt[unit].argument)) 847 ctlr->interrupt[unit].function(arg); 848 /* AHCI declares level triggered IS. */ 849 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 850} 851 852static void 853ahci_intr_one_edge(void *data) 854{ 855 struct ahci_controller_irq *irq = data; 856 struct ahci_controller *ctlr = irq->ctlr; 857 void *arg; 858 int unit; 859 860 unit = irq->r_irq_rid - 1; 861 /* Some controllers have edge triggered IS. */ 862 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 863 if ((arg = ctlr->interrupt[unit].argument)) 864 ctlr->interrupt[unit].function(arg); 865} 866 867static struct resource * 868ahci_alloc_resource(device_t dev, device_t child, int type, int *rid, 869 u_long start, u_long end, u_long count, u_int flags) 870{ 871 struct ahci_controller *ctlr = device_get_softc(dev); 872 struct resource *res; 873 long st; 874 int offset, size, unit; 875 876 unit = (intptr_t)device_get_ivars(child); 877 res = NULL; 878 switch (type) { 879 case SYS_RES_MEMORY: 880 if (unit >= 0) { 881 offset = AHCI_OFFSET + (unit << 7); 882 size = 128; 883 } else if (*rid == 0) { 884 offset = AHCI_EM_CTL; 885 size = 4; 886 } else { 887 offset = (ctlr->emloc & 0xffff0000) >> 14; 888 size = (ctlr->emloc & 0x0000ffff) << 2; 889 if (*rid != 1) { 890 if (*rid == 2 && (ctlr->capsem & 891 (AHCI_EM_XMT | AHCI_EM_SMB)) == 0) 892 offset += size; 893 else 894 break; 895 } 896 } 897 st = rman_get_start(ctlr->r_mem); 898 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset, 899 st + offset + size - 1, size, RF_ACTIVE, child); 900 if (res) { 901 bus_space_handle_t bsh; 902 bus_space_tag_t bst; 903 bsh = rman_get_bushandle(ctlr->r_mem); 904 bst = rman_get_bustag(ctlr->r_mem); 905 bus_space_subregion(bst, bsh, offset, 128, &bsh); 906 rman_set_bushandle(res, bsh); 907 rman_set_bustag(res, bst); 908 } 909 break; 910 case SYS_RES_IRQ: 911 if (*rid == ATA_IRQ_RID) 912 res = ctlr->irqs[0].r_irq; 913 break; 914 } 915 return (res); 916} 917 918static int 919ahci_release_resource(device_t dev, device_t child, int type, int rid, 920 struct resource *r) 921{ 922 923 switch (type) { 924 case SYS_RES_MEMORY: 925 rman_release_resource(r); 926 return (0); 927 case SYS_RES_IRQ: 928 if (rid != ATA_IRQ_RID) 929 return ENOENT; 930 return (0); 931 } 932 return (EINVAL); 933} 934 935static int 936ahci_setup_intr(device_t dev, device_t child, struct resource *irq, 937 int flags, driver_filter_t *filter, driver_intr_t *function, 938 void *argument, void **cookiep) 939{ 940 struct ahci_controller *ctlr = device_get_softc(dev); 941 int unit = (intptr_t)device_get_ivars(child); 942 943 if (filter != NULL) { 944 printf("ahci.c: we cannot use a filter here\n"); 945 return (EINVAL); 946 } 947 ctlr->interrupt[unit].function = function; 948 ctlr->interrupt[unit].argument = argument; 949 return (0); 950} 951 952static int 953ahci_teardown_intr(device_t dev, device_t child, struct resource *irq, 954 void *cookie) 955{ 956 struct ahci_controller *ctlr = device_get_softc(dev); 957 int unit = (intptr_t)device_get_ivars(child); 958 959 ctlr->interrupt[unit].function = NULL; 960 ctlr->interrupt[unit].argument = NULL; 961 return (0); 962} 963 964static int 965ahci_print_child(device_t dev, device_t child) 966{ 967 int retval, channel; 968 969 retval = bus_print_child_header(dev, child); 970 channel = (int)(intptr_t)device_get_ivars(child); 971 if (channel >= 0) 972 retval += printf(" at channel %d", channel); 973 retval += bus_print_child_footer(dev, child); 974 return (retval); 975} 976 977static int 978ahci_child_location_str(device_t dev, device_t child, char *buf, 979 size_t buflen) 980{ 981 int channel; 982 983 channel = (int)(intptr_t)device_get_ivars(child); 984 if (channel >= 0) 985 snprintf(buf, buflen, "channel=%d", channel); 986 return (0); 987} 988 989static bus_dma_tag_t 990ahci_get_dma_tag(device_t dev, device_t child) 991{ 992 struct ahci_controller *ctlr = device_get_softc(dev); 993 994 return (ctlr->dma_tag); 995} 996 997devclass_t ahci_devclass; 998static device_method_t ahci_methods[] = { 999 DEVMETHOD(device_probe, ahci_probe), 1000 DEVMETHOD(device_attach, ahci_attach), 1001 DEVMETHOD(device_detach, ahci_detach), 1002 DEVMETHOD(device_suspend, ahci_suspend), 1003 DEVMETHOD(device_resume, ahci_resume), 1004 DEVMETHOD(bus_print_child, ahci_print_child), 1005 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 1006 DEVMETHOD(bus_release_resource, ahci_release_resource), 1007 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 1008 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 1009 DEVMETHOD(bus_child_location_str, ahci_child_location_str), 1010 DEVMETHOD(bus_get_dma_tag, ahci_get_dma_tag), 1011 { 0, 0 } 1012}; 1013static driver_t ahci_driver = { 1014 "ahci", 1015 ahci_methods, 1016 sizeof(struct ahci_controller) 1017}; 1018DRIVER_MODULE(ahci, pci, ahci_driver, ahci_devclass, 0, 0); 1019static device_method_t ahci_ata_methods[] = { 1020 DEVMETHOD(device_probe, ahci_ata_probe), 1021 DEVMETHOD(device_attach, ahci_attach), 1022 DEVMETHOD(device_detach, ahci_detach), 1023 DEVMETHOD(device_suspend, ahci_suspend), 1024 DEVMETHOD(device_resume, ahci_resume), 1025 DEVMETHOD(bus_print_child, ahci_print_child), 1026 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 1027 DEVMETHOD(bus_release_resource, ahci_release_resource), 1028 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 1029 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 1030 DEVMETHOD(bus_child_location_str, ahci_child_location_str), 1031 { 0, 0 } 1032}; 1033static driver_t ahci_ata_driver = { 1034 "ahci", 1035 ahci_ata_methods, 1036 sizeof(struct ahci_controller) 1037}; 1038DRIVER_MODULE(ahci, atapci, ahci_ata_driver, ahci_devclass, 0, 0); 1039MODULE_VERSION(ahci, 1); 1040MODULE_DEPEND(ahci, cam, 1, 1, 1); 1041 1042static int 1043ahci_ch_probe(device_t dev) 1044{ 1045 1046 device_set_desc_copy(dev, "AHCI channel"); 1047 return (0); 1048} 1049 1050static int 1051ahci_ch_attach(device_t dev) 1052{ 1053 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1054 struct ahci_channel *ch = device_get_softc(dev); 1055 struct cam_devq *devq; 1056 int rid, error, i, sata_rev = 0; 1057 u_int32_t version; 1058 1059 ch->dev = dev; 1060 ch->unit = (intptr_t)device_get_ivars(dev); 1061 ch->caps = ctlr->caps; 1062 ch->caps2 = ctlr->caps2; 1063 ch->quirks = ctlr->quirks; 1064 ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1; 1065 mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF); 1066 resource_int_value(device_get_name(dev), 1067 device_get_unit(dev), "pm_level", &ch->pm_level); 1068 STAILQ_INIT(&ch->doneq); 1069 if (ch->pm_level > 3) 1070 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0); 1071 callout_init_mtx(&ch->reset_timer, &ch->mtx, 0); 1072 /* Limit speed for my onboard JMicron external port. 1073 * It is not eSATA really. */ 1074 if (pci_get_devid(ctlr->dev) == 0x2363197b && 1075 pci_get_subvendor(ctlr->dev) == 0x1043 && 1076 pci_get_subdevice(ctlr->dev) == 0x81e4 && 1077 ch->unit == 0) 1078 sata_rev = 1; 1079 if (ch->quirks & AHCI_Q_SATA2) 1080 sata_rev = 2; 1081 resource_int_value(device_get_name(dev), 1082 device_get_unit(dev), "sata_rev", &sata_rev); 1083 for (i = 0; i < 16; i++) { 1084 ch->user[i].revision = sata_rev; 1085 ch->user[i].mode = 0; 1086 ch->user[i].bytecount = 8192; 1087 ch->user[i].tags = ch->numslots; 1088 ch->user[i].caps = 0; 1089 ch->curr[i] = ch->user[i]; 1090 if (ch->pm_level) { 1091 ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ | 1092 CTS_SATA_CAPS_H_APST | 1093 CTS_SATA_CAPS_D_PMREQ | CTS_SATA_CAPS_D_APST; 1094 } 1095 ch->user[i].caps |= CTS_SATA_CAPS_H_DMAAA | 1096 CTS_SATA_CAPS_H_AN; 1097 } 1098 rid = 0; 1099 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1100 &rid, RF_ACTIVE))) 1101 return (ENXIO); 1102 ahci_dmainit(dev); 1103 ahci_slotsalloc(dev); 1104 ahci_ch_init(dev); 1105 mtx_lock(&ch->mtx); 1106 rid = ATA_IRQ_RID; 1107 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1108 &rid, RF_SHAREABLE | RF_ACTIVE))) { 1109 device_printf(dev, "Unable to map interrupt\n"); 1110 error = ENXIO; 1111 goto err0; 1112 } 1113 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL, 1114 ctlr->direct ? ahci_ch_intr_direct : ahci_ch_intr, 1115 dev, &ch->ih))) { 1116 device_printf(dev, "Unable to setup interrupt\n"); 1117 error = ENXIO; 1118 goto err1; 1119 } 1120 ch->chcaps = ATA_INL(ch->r_mem, AHCI_P_CMD); 1121 version = ATA_INL(ctlr->r_mem, AHCI_VS); 1122 if (version < 0x00010200 && (ctlr->caps & AHCI_CAP_FBSS)) 1123 ch->chcaps |= AHCI_P_CMD_FBSCP; 1124 if (ch->caps2 & AHCI_CAP2_SDS) 1125 ch->chscaps = ATA_INL(ch->r_mem, AHCI_P_DEVSLP); 1126 if (bootverbose) { 1127 device_printf(dev, "Caps:%s%s%s%s%s%s\n", 1128 (ch->chcaps & AHCI_P_CMD_HPCP) ? " HPCP":"", 1129 (ch->chcaps & AHCI_P_CMD_MPSP) ? " MPSP":"", 1130 (ch->chcaps & AHCI_P_CMD_CPD) ? " CPD":"", 1131 (ch->chcaps & AHCI_P_CMD_ESP) ? " ESP":"", 1132 (ch->chcaps & AHCI_P_CMD_FBSCP) ? " FBSCP":"", 1133 (ch->chscaps & AHCI_P_DEVSLP_DSP) ? " DSP":""); 1134 } 1135 /* Create the device queue for our SIM. */ 1136 devq = cam_simq_alloc(ch->numslots); 1137 if (devq == NULL) { 1138 device_printf(dev, "Unable to allocate simq\n"); 1139 error = ENOMEM; 1140 goto err1; 1141 } 1142 /* Construct SIM entry */ 1143 ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch, 1144 device_get_unit(dev), &ch->mtx, 1145 min(2, ch->numslots), 1146 (ch->caps & AHCI_CAP_SNCQ) ? ch->numslots : 0, 1147 devq); 1148 if (ch->sim == NULL) { 1149 cam_simq_free(devq); 1150 device_printf(dev, "unable to allocate sim\n"); 1151 error = ENOMEM; 1152 goto err1; 1153 } 1154 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) { 1155 device_printf(dev, "unable to register xpt bus\n"); 1156 error = ENXIO; 1157 goto err2; 1158 } 1159 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim), 1160 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1161 device_printf(dev, "unable to create path\n"); 1162 error = ENXIO; 1163 goto err3; 1164 } 1165 if (ch->pm_level > 3) { 1166 callout_reset(&ch->pm_timer, 1167 (ch->pm_level == 4) ? hz / 1000 : hz / 8, 1168 ahci_ch_pm, dev); 1169 } 1170 mtx_unlock(&ch->mtx); 1171 return (0); 1172 1173err3: 1174 xpt_bus_deregister(cam_sim_path(ch->sim)); 1175err2: 1176 cam_sim_free(ch->sim, /*free_devq*/TRUE); 1177err1: 1178 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 1179err0: 1180 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 1181 mtx_unlock(&ch->mtx); 1182 mtx_destroy(&ch->mtx); 1183 return (error); 1184} 1185 1186static int 1187ahci_ch_detach(device_t dev) 1188{ 1189 struct ahci_channel *ch = device_get_softc(dev); 1190 1191 mtx_lock(&ch->mtx); 1192 xpt_async(AC_LOST_DEVICE, ch->path, NULL); 1193 /* Forget about reset. */ 1194 if (ch->resetting) { 1195 ch->resetting = 0; 1196 xpt_release_simq(ch->sim, TRUE); 1197 } 1198 xpt_free_path(ch->path); 1199 xpt_bus_deregister(cam_sim_path(ch->sim)); 1200 cam_sim_free(ch->sim, /*free_devq*/TRUE); 1201 mtx_unlock(&ch->mtx); 1202 1203 if (ch->pm_level > 3) 1204 callout_drain(&ch->pm_timer); 1205 callout_drain(&ch->reset_timer); 1206 bus_teardown_intr(dev, ch->r_irq, ch->ih); 1207 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 1208 1209 ahci_ch_deinit(dev); 1210 ahci_slotsfree(dev); 1211 ahci_dmafini(dev); 1212 1213 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 1214 mtx_destroy(&ch->mtx); 1215 return (0); 1216} 1217 1218static int 1219ahci_ch_init(device_t dev) 1220{ 1221 struct ahci_channel *ch = device_get_softc(dev); 1222 uint64_t work; 1223 1224 /* Disable port interrupts */ 1225 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 1226 /* Setup work areas */ 1227 work = ch->dma.work_bus + AHCI_CL_OFFSET; 1228 ATA_OUTL(ch->r_mem, AHCI_P_CLB, work & 0xffffffff); 1229 ATA_OUTL(ch->r_mem, AHCI_P_CLBU, work >> 32); 1230 work = ch->dma.rfis_bus; 1231 ATA_OUTL(ch->r_mem, AHCI_P_FB, work & 0xffffffff); 1232 ATA_OUTL(ch->r_mem, AHCI_P_FBU, work >> 32); 1233 /* Activate the channel and power/spin up device */ 1234 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 1235 (AHCI_P_CMD_ACTIVE | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1236 ((ch->pm_level == 2 || ch->pm_level == 3) ? AHCI_P_CMD_ALPE : 0) | 1237 ((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 ))); 1238 ahci_start_fr(dev); 1239 ahci_start(dev, 1); 1240 return (0); 1241} 1242 1243static int 1244ahci_ch_deinit(device_t dev) 1245{ 1246 struct ahci_channel *ch = device_get_softc(dev); 1247 1248 /* Disable port interrupts. */ 1249 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 1250 /* Reset command register. */ 1251 ahci_stop(dev); 1252 ahci_stop_fr(dev); 1253 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0); 1254 /* Allow everything, including partial and slumber modes. */ 1255 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0); 1256 /* Request slumber mode transition and give some time to get there. */ 1257 ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER); 1258 DELAY(100); 1259 /* Disable PHY. */ 1260 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 1261 return (0); 1262} 1263 1264static int 1265ahci_ch_suspend(device_t dev) 1266{ 1267 struct ahci_channel *ch = device_get_softc(dev); 1268 1269 mtx_lock(&ch->mtx); 1270 xpt_freeze_simq(ch->sim, 1); 1271 /* Forget about reset. */ 1272 if (ch->resetting) { 1273 ch->resetting = 0; 1274 callout_stop(&ch->reset_timer); 1275 xpt_release_simq(ch->sim, TRUE); 1276 } 1277 while (ch->oslots) 1278 msleep(ch, &ch->mtx, PRIBIO, "ahcisusp", hz/100); 1279 ahci_ch_deinit(dev); 1280 mtx_unlock(&ch->mtx); 1281 return (0); 1282} 1283 1284static int 1285ahci_ch_resume(device_t dev) 1286{ 1287 struct ahci_channel *ch = device_get_softc(dev); 1288 1289 mtx_lock(&ch->mtx); 1290 ahci_ch_init(dev); 1291 ahci_reset(dev); 1292 xpt_release_simq(ch->sim, TRUE); 1293 mtx_unlock(&ch->mtx); 1294 return (0); 1295} 1296 1297devclass_t ahcich_devclass; 1298static device_method_t ahcich_methods[] = { 1299 DEVMETHOD(device_probe, ahci_ch_probe), 1300 DEVMETHOD(device_attach, ahci_ch_attach), 1301 DEVMETHOD(device_detach, ahci_ch_detach), 1302 DEVMETHOD(device_suspend, ahci_ch_suspend), 1303 DEVMETHOD(device_resume, ahci_ch_resume), 1304 { 0, 0 } 1305}; 1306static driver_t ahcich_driver = { 1307 "ahcich", 1308 ahcich_methods, 1309 sizeof(struct ahci_channel) 1310}; 1311DRIVER_MODULE(ahcich, ahci, ahcich_driver, ahcich_devclass, 0, 0); 1312 1313struct ahci_dc_cb_args { 1314 bus_addr_t maddr; 1315 int error; 1316}; 1317 1318static void 1319ahci_dmainit(device_t dev) 1320{ 1321 struct ahci_channel *ch = device_get_softc(dev); 1322 struct ahci_dc_cb_args dcba; 1323 size_t rfsize; 1324 1325 /* Command area. */ 1326 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0, 1327 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1328 NULL, NULL, AHCI_WORK_SIZE, 1, AHCI_WORK_SIZE, 1329 0, NULL, NULL, &ch->dma.work_tag)) 1330 goto error; 1331 if (bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work, 1332 BUS_DMA_ZERO, &ch->dma.work_map)) 1333 goto error; 1334 if (bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work, 1335 AHCI_WORK_SIZE, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 1336 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 1337 goto error; 1338 } 1339 ch->dma.work_bus = dcba.maddr; 1340 /* FIS receive area. */ 1341 if (ch->chcaps & AHCI_P_CMD_FBSCP) 1342 rfsize = 4096; 1343 else 1344 rfsize = 256; 1345 if (bus_dma_tag_create(bus_get_dma_tag(dev), rfsize, 0, 1346 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1347 NULL, NULL, rfsize, 1, rfsize, 1348 0, NULL, NULL, &ch->dma.rfis_tag)) 1349 goto error; 1350 if (bus_dmamem_alloc(ch->dma.rfis_tag, (void **)&ch->dma.rfis, 0, 1351 &ch->dma.rfis_map)) 1352 goto error; 1353 if (bus_dmamap_load(ch->dma.rfis_tag, ch->dma.rfis_map, ch->dma.rfis, 1354 rfsize, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 1355 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1356 goto error; 1357 } 1358 ch->dma.rfis_bus = dcba.maddr; 1359 /* Data area. */ 1360 if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 1361 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1362 NULL, NULL, 1363 AHCI_SG_ENTRIES * PAGE_SIZE * ch->numslots, 1364 AHCI_SG_ENTRIES, AHCI_PRD_MAX, 1365 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) { 1366 goto error; 1367 } 1368 return; 1369 1370error: 1371 device_printf(dev, "WARNING - DMA initialization failed\n"); 1372 ahci_dmafini(dev); 1373} 1374 1375static void 1376ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 1377{ 1378 struct ahci_dc_cb_args *dcba = (struct ahci_dc_cb_args *)xsc; 1379 1380 if (!(dcba->error = error)) 1381 dcba->maddr = segs[0].ds_addr; 1382} 1383 1384static void 1385ahci_dmafini(device_t dev) 1386{ 1387 struct ahci_channel *ch = device_get_softc(dev); 1388 1389 if (ch->dma.data_tag) { 1390 bus_dma_tag_destroy(ch->dma.data_tag); 1391 ch->dma.data_tag = NULL; 1392 } 1393 if (ch->dma.rfis_bus) { 1394 bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map); 1395 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1396 ch->dma.rfis_bus = 0; 1397 ch->dma.rfis_map = NULL; 1398 ch->dma.rfis = NULL; 1399 } 1400 if (ch->dma.work_bus) { 1401 bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map); 1402 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 1403 ch->dma.work_bus = 0; 1404 ch->dma.work_map = NULL; 1405 ch->dma.work = NULL; 1406 } 1407 if (ch->dma.work_tag) { 1408 bus_dma_tag_destroy(ch->dma.work_tag); 1409 ch->dma.work_tag = NULL; 1410 } 1411} 1412 1413static void 1414ahci_slotsalloc(device_t dev) 1415{ 1416 struct ahci_channel *ch = device_get_softc(dev); 1417 int i; 1418 1419 /* Alloc and setup command/dma slots */ 1420 bzero(ch->slot, sizeof(ch->slot)); 1421 for (i = 0; i < ch->numslots; i++) { 1422 struct ahci_slot *slot = &ch->slot[i]; 1423 1424 slot->dev = dev; 1425 slot->slot = i; 1426 slot->state = AHCI_SLOT_EMPTY; 1427 slot->ccb = NULL; 1428 callout_init_mtx(&slot->timeout, &ch->mtx, 0); 1429 1430 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map)) 1431 device_printf(ch->dev, "FAILURE - create data_map\n"); 1432 } 1433} 1434 1435static void 1436ahci_slotsfree(device_t dev) 1437{ 1438 struct ahci_channel *ch = device_get_softc(dev); 1439 int i; 1440 1441 /* Free all dma slots */ 1442 for (i = 0; i < ch->numslots; i++) { 1443 struct ahci_slot *slot = &ch->slot[i]; 1444 1445 callout_drain(&slot->timeout); 1446 if (slot->dma.data_map) { 1447 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map); 1448 slot->dma.data_map = NULL; 1449 } 1450 } 1451} 1452 1453static int 1454ahci_phy_check_events(device_t dev, u_int32_t serr) 1455{ 1456 struct ahci_channel *ch = device_get_softc(dev); 1457 1458 if (((ch->pm_level == 0) && (serr & ATA_SE_PHY_CHANGED)) || 1459 ((ch->pm_level != 0 || ch->listening) && (serr & ATA_SE_EXCHANGED))) { 1460 u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 1461 union ccb *ccb; 1462 1463 if (bootverbose) { 1464 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE) 1465 device_printf(dev, "CONNECT requested\n"); 1466 else 1467 device_printf(dev, "DISCONNECT requested\n"); 1468 } 1469 ahci_reset(dev); 1470 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 1471 return (0); 1472 if (xpt_create_path(&ccb->ccb_h.path, NULL, 1473 cam_sim_path(ch->sim), 1474 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1475 xpt_free_ccb(ccb); 1476 return (0); 1477 } 1478 xpt_rescan(ccb); 1479 return (1); 1480 } 1481 return (0); 1482} 1483 1484static void 1485ahci_cpd_check_events(device_t dev) 1486{ 1487 struct ahci_channel *ch = device_get_softc(dev); 1488 u_int32_t status; 1489 union ccb *ccb; 1490 1491 if (ch->pm_level == 0) 1492 return; 1493 1494 status = ATA_INL(ch->r_mem, AHCI_P_CMD); 1495 if ((status & AHCI_P_CMD_CPD) == 0) 1496 return; 1497 1498 if (bootverbose) { 1499 if (status & AHCI_P_CMD_CPS) { 1500 device_printf(dev, "COLD CONNECT requested\n"); 1501 } else 1502 device_printf(dev, "COLD DISCONNECT requested\n"); 1503 } 1504 ahci_reset(dev); 1505 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 1506 return; 1507 if (xpt_create_path(&ccb->ccb_h.path, NULL, cam_sim_path(ch->sim), 1508 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1509 xpt_free_ccb(ccb); 1510 return; 1511 } 1512 xpt_rescan(ccb); 1513} 1514 1515static void 1516ahci_notify_events(device_t dev, u_int32_t status) 1517{ 1518 struct ahci_channel *ch = device_get_softc(dev); 1519 struct cam_path *dpath; 1520 int i; 1521 1522 if (ch->caps & AHCI_CAP_SSNTF) 1523 ATA_OUTL(ch->r_mem, AHCI_P_SNTF, status); 1524 if (bootverbose) 1525 device_printf(dev, "SNTF 0x%04x\n", status); 1526 for (i = 0; i < 16; i++) { 1527 if ((status & (1 << i)) == 0) 1528 continue; 1529 if (xpt_create_path(&dpath, NULL, 1530 xpt_path_path_id(ch->path), i, 0) == CAM_REQ_CMP) { 1531 xpt_async(AC_SCSI_AEN, dpath, NULL); 1532 xpt_free_path(dpath); 1533 } 1534 } 1535} 1536 1537static void 1538ahci_done(struct ahci_channel *ch, union ccb *ccb) 1539{ 1540 1541 mtx_assert(&ch->mtx, MA_OWNED); 1542 if ((ccb->ccb_h.func_code & XPT_FC_QUEUED) == 0 || 1543 ch->batch == 0) { 1544 xpt_done(ccb); 1545 return; 1546 } 1547 1548 STAILQ_INSERT_TAIL(&ch->doneq, &ccb->ccb_h, sim_links.stqe); 1549} 1550 1551static void 1552ahci_ch_intr(void *arg) 1553{ 1554 device_t dev = (device_t)arg; 1555 struct ahci_channel *ch = device_get_softc(dev); 1556 uint32_t istatus; 1557 1558 /* Read interrupt statuses. */ 1559 istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 1560 if (istatus == 0) 1561 return; 1562 1563 mtx_lock(&ch->mtx); 1564 ahci_ch_intr_main(ch, istatus); 1565 mtx_unlock(&ch->mtx); 1566} 1567 1568static void 1569ahci_ch_intr_direct(void *arg) 1570{ 1571 device_t dev = (device_t)arg; 1572 struct ahci_channel *ch = device_get_softc(dev); 1573 struct ccb_hdr *ccb_h; 1574 uint32_t istatus; 1575 1576 /* Read interrupt statuses. */ 1577 istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 1578 if (istatus == 0) 1579 return; 1580 1581 mtx_lock(&ch->mtx); 1582 ch->batch = 1; 1583 ahci_ch_intr_main(ch, istatus); 1584 ch->batch = 0; 1585 mtx_unlock(&ch->mtx); 1586 while ((ccb_h = STAILQ_FIRST(&ch->doneq)) != NULL) { 1587 STAILQ_REMOVE_HEAD(&ch->doneq, sim_links.stqe); 1588 xpt_done_direct((union ccb *)ccb_h); 1589 } 1590} 1591 1592static void 1593ahci_ch_pm(void *arg) 1594{ 1595 device_t dev = (device_t)arg; 1596 struct ahci_channel *ch = device_get_softc(dev); 1597 uint32_t work; 1598 1599 if (ch->numrslots != 0) 1600 return; 1601 work = ATA_INL(ch->r_mem, AHCI_P_CMD); 1602 if (ch->pm_level == 4) 1603 work |= AHCI_P_CMD_PARTIAL; 1604 else 1605 work |= AHCI_P_CMD_SLUMBER; 1606 ATA_OUTL(ch->r_mem, AHCI_P_CMD, work); 1607} 1608 1609static void 1610ahci_ch_intr_main(struct ahci_channel *ch, uint32_t istatus) 1611{ 1612 device_t dev = ch->dev; 1613 uint32_t cstatus, serr = 0, sntf = 0, ok, err; 1614 enum ahci_err_type et; 1615 int i, ccs, port, reset = 0; 1616 1617 /* Clear interrupt statuses. */ 1618 ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus); 1619 /* Read command statuses. */ 1620 if (ch->numtslots != 0) 1621 cstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1622 else 1623 cstatus = 0; 1624 if (ch->numrslots != ch->numtslots) 1625 cstatus |= ATA_INL(ch->r_mem, AHCI_P_CI); 1626 /* Read SNTF in one of possible ways. */ 1627 if ((istatus & AHCI_P_IX_SDB) && 1628 (ch->pm_present || ch->curr[0].atapi != 0)) { 1629 if (ch->caps & AHCI_CAP_SSNTF) 1630 sntf = ATA_INL(ch->r_mem, AHCI_P_SNTF); 1631 else if (ch->fbs_enabled) { 1632 u_int8_t *fis = ch->dma.rfis + 0x58; 1633 1634 for (i = 0; i < 16; i++) { 1635 if (fis[1] & 0x80) { 1636 fis[1] &= 0x7f; 1637 sntf |= 1 << i; 1638 } 1639 fis += 256; 1640 } 1641 } else { 1642 u_int8_t *fis = ch->dma.rfis + 0x58; 1643 1644 if (fis[1] & 0x80) 1645 sntf = (1 << (fis[1] & 0x0f)); 1646 } 1647 } 1648 /* Process PHY events */ 1649 if (istatus & (AHCI_P_IX_PC | AHCI_P_IX_PRC | AHCI_P_IX_OF | 1650 AHCI_P_IX_IF | AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1651 serr = ATA_INL(ch->r_mem, AHCI_P_SERR); 1652 if (serr) { 1653 ATA_OUTL(ch->r_mem, AHCI_P_SERR, serr); 1654 reset = ahci_phy_check_events(dev, serr); 1655 } 1656 } 1657 /* Process cold presence detection events */ 1658 if ((istatus & AHCI_P_IX_CPD) && !reset) 1659 ahci_cpd_check_events(dev); 1660 /* Process command errors */ 1661 if (istatus & (AHCI_P_IX_OF | AHCI_P_IX_IF | 1662 AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1663 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1664 >> AHCI_P_CMD_CCS_SHIFT; 1665//device_printf(dev, "%s ERROR is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x fbs %08x ccs %d\n", 1666// __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD), 1667// serr, ATA_INL(ch->r_mem, AHCI_P_FBS), ccs); 1668 port = -1; 1669 if (ch->fbs_enabled) { 1670 uint32_t fbs = ATA_INL(ch->r_mem, AHCI_P_FBS); 1671 if (fbs & AHCI_P_FBS_SDE) { 1672 port = (fbs & AHCI_P_FBS_DWE) 1673 >> AHCI_P_FBS_DWE_SHIFT; 1674 } else { 1675 for (i = 0; i < 16; i++) { 1676 if (ch->numrslotspd[i] == 0) 1677 continue; 1678 if (port == -1) 1679 port = i; 1680 else if (port != i) { 1681 port = -2; 1682 break; 1683 } 1684 } 1685 } 1686 } 1687 err = ch->rslots & cstatus; 1688 } else { 1689 ccs = 0; 1690 err = 0; 1691 port = -1; 1692 } 1693 /* Complete all successfull commands. */ 1694 ok = ch->rslots & ~cstatus; 1695 for (i = 0; i < ch->numslots; i++) { 1696 if ((ok >> i) & 1) 1697 ahci_end_transaction(&ch->slot[i], AHCI_ERR_NONE); 1698 } 1699 /* On error, complete the rest of commands with error statuses. */ 1700 if (err) { 1701 if (ch->frozen) { 1702 union ccb *fccb = ch->frozen; 1703 ch->frozen = NULL; 1704 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1705 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1706 xpt_freeze_devq(fccb->ccb_h.path, 1); 1707 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1708 } 1709 ahci_done(ch, fccb); 1710 } 1711 for (i = 0; i < ch->numslots; i++) { 1712 /* XXX: reqests in loading state. */ 1713 if (((err >> i) & 1) == 0) 1714 continue; 1715 if (port >= 0 && 1716 ch->slot[i].ccb->ccb_h.target_id != port) 1717 continue; 1718 if (istatus & AHCI_P_IX_TFE) { 1719 if (port != -2) { 1720 /* Task File Error */ 1721 if (ch->numtslotspd[ 1722 ch->slot[i].ccb->ccb_h.target_id] == 0) { 1723 /* Untagged operation. */ 1724 if (i == ccs) 1725 et = AHCI_ERR_TFE; 1726 else 1727 et = AHCI_ERR_INNOCENT; 1728 } else { 1729 /* Tagged operation. */ 1730 et = AHCI_ERR_NCQ; 1731 } 1732 } else { 1733 et = AHCI_ERR_TFE; 1734 ch->fatalerr = 1; 1735 } 1736 } else if (istatus & AHCI_P_IX_IF) { 1737 if (ch->numtslots == 0 && i != ccs && port != -2) 1738 et = AHCI_ERR_INNOCENT; 1739 else 1740 et = AHCI_ERR_SATA; 1741 } else 1742 et = AHCI_ERR_INVALID; 1743 ahci_end_transaction(&ch->slot[i], et); 1744 } 1745 /* 1746 * We can't reinit port if there are some other 1747 * commands active, use resume to complete them. 1748 */ 1749 if (ch->rslots != 0 && !ch->recoverycmd) 1750 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | AHCI_P_FBS_DEC); 1751 } 1752 /* Process NOTIFY events */ 1753 if (sntf) 1754 ahci_notify_events(dev, sntf); 1755} 1756 1757/* Must be called with channel locked. */ 1758static int 1759ahci_check_collision(device_t dev, union ccb *ccb) 1760{ 1761 struct ahci_channel *ch = device_get_softc(dev); 1762 int t = ccb->ccb_h.target_id; 1763 1764 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1765 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1766 /* Tagged command while we have no supported tag free. */ 1767 if (((~ch->oslots) & (0xffffffff >> (32 - 1768 ch->curr[t].tags))) == 0) 1769 return (1); 1770 /* If we have FBS */ 1771 if (ch->fbs_enabled) { 1772 /* Tagged command while untagged are active. */ 1773 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] == 0) 1774 return (1); 1775 } else { 1776 /* Tagged command while untagged are active. */ 1777 if (ch->numrslots != 0 && ch->numtslots == 0) 1778 return (1); 1779 /* Tagged command while tagged to other target is active. */ 1780 if (ch->numtslots != 0 && 1781 ch->taggedtarget != ccb->ccb_h.target_id) 1782 return (1); 1783 } 1784 } else { 1785 /* If we have FBS */ 1786 if (ch->fbs_enabled) { 1787 /* Untagged command while tagged are active. */ 1788 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] != 0) 1789 return (1); 1790 } else { 1791 /* Untagged command while tagged are active. */ 1792 if (ch->numrslots != 0 && ch->numtslots != 0) 1793 return (1); 1794 } 1795 } 1796 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1797 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) { 1798 /* Atomic command while anything active. */ 1799 if (ch->numrslots != 0) 1800 return (1); 1801 } 1802 /* We have some atomic command running. */ 1803 if (ch->aslots != 0) 1804 return (1); 1805 return (0); 1806} 1807 1808/* Must be called with channel locked. */ 1809static void 1810ahci_begin_transaction(device_t dev, union ccb *ccb) 1811{ 1812 struct ahci_channel *ch = device_get_softc(dev); 1813 struct ahci_slot *slot; 1814 int tag, tags; 1815 1816 /* Choose empty slot. */ 1817 tags = ch->numslots; 1818 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1819 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) 1820 tags = ch->curr[ccb->ccb_h.target_id].tags; 1821 tag = ch->lastslot; 1822 while (1) { 1823 if (tag >= tags) 1824 tag = 0; 1825 if (ch->slot[tag].state == AHCI_SLOT_EMPTY) 1826 break; 1827 tag++; 1828 }; 1829 ch->lastslot = tag; 1830 /* Occupy chosen slot. */ 1831 slot = &ch->slot[tag]; 1832 slot->ccb = ccb; 1833 /* Stop PM timer. */ 1834 if (ch->numrslots == 0 && ch->pm_level > 3) 1835 callout_stop(&ch->pm_timer); 1836 /* Update channel stats. */ 1837 ch->oslots |= (1 << slot->slot); 1838 ch->numrslots++; 1839 ch->numrslotspd[ccb->ccb_h.target_id]++; 1840 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1841 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1842 ch->numtslots++; 1843 ch->numtslotspd[ccb->ccb_h.target_id]++; 1844 ch->taggedtarget = ccb->ccb_h.target_id; 1845 } 1846 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1847 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) 1848 ch->aslots |= (1 << slot->slot); 1849 slot->dma.nsegs = 0; 1850 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1851 slot->state = AHCI_SLOT_LOADING; 1852 bus_dmamap_load_ccb(ch->dma.data_tag, slot->dma.data_map, ccb, 1853 ahci_dmasetprd, slot, 0); 1854 } else 1855 ahci_execute_transaction(slot); 1856} 1857 1858/* Locked by busdma engine. */ 1859static void 1860ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1861{ 1862 struct ahci_slot *slot = arg; 1863 struct ahci_channel *ch = device_get_softc(slot->dev); 1864 struct ahci_cmd_tab *ctp; 1865 struct ahci_dma_prd *prd; 1866 int i; 1867 1868 if (error) { 1869 device_printf(slot->dev, "DMA load error\n"); 1870 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1871 return; 1872 } 1873 KASSERT(nsegs <= AHCI_SG_ENTRIES, ("too many DMA segment entries\n")); 1874 /* Get a piece of the workspace for this request */ 1875 ctp = (struct ahci_cmd_tab *) 1876 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1877 /* Fill S/G table */ 1878 prd = &ctp->prd_tab[0]; 1879 for (i = 0; i < nsegs; i++) { 1880 prd[i].dba = htole64(segs[i].ds_addr); 1881 prd[i].dbc = htole32((segs[i].ds_len - 1) & AHCI_PRD_MASK); 1882 } 1883 slot->dma.nsegs = nsegs; 1884 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1885 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ? 1886 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1887 ahci_execute_transaction(slot); 1888} 1889 1890/* Must be called with channel locked. */ 1891static void 1892ahci_execute_transaction(struct ahci_slot *slot) 1893{ 1894 device_t dev = slot->dev; 1895 struct ahci_channel *ch = device_get_softc(dev); 1896 struct ahci_cmd_tab *ctp; 1897 struct ahci_cmd_list *clp; 1898 union ccb *ccb = slot->ccb; 1899 int port = ccb->ccb_h.target_id & 0x0f; 1900 int fis_size, i, softreset; 1901 uint8_t *fis = ch->dma.rfis + 0x40; 1902 uint8_t val; 1903 1904 /* Get a piece of the workspace for this request */ 1905 ctp = (struct ahci_cmd_tab *) 1906 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1907 /* Setup the FIS for this request */ 1908 if (!(fis_size = ahci_setup_fis(dev, ctp, ccb, slot->slot))) { 1909 device_printf(ch->dev, "Setting up SATA FIS failed\n"); 1910 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1911 return; 1912 } 1913 /* Setup the command list entry */ 1914 clp = (struct ahci_cmd_list *) 1915 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 1916 clp->cmd_flags = htole16( 1917 (ccb->ccb_h.flags & CAM_DIR_OUT ? AHCI_CMD_WRITE : 0) | 1918 (ccb->ccb_h.func_code == XPT_SCSI_IO ? 1919 (AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH) : 0) | 1920 (fis_size / sizeof(u_int32_t)) | 1921 (port << 12)); 1922 clp->prd_length = htole16(slot->dma.nsegs); 1923 /* Special handling for Soft Reset command. */ 1924 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1925 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) { 1926 if (ccb->ataio.cmd.control & ATA_A_RESET) { 1927 softreset = 1; 1928 /* Kick controller into sane state */ 1929 ahci_stop(dev); 1930 ahci_clo(dev); 1931 ahci_start(dev, 0); 1932 clp->cmd_flags |= AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY; 1933 } else { 1934 softreset = 2; 1935 /* Prepare FIS receive area for check. */ 1936 for (i = 0; i < 20; i++) 1937 fis[i] = 0xff; 1938 } 1939 } else 1940 softreset = 0; 1941 clp->bytecount = 0; 1942 clp->cmd_table_phys = htole64(ch->dma.work_bus + AHCI_CT_OFFSET + 1943 (AHCI_CT_SIZE * slot->slot)); 1944 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1945 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1946 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1947 BUS_DMASYNC_PREREAD); 1948 /* Set ACTIVE bit for NCQ commands. */ 1949 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1950 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1951 ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot); 1952 } 1953 /* If FBS is enabled, set PMP port. */ 1954 if (ch->fbs_enabled) { 1955 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | 1956 (port << AHCI_P_FBS_DEV_SHIFT)); 1957 } 1958 /* Issue command to the controller. */ 1959 slot->state = AHCI_SLOT_RUNNING; 1960 ch->rslots |= (1 << slot->slot); 1961 ATA_OUTL(ch->r_mem, AHCI_P_CI, (1 << slot->slot)); 1962 /* Device reset commands doesn't interrupt. Poll them. */ 1963 if (ccb->ccb_h.func_code == XPT_ATA_IO && 1964 (ccb->ataio.cmd.command == ATA_DEVICE_RESET || softreset)) { 1965 int count, timeout = ccb->ccb_h.timeout * 100; 1966 enum ahci_err_type et = AHCI_ERR_NONE; 1967 1968 for (count = 0; count < timeout; count++) { 1969 DELAY(10); 1970 if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot))) 1971 break; 1972 if ((ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) && 1973 softreset != 1) { 1974#if 0 1975 device_printf(ch->dev, 1976 "Poll error on slot %d, TFD: %04x\n", 1977 slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD)); 1978#endif 1979 et = AHCI_ERR_TFE; 1980 break; 1981 } 1982 /* Workaround for ATI SB600/SB700 chipsets. */ 1983 if (ccb->ccb_h.target_id == 15 && 1984 pci_get_vendor(device_get_parent(dev)) == 0x1002 && 1985 (ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) { 1986 et = AHCI_ERR_TIMEOUT; 1987 break; 1988 } 1989 } 1990 1991 /* 1992 * Marvell HBAs with non-RAID firmware do not wait for 1993 * readiness after soft reset, so we have to wait here. 1994 * Marvell RAIDs do not have this problem, but instead 1995 * sometimes forget to update FIS receive area, breaking 1996 * this wait. 1997 */ 1998 if ((ch->quirks & AHCI_Q_NOBSYRES) == 0 && 1999 softreset == 2 && et == AHCI_ERR_NONE) { 2000 while ((val = fis[2]) & ATA_S_BUSY) { 2001 DELAY(10); 2002 if (count++ >= timeout) 2003 break; 2004 } 2005 } 2006 2007 if (timeout && (count >= timeout)) { 2008 device_printf(dev, "Poll timeout on slot %d port %d\n", 2009 slot->slot, port); 2010 device_printf(dev, "is %08x cs %08x ss %08x " 2011 "rs %08x tfd %02x serr %08x cmd %08x\n", 2012 ATA_INL(ch->r_mem, AHCI_P_IS), 2013 ATA_INL(ch->r_mem, AHCI_P_CI), 2014 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 2015 ATA_INL(ch->r_mem, AHCI_P_TFD), 2016 ATA_INL(ch->r_mem, AHCI_P_SERR), 2017 ATA_INL(ch->r_mem, AHCI_P_CMD)); 2018 et = AHCI_ERR_TIMEOUT; 2019 } 2020 2021 /* Kick controller into sane state and enable FBS. */ 2022 if (softreset == 2) 2023 ch->eslots |= (1 << slot->slot); 2024 ahci_end_transaction(slot, et); 2025 return; 2026 } 2027 /* Start command execution timeout */ 2028 callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 2000, 2029 (timeout_t*)ahci_timeout, slot); 2030 return; 2031} 2032 2033/* Must be called with channel locked. */ 2034static void 2035ahci_process_timeout(device_t dev) 2036{ 2037 struct ahci_channel *ch = device_get_softc(dev); 2038 int i; 2039 2040 mtx_assert(&ch->mtx, MA_OWNED); 2041 /* Handle the rest of commands. */ 2042 for (i = 0; i < ch->numslots; i++) { 2043 /* Do we have a running request on slot? */ 2044 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 2045 continue; 2046 ahci_end_transaction(&ch->slot[i], AHCI_ERR_TIMEOUT); 2047 } 2048} 2049 2050/* Must be called with channel locked. */ 2051static void 2052ahci_rearm_timeout(device_t dev) 2053{ 2054 struct ahci_channel *ch = device_get_softc(dev); 2055 int i; 2056 2057 mtx_assert(&ch->mtx, MA_OWNED); 2058 for (i = 0; i < ch->numslots; i++) { 2059 struct ahci_slot *slot = &ch->slot[i]; 2060 2061 /* Do we have a running request on slot? */ 2062 if (slot->state < AHCI_SLOT_RUNNING) 2063 continue; 2064 if ((ch->toslots & (1 << i)) == 0) 2065 continue; 2066 callout_reset(&slot->timeout, 2067 (int)slot->ccb->ccb_h.timeout * hz / 2000, 2068 (timeout_t*)ahci_timeout, slot); 2069 } 2070} 2071 2072/* Locked by callout mechanism. */ 2073static void 2074ahci_timeout(struct ahci_slot *slot) 2075{ 2076 device_t dev = slot->dev; 2077 struct ahci_channel *ch = device_get_softc(dev); 2078 uint32_t sstatus; 2079 int ccs; 2080 int i; 2081 2082 /* Check for stale timeout. */ 2083 if (slot->state < AHCI_SLOT_RUNNING) 2084 return; 2085 2086 /* Check if slot was not being executed last time we checked. */ 2087 if (slot->state < AHCI_SLOT_EXECUTING) { 2088 /* Check if slot started executing. */ 2089 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 2090 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 2091 >> AHCI_P_CMD_CCS_SHIFT; 2092 if ((sstatus & (1 << slot->slot)) != 0 || ccs == slot->slot || 2093 ch->fbs_enabled || ch->wrongccs) 2094 slot->state = AHCI_SLOT_EXECUTING; 2095 else if ((ch->rslots & (1 << ccs)) == 0) { 2096 ch->wrongccs = 1; 2097 slot->state = AHCI_SLOT_EXECUTING; 2098 } 2099 2100 callout_reset(&slot->timeout, 2101 (int)slot->ccb->ccb_h.timeout * hz / 2000, 2102 (timeout_t*)ahci_timeout, slot); 2103 return; 2104 } 2105 2106 device_printf(dev, "Timeout on slot %d port %d\n", 2107 slot->slot, slot->ccb->ccb_h.target_id & 0x0f); 2108 device_printf(dev, "is %08x cs %08x ss %08x rs %08x tfd %02x " 2109 "serr %08x cmd %08x\n", 2110 ATA_INL(ch->r_mem, AHCI_P_IS), ATA_INL(ch->r_mem, AHCI_P_CI), 2111 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 2112 ATA_INL(ch->r_mem, AHCI_P_TFD), ATA_INL(ch->r_mem, AHCI_P_SERR), 2113 ATA_INL(ch->r_mem, AHCI_P_CMD)); 2114 2115 /* Handle frozen command. */ 2116 if (ch->frozen) { 2117 union ccb *fccb = ch->frozen; 2118 ch->frozen = NULL; 2119 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 2120 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 2121 xpt_freeze_devq(fccb->ccb_h.path, 1); 2122 fccb->ccb_h.status |= CAM_DEV_QFRZN; 2123 } 2124 ahci_done(ch, fccb); 2125 } 2126 if (!ch->fbs_enabled && !ch->wrongccs) { 2127 /* Without FBS we know real timeout source. */ 2128 ch->fatalerr = 1; 2129 /* Handle command with timeout. */ 2130 ahci_end_transaction(&ch->slot[slot->slot], AHCI_ERR_TIMEOUT); 2131 /* Handle the rest of commands. */ 2132 for (i = 0; i < ch->numslots; i++) { 2133 /* Do we have a running request on slot? */ 2134 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 2135 continue; 2136 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 2137 } 2138 } else { 2139 /* With FBS we wait for other commands timeout and pray. */ 2140 if (ch->toslots == 0) 2141 xpt_freeze_simq(ch->sim, 1); 2142 ch->toslots |= (1 << slot->slot); 2143 if ((ch->rslots & ~ch->toslots) == 0) 2144 ahci_process_timeout(dev); 2145 else 2146 device_printf(dev, " ... waiting for slots %08x\n", 2147 ch->rslots & ~ch->toslots); 2148 } 2149} 2150 2151/* Must be called with channel locked. */ 2152static void 2153ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et) 2154{ 2155 device_t dev = slot->dev; 2156 struct ahci_channel *ch = device_get_softc(dev); 2157 union ccb *ccb = slot->ccb; 2158 struct ahci_cmd_list *clp; 2159 int lastto; 2160 uint32_t sig; 2161 2162 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 2163 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2164 clp = (struct ahci_cmd_list *) 2165 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 2166 /* Read result registers to the result struct 2167 * May be incorrect if several commands finished same time, 2168 * so read only when sure or have to. 2169 */ 2170 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 2171 struct ata_res *res = &ccb->ataio.res; 2172 2173 if ((et == AHCI_ERR_TFE) || 2174 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) { 2175 u_int8_t *fis = ch->dma.rfis + 0x40; 2176 2177 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 2178 BUS_DMASYNC_POSTREAD); 2179 if (ch->fbs_enabled) { 2180 fis += ccb->ccb_h.target_id * 256; 2181 res->status = fis[2]; 2182 res->error = fis[3]; 2183 } else { 2184 uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD); 2185 2186 res->status = tfd; 2187 res->error = tfd >> 8; 2188 } 2189 res->lba_low = fis[4]; 2190 res->lba_mid = fis[5]; 2191 res->lba_high = fis[6]; 2192 res->device = fis[7]; 2193 res->lba_low_exp = fis[8]; 2194 res->lba_mid_exp = fis[9]; 2195 res->lba_high_exp = fis[10]; 2196 res->sector_count = fis[12]; 2197 res->sector_count_exp = fis[13]; 2198 2199 /* 2200 * Some weird controllers do not return signature in 2201 * FIS receive area. Read it from PxSIG register. 2202 */ 2203 if ((ch->quirks & AHCI_Q_ALTSIG) && 2204 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 2205 (ccb->ataio.cmd.control & ATA_A_RESET) == 0) { 2206 sig = ATA_INL(ch->r_mem, AHCI_P_SIG); 2207 res->lba_high = sig >> 24; 2208 res->lba_mid = sig >> 16; 2209 res->lba_low = sig >> 8; 2210 res->sector_count = sig; 2211 } 2212 } else 2213 bzero(res, sizeof(*res)); 2214 if ((ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) == 0 && 2215 (ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2216 (ch->quirks & AHCI_Q_NOCOUNT) == 0) { 2217 ccb->ataio.resid = 2218 ccb->ataio.dxfer_len - le32toh(clp->bytecount); 2219 } 2220 } else { 2221 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2222 (ch->quirks & AHCI_Q_NOCOUNT) == 0) { 2223 ccb->csio.resid = 2224 ccb->csio.dxfer_len - le32toh(clp->bytecount); 2225 } 2226 } 2227 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 2228 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 2229 (ccb->ccb_h.flags & CAM_DIR_IN) ? 2230 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2231 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map); 2232 } 2233 if (et != AHCI_ERR_NONE) 2234 ch->eslots |= (1 << slot->slot); 2235 /* In case of error, freeze device for proper recovery. */ 2236 if ((et != AHCI_ERR_NONE) && (!ch->recoverycmd) && 2237 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) { 2238 xpt_freeze_devq(ccb->ccb_h.path, 1); 2239 ccb->ccb_h.status |= CAM_DEV_QFRZN; 2240 } 2241 /* Set proper result status. */ 2242 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2243 switch (et) { 2244 case AHCI_ERR_NONE: 2245 ccb->ccb_h.status |= CAM_REQ_CMP; 2246 if (ccb->ccb_h.func_code == XPT_SCSI_IO) 2247 ccb->csio.scsi_status = SCSI_STATUS_OK; 2248 break; 2249 case AHCI_ERR_INVALID: 2250 ch->fatalerr = 1; 2251 ccb->ccb_h.status |= CAM_REQ_INVALID; 2252 break; 2253 case AHCI_ERR_INNOCENT: 2254 ccb->ccb_h.status |= CAM_REQUEUE_REQ; 2255 break; 2256 case AHCI_ERR_TFE: 2257 case AHCI_ERR_NCQ: 2258 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 2259 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 2260 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 2261 } else { 2262 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR; 2263 } 2264 break; 2265 case AHCI_ERR_SATA: 2266 ch->fatalerr = 1; 2267 if (!ch->recoverycmd) { 2268 xpt_freeze_simq(ch->sim, 1); 2269 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2270 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 2271 } 2272 ccb->ccb_h.status |= CAM_UNCOR_PARITY; 2273 break; 2274 case AHCI_ERR_TIMEOUT: 2275 if (!ch->recoverycmd) { 2276 xpt_freeze_simq(ch->sim, 1); 2277 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2278 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 2279 } 2280 ccb->ccb_h.status |= CAM_CMD_TIMEOUT; 2281 break; 2282 default: 2283 ch->fatalerr = 1; 2284 ccb->ccb_h.status |= CAM_REQ_CMP_ERR; 2285 } 2286 /* Free slot. */ 2287 ch->oslots &= ~(1 << slot->slot); 2288 ch->rslots &= ~(1 << slot->slot); 2289 ch->aslots &= ~(1 << slot->slot); 2290 slot->state = AHCI_SLOT_EMPTY; 2291 slot->ccb = NULL; 2292 /* Update channel stats. */ 2293 ch->numrslots--; 2294 ch->numrslotspd[ccb->ccb_h.target_id]--; 2295 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 2296 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 2297 ch->numtslots--; 2298 ch->numtslotspd[ccb->ccb_h.target_id]--; 2299 } 2300 /* Cancel timeout state if request completed normally. */ 2301 if (et != AHCI_ERR_TIMEOUT) { 2302 lastto = (ch->toslots == (1 << slot->slot)); 2303 ch->toslots &= ~(1 << slot->slot); 2304 if (lastto) 2305 xpt_release_simq(ch->sim, TRUE); 2306 } 2307 /* If it was first request of reset sequence and there is no error, 2308 * proceed to second request. */ 2309 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 2310 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 2311 (ccb->ataio.cmd.control & ATA_A_RESET) && 2312 et == AHCI_ERR_NONE) { 2313 ccb->ataio.cmd.control &= ~ATA_A_RESET; 2314 ahci_begin_transaction(dev, ccb); 2315 return; 2316 } 2317 /* If it was our READ LOG command - process it. */ 2318 if (ccb->ccb_h.recovery_type == RECOVERY_READ_LOG) { 2319 ahci_process_read_log(dev, ccb); 2320 /* If it was our REQUEST SENSE command - process it. */ 2321 } else if (ccb->ccb_h.recovery_type == RECOVERY_REQUEST_SENSE) { 2322 ahci_process_request_sense(dev, ccb); 2323 /* If it was NCQ or ATAPI command error, put result on hold. */ 2324 } else if (et == AHCI_ERR_NCQ || 2325 ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR && 2326 (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0)) { 2327 ch->hold[slot->slot] = ccb; 2328 ch->numhslots++; 2329 } else 2330 ahci_done(ch, ccb); 2331 /* If we have no other active commands, ... */ 2332 if (ch->rslots == 0) { 2333 /* if there was fatal error - reset port. */ 2334 if (ch->toslots != 0 || ch->fatalerr) { 2335 ahci_reset(dev); 2336 } else { 2337 /* if we have slots in error, we can reinit port. */ 2338 if (ch->eslots != 0) { 2339 ahci_stop(dev); 2340 ahci_clo(dev); 2341 ahci_start(dev, 1); 2342 } 2343 /* if there commands on hold, we can do READ LOG. */ 2344 if (!ch->recoverycmd && ch->numhslots) 2345 ahci_issue_recovery(dev); 2346 } 2347 /* If all the rest of commands are in timeout - give them chance. */ 2348 } else if ((ch->rslots & ~ch->toslots) == 0 && 2349 et != AHCI_ERR_TIMEOUT) 2350 ahci_rearm_timeout(dev); 2351 /* Unfreeze frozen command. */ 2352 if (ch->frozen && !ahci_check_collision(dev, ch->frozen)) { 2353 union ccb *fccb = ch->frozen; 2354 ch->frozen = NULL; 2355 ahci_begin_transaction(dev, fccb); 2356 xpt_release_simq(ch->sim, TRUE); 2357 } 2358 /* Start PM timer. */ 2359 if (ch->numrslots == 0 && ch->pm_level > 3 && 2360 (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) { 2361 callout_schedule(&ch->pm_timer, 2362 (ch->pm_level == 4) ? hz / 1000 : hz / 8); 2363 } 2364} 2365 2366static void 2367ahci_issue_recovery(device_t dev) 2368{ 2369 struct ahci_channel *ch = device_get_softc(dev); 2370 union ccb *ccb; 2371 struct ccb_ataio *ataio; 2372 struct ccb_scsiio *csio; 2373 int i; 2374 2375 /* Find some held command. */ 2376 for (i = 0; i < ch->numslots; i++) { 2377 if (ch->hold[i]) 2378 break; 2379 } 2380 ccb = xpt_alloc_ccb_nowait(); 2381 if (ccb == NULL) { 2382 device_printf(dev, "Unable to allocate recovery command\n"); 2383completeall: 2384 /* We can't do anything -- complete held commands. */ 2385 for (i = 0; i < ch->numslots; i++) { 2386 if (ch->hold[i] == NULL) 2387 continue; 2388 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2389 ch->hold[i]->ccb_h.status |= CAM_RESRC_UNAVAIL; 2390 ahci_done(ch, ch->hold[i]); 2391 ch->hold[i] = NULL; 2392 ch->numhslots--; 2393 } 2394 ahci_reset(dev); 2395 return; 2396 } 2397 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */ 2398 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 2399 /* READ LOG */ 2400 ccb->ccb_h.recovery_type = RECOVERY_READ_LOG; 2401 ccb->ccb_h.func_code = XPT_ATA_IO; 2402 ccb->ccb_h.flags = CAM_DIR_IN; 2403 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 2404 ataio = &ccb->ataio; 2405 ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT); 2406 if (ataio->data_ptr == NULL) { 2407 xpt_free_ccb(ccb); 2408 device_printf(dev, 2409 "Unable to allocate memory for READ LOG command\n"); 2410 goto completeall; 2411 } 2412 ataio->dxfer_len = 512; 2413 bzero(&ataio->cmd, sizeof(ataio->cmd)); 2414 ataio->cmd.flags = CAM_ATAIO_48BIT; 2415 ataio->cmd.command = 0x2F; /* READ LOG EXT */ 2416 ataio->cmd.sector_count = 1; 2417 ataio->cmd.sector_count_exp = 0; 2418 ataio->cmd.lba_low = 0x10; 2419 ataio->cmd.lba_mid = 0; 2420 ataio->cmd.lba_mid_exp = 0; 2421 } else { 2422 /* REQUEST SENSE */ 2423 ccb->ccb_h.recovery_type = RECOVERY_REQUEST_SENSE; 2424 ccb->ccb_h.recovery_slot = i; 2425 ccb->ccb_h.func_code = XPT_SCSI_IO; 2426 ccb->ccb_h.flags = CAM_DIR_IN; 2427 ccb->ccb_h.status = 0; 2428 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 2429 csio = &ccb->csio; 2430 csio->data_ptr = (void *)&ch->hold[i]->csio.sense_data; 2431 csio->dxfer_len = ch->hold[i]->csio.sense_len; 2432 csio->cdb_len = 6; 2433 bzero(&csio->cdb_io, sizeof(csio->cdb_io)); 2434 csio->cdb_io.cdb_bytes[0] = 0x03; 2435 csio->cdb_io.cdb_bytes[4] = csio->dxfer_len; 2436 } 2437 /* Freeze SIM while doing recovery. */ 2438 ch->recoverycmd = 1; 2439 xpt_freeze_simq(ch->sim, 1); 2440 ahci_begin_transaction(dev, ccb); 2441} 2442 2443static void 2444ahci_process_read_log(device_t dev, union ccb *ccb) 2445{ 2446 struct ahci_channel *ch = device_get_softc(dev); 2447 uint8_t *data; 2448 struct ata_res *res; 2449 int i; 2450 2451 ch->recoverycmd = 0; 2452 2453 data = ccb->ataio.data_ptr; 2454 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP && 2455 (data[0] & 0x80) == 0) { 2456 for (i = 0; i < ch->numslots; i++) { 2457 if (!ch->hold[i]) 2458 continue; 2459 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO) 2460 continue; 2461 if ((data[0] & 0x1F) == i) { 2462 res = &ch->hold[i]->ataio.res; 2463 res->status = data[2]; 2464 res->error = data[3]; 2465 res->lba_low = data[4]; 2466 res->lba_mid = data[5]; 2467 res->lba_high = data[6]; 2468 res->device = data[7]; 2469 res->lba_low_exp = data[8]; 2470 res->lba_mid_exp = data[9]; 2471 res->lba_high_exp = data[10]; 2472 res->sector_count = data[12]; 2473 res->sector_count_exp = data[13]; 2474 } else { 2475 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2476 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ; 2477 } 2478 ahci_done(ch, ch->hold[i]); 2479 ch->hold[i] = NULL; 2480 ch->numhslots--; 2481 } 2482 } else { 2483 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP) 2484 device_printf(dev, "Error while READ LOG EXT\n"); 2485 else if ((data[0] & 0x80) == 0) { 2486 device_printf(dev, "Non-queued command error in READ LOG EXT\n"); 2487 } 2488 for (i = 0; i < ch->numslots; i++) { 2489 if (!ch->hold[i]) 2490 continue; 2491 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO) 2492 continue; 2493 ahci_done(ch, ch->hold[i]); 2494 ch->hold[i] = NULL; 2495 ch->numhslots--; 2496 } 2497 } 2498 free(ccb->ataio.data_ptr, M_AHCI); 2499 xpt_free_ccb(ccb); 2500 xpt_release_simq(ch->sim, TRUE); 2501} 2502 2503static void 2504ahci_process_request_sense(device_t dev, union ccb *ccb) 2505{ 2506 struct ahci_channel *ch = device_get_softc(dev); 2507 int i; 2508 2509 ch->recoverycmd = 0; 2510 2511 i = ccb->ccb_h.recovery_slot; 2512 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP) { 2513 ch->hold[i]->ccb_h.status |= CAM_AUTOSNS_VALID; 2514 } else { 2515 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2516 ch->hold[i]->ccb_h.status |= CAM_AUTOSENSE_FAIL; 2517 } 2518 ahci_done(ch, ch->hold[i]); 2519 ch->hold[i] = NULL; 2520 ch->numhslots--; 2521 xpt_free_ccb(ccb); 2522 xpt_release_simq(ch->sim, TRUE); 2523} 2524 2525static void 2526ahci_start(device_t dev, int fbs) 2527{ 2528 struct ahci_channel *ch = device_get_softc(dev); 2529 u_int32_t cmd; 2530 2531 /* Clear SATA error register */ 2532 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xFFFFFFFF); 2533 /* Clear any interrupts pending on this channel */ 2534 ATA_OUTL(ch->r_mem, AHCI_P_IS, 0xFFFFFFFF); 2535 /* Configure FIS-based switching if supported. */ 2536 if (ch->chcaps & AHCI_P_CMD_FBSCP) { 2537 ch->fbs_enabled = (fbs && ch->pm_present) ? 1 : 0; 2538 ATA_OUTL(ch->r_mem, AHCI_P_FBS, 2539 ch->fbs_enabled ? AHCI_P_FBS_EN : 0); 2540 } 2541 /* Start operations on this channel */ 2542 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2543 cmd &= ~AHCI_P_CMD_PMA; 2544 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_ST | 2545 (ch->pm_present ? AHCI_P_CMD_PMA : 0)); 2546} 2547 2548static void 2549ahci_stop(device_t dev) 2550{ 2551 struct ahci_channel *ch = device_get_softc(dev); 2552 u_int32_t cmd; 2553 int timeout; 2554 2555 /* Kill all activity on this channel */ 2556 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2557 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_ST); 2558 /* Wait for activity stop. */ 2559 timeout = 0; 2560 do { 2561 DELAY(10); 2562 if (timeout++ > 50000) { 2563 device_printf(dev, "stopping AHCI engine failed\n"); 2564 break; 2565 } 2566 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR); 2567 ch->eslots = 0; 2568} 2569 2570static void 2571ahci_clo(device_t dev) 2572{ 2573 struct ahci_channel *ch = device_get_softc(dev); 2574 u_int32_t cmd; 2575 int timeout; 2576 2577 /* Issue Command List Override if supported */ 2578 if (ch->caps & AHCI_CAP_SCLO) { 2579 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2580 cmd |= AHCI_P_CMD_CLO; 2581 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd); 2582 timeout = 0; 2583 do { 2584 DELAY(10); 2585 if (timeout++ > 50000) { 2586 device_printf(dev, "executing CLO failed\n"); 2587 break; 2588 } 2589 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO); 2590 } 2591} 2592 2593static void 2594ahci_stop_fr(device_t dev) 2595{ 2596 struct ahci_channel *ch = device_get_softc(dev); 2597 u_int32_t cmd; 2598 int timeout; 2599 2600 /* Kill all FIS reception on this channel */ 2601 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2602 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_FRE); 2603 /* Wait for FIS reception stop. */ 2604 timeout = 0; 2605 do { 2606 DELAY(10); 2607 if (timeout++ > 50000) { 2608 device_printf(dev, "stopping AHCI FR engine failed\n"); 2609 break; 2610 } 2611 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR); 2612} 2613 2614static void 2615ahci_start_fr(device_t dev) 2616{ 2617 struct ahci_channel *ch = device_get_softc(dev); 2618 u_int32_t cmd; 2619 2620 /* Start FIS reception on this channel */ 2621 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2622 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_FRE); 2623} 2624 2625static int 2626ahci_wait_ready(device_t dev, int t, int t0) 2627{ 2628 struct ahci_channel *ch = device_get_softc(dev); 2629 int timeout = 0; 2630 uint32_t val; 2631 2632 while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) & 2633 (ATA_S_BUSY | ATA_S_DRQ)) { 2634 if (timeout > t) { 2635 if (t != 0) { 2636 device_printf(dev, 2637 "AHCI reset: device not ready after %dms " 2638 "(tfd = %08x)\n", 2639 MAX(t, 0) + t0, val); 2640 } 2641 return (EBUSY); 2642 } 2643 DELAY(1000); 2644 timeout++; 2645 } 2646 if (bootverbose) 2647 device_printf(dev, "AHCI reset: device ready after %dms\n", 2648 timeout + t0); 2649 return (0); 2650} 2651 2652static void 2653ahci_reset_to(void *arg) 2654{ 2655 device_t dev = arg; 2656 struct ahci_channel *ch = device_get_softc(dev); 2657 2658 if (ch->resetting == 0) 2659 return; 2660 ch->resetting--; 2661 if (ahci_wait_ready(dev, ch->resetting == 0 ? -1 : 0, 2662 (310 - ch->resetting) * 100) == 0) { 2663 ch->resetting = 0; 2664 ahci_start(dev, 1); 2665 xpt_release_simq(ch->sim, TRUE); 2666 return; 2667 } 2668 if (ch->resetting == 0) { 2669 ahci_clo(dev); 2670 ahci_start(dev, 1); 2671 xpt_release_simq(ch->sim, TRUE); 2672 return; 2673 } 2674 callout_schedule(&ch->reset_timer, hz / 10); 2675} 2676 2677static void 2678ahci_reset(device_t dev) 2679{ 2680 struct ahci_channel *ch = device_get_softc(dev); 2681 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2682 int i; 2683 2684 xpt_freeze_simq(ch->sim, 1); 2685 if (bootverbose) 2686 device_printf(dev, "AHCI reset...\n"); 2687 /* Forget about previous reset. */ 2688 if (ch->resetting) { 2689 ch->resetting = 0; 2690 callout_stop(&ch->reset_timer); 2691 xpt_release_simq(ch->sim, TRUE); 2692 } 2693 /* Requeue freezed command. */ 2694 if (ch->frozen) { 2695 union ccb *fccb = ch->frozen; 2696 ch->frozen = NULL; 2697 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 2698 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 2699 xpt_freeze_devq(fccb->ccb_h.path, 1); 2700 fccb->ccb_h.status |= CAM_DEV_QFRZN; 2701 } 2702 ahci_done(ch, fccb); 2703 } 2704 /* Kill the engine and requeue all running commands. */ 2705 ahci_stop(dev); 2706 for (i = 0; i < ch->numslots; i++) { 2707 /* Do we have a running request on slot? */ 2708 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 2709 continue; 2710 /* XXX; Commands in loading state. */ 2711 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 2712 } 2713 for (i = 0; i < ch->numslots; i++) { 2714 if (!ch->hold[i]) 2715 continue; 2716 ahci_done(ch, ch->hold[i]); 2717 ch->hold[i] = NULL; 2718 ch->numhslots--; 2719 } 2720 if (ch->toslots != 0) 2721 xpt_release_simq(ch->sim, TRUE); 2722 ch->eslots = 0; 2723 ch->toslots = 0; 2724 ch->wrongccs = 0; 2725 ch->fatalerr = 0; 2726 /* Tell the XPT about the event */ 2727 xpt_async(AC_BUS_RESET, ch->path, NULL); 2728 /* Disable port interrupts */ 2729 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 2730 /* Reset and reconnect PHY, */ 2731 if (!ahci_sata_phy_reset(dev)) { 2732 if (bootverbose) 2733 device_printf(dev, 2734 "AHCI reset: device not found\n"); 2735 ch->devices = 0; 2736 /* Enable wanted port interrupts */ 2737 ATA_OUTL(ch->r_mem, AHCI_P_IE, 2738 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) | 2739 AHCI_P_IX_PRC | AHCI_P_IX_PC)); 2740 xpt_release_simq(ch->sim, TRUE); 2741 return; 2742 } 2743 if (bootverbose) 2744 device_printf(dev, "AHCI reset: device found\n"); 2745 /* Wait for clearing busy status. */ 2746 if (ahci_wait_ready(dev, dumping ? 31000 : 0, 0)) { 2747 if (dumping) 2748 ahci_clo(dev); 2749 else 2750 ch->resetting = 310; 2751 } 2752 ch->devices = 1; 2753 /* Enable wanted port interrupts */ 2754 ATA_OUTL(ch->r_mem, AHCI_P_IE, 2755 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) | 2756 AHCI_P_IX_TFE | AHCI_P_IX_HBF | 2757 AHCI_P_IX_HBD | AHCI_P_IX_IF | AHCI_P_IX_OF | 2758 ((ch->pm_level == 0) ? AHCI_P_IX_PRC : 0) | AHCI_P_IX_PC | 2759 AHCI_P_IX_DP | AHCI_P_IX_UF | (ctlr->ccc ? 0 : AHCI_P_IX_SDB) | 2760 AHCI_P_IX_DS | AHCI_P_IX_PS | (ctlr->ccc ? 0 : AHCI_P_IX_DHR))); 2761 if (ch->resetting) 2762 callout_reset(&ch->reset_timer, hz / 10, ahci_reset_to, dev); 2763 else { 2764 ahci_start(dev, 1); 2765 xpt_release_simq(ch->sim, TRUE); 2766 } 2767} 2768 2769static int 2770ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag) 2771{ 2772 struct ahci_channel *ch = device_get_softc(dev); 2773 u_int8_t *fis = &ctp->cfis[0]; 2774 2775 bzero(ctp->cfis, 16); 2776 fis[0] = 0x27; /* host to device */ 2777 fis[1] = (ccb->ccb_h.target_id & 0x0f); 2778 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 2779 fis[1] |= 0x80; 2780 fis[2] = ATA_PACKET_CMD; 2781 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2782 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA) 2783 fis[3] = ATA_F_DMA; 2784 else { 2785 fis[5] = ccb->csio.dxfer_len; 2786 fis[6] = ccb->csio.dxfer_len >> 8; 2787 } 2788 fis[7] = ATA_D_LBA; 2789 fis[15] = ATA_A_4BIT; 2790 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 2791 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes, 2792 ctp->acmd, ccb->csio.cdb_len); 2793 bzero(ctp->acmd + ccb->csio.cdb_len, 32 - ccb->csio.cdb_len); 2794 } else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) { 2795 fis[1] |= 0x80; 2796 fis[2] = ccb->ataio.cmd.command; 2797 fis[3] = ccb->ataio.cmd.features; 2798 fis[4] = ccb->ataio.cmd.lba_low; 2799 fis[5] = ccb->ataio.cmd.lba_mid; 2800 fis[6] = ccb->ataio.cmd.lba_high; 2801 fis[7] = ccb->ataio.cmd.device; 2802 fis[8] = ccb->ataio.cmd.lba_low_exp; 2803 fis[9] = ccb->ataio.cmd.lba_mid_exp; 2804 fis[10] = ccb->ataio.cmd.lba_high_exp; 2805 fis[11] = ccb->ataio.cmd.features_exp; 2806 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 2807 fis[12] = tag << 3; 2808 fis[13] = 0; 2809 } else { 2810 fis[12] = ccb->ataio.cmd.sector_count; 2811 fis[13] = ccb->ataio.cmd.sector_count_exp; 2812 } 2813 fis[15] = ATA_A_4BIT; 2814 } else { 2815 fis[15] = ccb->ataio.cmd.control; 2816 } 2817 return (20); 2818} 2819 2820static int 2821ahci_sata_connect(struct ahci_channel *ch) 2822{ 2823 u_int32_t status; 2824 int timeout, found = 0; 2825 2826 /* Wait up to 100ms for "connect well" */ 2827 for (timeout = 0; timeout < 1000 ; timeout++) { 2828 status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 2829 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE) 2830 found = 1; 2831 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && 2832 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && 2833 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) 2834 break; 2835 if ((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_OFFLINE) { 2836 if (bootverbose) { 2837 device_printf(ch->dev, "SATA offline status=%08x\n", 2838 status); 2839 } 2840 return (0); 2841 } 2842 if (found == 0 && timeout >= 100) 2843 break; 2844 DELAY(100); 2845 } 2846 if (timeout >= 1000 || !found) { 2847 if (bootverbose) { 2848 device_printf(ch->dev, 2849 "SATA connect timeout time=%dus status=%08x\n", 2850 timeout * 100, status); 2851 } 2852 return (0); 2853 } 2854 if (bootverbose) { 2855 device_printf(ch->dev, "SATA connect time=%dus status=%08x\n", 2856 timeout * 100, status); 2857 } 2858 /* Clear SATA error register */ 2859 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff); 2860 return (1); 2861} 2862 2863static int 2864ahci_sata_phy_reset(device_t dev) 2865{ 2866 struct ahci_channel *ch = device_get_softc(dev); 2867 int sata_rev; 2868 uint32_t val; 2869 2870 if (ch->listening) { 2871 val = ATA_INL(ch->r_mem, AHCI_P_CMD); 2872 val |= AHCI_P_CMD_SUD; 2873 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val); 2874 ch->listening = 0; 2875 } 2876 sata_rev = ch->user[ch->pm_present ? 15 : 0].revision; 2877 if (sata_rev == 1) 2878 val = ATA_SC_SPD_SPEED_GEN1; 2879 else if (sata_rev == 2) 2880 val = ATA_SC_SPD_SPEED_GEN2; 2881 else if (sata_rev == 3) 2882 val = ATA_SC_SPD_SPEED_GEN3; 2883 else 2884 val = 0; 2885 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2886 ATA_SC_DET_RESET | val | 2887 ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER); 2888 DELAY(1000); 2889 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2890 ATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 : 2891 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER))); 2892 if (!ahci_sata_connect(ch)) { 2893 if (ch->caps & AHCI_CAP_SSS) { 2894 val = ATA_INL(ch->r_mem, AHCI_P_CMD); 2895 val &= ~AHCI_P_CMD_SUD; 2896 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val); 2897 ch->listening = 1; 2898 } else if (ch->pm_level > 0) 2899 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 2900 return (0); 2901 } 2902 return (1); 2903} 2904 2905static int 2906ahci_check_ids(device_t dev, union ccb *ccb) 2907{ 2908 struct ahci_channel *ch = device_get_softc(dev); 2909 2910 if (ccb->ccb_h.target_id > ((ch->caps & AHCI_CAP_SPM) ? 15 : 0)) { 2911 ccb->ccb_h.status = CAM_TID_INVALID; 2912 ahci_done(ch, ccb); 2913 return (-1); 2914 } 2915 if (ccb->ccb_h.target_lun != 0) { 2916 ccb->ccb_h.status = CAM_LUN_INVALID; 2917 ahci_done(ch, ccb); 2918 return (-1); 2919 } 2920 return (0); 2921} 2922 2923static void 2924ahciaction(struct cam_sim *sim, union ccb *ccb) 2925{ 2926 device_t dev, parent; 2927 struct ahci_channel *ch; 2928 2929 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n", 2930 ccb->ccb_h.func_code)); 2931 2932 ch = (struct ahci_channel *)cam_sim_softc(sim); 2933 dev = ch->dev; 2934 switch (ccb->ccb_h.func_code) { 2935 /* Common cases first */ 2936 case XPT_ATA_IO: /* Execute the requested I/O operation */ 2937 case XPT_SCSI_IO: 2938 if (ahci_check_ids(dev, ccb)) 2939 return; 2940 if (ch->devices == 0 || 2941 (ch->pm_present == 0 && 2942 ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) { 2943 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2944 break; 2945 } 2946 ccb->ccb_h.recovery_type = RECOVERY_NONE; 2947 /* Check for command collision. */ 2948 if (ahci_check_collision(dev, ccb)) { 2949 /* Freeze command. */ 2950 ch->frozen = ccb; 2951 /* We have only one frozen slot, so freeze simq also. */ 2952 xpt_freeze_simq(ch->sim, 1); 2953 return; 2954 } 2955 ahci_begin_transaction(dev, ccb); 2956 return; 2957 case XPT_EN_LUN: /* Enable LUN as a target */ 2958 case XPT_TARGET_IO: /* Execute target I/O request */ 2959 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 2960 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/ 2961 case XPT_ABORT: /* Abort the specified CCB */ 2962 /* XXX Implement */ 2963 ccb->ccb_h.status = CAM_REQ_INVALID; 2964 break; 2965 case XPT_SET_TRAN_SETTINGS: 2966 { 2967 struct ccb_trans_settings *cts = &ccb->cts; 2968 struct ahci_device *d; 2969 2970 if (ahci_check_ids(dev, ccb)) 2971 return; 2972 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2973 d = &ch->curr[ccb->ccb_h.target_id]; 2974 else 2975 d = &ch->user[ccb->ccb_h.target_id]; 2976 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION) 2977 d->revision = cts->xport_specific.sata.revision; 2978 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE) 2979 d->mode = cts->xport_specific.sata.mode; 2980 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT) 2981 d->bytecount = min(8192, cts->xport_specific.sata.bytecount); 2982 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS) 2983 d->tags = min(ch->numslots, cts->xport_specific.sata.tags); 2984 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM) 2985 ch->pm_present = cts->xport_specific.sata.pm_present; 2986 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI) 2987 d->atapi = cts->xport_specific.sata.atapi; 2988 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS) 2989 d->caps = cts->xport_specific.sata.caps; 2990 ccb->ccb_h.status = CAM_REQ_CMP; 2991 break; 2992 } 2993 case XPT_GET_TRAN_SETTINGS: 2994 /* Get default/user set transfer settings for the target */ 2995 { 2996 struct ccb_trans_settings *cts = &ccb->cts; 2997 struct ahci_device *d; 2998 uint32_t status; 2999 3000 if (ahci_check_ids(dev, ccb)) 3001 return; 3002 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 3003 d = &ch->curr[ccb->ccb_h.target_id]; 3004 else 3005 d = &ch->user[ccb->ccb_h.target_id]; 3006 cts->protocol = PROTO_UNSPECIFIED; 3007 cts->protocol_version = PROTO_VERSION_UNSPECIFIED; 3008 cts->transport = XPORT_SATA; 3009 cts->transport_version = XPORT_VERSION_UNSPECIFIED; 3010 cts->proto_specific.valid = 0; 3011 cts->xport_specific.sata.valid = 0; 3012 if (cts->type == CTS_TYPE_CURRENT_SETTINGS && 3013 (ccb->ccb_h.target_id == 15 || 3014 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) { 3015 status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK; 3016 if (status & 0x0f0) { 3017 cts->xport_specific.sata.revision = 3018 (status & 0x0f0) >> 4; 3019 cts->xport_specific.sata.valid |= 3020 CTS_SATA_VALID_REVISION; 3021 } 3022 cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D; 3023 if (ch->pm_level) { 3024 if (ch->caps & (AHCI_CAP_PSC | AHCI_CAP_SSC)) 3025 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ; 3026 if (ch->caps2 & AHCI_CAP2_APST) 3027 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_APST; 3028 } 3029 if ((ch->caps & AHCI_CAP_SNCQ) && 3030 (ch->quirks & AHCI_Q_NOAA) == 0) 3031 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_DMAAA; 3032 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_AN; 3033 cts->xport_specific.sata.caps &= 3034 ch->user[ccb->ccb_h.target_id].caps; 3035 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 3036 } else { 3037 cts->xport_specific.sata.revision = d->revision; 3038 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION; 3039 cts->xport_specific.sata.caps = d->caps; 3040 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 3041 } 3042 cts->xport_specific.sata.mode = d->mode; 3043 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE; 3044 cts->xport_specific.sata.bytecount = d->bytecount; 3045 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT; 3046 cts->xport_specific.sata.pm_present = ch->pm_present; 3047 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM; 3048 cts->xport_specific.sata.tags = d->tags; 3049 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS; 3050 cts->xport_specific.sata.atapi = d->atapi; 3051 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI; 3052 ccb->ccb_h.status = CAM_REQ_CMP; 3053 break; 3054 } 3055 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 3056 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 3057 ahci_reset(dev); 3058 ccb->ccb_h.status = CAM_REQ_CMP; 3059 break; 3060 case XPT_TERM_IO: /* Terminate the I/O process */ 3061 /* XXX Implement */ 3062 ccb->ccb_h.status = CAM_REQ_INVALID; 3063 break; 3064 case XPT_PATH_INQ: /* Path routing inquiry */ 3065 { 3066 struct ccb_pathinq *cpi = &ccb->cpi; 3067 3068 parent = device_get_parent(dev); 3069 cpi->version_num = 1; /* XXX??? */ 3070 cpi->hba_inquiry = PI_SDTR_ABLE; 3071 if (ch->caps & AHCI_CAP_SNCQ) 3072 cpi->hba_inquiry |= PI_TAG_ABLE; 3073 if (ch->caps & AHCI_CAP_SPM) 3074 cpi->hba_inquiry |= PI_SATAPM; 3075 cpi->target_sprt = 0; 3076 cpi->hba_misc = PIM_SEQSCAN | PIM_UNMAPPED; 3077 cpi->hba_eng_cnt = 0; 3078 if (ch->caps & AHCI_CAP_SPM) 3079 cpi->max_target = 15; 3080 else 3081 cpi->max_target = 0; 3082 cpi->max_lun = 0; 3083 cpi->initiator_id = 0; 3084 cpi->bus_id = cam_sim_bus(sim); 3085 cpi->base_transfer_speed = 150000; 3086 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 3087 strncpy(cpi->hba_vid, "AHCI", HBA_IDLEN); 3088 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 3089 cpi->unit_number = cam_sim_unit(sim); 3090 cpi->transport = XPORT_SATA; 3091 cpi->transport_version = XPORT_VERSION_UNSPECIFIED; 3092 cpi->protocol = PROTO_ATA; 3093 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED; 3094 cpi->maxio = MAXPHYS; 3095 /* ATI SB600 can't handle 256 sectors with FPDMA (NCQ). */ 3096 if (pci_get_devid(parent) == 0x43801002) 3097 cpi->maxio = min(cpi->maxio, 128 * 512); 3098 cpi->hba_vendor = pci_get_vendor(parent); 3099 cpi->hba_device = pci_get_device(parent); 3100 cpi->hba_subvendor = pci_get_subvendor(parent); 3101 cpi->hba_subdevice = pci_get_subdevice(parent); 3102 cpi->ccb_h.status = CAM_REQ_CMP; 3103 break; 3104 } 3105 default: 3106 ccb->ccb_h.status = CAM_REQ_INVALID; 3107 break; 3108 } 3109 ahci_done(ch, ccb); 3110} 3111 3112static void 3113ahcipoll(struct cam_sim *sim) 3114{ 3115 struct ahci_channel *ch = (struct ahci_channel *)cam_sim_softc(sim); 3116 uint32_t istatus; 3117 3118 /* Read interrupt statuses and process if any. */ 3119 istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 3120 if (istatus != 0) 3121 ahci_ch_intr_main(ch, istatus); 3122 if (ch->resetting != 0 && 3123 (--ch->resetpolldiv <= 0 || !callout_pending(&ch->reset_timer))) { 3124 ch->resetpolldiv = 1000; 3125 ahci_reset_to(ch->dev); 3126 } 3127} 3128