1/***********************license start*************** 2 * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Inc. nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-rnm-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon rnm. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision$<hr> 50 * 51 */ 52#ifndef __CVMX_RNM_DEFS_H__ 53#define __CVMX_RNM_DEFS_H__ 54 55#define CVMX_RNM_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001180040000008ull)) 56#define CVMX_RNM_CTL_STATUS (CVMX_ADD_IO_SEG(0x0001180040000000ull)) 57#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 58#define CVMX_RNM_EER_DBG CVMX_RNM_EER_DBG_FUNC() 59static inline uint64_t CVMX_RNM_EER_DBG_FUNC(void) 60{ 61 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 62 cvmx_warn("CVMX_RNM_EER_DBG not supported on this chip\n"); 63 return CVMX_ADD_IO_SEG(0x0001180040000018ull); 64} 65#else 66#define CVMX_RNM_EER_DBG (CVMX_ADD_IO_SEG(0x0001180040000018ull)) 67#endif 68#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 69#define CVMX_RNM_EER_KEY CVMX_RNM_EER_KEY_FUNC() 70static inline uint64_t CVMX_RNM_EER_KEY_FUNC(void) 71{ 72 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 73 cvmx_warn("CVMX_RNM_EER_KEY not supported on this chip\n"); 74 return CVMX_ADD_IO_SEG(0x0001180040000010ull); 75} 76#else 77#define CVMX_RNM_EER_KEY (CVMX_ADD_IO_SEG(0x0001180040000010ull)) 78#endif 79#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 80#define CVMX_RNM_SERIAL_NUM CVMX_RNM_SERIAL_NUM_FUNC() 81static inline uint64_t CVMX_RNM_SERIAL_NUM_FUNC(void) 82{ 83 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 84 cvmx_warn("CVMX_RNM_SERIAL_NUM not supported on this chip\n"); 85 return CVMX_ADD_IO_SEG(0x0001180040000020ull); 86} 87#else 88#define CVMX_RNM_SERIAL_NUM (CVMX_ADD_IO_SEG(0x0001180040000020ull)) 89#endif 90 91/** 92 * cvmx_rnm_bist_status 93 * 94 * RNM_BIST_STATUS = RNM's BIST Status Register 95 * 96 * The RNM's Memory Bist Status register. 97 */ 98union cvmx_rnm_bist_status { 99 uint64_t u64; 100 struct cvmx_rnm_bist_status_s { 101#ifdef __BIG_ENDIAN_BITFIELD 102 uint64_t reserved_2_63 : 62; 103 uint64_t rrc : 1; /**< Status of RRC block bist. */ 104 uint64_t mem : 1; /**< Status of MEM block bist. */ 105#else 106 uint64_t mem : 1; 107 uint64_t rrc : 1; 108 uint64_t reserved_2_63 : 62; 109#endif 110 } s; 111 struct cvmx_rnm_bist_status_s cn30xx; 112 struct cvmx_rnm_bist_status_s cn31xx; 113 struct cvmx_rnm_bist_status_s cn38xx; 114 struct cvmx_rnm_bist_status_s cn38xxp2; 115 struct cvmx_rnm_bist_status_s cn50xx; 116 struct cvmx_rnm_bist_status_s cn52xx; 117 struct cvmx_rnm_bist_status_s cn52xxp1; 118 struct cvmx_rnm_bist_status_s cn56xx; 119 struct cvmx_rnm_bist_status_s cn56xxp1; 120 struct cvmx_rnm_bist_status_s cn58xx; 121 struct cvmx_rnm_bist_status_s cn58xxp1; 122 struct cvmx_rnm_bist_status_s cn61xx; 123 struct cvmx_rnm_bist_status_s cn63xx; 124 struct cvmx_rnm_bist_status_s cn63xxp1; 125 struct cvmx_rnm_bist_status_s cn66xx; 126 struct cvmx_rnm_bist_status_s cn68xx; 127 struct cvmx_rnm_bist_status_s cn68xxp1; 128 struct cvmx_rnm_bist_status_s cnf71xx; 129}; 130typedef union cvmx_rnm_bist_status cvmx_rnm_bist_status_t; 131 132/** 133 * cvmx_rnm_ctl_status 134 * 135 * RNM_CTL_STATUS = RNM's Control/Status Register 136 * 137 * The RNM's interrupt enable register. 138 */ 139union cvmx_rnm_ctl_status { 140 uint64_t u64; 141 struct cvmx_rnm_ctl_status_s { 142#ifdef __BIG_ENDIAN_BITFIELD 143 uint64_t reserved_12_63 : 52; 144 uint64_t dis_mak : 1; /**< Disable use of Master AES KEY */ 145 uint64_t eer_lck : 1; /**< Encryption enable register locked */ 146 uint64_t eer_val : 1; /**< Dormant encryption key match */ 147 uint64_t ent_sel : 4; /**< ? */ 148 uint64_t exp_ent : 1; /**< Exported entropy enable for random number generator */ 149 uint64_t rng_rst : 1; /**< Reset RNG as core reset. */ 150 uint64_t rnm_rst : 1; /**< Reset the RNM as core reset except for register 151 logic. */ 152 uint64_t rng_en : 1; /**< Enable the output of the RNG. */ 153 uint64_t ent_en : 1; /**< Entropy enable for random number generator. */ 154#else 155 uint64_t ent_en : 1; 156 uint64_t rng_en : 1; 157 uint64_t rnm_rst : 1; 158 uint64_t rng_rst : 1; 159 uint64_t exp_ent : 1; 160 uint64_t ent_sel : 4; 161 uint64_t eer_val : 1; 162 uint64_t eer_lck : 1; 163 uint64_t dis_mak : 1; 164 uint64_t reserved_12_63 : 52; 165#endif 166 } s; 167 struct cvmx_rnm_ctl_status_cn30xx { 168#ifdef __BIG_ENDIAN_BITFIELD 169 uint64_t reserved_4_63 : 60; 170 uint64_t rng_rst : 1; /**< Reset RNG as core reset. */ 171 uint64_t rnm_rst : 1; /**< Reset the RNM as core reset except for register 172 logic. */ 173 uint64_t rng_en : 1; /**< Enable the output of the RNG. */ 174 uint64_t ent_en : 1; /**< Entropy enable for random number generator. */ 175#else 176 uint64_t ent_en : 1; 177 uint64_t rng_en : 1; 178 uint64_t rnm_rst : 1; 179 uint64_t rng_rst : 1; 180 uint64_t reserved_4_63 : 60; 181#endif 182 } cn30xx; 183 struct cvmx_rnm_ctl_status_cn30xx cn31xx; 184 struct cvmx_rnm_ctl_status_cn30xx cn38xx; 185 struct cvmx_rnm_ctl_status_cn30xx cn38xxp2; 186 struct cvmx_rnm_ctl_status_cn50xx { 187#ifdef __BIG_ENDIAN_BITFIELD 188 uint64_t reserved_9_63 : 55; 189 uint64_t ent_sel : 4; /**< ? */ 190 uint64_t exp_ent : 1; /**< Exported entropy enable for random number generator */ 191 uint64_t rng_rst : 1; /**< Reset RNG as core reset. */ 192 uint64_t rnm_rst : 1; /**< Reset the RNM as core reset except for register 193 logic. */ 194 uint64_t rng_en : 1; /**< Enable the output of the RNG. */ 195 uint64_t ent_en : 1; /**< Entropy enable for random number generator. */ 196#else 197 uint64_t ent_en : 1; 198 uint64_t rng_en : 1; 199 uint64_t rnm_rst : 1; 200 uint64_t rng_rst : 1; 201 uint64_t exp_ent : 1; 202 uint64_t ent_sel : 4; 203 uint64_t reserved_9_63 : 55; 204#endif 205 } cn50xx; 206 struct cvmx_rnm_ctl_status_cn50xx cn52xx; 207 struct cvmx_rnm_ctl_status_cn50xx cn52xxp1; 208 struct cvmx_rnm_ctl_status_cn50xx cn56xx; 209 struct cvmx_rnm_ctl_status_cn50xx cn56xxp1; 210 struct cvmx_rnm_ctl_status_cn50xx cn58xx; 211 struct cvmx_rnm_ctl_status_cn50xx cn58xxp1; 212 struct cvmx_rnm_ctl_status_s cn61xx; 213 struct cvmx_rnm_ctl_status_cn63xx { 214#ifdef __BIG_ENDIAN_BITFIELD 215 uint64_t reserved_11_63 : 53; 216 uint64_t eer_lck : 1; /**< Encryption enable register locked */ 217 uint64_t eer_val : 1; /**< Dormant encryption key match */ 218 uint64_t ent_sel : 4; /**< ? */ 219 uint64_t exp_ent : 1; /**< Exported entropy enable for random number generator */ 220 uint64_t rng_rst : 1; /**< Reset RNG as core reset. */ 221 uint64_t rnm_rst : 1; /**< Reset the RNM as core reset except for register 222 logic. */ 223 uint64_t rng_en : 1; /**< Enable the output of the RNG. */ 224 uint64_t ent_en : 1; /**< Entropy enable for random number generator. */ 225#else 226 uint64_t ent_en : 1; 227 uint64_t rng_en : 1; 228 uint64_t rnm_rst : 1; 229 uint64_t rng_rst : 1; 230 uint64_t exp_ent : 1; 231 uint64_t ent_sel : 4; 232 uint64_t eer_val : 1; 233 uint64_t eer_lck : 1; 234 uint64_t reserved_11_63 : 53; 235#endif 236 } cn63xx; 237 struct cvmx_rnm_ctl_status_cn63xx cn63xxp1; 238 struct cvmx_rnm_ctl_status_s cn66xx; 239 struct cvmx_rnm_ctl_status_cn63xx cn68xx; 240 struct cvmx_rnm_ctl_status_cn63xx cn68xxp1; 241 struct cvmx_rnm_ctl_status_s cnf71xx; 242}; 243typedef union cvmx_rnm_ctl_status cvmx_rnm_ctl_status_t; 244 245/** 246 * cvmx_rnm_eer_dbg 247 * 248 * RNM_EER_DBG = RNM's Encryption enable debug register 249 * 250 * The RNM's Encryption enable debug register 251 */ 252union cvmx_rnm_eer_dbg { 253 uint64_t u64; 254 struct cvmx_rnm_eer_dbg_s { 255#ifdef __BIG_ENDIAN_BITFIELD 256 uint64_t dat : 64; /**< Dormant encryption debug info. */ 257#else 258 uint64_t dat : 64; 259#endif 260 } s; 261 struct cvmx_rnm_eer_dbg_s cn61xx; 262 struct cvmx_rnm_eer_dbg_s cn63xx; 263 struct cvmx_rnm_eer_dbg_s cn63xxp1; 264 struct cvmx_rnm_eer_dbg_s cn66xx; 265 struct cvmx_rnm_eer_dbg_s cn68xx; 266 struct cvmx_rnm_eer_dbg_s cn68xxp1; 267 struct cvmx_rnm_eer_dbg_s cnf71xx; 268}; 269typedef union cvmx_rnm_eer_dbg cvmx_rnm_eer_dbg_t; 270 271/** 272 * cvmx_rnm_eer_key 273 * 274 * RNM_EER_KEY = RNM's Encryption enable register 275 * 276 * The RNM's Encryption enable register 277 */ 278union cvmx_rnm_eer_key { 279 uint64_t u64; 280 struct cvmx_rnm_eer_key_s { 281#ifdef __BIG_ENDIAN_BITFIELD 282 uint64_t key : 64; /**< Dormant encryption key. If dormant crypto is fuse 283 enabled, crypto can be enable by writing this 284 register with the correct key. */ 285#else 286 uint64_t key : 64; 287#endif 288 } s; 289 struct cvmx_rnm_eer_key_s cn61xx; 290 struct cvmx_rnm_eer_key_s cn63xx; 291 struct cvmx_rnm_eer_key_s cn63xxp1; 292 struct cvmx_rnm_eer_key_s cn66xx; 293 struct cvmx_rnm_eer_key_s cn68xx; 294 struct cvmx_rnm_eer_key_s cn68xxp1; 295 struct cvmx_rnm_eer_key_s cnf71xx; 296}; 297typedef union cvmx_rnm_eer_key cvmx_rnm_eer_key_t; 298 299/** 300 * cvmx_rnm_serial_num 301 * 302 * RNM_SERIAL_NUM = RNM's fuse serial number register 303 * 304 * The RNM's fuse serial number register 305 * 306 * Notes: 307 * Added RNM_SERIAL_NUM in pass 2.0 308 * 309 */ 310union cvmx_rnm_serial_num { 311 uint64_t u64; 312 struct cvmx_rnm_serial_num_s { 313#ifdef __BIG_ENDIAN_BITFIELD 314 uint64_t dat : 64; /**< Dormant encryption serial number */ 315#else 316 uint64_t dat : 64; 317#endif 318 } s; 319 struct cvmx_rnm_serial_num_s cn61xx; 320 struct cvmx_rnm_serial_num_s cn63xx; 321 struct cvmx_rnm_serial_num_s cn66xx; 322 struct cvmx_rnm_serial_num_s cn68xx; 323 struct cvmx_rnm_serial_num_s cn68xxp1; 324 struct cvmx_rnm_serial_num_s cnf71xx; 325}; 326typedef union cvmx_rnm_serial_num cvmx_rnm_serial_num_t; 327 328#endif 329