elf_trampoline.c revision 239268
1/*- 2 * Copyright (c) 2005 Olivier Houchard. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 */ 24 25/* 26 * Since we are compiled outside of the normal kernel build process, we 27 * need to include opt_global.h manually. 28 */ 29#include "opt_global.h" 30#include "opt_kernname.h" 31 32#include <sys/cdefs.h> 33__FBSDID("$FreeBSD: head/sys/arm/arm/elf_trampoline.c 239268 2012-08-15 03:03:03Z gonzo $"); 34#include <machine/asm.h> 35#include <sys/param.h> 36#include <sys/elf32.h> 37#include <sys/inflate.h> 38#include <machine/elf.h> 39#include <machine/pte.h> 40#include <machine/cpufunc.h> 41#include <machine/armreg.h> 42 43extern char kernel_start[]; 44extern char kernel_end[]; 45 46extern void *_end; 47 48void _start(void); 49void __start(void); 50void __startC(void); 51 52#define GZ_HEAD 0xa 53 54#ifdef CPU_ARM7TDMI 55#define cpu_idcache_wbinv_all arm7tdmi_cache_flushID 56#elif defined(CPU_ARM8) 57#define cpu_idcache_wbinv_all arm8_cache_purgeID 58#elif defined(CPU_ARM9) 59#define cpu_idcache_wbinv_all arm9_idcache_wbinv_all 60#elif defined(CPU_FA526) || defined(CPU_FA626TE) 61#define cpu_idcache_wbinv_all fa526_idcache_wbinv_all 62#elif defined(CPU_ARM9E) 63#define cpu_idcache_wbinv_all armv5_ec_idcache_wbinv_all 64#elif defined(CPU_ARM10) 65#define cpu_idcache_wbinv_all arm10_idcache_wbinv_all 66#elif defined(CPU_SA110) || defined(CPU_SA1110) || defined(CPU_SA1100) || \ 67 defined(CPU_IXP12X0) 68#define cpu_idcache_wbinv_all sa1_cache_purgeID 69#elif defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 70 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ 71 defined(CPU_XSCALE_80219) 72#define cpu_idcache_wbinv_all xscale_cache_purgeID 73#elif defined(CPU_XSCALE_81342) 74#define cpu_idcache_wbinv_all xscalec3_cache_purgeID 75#elif defined(CPU_MV_PJ4B) 76#if !defined(SOC_MV_ARMADAXP) 77#define cpu_idcache_wbinv_all armv6_idcache_wbinv_all 78#else 79#define cpu_idcache_wbinv_all() armadaxp_idcache_wbinv_all 80#endif 81#endif /* CPU_MV_PJ4B */ 82#ifdef CPU_XSCALE_81342 83#define cpu_l2cache_wbinv_all xscalec3_l2cache_purge 84#elif defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY) 85#define cpu_l2cache_wbinv_all sheeva_l2cache_wbinv_all 86#elif defined(CPU_CORTEXA) 87#define cpu_idcache_wbinv_all armv7_idcache_wbinv_all 88#define cpu_l2cache_wbinv_all() 89#else 90#define cpu_l2cache_wbinv_all() 91#endif 92 93static void armadaxp_idcache_wbinv_all(void); 94 95int arm_picache_size; 96int arm_picache_line_size; 97int arm_picache_ways; 98 99int arm_pdcache_size; /* and unified */ 100int arm_pdcache_line_size = 32; 101int arm_pdcache_ways; 102 103int arm_pcache_type; 104int arm_pcache_unified; 105 106int arm_dcache_align; 107int arm_dcache_align_mask; 108 109u_int arm_cache_level; 110u_int arm_cache_type[14]; 111u_int arm_cache_loc; 112 113/* Additional cache information local to this file. Log2 of some of the 114 above numbers. */ 115static int arm_dcache_l2_nsets; 116static int arm_dcache_l2_assoc; 117static int arm_dcache_l2_linesize; 118 119 120int block_userspace_access = 0; 121extern int arm9_dcache_sets_inc; 122extern int arm9_dcache_sets_max; 123extern int arm9_dcache_index_max; 124extern int arm9_dcache_index_inc; 125 126static __inline void * 127memcpy(void *dst, const void *src, int len) 128{ 129 const char *s = src; 130 char *d = dst; 131 132 while (len) { 133 if (0 && len >= 4 && !((vm_offset_t)d & 3) && 134 !((vm_offset_t)s & 3)) { 135 *(uint32_t *)d = *(uint32_t *)s; 136 s += 4; 137 d += 4; 138 len -= 4; 139 } else { 140 *d++ = *s++; 141 len--; 142 } 143 } 144 return (dst); 145} 146 147static __inline void 148bzero(void *addr, int count) 149{ 150 char *tmp = (char *)addr; 151 152 while (count > 0) { 153 if (count >= 4 && !((vm_offset_t)tmp & 3)) { 154 *(uint32_t *)tmp = 0; 155 tmp += 4; 156 count -= 4; 157 } else { 158 *tmp = 0; 159 tmp++; 160 count--; 161 } 162 } 163} 164 165static void arm9_setup(void); 166 167void 168_startC(void) 169{ 170 int physaddr = KERNPHYSADDR; 171 int tmp1; 172 unsigned int sp = ((unsigned int)&_end & ~3) + 4; 173#if defined(FLASHADDR) && defined(LOADERRAMADDR) 174 unsigned int pc; 175 176 __asm __volatile("mov %0, pc\n" 177 : "=r" (pc)); 178 if ((FLASHADDR > LOADERRAMADDR && pc >= FLASHADDR) || 179 (FLASHADDR < LOADERRAMADDR && pc < LOADERRAMADDR)) { 180 /* 181 * We're running from flash, so just copy the whole thing 182 * from flash to memory. 183 * This is far from optimal, we could do the relocation or 184 * the unzipping directly from flash to memory to avoid this 185 * needless copy, but it would require to know the flash 186 * physical address. 187 */ 188 unsigned int target_addr; 189 unsigned int tmp_sp; 190 uint32_t src_addr = (uint32_t)&_start - PHYSADDR + FLASHADDR 191 + (pc - FLASHADDR - ((uint32_t)&_startC - PHYSADDR)) & 0xfffff000; 192 193 target_addr = (unsigned int)&_start - PHYSADDR + LOADERRAMADDR; 194 tmp_sp = target_addr + 0x100000 + 195 (unsigned int)&_end - (unsigned int)&_start; 196 memcpy((char *)target_addr, (char *)src_addr, 197 (unsigned int)&_end - (unsigned int)&_start); 198 /* Temporary set the sp and jump to the new location. */ 199 __asm __volatile( 200 "mov sp, %1\n" 201 "mov pc, %0\n" 202 : : "r" (target_addr), "r" (tmp_sp)); 203 204 } 205#endif 206#ifdef KZIP 207 sp += KERNSIZE + 0x100; 208 sp &= ~(L1_TABLE_SIZE - 1); 209 sp += 2 * L1_TABLE_SIZE; 210#endif 211 sp += 1024 * 1024; /* Should be enough for a stack */ 212 213 __asm __volatile("adr %0, 2f\n" 214 "bic %0, %0, #0xff000000\n" 215 "and %1, %1, #0xff000000\n" 216 "orr %0, %0, %1\n" 217 "mrc p15, 0, %1, c1, c0, 0\n" 218 "bic %1, %1, #1\n" /* Disable MMU */ 219 "orr %1, %1, #(4 | 8)\n" /* Add DC enable, 220 WBUF enable */ 221 "orr %1, %1, #0x1000\n" /* Add IC enable */ 222 "orr %1, %1, #(0x800)\n" /* BPRD enable */ 223 224 "mcr p15, 0, %1, c1, c0, 0\n" 225 "nop\n" 226 "nop\n" 227 "nop\n" 228 "mov pc, %0\n" 229 "2: nop\n" 230 "mov sp, %2\n" 231 : "=r" (tmp1), "+r" (physaddr), "+r" (sp)); 232#ifndef KZIP 233#ifdef CPU_ARM9 234 /* So that idcache_wbinv works; */ 235 if ((cpufunc_id() & 0x0000f000) == 0x00009000) 236 arm9_setup(); 237#endif 238#endif 239 __start(); 240} 241 242static void 243get_cachetype_cp15() 244{ 245 u_int ctype, isize, dsize, cpuid; 246 u_int clevel, csize, i, sel; 247 u_int multiplier; 248 u_char type; 249 250 __asm __volatile("mrc p15, 0, %0, c0, c0, 1" 251 : "=r" (ctype)); 252 253 cpuid = cpufunc_id(); 254 /* 255 * ...and thus spake the ARM ARM: 256 * 257 * If an <opcode2> value corresponding to an unimplemented or 258 * reserved ID register is encountered, the System Control 259 * processor returns the value of the main ID register. 260 */ 261 if (ctype == cpuid) 262 goto out; 263 264 if (CPU_CT_FORMAT(ctype) == CPU_CT_ARMV7) { 265 __asm __volatile("mrc p15, 1, %0, c0, c0, 1" 266 : "=r" (clevel)); 267 arm_cache_level = clevel; 268 arm_cache_loc = CPU_CLIDR_LOC(arm_cache_level) + 1; 269 i = 0; 270 while ((type = (clevel & 0x7)) && i < 7) { 271 if (type == CACHE_DCACHE || type == CACHE_UNI_CACHE || 272 type == CACHE_SEP_CACHE) { 273 sel = i << 1; 274 __asm __volatile("mcr p15, 2, %0, c0, c0, 0" 275 : : "r" (sel)); 276 __asm __volatile("mrc p15, 1, %0, c0, c0, 0" 277 : "=r" (csize)); 278 arm_cache_type[sel] = csize; 279 } 280 if (type == CACHE_ICACHE || type == CACHE_SEP_CACHE) { 281 sel = (i << 1) | 1; 282 __asm __volatile("mcr p15, 2, %0, c0, c0, 0" 283 : : "r" (sel)); 284 __asm __volatile("mrc p15, 1, %0, c0, c0, 0" 285 : "=r" (csize)); 286 arm_cache_type[sel] = csize; 287 } 288 i++; 289 clevel >>= 3; 290 } 291 } else { 292 if ((ctype & CPU_CT_S) == 0) 293 arm_pcache_unified = 1; 294 295 /* 296 * If you want to know how this code works, go read the ARM ARM. 297 */ 298 299 arm_pcache_type = CPU_CT_CTYPE(ctype); 300 301 if (arm_pcache_unified == 0) { 302 isize = CPU_CT_ISIZE(ctype); 303 multiplier = (isize & CPU_CT_xSIZE_M) ? 3 : 2; 304 arm_picache_line_size = 1U << (CPU_CT_xSIZE_LEN(isize) + 3); 305 if (CPU_CT_xSIZE_ASSOC(isize) == 0) { 306 if (isize & CPU_CT_xSIZE_M) 307 arm_picache_line_size = 0; /* not present */ 308 else 309 arm_picache_ways = 1; 310 } else { 311 arm_picache_ways = multiplier << 312 (CPU_CT_xSIZE_ASSOC(isize) - 1); 313 } 314 arm_picache_size = multiplier << (CPU_CT_xSIZE_SIZE(isize) + 8); 315 } 316 317 dsize = CPU_CT_DSIZE(ctype); 318 multiplier = (dsize & CPU_CT_xSIZE_M) ? 3 : 2; 319 arm_pdcache_line_size = 1U << (CPU_CT_xSIZE_LEN(dsize) + 3); 320 if (CPU_CT_xSIZE_ASSOC(dsize) == 0) { 321 if (dsize & CPU_CT_xSIZE_M) 322 arm_pdcache_line_size = 0; /* not present */ 323 else 324 arm_pdcache_ways = 1; 325 } else { 326 arm_pdcache_ways = multiplier << 327 (CPU_CT_xSIZE_ASSOC(dsize) - 1); 328 } 329 arm_pdcache_size = multiplier << (CPU_CT_xSIZE_SIZE(dsize) + 8); 330 331 arm_dcache_align = arm_pdcache_line_size; 332 333 arm_dcache_l2_assoc = CPU_CT_xSIZE_ASSOC(dsize) + multiplier - 2; 334 arm_dcache_l2_linesize = CPU_CT_xSIZE_LEN(dsize) + 3; 335 arm_dcache_l2_nsets = 6 + CPU_CT_xSIZE_SIZE(dsize) - 336 CPU_CT_xSIZE_ASSOC(dsize) - CPU_CT_xSIZE_LEN(dsize); 337 338 out: 339 arm_dcache_align_mask = arm_dcache_align - 1; 340 } 341} 342 343static void 344arm9_setup(void) 345{ 346 347 get_cachetype_cp15(); 348 arm9_dcache_sets_inc = 1U << arm_dcache_l2_linesize; 349 arm9_dcache_sets_max = (1U << (arm_dcache_l2_linesize + 350 arm_dcache_l2_nsets)) - arm9_dcache_sets_inc; 351 arm9_dcache_index_inc = 1U << (32 - arm_dcache_l2_assoc); 352 arm9_dcache_index_max = 0U - arm9_dcache_index_inc; 353} 354 355static void 356armadaxp_idcache_wbinv_all(void) 357{ 358 uint32_t feat; 359 360 __asm __volatile("mrc p15, 0, %0, c0, c1, 0" : "=r" (feat)); 361 if (feat & ARM_PFR0_THUMBEE_MASK) 362 armv7_idcache_wbinv_all(); 363 else 364 armv6_idcache_wbinv_all(); 365 366} 367#ifdef KZIP 368static unsigned char *orig_input, *i_input, *i_output; 369 370 371static u_int memcnt; /* Memory allocated: blocks */ 372static size_t memtot; /* Memory allocated: bytes */ 373/* 374 * Library functions required by inflate(). 375 */ 376 377#define MEMSIZ 0x8000 378 379/* 380 * Allocate memory block. 381 */ 382unsigned char * 383kzipmalloc(int size) 384{ 385 void *ptr; 386 static u_char mem[MEMSIZ]; 387 388 if (memtot + size > MEMSIZ) 389 return NULL; 390 ptr = mem + memtot; 391 memtot += size; 392 memcnt++; 393 return ptr; 394} 395 396/* 397 * Free allocated memory block. 398 */ 399void 400kzipfree(void *ptr) 401{ 402 memcnt--; 403 if (!memcnt) 404 memtot = 0; 405} 406 407void 408putstr(char *dummy) 409{ 410} 411 412static int 413input(void *dummy) 414{ 415 if ((size_t)(i_input - orig_input) >= KERNCOMPSIZE) { 416 return (GZ_EOF); 417 } 418 return *i_input++; 419} 420 421static int 422output(void *dummy, unsigned char *ptr, unsigned long len) 423{ 424 425 426 memcpy(i_output, ptr, len); 427 i_output += len; 428 return (0); 429} 430 431static void * 432inflate_kernel(void *kernel, void *startaddr) 433{ 434 struct inflate infl; 435 char slide[GZ_WSIZE]; 436 437 orig_input = kernel; 438 memcnt = memtot = 0; 439 i_input = (char *)kernel + GZ_HEAD; 440 if (((char *)kernel)[3] & 0x18) { 441 while (*i_input) 442 i_input++; 443 i_input++; 444 } 445 i_output = startaddr; 446 bzero(&infl, sizeof(infl)); 447 infl.gz_input = input; 448 infl.gz_output = output; 449 infl.gz_slide = slide; 450 inflate(&infl); 451 return ((char *)(((vm_offset_t)i_output & ~3) + 4)); 452} 453 454#endif 455 456void * 457load_kernel(unsigned int kstart, unsigned int curaddr,unsigned int func_end, 458 int d) 459{ 460 Elf32_Ehdr *eh; 461 Elf32_Phdr phdr[64] /* XXX */, *php; 462 Elf32_Shdr shdr[64] /* XXX */; 463 int i,j; 464 void *entry_point; 465 int symtabindex = -1; 466 int symstrindex = -1; 467 vm_offset_t lastaddr = 0; 468 Elf_Addr ssym = 0; 469 Elf_Dyn *dp; 470 471 eh = (Elf32_Ehdr *)kstart; 472 ssym = 0; 473 entry_point = (void*)eh->e_entry; 474 memcpy(phdr, (void *)(kstart + eh->e_phoff ), 475 eh->e_phnum * sizeof(phdr[0])); 476 477 /* Determine lastaddr. */ 478 for (i = 0; i < eh->e_phnum; i++) { 479 if (lastaddr < (phdr[i].p_vaddr - KERNVIRTADDR + curaddr 480 + phdr[i].p_memsz)) 481 lastaddr = phdr[i].p_vaddr - KERNVIRTADDR + 482 curaddr + phdr[i].p_memsz; 483 } 484 485 /* Save the symbol tables, as there're about to be scratched. */ 486 memcpy(shdr, (void *)(kstart + eh->e_shoff), 487 sizeof(*shdr) * eh->e_shnum); 488 if (eh->e_shnum * eh->e_shentsize != 0 && 489 eh->e_shoff != 0) { 490 for (i = 0; i < eh->e_shnum; i++) { 491 if (shdr[i].sh_type == SHT_SYMTAB) { 492 for (j = 0; j < eh->e_phnum; j++) { 493 if (phdr[j].p_type == PT_LOAD && 494 shdr[i].sh_offset >= 495 phdr[j].p_offset && 496 (shdr[i].sh_offset + 497 shdr[i].sh_size <= 498 phdr[j].p_offset + 499 phdr[j].p_filesz)) { 500 shdr[i].sh_offset = 0; 501 shdr[i].sh_size = 0; 502 j = eh->e_phnum; 503 } 504 } 505 if (shdr[i].sh_offset != 0 && 506 shdr[i].sh_size != 0) { 507 symtabindex = i; 508 symstrindex = shdr[i].sh_link; 509 } 510 } 511 } 512 func_end = roundup(func_end, sizeof(long)); 513 if (symtabindex >= 0 && symstrindex >= 0) { 514 ssym = lastaddr; 515 if (d) { 516 memcpy((void *)func_end, (void *)( 517 shdr[symtabindex].sh_offset + kstart), 518 shdr[symtabindex].sh_size); 519 memcpy((void *)(func_end + 520 shdr[symtabindex].sh_size), 521 (void *)(shdr[symstrindex].sh_offset + 522 kstart), shdr[symstrindex].sh_size); 523 } else { 524 lastaddr += shdr[symtabindex].sh_size; 525 lastaddr = roundup(lastaddr, 526 sizeof(shdr[symtabindex].sh_size)); 527 lastaddr += sizeof(shdr[symstrindex].sh_size); 528 lastaddr += shdr[symstrindex].sh_size; 529 lastaddr = roundup(lastaddr, 530 sizeof(shdr[symstrindex].sh_size)); 531 } 532 533 } 534 } 535 if (!d) 536 return ((void *)lastaddr); 537 538 j = eh->e_phnum; 539 for (i = 0; i < j; i++) { 540 volatile char c; 541 542 if (phdr[i].p_type != PT_LOAD) 543 continue; 544 memcpy((void *)(phdr[i].p_vaddr - KERNVIRTADDR + curaddr), 545 (void*)(kstart + phdr[i].p_offset), phdr[i].p_filesz); 546 /* Clean space from oversized segments, eg: bss. */ 547 if (phdr[i].p_filesz < phdr[i].p_memsz) 548 bzero((void *)(phdr[i].p_vaddr - KERNVIRTADDR + 549 curaddr + phdr[i].p_filesz), phdr[i].p_memsz - 550 phdr[i].p_filesz); 551 } 552 /* Now grab the symbol tables. */ 553 if (symtabindex >= 0 && symstrindex >= 0) { 554 *(Elf_Size *)lastaddr = 555 shdr[symtabindex].sh_size; 556 lastaddr += sizeof(shdr[symtabindex].sh_size); 557 memcpy((void*)lastaddr, 558 (void *)func_end, 559 shdr[symtabindex].sh_size); 560 lastaddr += shdr[symtabindex].sh_size; 561 lastaddr = roundup(lastaddr, 562 sizeof(shdr[symtabindex].sh_size)); 563 *(Elf_Size *)lastaddr = 564 shdr[symstrindex].sh_size; 565 lastaddr += sizeof(shdr[symstrindex].sh_size); 566 memcpy((void*)lastaddr, 567 (void*)(func_end + 568 shdr[symtabindex].sh_size), 569 shdr[symstrindex].sh_size); 570 lastaddr += shdr[symstrindex].sh_size; 571 lastaddr = roundup(lastaddr, 572 sizeof(shdr[symstrindex].sh_size)); 573 *(Elf_Addr *)curaddr = MAGIC_TRAMP_NUMBER; 574 *((Elf_Addr *)curaddr + 1) = ssym - curaddr + KERNVIRTADDR; 575 *((Elf_Addr *)curaddr + 2) = lastaddr - curaddr + KERNVIRTADDR; 576 } else 577 *(Elf_Addr *)curaddr = 0; 578 /* Invalidate the instruction cache. */ 579 __asm __volatile("mcr p15, 0, %0, c7, c5, 0\n" 580 "mcr p15, 0, %0, c7, c10, 4\n" 581 : : "r" (curaddr)); 582 __asm __volatile("mrc p15, 0, %0, c1, c0, 0\n" 583 "bic %0, %0, #1\n" /* MMU_ENABLE */ 584 "mcr p15, 0, %0, c1, c0, 0\n" 585 : "=r" (ssym)); 586 /* Jump to the entry point. */ 587 ((void(*)(void))(entry_point - KERNVIRTADDR + curaddr))(); 588 __asm __volatile(".globl func_end\n" 589 "func_end:"); 590 591} 592 593extern char func_end[]; 594 595 596#define PMAP_DOMAIN_KERNEL 0 /* 597 * Just define it instead of including the 598 * whole VM headers set. 599 */ 600int __hack; 601static __inline void 602setup_pagetables(unsigned int pt_addr, vm_paddr_t physstart, vm_paddr_t physend, 603 int write_back) 604{ 605 unsigned int *pd = (unsigned int *)pt_addr; 606 vm_paddr_t addr; 607 int domain = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | DOMAIN_CLIENT; 608 int tmp; 609 610 bzero(pd, L1_TABLE_SIZE); 611 for (addr = physstart; addr < physend; addr += L1_S_SIZE) { 612 pd[addr >> L1_S_SHIFT] = L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW)| 613 L1_S_DOM(PMAP_DOMAIN_KERNEL) | addr; 614 if (write_back && 0) 615 pd[addr >> L1_S_SHIFT] |= L1_S_B; 616 } 617 /* XXX: See below */ 618 if (0xfff00000 < physstart || 0xfff00000 > physend) 619 pd[0xfff00000 >> L1_S_SHIFT] = L1_TYPE_S|L1_S_AP(AP_KRW)| 620 L1_S_DOM(PMAP_DOMAIN_KERNEL)|physstart; 621 __asm __volatile("mcr p15, 0, %1, c2, c0, 0\n" /* set TTB */ 622 "mcr p15, 0, %1, c8, c7, 0\n" /* Flush TTB */ 623 "mcr p15, 0, %2, c3, c0, 0\n" /* Set DAR */ 624 "mrc p15, 0, %0, c1, c0, 0\n" 625 "orr %0, %0, #1\n" /* MMU_ENABLE */ 626 "mcr p15, 0, %0, c1, c0, 0\n" 627 "mrc p15, 0, %0, c2, c0, 0\n" /* CPWAIT */ 628 "mov r0, r0\n" 629 "sub pc, pc, #4\n" : 630 "=r" (tmp) : "r" (pd), "r" (domain)); 631 632 /* 633 * XXX: This is the most stupid workaround I've ever wrote. 634 * For some reason, the KB9202 won't boot the kernel unless 635 * we access an address which is not in the 636 * 0x20000000 - 0x20ffffff range. I hope I'll understand 637 * what's going on later. 638 */ 639 __hack = *(volatile int *)0xfffff21c; 640} 641 642void 643__start(void) 644{ 645 void *curaddr; 646 void *dst, *altdst; 647 char *kernel = (char *)&kernel_start; 648 int sp; 649 int pt_addr; 650 651 __asm __volatile("mov %0, pc" : 652 "=r" (curaddr)); 653 curaddr = (void*)((unsigned int)curaddr & 0xfff00000); 654#ifdef KZIP 655 if (*kernel == 0x1f && kernel[1] == 0x8b) { 656 pt_addr = (((int)&_end + KERNSIZE + 0x100) & 657 ~(L1_TABLE_SIZE - 1)) + L1_TABLE_SIZE; 658 659#ifdef CPU_ARM9 660 /* So that idcache_wbinv works; */ 661 if ((cpufunc_id() & 0x0000f000) == 0x00009000) 662 arm9_setup(); 663#endif 664 setup_pagetables(pt_addr, (vm_paddr_t)curaddr, 665 (vm_paddr_t)curaddr + 0x10000000, 1); 666 /* Gzipped kernel */ 667 dst = inflate_kernel(kernel, &_end); 668 kernel = (char *)&_end; 669 altdst = 4 + load_kernel((unsigned int)kernel, 670 (unsigned int)curaddr, 671 (unsigned int)&func_end + 800 , 0); 672 if (altdst > dst) 673 dst = altdst; 674 675 /* 676 * Disable MMU. Otherwise, setup_pagetables call below 677 * might overwrite the L1 table we are currently using. 678 */ 679 cpu_idcache_wbinv_all(); 680 cpu_l2cache_wbinv_all(); 681 __asm __volatile("mrc p15, 0, %0, c1, c0, 0\n" 682 "bic %0, %0, #1\n" /* MMU_DISABLE */ 683 "mcr p15, 0, %0, c1, c0, 0\n" 684 :"=r" (pt_addr)); 685 } else 686#endif 687 dst = 4 + load_kernel((unsigned int)&kernel_start, 688 (unsigned int)curaddr, 689 (unsigned int)&func_end, 0); 690 dst = (void *)(((vm_offset_t)dst & ~3)); 691 pt_addr = ((unsigned int)dst &~(L1_TABLE_SIZE - 1)) + L1_TABLE_SIZE; 692 setup_pagetables(pt_addr, (vm_paddr_t)curaddr, 693 (vm_paddr_t)curaddr + 0x10000000, 0); 694 sp = pt_addr + L1_TABLE_SIZE + 8192; 695 sp = sp &~3; 696 dst = (void *)(sp + 4); 697 memcpy((void *)dst, (void *)&load_kernel, (unsigned int)&func_end - 698 (unsigned int)&load_kernel + 800); 699 do_call(dst, kernel, dst + (unsigned int)(&func_end) - 700 (unsigned int)(&load_kernel) + 800, sp); 701} 702