elf_trampoline.c revision 201468
1/*- 2 * Copyright (c) 2005 Olivier Houchard. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 */ 24 25#include <sys/cdefs.h> 26__FBSDID("$FreeBSD: head/sys/arm/arm/elf_trampoline.c 201468 2010-01-04 03:35:45Z rpaulo $"); 27#include <machine/asm.h> 28#include <sys/param.h> 29#include <sys/elf32.h> 30#include <sys/inflate.h> 31#include <machine/elf.h> 32#include <machine/pte.h> 33#include <machine/cpufunc.h> 34#include <machine/armreg.h> 35 36/* 37 * Since we are compiled outside of the normal kernel build process, we 38 * need to include opt_global.h manually. 39 */ 40#include "opt_global.h" 41#include "opt_kernname.h" 42 43extern char kernel_start[]; 44extern char kernel_end[]; 45 46extern void *_end; 47 48void _start(void); 49void __start(void); 50void __startC(void); 51 52#define GZ_HEAD 0xa 53 54#ifdef CPU_ARM7TDMI 55#define cpu_idcache_wbinv_all arm7tdmi_cache_flushID 56#elif defined(CPU_ARM8) 57#define cpu_idcache_wbinv_all arm8_cache_purgeID 58#elif defined(CPU_ARM9) 59#define cpu_idcache_wbinv_all arm9_idcache_wbinv_all 60#elif defined(CPU_FA526) 61#define cpu_idcache_wbinv_all fa526_idcache_wbinv_all 62#elif defined(CPU_ARM9E) 63#define cpu_idcache_wbinv_all armv5_ec_idcache_wbinv_all 64#elif defined(CPU_ARM10) 65#define cpu_idcache_wbinv_all arm10_idcache_wbinv_all 66#elif defined(CPU_SA110) || defined(CPU_SA1110) || defined(CPU_SA1100) || \ 67 defined(CPU_IXP12X0) 68#define cpu_idcache_wbinv_all sa1_cache_purgeID 69#elif defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 70 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ 71 defined(CPU_XSCALE_80219) 72#define cpu_idcache_wbinv_all xscale_cache_purgeID 73#elif defined(CPU_XSCALE_81342) 74#define cpu_idcache_wbinv_all xscalec3_cache_purgeID 75#endif 76#ifdef CPU_XSCALE_81342 77#define cpu_l2cache_wbinv_all xscalec3_l2cache_purge 78#elif defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY) 79#define cpu_l2cache_wbinv_all sheeva_l2cache_wbinv_all 80#else 81#define cpu_l2cache_wbinv_all() 82#endif 83 84 85int arm_picache_size; 86int arm_picache_line_size; 87int arm_picache_ways; 88 89int arm_pdcache_size; /* and unified */ 90int arm_pdcache_line_size = 32; 91int arm_pdcache_ways; 92 93int arm_pcache_type; 94int arm_pcache_unified; 95 96int arm_dcache_align; 97int arm_dcache_align_mask; 98 99/* Additional cache information local to this file. Log2 of some of the 100 above numbers. */ 101static int arm_dcache_l2_nsets; 102static int arm_dcache_l2_assoc; 103static int arm_dcache_l2_linesize; 104 105 106int block_userspace_access = 0; 107extern int arm9_dcache_sets_inc; 108extern int arm9_dcache_sets_max; 109extern int arm9_dcache_index_max; 110extern int arm9_dcache_index_inc; 111 112static __inline void * 113memcpy(void *dst, const void *src, int len) 114{ 115 const char *s = src; 116 char *d = dst; 117 118 while (len) { 119 if (0 && len >= 4 && !((vm_offset_t)d & 3) && 120 !((vm_offset_t)s & 3)) { 121 *(uint32_t *)d = *(uint32_t *)s; 122 s += 4; 123 d += 4; 124 len -= 4; 125 } else { 126 *d++ = *s++; 127 len--; 128 } 129 } 130 return (dst); 131} 132 133static __inline void 134bzero(void *addr, int count) 135{ 136 char *tmp = (char *)addr; 137 138 while (count > 0) { 139 if (count >= 4 && !((vm_offset_t)tmp & 3)) { 140 *(uint32_t *)tmp = 0; 141 tmp += 4; 142 count -= 4; 143 } else { 144 *tmp = 0; 145 tmp++; 146 count--; 147 } 148 } 149} 150 151static void arm9_setup(void); 152 153void 154_startC(void) 155{ 156 int physaddr = KERNPHYSADDR; 157 int tmp1; 158 unsigned int sp = ((unsigned int)&_end & ~3) + 4; 159#if defined(FLASHADDR) && defined(LOADERRAMADDR) 160 unsigned int pc; 161 162 __asm __volatile("adr %0, _start\n" 163 : "=r" (pc)); 164 if ((FLASHADDR > LOADERRAMADDR && pc >= FLASHADDR) || 165 (FLASHADDR < LOADERRAMADDR && pc < LOADERRAMADDR)) { 166 /* 167 * We're running from flash, so just copy the whole thing 168 * from flash to memory. 169 * This is far from optimal, we could do the relocation or 170 * the unzipping directly from flash to memory to avoid this 171 * needless copy, but it would require to know the flash 172 * physical address. 173 */ 174 unsigned int target_addr; 175 unsigned int tmp_sp; 176 177 target_addr = (unsigned int)&_start - PHYSADDR + LOADERRAMADDR; 178 tmp_sp = target_addr + 0x100000 + 179 (unsigned int)&_end - (unsigned int)&_start; 180 memcpy((char *)target_addr, (char *)pc, 181 (unsigned int)&_end - (unsigned int)&_start); 182 /* Temporary set the sp and jump to the new location. */ 183 __asm __volatile( 184 "mov sp, %1\n" 185 "mov pc, %0\n" 186 : : "r" (target_addr), "r" (tmp_sp)); 187 188 } 189#endif 190#ifdef KZIP 191 sp += KERNSIZE + 0x100; 192 sp &= ~(L1_TABLE_SIZE - 1); 193 sp += 2 * L1_TABLE_SIZE; 194#endif 195 sp += 1024 * 1024; /* Should be enough for a stack */ 196 197 __asm __volatile("adr %0, 2f\n" 198 "bic %0, %0, #0xff000000\n" 199 "and %1, %1, #0xff000000\n" 200 "orr %0, %0, %1\n" 201 "mrc p15, 0, %1, c1, c0, 0\n" 202 "bic %1, %1, #1\n" /* Disable MMU */ 203 "orr %1, %1, #(4 | 8)\n" /* Add DC enable, 204 WBUF enable */ 205 "orr %1, %1, #0x1000\n" /* Add IC enable */ 206 "orr %1, %1, #(0x800)\n" /* BPRD enable */ 207 208 "mcr p15, 0, %1, c1, c0, 0\n" 209 "nop\n" 210 "nop\n" 211 "nop\n" 212 "mov pc, %0\n" 213 "2: nop\n" 214 "mov sp, %2\n" 215 : "=r" (tmp1), "+r" (physaddr), "+r" (sp)); 216#ifndef KZIP 217#ifdef CPU_ARM9 218 /* So that idcache_wbinv works; */ 219 if ((cpufunc_id() & 0x0000f000) == 0x00009000) 220 arm9_setup(); 221#endif 222 cpu_idcache_wbinv_all(); 223 cpu_l2cache_wbinv_all(); 224#endif 225 __start(); 226} 227 228static void 229get_cachetype_cp15() 230{ 231 u_int ctype, isize, dsize; 232 u_int multiplier; 233 234 __asm __volatile("mrc p15, 0, %0, c0, c0, 1" 235 : "=r" (ctype)); 236 237 /* 238 * ...and thus spake the ARM ARM: 239 * 240 * If an <opcode2> value corresponding to an unimplemented or 241 * reserved ID register is encountered, the System Control 242 * processor returns the value of the main ID register. 243 */ 244 if (ctype == cpufunc_id()) 245 goto out; 246 247 if ((ctype & CPU_CT_S) == 0) 248 arm_pcache_unified = 1; 249 250 /* 251 * If you want to know how this code works, go read the ARM ARM. 252 */ 253 254 arm_pcache_type = CPU_CT_CTYPE(ctype); 255 if (arm_pcache_unified == 0) { 256 isize = CPU_CT_ISIZE(ctype); 257 multiplier = (isize & CPU_CT_xSIZE_M) ? 3 : 2; 258 arm_picache_line_size = 1U << (CPU_CT_xSIZE_LEN(isize) + 3); 259 if (CPU_CT_xSIZE_ASSOC(isize) == 0) { 260 if (isize & CPU_CT_xSIZE_M) 261 arm_picache_line_size = 0; /* not present */ 262 else 263 arm_picache_ways = 1; 264 } else { 265 arm_picache_ways = multiplier << 266 (CPU_CT_xSIZE_ASSOC(isize) - 1); 267 } 268 arm_picache_size = multiplier << (CPU_CT_xSIZE_SIZE(isize) + 8); 269 } 270 271 dsize = CPU_CT_DSIZE(ctype); 272 multiplier = (dsize & CPU_CT_xSIZE_M) ? 3 : 2; 273 arm_pdcache_line_size = 1U << (CPU_CT_xSIZE_LEN(dsize) + 3); 274 if (CPU_CT_xSIZE_ASSOC(dsize) == 0) { 275 if (dsize & CPU_CT_xSIZE_M) 276 arm_pdcache_line_size = 0; /* not present */ 277 else 278 arm_pdcache_ways = 1; 279 } else { 280 arm_pdcache_ways = multiplier << 281 (CPU_CT_xSIZE_ASSOC(dsize) - 1); 282 } 283 arm_pdcache_size = multiplier << (CPU_CT_xSIZE_SIZE(dsize) + 8); 284 285 arm_dcache_align = arm_pdcache_line_size; 286 287 arm_dcache_l2_assoc = CPU_CT_xSIZE_ASSOC(dsize) + multiplier - 2; 288 arm_dcache_l2_linesize = CPU_CT_xSIZE_LEN(dsize) + 3; 289 arm_dcache_l2_nsets = 6 + CPU_CT_xSIZE_SIZE(dsize) - 290 CPU_CT_xSIZE_ASSOC(dsize) - CPU_CT_xSIZE_LEN(dsize); 291 out: 292 arm_dcache_align_mask = arm_dcache_align - 1; 293} 294 295static void 296arm9_setup(void) 297{ 298 299 get_cachetype_cp15(); 300 arm9_dcache_sets_inc = 1U << arm_dcache_l2_linesize; 301 arm9_dcache_sets_max = (1U << (arm_dcache_l2_linesize + 302 arm_dcache_l2_nsets)) - arm9_dcache_sets_inc; 303 arm9_dcache_index_inc = 1U << (32 - arm_dcache_l2_assoc); 304 arm9_dcache_index_max = 0U - arm9_dcache_index_inc; 305} 306 307 308#ifdef KZIP 309static unsigned char *orig_input, *i_input, *i_output; 310 311 312static u_int memcnt; /* Memory allocated: blocks */ 313static size_t memtot; /* Memory allocated: bytes */ 314/* 315 * Library functions required by inflate(). 316 */ 317 318#define MEMSIZ 0x8000 319 320/* 321 * Allocate memory block. 322 */ 323unsigned char * 324kzipmalloc(int size) 325{ 326 void *ptr; 327 static u_char mem[MEMSIZ]; 328 329 if (memtot + size > MEMSIZ) 330 return NULL; 331 ptr = mem + memtot; 332 memtot += size; 333 memcnt++; 334 return ptr; 335} 336 337/* 338 * Free allocated memory block. 339 */ 340void 341kzipfree(void *ptr) 342{ 343 memcnt--; 344 if (!memcnt) 345 memtot = 0; 346} 347 348void 349putstr(char *dummy) 350{ 351} 352 353static int 354input(void *dummy) 355{ 356 if ((size_t)(i_input - orig_input) >= KERNCOMPSIZE) { 357 return (GZ_EOF); 358 } 359 return *i_input++; 360} 361 362static int 363output(void *dummy, unsigned char *ptr, unsigned long len) 364{ 365 366 367 memcpy(i_output, ptr, len); 368 i_output += len; 369 return (0); 370} 371 372static void * 373inflate_kernel(void *kernel, void *startaddr) 374{ 375 struct inflate infl; 376 char slide[GZ_WSIZE]; 377 378 orig_input = kernel; 379 memcnt = memtot = 0; 380 i_input = (char *)kernel + GZ_HEAD; 381 if (((char *)kernel)[3] & 0x18) { 382 while (*i_input) 383 i_input++; 384 i_input++; 385 } 386 i_output = startaddr; 387 bzero(&infl, sizeof(infl)); 388 infl.gz_input = input; 389 infl.gz_output = output; 390 infl.gz_slide = slide; 391 inflate(&infl); 392 return ((char *)(((vm_offset_t)i_output & ~3) + 4)); 393} 394 395#endif 396 397void * 398load_kernel(unsigned int kstart, unsigned int curaddr,unsigned int func_end, 399 int d) 400{ 401 Elf32_Ehdr *eh; 402 Elf32_Phdr phdr[64] /* XXX */, *php; 403 Elf32_Shdr shdr[64] /* XXX */; 404 int i,j; 405 void *entry_point; 406 int symtabindex = -1; 407 int symstrindex = -1; 408 vm_offset_t lastaddr = 0; 409 Elf_Addr ssym = 0; 410 Elf_Dyn *dp; 411 412 eh = (Elf32_Ehdr *)kstart; 413 ssym = 0; 414 entry_point = (void*)eh->e_entry; 415 memcpy(phdr, (void *)(kstart + eh->e_phoff ), 416 eh->e_phnum * sizeof(phdr[0])); 417 418 /* Determine lastaddr. */ 419 for (i = 0; i < eh->e_phnum; i++) { 420 if (lastaddr < (phdr[i].p_vaddr - KERNVIRTADDR + curaddr 421 + phdr[i].p_memsz)) 422 lastaddr = phdr[i].p_vaddr - KERNVIRTADDR + 423 curaddr + phdr[i].p_memsz; 424 } 425 426 /* Save the symbol tables, as there're about to be scratched. */ 427 memcpy(shdr, (void *)(kstart + eh->e_shoff), 428 sizeof(*shdr) * eh->e_shnum); 429 if (eh->e_shnum * eh->e_shentsize != 0 && 430 eh->e_shoff != 0) { 431 for (i = 0; i < eh->e_shnum; i++) { 432 if (shdr[i].sh_type == SHT_SYMTAB) { 433 for (j = 0; j < eh->e_phnum; j++) { 434 if (phdr[j].p_type == PT_LOAD && 435 shdr[i].sh_offset >= 436 phdr[j].p_offset && 437 (shdr[i].sh_offset + 438 shdr[i].sh_size <= 439 phdr[j].p_offset + 440 phdr[j].p_filesz)) { 441 shdr[i].sh_offset = 0; 442 shdr[i].sh_size = 0; 443 j = eh->e_phnum; 444 } 445 } 446 if (shdr[i].sh_offset != 0 && 447 shdr[i].sh_size != 0) { 448 symtabindex = i; 449 symstrindex = shdr[i].sh_link; 450 } 451 } 452 } 453 func_end = roundup(func_end, sizeof(long)); 454 if (symtabindex >= 0 && symstrindex >= 0) { 455 ssym = lastaddr; 456 if (d) { 457 memcpy((void *)func_end, (void *)( 458 shdr[symtabindex].sh_offset + kstart), 459 shdr[symtabindex].sh_size); 460 memcpy((void *)(func_end + 461 shdr[symtabindex].sh_size), 462 (void *)(shdr[symstrindex].sh_offset + 463 kstart), shdr[symstrindex].sh_size); 464 } else { 465 lastaddr += shdr[symtabindex].sh_size; 466 lastaddr = roundup(lastaddr, 467 sizeof(shdr[symtabindex].sh_size)); 468 lastaddr += sizeof(shdr[symstrindex].sh_size); 469 lastaddr += shdr[symstrindex].sh_size; 470 lastaddr = roundup(lastaddr, 471 sizeof(shdr[symstrindex].sh_size)); 472 } 473 474 } 475 } 476 if (!d) 477 return ((void *)lastaddr); 478 479 j = eh->e_phnum; 480 for (i = 0; i < j; i++) { 481 volatile char c; 482 483 if (phdr[i].p_type != PT_LOAD) 484 continue; 485 memcpy((void *)(phdr[i].p_vaddr - KERNVIRTADDR + curaddr), 486 (void*)(kstart + phdr[i].p_offset), phdr[i].p_filesz); 487 /* Clean space from oversized segments, eg: bss. */ 488 if (phdr[i].p_filesz < phdr[i].p_memsz) 489 bzero((void *)(phdr[i].p_vaddr - KERNVIRTADDR + 490 curaddr + phdr[i].p_filesz), phdr[i].p_memsz - 491 phdr[i].p_filesz); 492 } 493 /* Now grab the symbol tables. */ 494 if (symtabindex >= 0 && symstrindex >= 0) { 495 *(Elf_Size *)lastaddr = 496 shdr[symtabindex].sh_size; 497 lastaddr += sizeof(shdr[symtabindex].sh_size); 498 memcpy((void*)lastaddr, 499 (void *)func_end, 500 shdr[symtabindex].sh_size); 501 lastaddr += shdr[symtabindex].sh_size; 502 lastaddr = roundup(lastaddr, 503 sizeof(shdr[symtabindex].sh_size)); 504 *(Elf_Size *)lastaddr = 505 shdr[symstrindex].sh_size; 506 lastaddr += sizeof(shdr[symstrindex].sh_size); 507 memcpy((void*)lastaddr, 508 (void*)(func_end + 509 shdr[symtabindex].sh_size), 510 shdr[symstrindex].sh_size); 511 lastaddr += shdr[symstrindex].sh_size; 512 lastaddr = roundup(lastaddr, 513 sizeof(shdr[symstrindex].sh_size)); 514 *(Elf_Addr *)curaddr = MAGIC_TRAMP_NUMBER; 515 *((Elf_Addr *)curaddr + 1) = ssym - curaddr + KERNVIRTADDR; 516 *((Elf_Addr *)curaddr + 2) = lastaddr - curaddr + KERNVIRTADDR; 517 } else 518 *(Elf_Addr *)curaddr = 0; 519 /* Invalidate the instruction cache. */ 520 __asm __volatile("mcr p15, 0, %0, c7, c5, 0\n" 521 "mcr p15, 0, %0, c7, c10, 4\n" 522 : : "r" (curaddr)); 523 __asm __volatile("mrc p15, 0, %0, c1, c0, 0\n" 524 "bic %0, %0, #1\n" /* MMU_ENABLE */ 525 "mcr p15, 0, %0, c1, c0, 0\n" 526 : "=r" (ssym)); 527 /* Jump to the entry point. */ 528 ((void(*)(void))(entry_point - KERNVIRTADDR + curaddr))(); 529 __asm __volatile(".globl func_end\n" 530 "func_end:"); 531 532} 533 534extern char func_end[]; 535 536 537#define PMAP_DOMAIN_KERNEL 0 /* 538 * Just define it instead of including the 539 * whole VM headers set. 540 */ 541int __hack; 542static __inline void 543setup_pagetables(unsigned int pt_addr, vm_paddr_t physstart, vm_paddr_t physend, 544 int write_back) 545{ 546 unsigned int *pd = (unsigned int *)pt_addr; 547 vm_paddr_t addr; 548 int domain = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | DOMAIN_CLIENT; 549 int tmp; 550 551 bzero(pd, L1_TABLE_SIZE); 552 for (addr = physstart; addr < physend; addr += L1_S_SIZE) { 553 pd[addr >> L1_S_SHIFT] = L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW)| 554 L1_S_DOM(PMAP_DOMAIN_KERNEL) | addr; 555 if (write_back && 0) 556 pd[addr >> L1_S_SHIFT] |= L1_S_B; 557 } 558 /* XXX: See below */ 559 if (0xfff00000 < physstart || 0xfff00000 > physend) 560 pd[0xfff00000 >> L1_S_SHIFT] = L1_TYPE_S|L1_S_AP(AP_KRW)| 561 L1_S_DOM(PMAP_DOMAIN_KERNEL)|physstart; 562 __asm __volatile("mcr p15, 0, %1, c2, c0, 0\n" /* set TTB */ 563 "mcr p15, 0, %1, c8, c7, 0\n" /* Flush TTB */ 564 "mcr p15, 0, %2, c3, c0, 0\n" /* Set DAR */ 565 "mrc p15, 0, %0, c1, c0, 0\n" 566 "orr %0, %0, #1\n" /* MMU_ENABLE */ 567 "mcr p15, 0, %0, c1, c0, 0\n" 568 "mrc p15, 0, %0, c2, c0, 0\n" /* CPWAIT */ 569 "mov r0, r0\n" 570 "sub pc, pc, #4\n" : 571 "=r" (tmp) : "r" (pd), "r" (domain)); 572 573 /* 574 * XXX: This is the most stupid workaround I've ever wrote. 575 * For some reason, the KB9202 won't boot the kernel unless 576 * we access an address which is not in the 577 * 0x20000000 - 0x20ffffff range. I hope I'll understand 578 * what's going on later. 579 */ 580 __hack = *(volatile int *)0xfffff21c; 581} 582 583void 584__start(void) 585{ 586 void *curaddr; 587 void *dst, *altdst; 588 char *kernel = (char *)&kernel_start; 589 int sp; 590 int pt_addr; 591 592 __asm __volatile("mov %0, pc" : 593 "=r" (curaddr)); 594 curaddr = (void*)((unsigned int)curaddr & 0xfff00000); 595#ifdef KZIP 596 if (*kernel == 0x1f && kernel[1] == 0x8b) { 597 pt_addr = (((int)&_end + KERNSIZE + 0x100) & 598 ~(L1_TABLE_SIZE - 1)) + L1_TABLE_SIZE; 599 600#ifdef CPU_ARM9 601 /* So that idcache_wbinv works; */ 602 if ((cpufunc_id() & 0x0000f000) == 0x00009000) 603 arm9_setup(); 604#endif 605 setup_pagetables(pt_addr, (vm_paddr_t)curaddr, 606 (vm_paddr_t)curaddr + 0x10000000, 1); 607 /* Gzipped kernel */ 608 dst = inflate_kernel(kernel, &_end); 609 kernel = (char *)&_end; 610 altdst = 4 + load_kernel((unsigned int)kernel, 611 (unsigned int)curaddr, 612 (unsigned int)&func_end + 800 , 0); 613 if (altdst > dst) 614 dst = altdst; 615 } else 616#endif 617 dst = 4 + load_kernel((unsigned int)&kernel_start, 618 (unsigned int)curaddr, 619 (unsigned int)&func_end, 0); 620 dst = (void *)(((vm_offset_t)dst & ~3)); 621 pt_addr = ((unsigned int)dst &~(L1_TABLE_SIZE - 1)) + L1_TABLE_SIZE; 622 setup_pagetables(pt_addr, (vm_paddr_t)curaddr, 623 (vm_paddr_t)curaddr + 0x10000000, 0); 624 sp = pt_addr + L1_TABLE_SIZE + 8192; 625 sp = sp &~3; 626 dst = (void *)(sp + 4); 627 memcpy((void *)dst, (void *)&load_kernel, (unsigned int)&func_end - 628 (unsigned int)&load_kernel + 800); 629 do_call(dst, kernel, dst + (unsigned int)(&func_end) - 630 (unsigned int)(&load_kernel) + 800, sp); 631} 632