1/*- 2 * Copyright (c) 2003 Peter Wemm. 3 * Copyright (c) 1993 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 4. Neither the name of the University nor the names of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD$ 31 */ 32 33/* 34 * Functions to provide access to special i386 instructions. 35 * This in included in sys/systm.h, and that file should be 36 * used in preference to this. 37 */ 38 39#ifndef _MACHINE_CPUFUNC_H_ 40#define _MACHINE_CPUFUNC_H_ 41 42#ifndef _SYS_CDEFS_H_ 43#error this file needs sys/cdefs.h as a prerequisite 44#endif 45 46struct region_descriptor; 47 48#define readb(va) (*(volatile uint8_t *) (va)) 49#define readw(va) (*(volatile uint16_t *) (va)) 50#define readl(va) (*(volatile uint32_t *) (va)) 51#define readq(va) (*(volatile uint64_t *) (va)) 52 53#define writeb(va, d) (*(volatile uint8_t *) (va) = (d)) 54#define writew(va, d) (*(volatile uint16_t *) (va) = (d)) 55#define writel(va, d) (*(volatile uint32_t *) (va) = (d)) 56#define writeq(va, d) (*(volatile uint64_t *) (va) = (d)) 57 58#if defined(__GNUCLIKE_ASM) && defined(__CC_SUPPORTS___INLINE) 59 60static __inline void 61breakpoint(void) 62{ 63 __asm __volatile("int $3"); 64} 65 66static __inline u_int 67bsfl(u_int mask) 68{ 69 u_int result; 70 71 __asm __volatile("bsfl %1,%0" : "=r" (result) : "rm" (mask)); 72 return (result); 73} 74 75static __inline u_long 76bsfq(u_long mask) 77{ 78 u_long result; 79 80 __asm __volatile("bsfq %1,%0" : "=r" (result) : "rm" (mask)); 81 return (result); 82} 83 84static __inline u_int 85bsrl(u_int mask) 86{ 87 u_int result; 88 89 __asm __volatile("bsrl %1,%0" : "=r" (result) : "rm" (mask)); 90 return (result); 91} 92 93static __inline u_long 94bsrq(u_long mask) 95{ 96 u_long result; 97 98 __asm __volatile("bsrq %1,%0" : "=r" (result) : "rm" (mask)); 99 return (result); 100} 101 102static __inline void 103clflush(u_long addr) 104{ 105 106 __asm __volatile("clflush %0" : : "m" (*(char *)addr)); 107} 108 109static __inline void 110clts(void) 111{ 112 113 __asm __volatile("clts"); 114} 115 116static __inline void 117disable_intr(void) 118{ 119 __asm __volatile("cli" : : : "memory"); 120} 121 122static __inline void 123do_cpuid(u_int ax, u_int *p) 124{ 125 __asm __volatile("cpuid" 126 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3]) 127 : "0" (ax)); 128} 129 130static __inline void 131cpuid_count(u_int ax, u_int cx, u_int *p) 132{ 133 __asm __volatile("cpuid" 134 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3]) 135 : "0" (ax), "c" (cx)); 136} 137 138static __inline void 139enable_intr(void) 140{ 141 __asm __volatile("sti"); 142} 143 144#ifdef _KERNEL 145 146#define HAVE_INLINE_FFS 147#define ffs(x) __builtin_ffs(x) 148 149#define HAVE_INLINE_FFSL 150 151static __inline int 152ffsl(long mask) 153{ 154 return (mask == 0 ? mask : (int)bsfq((u_long)mask) + 1); 155} 156 157#define HAVE_INLINE_FLS 158 159static __inline int 160fls(int mask) 161{ 162 return (mask == 0 ? mask : (int)bsrl((u_int)mask) + 1); 163} 164 165#define HAVE_INLINE_FLSL 166 167static __inline int 168flsl(long mask) 169{ 170 return (mask == 0 ? mask : (int)bsrq((u_long)mask) + 1); 171} 172 173#endif /* _KERNEL */ 174 175static __inline void 176halt(void) 177{ 178 __asm __volatile("hlt"); 179} 180 181static __inline u_char 182inb(u_int port) 183{ 184 u_char data; 185 186 __asm __volatile("inb %w1, %0" : "=a" (data) : "Nd" (port)); 187 return (data); 188} 189 190static __inline u_int 191inl(u_int port) 192{ 193 u_int data; 194 195 __asm __volatile("inl %w1, %0" : "=a" (data) : "Nd" (port)); 196 return (data); 197} 198 199static __inline void 200insb(u_int port, void *addr, size_t count) 201{ 202 __asm __volatile("cld; rep; insb" 203 : "+D" (addr), "+c" (count) 204 : "d" (port) 205 : "memory"); 206} 207 208static __inline void 209insw(u_int port, void *addr, size_t count) 210{ 211 __asm __volatile("cld; rep; insw" 212 : "+D" (addr), "+c" (count) 213 : "d" (port) 214 : "memory"); 215} 216 217static __inline void 218insl(u_int port, void *addr, size_t count) 219{ 220 __asm __volatile("cld; rep; insl" 221 : "+D" (addr), "+c" (count) 222 : "d" (port) 223 : "memory"); 224} 225 226static __inline void 227invd(void) 228{ 229 __asm __volatile("invd"); 230} 231 232static __inline u_short 233inw(u_int port) 234{ 235 u_short data; 236 237 __asm __volatile("inw %w1, %0" : "=a" (data) : "Nd" (port)); 238 return (data); 239} 240 241static __inline void 242outb(u_int port, u_char data) 243{ 244 __asm __volatile("outb %0, %w1" : : "a" (data), "Nd" (port)); 245} 246 247static __inline void 248outl(u_int port, u_int data) 249{ 250 __asm __volatile("outl %0, %w1" : : "a" (data), "Nd" (port)); 251} 252 253static __inline void 254outsb(u_int port, const void *addr, size_t count) 255{ 256 __asm __volatile("cld; rep; outsb" 257 : "+S" (addr), "+c" (count) 258 : "d" (port)); 259} 260 261static __inline void 262outsw(u_int port, const void *addr, size_t count) 263{ 264 __asm __volatile("cld; rep; outsw" 265 : "+S" (addr), "+c" (count) 266 : "d" (port)); 267} 268 269static __inline void 270outsl(u_int port, const void *addr, size_t count) 271{ 272 __asm __volatile("cld; rep; outsl" 273 : "+S" (addr), "+c" (count) 274 : "d" (port)); 275} 276 277static __inline void 278outw(u_int port, u_short data) 279{ 280 __asm __volatile("outw %0, %w1" : : "a" (data), "Nd" (port)); 281} 282 283static __inline u_long 284popcntq(u_long mask) 285{ 286 u_long result; 287 288 __asm __volatile("popcntq %1,%0" : "=r" (result) : "rm" (mask)); 289 return (result); 290} 291 292static __inline void 293lfence(void) 294{ 295 296 __asm __volatile("lfence" : : : "memory"); 297} 298 299static __inline void 300mfence(void) 301{ 302 303 __asm __volatile("mfence" : : : "memory"); 304} 305 306static __inline void 307ia32_pause(void) 308{ 309 __asm __volatile("pause"); 310} 311 312static __inline u_long 313read_rflags(void) 314{ 315 u_long rf; 316 317 __asm __volatile("pushfq; popq %0" : "=r" (rf)); 318 return (rf); 319} 320 321static __inline uint64_t 322rdmsr(u_int msr) 323{ 324 uint32_t low, high; 325 326 __asm __volatile("rdmsr" : "=a" (low), "=d" (high) : "c" (msr)); 327 return (low | ((uint64_t)high << 32)); 328} 329 330static __inline uint64_t 331rdpmc(u_int pmc) 332{ 333 uint32_t low, high; 334 335 __asm __volatile("rdpmc" : "=a" (low), "=d" (high) : "c" (pmc)); 336 return (low | ((uint64_t)high << 32)); 337} 338 339static __inline uint64_t 340rdtsc(void) 341{ 342 uint32_t low, high; 343 344 __asm __volatile("rdtsc" : "=a" (low), "=d" (high)); 345 return (low | ((uint64_t)high << 32)); 346} 347 348static __inline uint32_t 349rdtsc32(void) 350{ 351 uint32_t rv; 352 353 __asm __volatile("rdtsc" : "=a" (rv) : : "edx"); 354 return (rv); 355} 356 357static __inline void 358wbinvd(void) 359{ 360 __asm __volatile("wbinvd"); 361} 362 363static __inline void 364write_rflags(u_long rf) 365{ 366 __asm __volatile("pushq %0; popfq" : : "r" (rf)); 367} 368 369static __inline void 370wrmsr(u_int msr, uint64_t newval) 371{ 372 uint32_t low, high; 373 374 low = newval; 375 high = newval >> 32; 376 __asm __volatile("wrmsr" : : "a" (low), "d" (high), "c" (msr)); 377} 378 379static __inline void 380load_cr0(u_long data) 381{ 382 383 __asm __volatile("movq %0,%%cr0" : : "r" (data)); 384} 385 386static __inline u_long 387rcr0(void) 388{ 389 u_long data; 390 391 __asm __volatile("movq %%cr0,%0" : "=r" (data)); 392 return (data); 393} 394 395static __inline u_long 396rcr2(void) 397{ 398 u_long data; 399 400 __asm __volatile("movq %%cr2,%0" : "=r" (data)); 401 return (data); 402} 403 404static __inline void 405load_cr3(u_long data) 406{ 407 408 __asm __volatile("movq %0,%%cr3" : : "r" (data) : "memory"); 409} 410 411static __inline u_long 412rcr3(void) 413{ 414 u_long data; 415 416 __asm __volatile("movq %%cr3,%0" : "=r" (data)); 417 return (data); 418} 419 420static __inline void 421load_cr4(u_long data) 422{ 423 __asm __volatile("movq %0,%%cr4" : : "r" (data)); 424} 425 426static __inline u_long 427rcr4(void) 428{ 429 u_long data; 430 431 __asm __volatile("movq %%cr4,%0" : "=r" (data)); 432 return (data); 433} 434 435static __inline u_long 436rxcr(u_int reg) 437{ 438 u_int low, high; 439 440 __asm __volatile("xgetbv" : "=a" (low), "=d" (high) : "c" (reg)); 441 return (low | ((uint64_t)high << 32)); 442} 443 444static __inline void 445load_xcr(u_int reg, u_long val) 446{ 447 u_int low, high; 448 449 low = val; 450 high = val >> 32; 451 __asm __volatile("xsetbv" : : "c" (reg), "a" (low), "d" (high)); 452} 453 454/* 455 * Global TLB flush (except for thise for pages marked PG_G) 456 */ 457static __inline void 458invltlb(void) 459{ 460 461 load_cr3(rcr3()); 462} 463 464#ifndef CR4_PGE 465#define CR4_PGE 0x00000080 /* Page global enable */ 466#endif 467 468/* 469 * Perform the guaranteed invalidation of all TLB entries. This 470 * includes the global entries, and entries in all PCIDs, not only the 471 * current context. The function works both on non-PCID CPUs and CPUs 472 * with the PCID turned off or on. See IA-32 SDM Vol. 3a 4.10.4.1 473 * Operations that Invalidate TLBs and Paging-Structure Caches. 474 */ 475static __inline void 476invltlb_globpcid(void) 477{ 478 uint64_t cr4; 479 480 cr4 = rcr4(); 481 load_cr4(cr4 & ~CR4_PGE); 482 /* 483 * Although preemption at this point could be detrimental to 484 * performance, it would not lead to an error. PG_G is simply 485 * ignored if CR4.PGE is clear. Moreover, in case this block 486 * is re-entered, the load_cr4() either above or below will 487 * modify CR4.PGE flushing the TLB. 488 */ 489 load_cr4(cr4 | CR4_PGE); 490} 491 492/* 493 * TLB flush for an individual page (even if it has PG_G). 494 * Only works on 486+ CPUs (i386 does not have PG_G). 495 */ 496static __inline void 497invlpg(u_long addr) 498{ 499 500 __asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory"); 501} 502 503#define INVPCID_ADDR 0 504#define INVPCID_CTX 1 505#define INVPCID_CTXGLOB 2 506#define INVPCID_ALLCTX 3 507 508struct invpcid_descr { 509 uint64_t pcid:12 __packed; 510 uint64_t pad:52 __packed; 511 uint64_t addr; 512} __packed; 513 514static __inline void 515invpcid(struct invpcid_descr *d, int type) 516{ 517 518 /* invpcid (%rdx),%rax */ 519 __asm __volatile(".byte 0x66,0x0f,0x38,0x82,0x02" 520 : : "d" (d), "a" ((u_long)type) : "memory"); 521} 522 523static __inline u_short 524rfs(void) 525{ 526 u_short sel; 527 __asm __volatile("movw %%fs,%0" : "=rm" (sel)); 528 return (sel); 529} 530 531static __inline u_short 532rgs(void) 533{ 534 u_short sel; 535 __asm __volatile("movw %%gs,%0" : "=rm" (sel)); 536 return (sel); 537} 538 539static __inline u_short 540rss(void) 541{ 542 u_short sel; 543 __asm __volatile("movw %%ss,%0" : "=rm" (sel)); 544 return (sel); 545} 546 547static __inline void 548load_ds(u_short sel) 549{ 550 __asm __volatile("movw %0,%%ds" : : "rm" (sel)); 551} 552 553static __inline void 554load_es(u_short sel) 555{ 556 __asm __volatile("movw %0,%%es" : : "rm" (sel)); 557} 558 559static __inline void 560cpu_monitor(const void *addr, u_long extensions, u_int hints) 561{ 562 563 __asm __volatile("monitor" 564 : : "a" (addr), "c" (extensions), "d" (hints)); 565} 566 567static __inline void 568cpu_mwait(u_long extensions, u_int hints) 569{ 570 571 __asm __volatile("mwait" : : "a" (hints), "c" (extensions)); 572} 573 574#ifdef _KERNEL 575/* This is defined in <machine/specialreg.h> but is too painful to get to */ 576#ifndef MSR_FSBASE 577#define MSR_FSBASE 0xc0000100 578#endif 579static __inline void 580load_fs(u_short sel) 581{ 582 /* Preserve the fsbase value across the selector load */ 583 __asm __volatile("rdmsr; movw %0,%%fs; wrmsr" 584 : : "rm" (sel), "c" (MSR_FSBASE) : "eax", "edx"); 585} 586 587#ifndef MSR_GSBASE 588#define MSR_GSBASE 0xc0000101 589#endif 590static __inline void 591load_gs(u_short sel) 592{ 593 /* 594 * Preserve the gsbase value across the selector load. 595 * Note that we have to disable interrupts because the gsbase 596 * being trashed happens to be the kernel gsbase at the time. 597 */ 598 __asm __volatile("pushfq; cli; rdmsr; movw %0,%%gs; wrmsr; popfq" 599 : : "rm" (sel), "c" (MSR_GSBASE) : "eax", "edx"); 600} 601#else 602/* Usable by userland */ 603static __inline void 604load_fs(u_short sel) 605{ 606 __asm __volatile("movw %0,%%fs" : : "rm" (sel)); 607} 608 609static __inline void 610load_gs(u_short sel) 611{ 612 __asm __volatile("movw %0,%%gs" : : "rm" (sel)); 613} 614#endif 615 616static __inline void 617lidt(struct region_descriptor *addr) 618{ 619 __asm __volatile("lidt (%0)" : : "r" (addr)); 620} 621 622static __inline void 623lldt(u_short sel) 624{ 625 __asm __volatile("lldt %0" : : "r" (sel)); 626} 627 628static __inline void 629ltr(u_short sel) 630{ 631 __asm __volatile("ltr %0" : : "r" (sel)); 632} 633 634static __inline uint64_t 635rdr0(void) 636{ 637 uint64_t data; 638 __asm __volatile("movq %%dr0,%0" : "=r" (data)); 639 return (data); 640} 641 642static __inline void 643load_dr0(uint64_t dr0) 644{ 645 __asm __volatile("movq %0,%%dr0" : : "r" (dr0)); 646} 647 648static __inline uint64_t 649rdr1(void) 650{ 651 uint64_t data; 652 __asm __volatile("movq %%dr1,%0" : "=r" (data)); 653 return (data); 654} 655 656static __inline void 657load_dr1(uint64_t dr1) 658{ 659 __asm __volatile("movq %0,%%dr1" : : "r" (dr1)); 660} 661 662static __inline uint64_t 663rdr2(void) 664{ 665 uint64_t data; 666 __asm __volatile("movq %%dr2,%0" : "=r" (data)); 667 return (data); 668} 669 670static __inline void 671load_dr2(uint64_t dr2) 672{ 673 __asm __volatile("movq %0,%%dr2" : : "r" (dr2)); 674} 675 676static __inline uint64_t 677rdr3(void) 678{ 679 uint64_t data; 680 __asm __volatile("movq %%dr3,%0" : "=r" (data)); 681 return (data); 682} 683 684static __inline void 685load_dr3(uint64_t dr3) 686{ 687 __asm __volatile("movq %0,%%dr3" : : "r" (dr3)); 688} 689 690static __inline uint64_t 691rdr4(void) 692{ 693 uint64_t data; 694 __asm __volatile("movq %%dr4,%0" : "=r" (data)); 695 return (data); 696} 697 698static __inline void 699load_dr4(uint64_t dr4) 700{ 701 __asm __volatile("movq %0,%%dr4" : : "r" (dr4)); 702} 703 704static __inline uint64_t 705rdr5(void) 706{ 707 uint64_t data; 708 __asm __volatile("movq %%dr5,%0" : "=r" (data)); 709 return (data); 710} 711 712static __inline void 713load_dr5(uint64_t dr5) 714{ 715 __asm __volatile("movq %0,%%dr5" : : "r" (dr5)); 716} 717 718static __inline uint64_t 719rdr6(void) 720{ 721 uint64_t data; 722 __asm __volatile("movq %%dr6,%0" : "=r" (data)); 723 return (data); 724} 725 726static __inline void 727load_dr6(uint64_t dr6) 728{ 729 __asm __volatile("movq %0,%%dr6" : : "r" (dr6)); 730} 731 732static __inline uint64_t 733rdr7(void) 734{ 735 uint64_t data; 736 __asm __volatile("movq %%dr7,%0" : "=r" (data)); 737 return (data); 738} 739 740static __inline void 741load_dr7(uint64_t dr7) 742{ 743 __asm __volatile("movq %0,%%dr7" : : "r" (dr7)); 744} 745 746static __inline register_t 747intr_disable(void) 748{ 749 register_t rflags; 750 751 rflags = read_rflags(); 752 disable_intr(); 753 return (rflags); 754} 755 756static __inline void 757intr_restore(register_t rflags) 758{ 759 write_rflags(rflags); 760} 761 762#else /* !(__GNUCLIKE_ASM && __CC_SUPPORTS___INLINE) */ 763 764int breakpoint(void); 765u_int bsfl(u_int mask); 766u_int bsrl(u_int mask); 767void clflush(u_long addr); 768void clts(void); 769void cpuid_count(u_int ax, u_int cx, u_int *p); 770void disable_intr(void); 771void do_cpuid(u_int ax, u_int *p); 772void enable_intr(void); 773void halt(void); 774void ia32_pause(void); 775u_char inb(u_int port); 776u_int inl(u_int port); 777void insb(u_int port, void *addr, size_t count); 778void insl(u_int port, void *addr, size_t count); 779void insw(u_int port, void *addr, size_t count); 780register_t intr_disable(void); 781void intr_restore(register_t rf); 782void invd(void); 783void invlpg(u_int addr); 784void invltlb(void); 785u_short inw(u_int port); 786void lidt(struct region_descriptor *addr); 787void lldt(u_short sel); 788void load_cr0(u_long cr0); 789void load_cr3(u_long cr3); 790void load_cr4(u_long cr4); 791void load_dr0(uint64_t dr0); 792void load_dr1(uint64_t dr1); 793void load_dr2(uint64_t dr2); 794void load_dr3(uint64_t dr3); 795void load_dr4(uint64_t dr4); 796void load_dr5(uint64_t dr5); 797void load_dr6(uint64_t dr6); 798void load_dr7(uint64_t dr7); 799void load_fs(u_short sel); 800void load_gs(u_short sel); 801void ltr(u_short sel); 802void outb(u_int port, u_char data); 803void outl(u_int port, u_int data); 804void outsb(u_int port, const void *addr, size_t count); 805void outsl(u_int port, const void *addr, size_t count); 806void outsw(u_int port, const void *addr, size_t count); 807void outw(u_int port, u_short data); 808u_long rcr0(void); 809u_long rcr2(void); 810u_long rcr3(void); 811u_long rcr4(void); 812uint64_t rdmsr(u_int msr); 813uint64_t rdpmc(u_int pmc); 814uint64_t rdr0(void); 815uint64_t rdr1(void); 816uint64_t rdr2(void); 817uint64_t rdr3(void); 818uint64_t rdr4(void); 819uint64_t rdr5(void); 820uint64_t rdr6(void); 821uint64_t rdr7(void); 822uint64_t rdtsc(void); 823u_long read_rflags(void); 824u_int rfs(void); 825u_int rgs(void); 826void wbinvd(void); 827void write_rflags(u_int rf); 828void wrmsr(u_int msr, uint64_t newval); 829 830#endif /* __GNUCLIKE_ASM && __CC_SUPPORTS___INLINE */ 831 832void reset_dbregs(void); 833 834#ifdef _KERNEL 835int rdmsr_safe(u_int msr, uint64_t *val); 836int wrmsr_safe(u_int msr, uint64_t newval); 837#endif 838 839#endif /* !_MACHINE_CPUFUNC_H_ */ 840