1//===-- RegisterContext_x86.h -----------------------------------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10#ifndef liblldb_RegisterContext_x86_H_ 11#define liblldb_RegisterContext_x86_H_ 12 13//--------------------------------------------------------------------------- 14// i386 gcc, dwarf, gdb enums 15//--------------------------------------------------------------------------- 16 17// Register numbers seen in eh_frame (eRegisterKindGCC) 18// 19// From Jason Molenda: "gcc registers" is the register numbering used in the eh_frame 20// CFI. The only registers that are described in eh_frame CFI are those that are 21// preserved across function calls aka callee-saved aka non-volatile. And none 22// of the floating point registers on x86 are preserved across function calls. 23// 24// The only reason there is a "gcc register" and a "dwarf register" is because of a 25// mistake years and years ago with i386 where they got esp and ebp 26// backwards when they emitted the eh_frame instructions. Once there were 27// binaries In The Wild using the reversed numbering, we had to stick with it 28// forever. 29enum 30{ 31 // 2nd parameter in DwarfRegNum() is regnum for exception handling on x86-32. 32 // See http://llvm.org/docs/WritingAnLLVMBackend.html#defining-a-register 33 gcc_eax_i386 = 0, 34 gcc_ecx_i386, 35 gcc_edx_i386, 36 gcc_ebx_i386, 37 gcc_ebp_i386, // Warning: these are switched from dwarf values 38 gcc_esp_i386, // 39 gcc_esi_i386, 40 gcc_edi_i386, 41 gcc_eip_i386, 42 gcc_eflags_i386, 43 gcc_st0_i386 = 12, 44 gcc_st1_i386, 45 gcc_st2_i386, 46 gcc_st3_i386, 47 gcc_st4_i386, 48 gcc_st5_i386, 49 gcc_st6_i386, 50 gcc_st7_i386, 51 gcc_xmm0_i386 = 21, 52 gcc_xmm1_i386, 53 gcc_xmm2_i386, 54 gcc_xmm3_i386, 55 gcc_xmm4_i386, 56 gcc_xmm5_i386, 57 gcc_xmm6_i386, 58 gcc_xmm7_i386, 59 gcc_mm0_i386 = 29, 60 gcc_mm1_i386, 61 gcc_mm2_i386, 62 gcc_mm3_i386, 63 gcc_mm4_i386, 64 gcc_mm5_i386, 65 gcc_mm6_i386, 66 gcc_mm7_i386, 67}; 68 69// DWARF register numbers (eRegisterKindDWARF) 70// Intel's x86 or IA-32 71enum 72{ 73 // General Purpose Registers. 74 dwarf_eax_i386 = 0, 75 dwarf_ecx_i386, 76 dwarf_edx_i386, 77 dwarf_ebx_i386, 78 dwarf_esp_i386, 79 dwarf_ebp_i386, 80 dwarf_esi_i386, 81 dwarf_edi_i386, 82 dwarf_eip_i386, 83 dwarf_eflags_i386, 84 // Floating Point Registers 85 dwarf_st0_i386 = 11, 86 dwarf_st1_i386, 87 dwarf_st2_i386, 88 dwarf_st3_i386, 89 dwarf_st4_i386, 90 dwarf_st5_i386, 91 dwarf_st6_i386, 92 dwarf_st7_i386, 93 // SSE Registers 94 dwarf_xmm0_i386 = 21, 95 dwarf_xmm1_i386, 96 dwarf_xmm2_i386, 97 dwarf_xmm3_i386, 98 dwarf_xmm4_i386, 99 dwarf_xmm5_i386, 100 dwarf_xmm6_i386, 101 dwarf_xmm7_i386, 102 // MMX Registers 103 dwarf_mm0_i386 = 29, 104 dwarf_mm1_i386, 105 dwarf_mm2_i386, 106 dwarf_mm3_i386, 107 dwarf_mm4_i386, 108 dwarf_mm5_i386, 109 dwarf_mm6_i386, 110 dwarf_mm7_i386, 111 dwarf_fctrl_i386 = 37, // x87 control word 112 dwarf_fstat_i386 = 38, // x87 status word 113 dwarf_mxcsr_i386 = 39, 114 dwarf_es_i386 = 40, 115 dwarf_cs_i386 = 41, 116 dwarf_ss_i386 = 42, 117 dwarf_ds_i386 = 43, 118 dwarf_fs_i386 = 44, 119 dwarf_gs_i386 = 45 120 121 // I believe the ymm registers use the dwarf_xmm%_i386 register numbers and 122 // then differentiate based on size of the register. 123}; 124 125// Register numbers GDB uses (eRegisterKindGDB) 126// 127// From Jason Molenda: The "gdb numbers" are what you would see in the stabs debug format. 128enum 129{ 130 gdb_eax_i386, 131 gdb_ecx_i386, 132 gdb_edx_i386, 133 gdb_ebx_i386, 134 gdb_esp_i386, 135 gdb_ebp_i386, 136 gdb_esi_i386, 137 gdb_edi_i386, 138 gdb_eip_i386, 139 gdb_eflags_i386, 140 gdb_cs_i386, 141 gdb_ss_i386, 142 gdb_ds_i386, 143 gdb_es_i386, 144 gdb_fs_i386, 145 gdb_gs_i386, 146 gdb_st0_i386 = 16, 147 gdb_st1_i386, 148 gdb_st2_i386, 149 gdb_st3_i386, 150 gdb_st4_i386, 151 gdb_st5_i386, 152 gdb_st6_i386, 153 gdb_st7_i386, 154 gdb_fctrl_i386, // FPU Control Word 155 gdb_fstat_i386, // FPU Status Word 156 gdb_ftag_i386, // FPU Tag Word 157 gdb_fiseg_i386, // FPU IP Selector 158 gdb_fioff_i386, // FPU IP Offset 159 gdb_foseg_i386, // FPU Operand Pointer Selector 160 gdb_fooff_i386, // FPU Operand Pointer Offset 161 gdb_fop_i386, // Last Instruction Opcode 162 gdb_xmm0_i386 = 32, 163 gdb_xmm1_i386, 164 gdb_xmm2_i386, 165 gdb_xmm3_i386, 166 gdb_xmm4_i386, 167 gdb_xmm5_i386, 168 gdb_xmm6_i386, 169 gdb_xmm7_i386, 170 gdb_mxcsr_i386 = 40, 171 gdb_ymm0h_i386, 172 gdb_ymm1h_i386, 173 gdb_ymm2h_i386, 174 gdb_ymm3h_i386, 175 gdb_ymm4h_i386, 176 gdb_ymm5h_i386, 177 gdb_ymm6h_i386, 178 gdb_ymm7h_i386, 179 gdb_mm0_i386, 180 gdb_mm1_i386, 181 gdb_mm2_i386, 182 gdb_mm3_i386, 183 gdb_mm4_i386, 184 gdb_mm5_i386, 185 gdb_mm6_i386, 186 gdb_mm7_i386, 187}; 188 189//--------------------------------------------------------------------------- 190// AMD x86_64, AMD64, Intel EM64T, or Intel 64 gcc, dwarf, gdb enums 191//--------------------------------------------------------------------------- 192 193// GCC and DWARF Register numbers (eRegisterKindGCC & eRegisterKindDWARF) 194// This is the spec I used (as opposed to x86-64-abi-0.99.pdf): 195// http://software.intel.com/sites/default/files/article/402129/mpx-linux64-abi.pdf 196enum 197{ 198 // GP Registers 199 gcc_dwarf_rax_x86_64 = 0, 200 gcc_dwarf_rdx_x86_64, 201 gcc_dwarf_rcx_x86_64, 202 gcc_dwarf_rbx_x86_64, 203 gcc_dwarf_rsi_x86_64, 204 gcc_dwarf_rdi_x86_64, 205 gcc_dwarf_rbp_x86_64, 206 gcc_dwarf_rsp_x86_64, 207 // Extended GP Registers 208 gcc_dwarf_r8_x86_64 = 8, 209 gcc_dwarf_r9_x86_64, 210 gcc_dwarf_r10_x86_64, 211 gcc_dwarf_r11_x86_64, 212 gcc_dwarf_r12_x86_64, 213 gcc_dwarf_r13_x86_64, 214 gcc_dwarf_r14_x86_64, 215 gcc_dwarf_r15_x86_64, 216 // Return Address (RA) mapped to RIP 217 gcc_dwarf_rip_x86_64 = 16, 218 // SSE Vector Registers 219 gcc_dwarf_xmm0_x86_64 = 17, 220 gcc_dwarf_xmm1_x86_64, 221 gcc_dwarf_xmm2_x86_64, 222 gcc_dwarf_xmm3_x86_64, 223 gcc_dwarf_xmm4_x86_64, 224 gcc_dwarf_xmm5_x86_64, 225 gcc_dwarf_xmm6_x86_64, 226 gcc_dwarf_xmm7_x86_64, 227 gcc_dwarf_xmm8_x86_64, 228 gcc_dwarf_xmm9_x86_64, 229 gcc_dwarf_xmm10_x86_64, 230 gcc_dwarf_xmm11_x86_64, 231 gcc_dwarf_xmm12_x86_64, 232 gcc_dwarf_xmm13_x86_64, 233 gcc_dwarf_xmm14_x86_64, 234 gcc_dwarf_xmm15_x86_64, 235 // Floating Point Registers 236 gcc_dwarf_st0_x86_64 = 33, 237 gcc_dwarf_st1_x86_64, 238 gcc_dwarf_st2_x86_64, 239 gcc_dwarf_st3_x86_64, 240 gcc_dwarf_st4_x86_64, 241 gcc_dwarf_st5_x86_64, 242 gcc_dwarf_st6_x86_64, 243 gcc_dwarf_st7_x86_64, 244 // MMX Registers 245 gcc_dwarf_mm0_x86_64 = 41, 246 gcc_dwarf_mm1_x86_64, 247 gcc_dwarf_mm2_x86_64, 248 gcc_dwarf_mm3_x86_64, 249 gcc_dwarf_mm4_x86_64, 250 gcc_dwarf_mm5_x86_64, 251 gcc_dwarf_mm6_x86_64, 252 gcc_dwarf_mm7_x86_64, 253 // Control and Status Flags Register 254 gcc_dwarf_rflags_x86_64 = 49, 255 // selector registers 256 gcc_dwarf_es_x86_64 = 50, 257 gcc_dwarf_cs_x86_64, 258 gcc_dwarf_ss_x86_64, 259 gcc_dwarf_ds_x86_64, 260 gcc_dwarf_fs_x86_64, 261 gcc_dwarf_gs_x86_64, 262 // Floating point control registers 263 gcc_dwarf_mxcsr_x86_64 = 64, // Media Control and Status 264 gcc_dwarf_fctrl_x86_64, // x87 control word 265 gcc_dwarf_fstat_x86_64, // x87 status word 266 // Upper Vector Registers 267 gcc_dwarf_ymm0h_x86_64 = 67, 268 gcc_dwarf_ymm1h_x86_64, 269 gcc_dwarf_ymm2h_x86_64, 270 gcc_dwarf_ymm3h_x86_64, 271 gcc_dwarf_ymm4h_x86_64, 272 gcc_dwarf_ymm5h_x86_64, 273 gcc_dwarf_ymm6h_x86_64, 274 gcc_dwarf_ymm7h_x86_64, 275 gcc_dwarf_ymm8h_x86_64, 276 gcc_dwarf_ymm9h_x86_64, 277 gcc_dwarf_ymm10h_x86_64, 278 gcc_dwarf_ymm11h_x86_64, 279 gcc_dwarf_ymm12h_x86_64, 280 gcc_dwarf_ymm13h_x86_64, 281 gcc_dwarf_ymm14h_x86_64, 282 gcc_dwarf_ymm15h_x86_64, 283 // AVX2 Vector Mask Registers 284 // gcc_dwarf_k0_x86_64 = 118, 285 // gcc_dwarf_k1_x86_64, 286 // gcc_dwarf_k2_x86_64, 287 // gcc_dwarf_k3_x86_64, 288 // gcc_dwarf_k4_x86_64, 289 // gcc_dwarf_k5_x86_64, 290 // gcc_dwarf_k6_x86_64, 291 // gcc_dwarf_k7_x86_64, 292}; 293 294// GDB Register numbers (eRegisterKindGDB) 295enum 296{ 297 // GP Registers 298 gdb_rax_x86_64 = 0, 299 gdb_rbx_x86_64, 300 gdb_rcx_x86_64, 301 gdb_rdx_x86_64, 302 gdb_rsi_x86_64, 303 gdb_rdi_x86_64, 304 gdb_rbp_x86_64, 305 gdb_rsp_x86_64, 306 // Extended GP Registers 307 gdb_r8_x86_64, 308 gdb_r9_x86_64, 309 gdb_r10_x86_64, 310 gdb_r11_x86_64, 311 gdb_r12_x86_64, 312 gdb_r13_x86_64, 313 gdb_r14_x86_64, 314 gdb_r15_x86_64, 315 // Return Address (RA) mapped to RIP 316 gdb_rip_x86_64, 317 // Control and Status Flags Register 318 gdb_rflags_x86_64, 319 gdb_cs_x86_64, 320 gdb_ss_x86_64, 321 gdb_ds_x86_64, 322 gdb_es_x86_64, 323 gdb_fs_x86_64, 324 gdb_gs_x86_64, 325 // Floating Point Registers 326 gdb_st0_x86_64, 327 gdb_st1_x86_64, 328 gdb_st2_x86_64, 329 gdb_st3_x86_64, 330 gdb_st4_x86_64, 331 gdb_st5_x86_64, 332 gdb_st6_x86_64, 333 gdb_st7_x86_64, 334 gdb_fctrl_x86_64, 335 gdb_fstat_x86_64, 336 gdb_ftag_x86_64, 337 gdb_fiseg_x86_64, 338 gdb_fioff_x86_64, 339 gdb_foseg_x86_64, 340 gdb_fooff_x86_64, 341 gdb_fop_x86_64, 342 // SSE Vector Registers 343 gdb_xmm0_x86_64 = 40, 344 gdb_xmm1_x86_64, 345 gdb_xmm2_x86_64, 346 gdb_xmm3_x86_64, 347 gdb_xmm4_x86_64, 348 gdb_xmm5_x86_64, 349 gdb_xmm6_x86_64, 350 gdb_xmm7_x86_64, 351 gdb_xmm8_x86_64, 352 gdb_xmm9_x86_64, 353 gdb_xmm10_x86_64, 354 gdb_xmm11_x86_64, 355 gdb_xmm12_x86_64, 356 gdb_xmm13_x86_64, 357 gdb_xmm14_x86_64, 358 gdb_xmm15_x86_64, 359 // Floating point control registers 360 gdb_mxcsr_x86_64 = 56, 361 gdb_ymm0h_x86_64, 362 gdb_ymm1h_x86_64, 363 gdb_ymm2h_x86_64, 364 gdb_ymm3h_x86_64, 365 gdb_ymm4h_x86_64, 366 gdb_ymm5h_x86_64, 367 gdb_ymm6h_x86_64, 368 gdb_ymm7h_x86_64, 369 gdb_ymm8h_x86_64, 370 gdb_ymm9h_x86_64, 371 gdb_ymm10h_x86_64, 372 gdb_ymm11h_x86_64, 373 gdb_ymm12h_x86_64, 374 gdb_ymm13h_x86_64, 375 gdb_ymm14h_x86_64, 376 gdb_ymm15h_x86_64 377}; 378 379//--------------------------------------------------------------------------- 380// Generic floating-point registers 381//--------------------------------------------------------------------------- 382 383struct MMSReg 384{ 385 uint8_t bytes[10]; 386 uint8_t pad[6]; 387}; 388 389struct XMMReg 390{ 391 uint8_t bytes[16]; // 128-bits for each XMM register 392}; 393 394// i387_fxsave_struct 395struct FXSAVE 396{ 397 uint16_t fctrl; // FPU Control Word (fcw) 398 uint16_t fstat; // FPU Status Word (fsw) 399 uint16_t ftag; // FPU Tag Word (ftw) 400 uint16_t fop; // Last Instruction Opcode (fop) 401 union 402 { 403 struct 404 { 405 uint64_t fip; // Instruction Pointer 406 uint64_t fdp; // Data Pointer 407 } x86_64; 408 struct 409 { 410 uint32_t fioff; // FPU IP Offset (fip) 411 uint32_t fiseg; // FPU IP Selector (fcs) 412 uint32_t fooff; // FPU Operand Pointer Offset (foo) 413 uint32_t foseg; // FPU Operand Pointer Selector (fos) 414 } i386; 415 } ptr; 416 uint32_t mxcsr; // MXCSR Register State 417 uint32_t mxcsrmask; // MXCSR Mask 418 MMSReg stmm[8]; // 8*16 bytes for each FP-reg = 128 bytes 419 XMMReg xmm[16]; // 16*16 bytes for each XMM-reg = 256 bytes 420 uint32_t padding[24]; 421}; 422 423//--------------------------------------------------------------------------- 424// Extended floating-point registers 425//--------------------------------------------------------------------------- 426 427struct YMMHReg 428{ 429 uint8_t bytes[16]; // 16 * 8 bits for the high bytes of each YMM register 430}; 431 432struct YMMReg 433{ 434 uint8_t bytes[32]; // 16 * 16 bits for each YMM register 435}; 436 437struct YMM 438{ 439 YMMReg ymm[16]; // assembled from ymmh and xmm registers 440}; 441 442struct XSAVE_HDR 443{ 444 uint64_t xstate_bv; // OS enabled xstate mask to determine the extended states supported by the processor 445 uint64_t reserved1[2]; 446 uint64_t reserved2[5]; 447} __attribute__((packed)); 448 449// x86 extensions to FXSAVE (i.e. for AVX processors) 450struct XSAVE 451{ 452 FXSAVE i387; // floating point registers typical in i387_fxsave_struct 453 XSAVE_HDR header; // The xsave_hdr_struct can be used to determine if the following extensions are usable 454 YMMHReg ymmh[16]; // High 16 bytes of each of 16 YMM registers (the low bytes are in FXSAVE.xmm for compatibility with SSE) 455 // Slot any extensions to the register file here 456} __attribute__((packed, aligned (64))); 457 458// Floating-point registers 459struct FPR 460{ 461 // Thread state for the floating-point unit of the processor read by ptrace. 462 union XSTATE 463 { 464 FXSAVE fxsave; // Generic floating-point registers. 465 XSAVE xsave; // x86 extended processor state. 466 } xstate; 467}; 468 469//--------------------------------------------------------------------------- 470// ptrace PTRACE_GETREGSET, PTRACE_SETREGSET structure 471//--------------------------------------------------------------------------- 472 473struct IOVEC 474{ 475 void *iov_base; // pointer to XSAVE 476 size_t iov_len; // sizeof(XSAVE) 477}; 478 479#endif 480