1234353Sdim//===-- PPCRegisterInfo.td - The PowerPC Register File -----*- tablegen -*-===// 2234353Sdim// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7234353Sdim// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// 11193323Sed//===----------------------------------------------------------------------===// 12193323Sed 13208599Srdivackylet Namespace = "PPC" in { 14263508Sdimdef sub_lt : SubRegIndex<1>; 15263508Sdimdef sub_gt : SubRegIndex<1, 1>; 16263508Sdimdef sub_eq : SubRegIndex<1, 2>; 17263508Sdimdef sub_un : SubRegIndex<1, 3>; 18263508Sdimdef sub_32 : SubRegIndex<32>; 19208599Srdivacky} 20208599Srdivacky 21208599Srdivacky 22193323Sedclass PPCReg<string n> : Register<n> { 23193323Sed let Namespace = "PPC"; 24193323Sed} 25193323Sed 26193323Sed// We identify all our registers with a 5-bit ID, for consistency's sake. 27193323Sed 28193323Sed// GPR - One of the 32 32-bit general-purpose registers 29193323Sedclass GPR<bits<5> num, string n> : PPCReg<n> { 30249423Sdim let HWEncoding{4-0} = num; 31193323Sed} 32193323Sed 33193323Sed// GP8 - One of the 32 64-bit general-purpose registers 34193323Sedclass GP8<GPR SubReg, string n> : PPCReg<n> { 35249423Sdim let HWEncoding = SubReg.HWEncoding; 36193323Sed let SubRegs = [SubReg]; 37208599Srdivacky let SubRegIndices = [sub_32]; 38193323Sed} 39193323Sed 40193323Sed// SPR - One of the 32-bit special-purpose registers 41193323Sedclass SPR<bits<10> num, string n> : PPCReg<n> { 42249423Sdim let HWEncoding{9-0} = num; 43193323Sed} 44193323Sed 45193323Sed// FPR - One of the 32 64-bit floating-point registers 46193323Sedclass FPR<bits<5> num, string n> : PPCReg<n> { 47249423Sdim let HWEncoding{4-0} = num; 48193323Sed} 49193323Sed 50193323Sed// VR - One of the 32 128-bit vector registers 51193323Sedclass VR<bits<5> num, string n> : PPCReg<n> { 52249423Sdim let HWEncoding{4-0} = num; 53193323Sed} 54193323Sed 55193323Sed// CR - One of the 8 4-bit condition registers 56195340Sedclass CR<bits<3> num, string n, list<Register> subregs> : PPCReg<n> { 57249423Sdim let HWEncoding{2-0} = num; 58195340Sed let SubRegs = subregs; 59193323Sed} 60193323Sed 61193323Sed// CRBIT - One of the 32 1-bit condition register fields 62193323Sedclass CRBIT<bits<5> num, string n> : PPCReg<n> { 63249423Sdim let HWEncoding{4-0} = num; 64193323Sed} 65193323Sed 66193323Sed// General-purpose registers 67249423Sdimforeach Index = 0-31 in { 68249423Sdim def R#Index : GPR<Index, "r"#Index>, DwarfRegNum<[-2, Index]>; 69249423Sdim} 70193323Sed 71193323Sed// 64-bit General-purpose registers 72249423Sdimforeach Index = 0-31 in { 73249423Sdim def X#Index : GP8<!cast<GPR>("R"#Index), "r"#Index>, 74249423Sdim DwarfRegNum<[Index, -2]>; 75249423Sdim} 76193323Sed 77193323Sed// Floating-point registers 78249423Sdimforeach Index = 0-31 in { 79249423Sdim def F#Index : FPR<Index, "f"#Index>, 80249423Sdim DwarfRegNum<[!add(Index, 32), !add(Index, 32)]>; 81249423Sdim} 82193323Sed 83193323Sed// Vector registers 84249423Sdimforeach Index = 0-31 in { 85249423Sdim def V#Index : VR<Index, "v"#Index>, 86249423Sdim DwarfRegNum<[!add(Index, 77), !add(Index, 77)]>; 87249423Sdim} 88193323Sed 89249423Sdim// The reprsentation of r0 when treated as the constant 0. 90249423Sdimdef ZERO : GPR<0, "0">; 91249423Sdimdef ZERO8 : GP8<ZERO, "0">; 92249423Sdim 93249423Sdim// Representations of the frame pointer used by ISD::FRAMEADDR. 94249423Sdimdef FP : GPR<0 /* arbitrary */, "**FRAME POINTER**">; 95249423Sdimdef FP8 : GP8<FP, "**FRAME POINTER**">; 96249423Sdim 97263508Sdim// Representations of the base pointer used by setjmp. 98263508Sdimdef BP : GPR<0 /* arbitrary */, "**BASE POINTER**">; 99263508Sdimdef BP8 : GP8<BP, "**BASE POINTER**">; 100263508Sdim 101193323Sed// Condition register bits 102223017Sdimdef CR0LT : CRBIT< 0, "0">; 103223017Sdimdef CR0GT : CRBIT< 1, "1">; 104223017Sdimdef CR0EQ : CRBIT< 2, "2">; 105223017Sdimdef CR0UN : CRBIT< 3, "3">; 106223017Sdimdef CR1LT : CRBIT< 4, "4">; 107223017Sdimdef CR1GT : CRBIT< 5, "5">; 108223017Sdimdef CR1EQ : CRBIT< 6, "6">; 109223017Sdimdef CR1UN : CRBIT< 7, "7">; 110223017Sdimdef CR2LT : CRBIT< 8, "8">; 111223017Sdimdef CR2GT : CRBIT< 9, "9">; 112223017Sdimdef CR2EQ : CRBIT<10, "10">; 113223017Sdimdef CR2UN : CRBIT<11, "11">; 114223017Sdimdef CR3LT : CRBIT<12, "12">; 115223017Sdimdef CR3GT : CRBIT<13, "13">; 116223017Sdimdef CR3EQ : CRBIT<14, "14">; 117223017Sdimdef CR3UN : CRBIT<15, "15">; 118223017Sdimdef CR4LT : CRBIT<16, "16">; 119223017Sdimdef CR4GT : CRBIT<17, "17">; 120223017Sdimdef CR4EQ : CRBIT<18, "18">; 121223017Sdimdef CR4UN : CRBIT<19, "19">; 122223017Sdimdef CR5LT : CRBIT<20, "20">; 123223017Sdimdef CR5GT : CRBIT<21, "21">; 124223017Sdimdef CR5EQ : CRBIT<22, "22">; 125223017Sdimdef CR5UN : CRBIT<23, "23">; 126223017Sdimdef CR6LT : CRBIT<24, "24">; 127223017Sdimdef CR6GT : CRBIT<25, "25">; 128223017Sdimdef CR6EQ : CRBIT<26, "26">; 129223017Sdimdef CR6UN : CRBIT<27, "27">; 130223017Sdimdef CR7LT : CRBIT<28, "28">; 131223017Sdimdef CR7GT : CRBIT<29, "29">; 132223017Sdimdef CR7EQ : CRBIT<30, "30">; 133223017Sdimdef CR7UN : CRBIT<31, "31">; 134193323Sed 135195340Sed// Condition registers 136208599Srdivackylet SubRegIndices = [sub_lt, sub_gt, sub_eq, sub_un] in { 137223017Sdimdef CR0 : CR<0, "cr0", [CR0LT, CR0GT, CR0EQ, CR0UN]>, DwarfRegNum<[68, 68]>; 138223017Sdimdef CR1 : CR<1, "cr1", [CR1LT, CR1GT, CR1EQ, CR1UN]>, DwarfRegNum<[69, 69]>; 139223017Sdimdef CR2 : CR<2, "cr2", [CR2LT, CR2GT, CR2EQ, CR2UN]>, DwarfRegNum<[70, 70]>; 140223017Sdimdef CR3 : CR<3, "cr3", [CR3LT, CR3GT, CR3EQ, CR3UN]>, DwarfRegNum<[71, 71]>; 141223017Sdimdef CR4 : CR<4, "cr4", [CR4LT, CR4GT, CR4EQ, CR4UN]>, DwarfRegNum<[72, 72]>; 142223017Sdimdef CR5 : CR<5, "cr5", [CR5LT, CR5GT, CR5EQ, CR5UN]>, DwarfRegNum<[73, 73]>; 143223017Sdimdef CR6 : CR<6, "cr6", [CR6LT, CR6GT, CR6EQ, CR6UN]>, DwarfRegNum<[74, 74]>; 144223017Sdimdef CR7 : CR<7, "cr7", [CR7LT, CR7GT, CR7EQ, CR7UN]>, DwarfRegNum<[75, 75]>; 145208599Srdivacky} 146195340Sed 147266715Sdim// The full condition-code register. This is not modeled fully, but defined 148266715Sdim// here primarily, for compatibility with gcc, to allow the inline asm "cc" 149266715Sdim// clobber specification to work. 150266715Sdimdef CC : PPCReg<"cc">, DwarfRegAlias<CR0> { 151266715Sdim let Aliases = [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7]; 152266715Sdim} 153266715Sdim 154193323Sed// Link register 155223017Sdimdef LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>; 156193323Sed//let Aliases = [LR] in 157223017Sdimdef LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>; 158193323Sed 159193323Sed// Count register 160223017Sdimdef CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>; 161223017Sdimdef CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>; 162193323Sed 163193323Sed// VRsave register 164263508Sdimdef VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>; 165193323Sed 166198090Srdivacky// Carry bit. In the architecture this is really bit 0 of the XER register 167198090Srdivacky// (which really is SPR register 1); this is the only bit interesting to a 168198090Srdivacky// compiler. 169223017Sdimdef CARRY: SPR<1, "ca">; 170198090Srdivacky 171193323Sed// FP rounding mode: bits 30 and 31 of the FP status and control register 172193323Sed// This is not allocated as a normal register; it appears only in 173193323Sed// Uses and Defs. The ABI says it needs to be preserved by a function, 174193323Sed// but this is not achieved by saving and restoring it as with 175193323Sed// most registers, it has to be done in code; to make this work all the 176193323Sed// return and call instructions are described as Uses of RM, so instructions 177193323Sed// that do nothing but change RM will not get deleted. 178193323Sed// Also, in the architecture it is not really a SPR; 512 is arbitrary. 179223017Sdimdef RM: SPR<512, "**ROUNDING MODE**">; 180193323Sed 181193323Sed/// Register classes 182193323Sed// Allocate volatiles first 183193323Sed// then nonvolatiles in reverse order since stmw/lmw save from rN to r31 184224145Sdimdef GPRC : RegisterClass<"PPC", [i32], 32, (add (sequence "R%u", 2, 12), 185224145Sdim (sequence "R%u", 30, 13), 186263508Sdim R31, R0, R1, FP, BP)>; 187223017Sdim 188224145Sdimdef G8RC : RegisterClass<"PPC", [i64], 64, (add (sequence "X%u", 2, 12), 189224145Sdim (sequence "X%u", 30, 14), 190263508Sdim X31, X13, X0, X1, FP8, BP8)>; 191193323Sed 192249423Sdim// For some instructions r0 is special (representing the value 0 instead of 193249423Sdim// the value in the r0 register), and we use these register subclasses to 194249423Sdim// prevent r0 from being allocated for use by those instructions. 195249423Sdimdef GPRC_NOR0 : RegisterClass<"PPC", [i32], 32, (add (sub GPRC, R0), ZERO)>; 196249423Sdimdef G8RC_NOX0 : RegisterClass<"PPC", [i64], 64, (add (sub G8RC, X0), ZERO8)>; 197249423Sdim 198195340Sed// Allocate volatiles first, then non-volatiles in reverse order. With the SVR4 199195340Sed// ABI the size of the Floating-point register save area is determined by the 200195340Sed// allocated non-volatile register with the lowest register number, as FP 201195340Sed// register N is spilled to offset 8 * (32 - N) below the back chain word of the 202195340Sed// previous stack frame. By allocating non-volatiles in reverse order we make 203195340Sed// sure that the Floating-point register save area is always as small as 204195340Sed// possible because there aren't any unused spill slots. 205224145Sdimdef F8RC : RegisterClass<"PPC", [f64], 64, (add (sequence "F%u", 0, 13), 206224145Sdim (sequence "F%u", 31, 14))>; 207224145Sdimdef F4RC : RegisterClass<"PPC", [f32], 32, (add F8RC)>; 208193323Sed 209193323Seddef VRRC : RegisterClass<"PPC", [v16i8,v8i16,v4i32,v4f32], 128, 210224145Sdim (add V2, V3, V4, V5, V0, V1, V6, V7, V8, V9, V10, V11, 211224145Sdim V12, V13, V14, V15, V16, V17, V18, V19, V31, V30, 212224145Sdim V29, V28, V27, V26, V25, V24, V23, V22, V21, V20)>; 213193323Sed 214193323Seddef CRBITRC : RegisterClass<"PPC", [i32], 32, 215224145Sdim (add CR0LT, CR0GT, CR0EQ, CR0UN, 216224145Sdim CR1LT, CR1GT, CR1EQ, CR1UN, 217224145Sdim CR2LT, CR2GT, CR2EQ, CR2UN, 218224145Sdim CR3LT, CR3GT, CR3EQ, CR3UN, 219224145Sdim CR4LT, CR4GT, CR4EQ, CR4UN, 220224145Sdim CR5LT, CR5GT, CR5EQ, CR5UN, 221224145Sdim CR6LT, CR6GT, CR6EQ, CR6UN, 222224145Sdim CR7LT, CR7GT, CR7EQ, CR7UN)> 223193323Sed{ 224193323Sed let CopyCost = -1; 225193323Sed} 226193323Sed 227224145Sdimdef CRRC : RegisterClass<"PPC", [i32], 32, (add CR0, CR1, CR5, CR6, 228239462Sdim CR7, CR2, CR3, CR4)>; 229239462Sdim 230239462Sdim// The CTR registers are not allocatable because they're used by the 231239462Sdim// decrement-and-branch instructions, and thus need to stay live across 232239462Sdim// multiple basic blocks. 233239462Sdimdef CTRRC : RegisterClass<"PPC", [i32], 32, (add CTR)> { 234239462Sdim let isAllocatable = 0; 235195340Sed} 236239462Sdimdef CTRRC8 : RegisterClass<"PPC", [i64], 64, (add CTR8)> { 237239462Sdim let isAllocatable = 0; 238239462Sdim} 239193323Sed 240224145Sdimdef VRSAVERC : RegisterClass<"PPC", [i32], 32, (add VRSAVE)>; 241224145Sdimdef CARRYRC : RegisterClass<"PPC", [i32], 32, (add CARRY)> { 242198090Srdivacky let CopyCost = -1; 243198090Srdivacky} 244266715Sdim 245266715Sdimdef CCRC : RegisterClass<"PPC", [i32], 32, (add CC)> { 246266715Sdim let isAllocatable = 0; 247266715Sdim} 248266715Sdim 249