1249259Sdim//===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation -----===// 2249259Sdim// 3249259Sdim// The LLVM Compiler Infrastructure 4249259Sdim// 5249259Sdim// This file is distributed under the University of Illinois Open Source 6249259Sdim// License. See LICENSE.TXT for details. 7249259Sdim// 8249259Sdim//===----------------------------------------------------------------------===// 9249259Sdim// 10249259Sdim// This file defines the interfaces that AArch64 uses to lower LLVM code into a 11249259Sdim// selection DAG. 12249259Sdim// 13249259Sdim//===----------------------------------------------------------------------===// 14249259Sdim 15249259Sdim#define DEBUG_TYPE "aarch64-isel" 16249259Sdim#include "AArch64.h" 17249259Sdim#include "AArch64ISelLowering.h" 18249259Sdim#include "AArch64MachineFunctionInfo.h" 19249259Sdim#include "AArch64TargetMachine.h" 20249259Sdim#include "AArch64TargetObjectFile.h" 21249259Sdim#include "Utils/AArch64BaseInfo.h" 22249259Sdim#include "llvm/CodeGen/Analysis.h" 23249259Sdim#include "llvm/CodeGen/CallingConvLower.h" 24249259Sdim#include "llvm/CodeGen/MachineFrameInfo.h" 25249259Sdim#include "llvm/CodeGen/MachineInstrBuilder.h" 26249259Sdim#include "llvm/CodeGen/MachineRegisterInfo.h" 27249259Sdim#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 28249259Sdim#include "llvm/IR/CallingConv.h" 29249259Sdim 30249259Sdimusing namespace llvm; 31249259Sdim 32249259Sdimstatic TargetLoweringObjectFile *createTLOF(AArch64TargetMachine &TM) { 33249259Sdim const AArch64Subtarget *Subtarget = &TM.getSubtarget<AArch64Subtarget>(); 34266715Sdim assert (Subtarget->isTargetELF() && "unknown subtarget type"); 35266715Sdim return new AArch64ElfTargetObjectFile(); 36249259Sdim} 37249259Sdim 38249259SdimAArch64TargetLowering::AArch64TargetLowering(AArch64TargetMachine &TM) 39263508Sdim : TargetLowering(TM, createTLOF(TM)), Itins(TM.getInstrItineraryData()) { 40249259Sdim 41263508Sdim const AArch64Subtarget *Subtarget = &TM.getSubtarget<AArch64Subtarget>(); 42263508Sdim 43249259Sdim // SIMD compares set the entire lane's bits to 1 44249259Sdim setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 45249259Sdim 46249259Sdim // Scalar register <-> type mapping 47249259Sdim addRegisterClass(MVT::i32, &AArch64::GPR32RegClass); 48249259Sdim addRegisterClass(MVT::i64, &AArch64::GPR64RegClass); 49249259Sdim 50263508Sdim if (Subtarget->hasFPARMv8()) { 51263508Sdim addRegisterClass(MVT::f16, &AArch64::FPR16RegClass); 52263508Sdim addRegisterClass(MVT::f32, &AArch64::FPR32RegClass); 53263508Sdim addRegisterClass(MVT::f64, &AArch64::FPR64RegClass); 54263508Sdim addRegisterClass(MVT::f128, &AArch64::FPR128RegClass); 55263508Sdim } 56263508Sdim 57263508Sdim if (Subtarget->hasNEON()) { 58263508Sdim // And the vectors 59263508Sdim addRegisterClass(MVT::v1i8, &AArch64::FPR8RegClass); 60263508Sdim addRegisterClass(MVT::v1i16, &AArch64::FPR16RegClass); 61263508Sdim addRegisterClass(MVT::v1i32, &AArch64::FPR32RegClass); 62263508Sdim addRegisterClass(MVT::v1i64, &AArch64::FPR64RegClass); 63263508Sdim addRegisterClass(MVT::v1f32, &AArch64::FPR32RegClass); 64263508Sdim addRegisterClass(MVT::v1f64, &AArch64::FPR64RegClass); 65263508Sdim addRegisterClass(MVT::v8i8, &AArch64::FPR64RegClass); 66263508Sdim addRegisterClass(MVT::v4i16, &AArch64::FPR64RegClass); 67263508Sdim addRegisterClass(MVT::v2i32, &AArch64::FPR64RegClass); 68263508Sdim addRegisterClass(MVT::v1i64, &AArch64::FPR64RegClass); 69263508Sdim addRegisterClass(MVT::v2f32, &AArch64::FPR64RegClass); 70263508Sdim addRegisterClass(MVT::v16i8, &AArch64::FPR128RegClass); 71263508Sdim addRegisterClass(MVT::v8i16, &AArch64::FPR128RegClass); 72263508Sdim addRegisterClass(MVT::v4i32, &AArch64::FPR128RegClass); 73263508Sdim addRegisterClass(MVT::v2i64, &AArch64::FPR128RegClass); 74263508Sdim addRegisterClass(MVT::v4f32, &AArch64::FPR128RegClass); 75263508Sdim addRegisterClass(MVT::v2f64, &AArch64::FPR128RegClass); 76263508Sdim } 77263508Sdim 78249259Sdim computeRegisterProperties(); 79249259Sdim 80249259Sdim // We combine OR nodes for bitfield and NEON BSL operations. 81249259Sdim setTargetDAGCombine(ISD::OR); 82249259Sdim 83249259Sdim setTargetDAGCombine(ISD::AND); 84249259Sdim setTargetDAGCombine(ISD::SRA); 85263508Sdim setTargetDAGCombine(ISD::SRL); 86263508Sdim setTargetDAGCombine(ISD::SHL); 87249259Sdim 88263508Sdim setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN); 89263508Sdim setTargetDAGCombine(ISD::INTRINSIC_VOID); 90263508Sdim setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN); 91263508Sdim 92249259Sdim // AArch64 does not have i1 loads, or much of anything for i1 really. 93249259Sdim setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 94249259Sdim setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 95249259Sdim setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 96249259Sdim 97249259Sdim setStackPointerRegisterToSaveRestore(AArch64::XSP); 98249259Sdim setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 99249259Sdim setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 100249259Sdim setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 101249259Sdim 102249259Sdim // We'll lower globals to wrappers for selection. 103249259Sdim setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 104249259Sdim setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 105249259Sdim 106249259Sdim // A64 instructions have the comparison predicate attached to the user of the 107249259Sdim // result, but having a separate comparison is valuable for matching. 108249259Sdim setOperationAction(ISD::BR_CC, MVT::i32, Custom); 109249259Sdim setOperationAction(ISD::BR_CC, MVT::i64, Custom); 110249259Sdim setOperationAction(ISD::BR_CC, MVT::f32, Custom); 111249259Sdim setOperationAction(ISD::BR_CC, MVT::f64, Custom); 112249259Sdim 113249259Sdim setOperationAction(ISD::SELECT, MVT::i32, Custom); 114249259Sdim setOperationAction(ISD::SELECT, MVT::i64, Custom); 115249259Sdim setOperationAction(ISD::SELECT, MVT::f32, Custom); 116249259Sdim setOperationAction(ISD::SELECT, MVT::f64, Custom); 117249259Sdim 118249259Sdim setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 119249259Sdim setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); 120249259Sdim setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 121249259Sdim setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 122249259Sdim 123249259Sdim setOperationAction(ISD::BRCOND, MVT::Other, Custom); 124249259Sdim 125249259Sdim setOperationAction(ISD::SETCC, MVT::i32, Custom); 126249259Sdim setOperationAction(ISD::SETCC, MVT::i64, Custom); 127249259Sdim setOperationAction(ISD::SETCC, MVT::f32, Custom); 128249259Sdim setOperationAction(ISD::SETCC, MVT::f64, Custom); 129249259Sdim 130249259Sdim setOperationAction(ISD::BR_JT, MVT::Other, Expand); 131249259Sdim setOperationAction(ISD::JumpTable, MVT::i32, Custom); 132249259Sdim setOperationAction(ISD::JumpTable, MVT::i64, Custom); 133249259Sdim 134249259Sdim setOperationAction(ISD::VASTART, MVT::Other, Custom); 135249259Sdim setOperationAction(ISD::VACOPY, MVT::Other, Custom); 136249259Sdim setOperationAction(ISD::VAEND, MVT::Other, Expand); 137249259Sdim setOperationAction(ISD::VAARG, MVT::Other, Expand); 138249259Sdim 139249259Sdim setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 140249259Sdim 141249259Sdim setOperationAction(ISD::ROTL, MVT::i32, Expand); 142249259Sdim setOperationAction(ISD::ROTL, MVT::i64, Expand); 143249259Sdim 144249259Sdim setOperationAction(ISD::UREM, MVT::i32, Expand); 145249259Sdim setOperationAction(ISD::UREM, MVT::i64, Expand); 146249259Sdim setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 147249259Sdim setOperationAction(ISD::UDIVREM, MVT::i64, Expand); 148249259Sdim 149249259Sdim setOperationAction(ISD::SREM, MVT::i32, Expand); 150249259Sdim setOperationAction(ISD::SREM, MVT::i64, Expand); 151249259Sdim setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 152249259Sdim setOperationAction(ISD::SDIVREM, MVT::i64, Expand); 153249259Sdim 154249259Sdim setOperationAction(ISD::CTPOP, MVT::i32, Expand); 155249259Sdim setOperationAction(ISD::CTPOP, MVT::i64, Expand); 156249259Sdim 157249259Sdim // Legal floating-point operations. 158249259Sdim setOperationAction(ISD::FABS, MVT::f32, Legal); 159249259Sdim setOperationAction(ISD::FABS, MVT::f64, Legal); 160249259Sdim 161249259Sdim setOperationAction(ISD::FCEIL, MVT::f32, Legal); 162249259Sdim setOperationAction(ISD::FCEIL, MVT::f64, Legal); 163249259Sdim 164249259Sdim setOperationAction(ISD::FFLOOR, MVT::f32, Legal); 165249259Sdim setOperationAction(ISD::FFLOOR, MVT::f64, Legal); 166249259Sdim 167249259Sdim setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); 168249259Sdim setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); 169249259Sdim 170249259Sdim setOperationAction(ISD::FNEG, MVT::f32, Legal); 171249259Sdim setOperationAction(ISD::FNEG, MVT::f64, Legal); 172249259Sdim 173249259Sdim setOperationAction(ISD::FRINT, MVT::f32, Legal); 174249259Sdim setOperationAction(ISD::FRINT, MVT::f64, Legal); 175249259Sdim 176249259Sdim setOperationAction(ISD::FSQRT, MVT::f32, Legal); 177249259Sdim setOperationAction(ISD::FSQRT, MVT::f64, Legal); 178249259Sdim 179249259Sdim setOperationAction(ISD::FTRUNC, MVT::f32, Legal); 180249259Sdim setOperationAction(ISD::FTRUNC, MVT::f64, Legal); 181249259Sdim 182249259Sdim setOperationAction(ISD::ConstantFP, MVT::f32, Legal); 183249259Sdim setOperationAction(ISD::ConstantFP, MVT::f64, Legal); 184249259Sdim setOperationAction(ISD::ConstantFP, MVT::f128, Legal); 185249259Sdim 186249259Sdim // Illegal floating-point operations. 187249259Sdim setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 188249259Sdim setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 189249259Sdim 190249259Sdim setOperationAction(ISD::FCOS, MVT::f32, Expand); 191249259Sdim setOperationAction(ISD::FCOS, MVT::f64, Expand); 192249259Sdim 193249259Sdim setOperationAction(ISD::FEXP, MVT::f32, Expand); 194249259Sdim setOperationAction(ISD::FEXP, MVT::f64, Expand); 195249259Sdim 196249259Sdim setOperationAction(ISD::FEXP2, MVT::f32, Expand); 197249259Sdim setOperationAction(ISD::FEXP2, MVT::f64, Expand); 198249259Sdim 199249259Sdim setOperationAction(ISD::FLOG, MVT::f32, Expand); 200249259Sdim setOperationAction(ISD::FLOG, MVT::f64, Expand); 201249259Sdim 202249259Sdim setOperationAction(ISD::FLOG2, MVT::f32, Expand); 203249259Sdim setOperationAction(ISD::FLOG2, MVT::f64, Expand); 204249259Sdim 205249259Sdim setOperationAction(ISD::FLOG10, MVT::f32, Expand); 206249259Sdim setOperationAction(ISD::FLOG10, MVT::f64, Expand); 207249259Sdim 208249259Sdim setOperationAction(ISD::FPOW, MVT::f32, Expand); 209249259Sdim setOperationAction(ISD::FPOW, MVT::f64, Expand); 210249259Sdim 211249259Sdim setOperationAction(ISD::FPOWI, MVT::f32, Expand); 212249259Sdim setOperationAction(ISD::FPOWI, MVT::f64, Expand); 213249259Sdim 214249259Sdim setOperationAction(ISD::FREM, MVT::f32, Expand); 215249259Sdim setOperationAction(ISD::FREM, MVT::f64, Expand); 216249259Sdim 217249259Sdim setOperationAction(ISD::FSIN, MVT::f32, Expand); 218249259Sdim setOperationAction(ISD::FSIN, MVT::f64, Expand); 219249259Sdim 220249259Sdim setOperationAction(ISD::FSINCOS, MVT::f32, Expand); 221249259Sdim setOperationAction(ISD::FSINCOS, MVT::f64, Expand); 222249259Sdim 223249259Sdim // Virtually no operation on f128 is legal, but LLVM can't expand them when 224249259Sdim // there's a valid register class, so we need custom operations in most cases. 225249259Sdim setOperationAction(ISD::FABS, MVT::f128, Expand); 226249259Sdim setOperationAction(ISD::FADD, MVT::f128, Custom); 227249259Sdim setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand); 228249259Sdim setOperationAction(ISD::FCOS, MVT::f128, Expand); 229249259Sdim setOperationAction(ISD::FDIV, MVT::f128, Custom); 230249259Sdim setOperationAction(ISD::FMA, MVT::f128, Expand); 231249259Sdim setOperationAction(ISD::FMUL, MVT::f128, Custom); 232249259Sdim setOperationAction(ISD::FNEG, MVT::f128, Expand); 233249259Sdim setOperationAction(ISD::FP_EXTEND, MVT::f128, Expand); 234249259Sdim setOperationAction(ISD::FP_ROUND, MVT::f128, Expand); 235249259Sdim setOperationAction(ISD::FPOW, MVT::f128, Expand); 236249259Sdim setOperationAction(ISD::FREM, MVT::f128, Expand); 237249259Sdim setOperationAction(ISD::FRINT, MVT::f128, Expand); 238249259Sdim setOperationAction(ISD::FSIN, MVT::f128, Expand); 239249259Sdim setOperationAction(ISD::FSINCOS, MVT::f128, Expand); 240249259Sdim setOperationAction(ISD::FSQRT, MVT::f128, Expand); 241249259Sdim setOperationAction(ISD::FSUB, MVT::f128, Custom); 242249259Sdim setOperationAction(ISD::FTRUNC, MVT::f128, Expand); 243249259Sdim setOperationAction(ISD::SETCC, MVT::f128, Custom); 244249259Sdim setOperationAction(ISD::BR_CC, MVT::f128, Custom); 245249259Sdim setOperationAction(ISD::SELECT, MVT::f128, Expand); 246249259Sdim setOperationAction(ISD::SELECT_CC, MVT::f128, Custom); 247249259Sdim setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom); 248249259Sdim 249249259Sdim // Lowering for many of the conversions is actually specified by the non-f128 250249259Sdim // type. The LowerXXX function will be trivial when f128 isn't involved. 251249259Sdim setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 252249259Sdim setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 253249259Sdim setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom); 254249259Sdim setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); 255249259Sdim setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom); 256249259Sdim setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom); 257249259Sdim setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 258249259Sdim setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 259249259Sdim setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom); 260249259Sdim setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); 261249259Sdim setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); 262249259Sdim setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom); 263249259Sdim setOperationAction(ISD::FP_ROUND, MVT::f32, Custom); 264249259Sdim setOperationAction(ISD::FP_ROUND, MVT::f64, Custom); 265249259Sdim 266249259Sdim // This prevents LLVM trying to compress double constants into a floating 267249259Sdim // constant-pool entry and trying to load from there. It's of doubtful benefit 268249259Sdim // for A64: we'd need LDR followed by FCVT, I believe. 269249259Sdim setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand); 270249259Sdim setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 271249259Sdim setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand); 272249259Sdim 273249259Sdim setTruncStoreAction(MVT::f128, MVT::f64, Expand); 274249259Sdim setTruncStoreAction(MVT::f128, MVT::f32, Expand); 275249259Sdim setTruncStoreAction(MVT::f128, MVT::f16, Expand); 276249259Sdim setTruncStoreAction(MVT::f64, MVT::f32, Expand); 277249259Sdim setTruncStoreAction(MVT::f64, MVT::f16, Expand); 278249259Sdim setTruncStoreAction(MVT::f32, MVT::f16, Expand); 279249259Sdim 280249259Sdim setExceptionPointerRegister(AArch64::X0); 281249259Sdim setExceptionSelectorRegister(AArch64::X1); 282263508Sdim 283263508Sdim if (Subtarget->hasNEON()) { 284263508Sdim setOperationAction(ISD::BUILD_VECTOR, MVT::v1i8, Custom); 285263508Sdim setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom); 286263508Sdim setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom); 287263508Sdim setOperationAction(ISD::BUILD_VECTOR, MVT::v1i16, Custom); 288263508Sdim setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom); 289263508Sdim setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom); 290263508Sdim setOperationAction(ISD::BUILD_VECTOR, MVT::v1i32, Custom); 291263508Sdim setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom); 292263508Sdim setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom); 293263508Sdim setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom); 294263508Sdim setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); 295263508Sdim setOperationAction(ISD::BUILD_VECTOR, MVT::v1f32, Custom); 296263508Sdim setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom); 297263508Sdim setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 298263508Sdim setOperationAction(ISD::BUILD_VECTOR, MVT::v1f64, Custom); 299263508Sdim setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); 300263508Sdim 301263508Sdim setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom); 302263508Sdim setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); 303263508Sdim setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom); 304263508Sdim setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i16, Custom); 305263508Sdim setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom); 306263508Sdim setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i32, Custom); 307263508Sdim setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom); 308263508Sdim setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); 309263508Sdim setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f32, Custom); 310263508Sdim setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); 311263508Sdim setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1f64, Custom); 312263508Sdim setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); 313263508Sdim 314263508Sdim setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Legal); 315263508Sdim setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Legal); 316263508Sdim setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Legal); 317263508Sdim setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Legal); 318263508Sdim setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Legal); 319263508Sdim setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Legal); 320263508Sdim setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Legal); 321263508Sdim setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Legal); 322263508Sdim setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Legal); 323263508Sdim 324263508Sdim setOperationAction(ISD::SETCC, MVT::v8i8, Custom); 325263508Sdim setOperationAction(ISD::SETCC, MVT::v16i8, Custom); 326263508Sdim setOperationAction(ISD::SETCC, MVT::v4i16, Custom); 327263508Sdim setOperationAction(ISD::SETCC, MVT::v8i16, Custom); 328263508Sdim setOperationAction(ISD::SETCC, MVT::v2i32, Custom); 329263508Sdim setOperationAction(ISD::SETCC, MVT::v4i32, Custom); 330263508Sdim setOperationAction(ISD::SETCC, MVT::v1i64, Custom); 331263508Sdim setOperationAction(ISD::SETCC, MVT::v2i64, Custom); 332263508Sdim setOperationAction(ISD::SETCC, MVT::v1f32, Custom); 333263508Sdim setOperationAction(ISD::SETCC, MVT::v2f32, Custom); 334263508Sdim setOperationAction(ISD::SETCC, MVT::v4f32, Custom); 335263508Sdim setOperationAction(ISD::SETCC, MVT::v1f64, Custom); 336263508Sdim setOperationAction(ISD::SETCC, MVT::v2f64, Custom); 337263508Sdim 338263508Sdim setOperationAction(ISD::FFLOOR, MVT::v2f32, Legal); 339263508Sdim setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal); 340263508Sdim setOperationAction(ISD::FFLOOR, MVT::v1f64, Legal); 341263508Sdim setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal); 342263508Sdim 343263508Sdim setOperationAction(ISD::FCEIL, MVT::v2f32, Legal); 344263508Sdim setOperationAction(ISD::FCEIL, MVT::v4f32, Legal); 345263508Sdim setOperationAction(ISD::FCEIL, MVT::v1f64, Legal); 346263508Sdim setOperationAction(ISD::FCEIL, MVT::v2f64, Legal); 347263508Sdim 348263508Sdim setOperationAction(ISD::FTRUNC, MVT::v2f32, Legal); 349263508Sdim setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal); 350263508Sdim setOperationAction(ISD::FTRUNC, MVT::v1f64, Legal); 351263508Sdim setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal); 352263508Sdim 353263508Sdim setOperationAction(ISD::FRINT, MVT::v2f32, Legal); 354263508Sdim setOperationAction(ISD::FRINT, MVT::v4f32, Legal); 355263508Sdim setOperationAction(ISD::FRINT, MVT::v1f64, Legal); 356263508Sdim setOperationAction(ISD::FRINT, MVT::v2f64, Legal); 357263508Sdim 358263508Sdim setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Legal); 359263508Sdim setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal); 360263508Sdim setOperationAction(ISD::FNEARBYINT, MVT::v1f64, Legal); 361263508Sdim setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal); 362263508Sdim 363263508Sdim setOperationAction(ISD::FROUND, MVT::v2f32, Legal); 364263508Sdim setOperationAction(ISD::FROUND, MVT::v4f32, Legal); 365263508Sdim setOperationAction(ISD::FROUND, MVT::v1f64, Legal); 366263508Sdim setOperationAction(ISD::FROUND, MVT::v2f64, Legal); 367263508Sdim } 368249259Sdim} 369249259Sdim 370263508SdimEVT AArch64TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const { 371249259Sdim // It's reasonably important that this value matches the "natural" legal 372249259Sdim // promotion from i1 for scalar types. Otherwise LegalizeTypes can get itself 373249259Sdim // in a twist (e.g. inserting an any_extend which then becomes i64 -> i64). 374249259Sdim if (!VT.isVector()) return MVT::i32; 375249259Sdim return VT.changeVectorElementTypeToInteger(); 376249259Sdim} 377249259Sdim 378251662Sdimstatic void getExclusiveOperation(unsigned Size, AtomicOrdering Ord, 379251662Sdim unsigned &LdrOpc, 380251662Sdim unsigned &StrOpc) { 381263508Sdim static const unsigned LoadBares[] = {AArch64::LDXR_byte, AArch64::LDXR_hword, 382263508Sdim AArch64::LDXR_word, AArch64::LDXR_dword}; 383263508Sdim static const unsigned LoadAcqs[] = {AArch64::LDAXR_byte, AArch64::LDAXR_hword, 384263508Sdim AArch64::LDAXR_word, AArch64::LDAXR_dword}; 385263508Sdim static const unsigned StoreBares[] = {AArch64::STXR_byte, AArch64::STXR_hword, 386263508Sdim AArch64::STXR_word, AArch64::STXR_dword}; 387263508Sdim static const unsigned StoreRels[] = {AArch64::STLXR_byte,AArch64::STLXR_hword, 388263508Sdim AArch64::STLXR_word, AArch64::STLXR_dword}; 389251662Sdim 390263508Sdim const unsigned *LoadOps, *StoreOps; 391251662Sdim if (Ord == Acquire || Ord == AcquireRelease || Ord == SequentiallyConsistent) 392251662Sdim LoadOps = LoadAcqs; 393251662Sdim else 394251662Sdim LoadOps = LoadBares; 395251662Sdim 396251662Sdim if (Ord == Release || Ord == AcquireRelease || Ord == SequentiallyConsistent) 397251662Sdim StoreOps = StoreRels; 398251662Sdim else 399251662Sdim StoreOps = StoreBares; 400251662Sdim 401251662Sdim assert(isPowerOf2_32(Size) && Size <= 8 && 402251662Sdim "unsupported size for atomic binary op!"); 403251662Sdim 404251662Sdim LdrOpc = LoadOps[Log2_32(Size)]; 405251662Sdim StrOpc = StoreOps[Log2_32(Size)]; 406249259Sdim} 407249259Sdim 408263508Sdim// FIXME: AArch64::DTripleRegClass and AArch64::QTripleRegClass don't really 409263508Sdim// have value type mapped, and they are both being defined as MVT::untyped. 410263508Sdim// Without knowing the MVT type, MachineLICM::getRegisterClassIDAndCost 411263508Sdim// would fail to figure out the register pressure correctly. 412263508Sdimstd::pair<const TargetRegisterClass*, uint8_t> 413263508SdimAArch64TargetLowering::findRepresentativeClass(MVT VT) const{ 414263508Sdim const TargetRegisterClass *RRC = 0; 415263508Sdim uint8_t Cost = 1; 416263508Sdim switch (VT.SimpleTy) { 417263508Sdim default: 418263508Sdim return TargetLowering::findRepresentativeClass(VT); 419263508Sdim case MVT::v4i64: 420263508Sdim RRC = &AArch64::QPairRegClass; 421263508Sdim Cost = 2; 422263508Sdim break; 423263508Sdim case MVT::v8i64: 424263508Sdim RRC = &AArch64::QQuadRegClass; 425263508Sdim Cost = 4; 426263508Sdim break; 427263508Sdim } 428263508Sdim return std::make_pair(RRC, Cost); 429263508Sdim} 430263508Sdim 431249259SdimMachineBasicBlock * 432249259SdimAArch64TargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 433249259Sdim unsigned Size, 434249259Sdim unsigned BinOpcode) const { 435249259Sdim // This also handles ATOMIC_SWAP, indicated by BinOpcode==0. 436249259Sdim const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 437249259Sdim 438249259Sdim const BasicBlock *LLVM_BB = BB->getBasicBlock(); 439249259Sdim MachineFunction *MF = BB->getParent(); 440249259Sdim MachineFunction::iterator It = BB; 441249259Sdim ++It; 442249259Sdim 443249259Sdim unsigned dest = MI->getOperand(0).getReg(); 444249259Sdim unsigned ptr = MI->getOperand(1).getReg(); 445249259Sdim unsigned incr = MI->getOperand(2).getReg(); 446251662Sdim AtomicOrdering Ord = static_cast<AtomicOrdering>(MI->getOperand(3).getImm()); 447249259Sdim DebugLoc dl = MI->getDebugLoc(); 448249259Sdim 449249259Sdim MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); 450249259Sdim 451249259Sdim unsigned ldrOpc, strOpc; 452251662Sdim getExclusiveOperation(Size, Ord, ldrOpc, strOpc); 453249259Sdim 454249259Sdim MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 455249259Sdim MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 456249259Sdim MF->insert(It, loopMBB); 457249259Sdim MF->insert(It, exitMBB); 458249259Sdim 459249259Sdim // Transfer the remainder of BB and its successor edges to exitMBB. 460249259Sdim exitMBB->splice(exitMBB->begin(), BB, 461249259Sdim llvm::next(MachineBasicBlock::iterator(MI)), 462249259Sdim BB->end()); 463249259Sdim exitMBB->transferSuccessorsAndUpdatePHIs(BB); 464249259Sdim 465249259Sdim const TargetRegisterClass *TRC 466249259Sdim = Size == 8 ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; 467249259Sdim unsigned scratch = (!BinOpcode) ? incr : MRI.createVirtualRegister(TRC); 468249259Sdim 469249259Sdim // thisMBB: 470249259Sdim // ... 471249259Sdim // fallthrough --> loopMBB 472249259Sdim BB->addSuccessor(loopMBB); 473249259Sdim 474249259Sdim // loopMBB: 475249259Sdim // ldxr dest, ptr 476249259Sdim // <binop> scratch, dest, incr 477249259Sdim // stxr stxr_status, scratch, ptr 478249259Sdim // cbnz stxr_status, loopMBB 479249259Sdim // fallthrough --> exitMBB 480249259Sdim BB = loopMBB; 481249259Sdim BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr); 482249259Sdim if (BinOpcode) { 483249259Sdim // All arithmetic operations we'll be creating are designed to take an extra 484249259Sdim // shift or extend operand, which we can conveniently set to zero. 485249259Sdim 486249259Sdim // Operand order needs to go the other way for NAND. 487249259Sdim if (BinOpcode == AArch64::BICwww_lsl || BinOpcode == AArch64::BICxxx_lsl) 488249259Sdim BuildMI(BB, dl, TII->get(BinOpcode), scratch) 489249259Sdim .addReg(incr).addReg(dest).addImm(0); 490249259Sdim else 491249259Sdim BuildMI(BB, dl, TII->get(BinOpcode), scratch) 492249259Sdim .addReg(dest).addReg(incr).addImm(0); 493249259Sdim } 494249259Sdim 495249259Sdim // From the stxr, the register is GPR32; from the cmp it's GPR32wsp 496249259Sdim unsigned stxr_status = MRI.createVirtualRegister(&AArch64::GPR32RegClass); 497249259Sdim MRI.constrainRegClass(stxr_status, &AArch64::GPR32wspRegClass); 498249259Sdim 499249259Sdim BuildMI(BB, dl, TII->get(strOpc), stxr_status).addReg(scratch).addReg(ptr); 500249259Sdim BuildMI(BB, dl, TII->get(AArch64::CBNZw)) 501249259Sdim .addReg(stxr_status).addMBB(loopMBB); 502249259Sdim 503249259Sdim BB->addSuccessor(loopMBB); 504249259Sdim BB->addSuccessor(exitMBB); 505249259Sdim 506249259Sdim // exitMBB: 507249259Sdim // ... 508249259Sdim BB = exitMBB; 509249259Sdim 510249259Sdim MI->eraseFromParent(); // The instruction is gone now. 511249259Sdim 512249259Sdim return BB; 513249259Sdim} 514249259Sdim 515249259SdimMachineBasicBlock * 516249259SdimAArch64TargetLowering::emitAtomicBinaryMinMax(MachineInstr *MI, 517249259Sdim MachineBasicBlock *BB, 518249259Sdim unsigned Size, 519249259Sdim unsigned CmpOp, 520249259Sdim A64CC::CondCodes Cond) const { 521249259Sdim const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 522249259Sdim 523249259Sdim const BasicBlock *LLVM_BB = BB->getBasicBlock(); 524249259Sdim MachineFunction *MF = BB->getParent(); 525249259Sdim MachineFunction::iterator It = BB; 526249259Sdim ++It; 527249259Sdim 528249259Sdim unsigned dest = MI->getOperand(0).getReg(); 529249259Sdim unsigned ptr = MI->getOperand(1).getReg(); 530249259Sdim unsigned incr = MI->getOperand(2).getReg(); 531251662Sdim AtomicOrdering Ord = static_cast<AtomicOrdering>(MI->getOperand(3).getImm()); 532251662Sdim 533249259Sdim unsigned oldval = dest; 534249259Sdim DebugLoc dl = MI->getDebugLoc(); 535249259Sdim 536249259Sdim MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); 537249259Sdim const TargetRegisterClass *TRC, *TRCsp; 538249259Sdim if (Size == 8) { 539249259Sdim TRC = &AArch64::GPR64RegClass; 540249259Sdim TRCsp = &AArch64::GPR64xspRegClass; 541249259Sdim } else { 542249259Sdim TRC = &AArch64::GPR32RegClass; 543249259Sdim TRCsp = &AArch64::GPR32wspRegClass; 544249259Sdim } 545249259Sdim 546249259Sdim unsigned ldrOpc, strOpc; 547251662Sdim getExclusiveOperation(Size, Ord, ldrOpc, strOpc); 548249259Sdim 549249259Sdim MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 550249259Sdim MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 551249259Sdim MF->insert(It, loopMBB); 552249259Sdim MF->insert(It, exitMBB); 553249259Sdim 554249259Sdim // Transfer the remainder of BB and its successor edges to exitMBB. 555249259Sdim exitMBB->splice(exitMBB->begin(), BB, 556249259Sdim llvm::next(MachineBasicBlock::iterator(MI)), 557249259Sdim BB->end()); 558249259Sdim exitMBB->transferSuccessorsAndUpdatePHIs(BB); 559249259Sdim 560249259Sdim unsigned scratch = MRI.createVirtualRegister(TRC); 561249259Sdim MRI.constrainRegClass(scratch, TRCsp); 562249259Sdim 563249259Sdim // thisMBB: 564249259Sdim // ... 565249259Sdim // fallthrough --> loopMBB 566249259Sdim BB->addSuccessor(loopMBB); 567249259Sdim 568249259Sdim // loopMBB: 569249259Sdim // ldxr dest, ptr 570249259Sdim // cmp incr, dest (, sign extend if necessary) 571249259Sdim // csel scratch, dest, incr, cond 572249259Sdim // stxr stxr_status, scratch, ptr 573249259Sdim // cbnz stxr_status, loopMBB 574249259Sdim // fallthrough --> exitMBB 575249259Sdim BB = loopMBB; 576249259Sdim BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr); 577249259Sdim 578249259Sdim // Build compare and cmov instructions. 579249259Sdim MRI.constrainRegClass(incr, TRCsp); 580249259Sdim BuildMI(BB, dl, TII->get(CmpOp)) 581249259Sdim .addReg(incr).addReg(oldval).addImm(0); 582249259Sdim 583249259Sdim BuildMI(BB, dl, TII->get(Size == 8 ? AArch64::CSELxxxc : AArch64::CSELwwwc), 584249259Sdim scratch) 585249259Sdim .addReg(oldval).addReg(incr).addImm(Cond); 586249259Sdim 587249259Sdim unsigned stxr_status = MRI.createVirtualRegister(&AArch64::GPR32RegClass); 588249259Sdim MRI.constrainRegClass(stxr_status, &AArch64::GPR32wspRegClass); 589249259Sdim 590249259Sdim BuildMI(BB, dl, TII->get(strOpc), stxr_status) 591249259Sdim .addReg(scratch).addReg(ptr); 592249259Sdim BuildMI(BB, dl, TII->get(AArch64::CBNZw)) 593249259Sdim .addReg(stxr_status).addMBB(loopMBB); 594249259Sdim 595249259Sdim BB->addSuccessor(loopMBB); 596249259Sdim BB->addSuccessor(exitMBB); 597249259Sdim 598249259Sdim // exitMBB: 599249259Sdim // ... 600249259Sdim BB = exitMBB; 601249259Sdim 602249259Sdim MI->eraseFromParent(); // The instruction is gone now. 603249259Sdim 604249259Sdim return BB; 605249259Sdim} 606249259Sdim 607249259SdimMachineBasicBlock * 608249259SdimAArch64TargetLowering::emitAtomicCmpSwap(MachineInstr *MI, 609249259Sdim MachineBasicBlock *BB, 610249259Sdim unsigned Size) const { 611249259Sdim unsigned dest = MI->getOperand(0).getReg(); 612249259Sdim unsigned ptr = MI->getOperand(1).getReg(); 613249259Sdim unsigned oldval = MI->getOperand(2).getReg(); 614249259Sdim unsigned newval = MI->getOperand(3).getReg(); 615251662Sdim AtomicOrdering Ord = static_cast<AtomicOrdering>(MI->getOperand(4).getImm()); 616249259Sdim const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 617249259Sdim DebugLoc dl = MI->getDebugLoc(); 618249259Sdim 619249259Sdim MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); 620249259Sdim const TargetRegisterClass *TRCsp; 621249259Sdim TRCsp = Size == 8 ? &AArch64::GPR64xspRegClass : &AArch64::GPR32wspRegClass; 622249259Sdim 623249259Sdim unsigned ldrOpc, strOpc; 624251662Sdim getExclusiveOperation(Size, Ord, ldrOpc, strOpc); 625249259Sdim 626249259Sdim MachineFunction *MF = BB->getParent(); 627249259Sdim const BasicBlock *LLVM_BB = BB->getBasicBlock(); 628249259Sdim MachineFunction::iterator It = BB; 629249259Sdim ++It; // insert the new blocks after the current block 630249259Sdim 631249259Sdim MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 632249259Sdim MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 633249259Sdim MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 634249259Sdim MF->insert(It, loop1MBB); 635249259Sdim MF->insert(It, loop2MBB); 636249259Sdim MF->insert(It, exitMBB); 637249259Sdim 638249259Sdim // Transfer the remainder of BB and its successor edges to exitMBB. 639249259Sdim exitMBB->splice(exitMBB->begin(), BB, 640249259Sdim llvm::next(MachineBasicBlock::iterator(MI)), 641249259Sdim BB->end()); 642249259Sdim exitMBB->transferSuccessorsAndUpdatePHIs(BB); 643249259Sdim 644249259Sdim // thisMBB: 645249259Sdim // ... 646249259Sdim // fallthrough --> loop1MBB 647249259Sdim BB->addSuccessor(loop1MBB); 648249259Sdim 649249259Sdim // loop1MBB: 650249259Sdim // ldxr dest, [ptr] 651249259Sdim // cmp dest, oldval 652249259Sdim // b.ne exitMBB 653249259Sdim BB = loop1MBB; 654249259Sdim BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr); 655249259Sdim 656249259Sdim unsigned CmpOp = Size == 8 ? AArch64::CMPxx_lsl : AArch64::CMPww_lsl; 657249259Sdim MRI.constrainRegClass(dest, TRCsp); 658249259Sdim BuildMI(BB, dl, TII->get(CmpOp)) 659249259Sdim .addReg(dest).addReg(oldval).addImm(0); 660249259Sdim BuildMI(BB, dl, TII->get(AArch64::Bcc)) 661249259Sdim .addImm(A64CC::NE).addMBB(exitMBB); 662249259Sdim BB->addSuccessor(loop2MBB); 663249259Sdim BB->addSuccessor(exitMBB); 664249259Sdim 665249259Sdim // loop2MBB: 666249259Sdim // strex stxr_status, newval, [ptr] 667249259Sdim // cbnz stxr_status, loop1MBB 668249259Sdim BB = loop2MBB; 669249259Sdim unsigned stxr_status = MRI.createVirtualRegister(&AArch64::GPR32RegClass); 670249259Sdim MRI.constrainRegClass(stxr_status, &AArch64::GPR32wspRegClass); 671249259Sdim 672249259Sdim BuildMI(BB, dl, TII->get(strOpc), stxr_status).addReg(newval).addReg(ptr); 673249259Sdim BuildMI(BB, dl, TII->get(AArch64::CBNZw)) 674249259Sdim .addReg(stxr_status).addMBB(loop1MBB); 675249259Sdim BB->addSuccessor(loop1MBB); 676249259Sdim BB->addSuccessor(exitMBB); 677249259Sdim 678249259Sdim // exitMBB: 679249259Sdim // ... 680249259Sdim BB = exitMBB; 681249259Sdim 682249259Sdim MI->eraseFromParent(); // The instruction is gone now. 683249259Sdim 684249259Sdim return BB; 685249259Sdim} 686249259Sdim 687249259SdimMachineBasicBlock * 688249259SdimAArch64TargetLowering::EmitF128CSEL(MachineInstr *MI, 689249259Sdim MachineBasicBlock *MBB) const { 690249259Sdim // We materialise the F128CSEL pseudo-instruction using conditional branches 691249259Sdim // and loads, giving an instruciton sequence like: 692249259Sdim // str q0, [sp] 693249259Sdim // b.ne IfTrue 694249259Sdim // b Finish 695249259Sdim // IfTrue: 696249259Sdim // str q1, [sp] 697249259Sdim // Finish: 698249259Sdim // ldr q0, [sp] 699249259Sdim // 700249259Sdim // Using virtual registers would probably not be beneficial since COPY 701249259Sdim // instructions are expensive for f128 (there's no actual instruction to 702249259Sdim // implement them). 703249259Sdim // 704249259Sdim // An alternative would be to do an integer-CSEL on some address. E.g.: 705249259Sdim // mov x0, sp 706249259Sdim // add x1, sp, #16 707249259Sdim // str q0, [x0] 708249259Sdim // str q1, [x1] 709249259Sdim // csel x0, x0, x1, ne 710249259Sdim // ldr q0, [x0] 711249259Sdim // 712249259Sdim // It's unclear which approach is actually optimal. 713249259Sdim const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 714249259Sdim MachineFunction *MF = MBB->getParent(); 715249259Sdim const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 716249259Sdim DebugLoc DL = MI->getDebugLoc(); 717249259Sdim MachineFunction::iterator It = MBB; 718249259Sdim ++It; 719249259Sdim 720249259Sdim unsigned DestReg = MI->getOperand(0).getReg(); 721249259Sdim unsigned IfTrueReg = MI->getOperand(1).getReg(); 722249259Sdim unsigned IfFalseReg = MI->getOperand(2).getReg(); 723249259Sdim unsigned CondCode = MI->getOperand(3).getImm(); 724249259Sdim bool NZCVKilled = MI->getOperand(4).isKill(); 725249259Sdim 726249259Sdim MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(LLVM_BB); 727249259Sdim MachineBasicBlock *EndBB = MF->CreateMachineBasicBlock(LLVM_BB); 728249259Sdim MF->insert(It, TrueBB); 729249259Sdim MF->insert(It, EndBB); 730249259Sdim 731249259Sdim // Transfer rest of current basic-block to EndBB 732249259Sdim EndBB->splice(EndBB->begin(), MBB, 733249259Sdim llvm::next(MachineBasicBlock::iterator(MI)), 734249259Sdim MBB->end()); 735249259Sdim EndBB->transferSuccessorsAndUpdatePHIs(MBB); 736249259Sdim 737249259Sdim // We need somewhere to store the f128 value needed. 738249259Sdim int ScratchFI = MF->getFrameInfo()->CreateSpillStackObject(16, 16); 739249259Sdim 740249259Sdim // [... start of incoming MBB ...] 741249259Sdim // str qIFFALSE, [sp] 742249259Sdim // b.cc IfTrue 743249259Sdim // b Done 744249259Sdim BuildMI(MBB, DL, TII->get(AArch64::LSFP128_STR)) 745249259Sdim .addReg(IfFalseReg) 746249259Sdim .addFrameIndex(ScratchFI) 747249259Sdim .addImm(0); 748249259Sdim BuildMI(MBB, DL, TII->get(AArch64::Bcc)) 749249259Sdim .addImm(CondCode) 750249259Sdim .addMBB(TrueBB); 751249259Sdim BuildMI(MBB, DL, TII->get(AArch64::Bimm)) 752249259Sdim .addMBB(EndBB); 753249259Sdim MBB->addSuccessor(TrueBB); 754249259Sdim MBB->addSuccessor(EndBB); 755249259Sdim 756263508Sdim if (!NZCVKilled) { 757263508Sdim // NZCV is live-through TrueBB. 758263508Sdim TrueBB->addLiveIn(AArch64::NZCV); 759263508Sdim EndBB->addLiveIn(AArch64::NZCV); 760263508Sdim } 761263508Sdim 762249259Sdim // IfTrue: 763249259Sdim // str qIFTRUE, [sp] 764249259Sdim BuildMI(TrueBB, DL, TII->get(AArch64::LSFP128_STR)) 765249259Sdim .addReg(IfTrueReg) 766249259Sdim .addFrameIndex(ScratchFI) 767249259Sdim .addImm(0); 768249259Sdim 769249259Sdim // Note: fallthrough. We can rely on LLVM adding a branch if it reorders the 770249259Sdim // blocks. 771249259Sdim TrueBB->addSuccessor(EndBB); 772249259Sdim 773249259Sdim // Done: 774249259Sdim // ldr qDEST, [sp] 775249259Sdim // [... rest of incoming MBB ...] 776249259Sdim MachineInstr *StartOfEnd = EndBB->begin(); 777249259Sdim BuildMI(*EndBB, StartOfEnd, DL, TII->get(AArch64::LSFP128_LDR), DestReg) 778249259Sdim .addFrameIndex(ScratchFI) 779249259Sdim .addImm(0); 780249259Sdim 781249259Sdim MI->eraseFromParent(); 782249259Sdim return EndBB; 783249259Sdim} 784249259Sdim 785249259SdimMachineBasicBlock * 786249259SdimAArch64TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 787249259Sdim MachineBasicBlock *MBB) const { 788249259Sdim switch (MI->getOpcode()) { 789249259Sdim default: llvm_unreachable("Unhandled instruction with custom inserter"); 790249259Sdim case AArch64::F128CSEL: 791249259Sdim return EmitF128CSEL(MI, MBB); 792249259Sdim case AArch64::ATOMIC_LOAD_ADD_I8: 793249259Sdim return emitAtomicBinary(MI, MBB, 1, AArch64::ADDwww_lsl); 794249259Sdim case AArch64::ATOMIC_LOAD_ADD_I16: 795249259Sdim return emitAtomicBinary(MI, MBB, 2, AArch64::ADDwww_lsl); 796249259Sdim case AArch64::ATOMIC_LOAD_ADD_I32: 797249259Sdim return emitAtomicBinary(MI, MBB, 4, AArch64::ADDwww_lsl); 798249259Sdim case AArch64::ATOMIC_LOAD_ADD_I64: 799249259Sdim return emitAtomicBinary(MI, MBB, 8, AArch64::ADDxxx_lsl); 800249259Sdim 801249259Sdim case AArch64::ATOMIC_LOAD_SUB_I8: 802249259Sdim return emitAtomicBinary(MI, MBB, 1, AArch64::SUBwww_lsl); 803249259Sdim case AArch64::ATOMIC_LOAD_SUB_I16: 804249259Sdim return emitAtomicBinary(MI, MBB, 2, AArch64::SUBwww_lsl); 805249259Sdim case AArch64::ATOMIC_LOAD_SUB_I32: 806249259Sdim return emitAtomicBinary(MI, MBB, 4, AArch64::SUBwww_lsl); 807249259Sdim case AArch64::ATOMIC_LOAD_SUB_I64: 808249259Sdim return emitAtomicBinary(MI, MBB, 8, AArch64::SUBxxx_lsl); 809249259Sdim 810249259Sdim case AArch64::ATOMIC_LOAD_AND_I8: 811249259Sdim return emitAtomicBinary(MI, MBB, 1, AArch64::ANDwww_lsl); 812249259Sdim case AArch64::ATOMIC_LOAD_AND_I16: 813249259Sdim return emitAtomicBinary(MI, MBB, 2, AArch64::ANDwww_lsl); 814249259Sdim case AArch64::ATOMIC_LOAD_AND_I32: 815249259Sdim return emitAtomicBinary(MI, MBB, 4, AArch64::ANDwww_lsl); 816249259Sdim case AArch64::ATOMIC_LOAD_AND_I64: 817249259Sdim return emitAtomicBinary(MI, MBB, 8, AArch64::ANDxxx_lsl); 818249259Sdim 819249259Sdim case AArch64::ATOMIC_LOAD_OR_I8: 820249259Sdim return emitAtomicBinary(MI, MBB, 1, AArch64::ORRwww_lsl); 821249259Sdim case AArch64::ATOMIC_LOAD_OR_I16: 822249259Sdim return emitAtomicBinary(MI, MBB, 2, AArch64::ORRwww_lsl); 823249259Sdim case AArch64::ATOMIC_LOAD_OR_I32: 824249259Sdim return emitAtomicBinary(MI, MBB, 4, AArch64::ORRwww_lsl); 825249259Sdim case AArch64::ATOMIC_LOAD_OR_I64: 826249259Sdim return emitAtomicBinary(MI, MBB, 8, AArch64::ORRxxx_lsl); 827249259Sdim 828249259Sdim case AArch64::ATOMIC_LOAD_XOR_I8: 829249259Sdim return emitAtomicBinary(MI, MBB, 1, AArch64::EORwww_lsl); 830249259Sdim case AArch64::ATOMIC_LOAD_XOR_I16: 831249259Sdim return emitAtomicBinary(MI, MBB, 2, AArch64::EORwww_lsl); 832249259Sdim case AArch64::ATOMIC_LOAD_XOR_I32: 833249259Sdim return emitAtomicBinary(MI, MBB, 4, AArch64::EORwww_lsl); 834249259Sdim case AArch64::ATOMIC_LOAD_XOR_I64: 835249259Sdim return emitAtomicBinary(MI, MBB, 8, AArch64::EORxxx_lsl); 836249259Sdim 837249259Sdim case AArch64::ATOMIC_LOAD_NAND_I8: 838249259Sdim return emitAtomicBinary(MI, MBB, 1, AArch64::BICwww_lsl); 839249259Sdim case AArch64::ATOMIC_LOAD_NAND_I16: 840249259Sdim return emitAtomicBinary(MI, MBB, 2, AArch64::BICwww_lsl); 841249259Sdim case AArch64::ATOMIC_LOAD_NAND_I32: 842249259Sdim return emitAtomicBinary(MI, MBB, 4, AArch64::BICwww_lsl); 843249259Sdim case AArch64::ATOMIC_LOAD_NAND_I64: 844249259Sdim return emitAtomicBinary(MI, MBB, 8, AArch64::BICxxx_lsl); 845249259Sdim 846249259Sdim case AArch64::ATOMIC_LOAD_MIN_I8: 847249259Sdim return emitAtomicBinaryMinMax(MI, MBB, 1, AArch64::CMPww_sxtb, A64CC::GT); 848249259Sdim case AArch64::ATOMIC_LOAD_MIN_I16: 849249259Sdim return emitAtomicBinaryMinMax(MI, MBB, 2, AArch64::CMPww_sxth, A64CC::GT); 850249259Sdim case AArch64::ATOMIC_LOAD_MIN_I32: 851249259Sdim return emitAtomicBinaryMinMax(MI, MBB, 4, AArch64::CMPww_lsl, A64CC::GT); 852249259Sdim case AArch64::ATOMIC_LOAD_MIN_I64: 853249259Sdim return emitAtomicBinaryMinMax(MI, MBB, 8, AArch64::CMPxx_lsl, A64CC::GT); 854249259Sdim 855249259Sdim case AArch64::ATOMIC_LOAD_MAX_I8: 856249259Sdim return emitAtomicBinaryMinMax(MI, MBB, 1, AArch64::CMPww_sxtb, A64CC::LT); 857249259Sdim case AArch64::ATOMIC_LOAD_MAX_I16: 858249259Sdim return emitAtomicBinaryMinMax(MI, MBB, 2, AArch64::CMPww_sxth, A64CC::LT); 859249259Sdim case AArch64::ATOMIC_LOAD_MAX_I32: 860249259Sdim return emitAtomicBinaryMinMax(MI, MBB, 4, AArch64::CMPww_lsl, A64CC::LT); 861249259Sdim case AArch64::ATOMIC_LOAD_MAX_I64: 862249259Sdim return emitAtomicBinaryMinMax(MI, MBB, 8, AArch64::CMPxx_lsl, A64CC::LT); 863249259Sdim 864249259Sdim case AArch64::ATOMIC_LOAD_UMIN_I8: 865249259Sdim return emitAtomicBinaryMinMax(MI, MBB, 1, AArch64::CMPww_uxtb, A64CC::HI); 866249259Sdim case AArch64::ATOMIC_LOAD_UMIN_I16: 867249259Sdim return emitAtomicBinaryMinMax(MI, MBB, 2, AArch64::CMPww_uxth, A64CC::HI); 868249259Sdim case AArch64::ATOMIC_LOAD_UMIN_I32: 869249259Sdim return emitAtomicBinaryMinMax(MI, MBB, 4, AArch64::CMPww_lsl, A64CC::HI); 870249259Sdim case AArch64::ATOMIC_LOAD_UMIN_I64: 871249259Sdim return emitAtomicBinaryMinMax(MI, MBB, 8, AArch64::CMPxx_lsl, A64CC::HI); 872249259Sdim 873249259Sdim case AArch64::ATOMIC_LOAD_UMAX_I8: 874249259Sdim return emitAtomicBinaryMinMax(MI, MBB, 1, AArch64::CMPww_uxtb, A64CC::LO); 875249259Sdim case AArch64::ATOMIC_LOAD_UMAX_I16: 876249259Sdim return emitAtomicBinaryMinMax(MI, MBB, 2, AArch64::CMPww_uxth, A64CC::LO); 877249259Sdim case AArch64::ATOMIC_LOAD_UMAX_I32: 878249259Sdim return emitAtomicBinaryMinMax(MI, MBB, 4, AArch64::CMPww_lsl, A64CC::LO); 879249259Sdim case AArch64::ATOMIC_LOAD_UMAX_I64: 880249259Sdim return emitAtomicBinaryMinMax(MI, MBB, 8, AArch64::CMPxx_lsl, A64CC::LO); 881249259Sdim 882249259Sdim case AArch64::ATOMIC_SWAP_I8: 883249259Sdim return emitAtomicBinary(MI, MBB, 1, 0); 884249259Sdim case AArch64::ATOMIC_SWAP_I16: 885249259Sdim return emitAtomicBinary(MI, MBB, 2, 0); 886249259Sdim case AArch64::ATOMIC_SWAP_I32: 887249259Sdim return emitAtomicBinary(MI, MBB, 4, 0); 888249259Sdim case AArch64::ATOMIC_SWAP_I64: 889249259Sdim return emitAtomicBinary(MI, MBB, 8, 0); 890249259Sdim 891249259Sdim case AArch64::ATOMIC_CMP_SWAP_I8: 892249259Sdim return emitAtomicCmpSwap(MI, MBB, 1); 893249259Sdim case AArch64::ATOMIC_CMP_SWAP_I16: 894249259Sdim return emitAtomicCmpSwap(MI, MBB, 2); 895249259Sdim case AArch64::ATOMIC_CMP_SWAP_I32: 896249259Sdim return emitAtomicCmpSwap(MI, MBB, 4); 897249259Sdim case AArch64::ATOMIC_CMP_SWAP_I64: 898249259Sdim return emitAtomicCmpSwap(MI, MBB, 8); 899249259Sdim } 900249259Sdim} 901249259Sdim 902249259Sdim 903249259Sdimconst char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const { 904249259Sdim switch (Opcode) { 905249259Sdim case AArch64ISD::BR_CC: return "AArch64ISD::BR_CC"; 906249259Sdim case AArch64ISD::Call: return "AArch64ISD::Call"; 907249259Sdim case AArch64ISD::FPMOV: return "AArch64ISD::FPMOV"; 908249259Sdim case AArch64ISD::GOTLoad: return "AArch64ISD::GOTLoad"; 909249259Sdim case AArch64ISD::BFI: return "AArch64ISD::BFI"; 910249259Sdim case AArch64ISD::EXTR: return "AArch64ISD::EXTR"; 911249259Sdim case AArch64ISD::Ret: return "AArch64ISD::Ret"; 912249259Sdim case AArch64ISD::SBFX: return "AArch64ISD::SBFX"; 913249259Sdim case AArch64ISD::SELECT_CC: return "AArch64ISD::SELECT_CC"; 914249259Sdim case AArch64ISD::SETCC: return "AArch64ISD::SETCC"; 915249259Sdim case AArch64ISD::TC_RETURN: return "AArch64ISD::TC_RETURN"; 916249259Sdim case AArch64ISD::THREAD_POINTER: return "AArch64ISD::THREAD_POINTER"; 917249259Sdim case AArch64ISD::TLSDESCCALL: return "AArch64ISD::TLSDESCCALL"; 918251662Sdim case AArch64ISD::WrapperLarge: return "AArch64ISD::WrapperLarge"; 919249259Sdim case AArch64ISD::WrapperSmall: return "AArch64ISD::WrapperSmall"; 920249259Sdim 921263508Sdim case AArch64ISD::NEON_BSL: 922263508Sdim return "AArch64ISD::NEON_BSL"; 923263508Sdim case AArch64ISD::NEON_MOVIMM: 924263508Sdim return "AArch64ISD::NEON_MOVIMM"; 925263508Sdim case AArch64ISD::NEON_MVNIMM: 926263508Sdim return "AArch64ISD::NEON_MVNIMM"; 927263508Sdim case AArch64ISD::NEON_FMOVIMM: 928263508Sdim return "AArch64ISD::NEON_FMOVIMM"; 929263508Sdim case AArch64ISD::NEON_CMP: 930263508Sdim return "AArch64ISD::NEON_CMP"; 931263508Sdim case AArch64ISD::NEON_CMPZ: 932263508Sdim return "AArch64ISD::NEON_CMPZ"; 933263508Sdim case AArch64ISD::NEON_TST: 934263508Sdim return "AArch64ISD::NEON_TST"; 935263508Sdim case AArch64ISD::NEON_QSHLs: 936263508Sdim return "AArch64ISD::NEON_QSHLs"; 937263508Sdim case AArch64ISD::NEON_QSHLu: 938263508Sdim return "AArch64ISD::NEON_QSHLu"; 939263508Sdim case AArch64ISD::NEON_VDUP: 940263508Sdim return "AArch64ISD::NEON_VDUP"; 941263508Sdim case AArch64ISD::NEON_VDUPLANE: 942263508Sdim return "AArch64ISD::NEON_VDUPLANE"; 943263508Sdim case AArch64ISD::NEON_REV16: 944263508Sdim return "AArch64ISD::NEON_REV16"; 945263508Sdim case AArch64ISD::NEON_REV32: 946263508Sdim return "AArch64ISD::NEON_REV32"; 947263508Sdim case AArch64ISD::NEON_REV64: 948263508Sdim return "AArch64ISD::NEON_REV64"; 949263508Sdim case AArch64ISD::NEON_UZP1: 950263508Sdim return "AArch64ISD::NEON_UZP1"; 951263508Sdim case AArch64ISD::NEON_UZP2: 952263508Sdim return "AArch64ISD::NEON_UZP2"; 953263508Sdim case AArch64ISD::NEON_ZIP1: 954263508Sdim return "AArch64ISD::NEON_ZIP1"; 955263508Sdim case AArch64ISD::NEON_ZIP2: 956263508Sdim return "AArch64ISD::NEON_ZIP2"; 957263508Sdim case AArch64ISD::NEON_TRN1: 958263508Sdim return "AArch64ISD::NEON_TRN1"; 959263508Sdim case AArch64ISD::NEON_TRN2: 960263508Sdim return "AArch64ISD::NEON_TRN2"; 961263508Sdim case AArch64ISD::NEON_LD1_UPD: 962263508Sdim return "AArch64ISD::NEON_LD1_UPD"; 963263508Sdim case AArch64ISD::NEON_LD2_UPD: 964263508Sdim return "AArch64ISD::NEON_LD2_UPD"; 965263508Sdim case AArch64ISD::NEON_LD3_UPD: 966263508Sdim return "AArch64ISD::NEON_LD3_UPD"; 967263508Sdim case AArch64ISD::NEON_LD4_UPD: 968263508Sdim return "AArch64ISD::NEON_LD4_UPD"; 969263508Sdim case AArch64ISD::NEON_ST1_UPD: 970263508Sdim return "AArch64ISD::NEON_ST1_UPD"; 971263508Sdim case AArch64ISD::NEON_ST2_UPD: 972263508Sdim return "AArch64ISD::NEON_ST2_UPD"; 973263508Sdim case AArch64ISD::NEON_ST3_UPD: 974263508Sdim return "AArch64ISD::NEON_ST3_UPD"; 975263508Sdim case AArch64ISD::NEON_ST4_UPD: 976263508Sdim return "AArch64ISD::NEON_ST4_UPD"; 977263508Sdim case AArch64ISD::NEON_LD1x2_UPD: 978263508Sdim return "AArch64ISD::NEON_LD1x2_UPD"; 979263508Sdim case AArch64ISD::NEON_LD1x3_UPD: 980263508Sdim return "AArch64ISD::NEON_LD1x3_UPD"; 981263508Sdim case AArch64ISD::NEON_LD1x4_UPD: 982263508Sdim return "AArch64ISD::NEON_LD1x4_UPD"; 983263508Sdim case AArch64ISD::NEON_ST1x2_UPD: 984263508Sdim return "AArch64ISD::NEON_ST1x2_UPD"; 985263508Sdim case AArch64ISD::NEON_ST1x3_UPD: 986263508Sdim return "AArch64ISD::NEON_ST1x3_UPD"; 987263508Sdim case AArch64ISD::NEON_ST1x4_UPD: 988263508Sdim return "AArch64ISD::NEON_ST1x4_UPD"; 989263508Sdim case AArch64ISD::NEON_LD2DUP: 990263508Sdim return "AArch64ISD::NEON_LD2DUP"; 991263508Sdim case AArch64ISD::NEON_LD3DUP: 992263508Sdim return "AArch64ISD::NEON_LD3DUP"; 993263508Sdim case AArch64ISD::NEON_LD4DUP: 994263508Sdim return "AArch64ISD::NEON_LD4DUP"; 995263508Sdim case AArch64ISD::NEON_LD2DUP_UPD: 996263508Sdim return "AArch64ISD::NEON_LD2DUP_UPD"; 997263508Sdim case AArch64ISD::NEON_LD3DUP_UPD: 998263508Sdim return "AArch64ISD::NEON_LD3DUP_UPD"; 999263508Sdim case AArch64ISD::NEON_LD4DUP_UPD: 1000263508Sdim return "AArch64ISD::NEON_LD4DUP_UPD"; 1001263508Sdim case AArch64ISD::NEON_LD2LN_UPD: 1002263508Sdim return "AArch64ISD::NEON_LD2LN_UPD"; 1003263508Sdim case AArch64ISD::NEON_LD3LN_UPD: 1004263508Sdim return "AArch64ISD::NEON_LD3LN_UPD"; 1005263508Sdim case AArch64ISD::NEON_LD4LN_UPD: 1006263508Sdim return "AArch64ISD::NEON_LD4LN_UPD"; 1007263508Sdim case AArch64ISD::NEON_ST2LN_UPD: 1008263508Sdim return "AArch64ISD::NEON_ST2LN_UPD"; 1009263508Sdim case AArch64ISD::NEON_ST3LN_UPD: 1010263508Sdim return "AArch64ISD::NEON_ST3LN_UPD"; 1011263508Sdim case AArch64ISD::NEON_ST4LN_UPD: 1012263508Sdim return "AArch64ISD::NEON_ST4LN_UPD"; 1013263508Sdim case AArch64ISD::NEON_VEXTRACT: 1014263508Sdim return "AArch64ISD::NEON_VEXTRACT"; 1015263508Sdim default: 1016263508Sdim return NULL; 1017249259Sdim } 1018249259Sdim} 1019249259Sdim 1020249259Sdimstatic const uint16_t AArch64FPRArgRegs[] = { 1021249259Sdim AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, 1022249259Sdim AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 1023249259Sdim}; 1024249259Sdimstatic const unsigned NumFPRArgRegs = llvm::array_lengthof(AArch64FPRArgRegs); 1025249259Sdim 1026249259Sdimstatic const uint16_t AArch64ArgRegs[] = { 1027249259Sdim AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, 1028249259Sdim AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 1029249259Sdim}; 1030249259Sdimstatic const unsigned NumArgRegs = llvm::array_lengthof(AArch64ArgRegs); 1031249259Sdim 1032249259Sdimstatic bool CC_AArch64NoMoreRegs(unsigned ValNo, MVT ValVT, MVT LocVT, 1033249259Sdim CCValAssign::LocInfo LocInfo, 1034249259Sdim ISD::ArgFlagsTy ArgFlags, CCState &State) { 1035249259Sdim // Mark all remaining general purpose registers as allocated. We don't 1036249259Sdim // backtrack: if (for example) an i128 gets put on the stack, no subsequent 1037249259Sdim // i64 will go in registers (C.11). 1038249259Sdim for (unsigned i = 0; i < NumArgRegs; ++i) 1039249259Sdim State.AllocateReg(AArch64ArgRegs[i]); 1040249259Sdim 1041249259Sdim return false; 1042249259Sdim} 1043249259Sdim 1044249259Sdim#include "AArch64GenCallingConv.inc" 1045249259Sdim 1046249259SdimCCAssignFn *AArch64TargetLowering::CCAssignFnForNode(CallingConv::ID CC) const { 1047249259Sdim 1048249259Sdim switch(CC) { 1049249259Sdim default: llvm_unreachable("Unsupported calling convention"); 1050249259Sdim case CallingConv::Fast: 1051249259Sdim case CallingConv::C: 1052249259Sdim return CC_A64_APCS; 1053249259Sdim } 1054249259Sdim} 1055249259Sdim 1056249259Sdimvoid 1057249259SdimAArch64TargetLowering::SaveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG, 1058263508Sdim SDLoc DL, SDValue &Chain) const { 1059249259Sdim MachineFunction &MF = DAG.getMachineFunction(); 1060249259Sdim MachineFrameInfo *MFI = MF.getFrameInfo(); 1061249259Sdim AArch64MachineFunctionInfo *FuncInfo 1062249259Sdim = MF.getInfo<AArch64MachineFunctionInfo>(); 1063249259Sdim 1064249259Sdim SmallVector<SDValue, 8> MemOps; 1065249259Sdim 1066249259Sdim unsigned FirstVariadicGPR = CCInfo.getFirstUnallocated(AArch64ArgRegs, 1067249259Sdim NumArgRegs); 1068249259Sdim unsigned FirstVariadicFPR = CCInfo.getFirstUnallocated(AArch64FPRArgRegs, 1069249259Sdim NumFPRArgRegs); 1070249259Sdim 1071249259Sdim unsigned GPRSaveSize = 8 * (NumArgRegs - FirstVariadicGPR); 1072249259Sdim int GPRIdx = 0; 1073249259Sdim if (GPRSaveSize != 0) { 1074249259Sdim GPRIdx = MFI->CreateStackObject(GPRSaveSize, 8, false); 1075249259Sdim 1076249259Sdim SDValue FIN = DAG.getFrameIndex(GPRIdx, getPointerTy()); 1077249259Sdim 1078249259Sdim for (unsigned i = FirstVariadicGPR; i < NumArgRegs; ++i) { 1079249259Sdim unsigned VReg = MF.addLiveIn(AArch64ArgRegs[i], &AArch64::GPR64RegClass); 1080249259Sdim SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64); 1081249259Sdim SDValue Store = DAG.getStore(Val.getValue(1), DL, Val, FIN, 1082249259Sdim MachinePointerInfo::getStack(i * 8), 1083249259Sdim false, false, 0); 1084249259Sdim MemOps.push_back(Store); 1085249259Sdim FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN, 1086249259Sdim DAG.getConstant(8, getPointerTy())); 1087249259Sdim } 1088249259Sdim } 1089249259Sdim 1090263508Sdim if (getSubtarget()->hasFPARMv8()) { 1091249259Sdim unsigned FPRSaveSize = 16 * (NumFPRArgRegs - FirstVariadicFPR); 1092249259Sdim int FPRIdx = 0; 1093263508Sdim // According to the AArch64 Procedure Call Standard, section B.1/B.3, we 1094263508Sdim // can omit a register save area if we know we'll never use registers of 1095263508Sdim // that class. 1096263508Sdim if (FPRSaveSize != 0) { 1097263508Sdim FPRIdx = MFI->CreateStackObject(FPRSaveSize, 16, false); 1098249259Sdim 1099263508Sdim SDValue FIN = DAG.getFrameIndex(FPRIdx, getPointerTy()); 1100249259Sdim 1101263508Sdim for (unsigned i = FirstVariadicFPR; i < NumFPRArgRegs; ++i) { 1102263508Sdim unsigned VReg = MF.addLiveIn(AArch64FPRArgRegs[i], 1103263508Sdim &AArch64::FPR128RegClass); 1104263508Sdim SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f128); 1105263508Sdim SDValue Store = DAG.getStore(Val.getValue(1), DL, Val, FIN, 1106263508Sdim MachinePointerInfo::getStack(i * 16), 1107263508Sdim false, false, 0); 1108263508Sdim MemOps.push_back(Store); 1109263508Sdim FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN, 1110263508Sdim DAG.getConstant(16, getPointerTy())); 1111263508Sdim } 1112249259Sdim } 1113263508Sdim FuncInfo->setVariadicFPRIdx(FPRIdx); 1114263508Sdim FuncInfo->setVariadicFPRSize(FPRSaveSize); 1115249259Sdim } 1116249259Sdim 1117249259Sdim int StackIdx = MFI->CreateFixedObject(8, CCInfo.getNextStackOffset(), true); 1118249259Sdim 1119249259Sdim FuncInfo->setVariadicStackIdx(StackIdx); 1120249259Sdim FuncInfo->setVariadicGPRIdx(GPRIdx); 1121249259Sdim FuncInfo->setVariadicGPRSize(GPRSaveSize); 1122249259Sdim 1123249259Sdim if (!MemOps.empty()) { 1124249259Sdim Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, &MemOps[0], 1125249259Sdim MemOps.size()); 1126249259Sdim } 1127249259Sdim} 1128249259Sdim 1129249259Sdim 1130249259SdimSDValue 1131249259SdimAArch64TargetLowering::LowerFormalArguments(SDValue Chain, 1132249259Sdim CallingConv::ID CallConv, bool isVarArg, 1133249259Sdim const SmallVectorImpl<ISD::InputArg> &Ins, 1134263508Sdim SDLoc dl, SelectionDAG &DAG, 1135249259Sdim SmallVectorImpl<SDValue> &InVals) const { 1136249259Sdim MachineFunction &MF = DAG.getMachineFunction(); 1137249259Sdim AArch64MachineFunctionInfo *FuncInfo 1138249259Sdim = MF.getInfo<AArch64MachineFunctionInfo>(); 1139249259Sdim MachineFrameInfo *MFI = MF.getFrameInfo(); 1140249259Sdim bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt; 1141249259Sdim 1142249259Sdim SmallVector<CCValAssign, 16> ArgLocs; 1143249259Sdim CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1144249259Sdim getTargetMachine(), ArgLocs, *DAG.getContext()); 1145249259Sdim CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv)); 1146249259Sdim 1147249259Sdim SmallVector<SDValue, 16> ArgValues; 1148249259Sdim 1149249259Sdim SDValue ArgValue; 1150249259Sdim for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1151249259Sdim CCValAssign &VA = ArgLocs[i]; 1152249259Sdim ISD::ArgFlagsTy Flags = Ins[i].Flags; 1153249259Sdim 1154249259Sdim if (Flags.isByVal()) { 1155249259Sdim // Byval is used for small structs and HFAs in the PCS, but the system 1156249259Sdim // should work in a non-compliant manner for larger structs. 1157249259Sdim EVT PtrTy = getPointerTy(); 1158249259Sdim int Size = Flags.getByValSize(); 1159249259Sdim unsigned NumRegs = (Size + 7) / 8; 1160249259Sdim 1161249259Sdim unsigned FrameIdx = MFI->CreateFixedObject(8 * NumRegs, 1162249259Sdim VA.getLocMemOffset(), 1163249259Sdim false); 1164249259Sdim SDValue FrameIdxN = DAG.getFrameIndex(FrameIdx, PtrTy); 1165249259Sdim InVals.push_back(FrameIdxN); 1166249259Sdim 1167249259Sdim continue; 1168249259Sdim } else if (VA.isRegLoc()) { 1169249259Sdim MVT RegVT = VA.getLocVT(); 1170249259Sdim const TargetRegisterClass *RC = getRegClassFor(RegVT); 1171249259Sdim unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1172249259Sdim 1173249259Sdim ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 1174249259Sdim } else { // VA.isRegLoc() 1175249259Sdim assert(VA.isMemLoc()); 1176249259Sdim 1177249259Sdim int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8, 1178249259Sdim VA.getLocMemOffset(), true); 1179249259Sdim 1180249259Sdim SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 1181249259Sdim ArgValue = DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, 1182249259Sdim MachinePointerInfo::getFixedStack(FI), 1183249259Sdim false, false, false, 0); 1184249259Sdim 1185249259Sdim 1186249259Sdim } 1187249259Sdim 1188249259Sdim switch (VA.getLocInfo()) { 1189249259Sdim default: llvm_unreachable("Unknown loc info!"); 1190249259Sdim case CCValAssign::Full: break; 1191249259Sdim case CCValAssign::BCvt: 1192249259Sdim ArgValue = DAG.getNode(ISD::BITCAST,dl, VA.getValVT(), ArgValue); 1193249259Sdim break; 1194249259Sdim case CCValAssign::SExt: 1195249259Sdim case CCValAssign::ZExt: 1196249259Sdim case CCValAssign::AExt: { 1197249259Sdim unsigned DestSize = VA.getValVT().getSizeInBits(); 1198249259Sdim unsigned DestSubReg; 1199249259Sdim 1200249259Sdim switch (DestSize) { 1201249259Sdim case 8: DestSubReg = AArch64::sub_8; break; 1202249259Sdim case 16: DestSubReg = AArch64::sub_16; break; 1203249259Sdim case 32: DestSubReg = AArch64::sub_32; break; 1204249259Sdim case 64: DestSubReg = AArch64::sub_64; break; 1205249259Sdim default: llvm_unreachable("Unexpected argument promotion"); 1206249259Sdim } 1207249259Sdim 1208249259Sdim ArgValue = SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, 1209249259Sdim VA.getValVT(), ArgValue, 1210249259Sdim DAG.getTargetConstant(DestSubReg, MVT::i32)), 1211249259Sdim 0); 1212249259Sdim break; 1213249259Sdim } 1214249259Sdim } 1215249259Sdim 1216249259Sdim InVals.push_back(ArgValue); 1217249259Sdim } 1218249259Sdim 1219249259Sdim if (isVarArg) 1220249259Sdim SaveVarArgRegisters(CCInfo, DAG, dl, Chain); 1221249259Sdim 1222249259Sdim unsigned StackArgSize = CCInfo.getNextStackOffset(); 1223249259Sdim if (DoesCalleeRestoreStack(CallConv, TailCallOpt)) { 1224249259Sdim // This is a non-standard ABI so by fiat I say we're allowed to make full 1225249259Sdim // use of the stack area to be popped, which must be aligned to 16 bytes in 1226249259Sdim // any case: 1227249259Sdim StackArgSize = RoundUpToAlignment(StackArgSize, 16); 1228249259Sdim 1229249259Sdim // If we're expected to restore the stack (e.g. fastcc) then we'll be adding 1230249259Sdim // a multiple of 16. 1231249259Sdim FuncInfo->setArgumentStackToRestore(StackArgSize); 1232249259Sdim 1233249259Sdim // This realignment carries over to the available bytes below. Our own 1234249259Sdim // callers will guarantee the space is free by giving an aligned value to 1235249259Sdim // CALLSEQ_START. 1236249259Sdim } 1237249259Sdim // Even if we're not expected to free up the space, it's useful to know how 1238249259Sdim // much is there while considering tail calls (because we can reuse it). 1239249259Sdim FuncInfo->setBytesInStackArgArea(StackArgSize); 1240249259Sdim 1241249259Sdim return Chain; 1242249259Sdim} 1243249259Sdim 1244249259SdimSDValue 1245249259SdimAArch64TargetLowering::LowerReturn(SDValue Chain, 1246249259Sdim CallingConv::ID CallConv, bool isVarArg, 1247249259Sdim const SmallVectorImpl<ISD::OutputArg> &Outs, 1248249259Sdim const SmallVectorImpl<SDValue> &OutVals, 1249263508Sdim SDLoc dl, SelectionDAG &DAG) const { 1250249259Sdim // CCValAssign - represent the assignment of the return value to a location. 1251249259Sdim SmallVector<CCValAssign, 16> RVLocs; 1252249259Sdim 1253249259Sdim // CCState - Info about the registers and stack slots. 1254249259Sdim CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1255249259Sdim getTargetMachine(), RVLocs, *DAG.getContext()); 1256249259Sdim 1257249259Sdim // Analyze outgoing return values. 1258249259Sdim CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv)); 1259249259Sdim 1260249259Sdim SDValue Flag; 1261249259Sdim SmallVector<SDValue, 4> RetOps(1, Chain); 1262249259Sdim 1263249259Sdim for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 1264249259Sdim // PCS: "If the type, T, of the result of a function is such that 1265249259Sdim // void func(T arg) would require that arg be passed as a value in a 1266249259Sdim // register (or set of registers) according to the rules in 5.4, then the 1267249259Sdim // result is returned in the same registers as would be used for such an 1268249259Sdim // argument. 1269249259Sdim // 1270249259Sdim // Otherwise, the caller shall reserve a block of memory of sufficient 1271249259Sdim // size and alignment to hold the result. The address of the memory block 1272249259Sdim // shall be passed as an additional argument to the function in x8." 1273249259Sdim // 1274249259Sdim // This is implemented in two places. The register-return values are dealt 1275249259Sdim // with here, more complex returns are passed as an sret parameter, which 1276249259Sdim // means we don't have to worry about it during actual return. 1277249259Sdim CCValAssign &VA = RVLocs[i]; 1278249259Sdim assert(VA.isRegLoc() && "Only register-returns should be created by PCS"); 1279249259Sdim 1280249259Sdim 1281249259Sdim SDValue Arg = OutVals[i]; 1282249259Sdim 1283249259Sdim // There's no convenient note in the ABI about this as there is for normal 1284249259Sdim // arguments, but it says return values are passed in the same registers as 1285249259Sdim // an argument would be. I believe that includes the comments about 1286249259Sdim // unspecified higher bits, putting the burden of widening on the *caller* 1287249259Sdim // for return values. 1288249259Sdim switch (VA.getLocInfo()) { 1289249259Sdim default: llvm_unreachable("Unknown loc info"); 1290249259Sdim case CCValAssign::Full: break; 1291249259Sdim case CCValAssign::SExt: 1292249259Sdim case CCValAssign::ZExt: 1293249259Sdim case CCValAssign::AExt: 1294249259Sdim // Floating-point values should only be extended when they're going into 1295249259Sdim // memory, which can't happen here so an integer extend is acceptable. 1296249259Sdim Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 1297249259Sdim break; 1298249259Sdim case CCValAssign::BCvt: 1299249259Sdim Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); 1300249259Sdim break; 1301249259Sdim } 1302249259Sdim 1303249259Sdim Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag); 1304249259Sdim Flag = Chain.getValue(1); 1305249259Sdim RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 1306249259Sdim } 1307249259Sdim 1308249259Sdim RetOps[0] = Chain; // Update chain. 1309249259Sdim 1310249259Sdim // Add the flag if we have it. 1311249259Sdim if (Flag.getNode()) 1312249259Sdim RetOps.push_back(Flag); 1313249259Sdim 1314249259Sdim return DAG.getNode(AArch64ISD::Ret, dl, MVT::Other, 1315249259Sdim &RetOps[0], RetOps.size()); 1316249259Sdim} 1317249259Sdim 1318249259SdimSDValue 1319249259SdimAArch64TargetLowering::LowerCall(CallLoweringInfo &CLI, 1320249259Sdim SmallVectorImpl<SDValue> &InVals) const { 1321249259Sdim SelectionDAG &DAG = CLI.DAG; 1322263508Sdim SDLoc &dl = CLI.DL; 1323263508Sdim SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; 1324263508Sdim SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; 1325263508Sdim SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; 1326249259Sdim SDValue Chain = CLI.Chain; 1327249259Sdim SDValue Callee = CLI.Callee; 1328249259Sdim bool &IsTailCall = CLI.IsTailCall; 1329249259Sdim CallingConv::ID CallConv = CLI.CallConv; 1330249259Sdim bool IsVarArg = CLI.IsVarArg; 1331249259Sdim 1332249259Sdim MachineFunction &MF = DAG.getMachineFunction(); 1333249259Sdim AArch64MachineFunctionInfo *FuncInfo 1334249259Sdim = MF.getInfo<AArch64MachineFunctionInfo>(); 1335249259Sdim bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt; 1336249259Sdim bool IsStructRet = !Outs.empty() && Outs[0].Flags.isSRet(); 1337249259Sdim bool IsSibCall = false; 1338249259Sdim 1339249259Sdim if (IsTailCall) { 1340249259Sdim IsTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, 1341249259Sdim IsVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(), 1342249259Sdim Outs, OutVals, Ins, DAG); 1343249259Sdim 1344249259Sdim // A sibling call is one where we're under the usual C ABI and not planning 1345249259Sdim // to change that but can still do a tail call: 1346249259Sdim if (!TailCallOpt && IsTailCall) 1347249259Sdim IsSibCall = true; 1348249259Sdim } 1349249259Sdim 1350249259Sdim SmallVector<CCValAssign, 16> ArgLocs; 1351249259Sdim CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), 1352249259Sdim getTargetMachine(), ArgLocs, *DAG.getContext()); 1353249259Sdim CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv)); 1354249259Sdim 1355249259Sdim // On AArch64 (and all other architectures I'm aware of) the most this has to 1356249259Sdim // do is adjust the stack pointer. 1357249259Sdim unsigned NumBytes = RoundUpToAlignment(CCInfo.getNextStackOffset(), 16); 1358249259Sdim if (IsSibCall) { 1359249259Sdim // Since we're not changing the ABI to make this a tail call, the memory 1360249259Sdim // operands are already available in the caller's incoming argument space. 1361249259Sdim NumBytes = 0; 1362249259Sdim } 1363249259Sdim 1364249259Sdim // FPDiff is the byte offset of the call's argument area from the callee's. 1365249259Sdim // Stores to callee stack arguments will be placed in FixedStackSlots offset 1366249259Sdim // by this amount for a tail call. In a sibling call it must be 0 because the 1367249259Sdim // caller will deallocate the entire stack and the callee still expects its 1368249259Sdim // arguments to begin at SP+0. Completely unused for non-tail calls. 1369249259Sdim int FPDiff = 0; 1370249259Sdim 1371249259Sdim if (IsTailCall && !IsSibCall) { 1372249259Sdim unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea(); 1373249259Sdim 1374249259Sdim // FPDiff will be negative if this tail call requires more space than we 1375249259Sdim // would automatically have in our incoming argument space. Positive if we 1376249259Sdim // can actually shrink the stack. 1377249259Sdim FPDiff = NumReusableBytes - NumBytes; 1378249259Sdim 1379249259Sdim // The stack pointer must be 16-byte aligned at all times it's used for a 1380249259Sdim // memory operation, which in practice means at *all* times and in 1381249259Sdim // particular across call boundaries. Therefore our own arguments started at 1382249259Sdim // a 16-byte aligned SP and the delta applied for the tail call should 1383249259Sdim // satisfy the same constraint. 1384249259Sdim assert(FPDiff % 16 == 0 && "unaligned stack on tail call"); 1385249259Sdim } 1386249259Sdim 1387249259Sdim if (!IsSibCall) 1388263508Sdim Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true), 1389263508Sdim dl); 1390249259Sdim 1391249259Sdim SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, AArch64::XSP, 1392249259Sdim getPointerTy()); 1393249259Sdim 1394249259Sdim SmallVector<SDValue, 8> MemOpChains; 1395249259Sdim SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 1396249259Sdim 1397249259Sdim for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1398249259Sdim CCValAssign &VA = ArgLocs[i]; 1399249259Sdim ISD::ArgFlagsTy Flags = Outs[i].Flags; 1400249259Sdim SDValue Arg = OutVals[i]; 1401249259Sdim 1402249259Sdim // Callee does the actual widening, so all extensions just use an implicit 1403249259Sdim // definition of the rest of the Loc. Aesthetically, this would be nicer as 1404249259Sdim // an ANY_EXTEND, but that isn't valid for floating-point types and this 1405249259Sdim // alternative works on integer types too. 1406249259Sdim switch (VA.getLocInfo()) { 1407249259Sdim default: llvm_unreachable("Unknown loc info!"); 1408249259Sdim case CCValAssign::Full: break; 1409249259Sdim case CCValAssign::SExt: 1410249259Sdim case CCValAssign::ZExt: 1411249259Sdim case CCValAssign::AExt: { 1412249259Sdim unsigned SrcSize = VA.getValVT().getSizeInBits(); 1413249259Sdim unsigned SrcSubReg; 1414249259Sdim 1415249259Sdim switch (SrcSize) { 1416249259Sdim case 8: SrcSubReg = AArch64::sub_8; break; 1417249259Sdim case 16: SrcSubReg = AArch64::sub_16; break; 1418249259Sdim case 32: SrcSubReg = AArch64::sub_32; break; 1419249259Sdim case 64: SrcSubReg = AArch64::sub_64; break; 1420249259Sdim default: llvm_unreachable("Unexpected argument promotion"); 1421249259Sdim } 1422249259Sdim 1423249259Sdim Arg = SDValue(DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl, 1424249259Sdim VA.getLocVT(), 1425249259Sdim DAG.getUNDEF(VA.getLocVT()), 1426249259Sdim Arg, 1427249259Sdim DAG.getTargetConstant(SrcSubReg, MVT::i32)), 1428249259Sdim 0); 1429249259Sdim 1430249259Sdim break; 1431249259Sdim } 1432249259Sdim case CCValAssign::BCvt: 1433249259Sdim Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); 1434249259Sdim break; 1435249259Sdim } 1436249259Sdim 1437249259Sdim if (VA.isRegLoc()) { 1438249259Sdim // A normal register (sub-) argument. For now we just note it down because 1439249259Sdim // we want to copy things into registers as late as possible to avoid 1440249259Sdim // register-pressure (and possibly worse). 1441249259Sdim RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 1442249259Sdim continue; 1443249259Sdim } 1444249259Sdim 1445249259Sdim assert(VA.isMemLoc() && "unexpected argument location"); 1446249259Sdim 1447249259Sdim SDValue DstAddr; 1448249259Sdim MachinePointerInfo DstInfo; 1449249259Sdim if (IsTailCall) { 1450249259Sdim uint32_t OpSize = Flags.isByVal() ? Flags.getByValSize() : 1451249259Sdim VA.getLocVT().getSizeInBits(); 1452249259Sdim OpSize = (OpSize + 7) / 8; 1453249259Sdim int32_t Offset = VA.getLocMemOffset() + FPDiff; 1454249259Sdim int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); 1455249259Sdim 1456249259Sdim DstAddr = DAG.getFrameIndex(FI, getPointerTy()); 1457249259Sdim DstInfo = MachinePointerInfo::getFixedStack(FI); 1458249259Sdim 1459249259Sdim // Make sure any stack arguments overlapping with where we're storing are 1460249259Sdim // loaded before this eventual operation. Otherwise they'll be clobbered. 1461249259Sdim Chain = addTokenForArgument(Chain, DAG, MF.getFrameInfo(), FI); 1462249259Sdim } else { 1463249259Sdim SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()); 1464249259Sdim 1465249259Sdim DstAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 1466249259Sdim DstInfo = MachinePointerInfo::getStack(VA.getLocMemOffset()); 1467249259Sdim } 1468249259Sdim 1469249259Sdim if (Flags.isByVal()) { 1470249259Sdim SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i64); 1471249259Sdim SDValue Cpy = DAG.getMemcpy(Chain, dl, DstAddr, Arg, SizeNode, 1472249259Sdim Flags.getByValAlign(), 1473249259Sdim /*isVolatile = */ false, 1474249259Sdim /*alwaysInline = */ false, 1475249259Sdim DstInfo, MachinePointerInfo(0)); 1476249259Sdim MemOpChains.push_back(Cpy); 1477249259Sdim } else { 1478249259Sdim // Normal stack argument, put it where it's needed. 1479249259Sdim SDValue Store = DAG.getStore(Chain, dl, Arg, DstAddr, DstInfo, 1480249259Sdim false, false, 0); 1481249259Sdim MemOpChains.push_back(Store); 1482249259Sdim } 1483249259Sdim } 1484249259Sdim 1485249259Sdim // The loads and stores generated above shouldn't clash with each 1486249259Sdim // other. Combining them with this TokenFactor notes that fact for the rest of 1487249259Sdim // the backend. 1488249259Sdim if (!MemOpChains.empty()) 1489249259Sdim Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1490249259Sdim &MemOpChains[0], MemOpChains.size()); 1491249259Sdim 1492249259Sdim // Most of the rest of the instructions need to be glued together; we don't 1493249259Sdim // want assignments to actual registers used by a call to be rearranged by a 1494249259Sdim // well-meaning scheduler. 1495249259Sdim SDValue InFlag; 1496249259Sdim 1497249259Sdim for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1498249259Sdim Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 1499249259Sdim RegsToPass[i].second, InFlag); 1500249259Sdim InFlag = Chain.getValue(1); 1501249259Sdim } 1502249259Sdim 1503249259Sdim // The linker is responsible for inserting veneers when necessary to put a 1504249259Sdim // function call destination in range, so we don't need to bother with a 1505249259Sdim // wrapper here. 1506249259Sdim if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 1507249259Sdim const GlobalValue *GV = G->getGlobal(); 1508249259Sdim Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy()); 1509249259Sdim } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 1510249259Sdim const char *Sym = S->getSymbol(); 1511249259Sdim Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy()); 1512249259Sdim } 1513249259Sdim 1514249259Sdim // We don't usually want to end the call-sequence here because we would tidy 1515249259Sdim // the frame up *after* the call, however in the ABI-changing tail-call case 1516249259Sdim // we've carefully laid out the parameters so that when sp is reset they'll be 1517249259Sdim // in the correct location. 1518249259Sdim if (IsTailCall && !IsSibCall) { 1519249259Sdim Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 1520263508Sdim DAG.getIntPtrConstant(0, true), InFlag, dl); 1521249259Sdim InFlag = Chain.getValue(1); 1522249259Sdim } 1523249259Sdim 1524249259Sdim // We produce the following DAG scheme for the actual call instruction: 1525249259Sdim // (AArch64Call Chain, Callee, reg1, ..., regn, preserveMask, inflag? 1526249259Sdim // 1527249259Sdim // Most arguments aren't going to be used and just keep the values live as 1528249259Sdim // far as LLVM is concerned. It's expected to be selected as simply "bl 1529249259Sdim // callee" (for a direct, non-tail call). 1530249259Sdim std::vector<SDValue> Ops; 1531249259Sdim Ops.push_back(Chain); 1532249259Sdim Ops.push_back(Callee); 1533249259Sdim 1534249259Sdim if (IsTailCall) { 1535249259Sdim // Each tail call may have to adjust the stack by a different amount, so 1536249259Sdim // this information must travel along with the operation for eventual 1537249259Sdim // consumption by emitEpilogue. 1538249259Sdim Ops.push_back(DAG.getTargetConstant(FPDiff, MVT::i32)); 1539249259Sdim } 1540249259Sdim 1541249259Sdim for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1542249259Sdim Ops.push_back(DAG.getRegister(RegsToPass[i].first, 1543249259Sdim RegsToPass[i].second.getValueType())); 1544249259Sdim 1545249259Sdim 1546249259Sdim // Add a register mask operand representing the call-preserved registers. This 1547249259Sdim // is used later in codegen to constrain register-allocation. 1548249259Sdim const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 1549249259Sdim const uint32_t *Mask = TRI->getCallPreservedMask(CallConv); 1550249259Sdim assert(Mask && "Missing call preserved mask for calling convention"); 1551249259Sdim Ops.push_back(DAG.getRegisterMask(Mask)); 1552249259Sdim 1553249259Sdim // If we needed glue, put it in as the last argument. 1554249259Sdim if (InFlag.getNode()) 1555249259Sdim Ops.push_back(InFlag); 1556249259Sdim 1557249259Sdim SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 1558249259Sdim 1559249259Sdim if (IsTailCall) { 1560249259Sdim return DAG.getNode(AArch64ISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size()); 1561249259Sdim } 1562249259Sdim 1563249259Sdim Chain = DAG.getNode(AArch64ISD::Call, dl, NodeTys, &Ops[0], Ops.size()); 1564249259Sdim InFlag = Chain.getValue(1); 1565249259Sdim 1566249259Sdim // Now we can reclaim the stack, just as well do it before working out where 1567249259Sdim // our return value is. 1568249259Sdim if (!IsSibCall) { 1569249259Sdim uint64_t CalleePopBytes 1570249259Sdim = DoesCalleeRestoreStack(CallConv, TailCallOpt) ? NumBytes : 0; 1571249259Sdim 1572249259Sdim Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 1573249259Sdim DAG.getIntPtrConstant(CalleePopBytes, true), 1574263508Sdim InFlag, dl); 1575249259Sdim InFlag = Chain.getValue(1); 1576249259Sdim } 1577249259Sdim 1578249259Sdim return LowerCallResult(Chain, InFlag, CallConv, 1579249259Sdim IsVarArg, Ins, dl, DAG, InVals); 1580249259Sdim} 1581249259Sdim 1582249259SdimSDValue 1583249259SdimAArch64TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1584249259Sdim CallingConv::ID CallConv, bool IsVarArg, 1585249259Sdim const SmallVectorImpl<ISD::InputArg> &Ins, 1586263508Sdim SDLoc dl, SelectionDAG &DAG, 1587249259Sdim SmallVectorImpl<SDValue> &InVals) const { 1588249259Sdim // Assign locations to each value returned by this call. 1589249259Sdim SmallVector<CCValAssign, 16> RVLocs; 1590249259Sdim CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), 1591249259Sdim getTargetMachine(), RVLocs, *DAG.getContext()); 1592249259Sdim CCInfo.AnalyzeCallResult(Ins, CCAssignFnForNode(CallConv)); 1593249259Sdim 1594249259Sdim for (unsigned i = 0; i != RVLocs.size(); ++i) { 1595249259Sdim CCValAssign VA = RVLocs[i]; 1596249259Sdim 1597249259Sdim // Return values that are too big to fit into registers should use an sret 1598249259Sdim // pointer, so this can be a lot simpler than the main argument code. 1599249259Sdim assert(VA.isRegLoc() && "Memory locations not expected for call return"); 1600249259Sdim 1601249259Sdim SDValue Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(), 1602249259Sdim InFlag); 1603249259Sdim Chain = Val.getValue(1); 1604249259Sdim InFlag = Val.getValue(2); 1605249259Sdim 1606249259Sdim switch (VA.getLocInfo()) { 1607249259Sdim default: llvm_unreachable("Unknown loc info!"); 1608249259Sdim case CCValAssign::Full: break; 1609249259Sdim case CCValAssign::BCvt: 1610249259Sdim Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val); 1611249259Sdim break; 1612249259Sdim case CCValAssign::ZExt: 1613249259Sdim case CCValAssign::SExt: 1614249259Sdim case CCValAssign::AExt: 1615249259Sdim // Floating-point arguments only get extended/truncated if they're going 1616249259Sdim // in memory, so using the integer operation is acceptable here. 1617249259Sdim Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val); 1618249259Sdim break; 1619249259Sdim } 1620249259Sdim 1621249259Sdim InVals.push_back(Val); 1622249259Sdim } 1623249259Sdim 1624249259Sdim return Chain; 1625249259Sdim} 1626249259Sdim 1627249259Sdimbool 1628249259SdimAArch64TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 1629249259Sdim CallingConv::ID CalleeCC, 1630249259Sdim bool IsVarArg, 1631249259Sdim bool IsCalleeStructRet, 1632249259Sdim bool IsCallerStructRet, 1633249259Sdim const SmallVectorImpl<ISD::OutputArg> &Outs, 1634249259Sdim const SmallVectorImpl<SDValue> &OutVals, 1635249259Sdim const SmallVectorImpl<ISD::InputArg> &Ins, 1636249259Sdim SelectionDAG& DAG) const { 1637249259Sdim 1638249259Sdim // For CallingConv::C this function knows whether the ABI needs 1639249259Sdim // changing. That's not true for other conventions so they will have to opt in 1640249259Sdim // manually. 1641249259Sdim if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C) 1642249259Sdim return false; 1643249259Sdim 1644249259Sdim const MachineFunction &MF = DAG.getMachineFunction(); 1645249259Sdim const Function *CallerF = MF.getFunction(); 1646249259Sdim CallingConv::ID CallerCC = CallerF->getCallingConv(); 1647249259Sdim bool CCMatch = CallerCC == CalleeCC; 1648249259Sdim 1649249259Sdim // Byval parameters hand the function a pointer directly into the stack area 1650249259Sdim // we want to reuse during a tail call. Working around this *is* possible (see 1651249259Sdim // X86) but less efficient and uglier in LowerCall. 1652249259Sdim for (Function::const_arg_iterator i = CallerF->arg_begin(), 1653249259Sdim e = CallerF->arg_end(); i != e; ++i) 1654249259Sdim if (i->hasByValAttr()) 1655249259Sdim return false; 1656249259Sdim 1657249259Sdim if (getTargetMachine().Options.GuaranteedTailCallOpt) { 1658249259Sdim if (IsTailCallConvention(CalleeCC) && CCMatch) 1659249259Sdim return true; 1660249259Sdim return false; 1661249259Sdim } 1662249259Sdim 1663249259Sdim // Now we search for cases where we can use a tail call without changing the 1664249259Sdim // ABI. Sibcall is used in some places (particularly gcc) to refer to this 1665249259Sdim // concept. 1666249259Sdim 1667249259Sdim // I want anyone implementing a new calling convention to think long and hard 1668249259Sdim // about this assert. 1669249259Sdim assert((!IsVarArg || CalleeCC == CallingConv::C) 1670249259Sdim && "Unexpected variadic calling convention"); 1671249259Sdim 1672249259Sdim if (IsVarArg && !Outs.empty()) { 1673249259Sdim // At least two cases here: if caller is fastcc then we can't have any 1674249259Sdim // memory arguments (we'd be expected to clean up the stack afterwards). If 1675249259Sdim // caller is C then we could potentially use its argument area. 1676249259Sdim 1677249259Sdim // FIXME: for now we take the most conservative of these in both cases: 1678249259Sdim // disallow all variadic memory operands. 1679249259Sdim SmallVector<CCValAssign, 16> ArgLocs; 1680249259Sdim CCState CCInfo(CalleeCC, IsVarArg, DAG.getMachineFunction(), 1681249259Sdim getTargetMachine(), ArgLocs, *DAG.getContext()); 1682249259Sdim 1683249259Sdim CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CalleeCC)); 1684249259Sdim for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) 1685249259Sdim if (!ArgLocs[i].isRegLoc()) 1686249259Sdim return false; 1687249259Sdim } 1688249259Sdim 1689249259Sdim // If the calling conventions do not match, then we'd better make sure the 1690249259Sdim // results are returned in the same way as what the caller expects. 1691249259Sdim if (!CCMatch) { 1692249259Sdim SmallVector<CCValAssign, 16> RVLocs1; 1693249259Sdim CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), 1694249259Sdim getTargetMachine(), RVLocs1, *DAG.getContext()); 1695249259Sdim CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC)); 1696249259Sdim 1697249259Sdim SmallVector<CCValAssign, 16> RVLocs2; 1698249259Sdim CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), 1699249259Sdim getTargetMachine(), RVLocs2, *DAG.getContext()); 1700249259Sdim CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC)); 1701249259Sdim 1702249259Sdim if (RVLocs1.size() != RVLocs2.size()) 1703249259Sdim return false; 1704249259Sdim for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) { 1705249259Sdim if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) 1706249259Sdim return false; 1707249259Sdim if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo()) 1708249259Sdim return false; 1709249259Sdim if (RVLocs1[i].isRegLoc()) { 1710249259Sdim if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) 1711249259Sdim return false; 1712249259Sdim } else { 1713249259Sdim if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset()) 1714249259Sdim return false; 1715249259Sdim } 1716249259Sdim } 1717249259Sdim } 1718249259Sdim 1719249259Sdim // Nothing more to check if the callee is taking no arguments 1720249259Sdim if (Outs.empty()) 1721249259Sdim return true; 1722249259Sdim 1723249259Sdim SmallVector<CCValAssign, 16> ArgLocs; 1724249259Sdim CCState CCInfo(CalleeCC, IsVarArg, DAG.getMachineFunction(), 1725249259Sdim getTargetMachine(), ArgLocs, *DAG.getContext()); 1726249259Sdim 1727249259Sdim CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CalleeCC)); 1728249259Sdim 1729249259Sdim const AArch64MachineFunctionInfo *FuncInfo 1730249259Sdim = MF.getInfo<AArch64MachineFunctionInfo>(); 1731249259Sdim 1732249259Sdim // If the stack arguments for this call would fit into our own save area then 1733249259Sdim // the call can be made tail. 1734249259Sdim return CCInfo.getNextStackOffset() <= FuncInfo->getBytesInStackArgArea(); 1735249259Sdim} 1736249259Sdim 1737249259Sdimbool AArch64TargetLowering::DoesCalleeRestoreStack(CallingConv::ID CallCC, 1738249259Sdim bool TailCallOpt) const { 1739249259Sdim return CallCC == CallingConv::Fast && TailCallOpt; 1740249259Sdim} 1741249259Sdim 1742249259Sdimbool AArch64TargetLowering::IsTailCallConvention(CallingConv::ID CallCC) const { 1743249259Sdim return CallCC == CallingConv::Fast; 1744249259Sdim} 1745249259Sdim 1746249259SdimSDValue AArch64TargetLowering::addTokenForArgument(SDValue Chain, 1747249259Sdim SelectionDAG &DAG, 1748249259Sdim MachineFrameInfo *MFI, 1749249259Sdim int ClobberedFI) const { 1750249259Sdim SmallVector<SDValue, 8> ArgChains; 1751249259Sdim int64_t FirstByte = MFI->getObjectOffset(ClobberedFI); 1752249259Sdim int64_t LastByte = FirstByte + MFI->getObjectSize(ClobberedFI) - 1; 1753249259Sdim 1754249259Sdim // Include the original chain at the beginning of the list. When this is 1755249259Sdim // used by target LowerCall hooks, this helps legalize find the 1756249259Sdim // CALLSEQ_BEGIN node. 1757249259Sdim ArgChains.push_back(Chain); 1758249259Sdim 1759249259Sdim // Add a chain value for each stack argument corresponding 1760249259Sdim for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(), 1761249259Sdim UE = DAG.getEntryNode().getNode()->use_end(); U != UE; ++U) 1762249259Sdim if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U)) 1763249259Sdim if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr())) 1764249259Sdim if (FI->getIndex() < 0) { 1765249259Sdim int64_t InFirstByte = MFI->getObjectOffset(FI->getIndex()); 1766249259Sdim int64_t InLastByte = InFirstByte; 1767249259Sdim InLastByte += MFI->getObjectSize(FI->getIndex()) - 1; 1768249259Sdim 1769249259Sdim if ((InFirstByte <= FirstByte && FirstByte <= InLastByte) || 1770249259Sdim (FirstByte <= InFirstByte && InFirstByte <= LastByte)) 1771249259Sdim ArgChains.push_back(SDValue(L, 1)); 1772249259Sdim } 1773249259Sdim 1774249259Sdim // Build a tokenfactor for all the chains. 1775263508Sdim return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, 1776249259Sdim &ArgChains[0], ArgChains.size()); 1777249259Sdim} 1778249259Sdim 1779249259Sdimstatic A64CC::CondCodes IntCCToA64CC(ISD::CondCode CC) { 1780249259Sdim switch (CC) { 1781249259Sdim case ISD::SETEQ: return A64CC::EQ; 1782249259Sdim case ISD::SETGT: return A64CC::GT; 1783249259Sdim case ISD::SETGE: return A64CC::GE; 1784249259Sdim case ISD::SETLT: return A64CC::LT; 1785249259Sdim case ISD::SETLE: return A64CC::LE; 1786249259Sdim case ISD::SETNE: return A64CC::NE; 1787249259Sdim case ISD::SETUGT: return A64CC::HI; 1788249259Sdim case ISD::SETUGE: return A64CC::HS; 1789249259Sdim case ISD::SETULT: return A64CC::LO; 1790249259Sdim case ISD::SETULE: return A64CC::LS; 1791249259Sdim default: llvm_unreachable("Unexpected condition code"); 1792249259Sdim } 1793249259Sdim} 1794249259Sdim 1795249259Sdimbool AArch64TargetLowering::isLegalICmpImmediate(int64_t Val) const { 1796249259Sdim // icmp is implemented using adds/subs immediate, which take an unsigned 1797249259Sdim // 12-bit immediate, optionally shifted left by 12 bits. 1798249259Sdim 1799249259Sdim // Symmetric by using adds/subs 1800249259Sdim if (Val < 0) 1801249259Sdim Val = -Val; 1802249259Sdim 1803249259Sdim return (Val & ~0xfff) == 0 || (Val & ~0xfff000) == 0; 1804249259Sdim} 1805249259Sdim 1806249259SdimSDValue AArch64TargetLowering::getSelectableIntSetCC(SDValue LHS, SDValue RHS, 1807249259Sdim ISD::CondCode CC, SDValue &A64cc, 1808263508Sdim SelectionDAG &DAG, SDLoc &dl) const { 1809249259Sdim if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) { 1810249259Sdim int64_t C = 0; 1811249259Sdim EVT VT = RHSC->getValueType(0); 1812249259Sdim bool knownInvalid = false; 1813249259Sdim 1814249259Sdim // I'm not convinced the rest of LLVM handles these edge cases properly, but 1815249259Sdim // we can at least get it right. 1816249259Sdim if (isSignedIntSetCC(CC)) { 1817249259Sdim C = RHSC->getSExtValue(); 1818249259Sdim } else if (RHSC->getZExtValue() > INT64_MAX) { 1819249259Sdim // A 64-bit constant not representable by a signed 64-bit integer is far 1820249259Sdim // too big to fit into a SUBS immediate anyway. 1821249259Sdim knownInvalid = true; 1822249259Sdim } else { 1823249259Sdim C = RHSC->getZExtValue(); 1824249259Sdim } 1825249259Sdim 1826249259Sdim if (!knownInvalid && !isLegalICmpImmediate(C)) { 1827249259Sdim // Constant does not fit, try adjusting it by one? 1828249259Sdim switch (CC) { 1829249259Sdim default: break; 1830249259Sdim case ISD::SETLT: 1831249259Sdim case ISD::SETGE: 1832249259Sdim if (isLegalICmpImmediate(C-1)) { 1833249259Sdim CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT; 1834249259Sdim RHS = DAG.getConstant(C-1, VT); 1835249259Sdim } 1836249259Sdim break; 1837249259Sdim case ISD::SETULT: 1838249259Sdim case ISD::SETUGE: 1839249259Sdim if (isLegalICmpImmediate(C-1)) { 1840249259Sdim CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT; 1841249259Sdim RHS = DAG.getConstant(C-1, VT); 1842249259Sdim } 1843249259Sdim break; 1844249259Sdim case ISD::SETLE: 1845249259Sdim case ISD::SETGT: 1846249259Sdim if (isLegalICmpImmediate(C+1)) { 1847249259Sdim CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE; 1848249259Sdim RHS = DAG.getConstant(C+1, VT); 1849249259Sdim } 1850249259Sdim break; 1851249259Sdim case ISD::SETULE: 1852249259Sdim case ISD::SETUGT: 1853249259Sdim if (isLegalICmpImmediate(C+1)) { 1854249259Sdim CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; 1855249259Sdim RHS = DAG.getConstant(C+1, VT); 1856249259Sdim } 1857249259Sdim break; 1858249259Sdim } 1859249259Sdim } 1860249259Sdim } 1861249259Sdim 1862249259Sdim A64CC::CondCodes CondCode = IntCCToA64CC(CC); 1863249259Sdim A64cc = DAG.getConstant(CondCode, MVT::i32); 1864249259Sdim return DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, LHS, RHS, 1865249259Sdim DAG.getCondCode(CC)); 1866249259Sdim} 1867249259Sdim 1868249259Sdimstatic A64CC::CondCodes FPCCToA64CC(ISD::CondCode CC, 1869249259Sdim A64CC::CondCodes &Alternative) { 1870249259Sdim A64CC::CondCodes CondCode = A64CC::Invalid; 1871249259Sdim Alternative = A64CC::Invalid; 1872249259Sdim 1873249259Sdim switch (CC) { 1874249259Sdim default: llvm_unreachable("Unknown FP condition!"); 1875249259Sdim case ISD::SETEQ: 1876249259Sdim case ISD::SETOEQ: CondCode = A64CC::EQ; break; 1877249259Sdim case ISD::SETGT: 1878249259Sdim case ISD::SETOGT: CondCode = A64CC::GT; break; 1879249259Sdim case ISD::SETGE: 1880249259Sdim case ISD::SETOGE: CondCode = A64CC::GE; break; 1881249259Sdim case ISD::SETOLT: CondCode = A64CC::MI; break; 1882249259Sdim case ISD::SETOLE: CondCode = A64CC::LS; break; 1883249259Sdim case ISD::SETONE: CondCode = A64CC::MI; Alternative = A64CC::GT; break; 1884249259Sdim case ISD::SETO: CondCode = A64CC::VC; break; 1885249259Sdim case ISD::SETUO: CondCode = A64CC::VS; break; 1886249259Sdim case ISD::SETUEQ: CondCode = A64CC::EQ; Alternative = A64CC::VS; break; 1887249259Sdim case ISD::SETUGT: CondCode = A64CC::HI; break; 1888249259Sdim case ISD::SETUGE: CondCode = A64CC::PL; break; 1889249259Sdim case ISD::SETLT: 1890249259Sdim case ISD::SETULT: CondCode = A64CC::LT; break; 1891249259Sdim case ISD::SETLE: 1892249259Sdim case ISD::SETULE: CondCode = A64CC::LE; break; 1893249259Sdim case ISD::SETNE: 1894249259Sdim case ISD::SETUNE: CondCode = A64CC::NE; break; 1895249259Sdim } 1896249259Sdim return CondCode; 1897249259Sdim} 1898249259Sdim 1899249259SdimSDValue 1900249259SdimAArch64TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const { 1901263508Sdim SDLoc DL(Op); 1902249259Sdim EVT PtrVT = getPointerTy(); 1903249259Sdim const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 1904249259Sdim 1905251662Sdim switch(getTargetMachine().getCodeModel()) { 1906251662Sdim case CodeModel::Small: 1907251662Sdim // The most efficient code is PC-relative anyway for the small memory model, 1908251662Sdim // so we don't need to worry about relocation model. 1909251662Sdim return DAG.getNode(AArch64ISD::WrapperSmall, DL, PtrVT, 1910251662Sdim DAG.getTargetBlockAddress(BA, PtrVT, 0, 1911251662Sdim AArch64II::MO_NO_FLAG), 1912251662Sdim DAG.getTargetBlockAddress(BA, PtrVT, 0, 1913251662Sdim AArch64II::MO_LO12), 1914251662Sdim DAG.getConstant(/*Alignment=*/ 4, MVT::i32)); 1915251662Sdim case CodeModel::Large: 1916251662Sdim return DAG.getNode( 1917251662Sdim AArch64ISD::WrapperLarge, DL, PtrVT, 1918251662Sdim DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_ABS_G3), 1919251662Sdim DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_ABS_G2_NC), 1920251662Sdim DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_ABS_G1_NC), 1921251662Sdim DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_ABS_G0_NC)); 1922251662Sdim default: 1923251662Sdim llvm_unreachable("Only small and large code models supported now"); 1924251662Sdim } 1925249259Sdim} 1926249259Sdim 1927249259Sdim 1928249259Sdim// (BRCOND chain, val, dest) 1929249259SdimSDValue 1930249259SdimAArch64TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 1931263508Sdim SDLoc dl(Op); 1932249259Sdim SDValue Chain = Op.getOperand(0); 1933249259Sdim SDValue TheBit = Op.getOperand(1); 1934249259Sdim SDValue DestBB = Op.getOperand(2); 1935249259Sdim 1936249259Sdim // AArch64 BooleanContents is the default UndefinedBooleanContent, which means 1937249259Sdim // that as the consumer we are responsible for ignoring rubbish in higher 1938249259Sdim // bits. 1939249259Sdim TheBit = DAG.getNode(ISD::AND, dl, MVT::i32, TheBit, 1940249259Sdim DAG.getConstant(1, MVT::i32)); 1941249259Sdim 1942249259Sdim SDValue A64CMP = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, TheBit, 1943249259Sdim DAG.getConstant(0, TheBit.getValueType()), 1944249259Sdim DAG.getCondCode(ISD::SETNE)); 1945249259Sdim 1946249259Sdim return DAG.getNode(AArch64ISD::BR_CC, dl, MVT::Other, Chain, 1947249259Sdim A64CMP, DAG.getConstant(A64CC::NE, MVT::i32), 1948249259Sdim DestBB); 1949249259Sdim} 1950249259Sdim 1951249259Sdim// (BR_CC chain, condcode, lhs, rhs, dest) 1952249259SdimSDValue 1953249259SdimAArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const { 1954263508Sdim SDLoc dl(Op); 1955249259Sdim SDValue Chain = Op.getOperand(0); 1956249259Sdim ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 1957249259Sdim SDValue LHS = Op.getOperand(2); 1958249259Sdim SDValue RHS = Op.getOperand(3); 1959249259Sdim SDValue DestBB = Op.getOperand(4); 1960249259Sdim 1961249259Sdim if (LHS.getValueType() == MVT::f128) { 1962249259Sdim // f128 comparisons are lowered to runtime calls by a routine which sets 1963249259Sdim // LHS, RHS and CC appropriately for the rest of this function to continue. 1964249259Sdim softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl); 1965249259Sdim 1966249259Sdim // If softenSetCCOperands returned a scalar, we need to compare the result 1967249259Sdim // against zero to select between true and false values. 1968249259Sdim if (RHS.getNode() == 0) { 1969249259Sdim RHS = DAG.getConstant(0, LHS.getValueType()); 1970249259Sdim CC = ISD::SETNE; 1971249259Sdim } 1972249259Sdim } 1973249259Sdim 1974249259Sdim if (LHS.getValueType().isInteger()) { 1975249259Sdim SDValue A64cc; 1976249259Sdim 1977249259Sdim // Integers are handled in a separate function because the combinations of 1978249259Sdim // immediates and tests can get hairy and we may want to fiddle things. 1979249259Sdim SDValue CmpOp = getSelectableIntSetCC(LHS, RHS, CC, A64cc, DAG, dl); 1980249259Sdim 1981249259Sdim return DAG.getNode(AArch64ISD::BR_CC, dl, MVT::Other, 1982249259Sdim Chain, CmpOp, A64cc, DestBB); 1983249259Sdim } 1984249259Sdim 1985249259Sdim // Note that some LLVM floating-point CondCodes can't be lowered to a single 1986249259Sdim // conditional branch, hence FPCCToA64CC can set a second test, where either 1987249259Sdim // passing is sufficient. 1988249259Sdim A64CC::CondCodes CondCode, Alternative = A64CC::Invalid; 1989249259Sdim CondCode = FPCCToA64CC(CC, Alternative); 1990249259Sdim SDValue A64cc = DAG.getConstant(CondCode, MVT::i32); 1991249259Sdim SDValue SetCC = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, LHS, RHS, 1992249259Sdim DAG.getCondCode(CC)); 1993249259Sdim SDValue A64BR_CC = DAG.getNode(AArch64ISD::BR_CC, dl, MVT::Other, 1994249259Sdim Chain, SetCC, A64cc, DestBB); 1995249259Sdim 1996249259Sdim if (Alternative != A64CC::Invalid) { 1997249259Sdim A64cc = DAG.getConstant(Alternative, MVT::i32); 1998249259Sdim A64BR_CC = DAG.getNode(AArch64ISD::BR_CC, dl, MVT::Other, 1999249259Sdim A64BR_CC, SetCC, A64cc, DestBB); 2000249259Sdim 2001249259Sdim } 2002249259Sdim 2003249259Sdim return A64BR_CC; 2004249259Sdim} 2005249259Sdim 2006249259SdimSDValue 2007249259SdimAArch64TargetLowering::LowerF128ToCall(SDValue Op, SelectionDAG &DAG, 2008249259Sdim RTLIB::Libcall Call) const { 2009249259Sdim ArgListTy Args; 2010249259Sdim ArgListEntry Entry; 2011249259Sdim for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) { 2012249259Sdim EVT ArgVT = Op.getOperand(i).getValueType(); 2013249259Sdim Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 2014249259Sdim Entry.Node = Op.getOperand(i); Entry.Ty = ArgTy; 2015249259Sdim Entry.isSExt = false; 2016249259Sdim Entry.isZExt = false; 2017249259Sdim Args.push_back(Entry); 2018249259Sdim } 2019249259Sdim SDValue Callee = DAG.getExternalSymbol(getLibcallName(Call), getPointerTy()); 2020249259Sdim 2021249259Sdim Type *RetTy = Op.getValueType().getTypeForEVT(*DAG.getContext()); 2022249259Sdim 2023249259Sdim // By default, the input chain to this libcall is the entry node of the 2024249259Sdim // function. If the libcall is going to be emitted as a tail call then 2025249259Sdim // isUsedByReturnOnly will change it to the right chain if the return 2026249259Sdim // node which is being folded has a non-entry input chain. 2027249259Sdim SDValue InChain = DAG.getEntryNode(); 2028249259Sdim 2029249259Sdim // isTailCall may be true since the callee does not reference caller stack 2030249259Sdim // frame. Check if it's in the right position. 2031249259Sdim SDValue TCChain = InChain; 2032249259Sdim bool isTailCall = isInTailCallPosition(DAG, Op.getNode(), TCChain); 2033249259Sdim if (isTailCall) 2034249259Sdim InChain = TCChain; 2035249259Sdim 2036249259Sdim TargetLowering:: 2037249259Sdim CallLoweringInfo CLI(InChain, RetTy, false, false, false, false, 2038249259Sdim 0, getLibcallCallingConv(Call), isTailCall, 2039249259Sdim /*doesNotReturn=*/false, /*isReturnValueUsed=*/true, 2040263508Sdim Callee, Args, DAG, SDLoc(Op)); 2041249259Sdim std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI); 2042249259Sdim 2043249259Sdim if (!CallInfo.second.getNode()) 2044249259Sdim // It's a tailcall, return the chain (which is the DAG root). 2045249259Sdim return DAG.getRoot(); 2046249259Sdim 2047249259Sdim return CallInfo.first; 2048249259Sdim} 2049249259Sdim 2050249259SdimSDValue 2051249259SdimAArch64TargetLowering::LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const { 2052249259Sdim if (Op.getOperand(0).getValueType() != MVT::f128) { 2053249259Sdim // It's legal except when f128 is involved 2054249259Sdim return Op; 2055249259Sdim } 2056249259Sdim 2057249259Sdim RTLIB::Libcall LC; 2058249259Sdim LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType()); 2059249259Sdim 2060249259Sdim SDValue SrcVal = Op.getOperand(0); 2061249259Sdim return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1, 2062263508Sdim /*isSigned*/ false, SDLoc(Op)).first; 2063249259Sdim} 2064249259Sdim 2065249259SdimSDValue 2066249259SdimAArch64TargetLowering::LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const { 2067249259Sdim assert(Op.getValueType() == MVT::f128 && "Unexpected lowering"); 2068249259Sdim 2069249259Sdim RTLIB::Libcall LC; 2070249259Sdim LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType()); 2071249259Sdim 2072249259Sdim return LowerF128ToCall(Op, DAG, LC); 2073249259Sdim} 2074249259Sdim 2075249259SdimSDValue 2076249259SdimAArch64TargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, 2077249259Sdim bool IsSigned) const { 2078249259Sdim if (Op.getOperand(0).getValueType() != MVT::f128) { 2079249259Sdim // It's legal except when f128 is involved 2080249259Sdim return Op; 2081249259Sdim } 2082249259Sdim 2083249259Sdim RTLIB::Libcall LC; 2084249259Sdim if (IsSigned) 2085249259Sdim LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(), Op.getValueType()); 2086249259Sdim else 2087249259Sdim LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(), Op.getValueType()); 2088249259Sdim 2089249259Sdim return LowerF128ToCall(Op, DAG, LC); 2090249259Sdim} 2091249259Sdim 2092263508SdimSDValue AArch64TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{ 2093263508Sdim MachineFunction &MF = DAG.getMachineFunction(); 2094263508Sdim MachineFrameInfo *MFI = MF.getFrameInfo(); 2095263508Sdim MFI->setReturnAddressIsTaken(true); 2096263508Sdim 2097263508Sdim EVT VT = Op.getValueType(); 2098263508Sdim SDLoc dl(Op); 2099263508Sdim unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 2100263508Sdim if (Depth) { 2101263508Sdim SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 2102263508Sdim SDValue Offset = DAG.getConstant(8, MVT::i64); 2103263508Sdim return DAG.getLoad(VT, dl, DAG.getEntryNode(), 2104263508Sdim DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset), 2105263508Sdim MachinePointerInfo(), false, false, false, 0); 2106263508Sdim } 2107263508Sdim 2108263508Sdim // Return X30, which contains the return address. Mark it an implicit live-in. 2109263508Sdim unsigned Reg = MF.addLiveIn(AArch64::X30, getRegClassFor(MVT::i64)); 2110263508Sdim return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, MVT::i64); 2111263508Sdim} 2112263508Sdim 2113263508Sdim 2114263508SdimSDValue AArch64TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) 2115263508Sdim const { 2116263508Sdim MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2117263508Sdim MFI->setFrameAddressIsTaken(true); 2118263508Sdim 2119263508Sdim EVT VT = Op.getValueType(); 2120263508Sdim SDLoc dl(Op); 2121263508Sdim unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 2122263508Sdim unsigned FrameReg = AArch64::X29; 2123263508Sdim SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 2124263508Sdim while (Depth--) 2125263508Sdim FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, 2126263508Sdim MachinePointerInfo(), 2127263508Sdim false, false, false, 0); 2128263508Sdim return FrameAddr; 2129263508Sdim} 2130263508Sdim 2131249259SdimSDValue 2132251662SdimAArch64TargetLowering::LowerGlobalAddressELFLarge(SDValue Op, 2133251662Sdim SelectionDAG &DAG) const { 2134251662Sdim assert(getTargetMachine().getCodeModel() == CodeModel::Large); 2135251662Sdim assert(getTargetMachine().getRelocationModel() == Reloc::Static); 2136249259Sdim 2137251662Sdim EVT PtrVT = getPointerTy(); 2138263508Sdim SDLoc dl(Op); 2139251662Sdim const GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Op); 2140251662Sdim const GlobalValue *GV = GN->getGlobal(); 2141251662Sdim 2142251662Sdim SDValue GlobalAddr = DAG.getNode( 2143251662Sdim AArch64ISD::WrapperLarge, dl, PtrVT, 2144251662Sdim DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, AArch64II::MO_ABS_G3), 2145251662Sdim DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, AArch64II::MO_ABS_G2_NC), 2146251662Sdim DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, AArch64II::MO_ABS_G1_NC), 2147251662Sdim DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, AArch64II::MO_ABS_G0_NC)); 2148251662Sdim 2149251662Sdim if (GN->getOffset() != 0) 2150251662Sdim return DAG.getNode(ISD::ADD, dl, PtrVT, GlobalAddr, 2151251662Sdim DAG.getConstant(GN->getOffset(), PtrVT)); 2152251662Sdim 2153251662Sdim return GlobalAddr; 2154251662Sdim} 2155251662Sdim 2156251662SdimSDValue 2157251662SdimAArch64TargetLowering::LowerGlobalAddressELFSmall(SDValue Op, 2158251662Sdim SelectionDAG &DAG) const { 2159249259Sdim assert(getTargetMachine().getCodeModel() == CodeModel::Small); 2160249259Sdim 2161249259Sdim EVT PtrVT = getPointerTy(); 2162263508Sdim SDLoc dl(Op); 2163249259Sdim const GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Op); 2164249259Sdim const GlobalValue *GV = GN->getGlobal(); 2165249259Sdim unsigned Alignment = GV->getAlignment(); 2166249259Sdim Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 2167249259Sdim if (GV->isWeakForLinker() && GV->isDeclaration() && RelocM == Reloc::Static) { 2168249259Sdim // Weak undefined symbols can't use ADRP/ADD pair since they should evaluate 2169249259Sdim // to zero when they remain undefined. In PIC mode the GOT can take care of 2170249259Sdim // this, but in absolute mode we use a constant pool load. 2171249259Sdim SDValue PoolAddr; 2172249259Sdim PoolAddr = DAG.getNode(AArch64ISD::WrapperSmall, dl, PtrVT, 2173249259Sdim DAG.getTargetConstantPool(GV, PtrVT, 0, 0, 2174249259Sdim AArch64II::MO_NO_FLAG), 2175249259Sdim DAG.getTargetConstantPool(GV, PtrVT, 0, 0, 2176249259Sdim AArch64II::MO_LO12), 2177249259Sdim DAG.getConstant(8, MVT::i32)); 2178249259Sdim SDValue GlobalAddr = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), PoolAddr, 2179249259Sdim MachinePointerInfo::getConstantPool(), 2180249259Sdim /*isVolatile=*/ false, 2181249259Sdim /*isNonTemporal=*/ true, 2182249259Sdim /*isInvariant=*/ true, 8); 2183249259Sdim if (GN->getOffset() != 0) 2184249259Sdim return DAG.getNode(ISD::ADD, dl, PtrVT, GlobalAddr, 2185249259Sdim DAG.getConstant(GN->getOffset(), PtrVT)); 2186249259Sdim 2187249259Sdim return GlobalAddr; 2188249259Sdim } 2189249259Sdim 2190249259Sdim if (Alignment == 0) { 2191249259Sdim const PointerType *GVPtrTy = cast<PointerType>(GV->getType()); 2192249259Sdim if (GVPtrTy->getElementType()->isSized()) { 2193249259Sdim Alignment 2194249259Sdim = getDataLayout()->getABITypeAlignment(GVPtrTy->getElementType()); 2195249259Sdim } else { 2196249259Sdim // Be conservative if we can't guess, not that it really matters: 2197249259Sdim // functions and labels aren't valid for loads, and the methods used to 2198249259Sdim // actually calculate an address work with any alignment. 2199249259Sdim Alignment = 1; 2200249259Sdim } 2201249259Sdim } 2202249259Sdim 2203249259Sdim unsigned char HiFixup, LoFixup; 2204263508Sdim bool UseGOT = getSubtarget()->GVIsIndirectSymbol(GV, RelocM); 2205249259Sdim 2206249259Sdim if (UseGOT) { 2207249259Sdim HiFixup = AArch64II::MO_GOT; 2208249259Sdim LoFixup = AArch64II::MO_GOT_LO12; 2209249259Sdim Alignment = 8; 2210249259Sdim } else { 2211249259Sdim HiFixup = AArch64II::MO_NO_FLAG; 2212249259Sdim LoFixup = AArch64II::MO_LO12; 2213249259Sdim } 2214249259Sdim 2215249259Sdim // AArch64's small model demands the following sequence: 2216249259Sdim // ADRP x0, somewhere 2217249259Sdim // ADD x0, x0, #:lo12:somewhere ; (or LDR directly). 2218249259Sdim SDValue GlobalRef = DAG.getNode(AArch64ISD::WrapperSmall, dl, PtrVT, 2219249259Sdim DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 2220249259Sdim HiFixup), 2221249259Sdim DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 2222249259Sdim LoFixup), 2223249259Sdim DAG.getConstant(Alignment, MVT::i32)); 2224249259Sdim 2225249259Sdim if (UseGOT) { 2226249259Sdim GlobalRef = DAG.getNode(AArch64ISD::GOTLoad, dl, PtrVT, DAG.getEntryNode(), 2227249259Sdim GlobalRef); 2228249259Sdim } 2229249259Sdim 2230249259Sdim if (GN->getOffset() != 0) 2231249259Sdim return DAG.getNode(ISD::ADD, dl, PtrVT, GlobalRef, 2232249259Sdim DAG.getConstant(GN->getOffset(), PtrVT)); 2233249259Sdim 2234249259Sdim return GlobalRef; 2235249259Sdim} 2236249259Sdim 2237251662SdimSDValue 2238251662SdimAArch64TargetLowering::LowerGlobalAddressELF(SDValue Op, 2239251662Sdim SelectionDAG &DAG) const { 2240251662Sdim // TableGen doesn't have easy access to the CodeModel or RelocationModel, so 2241251662Sdim // we make those distinctions here. 2242251662Sdim 2243251662Sdim switch (getTargetMachine().getCodeModel()) { 2244251662Sdim case CodeModel::Small: 2245251662Sdim return LowerGlobalAddressELFSmall(Op, DAG); 2246251662Sdim case CodeModel::Large: 2247251662Sdim return LowerGlobalAddressELFLarge(Op, DAG); 2248251662Sdim default: 2249251662Sdim llvm_unreachable("Only small and large code models supported now"); 2250251662Sdim } 2251251662Sdim} 2252251662Sdim 2253249259SdimSDValue AArch64TargetLowering::LowerTLSDescCall(SDValue SymAddr, 2254249259Sdim SDValue DescAddr, 2255263508Sdim SDLoc DL, 2256249259Sdim SelectionDAG &DAG) const { 2257249259Sdim EVT PtrVT = getPointerTy(); 2258249259Sdim 2259249259Sdim // The function we need to call is simply the first entry in the GOT for this 2260249259Sdim // descriptor, load it in preparation. 2261249259Sdim SDValue Func, Chain; 2262249259Sdim Func = DAG.getNode(AArch64ISD::GOTLoad, DL, PtrVT, DAG.getEntryNode(), 2263249259Sdim DescAddr); 2264249259Sdim 2265249259Sdim // The function takes only one argument: the address of the descriptor itself 2266249259Sdim // in X0. 2267249259Sdim SDValue Glue; 2268249259Sdim Chain = DAG.getCopyToReg(DAG.getEntryNode(), DL, AArch64::X0, DescAddr, Glue); 2269249259Sdim Glue = Chain.getValue(1); 2270249259Sdim 2271249259Sdim // Finally, there's a special calling-convention which means that the lookup 2272249259Sdim // must preserve all registers (except X0, obviously). 2273249259Sdim const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 2274249259Sdim const AArch64RegisterInfo *A64RI 2275249259Sdim = static_cast<const AArch64RegisterInfo *>(TRI); 2276249259Sdim const uint32_t *Mask = A64RI->getTLSDescCallPreservedMask(); 2277249259Sdim 2278249259Sdim // We're now ready to populate the argument list, as with a normal call: 2279249259Sdim std::vector<SDValue> Ops; 2280249259Sdim Ops.push_back(Chain); 2281249259Sdim Ops.push_back(Func); 2282249259Sdim Ops.push_back(SymAddr); 2283249259Sdim Ops.push_back(DAG.getRegister(AArch64::X0, PtrVT)); 2284249259Sdim Ops.push_back(DAG.getRegisterMask(Mask)); 2285249259Sdim Ops.push_back(Glue); 2286249259Sdim 2287249259Sdim SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2288249259Sdim Chain = DAG.getNode(AArch64ISD::TLSDESCCALL, DL, NodeTys, &Ops[0], 2289249259Sdim Ops.size()); 2290249259Sdim Glue = Chain.getValue(1); 2291249259Sdim 2292249259Sdim // After the call, the offset from TPIDR_EL0 is in X0, copy it out and pass it 2293249259Sdim // back to the generic handling code. 2294249259Sdim return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Glue); 2295249259Sdim} 2296249259Sdim 2297249259SdimSDValue 2298249259SdimAArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op, 2299249259Sdim SelectionDAG &DAG) const { 2300263508Sdim assert(getSubtarget()->isTargetELF() && 2301249259Sdim "TLS not implemented for non-ELF targets"); 2302251662Sdim assert(getTargetMachine().getCodeModel() == CodeModel::Small 2303251662Sdim && "TLS only supported in small memory model"); 2304249259Sdim const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 2305249259Sdim 2306249259Sdim TLSModel::Model Model = getTargetMachine().getTLSModel(GA->getGlobal()); 2307249259Sdim 2308249259Sdim SDValue TPOff; 2309249259Sdim EVT PtrVT = getPointerTy(); 2310263508Sdim SDLoc DL(Op); 2311249259Sdim const GlobalValue *GV = GA->getGlobal(); 2312249259Sdim 2313249259Sdim SDValue ThreadBase = DAG.getNode(AArch64ISD::THREAD_POINTER, DL, PtrVT); 2314249259Sdim 2315249259Sdim if (Model == TLSModel::InitialExec) { 2316249259Sdim TPOff = DAG.getNode(AArch64ISD::WrapperSmall, DL, PtrVT, 2317249259Sdim DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2318249259Sdim AArch64II::MO_GOTTPREL), 2319249259Sdim DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2320249259Sdim AArch64II::MO_GOTTPREL_LO12), 2321249259Sdim DAG.getConstant(8, MVT::i32)); 2322249259Sdim TPOff = DAG.getNode(AArch64ISD::GOTLoad, DL, PtrVT, DAG.getEntryNode(), 2323249259Sdim TPOff); 2324249259Sdim } else if (Model == TLSModel::LocalExec) { 2325249259Sdim SDValue HiVar = DAG.getTargetGlobalAddress(GV, DL, MVT::i64, 0, 2326249259Sdim AArch64II::MO_TPREL_G1); 2327249259Sdim SDValue LoVar = DAG.getTargetGlobalAddress(GV, DL, MVT::i64, 0, 2328249259Sdim AArch64II::MO_TPREL_G0_NC); 2329249259Sdim 2330249259Sdim TPOff = SDValue(DAG.getMachineNode(AArch64::MOVZxii, DL, PtrVT, HiVar, 2331263508Sdim DAG.getTargetConstant(1, MVT::i32)), 0); 2332249259Sdim TPOff = SDValue(DAG.getMachineNode(AArch64::MOVKxii, DL, PtrVT, 2333249259Sdim TPOff, LoVar, 2334249259Sdim DAG.getTargetConstant(0, MVT::i32)), 0); 2335249259Sdim } else if (Model == TLSModel::GeneralDynamic) { 2336249259Sdim // Accesses used in this sequence go via the TLS descriptor which lives in 2337249259Sdim // the GOT. Prepare an address we can use to handle this. 2338249259Sdim SDValue HiDesc = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2339249259Sdim AArch64II::MO_TLSDESC); 2340249259Sdim SDValue LoDesc = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2341249259Sdim AArch64II::MO_TLSDESC_LO12); 2342249259Sdim SDValue DescAddr = DAG.getNode(AArch64ISD::WrapperSmall, DL, PtrVT, 2343249259Sdim HiDesc, LoDesc, 2344249259Sdim DAG.getConstant(8, MVT::i32)); 2345249259Sdim SDValue SymAddr = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0); 2346249259Sdim 2347249259Sdim TPOff = LowerTLSDescCall(SymAddr, DescAddr, DL, DAG); 2348249259Sdim } else if (Model == TLSModel::LocalDynamic) { 2349249259Sdim // Local-dynamic accesses proceed in two phases. A general-dynamic TLS 2350249259Sdim // descriptor call against the special symbol _TLS_MODULE_BASE_ to calculate 2351249259Sdim // the beginning of the module's TLS region, followed by a DTPREL offset 2352249259Sdim // calculation. 2353249259Sdim 2354249259Sdim // These accesses will need deduplicating if there's more than one. 2355249259Sdim AArch64MachineFunctionInfo* MFI = DAG.getMachineFunction() 2356249259Sdim .getInfo<AArch64MachineFunctionInfo>(); 2357249259Sdim MFI->incNumLocalDynamicTLSAccesses(); 2358249259Sdim 2359249259Sdim 2360249259Sdim // Get the location of _TLS_MODULE_BASE_: 2361249259Sdim SDValue HiDesc = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT, 2362249259Sdim AArch64II::MO_TLSDESC); 2363249259Sdim SDValue LoDesc = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT, 2364249259Sdim AArch64II::MO_TLSDESC_LO12); 2365249259Sdim SDValue DescAddr = DAG.getNode(AArch64ISD::WrapperSmall, DL, PtrVT, 2366249259Sdim HiDesc, LoDesc, 2367249259Sdim DAG.getConstant(8, MVT::i32)); 2368249259Sdim SDValue SymAddr = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT); 2369249259Sdim 2370249259Sdim ThreadBase = LowerTLSDescCall(SymAddr, DescAddr, DL, DAG); 2371249259Sdim 2372249259Sdim // Get the variable's offset from _TLS_MODULE_BASE_ 2373249259Sdim SDValue HiVar = DAG.getTargetGlobalAddress(GV, DL, MVT::i64, 0, 2374249259Sdim AArch64II::MO_DTPREL_G1); 2375249259Sdim SDValue LoVar = DAG.getTargetGlobalAddress(GV, DL, MVT::i64, 0, 2376249259Sdim AArch64II::MO_DTPREL_G0_NC); 2377249259Sdim 2378249259Sdim TPOff = SDValue(DAG.getMachineNode(AArch64::MOVZxii, DL, PtrVT, HiVar, 2379249259Sdim DAG.getTargetConstant(0, MVT::i32)), 0); 2380249259Sdim TPOff = SDValue(DAG.getMachineNode(AArch64::MOVKxii, DL, PtrVT, 2381249259Sdim TPOff, LoVar, 2382249259Sdim DAG.getTargetConstant(0, MVT::i32)), 0); 2383249259Sdim } else 2384249259Sdim llvm_unreachable("Unsupported TLS access model"); 2385249259Sdim 2386249259Sdim 2387249259Sdim return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadBase, TPOff); 2388249259Sdim} 2389249259Sdim 2390249259SdimSDValue 2391249259SdimAArch64TargetLowering::LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG, 2392249259Sdim bool IsSigned) const { 2393249259Sdim if (Op.getValueType() != MVT::f128) { 2394249259Sdim // Legal for everything except f128. 2395249259Sdim return Op; 2396249259Sdim } 2397249259Sdim 2398249259Sdim RTLIB::Libcall LC; 2399249259Sdim if (IsSigned) 2400249259Sdim LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType()); 2401249259Sdim else 2402249259Sdim LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType()); 2403249259Sdim 2404249259Sdim return LowerF128ToCall(Op, DAG, LC); 2405249259Sdim} 2406249259Sdim 2407249259Sdim 2408249259SdimSDValue 2409249259SdimAArch64TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const { 2410249259Sdim JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 2411263508Sdim SDLoc dl(JT); 2412251662Sdim EVT PtrVT = getPointerTy(); 2413249259Sdim 2414249259Sdim // When compiling PIC, jump tables get put in the code section so a static 2415249259Sdim // relocation-style is acceptable for both cases. 2416251662Sdim switch (getTargetMachine().getCodeModel()) { 2417251662Sdim case CodeModel::Small: 2418251662Sdim return DAG.getNode(AArch64ISD::WrapperSmall, dl, PtrVT, 2419251662Sdim DAG.getTargetJumpTable(JT->getIndex(), PtrVT), 2420251662Sdim DAG.getTargetJumpTable(JT->getIndex(), PtrVT, 2421251662Sdim AArch64II::MO_LO12), 2422251662Sdim DAG.getConstant(1, MVT::i32)); 2423251662Sdim case CodeModel::Large: 2424251662Sdim return DAG.getNode( 2425251662Sdim AArch64ISD::WrapperLarge, dl, PtrVT, 2426251662Sdim DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_ABS_G3), 2427251662Sdim DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_ABS_G2_NC), 2428251662Sdim DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_ABS_G1_NC), 2429251662Sdim DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_ABS_G0_NC)); 2430251662Sdim default: 2431251662Sdim llvm_unreachable("Only small and large code models supported now"); 2432251662Sdim } 2433249259Sdim} 2434249259Sdim 2435249259Sdim// (SELECT_CC lhs, rhs, iftrue, iffalse, condcode) 2436249259SdimSDValue 2437249259SdimAArch64TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { 2438263508Sdim SDLoc dl(Op); 2439249259Sdim SDValue LHS = Op.getOperand(0); 2440249259Sdim SDValue RHS = Op.getOperand(1); 2441249259Sdim SDValue IfTrue = Op.getOperand(2); 2442249259Sdim SDValue IfFalse = Op.getOperand(3); 2443249259Sdim ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 2444249259Sdim 2445249259Sdim if (LHS.getValueType() == MVT::f128) { 2446249259Sdim // f128 comparisons are lowered to libcalls, but slot in nicely here 2447249259Sdim // afterwards. 2448249259Sdim softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl); 2449249259Sdim 2450249259Sdim // If softenSetCCOperands returned a scalar, we need to compare the result 2451249259Sdim // against zero to select between true and false values. 2452249259Sdim if (RHS.getNode() == 0) { 2453249259Sdim RHS = DAG.getConstant(0, LHS.getValueType()); 2454249259Sdim CC = ISD::SETNE; 2455249259Sdim } 2456249259Sdim } 2457249259Sdim 2458249259Sdim if (LHS.getValueType().isInteger()) { 2459249259Sdim SDValue A64cc; 2460249259Sdim 2461249259Sdim // Integers are handled in a separate function because the combinations of 2462249259Sdim // immediates and tests can get hairy and we may want to fiddle things. 2463249259Sdim SDValue CmpOp = getSelectableIntSetCC(LHS, RHS, CC, A64cc, DAG, dl); 2464249259Sdim 2465249259Sdim return DAG.getNode(AArch64ISD::SELECT_CC, dl, Op.getValueType(), 2466249259Sdim CmpOp, IfTrue, IfFalse, A64cc); 2467249259Sdim } 2468249259Sdim 2469249259Sdim // Note that some LLVM floating-point CondCodes can't be lowered to a single 2470249259Sdim // conditional branch, hence FPCCToA64CC can set a second test, where either 2471249259Sdim // passing is sufficient. 2472249259Sdim A64CC::CondCodes CondCode, Alternative = A64CC::Invalid; 2473249259Sdim CondCode = FPCCToA64CC(CC, Alternative); 2474249259Sdim SDValue A64cc = DAG.getConstant(CondCode, MVT::i32); 2475249259Sdim SDValue SetCC = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, LHS, RHS, 2476249259Sdim DAG.getCondCode(CC)); 2477249259Sdim SDValue A64SELECT_CC = DAG.getNode(AArch64ISD::SELECT_CC, dl, 2478249259Sdim Op.getValueType(), 2479249259Sdim SetCC, IfTrue, IfFalse, A64cc); 2480249259Sdim 2481249259Sdim if (Alternative != A64CC::Invalid) { 2482249259Sdim A64cc = DAG.getConstant(Alternative, MVT::i32); 2483249259Sdim A64SELECT_CC = DAG.getNode(AArch64ISD::SELECT_CC, dl, Op.getValueType(), 2484249259Sdim SetCC, IfTrue, A64SELECT_CC, A64cc); 2485249259Sdim 2486249259Sdim } 2487249259Sdim 2488249259Sdim return A64SELECT_CC; 2489249259Sdim} 2490249259Sdim 2491249259Sdim// (SELECT testbit, iftrue, iffalse) 2492249259SdimSDValue 2493249259SdimAArch64TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { 2494263508Sdim SDLoc dl(Op); 2495249259Sdim SDValue TheBit = Op.getOperand(0); 2496249259Sdim SDValue IfTrue = Op.getOperand(1); 2497249259Sdim SDValue IfFalse = Op.getOperand(2); 2498249259Sdim 2499249259Sdim // AArch64 BooleanContents is the default UndefinedBooleanContent, which means 2500249259Sdim // that as the consumer we are responsible for ignoring rubbish in higher 2501249259Sdim // bits. 2502249259Sdim TheBit = DAG.getNode(ISD::AND, dl, MVT::i32, TheBit, 2503249259Sdim DAG.getConstant(1, MVT::i32)); 2504249259Sdim SDValue A64CMP = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, TheBit, 2505249259Sdim DAG.getConstant(0, TheBit.getValueType()), 2506249259Sdim DAG.getCondCode(ISD::SETNE)); 2507249259Sdim 2508249259Sdim return DAG.getNode(AArch64ISD::SELECT_CC, dl, Op.getValueType(), 2509249259Sdim A64CMP, IfTrue, IfFalse, 2510249259Sdim DAG.getConstant(A64CC::NE, MVT::i32)); 2511249259Sdim} 2512249259Sdim 2513263508Sdimstatic SDValue LowerVectorSETCC(SDValue Op, SelectionDAG &DAG) { 2514263508Sdim SDLoc DL(Op); 2515263508Sdim SDValue LHS = Op.getOperand(0); 2516263508Sdim SDValue RHS = Op.getOperand(1); 2517263508Sdim ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 2518263508Sdim EVT VT = Op.getValueType(); 2519263508Sdim bool Invert = false; 2520263508Sdim SDValue Op0, Op1; 2521263508Sdim unsigned Opcode; 2522263508Sdim 2523263508Sdim if (LHS.getValueType().isInteger()) { 2524263508Sdim 2525263508Sdim // Attempt to use Vector Integer Compare Mask Test instruction. 2526263508Sdim // TST = icmp ne (and (op0, op1), zero). 2527263508Sdim if (CC == ISD::SETNE) { 2528263508Sdim if (((LHS.getOpcode() == ISD::AND) && 2529263508Sdim ISD::isBuildVectorAllZeros(RHS.getNode())) || 2530263508Sdim ((RHS.getOpcode() == ISD::AND) && 2531263508Sdim ISD::isBuildVectorAllZeros(LHS.getNode()))) { 2532263508Sdim 2533263508Sdim SDValue AndOp = (LHS.getOpcode() == ISD::AND) ? LHS : RHS; 2534263508Sdim SDValue NewLHS = DAG.getNode(ISD::BITCAST, DL, VT, AndOp.getOperand(0)); 2535263508Sdim SDValue NewRHS = DAG.getNode(ISD::BITCAST, DL, VT, AndOp.getOperand(1)); 2536263508Sdim return DAG.getNode(AArch64ISD::NEON_TST, DL, VT, NewLHS, NewRHS); 2537263508Sdim } 2538263508Sdim } 2539263508Sdim 2540263508Sdim // Attempt to use Vector Integer Compare Mask against Zero instr (Signed). 2541263508Sdim // Note: Compare against Zero does not support unsigned predicates. 2542263508Sdim if ((ISD::isBuildVectorAllZeros(RHS.getNode()) || 2543263508Sdim ISD::isBuildVectorAllZeros(LHS.getNode())) && 2544263508Sdim !isUnsignedIntSetCC(CC)) { 2545263508Sdim 2546263508Sdim // If LHS is the zero value, swap operands and CondCode. 2547263508Sdim if (ISD::isBuildVectorAllZeros(LHS.getNode())) { 2548263508Sdim CC = getSetCCSwappedOperands(CC); 2549263508Sdim Op0 = RHS; 2550263508Sdim } else 2551263508Sdim Op0 = LHS; 2552263508Sdim 2553263508Sdim // Ensure valid CondCode for Compare Mask against Zero instruction: 2554263508Sdim // EQ, GE, GT, LE, LT. 2555263508Sdim if (ISD::SETNE == CC) { 2556263508Sdim Invert = true; 2557263508Sdim CC = ISD::SETEQ; 2558263508Sdim } 2559263508Sdim 2560263508Sdim // Using constant type to differentiate integer and FP compares with zero. 2561263508Sdim Op1 = DAG.getConstant(0, MVT::i32); 2562263508Sdim Opcode = AArch64ISD::NEON_CMPZ; 2563263508Sdim 2564263508Sdim } else { 2565263508Sdim // Attempt to use Vector Integer Compare Mask instr (Signed/Unsigned). 2566263508Sdim // Ensure valid CondCode for Compare Mask instr: EQ, GE, GT, UGE, UGT. 2567263508Sdim bool Swap = false; 2568263508Sdim switch (CC) { 2569263508Sdim default: 2570263508Sdim llvm_unreachable("Illegal integer comparison."); 2571263508Sdim case ISD::SETEQ: 2572263508Sdim case ISD::SETGT: 2573263508Sdim case ISD::SETGE: 2574263508Sdim case ISD::SETUGT: 2575263508Sdim case ISD::SETUGE: 2576263508Sdim break; 2577263508Sdim case ISD::SETNE: 2578263508Sdim Invert = true; 2579263508Sdim CC = ISD::SETEQ; 2580263508Sdim break; 2581263508Sdim case ISD::SETULT: 2582263508Sdim case ISD::SETULE: 2583263508Sdim case ISD::SETLT: 2584263508Sdim case ISD::SETLE: 2585263508Sdim Swap = true; 2586263508Sdim CC = getSetCCSwappedOperands(CC); 2587263508Sdim } 2588263508Sdim 2589263508Sdim if (Swap) 2590263508Sdim std::swap(LHS, RHS); 2591263508Sdim 2592263508Sdim Opcode = AArch64ISD::NEON_CMP; 2593263508Sdim Op0 = LHS; 2594263508Sdim Op1 = RHS; 2595263508Sdim } 2596263508Sdim 2597263508Sdim // Generate Compare Mask instr or Compare Mask against Zero instr. 2598263508Sdim SDValue NeonCmp = 2599263508Sdim DAG.getNode(Opcode, DL, VT, Op0, Op1, DAG.getCondCode(CC)); 2600263508Sdim 2601263508Sdim if (Invert) 2602263508Sdim NeonCmp = DAG.getNOT(DL, NeonCmp, VT); 2603263508Sdim 2604263508Sdim return NeonCmp; 2605263508Sdim } 2606263508Sdim 2607263508Sdim // Now handle Floating Point cases. 2608263508Sdim // Attempt to use Vector Floating Point Compare Mask against Zero instruction. 2609263508Sdim if (ISD::isBuildVectorAllZeros(RHS.getNode()) || 2610263508Sdim ISD::isBuildVectorAllZeros(LHS.getNode())) { 2611263508Sdim 2612263508Sdim // If LHS is the zero value, swap operands and CondCode. 2613263508Sdim if (ISD::isBuildVectorAllZeros(LHS.getNode())) { 2614263508Sdim CC = getSetCCSwappedOperands(CC); 2615263508Sdim Op0 = RHS; 2616263508Sdim } else 2617263508Sdim Op0 = LHS; 2618263508Sdim 2619263508Sdim // Using constant type to differentiate integer and FP compares with zero. 2620263508Sdim Op1 = DAG.getConstantFP(0, MVT::f32); 2621263508Sdim Opcode = AArch64ISD::NEON_CMPZ; 2622263508Sdim } else { 2623263508Sdim // Attempt to use Vector Floating Point Compare Mask instruction. 2624263508Sdim Op0 = LHS; 2625263508Sdim Op1 = RHS; 2626263508Sdim Opcode = AArch64ISD::NEON_CMP; 2627263508Sdim } 2628263508Sdim 2629263508Sdim SDValue NeonCmpAlt; 2630263508Sdim // Some register compares have to be implemented with swapped CC and operands, 2631263508Sdim // e.g.: OLT implemented as OGT with swapped operands. 2632263508Sdim bool SwapIfRegArgs = false; 2633263508Sdim 2634263508Sdim // Ensure valid CondCode for FP Compare Mask against Zero instruction: 2635263508Sdim // EQ, GE, GT, LE, LT. 2636263508Sdim // And ensure valid CondCode for FP Compare Mask instruction: EQ, GE, GT. 2637263508Sdim switch (CC) { 2638263508Sdim default: 2639263508Sdim llvm_unreachable("Illegal FP comparison"); 2640263508Sdim case ISD::SETUNE: 2641263508Sdim case ISD::SETNE: 2642263508Sdim Invert = true; // Fallthrough 2643263508Sdim case ISD::SETOEQ: 2644263508Sdim case ISD::SETEQ: 2645263508Sdim CC = ISD::SETEQ; 2646263508Sdim break; 2647263508Sdim case ISD::SETOLT: 2648263508Sdim case ISD::SETLT: 2649263508Sdim CC = ISD::SETLT; 2650263508Sdim SwapIfRegArgs = true; 2651263508Sdim break; 2652263508Sdim case ISD::SETOGT: 2653263508Sdim case ISD::SETGT: 2654263508Sdim CC = ISD::SETGT; 2655263508Sdim break; 2656263508Sdim case ISD::SETOLE: 2657263508Sdim case ISD::SETLE: 2658263508Sdim CC = ISD::SETLE; 2659263508Sdim SwapIfRegArgs = true; 2660263508Sdim break; 2661263508Sdim case ISD::SETOGE: 2662263508Sdim case ISD::SETGE: 2663263508Sdim CC = ISD::SETGE; 2664263508Sdim break; 2665263508Sdim case ISD::SETUGE: 2666263508Sdim Invert = true; 2667263508Sdim CC = ISD::SETLT; 2668263508Sdim SwapIfRegArgs = true; 2669263508Sdim break; 2670263508Sdim case ISD::SETULE: 2671263508Sdim Invert = true; 2672263508Sdim CC = ISD::SETGT; 2673263508Sdim break; 2674263508Sdim case ISD::SETUGT: 2675263508Sdim Invert = true; 2676263508Sdim CC = ISD::SETLE; 2677263508Sdim SwapIfRegArgs = true; 2678263508Sdim break; 2679263508Sdim case ISD::SETULT: 2680263508Sdim Invert = true; 2681263508Sdim CC = ISD::SETGE; 2682263508Sdim break; 2683263508Sdim case ISD::SETUEQ: 2684263508Sdim Invert = true; // Fallthrough 2685263508Sdim case ISD::SETONE: 2686263508Sdim // Expand this to (OGT |OLT). 2687263508Sdim NeonCmpAlt = 2688263508Sdim DAG.getNode(Opcode, DL, VT, Op0, Op1, DAG.getCondCode(ISD::SETGT)); 2689263508Sdim CC = ISD::SETLT; 2690263508Sdim SwapIfRegArgs = true; 2691263508Sdim break; 2692263508Sdim case ISD::SETUO: 2693263508Sdim Invert = true; // Fallthrough 2694263508Sdim case ISD::SETO: 2695263508Sdim // Expand this to (OGE | OLT). 2696263508Sdim NeonCmpAlt = 2697263508Sdim DAG.getNode(Opcode, DL, VT, Op0, Op1, DAG.getCondCode(ISD::SETGE)); 2698263508Sdim CC = ISD::SETLT; 2699263508Sdim SwapIfRegArgs = true; 2700263508Sdim break; 2701263508Sdim } 2702263508Sdim 2703263508Sdim if (Opcode == AArch64ISD::NEON_CMP && SwapIfRegArgs) { 2704263508Sdim CC = getSetCCSwappedOperands(CC); 2705263508Sdim std::swap(Op0, Op1); 2706263508Sdim } 2707263508Sdim 2708263508Sdim // Generate FP Compare Mask instr or FP Compare Mask against Zero instr 2709263508Sdim SDValue NeonCmp = DAG.getNode(Opcode, DL, VT, Op0, Op1, DAG.getCondCode(CC)); 2710263508Sdim 2711263508Sdim if (NeonCmpAlt.getNode()) 2712263508Sdim NeonCmp = DAG.getNode(ISD::OR, DL, VT, NeonCmp, NeonCmpAlt); 2713263508Sdim 2714263508Sdim if (Invert) 2715263508Sdim NeonCmp = DAG.getNOT(DL, NeonCmp, VT); 2716263508Sdim 2717263508Sdim return NeonCmp; 2718263508Sdim} 2719263508Sdim 2720249259Sdim// (SETCC lhs, rhs, condcode) 2721249259SdimSDValue 2722249259SdimAArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 2723263508Sdim SDLoc dl(Op); 2724249259Sdim SDValue LHS = Op.getOperand(0); 2725249259Sdim SDValue RHS = Op.getOperand(1); 2726249259Sdim ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 2727249259Sdim EVT VT = Op.getValueType(); 2728249259Sdim 2729263508Sdim if (VT.isVector()) 2730263508Sdim return LowerVectorSETCC(Op, DAG); 2731263508Sdim 2732249259Sdim if (LHS.getValueType() == MVT::f128) { 2733249259Sdim // f128 comparisons will be lowered to libcalls giving a valid LHS and RHS 2734249259Sdim // for the rest of the function (some i32 or i64 values). 2735249259Sdim softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl); 2736249259Sdim 2737249259Sdim // If softenSetCCOperands returned a scalar, use it. 2738249259Sdim if (RHS.getNode() == 0) { 2739249259Sdim assert(LHS.getValueType() == Op.getValueType() && 2740249259Sdim "Unexpected setcc expansion!"); 2741249259Sdim return LHS; 2742249259Sdim } 2743249259Sdim } 2744249259Sdim 2745249259Sdim if (LHS.getValueType().isInteger()) { 2746249259Sdim SDValue A64cc; 2747249259Sdim 2748249259Sdim // Integers are handled in a separate function because the combinations of 2749249259Sdim // immediates and tests can get hairy and we may want to fiddle things. 2750249259Sdim SDValue CmpOp = getSelectableIntSetCC(LHS, RHS, CC, A64cc, DAG, dl); 2751249259Sdim 2752249259Sdim return DAG.getNode(AArch64ISD::SELECT_CC, dl, VT, 2753249259Sdim CmpOp, DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2754249259Sdim A64cc); 2755249259Sdim } 2756249259Sdim 2757249259Sdim // Note that some LLVM floating-point CondCodes can't be lowered to a single 2758249259Sdim // conditional branch, hence FPCCToA64CC can set a second test, where either 2759249259Sdim // passing is sufficient. 2760249259Sdim A64CC::CondCodes CondCode, Alternative = A64CC::Invalid; 2761249259Sdim CondCode = FPCCToA64CC(CC, Alternative); 2762249259Sdim SDValue A64cc = DAG.getConstant(CondCode, MVT::i32); 2763249259Sdim SDValue CmpOp = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, LHS, RHS, 2764249259Sdim DAG.getCondCode(CC)); 2765249259Sdim SDValue A64SELECT_CC = DAG.getNode(AArch64ISD::SELECT_CC, dl, VT, 2766249259Sdim CmpOp, DAG.getConstant(1, VT), 2767249259Sdim DAG.getConstant(0, VT), A64cc); 2768249259Sdim 2769249259Sdim if (Alternative != A64CC::Invalid) { 2770249259Sdim A64cc = DAG.getConstant(Alternative, MVT::i32); 2771249259Sdim A64SELECT_CC = DAG.getNode(AArch64ISD::SELECT_CC, dl, VT, CmpOp, 2772249259Sdim DAG.getConstant(1, VT), A64SELECT_CC, A64cc); 2773249259Sdim } 2774249259Sdim 2775249259Sdim return A64SELECT_CC; 2776249259Sdim} 2777249259Sdim 2778249259SdimSDValue 2779249259SdimAArch64TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const { 2780249259Sdim const Value *DestSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); 2781266715Sdim const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 2782249259Sdim 2783249259Sdim // We have to make sure we copy the entire structure: 8+8+8+4+4 = 32 bytes 2784249259Sdim // rather than just 8. 2785263508Sdim return DAG.getMemcpy(Op.getOperand(0), SDLoc(Op), 2786249259Sdim Op.getOperand(1), Op.getOperand(2), 2787249259Sdim DAG.getConstant(32, MVT::i32), 8, false, false, 2788249259Sdim MachinePointerInfo(DestSV), MachinePointerInfo(SrcSV)); 2789249259Sdim} 2790249259Sdim 2791249259SdimSDValue 2792249259SdimAArch64TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 2793249259Sdim // The layout of the va_list struct is specified in the AArch64 Procedure Call 2794249259Sdim // Standard, section B.3. 2795249259Sdim MachineFunction &MF = DAG.getMachineFunction(); 2796249259Sdim AArch64MachineFunctionInfo *FuncInfo 2797249259Sdim = MF.getInfo<AArch64MachineFunctionInfo>(); 2798263508Sdim SDLoc DL(Op); 2799249259Sdim 2800249259Sdim SDValue Chain = Op.getOperand(0); 2801249259Sdim SDValue VAList = Op.getOperand(1); 2802249259Sdim const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 2803249259Sdim SmallVector<SDValue, 4> MemOps; 2804249259Sdim 2805249259Sdim // void *__stack at offset 0 2806249259Sdim SDValue Stack = DAG.getFrameIndex(FuncInfo->getVariadicStackIdx(), 2807249259Sdim getPointerTy()); 2808249259Sdim MemOps.push_back(DAG.getStore(Chain, DL, Stack, VAList, 2809249259Sdim MachinePointerInfo(SV), false, false, 0)); 2810249259Sdim 2811249259Sdim // void *__gr_top at offset 8 2812249259Sdim int GPRSize = FuncInfo->getVariadicGPRSize(); 2813249259Sdim if (GPRSize > 0) { 2814249259Sdim SDValue GRTop, GRTopAddr; 2815249259Sdim 2816249259Sdim GRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList, 2817249259Sdim DAG.getConstant(8, getPointerTy())); 2818249259Sdim 2819249259Sdim GRTop = DAG.getFrameIndex(FuncInfo->getVariadicGPRIdx(), getPointerTy()); 2820249259Sdim GRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), GRTop, 2821249259Sdim DAG.getConstant(GPRSize, getPointerTy())); 2822249259Sdim 2823249259Sdim MemOps.push_back(DAG.getStore(Chain, DL, GRTop, GRTopAddr, 2824249259Sdim MachinePointerInfo(SV, 8), 2825249259Sdim false, false, 0)); 2826249259Sdim } 2827249259Sdim 2828249259Sdim // void *__vr_top at offset 16 2829249259Sdim int FPRSize = FuncInfo->getVariadicFPRSize(); 2830249259Sdim if (FPRSize > 0) { 2831249259Sdim SDValue VRTop, VRTopAddr; 2832249259Sdim VRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList, 2833249259Sdim DAG.getConstant(16, getPointerTy())); 2834249259Sdim 2835249259Sdim VRTop = DAG.getFrameIndex(FuncInfo->getVariadicFPRIdx(), getPointerTy()); 2836249259Sdim VRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), VRTop, 2837249259Sdim DAG.getConstant(FPRSize, getPointerTy())); 2838249259Sdim 2839249259Sdim MemOps.push_back(DAG.getStore(Chain, DL, VRTop, VRTopAddr, 2840249259Sdim MachinePointerInfo(SV, 16), 2841249259Sdim false, false, 0)); 2842249259Sdim } 2843249259Sdim 2844249259Sdim // int __gr_offs at offset 24 2845249259Sdim SDValue GROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList, 2846249259Sdim DAG.getConstant(24, getPointerTy())); 2847249259Sdim MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-GPRSize, MVT::i32), 2848249259Sdim GROffsAddr, MachinePointerInfo(SV, 24), 2849249259Sdim false, false, 0)); 2850249259Sdim 2851249259Sdim // int __vr_offs at offset 28 2852249259Sdim SDValue VROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList, 2853249259Sdim DAG.getConstant(28, getPointerTy())); 2854249259Sdim MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-FPRSize, MVT::i32), 2855249259Sdim VROffsAddr, MachinePointerInfo(SV, 28), 2856249259Sdim false, false, 0)); 2857249259Sdim 2858249259Sdim return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, &MemOps[0], 2859249259Sdim MemOps.size()); 2860249259Sdim} 2861249259Sdim 2862249259SdimSDValue 2863249259SdimAArch64TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 2864249259Sdim switch (Op.getOpcode()) { 2865249259Sdim default: llvm_unreachable("Don't know how to custom lower this!"); 2866249259Sdim case ISD::FADD: return LowerF128ToCall(Op, DAG, RTLIB::ADD_F128); 2867249259Sdim case ISD::FSUB: return LowerF128ToCall(Op, DAG, RTLIB::SUB_F128); 2868249259Sdim case ISD::FMUL: return LowerF128ToCall(Op, DAG, RTLIB::MUL_F128); 2869249259Sdim case ISD::FDIV: return LowerF128ToCall(Op, DAG, RTLIB::DIV_F128); 2870249259Sdim case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG, true); 2871249259Sdim case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG, false); 2872249259Sdim case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG, true); 2873249259Sdim case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG, false); 2874249259Sdim case ISD::FP_ROUND: return LowerFP_ROUND(Op, DAG); 2875249259Sdim case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG); 2876263508Sdim case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 2877263508Sdim case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 2878249259Sdim 2879249259Sdim case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 2880249259Sdim case ISD::BRCOND: return LowerBRCOND(Op, DAG); 2881249259Sdim case ISD::BR_CC: return LowerBR_CC(Op, DAG); 2882249259Sdim case ISD::GlobalAddress: return LowerGlobalAddressELF(Op, DAG); 2883249259Sdim case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 2884249259Sdim case ISD::JumpTable: return LowerJumpTable(Op, DAG); 2885249259Sdim case ISD::SELECT: return LowerSELECT(Op, DAG); 2886249259Sdim case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 2887249259Sdim case ISD::SETCC: return LowerSETCC(Op, DAG); 2888249259Sdim case ISD::VACOPY: return LowerVACOPY(Op, DAG); 2889249259Sdim case ISD::VASTART: return LowerVASTART(Op, DAG); 2890263508Sdim case ISD::BUILD_VECTOR: 2891263508Sdim return LowerBUILD_VECTOR(Op, DAG, getSubtarget()); 2892263508Sdim case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 2893249259Sdim } 2894249259Sdim 2895249259Sdim return SDValue(); 2896249259Sdim} 2897249259Sdim 2898263508Sdim/// Check if the specified splat value corresponds to a valid vector constant 2899263508Sdim/// for a Neon instruction with a "modified immediate" operand (e.g., MOVI). If 2900263508Sdim/// so, return the encoded 8-bit immediate and the OpCmode instruction fields 2901263508Sdim/// values. 2902263508Sdimstatic bool isNeonModifiedImm(uint64_t SplatBits, uint64_t SplatUndef, 2903263508Sdim unsigned SplatBitSize, SelectionDAG &DAG, 2904263508Sdim bool is128Bits, NeonModImmType type, EVT &VT, 2905263508Sdim unsigned &Imm, unsigned &OpCmode) { 2906263508Sdim switch (SplatBitSize) { 2907263508Sdim default: 2908263508Sdim llvm_unreachable("unexpected size for isNeonModifiedImm"); 2909263508Sdim case 8: { 2910263508Sdim if (type != Neon_Mov_Imm) 2911263508Sdim return false; 2912263508Sdim assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big"); 2913263508Sdim // Neon movi per byte: Op=0, Cmode=1110. 2914263508Sdim OpCmode = 0xe; 2915263508Sdim Imm = SplatBits; 2916263508Sdim VT = is128Bits ? MVT::v16i8 : MVT::v8i8; 2917263508Sdim break; 2918263508Sdim } 2919263508Sdim case 16: { 2920263508Sdim // Neon move inst per halfword 2921263508Sdim VT = is128Bits ? MVT::v8i16 : MVT::v4i16; 2922263508Sdim if ((SplatBits & ~0xff) == 0) { 2923263508Sdim // Value = 0x00nn is 0x00nn LSL 0 2924263508Sdim // movi: Op=0, Cmode=1000; mvni: Op=1, Cmode=1000 2925263508Sdim // bic: Op=1, Cmode=1001; orr: Op=0, Cmode=1001 2926263508Sdim // Op=x, Cmode=100y 2927263508Sdim Imm = SplatBits; 2928263508Sdim OpCmode = 0x8; 2929263508Sdim break; 2930263508Sdim } 2931263508Sdim if ((SplatBits & ~0xff00) == 0) { 2932263508Sdim // Value = 0xnn00 is 0x00nn LSL 8 2933263508Sdim // movi: Op=0, Cmode=1010; mvni: Op=1, Cmode=1010 2934263508Sdim // bic: Op=1, Cmode=1011; orr: Op=0, Cmode=1011 2935263508Sdim // Op=x, Cmode=101x 2936263508Sdim Imm = SplatBits >> 8; 2937263508Sdim OpCmode = 0xa; 2938263508Sdim break; 2939263508Sdim } 2940263508Sdim // can't handle any other 2941263508Sdim return false; 2942263508Sdim } 2943263508Sdim 2944263508Sdim case 32: { 2945263508Sdim // First the LSL variants (MSL is unusable by some interested instructions). 2946263508Sdim 2947263508Sdim // Neon move instr per word, shift zeros 2948263508Sdim VT = is128Bits ? MVT::v4i32 : MVT::v2i32; 2949263508Sdim if ((SplatBits & ~0xff) == 0) { 2950263508Sdim // Value = 0x000000nn is 0x000000nn LSL 0 2951263508Sdim // movi: Op=0, Cmode= 0000; mvni: Op=1, Cmode= 0000 2952263508Sdim // bic: Op=1, Cmode= 0001; orr: Op=0, Cmode= 0001 2953263508Sdim // Op=x, Cmode=000x 2954263508Sdim Imm = SplatBits; 2955263508Sdim OpCmode = 0; 2956263508Sdim break; 2957263508Sdim } 2958263508Sdim if ((SplatBits & ~0xff00) == 0) { 2959263508Sdim // Value = 0x0000nn00 is 0x000000nn LSL 8 2960263508Sdim // movi: Op=0, Cmode= 0010; mvni: Op=1, Cmode= 0010 2961263508Sdim // bic: Op=1, Cmode= 0011; orr : Op=0, Cmode= 0011 2962263508Sdim // Op=x, Cmode=001x 2963263508Sdim Imm = SplatBits >> 8; 2964263508Sdim OpCmode = 0x2; 2965263508Sdim break; 2966263508Sdim } 2967263508Sdim if ((SplatBits & ~0xff0000) == 0) { 2968263508Sdim // Value = 0x00nn0000 is 0x000000nn LSL 16 2969263508Sdim // movi: Op=0, Cmode= 0100; mvni: Op=1, Cmode= 0100 2970263508Sdim // bic: Op=1, Cmode= 0101; orr: Op=0, Cmode= 0101 2971263508Sdim // Op=x, Cmode=010x 2972263508Sdim Imm = SplatBits >> 16; 2973263508Sdim OpCmode = 0x4; 2974263508Sdim break; 2975263508Sdim } 2976263508Sdim if ((SplatBits & ~0xff000000) == 0) { 2977263508Sdim // Value = 0xnn000000 is 0x000000nn LSL 24 2978263508Sdim // movi: Op=0, Cmode= 0110; mvni: Op=1, Cmode= 0110 2979263508Sdim // bic: Op=1, Cmode= 0111; orr: Op=0, Cmode= 0111 2980263508Sdim // Op=x, Cmode=011x 2981263508Sdim Imm = SplatBits >> 24; 2982263508Sdim OpCmode = 0x6; 2983263508Sdim break; 2984263508Sdim } 2985263508Sdim 2986263508Sdim // Now the MSL immediates. 2987263508Sdim 2988263508Sdim // Neon move instr per word, shift ones 2989263508Sdim if ((SplatBits & ~0xffff) == 0 && 2990263508Sdim ((SplatBits | SplatUndef) & 0xff) == 0xff) { 2991263508Sdim // Value = 0x0000nnff is 0x000000nn MSL 8 2992263508Sdim // movi: Op=0, Cmode= 1100; mvni: Op=1, Cmode= 1100 2993263508Sdim // Op=x, Cmode=1100 2994263508Sdim Imm = SplatBits >> 8; 2995263508Sdim OpCmode = 0xc; 2996263508Sdim break; 2997263508Sdim } 2998263508Sdim if ((SplatBits & ~0xffffff) == 0 && 2999263508Sdim ((SplatBits | SplatUndef) & 0xffff) == 0xffff) { 3000263508Sdim // Value = 0x00nnffff is 0x000000nn MSL 16 3001263508Sdim // movi: Op=1, Cmode= 1101; mvni: Op=1, Cmode= 1101 3002263508Sdim // Op=x, Cmode=1101 3003263508Sdim Imm = SplatBits >> 16; 3004263508Sdim OpCmode = 0xd; 3005263508Sdim break; 3006263508Sdim } 3007263508Sdim // can't handle any other 3008263508Sdim return false; 3009263508Sdim } 3010263508Sdim 3011263508Sdim case 64: { 3012263508Sdim if (type != Neon_Mov_Imm) 3013263508Sdim return false; 3014263508Sdim // Neon move instr bytemask, where each byte is either 0x00 or 0xff. 3015263508Sdim // movi Op=1, Cmode=1110. 3016263508Sdim OpCmode = 0x1e; 3017263508Sdim uint64_t BitMask = 0xff; 3018263508Sdim uint64_t Val = 0; 3019263508Sdim unsigned ImmMask = 1; 3020263508Sdim Imm = 0; 3021263508Sdim for (int ByteNum = 0; ByteNum < 8; ++ByteNum) { 3022263508Sdim if (((SplatBits | SplatUndef) & BitMask) == BitMask) { 3023263508Sdim Val |= BitMask; 3024263508Sdim Imm |= ImmMask; 3025263508Sdim } else if ((SplatBits & BitMask) != 0) { 3026263508Sdim return false; 3027263508Sdim } 3028263508Sdim BitMask <<= 8; 3029263508Sdim ImmMask <<= 1; 3030263508Sdim } 3031263508Sdim SplatBits = Val; 3032263508Sdim VT = is128Bits ? MVT::v2i64 : MVT::v1i64; 3033263508Sdim break; 3034263508Sdim } 3035263508Sdim } 3036263508Sdim 3037263508Sdim return true; 3038263508Sdim} 3039263508Sdim 3040249259Sdimstatic SDValue PerformANDCombine(SDNode *N, 3041249259Sdim TargetLowering::DAGCombinerInfo &DCI) { 3042249259Sdim 3043249259Sdim SelectionDAG &DAG = DCI.DAG; 3044263508Sdim SDLoc DL(N); 3045249259Sdim EVT VT = N->getValueType(0); 3046249259Sdim 3047249259Sdim // We're looking for an SRA/SHL pair which form an SBFX. 3048249259Sdim 3049249259Sdim if (VT != MVT::i32 && VT != MVT::i64) 3050249259Sdim return SDValue(); 3051249259Sdim 3052249259Sdim if (!isa<ConstantSDNode>(N->getOperand(1))) 3053249259Sdim return SDValue(); 3054249259Sdim 3055249259Sdim uint64_t TruncMask = N->getConstantOperandVal(1); 3056249259Sdim if (!isMask_64(TruncMask)) 3057249259Sdim return SDValue(); 3058249259Sdim 3059249259Sdim uint64_t Width = CountPopulation_64(TruncMask); 3060249259Sdim SDValue Shift = N->getOperand(0); 3061249259Sdim 3062249259Sdim if (Shift.getOpcode() != ISD::SRL) 3063249259Sdim return SDValue(); 3064249259Sdim 3065249259Sdim if (!isa<ConstantSDNode>(Shift->getOperand(1))) 3066249259Sdim return SDValue(); 3067249259Sdim uint64_t LSB = Shift->getConstantOperandVal(1); 3068249259Sdim 3069249259Sdim if (LSB > VT.getSizeInBits() || Width > VT.getSizeInBits()) 3070249259Sdim return SDValue(); 3071249259Sdim 3072249259Sdim return DAG.getNode(AArch64ISD::UBFX, DL, VT, Shift.getOperand(0), 3073249259Sdim DAG.getConstant(LSB, MVT::i64), 3074249259Sdim DAG.getConstant(LSB + Width - 1, MVT::i64)); 3075249259Sdim} 3076249259Sdim 3077249259Sdim/// For a true bitfield insert, the bits getting into that contiguous mask 3078249259Sdim/// should come from the low part of an existing value: they must be formed from 3079249259Sdim/// a compatible SHL operation (unless they're already low). This function 3080249259Sdim/// checks that condition and returns the least-significant bit that's 3081249259Sdim/// intended. If the operation not a field preparation, -1 is returned. 3082263508Sdimstatic int32_t getLSBForBFI(SelectionDAG &DAG, SDLoc DL, EVT VT, 3083249259Sdim SDValue &MaskedVal, uint64_t Mask) { 3084249259Sdim if (!isShiftedMask_64(Mask)) 3085249259Sdim return -1; 3086249259Sdim 3087249259Sdim // Now we need to alter MaskedVal so that it is an appropriate input for a BFI 3088249259Sdim // instruction. BFI will do a left-shift by LSB before applying the mask we've 3089249259Sdim // spotted, so in general we should pre-emptively "undo" that by making sure 3090249259Sdim // the incoming bits have had a right-shift applied to them. 3091249259Sdim // 3092249259Sdim // This right shift, however, will combine with existing left/right shifts. In 3093249259Sdim // the simplest case of a completely straight bitfield operation, it will be 3094249259Sdim // expected to completely cancel out with an existing SHL. More complicated 3095249259Sdim // cases (e.g. bitfield to bitfield copy) may still need a real shift before 3096249259Sdim // the BFI. 3097249259Sdim 3098263508Sdim uint64_t LSB = countTrailingZeros(Mask); 3099249259Sdim int64_t ShiftRightRequired = LSB; 3100249259Sdim if (MaskedVal.getOpcode() == ISD::SHL && 3101249259Sdim isa<ConstantSDNode>(MaskedVal.getOperand(1))) { 3102249259Sdim ShiftRightRequired -= MaskedVal.getConstantOperandVal(1); 3103249259Sdim MaskedVal = MaskedVal.getOperand(0); 3104249259Sdim } else if (MaskedVal.getOpcode() == ISD::SRL && 3105249259Sdim isa<ConstantSDNode>(MaskedVal.getOperand(1))) { 3106249259Sdim ShiftRightRequired += MaskedVal.getConstantOperandVal(1); 3107249259Sdim MaskedVal = MaskedVal.getOperand(0); 3108249259Sdim } 3109249259Sdim 3110249259Sdim if (ShiftRightRequired > 0) 3111249259Sdim MaskedVal = DAG.getNode(ISD::SRL, DL, VT, MaskedVal, 3112249259Sdim DAG.getConstant(ShiftRightRequired, MVT::i64)); 3113249259Sdim else if (ShiftRightRequired < 0) { 3114249259Sdim // We could actually end up with a residual left shift, for example with 3115249259Sdim // "struc.bitfield = val << 1". 3116249259Sdim MaskedVal = DAG.getNode(ISD::SHL, DL, VT, MaskedVal, 3117249259Sdim DAG.getConstant(-ShiftRightRequired, MVT::i64)); 3118249259Sdim } 3119249259Sdim 3120249259Sdim return LSB; 3121249259Sdim} 3122249259Sdim 3123249259Sdim/// Searches from N for an existing AArch64ISD::BFI node, possibly surrounded by 3124249259Sdim/// a mask and an extension. Returns true if a BFI was found and provides 3125249259Sdim/// information on its surroundings. 3126249259Sdimstatic bool findMaskedBFI(SDValue N, SDValue &BFI, uint64_t &Mask, 3127249259Sdim bool &Extended) { 3128249259Sdim Extended = false; 3129249259Sdim if (N.getOpcode() == ISD::ZERO_EXTEND) { 3130249259Sdim Extended = true; 3131249259Sdim N = N.getOperand(0); 3132249259Sdim } 3133249259Sdim 3134249259Sdim if (N.getOpcode() == ISD::AND && isa<ConstantSDNode>(N.getOperand(1))) { 3135249259Sdim Mask = N->getConstantOperandVal(1); 3136249259Sdim N = N.getOperand(0); 3137249259Sdim } else { 3138249259Sdim // Mask is the whole width. 3139249259Sdim Mask = -1ULL >> (64 - N.getValueType().getSizeInBits()); 3140249259Sdim } 3141249259Sdim 3142249259Sdim if (N.getOpcode() == AArch64ISD::BFI) { 3143249259Sdim BFI = N; 3144249259Sdim return true; 3145249259Sdim } 3146249259Sdim 3147249259Sdim return false; 3148249259Sdim} 3149249259Sdim 3150249259Sdim/// Try to combine a subtree (rooted at an OR) into a "masked BFI" node, which 3151249259Sdim/// is roughly equivalent to (and (BFI ...), mask). This form is used because it 3152249259Sdim/// can often be further combined with a larger mask. Ultimately, we want mask 3153249259Sdim/// to be 2^32-1 or 2^64-1 so the AND can be skipped. 3154249259Sdimstatic SDValue tryCombineToBFI(SDNode *N, 3155249259Sdim TargetLowering::DAGCombinerInfo &DCI, 3156249259Sdim const AArch64Subtarget *Subtarget) { 3157249259Sdim SelectionDAG &DAG = DCI.DAG; 3158263508Sdim SDLoc DL(N); 3159249259Sdim EVT VT = N->getValueType(0); 3160249259Sdim 3161249259Sdim assert(N->getOpcode() == ISD::OR && "Unexpected root"); 3162249259Sdim 3163249259Sdim // We need the LHS to be (and SOMETHING, MASK). Find out what that mask is or 3164249259Sdim // abandon the effort. 3165249259Sdim SDValue LHS = N->getOperand(0); 3166249259Sdim if (LHS.getOpcode() != ISD::AND) 3167249259Sdim return SDValue(); 3168249259Sdim 3169249259Sdim uint64_t LHSMask; 3170249259Sdim if (isa<ConstantSDNode>(LHS.getOperand(1))) 3171249259Sdim LHSMask = LHS->getConstantOperandVal(1); 3172249259Sdim else 3173249259Sdim return SDValue(); 3174249259Sdim 3175249259Sdim // We also need the RHS to be (and SOMETHING, MASK). Find out what that mask 3176249259Sdim // is or abandon the effort. 3177249259Sdim SDValue RHS = N->getOperand(1); 3178249259Sdim if (RHS.getOpcode() != ISD::AND) 3179249259Sdim return SDValue(); 3180249259Sdim 3181249259Sdim uint64_t RHSMask; 3182249259Sdim if (isa<ConstantSDNode>(RHS.getOperand(1))) 3183249259Sdim RHSMask = RHS->getConstantOperandVal(1); 3184249259Sdim else 3185249259Sdim return SDValue(); 3186249259Sdim 3187249259Sdim // Can't do anything if the masks are incompatible. 3188249259Sdim if (LHSMask & RHSMask) 3189249259Sdim return SDValue(); 3190249259Sdim 3191249259Sdim // Now we need one of the masks to be a contiguous field. Without loss of 3192249259Sdim // generality that should be the RHS one. 3193249259Sdim SDValue Bitfield = LHS.getOperand(0); 3194249259Sdim if (getLSBForBFI(DAG, DL, VT, Bitfield, LHSMask) != -1) { 3195249259Sdim // We know that LHS is a candidate new value, and RHS isn't already a better 3196249259Sdim // one. 3197249259Sdim std::swap(LHS, RHS); 3198249259Sdim std::swap(LHSMask, RHSMask); 3199249259Sdim } 3200249259Sdim 3201249259Sdim // We've done our best to put the right operands in the right places, all we 3202249259Sdim // can do now is check whether a BFI exists. 3203249259Sdim Bitfield = RHS.getOperand(0); 3204249259Sdim int32_t LSB = getLSBForBFI(DAG, DL, VT, Bitfield, RHSMask); 3205249259Sdim if (LSB == -1) 3206249259Sdim return SDValue(); 3207249259Sdim 3208249259Sdim uint32_t Width = CountPopulation_64(RHSMask); 3209249259Sdim assert(Width && "Expected non-zero bitfield width"); 3210249259Sdim 3211249259Sdim SDValue BFI = DAG.getNode(AArch64ISD::BFI, DL, VT, 3212249259Sdim LHS.getOperand(0), Bitfield, 3213249259Sdim DAG.getConstant(LSB, MVT::i64), 3214249259Sdim DAG.getConstant(Width, MVT::i64)); 3215249259Sdim 3216249259Sdim // Mask is trivial 3217249259Sdim if ((LHSMask | RHSMask) == (-1ULL >> (64 - VT.getSizeInBits()))) 3218249259Sdim return BFI; 3219249259Sdim 3220249259Sdim return DAG.getNode(ISD::AND, DL, VT, BFI, 3221249259Sdim DAG.getConstant(LHSMask | RHSMask, VT)); 3222249259Sdim} 3223249259Sdim 3224249259Sdim/// Search for the bitwise combining (with careful masks) of a MaskedBFI and its 3225249259Sdim/// original input. This is surprisingly common because SROA splits things up 3226249259Sdim/// into i8 chunks, so the originally detected MaskedBFI may actually only act 3227249259Sdim/// on the low (say) byte of a word. This is then orred into the rest of the 3228249259Sdim/// word afterwards. 3229249259Sdim/// 3230249259Sdim/// Basic input: (or (and OLDFIELD, MASK1), (MaskedBFI MASK2, OLDFIELD, ...)). 3231249259Sdim/// 3232249259Sdim/// If MASK1 and MASK2 are compatible, we can fold the whole thing into the 3233249259Sdim/// MaskedBFI. We can also deal with a certain amount of extend/truncate being 3234249259Sdim/// involved. 3235249259Sdimstatic SDValue tryCombineToLargerBFI(SDNode *N, 3236249259Sdim TargetLowering::DAGCombinerInfo &DCI, 3237249259Sdim const AArch64Subtarget *Subtarget) { 3238249259Sdim SelectionDAG &DAG = DCI.DAG; 3239263508Sdim SDLoc DL(N); 3240249259Sdim EVT VT = N->getValueType(0); 3241249259Sdim 3242249259Sdim // First job is to hunt for a MaskedBFI on either the left or right. Swap 3243249259Sdim // operands if it's actually on the right. 3244249259Sdim SDValue BFI; 3245249259Sdim SDValue PossExtraMask; 3246249259Sdim uint64_t ExistingMask = 0; 3247249259Sdim bool Extended = false; 3248249259Sdim if (findMaskedBFI(N->getOperand(0), BFI, ExistingMask, Extended)) 3249249259Sdim PossExtraMask = N->getOperand(1); 3250249259Sdim else if (findMaskedBFI(N->getOperand(1), BFI, ExistingMask, Extended)) 3251249259Sdim PossExtraMask = N->getOperand(0); 3252249259Sdim else 3253249259Sdim return SDValue(); 3254249259Sdim 3255249259Sdim // We can only combine a BFI with another compatible mask. 3256249259Sdim if (PossExtraMask.getOpcode() != ISD::AND || 3257249259Sdim !isa<ConstantSDNode>(PossExtraMask.getOperand(1))) 3258249259Sdim return SDValue(); 3259249259Sdim 3260249259Sdim uint64_t ExtraMask = PossExtraMask->getConstantOperandVal(1); 3261249259Sdim 3262249259Sdim // Masks must be compatible. 3263249259Sdim if (ExtraMask & ExistingMask) 3264249259Sdim return SDValue(); 3265249259Sdim 3266249259Sdim SDValue OldBFIVal = BFI.getOperand(0); 3267249259Sdim SDValue NewBFIVal = BFI.getOperand(1); 3268249259Sdim if (Extended) { 3269249259Sdim // We skipped a ZERO_EXTEND above, so the input to the MaskedBFIs should be 3270249259Sdim // 32-bit and we'll be forming a 64-bit MaskedBFI. The MaskedBFI arguments 3271249259Sdim // need to be made compatible. 3272249259Sdim assert(VT == MVT::i64 && BFI.getValueType() == MVT::i32 3273249259Sdim && "Invalid types for BFI"); 3274249259Sdim OldBFIVal = DAG.getNode(ISD::ANY_EXTEND, DL, VT, OldBFIVal); 3275249259Sdim NewBFIVal = DAG.getNode(ISD::ANY_EXTEND, DL, VT, NewBFIVal); 3276249259Sdim } 3277249259Sdim 3278249259Sdim // We need the MaskedBFI to be combined with a mask of the *same* value. 3279249259Sdim if (PossExtraMask.getOperand(0) != OldBFIVal) 3280249259Sdim return SDValue(); 3281249259Sdim 3282249259Sdim BFI = DAG.getNode(AArch64ISD::BFI, DL, VT, 3283249259Sdim OldBFIVal, NewBFIVal, 3284249259Sdim BFI.getOperand(2), BFI.getOperand(3)); 3285249259Sdim 3286249259Sdim // If the masking is trivial, we don't need to create it. 3287249259Sdim if ((ExtraMask | ExistingMask) == (-1ULL >> (64 - VT.getSizeInBits()))) 3288249259Sdim return BFI; 3289249259Sdim 3290249259Sdim return DAG.getNode(ISD::AND, DL, VT, BFI, 3291249259Sdim DAG.getConstant(ExtraMask | ExistingMask, VT)); 3292249259Sdim} 3293249259Sdim 3294249259Sdim/// An EXTR instruction is made up of two shifts, ORed together. This helper 3295249259Sdim/// searches for and classifies those shifts. 3296249259Sdimstatic bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount, 3297249259Sdim bool &FromHi) { 3298249259Sdim if (N.getOpcode() == ISD::SHL) 3299249259Sdim FromHi = false; 3300249259Sdim else if (N.getOpcode() == ISD::SRL) 3301249259Sdim FromHi = true; 3302249259Sdim else 3303249259Sdim return false; 3304249259Sdim 3305249259Sdim if (!isa<ConstantSDNode>(N.getOperand(1))) 3306249259Sdim return false; 3307249259Sdim 3308249259Sdim ShiftAmount = N->getConstantOperandVal(1); 3309249259Sdim Src = N->getOperand(0); 3310249259Sdim return true; 3311249259Sdim} 3312249259Sdim 3313249259Sdim/// EXTR instruction extracts a contiguous chunk of bits from two existing 3314249259Sdim/// registers viewed as a high/low pair. This function looks for the pattern: 3315249259Sdim/// (or (shl VAL1, #N), (srl VAL2, #RegWidth-N)) and replaces it with an 3316249259Sdim/// EXTR. Can't quite be done in TableGen because the two immediates aren't 3317249259Sdim/// independent. 3318249259Sdimstatic SDValue tryCombineToEXTR(SDNode *N, 3319249259Sdim TargetLowering::DAGCombinerInfo &DCI) { 3320249259Sdim SelectionDAG &DAG = DCI.DAG; 3321263508Sdim SDLoc DL(N); 3322249259Sdim EVT VT = N->getValueType(0); 3323249259Sdim 3324249259Sdim assert(N->getOpcode() == ISD::OR && "Unexpected root"); 3325249259Sdim 3326249259Sdim if (VT != MVT::i32 && VT != MVT::i64) 3327249259Sdim return SDValue(); 3328249259Sdim 3329249259Sdim SDValue LHS; 3330249259Sdim uint32_t ShiftLHS = 0; 3331249259Sdim bool LHSFromHi = 0; 3332249259Sdim if (!findEXTRHalf(N->getOperand(0), LHS, ShiftLHS, LHSFromHi)) 3333249259Sdim return SDValue(); 3334249259Sdim 3335249259Sdim SDValue RHS; 3336249259Sdim uint32_t ShiftRHS = 0; 3337249259Sdim bool RHSFromHi = 0; 3338249259Sdim if (!findEXTRHalf(N->getOperand(1), RHS, ShiftRHS, RHSFromHi)) 3339249259Sdim return SDValue(); 3340249259Sdim 3341249259Sdim // If they're both trying to come from the high part of the register, they're 3342249259Sdim // not really an EXTR. 3343249259Sdim if (LHSFromHi == RHSFromHi) 3344249259Sdim return SDValue(); 3345249259Sdim 3346249259Sdim if (ShiftLHS + ShiftRHS != VT.getSizeInBits()) 3347249259Sdim return SDValue(); 3348249259Sdim 3349249259Sdim if (LHSFromHi) { 3350249259Sdim std::swap(LHS, RHS); 3351249259Sdim std::swap(ShiftLHS, ShiftRHS); 3352249259Sdim } 3353249259Sdim 3354249259Sdim return DAG.getNode(AArch64ISD::EXTR, DL, VT, 3355249259Sdim LHS, RHS, 3356249259Sdim DAG.getConstant(ShiftRHS, MVT::i64)); 3357249259Sdim} 3358249259Sdim 3359249259Sdim/// Target-specific dag combine xforms for ISD::OR 3360249259Sdimstatic SDValue PerformORCombine(SDNode *N, 3361249259Sdim TargetLowering::DAGCombinerInfo &DCI, 3362249259Sdim const AArch64Subtarget *Subtarget) { 3363249259Sdim 3364249259Sdim SelectionDAG &DAG = DCI.DAG; 3365263508Sdim SDLoc DL(N); 3366249259Sdim EVT VT = N->getValueType(0); 3367249259Sdim 3368249259Sdim if(!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 3369249259Sdim return SDValue(); 3370249259Sdim 3371249259Sdim // Attempt to recognise bitfield-insert operations. 3372249259Sdim SDValue Res = tryCombineToBFI(N, DCI, Subtarget); 3373249259Sdim if (Res.getNode()) 3374249259Sdim return Res; 3375249259Sdim 3376249259Sdim // Attempt to combine an existing MaskedBFI operation into one with a larger 3377249259Sdim // mask. 3378249259Sdim Res = tryCombineToLargerBFI(N, DCI, Subtarget); 3379249259Sdim if (Res.getNode()) 3380249259Sdim return Res; 3381249259Sdim 3382249259Sdim Res = tryCombineToEXTR(N, DCI); 3383249259Sdim if (Res.getNode()) 3384249259Sdim return Res; 3385249259Sdim 3386263508Sdim if (!Subtarget->hasNEON()) 3387263508Sdim return SDValue(); 3388263508Sdim 3389263508Sdim // Attempt to use vector immediate-form BSL 3390263508Sdim // (or (and B, A), (and C, ~A)) => (VBSL A, B, C) when A is a constant. 3391263508Sdim 3392263508Sdim SDValue N0 = N->getOperand(0); 3393263508Sdim if (N0.getOpcode() != ISD::AND) 3394263508Sdim return SDValue(); 3395263508Sdim 3396263508Sdim SDValue N1 = N->getOperand(1); 3397263508Sdim if (N1.getOpcode() != ISD::AND) 3398263508Sdim return SDValue(); 3399263508Sdim 3400263508Sdim if (VT.isVector() && DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 3401263508Sdim APInt SplatUndef; 3402263508Sdim unsigned SplatBitSize; 3403263508Sdim bool HasAnyUndefs; 3404263508Sdim BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1)); 3405263508Sdim APInt SplatBits0; 3406263508Sdim if (BVN0 && BVN0->isConstantSplat(SplatBits0, SplatUndef, SplatBitSize, 3407263508Sdim HasAnyUndefs) && 3408263508Sdim !HasAnyUndefs) { 3409263508Sdim BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(1)); 3410263508Sdim APInt SplatBits1; 3411263508Sdim if (BVN1 && BVN1->isConstantSplat(SplatBits1, SplatUndef, SplatBitSize, 3412263508Sdim HasAnyUndefs) && 3413263508Sdim !HasAnyUndefs && SplatBits0 == ~SplatBits1) { 3414263508Sdim // Canonicalize the vector type to make instruction selection simpler. 3415263508Sdim EVT CanonicalVT = VT.is128BitVector() ? MVT::v16i8 : MVT::v8i8; 3416263508Sdim SDValue Result = DAG.getNode(AArch64ISD::NEON_BSL, DL, CanonicalVT, 3417263508Sdim N0->getOperand(1), N0->getOperand(0), 3418263508Sdim N1->getOperand(0)); 3419263508Sdim return DAG.getNode(ISD::BITCAST, DL, VT, Result); 3420263508Sdim } 3421263508Sdim } 3422263508Sdim } 3423263508Sdim 3424249259Sdim return SDValue(); 3425249259Sdim} 3426249259Sdim 3427249259Sdim/// Target-specific dag combine xforms for ISD::SRA 3428249259Sdimstatic SDValue PerformSRACombine(SDNode *N, 3429249259Sdim TargetLowering::DAGCombinerInfo &DCI) { 3430249259Sdim 3431249259Sdim SelectionDAG &DAG = DCI.DAG; 3432263508Sdim SDLoc DL(N); 3433249259Sdim EVT VT = N->getValueType(0); 3434249259Sdim 3435249259Sdim // We're looking for an SRA/SHL pair which form an SBFX. 3436249259Sdim 3437249259Sdim if (VT != MVT::i32 && VT != MVT::i64) 3438249259Sdim return SDValue(); 3439249259Sdim 3440249259Sdim if (!isa<ConstantSDNode>(N->getOperand(1))) 3441249259Sdim return SDValue(); 3442249259Sdim 3443249259Sdim uint64_t ExtraSignBits = N->getConstantOperandVal(1); 3444249259Sdim SDValue Shift = N->getOperand(0); 3445249259Sdim 3446249259Sdim if (Shift.getOpcode() != ISD::SHL) 3447249259Sdim return SDValue(); 3448249259Sdim 3449249259Sdim if (!isa<ConstantSDNode>(Shift->getOperand(1))) 3450249259Sdim return SDValue(); 3451249259Sdim 3452249259Sdim uint64_t BitsOnLeft = Shift->getConstantOperandVal(1); 3453249259Sdim uint64_t Width = VT.getSizeInBits() - ExtraSignBits; 3454249259Sdim uint64_t LSB = VT.getSizeInBits() - Width - BitsOnLeft; 3455249259Sdim 3456249259Sdim if (LSB > VT.getSizeInBits() || Width > VT.getSizeInBits()) 3457249259Sdim return SDValue(); 3458249259Sdim 3459249259Sdim return DAG.getNode(AArch64ISD::SBFX, DL, VT, Shift.getOperand(0), 3460249259Sdim DAG.getConstant(LSB, MVT::i64), 3461249259Sdim DAG.getConstant(LSB + Width - 1, MVT::i64)); 3462249259Sdim} 3463249259Sdim 3464263508Sdim/// Check if this is a valid build_vector for the immediate operand of 3465263508Sdim/// a vector shift operation, where all the elements of the build_vector 3466263508Sdim/// must have the same constant integer value. 3467263508Sdimstatic bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) { 3468263508Sdim // Ignore bit_converts. 3469263508Sdim while (Op.getOpcode() == ISD::BITCAST) 3470263508Sdim Op = Op.getOperand(0); 3471263508Sdim BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode()); 3472263508Sdim APInt SplatBits, SplatUndef; 3473263508Sdim unsigned SplatBitSize; 3474263508Sdim bool HasAnyUndefs; 3475263508Sdim if (!BVN || !BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, 3476263508Sdim HasAnyUndefs, ElementBits) || 3477263508Sdim SplatBitSize > ElementBits) 3478263508Sdim return false; 3479263508Sdim Cnt = SplatBits.getSExtValue(); 3480263508Sdim return true; 3481263508Sdim} 3482249259Sdim 3483263508Sdim/// Check if this is a valid build_vector for the immediate operand of 3484263508Sdim/// a vector shift left operation. That value must be in the range: 3485263508Sdim/// 0 <= Value < ElementBits 3486263508Sdimstatic bool isVShiftLImm(SDValue Op, EVT VT, int64_t &Cnt) { 3487263508Sdim assert(VT.isVector() && "vector shift count is not a vector type"); 3488263508Sdim unsigned ElementBits = VT.getVectorElementType().getSizeInBits(); 3489263508Sdim if (!getVShiftImm(Op, ElementBits, Cnt)) 3490263508Sdim return false; 3491263508Sdim return (Cnt >= 0 && Cnt < ElementBits); 3492263508Sdim} 3493263508Sdim 3494263508Sdim/// Check if this is a valid build_vector for the immediate operand of a 3495263508Sdim/// vector shift right operation. The value must be in the range: 3496263508Sdim/// 1 <= Value <= ElementBits 3497263508Sdimstatic bool isVShiftRImm(SDValue Op, EVT VT, int64_t &Cnt) { 3498263508Sdim assert(VT.isVector() && "vector shift count is not a vector type"); 3499263508Sdim unsigned ElementBits = VT.getVectorElementType().getSizeInBits(); 3500263508Sdim if (!getVShiftImm(Op, ElementBits, Cnt)) 3501263508Sdim return false; 3502263508Sdim return (Cnt >= 1 && Cnt <= ElementBits); 3503263508Sdim} 3504263508Sdim 3505263508Sdim/// Checks for immediate versions of vector shifts and lowers them. 3506263508Sdimstatic SDValue PerformShiftCombine(SDNode *N, 3507263508Sdim TargetLowering::DAGCombinerInfo &DCI, 3508263508Sdim const AArch64Subtarget *ST) { 3509263508Sdim SelectionDAG &DAG = DCI.DAG; 3510263508Sdim EVT VT = N->getValueType(0); 3511263508Sdim if (N->getOpcode() == ISD::SRA && (VT == MVT::i32 || VT == MVT::i64)) 3512263508Sdim return PerformSRACombine(N, DCI); 3513263508Sdim 3514263508Sdim // Nothing to be done for scalar shifts. 3515263508Sdim const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3516263508Sdim if (!VT.isVector() || !TLI.isTypeLegal(VT)) 3517263508Sdim return SDValue(); 3518263508Sdim 3519263508Sdim assert(ST->hasNEON() && "unexpected vector shift"); 3520263508Sdim int64_t Cnt; 3521263508Sdim 3522263508Sdim switch (N->getOpcode()) { 3523263508Sdim default: 3524263508Sdim llvm_unreachable("unexpected shift opcode"); 3525263508Sdim 3526263508Sdim case ISD::SHL: 3527263508Sdim if (isVShiftLImm(N->getOperand(1), VT, Cnt)) { 3528263508Sdim SDValue RHS = 3529263508Sdim DAG.getNode(AArch64ISD::NEON_VDUP, SDLoc(N->getOperand(1)), VT, 3530263508Sdim DAG.getConstant(Cnt, MVT::i32)); 3531263508Sdim return DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0), RHS); 3532263508Sdim } 3533263508Sdim break; 3534263508Sdim 3535263508Sdim case ISD::SRA: 3536263508Sdim case ISD::SRL: 3537263508Sdim if (isVShiftRImm(N->getOperand(1), VT, Cnt)) { 3538263508Sdim SDValue RHS = 3539263508Sdim DAG.getNode(AArch64ISD::NEON_VDUP, SDLoc(N->getOperand(1)), VT, 3540263508Sdim DAG.getConstant(Cnt, MVT::i32)); 3541263508Sdim return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N->getOperand(0), RHS); 3542263508Sdim } 3543263508Sdim break; 3544263508Sdim } 3545263508Sdim 3546263508Sdim return SDValue(); 3547263508Sdim} 3548263508Sdim 3549263508Sdim/// ARM-specific DAG combining for intrinsics. 3550263508Sdimstatic SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) { 3551263508Sdim unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); 3552263508Sdim 3553263508Sdim switch (IntNo) { 3554263508Sdim default: 3555263508Sdim // Don't do anything for most intrinsics. 3556263508Sdim break; 3557263508Sdim 3558263508Sdim case Intrinsic::arm_neon_vqshifts: 3559263508Sdim case Intrinsic::arm_neon_vqshiftu: 3560263508Sdim EVT VT = N->getOperand(1).getValueType(); 3561263508Sdim int64_t Cnt; 3562263508Sdim if (!isVShiftLImm(N->getOperand(2), VT, Cnt)) 3563263508Sdim break; 3564263508Sdim unsigned VShiftOpc = (IntNo == Intrinsic::arm_neon_vqshifts) 3565263508Sdim ? AArch64ISD::NEON_QSHLs 3566263508Sdim : AArch64ISD::NEON_QSHLu; 3567263508Sdim return DAG.getNode(VShiftOpc, SDLoc(N), N->getValueType(0), 3568263508Sdim N->getOperand(1), DAG.getConstant(Cnt, MVT::i32)); 3569263508Sdim } 3570263508Sdim 3571263508Sdim return SDValue(); 3572263508Sdim} 3573263508Sdim 3574263508Sdim/// Target-specific DAG combine function for NEON load/store intrinsics 3575263508Sdim/// to merge base address updates. 3576263508Sdimstatic SDValue CombineBaseUpdate(SDNode *N, 3577263508Sdim TargetLowering::DAGCombinerInfo &DCI) { 3578263508Sdim if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 3579263508Sdim return SDValue(); 3580263508Sdim 3581263508Sdim SelectionDAG &DAG = DCI.DAG; 3582263508Sdim bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID || 3583263508Sdim N->getOpcode() == ISD::INTRINSIC_W_CHAIN); 3584263508Sdim unsigned AddrOpIdx = (isIntrinsic ? 2 : 1); 3585263508Sdim SDValue Addr = N->getOperand(AddrOpIdx); 3586263508Sdim 3587263508Sdim // Search for a use of the address operand that is an increment. 3588263508Sdim for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), 3589263508Sdim UE = Addr.getNode()->use_end(); UI != UE; ++UI) { 3590263508Sdim SDNode *User = *UI; 3591263508Sdim if (User->getOpcode() != ISD::ADD || 3592263508Sdim UI.getUse().getResNo() != Addr.getResNo()) 3593263508Sdim continue; 3594263508Sdim 3595263508Sdim // Check that the add is independent of the load/store. Otherwise, folding 3596263508Sdim // it would create a cycle. 3597263508Sdim if (User->isPredecessorOf(N) || N->isPredecessorOf(User)) 3598263508Sdim continue; 3599263508Sdim 3600263508Sdim // Find the new opcode for the updating load/store. 3601263508Sdim bool isLoad = true; 3602263508Sdim bool isLaneOp = false; 3603263508Sdim unsigned NewOpc = 0; 3604263508Sdim unsigned NumVecs = 0; 3605263508Sdim if (isIntrinsic) { 3606263508Sdim unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); 3607263508Sdim switch (IntNo) { 3608263508Sdim default: llvm_unreachable("unexpected intrinsic for Neon base update"); 3609263508Sdim case Intrinsic::arm_neon_vld1: NewOpc = AArch64ISD::NEON_LD1_UPD; 3610263508Sdim NumVecs = 1; break; 3611263508Sdim case Intrinsic::arm_neon_vld2: NewOpc = AArch64ISD::NEON_LD2_UPD; 3612263508Sdim NumVecs = 2; break; 3613263508Sdim case Intrinsic::arm_neon_vld3: NewOpc = AArch64ISD::NEON_LD3_UPD; 3614263508Sdim NumVecs = 3; break; 3615263508Sdim case Intrinsic::arm_neon_vld4: NewOpc = AArch64ISD::NEON_LD4_UPD; 3616263508Sdim NumVecs = 4; break; 3617263508Sdim case Intrinsic::arm_neon_vst1: NewOpc = AArch64ISD::NEON_ST1_UPD; 3618263508Sdim NumVecs = 1; isLoad = false; break; 3619263508Sdim case Intrinsic::arm_neon_vst2: NewOpc = AArch64ISD::NEON_ST2_UPD; 3620263508Sdim NumVecs = 2; isLoad = false; break; 3621263508Sdim case Intrinsic::arm_neon_vst3: NewOpc = AArch64ISD::NEON_ST3_UPD; 3622263508Sdim NumVecs = 3; isLoad = false; break; 3623263508Sdim case Intrinsic::arm_neon_vst4: NewOpc = AArch64ISD::NEON_ST4_UPD; 3624263508Sdim NumVecs = 4; isLoad = false; break; 3625263508Sdim case Intrinsic::aarch64_neon_vld1x2: NewOpc = AArch64ISD::NEON_LD1x2_UPD; 3626263508Sdim NumVecs = 2; break; 3627263508Sdim case Intrinsic::aarch64_neon_vld1x3: NewOpc = AArch64ISD::NEON_LD1x3_UPD; 3628263508Sdim NumVecs = 3; break; 3629263508Sdim case Intrinsic::aarch64_neon_vld1x4: NewOpc = AArch64ISD::NEON_LD1x4_UPD; 3630263508Sdim NumVecs = 4; break; 3631263508Sdim case Intrinsic::aarch64_neon_vst1x2: NewOpc = AArch64ISD::NEON_ST1x2_UPD; 3632263508Sdim NumVecs = 2; isLoad = false; break; 3633263508Sdim case Intrinsic::aarch64_neon_vst1x3: NewOpc = AArch64ISD::NEON_ST1x3_UPD; 3634263508Sdim NumVecs = 3; isLoad = false; break; 3635263508Sdim case Intrinsic::aarch64_neon_vst1x4: NewOpc = AArch64ISD::NEON_ST1x4_UPD; 3636263508Sdim NumVecs = 4; isLoad = false; break; 3637263508Sdim case Intrinsic::arm_neon_vld2lane: NewOpc = AArch64ISD::NEON_LD2LN_UPD; 3638263508Sdim NumVecs = 2; isLaneOp = true; break; 3639263508Sdim case Intrinsic::arm_neon_vld3lane: NewOpc = AArch64ISD::NEON_LD3LN_UPD; 3640263508Sdim NumVecs = 3; isLaneOp = true; break; 3641263508Sdim case Intrinsic::arm_neon_vld4lane: NewOpc = AArch64ISD::NEON_LD4LN_UPD; 3642263508Sdim NumVecs = 4; isLaneOp = true; break; 3643263508Sdim case Intrinsic::arm_neon_vst2lane: NewOpc = AArch64ISD::NEON_ST2LN_UPD; 3644263508Sdim NumVecs = 2; isLoad = false; isLaneOp = true; break; 3645263508Sdim case Intrinsic::arm_neon_vst3lane: NewOpc = AArch64ISD::NEON_ST3LN_UPD; 3646263508Sdim NumVecs = 3; isLoad = false; isLaneOp = true; break; 3647263508Sdim case Intrinsic::arm_neon_vst4lane: NewOpc = AArch64ISD::NEON_ST4LN_UPD; 3648263508Sdim NumVecs = 4; isLoad = false; isLaneOp = true; break; 3649263508Sdim } 3650263508Sdim } else { 3651263508Sdim isLaneOp = true; 3652263508Sdim switch (N->getOpcode()) { 3653263508Sdim default: llvm_unreachable("unexpected opcode for Neon base update"); 3654263508Sdim case AArch64ISD::NEON_LD2DUP: NewOpc = AArch64ISD::NEON_LD2DUP_UPD; 3655263508Sdim NumVecs = 2; break; 3656263508Sdim case AArch64ISD::NEON_LD3DUP: NewOpc = AArch64ISD::NEON_LD3DUP_UPD; 3657263508Sdim NumVecs = 3; break; 3658263508Sdim case AArch64ISD::NEON_LD4DUP: NewOpc = AArch64ISD::NEON_LD4DUP_UPD; 3659263508Sdim NumVecs = 4; break; 3660263508Sdim } 3661263508Sdim } 3662263508Sdim 3663263508Sdim // Find the size of memory referenced by the load/store. 3664263508Sdim EVT VecTy; 3665263508Sdim if (isLoad) 3666263508Sdim VecTy = N->getValueType(0); 3667263508Sdim else 3668263508Sdim VecTy = N->getOperand(AddrOpIdx + 1).getValueType(); 3669263508Sdim unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8; 3670263508Sdim if (isLaneOp) 3671263508Sdim NumBytes /= VecTy.getVectorNumElements(); 3672263508Sdim 3673263508Sdim // If the increment is a constant, it must match the memory ref size. 3674263508Sdim SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0); 3675263508Sdim if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) { 3676263508Sdim uint32_t IncVal = CInc->getZExtValue(); 3677263508Sdim if (IncVal != NumBytes) 3678263508Sdim continue; 3679263508Sdim Inc = DAG.getTargetConstant(IncVal, MVT::i32); 3680263508Sdim } 3681263508Sdim 3682263508Sdim // Create the new updating load/store node. 3683263508Sdim EVT Tys[6]; 3684263508Sdim unsigned NumResultVecs = (isLoad ? NumVecs : 0); 3685263508Sdim unsigned n; 3686263508Sdim for (n = 0; n < NumResultVecs; ++n) 3687263508Sdim Tys[n] = VecTy; 3688263508Sdim Tys[n++] = MVT::i64; 3689263508Sdim Tys[n] = MVT::Other; 3690263508Sdim SDVTList SDTys = DAG.getVTList(Tys, NumResultVecs + 2); 3691263508Sdim SmallVector<SDValue, 8> Ops; 3692263508Sdim Ops.push_back(N->getOperand(0)); // incoming chain 3693263508Sdim Ops.push_back(N->getOperand(AddrOpIdx)); 3694263508Sdim Ops.push_back(Inc); 3695263508Sdim for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands(); ++i) { 3696263508Sdim Ops.push_back(N->getOperand(i)); 3697263508Sdim } 3698263508Sdim MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N); 3699263508Sdim SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys, 3700263508Sdim Ops.data(), Ops.size(), 3701263508Sdim MemInt->getMemoryVT(), 3702263508Sdim MemInt->getMemOperand()); 3703263508Sdim 3704263508Sdim // Update the uses. 3705263508Sdim std::vector<SDValue> NewResults; 3706263508Sdim for (unsigned i = 0; i < NumResultVecs; ++i) { 3707263508Sdim NewResults.push_back(SDValue(UpdN.getNode(), i)); 3708263508Sdim } 3709263508Sdim NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs + 1)); // chain 3710263508Sdim DCI.CombineTo(N, NewResults); 3711263508Sdim DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs)); 3712263508Sdim 3713263508Sdim break; 3714263508Sdim } 3715263508Sdim return SDValue(); 3716263508Sdim} 3717263508Sdim 3718263508Sdim/// For a VDUPLANE node N, check if its source operand is a vldN-lane (N > 1) 3719263508Sdim/// intrinsic, and if all the other uses of that intrinsic are also VDUPLANEs. 3720263508Sdim/// If so, combine them to a vldN-dup operation and return true. 3721263508Sdimstatic SDValue CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) { 3722263508Sdim SelectionDAG &DAG = DCI.DAG; 3723263508Sdim EVT VT = N->getValueType(0); 3724263508Sdim 3725263508Sdim // Check if the VDUPLANE operand is a vldN-dup intrinsic. 3726263508Sdim SDNode *VLD = N->getOperand(0).getNode(); 3727263508Sdim if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN) 3728263508Sdim return SDValue(); 3729263508Sdim unsigned NumVecs = 0; 3730263508Sdim unsigned NewOpc = 0; 3731263508Sdim unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue(); 3732263508Sdim if (IntNo == Intrinsic::arm_neon_vld2lane) { 3733263508Sdim NumVecs = 2; 3734263508Sdim NewOpc = AArch64ISD::NEON_LD2DUP; 3735263508Sdim } else if (IntNo == Intrinsic::arm_neon_vld3lane) { 3736263508Sdim NumVecs = 3; 3737263508Sdim NewOpc = AArch64ISD::NEON_LD3DUP; 3738263508Sdim } else if (IntNo == Intrinsic::arm_neon_vld4lane) { 3739263508Sdim NumVecs = 4; 3740263508Sdim NewOpc = AArch64ISD::NEON_LD4DUP; 3741263508Sdim } else { 3742263508Sdim return SDValue(); 3743263508Sdim } 3744263508Sdim 3745263508Sdim // First check that all the vldN-lane uses are VDUPLANEs and that the lane 3746263508Sdim // numbers match the load. 3747263508Sdim unsigned VLDLaneNo = 3748263508Sdim cast<ConstantSDNode>(VLD->getOperand(NumVecs + 3))->getZExtValue(); 3749263508Sdim for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end(); 3750263508Sdim UI != UE; ++UI) { 3751263508Sdim // Ignore uses of the chain result. 3752263508Sdim if (UI.getUse().getResNo() == NumVecs) 3753263508Sdim continue; 3754263508Sdim SDNode *User = *UI; 3755263508Sdim if (User->getOpcode() != AArch64ISD::NEON_VDUPLANE || 3756263508Sdim VLDLaneNo != cast<ConstantSDNode>(User->getOperand(1))->getZExtValue()) 3757263508Sdim return SDValue(); 3758263508Sdim } 3759263508Sdim 3760263508Sdim // Create the vldN-dup node. 3761263508Sdim EVT Tys[5]; 3762263508Sdim unsigned n; 3763263508Sdim for (n = 0; n < NumVecs; ++n) 3764263508Sdim Tys[n] = VT; 3765263508Sdim Tys[n] = MVT::Other; 3766263508Sdim SDVTList SDTys = DAG.getVTList(Tys, NumVecs + 1); 3767263508Sdim SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) }; 3768263508Sdim MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD); 3769263508Sdim SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, SDLoc(VLD), SDTys, Ops, 2, 3770263508Sdim VLDMemInt->getMemoryVT(), 3771263508Sdim VLDMemInt->getMemOperand()); 3772263508Sdim 3773263508Sdim // Update the uses. 3774263508Sdim for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end(); 3775263508Sdim UI != UE; ++UI) { 3776263508Sdim unsigned ResNo = UI.getUse().getResNo(); 3777263508Sdim // Ignore uses of the chain result. 3778263508Sdim if (ResNo == NumVecs) 3779263508Sdim continue; 3780263508Sdim SDNode *User = *UI; 3781263508Sdim DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo)); 3782263508Sdim } 3783263508Sdim 3784263508Sdim // Now the vldN-lane intrinsic is dead except for its chain result. 3785263508Sdim // Update uses of the chain. 3786263508Sdim std::vector<SDValue> VLDDupResults; 3787263508Sdim for (unsigned n = 0; n < NumVecs; ++n) 3788263508Sdim VLDDupResults.push_back(SDValue(VLDDup.getNode(), n)); 3789263508Sdim VLDDupResults.push_back(SDValue(VLDDup.getNode(), NumVecs)); 3790263508Sdim DCI.CombineTo(VLD, VLDDupResults); 3791263508Sdim 3792263508Sdim return SDValue(N, 0); 3793263508Sdim} 3794263508Sdim 3795249259SdimSDValue 3796249259SdimAArch64TargetLowering::PerformDAGCombine(SDNode *N, 3797249259Sdim DAGCombinerInfo &DCI) const { 3798249259Sdim switch (N->getOpcode()) { 3799249259Sdim default: break; 3800249259Sdim case ISD::AND: return PerformANDCombine(N, DCI); 3801263508Sdim case ISD::OR: return PerformORCombine(N, DCI, getSubtarget()); 3802263508Sdim case ISD::SHL: 3803263508Sdim case ISD::SRA: 3804263508Sdim case ISD::SRL: 3805263508Sdim return PerformShiftCombine(N, DCI, getSubtarget()); 3806263508Sdim case ISD::INTRINSIC_WO_CHAIN: 3807263508Sdim return PerformIntrinsicCombine(N, DCI.DAG); 3808263508Sdim case AArch64ISD::NEON_VDUPLANE: 3809263508Sdim return CombineVLDDUP(N, DCI); 3810263508Sdim case AArch64ISD::NEON_LD2DUP: 3811263508Sdim case AArch64ISD::NEON_LD3DUP: 3812263508Sdim case AArch64ISD::NEON_LD4DUP: 3813263508Sdim return CombineBaseUpdate(N, DCI); 3814263508Sdim case ISD::INTRINSIC_VOID: 3815263508Sdim case ISD::INTRINSIC_W_CHAIN: 3816263508Sdim switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) { 3817263508Sdim case Intrinsic::arm_neon_vld1: 3818263508Sdim case Intrinsic::arm_neon_vld2: 3819263508Sdim case Intrinsic::arm_neon_vld3: 3820263508Sdim case Intrinsic::arm_neon_vld4: 3821263508Sdim case Intrinsic::arm_neon_vst1: 3822263508Sdim case Intrinsic::arm_neon_vst2: 3823263508Sdim case Intrinsic::arm_neon_vst3: 3824263508Sdim case Intrinsic::arm_neon_vst4: 3825263508Sdim case Intrinsic::arm_neon_vld2lane: 3826263508Sdim case Intrinsic::arm_neon_vld3lane: 3827263508Sdim case Intrinsic::arm_neon_vld4lane: 3828263508Sdim case Intrinsic::aarch64_neon_vld1x2: 3829263508Sdim case Intrinsic::aarch64_neon_vld1x3: 3830263508Sdim case Intrinsic::aarch64_neon_vld1x4: 3831263508Sdim case Intrinsic::aarch64_neon_vst1x2: 3832263508Sdim case Intrinsic::aarch64_neon_vst1x3: 3833263508Sdim case Intrinsic::aarch64_neon_vst1x4: 3834263508Sdim case Intrinsic::arm_neon_vst2lane: 3835263508Sdim case Intrinsic::arm_neon_vst3lane: 3836263508Sdim case Intrinsic::arm_neon_vst4lane: 3837263508Sdim return CombineBaseUpdate(N, DCI); 3838263508Sdim default: 3839263508Sdim break; 3840263508Sdim } 3841249259Sdim } 3842249259Sdim return SDValue(); 3843249259Sdim} 3844249259Sdim 3845263508Sdimbool 3846263508SdimAArch64TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const { 3847263508Sdim VT = VT.getScalarType(); 3848263508Sdim 3849263508Sdim if (!VT.isSimple()) 3850263508Sdim return false; 3851263508Sdim 3852263508Sdim switch (VT.getSimpleVT().SimpleTy) { 3853263508Sdim case MVT::f16: 3854263508Sdim case MVT::f32: 3855263508Sdim case MVT::f64: 3856263508Sdim return true; 3857263508Sdim case MVT::f128: 3858263508Sdim return false; 3859263508Sdim default: 3860263508Sdim break; 3861263508Sdim } 3862263508Sdim 3863263508Sdim return false; 3864263508Sdim} 3865263508Sdim 3866263508Sdim// Check whether a Build Vector could be presented as Shuffle Vector. If yes, 3867263508Sdim// try to call LowerVECTOR_SHUFFLE to lower it. 3868263508Sdimbool AArch64TargetLowering::isKnownShuffleVector(SDValue Op, SelectionDAG &DAG, 3869263508Sdim SDValue &Res) const { 3870263508Sdim SDLoc DL(Op); 3871263508Sdim EVT VT = Op.getValueType(); 3872263508Sdim unsigned NumElts = VT.getVectorNumElements(); 3873263508Sdim unsigned V0NumElts = 0; 3874263508Sdim int Mask[16]; 3875263508Sdim SDValue V0, V1; 3876263508Sdim 3877263508Sdim // Check if all elements are extracted from less than 3 vectors. 3878263508Sdim for (unsigned i = 0; i < NumElts; ++i) { 3879263508Sdim SDValue Elt = Op.getOperand(i); 3880263508Sdim if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT) 3881263508Sdim return false; 3882263508Sdim 3883263508Sdim if (V0.getNode() == 0) { 3884263508Sdim V0 = Elt.getOperand(0); 3885263508Sdim V0NumElts = V0.getValueType().getVectorNumElements(); 3886263508Sdim } 3887263508Sdim if (Elt.getOperand(0) == V0) { 3888263508Sdim Mask[i] = (cast<ConstantSDNode>(Elt->getOperand(1))->getZExtValue()); 3889263508Sdim continue; 3890263508Sdim } else if (V1.getNode() == 0) { 3891263508Sdim V1 = Elt.getOperand(0); 3892263508Sdim } 3893263508Sdim if (Elt.getOperand(0) == V1) { 3894263508Sdim unsigned Lane = cast<ConstantSDNode>(Elt->getOperand(1))->getZExtValue(); 3895263508Sdim Mask[i] = (Lane + V0NumElts); 3896263508Sdim continue; 3897263508Sdim } else { 3898263508Sdim return false; 3899263508Sdim } 3900263508Sdim } 3901263508Sdim 3902263508Sdim if (!V1.getNode() && V0NumElts == NumElts * 2) { 3903263508Sdim V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V0, 3904263508Sdim DAG.getConstant(NumElts, MVT::i64)); 3905263508Sdim V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V0, 3906263508Sdim DAG.getConstant(0, MVT::i64)); 3907263508Sdim V0NumElts = V0.getValueType().getVectorNumElements(); 3908263508Sdim } 3909263508Sdim 3910263508Sdim if (V1.getNode() && NumElts == V0NumElts && 3911263508Sdim V0NumElts == V1.getValueType().getVectorNumElements()) { 3912263508Sdim SDValue Shuffle = DAG.getVectorShuffle(VT, DL, V0, V1, Mask); 3913263508Sdim Res = LowerVECTOR_SHUFFLE(Shuffle, DAG); 3914263508Sdim return true; 3915263508Sdim } else 3916263508Sdim return false; 3917263508Sdim} 3918263508Sdim 3919263508Sdim// If this is a case we can't handle, return null and let the default 3920263508Sdim// expansion code take care of it. 3921263508SdimSDValue 3922263508SdimAArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, 3923263508Sdim const AArch64Subtarget *ST) const { 3924263508Sdim 3925263508Sdim BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode()); 3926263508Sdim SDLoc DL(Op); 3927263508Sdim EVT VT = Op.getValueType(); 3928263508Sdim 3929263508Sdim APInt SplatBits, SplatUndef; 3930263508Sdim unsigned SplatBitSize; 3931263508Sdim bool HasAnyUndefs; 3932263508Sdim 3933263508Sdim unsigned UseNeonMov = VT.getSizeInBits() >= 64; 3934263508Sdim 3935263508Sdim // Note we favor lowering MOVI over MVNI. 3936263508Sdim // This has implications on the definition of patterns in TableGen to select 3937263508Sdim // BIC immediate instructions but not ORR immediate instructions. 3938263508Sdim // If this lowering order is changed, TableGen patterns for BIC immediate and 3939263508Sdim // ORR immediate instructions have to be updated. 3940263508Sdim if (UseNeonMov && 3941263508Sdim BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) { 3942263508Sdim if (SplatBitSize <= 64) { 3943263508Sdim // First attempt to use vector immediate-form MOVI 3944263508Sdim EVT NeonMovVT; 3945263508Sdim unsigned Imm = 0; 3946263508Sdim unsigned OpCmode = 0; 3947263508Sdim 3948263508Sdim if (isNeonModifiedImm(SplatBits.getZExtValue(), SplatUndef.getZExtValue(), 3949263508Sdim SplatBitSize, DAG, VT.is128BitVector(), 3950263508Sdim Neon_Mov_Imm, NeonMovVT, Imm, OpCmode)) { 3951263508Sdim SDValue ImmVal = DAG.getTargetConstant(Imm, MVT::i32); 3952263508Sdim SDValue OpCmodeVal = DAG.getConstant(OpCmode, MVT::i32); 3953263508Sdim 3954263508Sdim if (ImmVal.getNode() && OpCmodeVal.getNode()) { 3955263508Sdim SDValue NeonMov = DAG.getNode(AArch64ISD::NEON_MOVIMM, DL, NeonMovVT, 3956263508Sdim ImmVal, OpCmodeVal); 3957263508Sdim return DAG.getNode(ISD::BITCAST, DL, VT, NeonMov); 3958263508Sdim } 3959263508Sdim } 3960263508Sdim 3961263508Sdim // Then attempt to use vector immediate-form MVNI 3962263508Sdim uint64_t NegatedImm = (~SplatBits).getZExtValue(); 3963263508Sdim if (isNeonModifiedImm(NegatedImm, SplatUndef.getZExtValue(), SplatBitSize, 3964263508Sdim DAG, VT.is128BitVector(), Neon_Mvn_Imm, NeonMovVT, 3965263508Sdim Imm, OpCmode)) { 3966263508Sdim SDValue ImmVal = DAG.getTargetConstant(Imm, MVT::i32); 3967263508Sdim SDValue OpCmodeVal = DAG.getConstant(OpCmode, MVT::i32); 3968263508Sdim if (ImmVal.getNode() && OpCmodeVal.getNode()) { 3969263508Sdim SDValue NeonMov = DAG.getNode(AArch64ISD::NEON_MVNIMM, DL, NeonMovVT, 3970263508Sdim ImmVal, OpCmodeVal); 3971263508Sdim return DAG.getNode(ISD::BITCAST, DL, VT, NeonMov); 3972263508Sdim } 3973263508Sdim } 3974263508Sdim 3975263508Sdim // Attempt to use vector immediate-form FMOV 3976263508Sdim if (((VT == MVT::v2f32 || VT == MVT::v4f32) && SplatBitSize == 32) || 3977263508Sdim (VT == MVT::v2f64 && SplatBitSize == 64)) { 3978263508Sdim APFloat RealVal( 3979263508Sdim SplatBitSize == 32 ? APFloat::IEEEsingle : APFloat::IEEEdouble, 3980263508Sdim SplatBits); 3981263508Sdim uint32_t ImmVal; 3982263508Sdim if (A64Imms::isFPImm(RealVal, ImmVal)) { 3983263508Sdim SDValue Val = DAG.getTargetConstant(ImmVal, MVT::i32); 3984263508Sdim return DAG.getNode(AArch64ISD::NEON_FMOVIMM, DL, VT, Val); 3985263508Sdim } 3986263508Sdim } 3987263508Sdim } 3988263508Sdim } 3989263508Sdim 3990263508Sdim unsigned NumElts = VT.getVectorNumElements(); 3991263508Sdim bool isOnlyLowElement = true; 3992263508Sdim bool usesOnlyOneValue = true; 3993263508Sdim bool hasDominantValue = false; 3994263508Sdim bool isConstant = true; 3995263508Sdim 3996263508Sdim // Map of the number of times a particular SDValue appears in the 3997263508Sdim // element list. 3998263508Sdim DenseMap<SDValue, unsigned> ValueCounts; 3999263508Sdim SDValue Value; 4000263508Sdim for (unsigned i = 0; i < NumElts; ++i) { 4001263508Sdim SDValue V = Op.getOperand(i); 4002263508Sdim if (V.getOpcode() == ISD::UNDEF) 4003263508Sdim continue; 4004263508Sdim if (i > 0) 4005263508Sdim isOnlyLowElement = false; 4006263508Sdim if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V)) 4007263508Sdim isConstant = false; 4008263508Sdim 4009263508Sdim ValueCounts.insert(std::make_pair(V, 0)); 4010263508Sdim unsigned &Count = ValueCounts[V]; 4011263508Sdim 4012263508Sdim // Is this value dominant? (takes up more than half of the lanes) 4013263508Sdim if (++Count > (NumElts / 2)) { 4014263508Sdim hasDominantValue = true; 4015263508Sdim Value = V; 4016263508Sdim } 4017263508Sdim } 4018263508Sdim if (ValueCounts.size() != 1) 4019263508Sdim usesOnlyOneValue = false; 4020263508Sdim if (!Value.getNode() && ValueCounts.size() > 0) 4021263508Sdim Value = ValueCounts.begin()->first; 4022263508Sdim 4023263508Sdim if (ValueCounts.size() == 0) 4024263508Sdim return DAG.getUNDEF(VT); 4025263508Sdim 4026263508Sdim // Loads are better lowered with insert_vector_elt. 4027263508Sdim // Keep going if we are hitting this case. 4028263508Sdim if (isOnlyLowElement && !ISD::isNormalLoad(Value.getNode())) 4029263508Sdim return DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Value); 4030263508Sdim 4031263508Sdim unsigned EltSize = VT.getVectorElementType().getSizeInBits(); 4032263508Sdim if (hasDominantValue && EltSize <= 64) { 4033263508Sdim // Use VDUP for non-constant splats. 4034263508Sdim if (!isConstant) { 4035263508Sdim SDValue N; 4036263508Sdim 4037263508Sdim // If we are DUPing a value that comes directly from a vector, we could 4038263508Sdim // just use DUPLANE. We can only do this if the lane being extracted 4039263508Sdim // is at a constant index, as the DUP from lane instructions only have 4040263508Sdim // constant-index forms. 4041263508Sdim if (Value->getOpcode() == ISD::EXTRACT_VECTOR_ELT && 4042263508Sdim isa<ConstantSDNode>(Value->getOperand(1))) { 4043263508Sdim N = DAG.getNode(AArch64ISD::NEON_VDUPLANE, DL, VT, 4044263508Sdim Value->getOperand(0), Value->getOperand(1)); 4045263508Sdim } else 4046263508Sdim N = DAG.getNode(AArch64ISD::NEON_VDUP, DL, VT, Value); 4047263508Sdim 4048263508Sdim if (!usesOnlyOneValue) { 4049263508Sdim // The dominant value was splatted as 'N', but we now have to insert 4050263508Sdim // all differing elements. 4051263508Sdim for (unsigned I = 0; I < NumElts; ++I) { 4052263508Sdim if (Op.getOperand(I) == Value) 4053263508Sdim continue; 4054263508Sdim SmallVector<SDValue, 3> Ops; 4055263508Sdim Ops.push_back(N); 4056263508Sdim Ops.push_back(Op.getOperand(I)); 4057263508Sdim Ops.push_back(DAG.getConstant(I, MVT::i64)); 4058263508Sdim N = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, &Ops[0], 3); 4059263508Sdim } 4060263508Sdim } 4061263508Sdim return N; 4062263508Sdim } 4063263508Sdim if (usesOnlyOneValue && isConstant) { 4064263508Sdim return DAG.getNode(AArch64ISD::NEON_VDUP, DL, VT, Value); 4065263508Sdim } 4066263508Sdim } 4067263508Sdim // If all elements are constants and the case above didn't get hit, fall back 4068263508Sdim // to the default expansion, which will generate a load from the constant 4069263508Sdim // pool. 4070263508Sdim if (isConstant) 4071263508Sdim return SDValue(); 4072263508Sdim 4073263508Sdim // Try to lower this in lowering ShuffleVector way. 4074263508Sdim SDValue Shuf; 4075263508Sdim if (isKnownShuffleVector(Op, DAG, Shuf)) 4076263508Sdim return Shuf; 4077263508Sdim 4078263508Sdim // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we 4079263508Sdim // know the default expansion would otherwise fall back on something even 4080263508Sdim // worse. For a vector with one or two non-undef values, that's 4081263508Sdim // scalar_to_vector for the elements followed by a shuffle (provided the 4082263508Sdim // shuffle is valid for the target) and materialization element by element 4083263508Sdim // on the stack followed by a load for everything else. 4084263508Sdim if (!isConstant && !usesOnlyOneValue) { 4085263508Sdim SDValue Vec = DAG.getUNDEF(VT); 4086263508Sdim for (unsigned i = 0 ; i < NumElts; ++i) { 4087263508Sdim SDValue V = Op.getOperand(i); 4088263508Sdim if (V.getOpcode() == ISD::UNDEF) 4089263508Sdim continue; 4090263508Sdim SDValue LaneIdx = DAG.getConstant(i, MVT::i64); 4091263508Sdim Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, Vec, V, LaneIdx); 4092263508Sdim } 4093263508Sdim return Vec; 4094263508Sdim } 4095263508Sdim return SDValue(); 4096263508Sdim} 4097263508Sdim 4098263508Sdim/// isREVMask - Check if a vector shuffle corresponds to a REV 4099263508Sdim/// instruction with the specified blocksize. (The order of the elements 4100263508Sdim/// within each block of the vector is reversed.) 4101263508Sdimstatic bool isREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) { 4102263508Sdim assert((BlockSize == 16 || BlockSize == 32 || BlockSize == 64) && 4103263508Sdim "Only possible block sizes for REV are: 16, 32, 64"); 4104263508Sdim 4105263508Sdim unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 4106263508Sdim if (EltSz == 64) 4107263508Sdim return false; 4108263508Sdim 4109263508Sdim unsigned NumElts = VT.getVectorNumElements(); 4110263508Sdim unsigned BlockElts = M[0] + 1; 4111263508Sdim // If the first shuffle index is UNDEF, be optimistic. 4112263508Sdim if (M[0] < 0) 4113263508Sdim BlockElts = BlockSize / EltSz; 4114263508Sdim 4115263508Sdim if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz) 4116263508Sdim return false; 4117263508Sdim 4118263508Sdim for (unsigned i = 0; i < NumElts; ++i) { 4119263508Sdim if (M[i] < 0) 4120263508Sdim continue; // ignore UNDEF indices 4121263508Sdim if ((unsigned)M[i] != (i - i % BlockElts) + (BlockElts - 1 - i % BlockElts)) 4122263508Sdim return false; 4123263508Sdim } 4124263508Sdim 4125263508Sdim return true; 4126263508Sdim} 4127263508Sdim 4128263508Sdim// isPermuteMask - Check whether the vector shuffle matches to UZP, ZIP and 4129263508Sdim// TRN instruction. 4130263508Sdimstatic unsigned isPermuteMask(ArrayRef<int> M, EVT VT) { 4131263508Sdim unsigned NumElts = VT.getVectorNumElements(); 4132263508Sdim if (NumElts < 4) 4133263508Sdim return 0; 4134263508Sdim 4135263508Sdim bool ismatch = true; 4136263508Sdim 4137263508Sdim // Check UZP1 4138263508Sdim for (unsigned i = 0; i < NumElts; ++i) { 4139263508Sdim if ((unsigned)M[i] != i * 2) { 4140263508Sdim ismatch = false; 4141263508Sdim break; 4142263508Sdim } 4143263508Sdim } 4144263508Sdim if (ismatch) 4145263508Sdim return AArch64ISD::NEON_UZP1; 4146263508Sdim 4147263508Sdim // Check UZP2 4148263508Sdim ismatch = true; 4149263508Sdim for (unsigned i = 0; i < NumElts; ++i) { 4150263508Sdim if ((unsigned)M[i] != i * 2 + 1) { 4151263508Sdim ismatch = false; 4152263508Sdim break; 4153263508Sdim } 4154263508Sdim } 4155263508Sdim if (ismatch) 4156263508Sdim return AArch64ISD::NEON_UZP2; 4157263508Sdim 4158263508Sdim // Check ZIP1 4159263508Sdim ismatch = true; 4160263508Sdim for (unsigned i = 0; i < NumElts; ++i) { 4161263508Sdim if ((unsigned)M[i] != i / 2 + NumElts * (i % 2)) { 4162263508Sdim ismatch = false; 4163263508Sdim break; 4164263508Sdim } 4165263508Sdim } 4166263508Sdim if (ismatch) 4167263508Sdim return AArch64ISD::NEON_ZIP1; 4168263508Sdim 4169263508Sdim // Check ZIP2 4170263508Sdim ismatch = true; 4171263508Sdim for (unsigned i = 0; i < NumElts; ++i) { 4172263508Sdim if ((unsigned)M[i] != (NumElts + i) / 2 + NumElts * (i % 2)) { 4173263508Sdim ismatch = false; 4174263508Sdim break; 4175263508Sdim } 4176263508Sdim } 4177263508Sdim if (ismatch) 4178263508Sdim return AArch64ISD::NEON_ZIP2; 4179263508Sdim 4180263508Sdim // Check TRN1 4181263508Sdim ismatch = true; 4182263508Sdim for (unsigned i = 0; i < NumElts; ++i) { 4183263508Sdim if ((unsigned)M[i] != i + (NumElts - 1) * (i % 2)) { 4184263508Sdim ismatch = false; 4185263508Sdim break; 4186263508Sdim } 4187263508Sdim } 4188263508Sdim if (ismatch) 4189263508Sdim return AArch64ISD::NEON_TRN1; 4190263508Sdim 4191263508Sdim // Check TRN2 4192263508Sdim ismatch = true; 4193263508Sdim for (unsigned i = 0; i < NumElts; ++i) { 4194263508Sdim if ((unsigned)M[i] != 1 + i + (NumElts - 1) * (i % 2)) { 4195263508Sdim ismatch = false; 4196263508Sdim break; 4197263508Sdim } 4198263508Sdim } 4199263508Sdim if (ismatch) 4200263508Sdim return AArch64ISD::NEON_TRN2; 4201263508Sdim 4202263508Sdim return 0; 4203263508Sdim} 4204263508Sdim 4205263508SdimSDValue 4206263508SdimAArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, 4207263508Sdim SelectionDAG &DAG) const { 4208263508Sdim SDValue V1 = Op.getOperand(0); 4209263508Sdim SDValue V2 = Op.getOperand(1); 4210263508Sdim SDLoc dl(Op); 4211263508Sdim EVT VT = Op.getValueType(); 4212263508Sdim ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode()); 4213263508Sdim 4214263508Sdim // Convert shuffles that are directly supported on NEON to target-specific 4215263508Sdim // DAG nodes, instead of keeping them as shuffles and matching them again 4216263508Sdim // during code selection. This is more efficient and avoids the possibility 4217263508Sdim // of inconsistencies between legalization and selection. 4218263508Sdim ArrayRef<int> ShuffleMask = SVN->getMask(); 4219263508Sdim 4220263508Sdim unsigned EltSize = VT.getVectorElementType().getSizeInBits(); 4221263508Sdim if (EltSize > 64) 4222263508Sdim return SDValue(); 4223263508Sdim 4224263508Sdim if (isREVMask(ShuffleMask, VT, 64)) 4225263508Sdim return DAG.getNode(AArch64ISD::NEON_REV64, dl, VT, V1); 4226263508Sdim if (isREVMask(ShuffleMask, VT, 32)) 4227263508Sdim return DAG.getNode(AArch64ISD::NEON_REV32, dl, VT, V1); 4228263508Sdim if (isREVMask(ShuffleMask, VT, 16)) 4229263508Sdim return DAG.getNode(AArch64ISD::NEON_REV16, dl, VT, V1); 4230263508Sdim 4231263508Sdim unsigned ISDNo = isPermuteMask(ShuffleMask, VT); 4232263508Sdim if (ISDNo) 4233263508Sdim return DAG.getNode(ISDNo, dl, VT, V1, V2); 4234263508Sdim 4235263508Sdim // If the element of shuffle mask are all the same constant, we can 4236263508Sdim // transform it into either NEON_VDUP or NEON_VDUPLANE 4237263508Sdim if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) { 4238263508Sdim int Lane = SVN->getSplatIndex(); 4239263508Sdim // If this is undef splat, generate it via "just" vdup, if possible. 4240263508Sdim if (Lane == -1) Lane = 0; 4241263508Sdim 4242263508Sdim // Test if V1 is a SCALAR_TO_VECTOR. 4243263508Sdim if (V1.getOpcode() == ISD::SCALAR_TO_VECTOR) { 4244263508Sdim return DAG.getNode(AArch64ISD::NEON_VDUP, dl, VT, V1.getOperand(0)); 4245263508Sdim } 4246263508Sdim // Test if V1 is a BUILD_VECTOR which is equivalent to a SCALAR_TO_VECTOR. 4247263508Sdim if (V1.getOpcode() == ISD::BUILD_VECTOR) { 4248263508Sdim bool IsScalarToVector = true; 4249263508Sdim for (unsigned i = 0, e = V1.getNumOperands(); i != e; ++i) 4250263508Sdim if (V1.getOperand(i).getOpcode() != ISD::UNDEF && 4251263508Sdim i != (unsigned)Lane) { 4252263508Sdim IsScalarToVector = false; 4253263508Sdim break; 4254263508Sdim } 4255263508Sdim if (IsScalarToVector) 4256263508Sdim return DAG.getNode(AArch64ISD::NEON_VDUP, dl, VT, 4257263508Sdim V1.getOperand(Lane)); 4258263508Sdim } 4259263508Sdim 4260263508Sdim // Test if V1 is a EXTRACT_SUBVECTOR. 4261263508Sdim if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) { 4262263508Sdim int ExtLane = cast<ConstantSDNode>(V1.getOperand(1))->getZExtValue(); 4263263508Sdim return DAG.getNode(AArch64ISD::NEON_VDUPLANE, dl, VT, V1.getOperand(0), 4264263508Sdim DAG.getConstant(Lane + ExtLane, MVT::i64)); 4265263508Sdim } 4266263508Sdim // Test if V1 is a CONCAT_VECTORS. 4267263508Sdim if (V1.getOpcode() == ISD::CONCAT_VECTORS && 4268263508Sdim V1.getOperand(1).getOpcode() == ISD::UNDEF) { 4269263508Sdim SDValue Op0 = V1.getOperand(0); 4270263508Sdim assert((unsigned)Lane < Op0.getValueType().getVectorNumElements() && 4271263508Sdim "Invalid vector lane access"); 4272263508Sdim return DAG.getNode(AArch64ISD::NEON_VDUPLANE, dl, VT, Op0, 4273263508Sdim DAG.getConstant(Lane, MVT::i64)); 4274263508Sdim } 4275263508Sdim 4276263508Sdim return DAG.getNode(AArch64ISD::NEON_VDUPLANE, dl, VT, V1, 4277263508Sdim DAG.getConstant(Lane, MVT::i64)); 4278263508Sdim } 4279263508Sdim 4280263508Sdim int Length = ShuffleMask.size(); 4281263508Sdim int V1EltNum = V1.getValueType().getVectorNumElements(); 4282263508Sdim 4283263508Sdim // If the number of v1 elements is the same as the number of shuffle mask 4284263508Sdim // element and the shuffle masks are sequential values, we can transform 4285263508Sdim // it into NEON_VEXTRACT. 4286263508Sdim if (V1EltNum == Length) { 4287263508Sdim // Check if the shuffle mask is sequential. 4288263508Sdim bool IsSequential = true; 4289263508Sdim int CurMask = ShuffleMask[0]; 4290263508Sdim for (int I = 0; I < Length; ++I) { 4291263508Sdim if (ShuffleMask[I] != CurMask) { 4292263508Sdim IsSequential = false; 4293263508Sdim break; 4294263508Sdim } 4295263508Sdim CurMask++; 4296263508Sdim } 4297263508Sdim if (IsSequential) { 4298263508Sdim assert((EltSize % 8 == 0) && "Bitsize of vector element is incorrect"); 4299263508Sdim unsigned VecSize = EltSize * V1EltNum; 4300263508Sdim unsigned Index = (EltSize/8) * ShuffleMask[0]; 4301263508Sdim if (VecSize == 64 || VecSize == 128) 4302263508Sdim return DAG.getNode(AArch64ISD::NEON_VEXTRACT, dl, VT, V1, V2, 4303263508Sdim DAG.getConstant(Index, MVT::i64)); 4304263508Sdim } 4305263508Sdim } 4306263508Sdim 4307263508Sdim // For shuffle mask like "0, 1, 2, 3, 4, 5, 13, 7", try to generate insert 4308263508Sdim // by element from V2 to V1 . 4309263508Sdim // If shuffle mask is like "0, 1, 10, 11, 12, 13, 14, 15", V2 would be a 4310263508Sdim // better choice to be inserted than V1 as less insert needed, so we count 4311263508Sdim // element to be inserted for both V1 and V2, and select less one as insert 4312263508Sdim // target. 4313263508Sdim 4314263508Sdim // Collect elements need to be inserted and their index. 4315263508Sdim SmallVector<int, 8> NV1Elt; 4316263508Sdim SmallVector<int, 8> N1Index; 4317263508Sdim SmallVector<int, 8> NV2Elt; 4318263508Sdim SmallVector<int, 8> N2Index; 4319263508Sdim for (int I = 0; I != Length; ++I) { 4320263508Sdim if (ShuffleMask[I] != I) { 4321263508Sdim NV1Elt.push_back(ShuffleMask[I]); 4322263508Sdim N1Index.push_back(I); 4323263508Sdim } 4324263508Sdim } 4325263508Sdim for (int I = 0; I != Length; ++I) { 4326263508Sdim if (ShuffleMask[I] != (I + V1EltNum)) { 4327263508Sdim NV2Elt.push_back(ShuffleMask[I]); 4328263508Sdim N2Index.push_back(I); 4329263508Sdim } 4330263508Sdim } 4331263508Sdim 4332263508Sdim // Decide which to be inserted. If all lanes mismatch, neither V1 nor V2 4333263508Sdim // will be inserted. 4334263508Sdim SDValue InsV = V1; 4335263508Sdim SmallVector<int, 8> InsMasks = NV1Elt; 4336263508Sdim SmallVector<int, 8> InsIndex = N1Index; 4337263508Sdim if ((int)NV1Elt.size() != Length || (int)NV2Elt.size() != Length) { 4338263508Sdim if (NV1Elt.size() > NV2Elt.size()) { 4339263508Sdim InsV = V2; 4340263508Sdim InsMasks = NV2Elt; 4341263508Sdim InsIndex = N2Index; 4342263508Sdim } 4343263508Sdim } else { 4344263508Sdim InsV = DAG.getNode(ISD::UNDEF, dl, VT); 4345263508Sdim } 4346263508Sdim 4347263508Sdim for (int I = 0, E = InsMasks.size(); I != E; ++I) { 4348263508Sdim SDValue ExtV = V1; 4349263508Sdim int Mask = InsMasks[I]; 4350263508Sdim if (Mask >= V1EltNum) { 4351263508Sdim ExtV = V2; 4352263508Sdim Mask -= V1EltNum; 4353263508Sdim } 4354263508Sdim // Any value type smaller than i32 is illegal in AArch64, and this lower 4355263508Sdim // function is called after legalize pass, so we need to legalize 4356263508Sdim // the result here. 4357263508Sdim EVT EltVT; 4358263508Sdim if (VT.getVectorElementType().isFloatingPoint()) 4359263508Sdim EltVT = (EltSize == 64) ? MVT::f64 : MVT::f32; 4360263508Sdim else 4361263508Sdim EltVT = (EltSize == 64) ? MVT::i64 : MVT::i32; 4362263508Sdim 4363263508Sdim if (Mask >= 0) { 4364263508Sdim ExtV = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, ExtV, 4365263508Sdim DAG.getConstant(Mask, MVT::i64)); 4366263508Sdim InsV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, InsV, ExtV, 4367263508Sdim DAG.getConstant(InsIndex[I], MVT::i64)); 4368263508Sdim } 4369263508Sdim } 4370263508Sdim return InsV; 4371263508Sdim} 4372263508Sdim 4373249259SdimAArch64TargetLowering::ConstraintType 4374249259SdimAArch64TargetLowering::getConstraintType(const std::string &Constraint) const { 4375249259Sdim if (Constraint.size() == 1) { 4376249259Sdim switch (Constraint[0]) { 4377249259Sdim default: break; 4378249259Sdim case 'w': // An FP/SIMD vector register 4379249259Sdim return C_RegisterClass; 4380249259Sdim case 'I': // Constant that can be used with an ADD instruction 4381249259Sdim case 'J': // Constant that can be used with a SUB instruction 4382249259Sdim case 'K': // Constant that can be used with a 32-bit logical instruction 4383249259Sdim case 'L': // Constant that can be used with a 64-bit logical instruction 4384249259Sdim case 'M': // Constant that can be used as a 32-bit MOV immediate 4385249259Sdim case 'N': // Constant that can be used as a 64-bit MOV immediate 4386249259Sdim case 'Y': // Floating point constant zero 4387249259Sdim case 'Z': // Integer constant zero 4388249259Sdim return C_Other; 4389249259Sdim case 'Q': // A memory reference with base register and no offset 4390249259Sdim return C_Memory; 4391249259Sdim case 'S': // A symbolic address 4392249259Sdim return C_Other; 4393249259Sdim } 4394249259Sdim } 4395249259Sdim 4396249259Sdim // FIXME: Ump, Utf, Usa, Ush 4397249259Sdim // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, 4398249259Sdim // whatever they may be 4399249259Sdim // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be 4400249259Sdim // Usa: An absolute symbolic address 4401249259Sdim // Ush: The high part (bits 32:12) of a pc-relative symbolic address 4402249259Sdim assert(Constraint != "Ump" && Constraint != "Utf" && Constraint != "Usa" 4403249259Sdim && Constraint != "Ush" && "Unimplemented constraints"); 4404249259Sdim 4405249259Sdim return TargetLowering::getConstraintType(Constraint); 4406249259Sdim} 4407249259Sdim 4408249259SdimTargetLowering::ConstraintWeight 4409249259SdimAArch64TargetLowering::getSingleConstraintMatchWeight(AsmOperandInfo &Info, 4410249259Sdim const char *Constraint) const { 4411249259Sdim 4412249259Sdim llvm_unreachable("Constraint weight unimplemented"); 4413249259Sdim} 4414249259Sdim 4415249259Sdimvoid 4416249259SdimAArch64TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 4417249259Sdim std::string &Constraint, 4418249259Sdim std::vector<SDValue> &Ops, 4419249259Sdim SelectionDAG &DAG) const { 4420249259Sdim SDValue Result(0, 0); 4421249259Sdim 4422249259Sdim // Only length 1 constraints are C_Other. 4423249259Sdim if (Constraint.size() != 1) return; 4424249259Sdim 4425249259Sdim // Only C_Other constraints get lowered like this. That means constants for us 4426249259Sdim // so return early if there's no hope the constraint can be lowered. 4427249259Sdim 4428249259Sdim switch(Constraint[0]) { 4429249259Sdim default: break; 4430249259Sdim case 'I': case 'J': case 'K': case 'L': 4431249259Sdim case 'M': case 'N': case 'Z': { 4432249259Sdim ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 4433249259Sdim if (!C) 4434249259Sdim return; 4435249259Sdim 4436249259Sdim uint64_t CVal = C->getZExtValue(); 4437249259Sdim uint32_t Bits; 4438249259Sdim 4439249259Sdim switch (Constraint[0]) { 4440249259Sdim default: 4441249259Sdim // FIXME: 'M' and 'N' are MOV pseudo-insts -- unsupported in assembly. 'J' 4442249259Sdim // is a peculiarly useless SUB constraint. 4443249259Sdim llvm_unreachable("Unimplemented C_Other constraint"); 4444249259Sdim case 'I': 4445249259Sdim if (CVal <= 0xfff) 4446249259Sdim break; 4447249259Sdim return; 4448249259Sdim case 'K': 4449249259Sdim if (A64Imms::isLogicalImm(32, CVal, Bits)) 4450249259Sdim break; 4451249259Sdim return; 4452249259Sdim case 'L': 4453249259Sdim if (A64Imms::isLogicalImm(64, CVal, Bits)) 4454249259Sdim break; 4455249259Sdim return; 4456249259Sdim case 'Z': 4457249259Sdim if (CVal == 0) 4458249259Sdim break; 4459249259Sdim return; 4460249259Sdim } 4461249259Sdim 4462249259Sdim Result = DAG.getTargetConstant(CVal, Op.getValueType()); 4463249259Sdim break; 4464249259Sdim } 4465249259Sdim case 'S': { 4466249259Sdim // An absolute symbolic address or label reference. 4467249259Sdim if (const GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op)) { 4468263508Sdim Result = DAG.getTargetGlobalAddress(GA->getGlobal(), SDLoc(Op), 4469249259Sdim GA->getValueType(0)); 4470249259Sdim } else if (const BlockAddressSDNode *BA 4471249259Sdim = dyn_cast<BlockAddressSDNode>(Op)) { 4472249259Sdim Result = DAG.getTargetBlockAddress(BA->getBlockAddress(), 4473249259Sdim BA->getValueType(0)); 4474249259Sdim } else if (const ExternalSymbolSDNode *ES 4475249259Sdim = dyn_cast<ExternalSymbolSDNode>(Op)) { 4476249259Sdim Result = DAG.getTargetExternalSymbol(ES->getSymbol(), 4477249259Sdim ES->getValueType(0)); 4478249259Sdim } else 4479249259Sdim return; 4480249259Sdim break; 4481249259Sdim } 4482249259Sdim case 'Y': 4483249259Sdim if (const ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) { 4484249259Sdim if (CFP->isExactlyValue(0.0)) { 4485249259Sdim Result = DAG.getTargetConstantFP(0.0, CFP->getValueType(0)); 4486249259Sdim break; 4487249259Sdim } 4488249259Sdim } 4489249259Sdim return; 4490249259Sdim } 4491249259Sdim 4492249259Sdim if (Result.getNode()) { 4493249259Sdim Ops.push_back(Result); 4494249259Sdim return; 4495249259Sdim } 4496249259Sdim 4497249259Sdim // It's an unknown constraint for us. Let generic code have a go. 4498249259Sdim TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 4499249259Sdim} 4500249259Sdim 4501249259Sdimstd::pair<unsigned, const TargetRegisterClass*> 4502249259SdimAArch64TargetLowering::getRegForInlineAsmConstraint( 4503249259Sdim const std::string &Constraint, 4504263508Sdim MVT VT) const { 4505249259Sdim if (Constraint.size() == 1) { 4506249259Sdim switch (Constraint[0]) { 4507249259Sdim case 'r': 4508249259Sdim if (VT.getSizeInBits() <= 32) 4509249259Sdim return std::make_pair(0U, &AArch64::GPR32RegClass); 4510249259Sdim else if (VT == MVT::i64) 4511249259Sdim return std::make_pair(0U, &AArch64::GPR64RegClass); 4512249259Sdim break; 4513249259Sdim case 'w': 4514249259Sdim if (VT == MVT::f16) 4515249259Sdim return std::make_pair(0U, &AArch64::FPR16RegClass); 4516249259Sdim else if (VT == MVT::f32) 4517249259Sdim return std::make_pair(0U, &AArch64::FPR32RegClass); 4518263508Sdim else if (VT.getSizeInBits() == 64) 4519249259Sdim return std::make_pair(0U, &AArch64::FPR64RegClass); 4520263508Sdim else if (VT.getSizeInBits() == 128) 4521249259Sdim return std::make_pair(0U, &AArch64::FPR128RegClass); 4522249259Sdim break; 4523249259Sdim } 4524249259Sdim } 4525249259Sdim 4526249259Sdim // Use the default implementation in TargetLowering to convert the register 4527249259Sdim // constraint into a member of a register class. 4528249259Sdim return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 4529249259Sdim} 4530263508Sdim 4531263508Sdim/// Represent NEON load and store intrinsics as MemIntrinsicNodes. 4532263508Sdim/// The associated MachineMemOperands record the alignment specified 4533263508Sdim/// in the intrinsic calls. 4534263508Sdimbool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, 4535263508Sdim const CallInst &I, 4536263508Sdim unsigned Intrinsic) const { 4537263508Sdim switch (Intrinsic) { 4538263508Sdim case Intrinsic::arm_neon_vld1: 4539263508Sdim case Intrinsic::arm_neon_vld2: 4540263508Sdim case Intrinsic::arm_neon_vld3: 4541263508Sdim case Intrinsic::arm_neon_vld4: 4542263508Sdim case Intrinsic::aarch64_neon_vld1x2: 4543263508Sdim case Intrinsic::aarch64_neon_vld1x3: 4544263508Sdim case Intrinsic::aarch64_neon_vld1x4: 4545263508Sdim case Intrinsic::arm_neon_vld2lane: 4546263508Sdim case Intrinsic::arm_neon_vld3lane: 4547263508Sdim case Intrinsic::arm_neon_vld4lane: { 4548263508Sdim Info.opc = ISD::INTRINSIC_W_CHAIN; 4549263508Sdim // Conservatively set memVT to the entire set of vectors loaded. 4550263508Sdim uint64_t NumElts = getDataLayout()->getTypeAllocSize(I.getType()) / 8; 4551263508Sdim Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts); 4552263508Sdim Info.ptrVal = I.getArgOperand(0); 4553263508Sdim Info.offset = 0; 4554263508Sdim Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1); 4555263508Sdim Info.align = cast<ConstantInt>(AlignArg)->getZExtValue(); 4556263508Sdim Info.vol = false; // volatile loads with NEON intrinsics not supported 4557263508Sdim Info.readMem = true; 4558263508Sdim Info.writeMem = false; 4559263508Sdim return true; 4560263508Sdim } 4561263508Sdim case Intrinsic::arm_neon_vst1: 4562263508Sdim case Intrinsic::arm_neon_vst2: 4563263508Sdim case Intrinsic::arm_neon_vst3: 4564263508Sdim case Intrinsic::arm_neon_vst4: 4565263508Sdim case Intrinsic::aarch64_neon_vst1x2: 4566263508Sdim case Intrinsic::aarch64_neon_vst1x3: 4567263508Sdim case Intrinsic::aarch64_neon_vst1x4: 4568263508Sdim case Intrinsic::arm_neon_vst2lane: 4569263508Sdim case Intrinsic::arm_neon_vst3lane: 4570263508Sdim case Intrinsic::arm_neon_vst4lane: { 4571263508Sdim Info.opc = ISD::INTRINSIC_VOID; 4572263508Sdim // Conservatively set memVT to the entire set of vectors stored. 4573263508Sdim unsigned NumElts = 0; 4574263508Sdim for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) { 4575263508Sdim Type *ArgTy = I.getArgOperand(ArgI)->getType(); 4576263508Sdim if (!ArgTy->isVectorTy()) 4577263508Sdim break; 4578263508Sdim NumElts += getDataLayout()->getTypeAllocSize(ArgTy) / 8; 4579263508Sdim } 4580263508Sdim Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts); 4581263508Sdim Info.ptrVal = I.getArgOperand(0); 4582263508Sdim Info.offset = 0; 4583263508Sdim Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1); 4584263508Sdim Info.align = cast<ConstantInt>(AlignArg)->getZExtValue(); 4585263508Sdim Info.vol = false; // volatile stores with NEON intrinsics not supported 4586263508Sdim Info.readMem = false; 4587263508Sdim Info.writeMem = true; 4588263508Sdim return true; 4589263508Sdim } 4590263508Sdim default: 4591263508Sdim break; 4592263508Sdim } 4593263508Sdim 4594263508Sdim return false; 4595263508Sdim} 4596