1;; Constraint definitions for ARM and Thumb 2;; Copyright (C) 2006 Free Software Foundation, Inc. 3;; Contributed by ARM Ltd. 4 5;; This file is part of GCC. 6 7;; GCC is free software; you can redistribute it and/or modify it 8;; under the terms of the GNU General Public License as published 9;; by the Free Software Foundation; either version 2, or (at your 10;; option) any later version. 11 12;; GCC is distributed in the hope that it will be useful, but WITHOUT 13;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15;; License for more details. 16 17;; You should have received a copy of the GNU General Public License 18;; along with GCC; see the file COPYING. If not, write to 19;; the Free Software Foundation, 51 Franklin Street, Fifth Floor, 20;; Boston, MA 02110-1301, USA. 21 22;; The following register constraints have been used: 23;; - in ARM state: f, v, w, y, z 24;; - in Thumb state: h, k, b 25;; - in both states: l, c 26;; In ARM state, 'l' is an alias for 'r' 27 28;; The following normal constraints have been used: 29;; in ARM state: G, H, I, J, K, L, M 30;; in Thumb state: I, J, K, L, M, N, O 31 32;; The following multi-letter normal constraints have been used: 33;; in ARM state: Da, Db, Dc 34 35;; The following memory constraints have been used: 36;; in ARM state: Q, Uq, Uv, Uy 37 38 39(define_register_constraint "f" "TARGET_ARM ? FPA_REGS : NO_REGS" 40 "Legacy FPA registers @code{f0}-@code{f7}.") 41 42(define_register_constraint "v" "TARGET_ARM ? CIRRUS_REGS : NO_REGS" 43 "The Cirrus Maverick co-processor registers.") 44 45(define_register_constraint "w" "TARGET_ARM ? VFP_REGS : NO_REGS" 46 "The VFP registers @code{s0}-@code{s31}.") 47 48(define_register_constraint "y" "TARGET_REALLY_IWMMXT ? IWMMXT_REGS : NO_REGS" 49 "The Intel iWMMX co-processor registers.") 50 51(define_register_constraint "z" 52 "TARGET_REALLY_IWMMXT ? IWMMXT_GR_REGS : NO_REGS" 53 "The Intel iWMMX GR registers.") 54 55(define_register_constraint "l" "TARGET_THUMB ? LO_REGS : GENERAL_REGS" 56 "In Thumb state the core registers @code{r0}-@code{r7}.") 57 58(define_register_constraint "h" "TARGET_THUMB ? HI_REGS : NO_REGS" 59 "In Thumb state the core registers @code{r8}-@code{r15}.") 60 61(define_register_constraint "k" "TARGET_THUMB ? STACK_REG : NO_REGS" 62 "@internal 63 Thumb only. The stack register.") 64 65(define_register_constraint "b" "TARGET_THUMB ? BASE_REGS : NO_REGS" 66 "@internal 67 Thumb only. The union of the low registers and the stack register.") 68 69(define_register_constraint "c" "CC_REG" 70 "@internal The condition code register.") 71 72(define_constraint "I" 73 "In ARM state a constant that can be used as an immediate value in a Data 74 Processing instruction. In Thumb state a constant in the range 0-255." 75 (and (match_code "const_int") 76 (match_test "TARGET_ARM ? const_ok_for_arm (ival) 77 : ival >= 0 && ival <= 255"))) 78 79(define_constraint "J" 80 "In ARM state a constant in the range @minus{}4095-4095. In Thumb state 81 a constant in the range @minus{}255-@minus{}1." 82 (and (match_code "const_int") 83 (match_test "TARGET_ARM ? (ival >= -4095 && ival <= 4095) 84 : (ival >= -255 && ival <= -1)"))) 85 86(define_constraint "K" 87 "In ARM state a constant that satisfies the @code{I} constraint if inverted. 88 In Thumb state a constant that satisfies the @code{I} constraint multiplied 89 by any power of 2." 90 (and (match_code "const_int") 91 (match_test "TARGET_ARM ? const_ok_for_arm (~ival) 92 : thumb_shiftable_const (ival)"))) 93 94(define_constraint "L" 95 "In ARM state a constant that satisfies the @code{I} constraint if negated. 96 In Thumb state a constant in the range @minus{}7-7." 97 (and (match_code "const_int") 98 (match_test "TARGET_ARM ? const_ok_for_arm (-ival) 99 : (ival >= -7 && ival <= 7)"))) 100 101;; The ARM state version is internal... 102;; @internal In ARM state a constant in the range 0-32 or any power of 2. 103(define_constraint "M" 104 "In Thumb state a constant that is a multiple of 4 in the range 0-1020." 105 (and (match_code "const_int") 106 (match_test "TARGET_ARM ? ((ival >= 0 && ival <= 32) 107 || ((ival & (ival - 1)) == 0)) 108 : ((ival >= 0 && ival <= 1020) && ((ival & 3) == 0))"))) 109 110(define_constraint "N" 111 "In Thumb state a constant in the range 0-31." 112 (and (match_code "const_int") 113 (match_test "TARGET_THUMB && ival >= 0 && ival <= 31"))) 114 115(define_constraint "O" 116 "In Thumb state a constant that is a multiple of 4 in the range 117 @minus{}508-508." 118 (and (match_code "const_int") 119 (match_test "TARGET_THUMB && ival >= -508 && ival <= 508 120 && ((ival & 3) == 0)"))) 121 122(define_constraint "G" 123 "In ARM state a valid FPA immediate constant." 124 (and (match_code "const_double") 125 (match_test "TARGET_ARM && arm_const_double_rtx (op)"))) 126 127(define_constraint "H" 128 "In ARM state a valid FPA immediate constant when negated." 129 (and (match_code "const_double") 130 (match_test "TARGET_ARM && neg_const_double_rtx_ok_for_fpa (op)"))) 131 132(define_constraint "Da" 133 "@internal 134 In ARM state a const_int, const_double or const_vector that can 135 be generated with two Data Processing insns." 136 (and (match_code "const_double,const_int,const_vector") 137 (match_test "TARGET_ARM && arm_const_double_inline_cost (op) == 2"))) 138 139(define_constraint "Db" 140 "@internal 141 In ARM state a const_int, const_double or const_vector that can 142 be generated with three Data Processing insns." 143 (and (match_code "const_double,const_int,const_vector") 144 (match_test "TARGET_ARM && arm_const_double_inline_cost (op) == 3"))) 145 146(define_constraint "Dc" 147 "@internal 148 In ARM state a const_int, const_double or const_vector that can 149 be generated with four Data Processing insns. This pattern is disabled 150 if optimizing for space or when we have load-delay slots to fill." 151 (and (match_code "const_double,const_int,const_vector") 152 (match_test "TARGET_ARM && arm_const_double_inline_cost (op) == 4 153 && !(optimize_size || arm_ld_sched)"))) 154 155(define_memory_constraint "Uv" 156 "@internal 157 In ARM state a valid VFP load/store address." 158 (and (match_code "mem") 159 (match_test "TARGET_ARM && arm_coproc_mem_operand (op, FALSE)"))) 160 161(define_memory_constraint "Uy" 162 "@internal 163 In ARM state a valid iWMMX load/store address." 164 (and (match_code "mem") 165 (match_test "TARGET_ARM && arm_coproc_mem_operand (op, TRUE)"))) 166 167(define_memory_constraint "Uq" 168 "@internal 169 In ARM state an address valid in ldrsb instructions." 170 (and (match_code "mem") 171 (match_test "TARGET_ARM 172 && arm_legitimate_address_p (GET_MODE (op), XEXP (op, 0), 173 SIGN_EXTEND, 0)"))) 174 175(define_memory_constraint "Q" 176 "@internal 177 In ARM state an address that is a single base register." 178 (and (match_code "mem") 179 (match_test "REG_P (XEXP (op, 0))"))) 180 181;; We used to have constraint letters for S and R in ARM state, but 182;; all uses of these now appear to have been removed. 183 184;; Additionally, we used to have a Q constraint in Thumb state, but 185;; this wasn't really a valid memory constraint. Again, all uses of 186;; this now seem to have been removed. 187