1/* 2 * Structure definitions for HVM state that is held by Xen and must 3 * be saved along with the domain's memory and device-model state. 4 * 5 * Copyright (c) 2007 XenSource Ltd. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to 9 * deal in the Software without restriction, including without limitation the 10 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 11 * sell copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 20 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 */ 25 26#ifndef __XEN_PUBLIC_HVM_SAVE_X86_H__ 27#define __XEN_PUBLIC_HVM_SAVE_X86_H__ 28 29/* 30 * Save/restore header: general info about the save file. 31 */ 32 33#define HVM_FILE_MAGIC 0x54381286 34#define HVM_FILE_VERSION 0x00000001 35 36struct hvm_save_header { 37 uint32_t magic; /* Must be HVM_FILE_MAGIC */ 38 uint32_t version; /* File format version */ 39 uint64_t changeset; /* Version of Xen that saved this file */ 40 uint32_t cpuid; /* CPUID[0x01][%eax] on the saving machine */ 41 uint32_t gtsc_khz; /* Guest's TSC frequency in kHz */ 42}; 43 44DECLARE_HVM_SAVE_TYPE(HEADER, 1, struct hvm_save_header); 45 46 47/* 48 * Processor 49 * 50 * Compat: Pre-3.4 didn't have msr_tsc_aux 51 */ 52 53struct hvm_hw_cpu { 54 uint8_t fpu_regs[512]; 55 56 uint64_t rax; 57 uint64_t rbx; 58 uint64_t rcx; 59 uint64_t rdx; 60 uint64_t rbp; 61 uint64_t rsi; 62 uint64_t rdi; 63 uint64_t rsp; 64 uint64_t r8; 65 uint64_t r9; 66 uint64_t r10; 67 uint64_t r11; 68 uint64_t r12; 69 uint64_t r13; 70 uint64_t r14; 71 uint64_t r15; 72 73 uint64_t rip; 74 uint64_t rflags; 75 76 uint64_t cr0; 77 uint64_t cr2; 78 uint64_t cr3; 79 uint64_t cr4; 80 81 uint64_t dr0; 82 uint64_t dr1; 83 uint64_t dr2; 84 uint64_t dr3; 85 uint64_t dr6; 86 uint64_t dr7; 87 88 uint32_t cs_sel; 89 uint32_t ds_sel; 90 uint32_t es_sel; 91 uint32_t fs_sel; 92 uint32_t gs_sel; 93 uint32_t ss_sel; 94 uint32_t tr_sel; 95 uint32_t ldtr_sel; 96 97 uint32_t cs_limit; 98 uint32_t ds_limit; 99 uint32_t es_limit; 100 uint32_t fs_limit; 101 uint32_t gs_limit; 102 uint32_t ss_limit; 103 uint32_t tr_limit; 104 uint32_t ldtr_limit; 105 uint32_t idtr_limit; 106 uint32_t gdtr_limit; 107 108 uint64_t cs_base; 109 uint64_t ds_base; 110 uint64_t es_base; 111 uint64_t fs_base; 112 uint64_t gs_base; 113 uint64_t ss_base; 114 uint64_t tr_base; 115 uint64_t ldtr_base; 116 uint64_t idtr_base; 117 uint64_t gdtr_base; 118 119 uint32_t cs_arbytes; 120 uint32_t ds_arbytes; 121 uint32_t es_arbytes; 122 uint32_t fs_arbytes; 123 uint32_t gs_arbytes; 124 uint32_t ss_arbytes; 125 uint32_t tr_arbytes; 126 uint32_t ldtr_arbytes; 127 128 uint64_t sysenter_cs; 129 uint64_t sysenter_esp; 130 uint64_t sysenter_eip; 131 132 /* msr for em64t */ 133 uint64_t shadow_gs; 134 135 /* msr content saved/restored. */ 136 uint64_t msr_flags; 137 uint64_t msr_lstar; 138 uint64_t msr_star; 139 uint64_t msr_cstar; 140 uint64_t msr_syscall_mask; 141 uint64_t msr_efer; 142 uint64_t msr_tsc_aux; 143 144 /* guest's idea of what rdtsc() would return */ 145 uint64_t tsc; 146 147 /* pending event, if any */ 148 union { 149 uint32_t pending_event; 150 struct { 151 uint8_t pending_vector:8; 152 uint8_t pending_type:3; 153 uint8_t pending_error_valid:1; 154 uint32_t pending_reserved:19; 155 uint8_t pending_valid:1; 156 }; 157 }; 158 /* error code for pending event */ 159 uint32_t error_code; 160}; 161 162struct hvm_hw_cpu_compat { 163 uint8_t fpu_regs[512]; 164 165 uint64_t rax; 166 uint64_t rbx; 167 uint64_t rcx; 168 uint64_t rdx; 169 uint64_t rbp; 170 uint64_t rsi; 171 uint64_t rdi; 172 uint64_t rsp; 173 uint64_t r8; 174 uint64_t r9; 175 uint64_t r10; 176 uint64_t r11; 177 uint64_t r12; 178 uint64_t r13; 179 uint64_t r14; 180 uint64_t r15; 181 182 uint64_t rip; 183 uint64_t rflags; 184 185 uint64_t cr0; 186 uint64_t cr2; 187 uint64_t cr3; 188 uint64_t cr4; 189 190 uint64_t dr0; 191 uint64_t dr1; 192 uint64_t dr2; 193 uint64_t dr3; 194 uint64_t dr6; 195 uint64_t dr7; 196 197 uint32_t cs_sel; 198 uint32_t ds_sel; 199 uint32_t es_sel; 200 uint32_t fs_sel; 201 uint32_t gs_sel; 202 uint32_t ss_sel; 203 uint32_t tr_sel; 204 uint32_t ldtr_sel; 205 206 uint32_t cs_limit; 207 uint32_t ds_limit; 208 uint32_t es_limit; 209 uint32_t fs_limit; 210 uint32_t gs_limit; 211 uint32_t ss_limit; 212 uint32_t tr_limit; 213 uint32_t ldtr_limit; 214 uint32_t idtr_limit; 215 uint32_t gdtr_limit; 216 217 uint64_t cs_base; 218 uint64_t ds_base; 219 uint64_t es_base; 220 uint64_t fs_base; 221 uint64_t gs_base; 222 uint64_t ss_base; 223 uint64_t tr_base; 224 uint64_t ldtr_base; 225 uint64_t idtr_base; 226 uint64_t gdtr_base; 227 228 uint32_t cs_arbytes; 229 uint32_t ds_arbytes; 230 uint32_t es_arbytes; 231 uint32_t fs_arbytes; 232 uint32_t gs_arbytes; 233 uint32_t ss_arbytes; 234 uint32_t tr_arbytes; 235 uint32_t ldtr_arbytes; 236 237 uint64_t sysenter_cs; 238 uint64_t sysenter_esp; 239 uint64_t sysenter_eip; 240 241 /* msr for em64t */ 242 uint64_t shadow_gs; 243 244 /* msr content saved/restored. */ 245 uint64_t msr_flags; 246 uint64_t msr_lstar; 247 uint64_t msr_star; 248 uint64_t msr_cstar; 249 uint64_t msr_syscall_mask; 250 uint64_t msr_efer; 251 /*uint64_t msr_tsc_aux; COMPAT */ 252 253 /* guest's idea of what rdtsc() would return */ 254 uint64_t tsc; 255 256 /* pending event, if any */ 257 union { 258 uint32_t pending_event; 259 struct { 260 uint8_t pending_vector:8; 261 uint8_t pending_type:3; 262 uint8_t pending_error_valid:1; 263 uint32_t pending_reserved:19; 264 uint8_t pending_valid:1; 265 }; 266 }; 267 /* error code for pending event */ 268 uint32_t error_code; 269}; 270 271static inline int _hvm_hw_fix_cpu(void *h) { 272 struct hvm_hw_cpu *new=h; 273 struct hvm_hw_cpu_compat *old=h; 274 275 /* If we copy from the end backwards, we should 276 * be able to do the modification in-place */ 277 new->error_code=old->error_code; 278 new->pending_event=old->pending_event; 279 new->tsc=old->tsc; 280 new->msr_tsc_aux=0; 281 282 return 0; 283} 284 285DECLARE_HVM_SAVE_TYPE_COMPAT(CPU, 2, struct hvm_hw_cpu, \ 286 struct hvm_hw_cpu_compat, _hvm_hw_fix_cpu); 287 288/* 289 * PIC 290 */ 291 292struct hvm_hw_vpic { 293 /* IR line bitmasks. */ 294 uint8_t irr; 295 uint8_t imr; 296 uint8_t isr; 297 298 /* Line IRx maps to IRQ irq_base+x */ 299 uint8_t irq_base; 300 301 /* 302 * Where are we in ICW2-4 initialisation (0 means no init in progress)? 303 * Bits 0-1 (=x): Next write at A=1 sets ICW(x+1). 304 * Bit 2: ICW1.IC4 (1 == ICW4 included in init sequence) 305 * Bit 3: ICW1.SNGL (0 == ICW3 included in init sequence) 306 */ 307 uint8_t init_state:4; 308 309 /* IR line with highest priority. */ 310 uint8_t priority_add:4; 311 312 /* Reads from A=0 obtain ISR or IRR? */ 313 uint8_t readsel_isr:1; 314 315 /* Reads perform a polling read? */ 316 uint8_t poll:1; 317 318 /* Automatically clear IRQs from the ISR during INTA? */ 319 uint8_t auto_eoi:1; 320 321 /* Automatically rotate IRQ priorities during AEOI? */ 322 uint8_t rotate_on_auto_eoi:1; 323 324 /* Exclude slave inputs when considering in-service IRQs? */ 325 uint8_t special_fully_nested_mode:1; 326 327 /* Special mask mode excludes masked IRs from AEOI and priority checks. */ 328 uint8_t special_mask_mode:1; 329 330 /* Is this a master PIC or slave PIC? (NB. This is not programmable.) */ 331 uint8_t is_master:1; 332 333 /* Edge/trigger selection. */ 334 uint8_t elcr; 335 336 /* Virtual INT output. */ 337 uint8_t int_output; 338}; 339 340DECLARE_HVM_SAVE_TYPE(PIC, 3, struct hvm_hw_vpic); 341 342 343/* 344 * IO-APIC 345 */ 346 347#define VIOAPIC_NUM_PINS 48 /* 16 ISA IRQs, 32 non-legacy PCI IRQS. */ 348 349struct hvm_hw_vioapic { 350 uint64_t base_address; 351 uint32_t ioregsel; 352 uint32_t id; 353 union vioapic_redir_entry 354 { 355 uint64_t bits; 356 struct { 357 uint8_t vector; 358 uint8_t delivery_mode:3; 359 uint8_t dest_mode:1; 360 uint8_t delivery_status:1; 361 uint8_t polarity:1; 362 uint8_t remote_irr:1; 363 uint8_t trig_mode:1; 364 uint8_t mask:1; 365 uint8_t reserve:7; 366 uint8_t reserved[4]; 367 uint8_t dest_id; 368 } fields; 369 } redirtbl[VIOAPIC_NUM_PINS]; 370}; 371 372DECLARE_HVM_SAVE_TYPE(IOAPIC, 4, struct hvm_hw_vioapic); 373 374 375/* 376 * LAPIC 377 */ 378 379struct hvm_hw_lapic { 380 uint64_t apic_base_msr; 381 uint32_t disabled; /* VLAPIC_xx_DISABLED */ 382 uint32_t timer_divisor; 383 uint64_t tdt_msr; 384}; 385 386DECLARE_HVM_SAVE_TYPE(LAPIC, 5, struct hvm_hw_lapic); 387 388struct hvm_hw_lapic_regs { 389 uint8_t data[1024]; 390}; 391 392DECLARE_HVM_SAVE_TYPE(LAPIC_REGS, 6, struct hvm_hw_lapic_regs); 393 394 395/* 396 * IRQs 397 */ 398 399struct hvm_hw_pci_irqs { 400 /* 401 * Virtual interrupt wires for a single PCI bus. 402 * Indexed by: device*4 + INTx#. 403 */ 404 union { 405 unsigned long i[16 / sizeof (unsigned long)]; /* DECLARE_BITMAP(i, 32*4); */ 406 uint64_t pad[2]; 407 }; 408}; 409 410DECLARE_HVM_SAVE_TYPE(PCI_IRQ, 7, struct hvm_hw_pci_irqs); 411 412struct hvm_hw_isa_irqs { 413 /* 414 * Virtual interrupt wires for ISA devices. 415 * Indexed by ISA IRQ (assumes no ISA-device IRQ sharing). 416 */ 417 union { 418 unsigned long i[1]; /* DECLARE_BITMAP(i, 16); */ 419 uint64_t pad[1]; 420 }; 421}; 422 423DECLARE_HVM_SAVE_TYPE(ISA_IRQ, 8, struct hvm_hw_isa_irqs); 424 425struct hvm_hw_pci_link { 426 /* 427 * PCI-ISA interrupt router. 428 * Each PCI <device:INTx#> is 'wire-ORed' into one of four links using 429 * the traditional 'barber's pole' mapping ((device + INTx#) & 3). 430 * The router provides a programmable mapping from each link to a GSI. 431 */ 432 uint8_t route[4]; 433 uint8_t pad0[4]; 434}; 435 436DECLARE_HVM_SAVE_TYPE(PCI_LINK, 9, struct hvm_hw_pci_link); 437 438/* 439 * PIT 440 */ 441 442struct hvm_hw_pit { 443 struct hvm_hw_pit_channel { 444 uint32_t count; /* can be 65536 */ 445 uint16_t latched_count; 446 uint8_t count_latched; 447 uint8_t status_latched; 448 uint8_t status; 449 uint8_t read_state; 450 uint8_t write_state; 451 uint8_t write_latch; 452 uint8_t rw_mode; 453 uint8_t mode; 454 uint8_t bcd; /* not supported */ 455 uint8_t gate; /* timer start */ 456 } channels[3]; /* 3 x 16 bytes */ 457 uint32_t speaker_data_on; 458 uint32_t pad0; 459}; 460 461DECLARE_HVM_SAVE_TYPE(PIT, 10, struct hvm_hw_pit); 462 463 464/* 465 * RTC 466 */ 467 468#define RTC_CMOS_SIZE 14 469struct hvm_hw_rtc { 470 /* CMOS bytes */ 471 uint8_t cmos_data[RTC_CMOS_SIZE]; 472 /* Index register for 2-part operations */ 473 uint8_t cmos_index; 474 uint8_t pad0; 475}; 476 477DECLARE_HVM_SAVE_TYPE(RTC, 11, struct hvm_hw_rtc); 478 479 480/* 481 * HPET 482 */ 483 484#define HPET_TIMER_NUM 3 /* 3 timers supported now */ 485struct hvm_hw_hpet { 486 /* Memory-mapped, software visible registers */ 487 uint64_t capability; /* capabilities */ 488 uint64_t res0; /* reserved */ 489 uint64_t config; /* configuration */ 490 uint64_t res1; /* reserved */ 491 uint64_t isr; /* interrupt status reg */ 492 uint64_t res2[25]; /* reserved */ 493 uint64_t mc64; /* main counter */ 494 uint64_t res3; /* reserved */ 495 struct { /* timers */ 496 uint64_t config; /* configuration/cap */ 497 uint64_t cmp; /* comparator */ 498 uint64_t fsb; /* FSB route, not supported now */ 499 uint64_t res4; /* reserved */ 500 } timers[HPET_TIMER_NUM]; 501 uint64_t res5[4*(24-HPET_TIMER_NUM)]; /* reserved, up to 0x3ff */ 502 503 /* Hidden register state */ 504 uint64_t period[HPET_TIMER_NUM]; /* Last value written to comparator */ 505}; 506 507DECLARE_HVM_SAVE_TYPE(HPET, 12, struct hvm_hw_hpet); 508 509 510/* 511 * PM timer 512 */ 513 514struct hvm_hw_pmtimer { 515 uint32_t tmr_val; /* PM_TMR_BLK.TMR_VAL: 32bit free-running counter */ 516 uint16_t pm1a_sts; /* PM1a_EVT_BLK.PM1a_STS: status register */ 517 uint16_t pm1a_en; /* PM1a_EVT_BLK.PM1a_EN: enable register */ 518}; 519 520DECLARE_HVM_SAVE_TYPE(PMTIMER, 13, struct hvm_hw_pmtimer); 521 522/* 523 * MTRR MSRs 524 */ 525 526struct hvm_hw_mtrr { 527#define MTRR_VCNT 8 528#define NUM_FIXED_MSR 11 529 uint64_t msr_pat_cr; 530 /* mtrr physbase & physmask msr pair*/ 531 uint64_t msr_mtrr_var[MTRR_VCNT*2]; 532 uint64_t msr_mtrr_fixed[NUM_FIXED_MSR]; 533 uint64_t msr_mtrr_cap; 534 uint64_t msr_mtrr_def_type; 535}; 536 537DECLARE_HVM_SAVE_TYPE(MTRR, 14, struct hvm_hw_mtrr); 538 539/* 540 * The save area of XSAVE/XRSTOR. 541 */ 542 543struct hvm_hw_cpu_xsave { 544 uint64_t xfeature_mask; 545 uint64_t xcr0; /* Updated by XSETBV */ 546 uint64_t xcr0_accum; /* Updated by XSETBV */ 547 struct { 548 struct { char x[512]; } fpu_sse; 549 550 struct { 551 uint64_t xstate_bv; /* Updated by XRSTOR */ 552 uint64_t reserved[7]; 553 } xsave_hdr; /* The 64-byte header */ 554 555 struct { char x[0]; } ymm; /* YMM */ 556 } save_area; 557}; 558 559#define CPU_XSAVE_CODE 16 560 561/* 562 * Viridian hypervisor context. 563 */ 564 565struct hvm_viridian_domain_context { 566 uint64_t hypercall_gpa; 567 uint64_t guest_os_id; 568}; 569 570DECLARE_HVM_SAVE_TYPE(VIRIDIAN_DOMAIN, 15, struct hvm_viridian_domain_context); 571 572struct hvm_viridian_vcpu_context { 573 uint64_t apic_assist; 574}; 575 576DECLARE_HVM_SAVE_TYPE(VIRIDIAN_VCPU, 17, struct hvm_viridian_vcpu_context); 577 578struct hvm_vmce_vcpu { 579 uint64_t caps; 580}; 581 582DECLARE_HVM_SAVE_TYPE(VMCE_VCPU, 18, struct hvm_vmce_vcpu); 583 584/* 585 * Largest type-code in use 586 */ 587#define HVM_SAVE_CODE_MAX 18 588 589#endif /* __XEN_PUBLIC_HVM_SAVE_X86_H__ */ 590